From 754a3b9622de205b93a864f73c08468f4e6031a4 Mon Sep 17 00:00:00 2001 From: NandniJamnadas Date: Fri, 14 Oct 2022 16:25:51 +0100 Subject: [PATCH] PULP: Added SIMD (Single Instruction Multiple Data) tests: individual instruction tests, register boundary tests, immediate boundary tests, march tests for rv32i, rv32i_xcorevsimd and rv32i_xcorev. * gas/testsuite/gas/riscv/cv-simd-march-fail.d: Likewise * gas/testsuite/gas/riscv/cv-simd-march-fail.l: Likewise * gas/testsuite/gas/riscv/cv-simd-march-fail.s: Likewise * gas/testsuite/gas/riscv/cv-simd-march-xcorev.d: Likewise * gas/testsuite/gas/riscv/cv-simd-march-xcorev.s: Likewise * gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d: Likewise * gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s: Likewise * gas/testsuite/gas/riscv/cv-add-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avg-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avg-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avg-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avg-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avg-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avg-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avg-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avg-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avg-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avg-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avgu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avgu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-min-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-min-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-min-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-min-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-min-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-min-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-min-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-min-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-min-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-min-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-min-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-min-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-min-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-min-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-min-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-min-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-min-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-min-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-min-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-min-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-min-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-min-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-min-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-min-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-min-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-min-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-min-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-min-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-min-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-min-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-minu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-minu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-minu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-minu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-minu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-minu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-minu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-minu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-minu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-minu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-max-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-max-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-max-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-max-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-max-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-max-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-max-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-max-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-max-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-max-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-max-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-max-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-max-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-max-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-max-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-max-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-max-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-max-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-max-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-max-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-max-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-max-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-max-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-max-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-max-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-max-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-max-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-max-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-max-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-max-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-maxu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-maxu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-srl-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-srl-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-srl-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-srl-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-srl-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-srl-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-srl-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-srl-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-srl-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-srl-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-srl-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-srl-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-srl-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-srl-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-srl-sc-h-fail.l: Likewise * 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gas/testsuite/gas/riscv/cv-sra-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sra-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sra-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sra-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sra-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sra-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sra-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sll-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sll-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sll-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sll-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sll-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sll-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sll-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sll-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sll-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sll-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sll-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-or-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-or-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-or-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-or-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-or-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-or-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-or-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-or-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-or-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-or-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-or-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-or-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-or-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-or-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-or-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-or-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-or-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-or-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-or-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-or-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-or-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-or-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-or-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-or-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-or-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-or-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-or-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-or-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-or-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-or-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-xor-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-xor-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-xor-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-xor-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-xor-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-xor-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-xor-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-xor-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-xor-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-xor-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-and-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-and-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-and-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-and-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-and-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-and-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-and-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-and-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-and-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-and-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-and-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-and-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-and-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-and-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-and-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-and-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-and-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-and-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-and-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-and-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-and-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-and-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-and-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-and-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-and-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-and-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-and-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-and-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-and-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-and-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-abs-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-abs-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-abs-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-abs-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-abs-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-abs-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-abs-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-abs-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-abs-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-abs-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotup-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotup-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotusp-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotusp-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotsp-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotsp-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotup-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotup-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-extract-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-extract-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-extract-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-extract-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-extract-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-extract-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-extract-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-extract-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-extract-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-extract-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-extractu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-extractu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-extractu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-extractu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-extractu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-extractu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-extractu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-extractu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-extractu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-extractu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-insert-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-insert-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-insert-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-insert-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-insert-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-insert-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-insert-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-insert-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-insert-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-insert-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shuffle-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shuffle-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-pack-pass.d: Likewise * gas/testsuite/gas/riscv/cv-pack-pass.s: Likewise * gas/testsuite/gas/riscv/cv-pack-fail.d: Likewise * gas/testsuite/gas/riscv/cv-pack-fail.s: Likewise * gas/testsuite/gas/riscv/cv-pack-fail.l: Likewise * gas/testsuite/gas/riscv/cv-pack-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-pack-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-pack-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-pack-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-pack-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-packhi-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-packhi-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-packhi-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-packhi-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-packhi-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-packlo-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-packlo-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-packlo-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-packlo-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-packlo-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpne-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpne-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpge-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpge-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmplt-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmplt-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmple-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmple-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l: Likewise * gas/testsuite/gas/riscv/cv-cplxconj-pass.d: Likewise * gas/testsuite/gas/riscv/cv-cplxconj-pass.s: Likewise * gas/testsuite/gas/riscv/cv-cplxconj-fail.d: Likewise * gas/testsuite/gas/riscv/cv-cplxconj-fail.s: Likewise * gas/testsuite/gas/riscv/cv-cplxconj-fail.l: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-pass.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-pass.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-fail.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-fail.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-fail.l: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.l: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.l: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.d: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.s: Likewise * gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-div2-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-div2-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-div2-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-div2-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-div2-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-div4-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-div4-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-div4-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-div4-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-div4-fail.l: Likewise * gas/testsuite/gas/riscv/cv-add-div8-pass.d: Likewise * gas/testsuite/gas/riscv/cv-add-div8-pass.s: Likewise * gas/testsuite/gas/riscv/cv-add-div8-fail.d: Likewise * gas/testsuite/gas/riscv/cv-add-div8-fail.s: Likewise * gas/testsuite/gas/riscv/cv-add-div8-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-div2-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-div2-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-div2-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-div2-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-div2-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-div4-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-div4-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-div4-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-div4-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-div4-fail.l: Likewise * gas/testsuite/gas/riscv/cv-sub-div8-pass.d: Likewise * gas/testsuite/gas/riscv/cv-sub-div8-pass.s: Likewise * gas/testsuite/gas/riscv/cv-sub-div8-fail.d: Likewise * gas/testsuite/gas/riscv/cv-sub-div8-fail.s: Likewise * gas/testsuite/gas/riscv/cv-sub-div8-fail.l: Likewise Signed-off-by: NandniJamnadas --- gas/testsuite/gas/riscv/cv-abs-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-abs-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-abs-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-abs-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-abs-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-abs-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-abs-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-abs-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-abs-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-abs-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-add-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-add-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-add-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-div2-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-div2-fail.l | 3 + gas/testsuite/gas/riscv/cv-add-div2-fail.s | 4 + gas/testsuite/gas/riscv/cv-add-div2-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-add-div2-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-div4-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-div4-fail.l | 3 + gas/testsuite/gas/riscv/cv-add-div4-fail.s | 4 + gas/testsuite/gas/riscv/cv-add-div4-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-add-div4-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-div8-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-div8-fail.l | 3 + gas/testsuite/gas/riscv/cv-add-div8-fail.s | 4 + gas/testsuite/gas/riscv/cv-add-div8-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-add-div8-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-add-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-add-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-add-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-add-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-add-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-add-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-add-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-add-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-add-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-add-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-add-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-add-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-add-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-add-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-add-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-add-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-add-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-add-sci-h-pass.s | 12 + .../gas/riscv/cv-add-sci-h-reg-fail.l | 5 + gas/testsuite/gas/riscv/cv-and-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-and-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-and-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-and-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-and-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-and-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-and-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-and-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-and-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-and-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-and-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-and-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-and-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-and-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-and-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-and-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-and-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-and-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-and-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-and-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-and-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-and-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-and-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-and-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-and-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-and-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-and-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-and-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-and-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-and-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-avg-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-avg-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-avg-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-avg-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avg-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-avg-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-avg-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-avg-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-avg-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avg-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-avgu-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-avgu-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-avgu-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-avgu-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avgu-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-avgu-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-avgu-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-avgu-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-avgu-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avgu-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpge-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpge-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpge-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpge-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpge-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpge-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpge-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpge-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpge-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpge-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s | 8 + .../gas/riscv/cv-cmpgeu-sci-b-fail.d | 3 + .../gas/riscv/cv-cmpgeu-sci-b-fail.l | 5 + .../gas/riscv/cv-cmpgeu-sci-b-fail.s | 7 + .../gas/riscv/cv-cmpgeu-sci-b-pass.d | 19 ++ .../gas/riscv/cv-cmpgeu-sci-b-pass.s | 12 + .../gas/riscv/cv-cmpgeu-sci-h-fail.d | 3 + .../gas/riscv/cv-cmpgeu-sci-h-fail.l | 5 + .../gas/riscv/cv-cmpgeu-sci-h-fail.s | 7 + .../gas/riscv/cv-cmpgeu-sci-h-pass.d | 19 ++ .../gas/riscv/cv-cmpgeu-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s | 8 + .../gas/riscv/cv-cmpgtu-sci-b-fail.d | 3 + .../gas/riscv/cv-cmpgtu-sci-b-fail.l | 5 + .../gas/riscv/cv-cmpgtu-sci-b-fail.s | 7 + .../gas/riscv/cv-cmpgtu-sci-b-pass.d | 19 ++ .../gas/riscv/cv-cmpgtu-sci-b-pass.s | 12 + .../gas/riscv/cv-cmpgtu-sci-h-fail.d | 3 + .../gas/riscv/cv-cmpgtu-sci-h-fail.l | 5 + .../gas/riscv/cv-cmpgtu-sci-h-fail.s | 7 + .../gas/riscv/cv-cmpgtu-sci-h-pass.d | 19 ++ .../gas/riscv/cv-cmpgtu-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmple-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmple-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmple-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmple-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmple-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmple-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmple-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmple-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmple-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmple-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s | 8 + .../gas/riscv/cv-cmpleu-sci-b-fail.d | 3 + .../gas/riscv/cv-cmpleu-sci-b-fail.l | 5 + .../gas/riscv/cv-cmpleu-sci-b-fail.s | 7 + .../gas/riscv/cv-cmpleu-sci-b-pass.d | 19 ++ .../gas/riscv/cv-cmpleu-sci-b-pass.s | 12 + .../gas/riscv/cv-cmpleu-sci-h-fail.d | 3 + .../gas/riscv/cv-cmpleu-sci-h-fail.l | 5 + .../gas/riscv/cv-cmpleu-sci-h-fail.s | 7 + .../gas/riscv/cv-cmpleu-sci-h-pass.d | 19 ++ .../gas/riscv/cv-cmpleu-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmplt-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmplt-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmplt-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmplt-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmplt-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmplt-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmplt-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmplt-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmplt-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmplt-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s | 8 + .../gas/riscv/cv-cmpltu-sci-b-fail.d | 3 + .../gas/riscv/cv-cmpltu-sci-b-fail.l | 5 + .../gas/riscv/cv-cmpltu-sci-b-fail.s | 7 + .../gas/riscv/cv-cmpltu-sci-b-pass.d | 19 ++ .../gas/riscv/cv-cmpltu-sci-b-pass.s | 12 + .../gas/riscv/cv-cmpltu-sci-h-fail.d | 3 + .../gas/riscv/cv-cmpltu-sci-h-fail.l | 5 + .../gas/riscv/cv-cmpltu-sci-h-fail.s | 7 + .../gas/riscv/cv-cmpltu-sci-h-pass.d | 19 ++ .../gas/riscv/cv-cmpltu-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpne-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpne-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpne-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpne-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpne-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpne-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpne-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpne-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpne-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpne-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-cplxconj-fail.d | 3 + gas/testsuite/gas/riscv/cv-cplxconj-fail.l | 3 + gas/testsuite/gas/riscv/cv-cplxconj-fail.s | 4 + gas/testsuite/gas/riscv/cv-cplxconj-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cplxconj-pass.s | 8 + .../gas/riscv/cv-cplxmul-i-div2-fail.d | 3 + .../gas/riscv/cv-cplxmul-i-div2-fail.l | 3 + .../gas/riscv/cv-cplxmul-i-div2-fail.s | 4 + .../gas/riscv/cv-cplxmul-i-div2-pass.d | 16 ++ .../gas/riscv/cv-cplxmul-i-div2-pass.s | 8 + .../gas/riscv/cv-cplxmul-i-div4-fail.d | 3 + .../gas/riscv/cv-cplxmul-i-div4-fail.l | 3 + .../gas/riscv/cv-cplxmul-i-div4-fail.s | 4 + .../gas/riscv/cv-cplxmul-i-div4-pass.d | 16 ++ .../gas/riscv/cv-cplxmul-i-div4-pass.s | 8 + .../gas/riscv/cv-cplxmul-i-div8-fail.d | 3 + .../gas/riscv/cv-cplxmul-i-div8-fail.l | 3 + .../gas/riscv/cv-cplxmul-i-div8-fail.s | 4 + .../gas/riscv/cv-cplxmul-i-div8-pass.d | 16 ++ .../gas/riscv/cv-cplxmul-i-div8-pass.s | 8 + gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d | 3 + gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l | 3 + gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s | 4 + gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s | 8 + .../gas/riscv/cv-cplxmul-r-div2-fail.d | 3 + .../gas/riscv/cv-cplxmul-r-div2-fail.l | 3 + .../gas/riscv/cv-cplxmul-r-div2-fail.s | 4 + .../gas/riscv/cv-cplxmul-r-div2-pass.d | 16 ++ .../gas/riscv/cv-cplxmul-r-div2-pass.s | 8 + .../gas/riscv/cv-cplxmul-r-div4-fail.d | 3 + .../gas/riscv/cv-cplxmul-r-div4-fail.l | 3 + .../gas/riscv/cv-cplxmul-r-div4-fail.s | 4 + .../gas/riscv/cv-cplxmul-r-div4-pass.d | 16 ++ .../gas/riscv/cv-cplxmul-r-div4-pass.s | 8 + .../gas/riscv/cv-cplxmul-r-div8-fail.d | 3 + .../gas/riscv/cv-cplxmul-r-div8-fail.l | 3 + .../gas/riscv/cv-cplxmul-r-div8-fail.s | 4 + .../gas/riscv/cv-cplxmul-r-div8-pass.d | 16 ++ .../gas/riscv/cv-cplxmul-r-div8-pass.s | 8 + gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d | 3 + gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l | 3 + gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s | 4 + gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotsp-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotsp-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotsp-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotsp-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotsp-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotsp-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotsp-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotsp-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotsp-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotsp-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-dotup-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotup-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotup-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotup-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotup-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotup-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotup-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotup-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotup-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotup-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l | 5 + gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s | 7 + gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s | 12 + gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l | 5 + gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s | 7 + gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d | 19 ++ gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-dotusp-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotusp-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotusp-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotusp-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotusp-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotusp-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotusp-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotusp-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotusp-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotusp-h-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s | 8 + gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d | 3 + gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l | 3 + gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s | 4 + gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d | 16 ++ gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s | 8 + .../gas/riscv/cv-dotusp-sci-b-fail.d | 3 + .../gas/riscv/cv-dotusp-sci-b-fail.l | 5 + .../gas/riscv/cv-dotusp-sci-b-fail.s | 7 + .../gas/riscv/cv-dotusp-sci-b-pass.d | 19 ++ .../gas/riscv/cv-dotusp-sci-b-pass.s | 12 + .../gas/riscv/cv-dotusp-sci-h-fail.d | 3 + .../gas/riscv/cv-dotusp-sci-h-fail.l | 5 + .../gas/riscv/cv-dotusp-sci-h-fail.s | 7 + .../gas/riscv/cv-dotusp-sci-h-pass.d | 19 ++ .../gas/riscv/cv-dotusp-sci-h-pass.s | 12 + gas/testsuite/gas/riscv/cv-extract-b-fail.d | 3 + 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gas/testsuite/gas/riscv/cv-and-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-and-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-and-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-and-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-and-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-and-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-and-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avg-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avg-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avgu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avgu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmple-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmple-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxconj-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxconj-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxconj-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxconj-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxconj-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotup-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotup-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-extract-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-extract-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-extract-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-extract-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-extract-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-extract-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-extract-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-extract-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-extract-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-extract-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-extractu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-extractu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-extractu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-extractu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-extractu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-extractu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-extractu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-extractu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-extractu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-extractu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-insert-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-insert-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-insert-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-insert-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-insert-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-insert-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-insert-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-insert-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-insert-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-insert-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-max-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-max-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-max-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-max-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-max-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-max-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-max-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-max-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-max-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-max-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-max-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-maxu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-maxu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-min-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-min-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-min-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-min-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-min-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-min-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-min-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-min-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-min-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-min-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-min-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-minu-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-minu-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-or-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-or-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-or-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-or-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-or-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-or-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-or-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-or-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-or-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-or-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-or-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-pack-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-pack-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-pack-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-pack-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-pack-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-pack-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-pack-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-pack-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-pack-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-pack-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-packhi-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-packhi-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-packhi-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-packhi-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-packhi-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-packlo-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-packlo-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-packlo-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-packlo-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-packlo-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s create mode 100644 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gas/testsuite/gas/riscv/cv-shuffle-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-simd-march-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-simd-march-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-simd-march-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-simd-march-xcorev.d create mode 100644 gas/testsuite/gas/riscv/cv-simd-march-xcorev.s create mode 100644 gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d create mode 100644 gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s create mode 100644 gas/testsuite/gas/riscv/cv-sll-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sll-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sll-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sll-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sll-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sll-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sll-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sll-h-fail.s create mode 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gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d create mode 100644 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gas/testsuite/gas/riscv/cv-srl-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-srl-sci-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sub-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sub-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sub-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sub-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sub-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sub-div2-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sub-div2-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sub-div2-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sub-div2-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-sub-div2-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-sub-div4-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-sub-div4-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-sub-div4-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-sub-div4-pass.d create mode 100644 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gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d create mode 100644 gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s diff --git a/gas/testsuite/gas/riscv/cv-abs-b-fail.d b/gas/testsuite/gas/riscv/cv-abs-b-fail.d new file mode 100644 index 00000000000..07b58a636a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-b-fail.s +#error_output: cv-abs-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-abs-b-fail.l b/gas/testsuite/gas/riscv/cv-abs-b-fail.l new file mode 100644 index 00000000000..93156ef3807 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.abs.b x32,x32' +.*: Error: illegal operands `cv.abs.b x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-abs-b-fail.s b/gas/testsuite/gas/riscv/cv-abs-b-fail.s new file mode 100644 index 00000000000..e2dfb8e054f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.abs.b x32, x32 + cv.abs.b x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-abs-b-pass.d b/gas/testsuite/gas/riscv/cv-abs-b-pass.d new file mode 100644 index 00000000000..656b1f5c011 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7000107b cv.abs.b zero,zero + 4: 700090fb cv.abs.b ra,ra + 8: 7001117b cv.abs.b sp,sp + c: 7004147b cv.abs.b s0,s0 + 10: 700a1a7b cv.abs.b s4,s4 + 14: 700f9ffb cv.abs.b t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-abs-b-pass.s b/gas/testsuite/gas/riscv/cv-abs-b-pass.s new file mode 100644 index 00000000000..6ea328015fe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.abs.b x0, x0 + cv.abs.b x1, x1 + cv.abs.b x2, x2 + cv.abs.b x8, x8 + cv.abs.b x20, x20 + cv.abs.b x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-abs-h-fail.d b/gas/testsuite/gas/riscv/cv-abs-h-fail.d new file mode 100644 index 00000000000..8e2da38188e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-h-fail.s +#error_output: cv-abs-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-abs-h-fail.l b/gas/testsuite/gas/riscv/cv-abs-h-fail.l new file mode 100644 index 00000000000..74867e1b611 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.abs.h x32,x32' +.*: Error: illegal operands `cv.abs.h x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-abs-h-fail.s b/gas/testsuite/gas/riscv/cv-abs-h-fail.s new file mode 100644 index 00000000000..930e79ae5bc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.abs.h x32, x32 + cv.abs.h x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-abs-h-pass.d b/gas/testsuite/gas/riscv/cv-abs-h-pass.d new file mode 100644 index 00000000000..c86318c4bfd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7000007b cv.abs.h zero,zero + 4: 700080fb cv.abs.h ra,ra + 8: 7001017b cv.abs.h sp,sp + c: 7004047b cv.abs.h s0,s0 + 10: 700a0a7b cv.abs.h s4,s4 + 14: 700f8ffb cv.abs.h t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-abs-h-pass.s b/gas/testsuite/gas/riscv/cv-abs-h-pass.s new file mode 100644 index 00000000000..050f403799c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.abs.h x0, x0 + cv.abs.h x1, x1 + cv.abs.h x2, x2 + cv.abs.h x8, x8 + cv.abs.h x20, x20 + cv.abs.h x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-b-fail.d b/gas/testsuite/gas/riscv/cv-add-b-fail.d new file mode 100644 index 00000000000..c9f3cb58070 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-b-fail.s +#error_output: cv-add-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-b-fail.l b/gas/testsuite/gas/riscv/cv-add-b-fail.l new file mode 100644 index 00000000000..e43a2c5536b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.b x32,x32,x32' +.*: Error: illegal operands `cv.add.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-b-fail.s b/gas/testsuite/gas/riscv/cv-add-b-fail.s new file mode 100644 index 00000000000..193a295e858 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.b x32, x32, x32 + cv.add.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-b-pass.d b/gas/testsuite/gas/riscv/cv-add-b-pass.d new file mode 100644 index 00000000000..dc3dfca91da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000107b cv.add.b zero,zero,zero + 4: 001090fb cv.add.b ra,ra,ra + 8: 0021117b cv.add.b sp,sp,sp + c: 0084147b cv.add.b s0,s0,s0 + 10: 014a1a7b cv.add.b s4,s4,s4 + 14: 01ff9ffb cv.add.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-b-pass.s b/gas/testsuite/gas/riscv/cv-add-b-pass.s new file mode 100644 index 00000000000..2cdf11e26d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.b x0, x0, x0 + cv.add.b x1, x1, x1 + cv.add.b x2, x2, x2 + cv.add.b x8, x8, x8 + cv.add.b x20, x20, x20 + cv.add.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-div2-fail.d b/gas/testsuite/gas/riscv/cv-add-div2-fail.d new file mode 100644 index 00000000000..80764a83175 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div2-fail.s +#error_output: cv-add-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-div2-fail.l b/gas/testsuite/gas/riscv/cv-add-div2-fail.l new file mode 100644 index 00000000000..aaf581ef21d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.div2 x32,x32,x32' +.*: Error: illegal operands `cv.add.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-div2-fail.s b/gas/testsuite/gas/riscv/cv-add-div2-fail.s new file mode 100644 index 00000000000..dbf1be61ca3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.div2 x32, x32, x32 + cv.add.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-div2-pass.d b/gas/testsuite/gas/riscv/cv-add-div2-pass.d new file mode 100644 index 00000000000..42e242dedab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6c00207b cv.add.div2 zero,zero,zero + 4: 6c10a0fb cv.add.div2 ra,ra,ra + 8: 6c21217b cv.add.div2 sp,sp,sp + c: 6c84247b cv.add.div2 s0,s0,s0 + 10: 6d4a2a7b cv.add.div2 s4,s4,s4 + 14: 6dffaffb cv.add.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-div2-pass.s b/gas/testsuite/gas/riscv/cv-add-div2-pass.s new file mode 100644 index 00000000000..396bda9ee77 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.div2 x0, x0, x0 + cv.add.div2 x1, x1, x1 + cv.add.div2 x2, x2, x2 + cv.add.div2 x8, x8, x8 + cv.add.div2 x20, x20, x20 + cv.add.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-div4-fail.d b/gas/testsuite/gas/riscv/cv-add-div4-fail.d new file mode 100644 index 00000000000..0a355fd470c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div4-fail.s +#error_output: cv-add-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-div4-fail.l b/gas/testsuite/gas/riscv/cv-add-div4-fail.l new file mode 100644 index 00000000000..4f91c5031c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.div4 x32,x32,x32' +.*: Error: illegal operands `cv.add.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-div4-fail.s b/gas/testsuite/gas/riscv/cv-add-div4-fail.s new file mode 100644 index 00000000000..7dd658bdcda --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.div4 x32, x32, x32 + cv.add.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-div4-pass.d b/gas/testsuite/gas/riscv/cv-add-div4-pass.d new file mode 100644 index 00000000000..bde5d4dbe96 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6c00407b cv.add.div4 zero,zero,zero + 4: 6c10c0fb cv.add.div4 ra,ra,ra + 8: 6c21417b cv.add.div4 sp,sp,sp + c: 6c84447b cv.add.div4 s0,s0,s0 + 10: 6d4a4a7b cv.add.div4 s4,s4,s4 + 14: 6dffcffb cv.add.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-div4-pass.s b/gas/testsuite/gas/riscv/cv-add-div4-pass.s new file mode 100644 index 00000000000..e4587ce815c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.div4 x0, x0, x0 + cv.add.div4 x1, x1, x1 + cv.add.div4 x2, x2, x2 + cv.add.div4 x8, x8, x8 + cv.add.div4 x20, x20, x20 + cv.add.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-div8-fail.d b/gas/testsuite/gas/riscv/cv-add-div8-fail.d new file mode 100644 index 00000000000..34702f30b50 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div8-fail.s +#error_output: cv-add-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-div8-fail.l b/gas/testsuite/gas/riscv/cv-add-div8-fail.l new file mode 100644 index 00000000000..b5628ada078 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.div8 x32,x32,x32' +.*: Error: illegal operands `cv.add.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-div8-fail.s b/gas/testsuite/gas/riscv/cv-add-div8-fail.s new file mode 100644 index 00000000000..bedbed050a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.div8 x32, x32, x32 + cv.add.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-div8-pass.d b/gas/testsuite/gas/riscv/cv-add-div8-pass.d new file mode 100644 index 00000000000..7ca74033726 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6c00607b cv.add.div8 zero,zero,zero + 4: 6c10e0fb cv.add.div8 ra,ra,ra + 8: 6c21617b cv.add.div8 sp,sp,sp + c: 6c84647b cv.add.div8 s0,s0,s0 + 10: 6d4a6a7b cv.add.div8 s4,s4,s4 + 14: 6dffeffb cv.add.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-div8-pass.s b/gas/testsuite/gas/riscv/cv-add-div8-pass.s new file mode 100644 index 00000000000..2472f00f34b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.div8 x0, x0, x0 + cv.add.div8 x1, x1, x1 + cv.add.div8 x2, x2, x2 + cv.add.div8 x8, x8, x8 + cv.add.div8 x20, x20, x20 + cv.add.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-h-fail.d b/gas/testsuite/gas/riscv/cv-add-h-fail.d new file mode 100644 index 00000000000..f63d128606e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-h-fail.s +#error_output: cv-add-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-h-fail.l b/gas/testsuite/gas/riscv/cv-add-h-fail.l new file mode 100644 index 00000000000..a82b28674ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.h x32,x32,x32' +.*: Error: illegal operands `cv.add.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-h-fail.s b/gas/testsuite/gas/riscv/cv-add-h-fail.s new file mode 100644 index 00000000000..148bf21959f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.h x32, x32, x32 + cv.add.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-h-pass.d b/gas/testsuite/gas/riscv/cv-add-h-pass.d new file mode 100644 index 00000000000..3b40dac0baf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000007b cv.add.h zero,zero,zero + 4: 001080fb cv.add.h ra,ra,ra + 8: 0021017b cv.add.h sp,sp,sp + c: 0084047b cv.add.h s0,s0,s0 + 10: 014a0a7b cv.add.h s4,s4,s4 + 14: 01ff8ffb cv.add.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-h-pass.s b/gas/testsuite/gas/riscv/cv-add-h-pass.s new file mode 100644 index 00000000000..2a4bd6942a7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.h x0, x0, x0 + cv.add.h x1, x1, x1 + cv.add.h x2, x2, x2 + cv.add.h x8, x8, x8 + cv.add.h x20, x20, x20 + cv.add.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.d new file mode 100644 index 00000000000..780f0835633 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-b-fail.s +#error_output: cv-add-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.l new file mode 100644 index 00000000000..20b1f4fa1dd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.add.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.s new file mode 100644 index 00000000000..2a89aca5751 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.sc.b x32, x32, x32 + cv.add.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.d new file mode 100644 index 00000000000..10694b5fa0c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000507b cv.add.sc.b zero,zero,zero + 4: 0010d0fb cv.add.sc.b ra,ra,ra + 8: 0021517b cv.add.sc.b sp,sp,sp + c: 0084547b cv.add.sc.b s0,s0,s0 + 10: 014a5a7b cv.add.sc.b s4,s4,s4 + 14: 01ffdffb cv.add.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.s new file mode 100644 index 00000000000..4a3401d7a5f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.sc.b x0, x0, x0 + cv.add.sc.b x1, x1, x1 + cv.add.sc.b x2, x2, x2 + cv.add.sc.b x8, x8, x8 + cv.add.sc.b x20, x20, x20 + cv.add.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.d new file mode 100644 index 00000000000..20219670a06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-h-fail.s +#error_output: cv-add-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.l new file mode 100644 index 00000000000..eaba711f44a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.add.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.s new file mode 100644 index 00000000000..9fc87c807d6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.sc.h x32, x32, x32 + cv.add.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.d new file mode 100644 index 00000000000..f7ae0be50ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000407b cv.add.sc.h zero,zero,zero + 4: 0010c0fb cv.add.sc.h ra,ra,ra + 8: 0021417b cv.add.sc.h sp,sp,sp + c: 0084447b cv.add.sc.h s0,s0,s0 + 10: 014a4a7b cv.add.sc.h s4,s4,s4 + 14: 01ffcffb cv.add.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.s new file mode 100644 index 00000000000..7aeee046c47 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.sc.h x0, x0, x0 + cv.add.sc.h x1, x1, x1 + cv.add.sc.h x2, x2, x2 + cv.add.sc.h x8, x8, x8 + cv.add.sc.h x20, x20, x20 + cv.add.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.d new file mode 100644 index 00000000000..68c1ace4f6d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-b-fail.s +#error_output: cv-add-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.l new file mode 100644 index 00000000000..c3f90cce759 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sci.b x32,x32,20' +.*: Error: illegal operands `cv.add.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.s new file mode 100644 index 00000000000..4aa7c516c00 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.add.sci.b x32, x32, 20 + cv.add.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.add.sci.b x6, x7, -33 + cv.add.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.d new file mode 100644 index 00000000000..d272fdcd0e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0140707b cv.add.sci.b zero,zero,20 + 4: 0140f0fb cv.add.sci.b ra,ra,20 + 8: 0141717b cv.add.sci.b sp,sp,20 + c: 0144747b cv.add.sci.b s0,s0,20 + 10: 014a7a7b cv.add.sci.b s4,s4,20 + 14: 014ffffb cv.add.sci.b t6,t6,20 + 18: 0203f37b cv.add.sci.b t1,t2,-32 + 1c: 0003f37b cv.add.sci.b t1,t2,0 + 20: 01f3f37b cv.add.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.s new file mode 100644 index 00000000000..1261bd2801e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.add.sci.b x0, x0, 20 + cv.add.sci.b x1, x1, 20 + cv.add.sci.b x2, x2, 20 + cv.add.sci.b x8, x8, 20 + cv.add.sci.b x20, x20, 20 + cv.add.sci.b x31, x31, 20 + #Immediate Values Test + cv.add.sci.b x6, x7, -32 + cv.add.sci.b x6, x7, 0 + cv.add.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.d new file mode 100644 index 00000000000..890c232e525 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-h-fail.s +#error_output: cv-add-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.l new file mode 100644 index 00000000000..2f0656f83a3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sci.h x32,x32,20' +.*: Error: illegal operands `cv.add.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.s new file mode 100644 index 00000000000..7a1cf469a23 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.add.sci.h x32, x32, 20 + cv.add.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.add.sci.h x6, x7, -33 + cv.add.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.d new file mode 100644 index 00000000000..074068fdf86 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0140607b cv.add.sci.h zero,zero,20 + 4: 0140e0fb cv.add.sci.h ra,ra,20 + 8: 0141617b cv.add.sci.h sp,sp,20 + c: 0144647b cv.add.sci.h s0,s0,20 + 10: 014a6a7b cv.add.sci.h s4,s4,20 + 14: 014feffb cv.add.sci.h t6,t6,20 + 18: 0203e37b cv.add.sci.h t1,t2,-32 + 1c: 0003e37b cv.add.sci.h t1,t2,0 + 20: 01f3e37b cv.add.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.s new file mode 100644 index 00000000000..027ca49550e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.add.sci.h x0, x0, 20 + cv.add.sci.h x1, x1, 20 + cv.add.sci.h x2, x2, 20 + cv.add.sci.h x8, x8, 20 + cv.add.sci.h x20, x20, 20 + cv.add.sci.h x31, x31, 20 + #Immediate Values Test + cv.add.sci.h x6, x7, -32 + cv.add.sci.h x6, x7, 0 + cv.add.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-reg-fail.l b/gas/testsuite/gas/riscv/cv-add-sci-h-reg-fail.l new file mode 100644 index 00000000000..24742faa445 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-reg-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sci.h x32, x32, 20' +.*: Error: illegal operands `cv.add.sci.h x33, x33, 20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-and-b-fail.d b/gas/testsuite/gas/riscv/cv-and-b-fail.d new file mode 100644 index 00000000000..b22747dcc72 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-b-fail.s +#error_output: cv-and-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-b-fail.l b/gas/testsuite/gas/riscv/cv-and-b-fail.l new file mode 100644 index 00000000000..18102aad53f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.b x32,x32,x32' +.*: Error: illegal operands `cv.and.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-b-fail.s b/gas/testsuite/gas/riscv/cv-and-b-fail.s new file mode 100644 index 00000000000..192fd54d16f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.b x32, x32, x32 + cv.and.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-b-pass.d b/gas/testsuite/gas/riscv/cv-and-b-pass.d new file mode 100644 index 00000000000..7ec010b2de9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800107b cv.and.b zero,zero,zero + 4: 681090fb cv.and.b ra,ra,ra + 8: 6821117b cv.and.b sp,sp,sp + c: 6884147b cv.and.b s0,s0,s0 + 10: 694a1a7b cv.and.b s4,s4,s4 + 14: 69ff9ffb cv.and.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-b-pass.s b/gas/testsuite/gas/riscv/cv-and-b-pass.s new file mode 100644 index 00000000000..7a84aa93975 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.b x0, x0, x0 + cv.and.b x1, x1, x1 + cv.and.b x2, x2, x2 + cv.and.b x8, x8, x8 + cv.and.b x20, x20, x20 + cv.and.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-h-fail.d b/gas/testsuite/gas/riscv/cv-and-h-fail.d new file mode 100644 index 00000000000..a704b663c7d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-h-fail.s +#error_output: cv-and-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-h-fail.l b/gas/testsuite/gas/riscv/cv-and-h-fail.l new file mode 100644 index 00000000000..a12d6a349db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.h x32,x32,x32' +.*: Error: illegal operands `cv.and.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-h-fail.s b/gas/testsuite/gas/riscv/cv-and-h-fail.s new file mode 100644 index 00000000000..98a278b3e3b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.h x32, x32, x32 + cv.and.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-h-pass.d b/gas/testsuite/gas/riscv/cv-and-h-pass.d new file mode 100644 index 00000000000..1f9b57df1c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800007b cv.and.h zero,zero,zero + 4: 681080fb cv.and.h ra,ra,ra + 8: 6821017b cv.and.h sp,sp,sp + c: 6884047b cv.and.h s0,s0,s0 + 10: 694a0a7b cv.and.h s4,s4,s4 + 14: 69ff8ffb cv.and.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-h-pass.s b/gas/testsuite/gas/riscv/cv-and-h-pass.s new file mode 100644 index 00000000000..2d3149b667a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.h x0, x0, x0 + cv.and.h x1, x1, x1 + cv.and.h x2, x2, x2 + cv.and.h x8, x8, x8 + cv.and.h x20, x20, x20 + cv.and.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.d new file mode 100644 index 00000000000..8a1cfa4e333 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-b-fail.s +#error_output: cv-and-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.l new file mode 100644 index 00000000000..cf9dd0e2935 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.and.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.s new file mode 100644 index 00000000000..780f7532e9b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.sc.b x32, x32, x32 + cv.and.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.d new file mode 100644 index 00000000000..bdece4adc7e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800507b cv.and.sc.b zero,zero,zero + 4: 6810d0fb cv.and.sc.b ra,ra,ra + 8: 6821517b cv.and.sc.b sp,sp,sp + c: 6884547b cv.and.sc.b s0,s0,s0 + 10: 694a5a7b cv.and.sc.b s4,s4,s4 + 14: 69ffdffb cv.and.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.s new file mode 100644 index 00000000000..a4e742fe76e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.sc.b x0, x0, x0 + cv.and.sc.b x1, x1, x1 + cv.and.sc.b x2, x2, x2 + cv.and.sc.b x8, x8, x8 + cv.and.sc.b x20, x20, x20 + cv.and.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.d new file mode 100644 index 00000000000..e65195da989 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-h-fail.s +#error_output: cv-and-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.l new file mode 100644 index 00000000000..cc0e3329db6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.and.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.s new file mode 100644 index 00000000000..c09eb0d1abc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.sc.h x32, x32, x32 + cv.and.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.d new file mode 100644 index 00000000000..8beb2b34ca8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800407b cv.and.sc.h zero,zero,zero + 4: 6810c0fb cv.and.sc.h ra,ra,ra + 8: 6821417b cv.and.sc.h sp,sp,sp + c: 6884447b cv.and.sc.h s0,s0,s0 + 10: 694a4a7b cv.and.sc.h s4,s4,s4 + 14: 69ffcffb cv.and.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.s new file mode 100644 index 00000000000..28830c19bee --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.sc.h x0, x0, x0 + cv.and.sc.h x1, x1, x1 + cv.and.sc.h x2, x2, x2 + cv.and.sc.h x8, x8, x8 + cv.and.sc.h x20, x20, x20 + cv.and.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.d new file mode 100644 index 00000000000..7df594b5dfc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-b-fail.s +#error_output: cv-and-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.l new file mode 100644 index 00000000000..a259452d78d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sci.b x32,x32,20' +.*: Error: illegal operands `cv.and.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.s new file mode 100644 index 00000000000..c250ed176da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.and.sci.b x32, x32, 20 + cv.and.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.and.sci.b x6, x7, -33 + cv.and.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.d new file mode 100644 index 00000000000..de6b9c5436d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6940707b cv.and.sci.b zero,zero,20 + 4: 6940f0fb cv.and.sci.b ra,ra,20 + 8: 6941717b cv.and.sci.b sp,sp,20 + c: 6944747b cv.and.sci.b s0,s0,20 + 10: 694a7a7b cv.and.sci.b s4,s4,20 + 14: 694ffffb cv.and.sci.b t6,t6,20 + 18: 6a03f37b cv.and.sci.b t1,t2,-32 + 1c: 6803f37b cv.and.sci.b t1,t2,0 + 20: 69f3f37b cv.and.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.s new file mode 100644 index 00000000000..4db2d1d79a7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.and.sci.b x0, x0, 20 + cv.and.sci.b x1, x1, 20 + cv.and.sci.b x2, x2, 20 + cv.and.sci.b x8, x8, 20 + cv.and.sci.b x20, x20, 20 + cv.and.sci.b x31, x31, 20 + #Immediate Values Test + cv.and.sci.b x6, x7, -32 + cv.and.sci.b x6, x7, 0 + cv.and.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.d new file mode 100644 index 00000000000..bf970ff736a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-h-fail.s +#error_output: cv-and-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.l new file mode 100644 index 00000000000..3564a7fce86 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sci.h x32,x32,20' +.*: Error: illegal operands `cv.and.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.s new file mode 100644 index 00000000000..25b85f2a3e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.and.sci.h x32, x32, 20 + cv.and.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.and.sci.h x6, x7, -33 + cv.and.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.d new file mode 100644 index 00000000000..0af22c73a63 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6940607b cv.and.sci.h zero,zero,20 + 4: 6940e0fb cv.and.sci.h ra,ra,20 + 8: 6941617b cv.and.sci.h sp,sp,20 + c: 6944647b cv.and.sci.h s0,s0,20 + 10: 694a6a7b cv.and.sci.h s4,s4,20 + 14: 694feffb cv.and.sci.h t6,t6,20 + 18: 6a03e37b cv.and.sci.h t1,t2,-32 + 1c: 6803e37b cv.and.sci.h t1,t2,0 + 20: 69f3e37b cv.and.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.s new file mode 100644 index 00000000000..4abb2f3daa8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.and.sci.h x0, x0, 20 + cv.and.sci.h x1, x1, 20 + cv.and.sci.h x2, x2, 20 + cv.and.sci.h x8, x8, 20 + cv.and.sci.h x20, x20, 20 + cv.and.sci.h x31, x31, 20 + #Immediate Values Test + cv.and.sci.h x6, x7, -32 + cv.and.sci.h x6, x7, 0 + cv.and.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avg-b-fail.d b/gas/testsuite/gas/riscv/cv-avg-b-fail.d new file mode 100644 index 00000000000..bb375b5cd7b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-b-fail.s +#error_output: cv-avg-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-b-fail.l b/gas/testsuite/gas/riscv/cv-avg-b-fail.l new file mode 100644 index 00000000000..7b693315d5e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.b x32,x32,x32' +.*: Error: illegal operands `cv.avg.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-b-fail.s b/gas/testsuite/gas/riscv/cv-avg-b-fail.s new file mode 100644 index 00000000000..93711991590 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.b x32, x32, x32 + cv.avg.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-b-pass.d b/gas/testsuite/gas/riscv/cv-avg-b-pass.d new file mode 100644 index 00000000000..f53777e530d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000107b cv.avg.b zero,zero,zero + 4: 101090fb cv.avg.b ra,ra,ra + 8: 1021117b cv.avg.b sp,sp,sp + c: 1084147b cv.avg.b s0,s0,s0 + 10: 114a1a7b cv.avg.b s4,s4,s4 + 14: 11ff9ffb cv.avg.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-b-pass.s b/gas/testsuite/gas/riscv/cv-avg-b-pass.s new file mode 100644 index 00000000000..1829a24774b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.b x0, x0, x0 + cv.avg.b x1, x1, x1 + cv.avg.b x2, x2, x2 + cv.avg.b x8, x8, x8 + cv.avg.b x20, x20, x20 + cv.avg.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-h-fail.d b/gas/testsuite/gas/riscv/cv-avg-h-fail.d new file mode 100644 index 00000000000..f68974ce4c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-h-fail.s +#error_output: cv-avg-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-h-fail.l b/gas/testsuite/gas/riscv/cv-avg-h-fail.l new file mode 100644 index 00000000000..387e31e1f04 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.h x32,x32,x32' +.*: Error: illegal operands `cv.avg.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-h-fail.s b/gas/testsuite/gas/riscv/cv-avg-h-fail.s new file mode 100644 index 00000000000..9a9171b76aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.h x32, x32, x32 + cv.avg.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-h-pass.d b/gas/testsuite/gas/riscv/cv-avg-h-pass.d new file mode 100644 index 00000000000..dbd588ce80d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000007b cv.avg.h zero,zero,zero + 4: 101080fb cv.avg.h ra,ra,ra + 8: 1021017b cv.avg.h sp,sp,sp + c: 1084047b cv.avg.h s0,s0,s0 + 10: 114a0a7b cv.avg.h s4,s4,s4 + 14: 11ff8ffb cv.avg.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-h-pass.s b/gas/testsuite/gas/riscv/cv-avg-h-pass.s new file mode 100644 index 00000000000..6572f47bc24 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.h x0, x0, x0 + cv.avg.h x1, x1, x1 + cv.avg.h x2, x2, x2 + cv.avg.h x8, x8, x8 + cv.avg.h x20, x20, x20 + cv.avg.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d new file mode 100644 index 00000000000..050cd525878 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-b-fail.s +#error_output: cv-avg-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l new file mode 100644 index 00000000000..dd22457c92d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.avg.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s new file mode 100644 index 00000000000..b4fcc7157f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.sc.b x32, x32, x32 + cv.avg.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d new file mode 100644 index 00000000000..7a381d1aa85 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000507b cv.avg.sc.b zero,zero,zero + 4: 1010d0fb cv.avg.sc.b ra,ra,ra + 8: 1021517b cv.avg.sc.b sp,sp,sp + c: 1084547b cv.avg.sc.b s0,s0,s0 + 10: 114a5a7b cv.avg.sc.b s4,s4,s4 + 14: 11ffdffb cv.avg.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s new file mode 100644 index 00000000000..65417deec84 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.sc.b x0, x0, x0 + cv.avg.sc.b x1, x1, x1 + cv.avg.sc.b x2, x2, x2 + cv.avg.sc.b x8, x8, x8 + cv.avg.sc.b x20, x20, x20 + cv.avg.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d new file mode 100644 index 00000000000..ff804203b77 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-h-fail.s +#error_output: cv-avg-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l new file mode 100644 index 00000000000..3df6422a9d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.avg.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s new file mode 100644 index 00000000000..f0e769cee1b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.sc.h x32, x32, x32 + cv.avg.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d new file mode 100644 index 00000000000..6f7e8855435 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000407b cv.avg.sc.h zero,zero,zero + 4: 1010c0fb cv.avg.sc.h ra,ra,ra + 8: 1021417b cv.avg.sc.h sp,sp,sp + c: 1084447b cv.avg.sc.h s0,s0,s0 + 10: 114a4a7b cv.avg.sc.h s4,s4,s4 + 14: 11ffcffb cv.avg.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s new file mode 100644 index 00000000000..6642c8e9836 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.sc.h x0, x0, x0 + cv.avg.sc.h x1, x1, x1 + cv.avg.sc.h x2, x2, x2 + cv.avg.sc.h x8, x8, x8 + cv.avg.sc.h x20, x20, x20 + cv.avg.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d new file mode 100644 index 00000000000..11aa6e0c706 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-b-fail.s +#error_output: cv-avg-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l new file mode 100644 index 00000000000..1d66f52499b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sci.b x32,x32,20' +.*: Error: illegal operands `cv.avg.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s new file mode 100644 index 00000000000..5eed74ad3c6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avg.sci.b x32, x32, 20 + cv.avg.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.avg.sci.b x6, x7, -33 + cv.avg.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d new file mode 100644 index 00000000000..9ebc5f5b0e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1140707b cv.avg.sci.b zero,zero,20 + 4: 1140f0fb cv.avg.sci.b ra,ra,20 + 8: 1141717b cv.avg.sci.b sp,sp,20 + c: 1144747b cv.avg.sci.b s0,s0,20 + 10: 114a7a7b cv.avg.sci.b s4,s4,20 + 14: 114ffffb cv.avg.sci.b t6,t6,20 + 18: 1203f37b cv.avg.sci.b t1,t2,-32 + 1c: 1003f37b cv.avg.sci.b t1,t2,0 + 20: 11f3f37b cv.avg.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s new file mode 100644 index 00000000000..726677aaa97 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avg.sci.b x0, x0, 20 + cv.avg.sci.b x1, x1, 20 + cv.avg.sci.b x2, x2, 20 + cv.avg.sci.b x8, x8, 20 + cv.avg.sci.b x20, x20, 20 + cv.avg.sci.b x31, x31, 20 + #Immediate Values Test + cv.avg.sci.b x6, x7, -32 + cv.avg.sci.b x6, x7, 0 + cv.avg.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d new file mode 100644 index 00000000000..5f607426064 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-h-fail.s +#error_output: cv-avg-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l new file mode 100644 index 00000000000..a5bc7a5cdb9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sci.h x32,x32,20' +.*: Error: illegal operands `cv.avg.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s new file mode 100644 index 00000000000..ae476ed9475 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avg.sci.h x32, x32, 20 + cv.avg.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.avg.sci.h x6, x7, -33 + cv.avg.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d new file mode 100644 index 00000000000..d4304f53bea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1140607b cv.avg.sci.h zero,zero,20 + 4: 1140e0fb cv.avg.sci.h ra,ra,20 + 8: 1141617b cv.avg.sci.h sp,sp,20 + c: 1144647b cv.avg.sci.h s0,s0,20 + 10: 114a6a7b cv.avg.sci.h s4,s4,20 + 14: 114feffb cv.avg.sci.h t6,t6,20 + 18: 1203e37b cv.avg.sci.h t1,t2,-32 + 1c: 1003e37b cv.avg.sci.h t1,t2,0 + 20: 11f3e37b cv.avg.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s new file mode 100644 index 00000000000..831c7812e69 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avg.sci.h x0, x0, 20 + cv.avg.sci.h x1, x1, 20 + cv.avg.sci.h x2, x2, 20 + cv.avg.sci.h x8, x8, 20 + cv.avg.sci.h x20, x20, 20 + cv.avg.sci.h x31, x31, 20 + #Immediate Values Test + cv.avg.sci.h x6, x7, -32 + cv.avg.sci.h x6, x7, 0 + cv.avg.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-fail.d b/gas/testsuite/gas/riscv/cv-avgu-b-fail.d new file mode 100644 index 00000000000..25450d4ebbd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-b-fail.s +#error_output: cv-avgu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-fail.l b/gas/testsuite/gas/riscv/cv-avgu-b-fail.l new file mode 100644 index 00000000000..945d5b11ad7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.b x32,x32,x32' +.*: Error: illegal operands `cv.avgu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-fail.s b/gas/testsuite/gas/riscv/cv-avgu-b-fail.s new file mode 100644 index 00000000000..b82b8f11107 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.b x32, x32, x32 + cv.avgu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-pass.d b/gas/testsuite/gas/riscv/cv-avgu-b-pass.d new file mode 100644 index 00000000000..b10162c7e22 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800107b cv.avgu.b zero,zero,zero + 4: 181090fb cv.avgu.b ra,ra,ra + 8: 1821117b cv.avgu.b sp,sp,sp + c: 1884147b cv.avgu.b s0,s0,s0 + 10: 194a1a7b cv.avgu.b s4,s4,s4 + 14: 19ff9ffb cv.avgu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-pass.s b/gas/testsuite/gas/riscv/cv-avgu-b-pass.s new file mode 100644 index 00000000000..b36cadcaf2d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.b x0, x0, x0 + cv.avgu.b x1, x1, x1 + cv.avgu.b x2, x2, x2 + cv.avgu.b x8, x8, x8 + cv.avgu.b x20, x20, x20 + cv.avgu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-fail.d b/gas/testsuite/gas/riscv/cv-avgu-h-fail.d new file mode 100644 index 00000000000..dd95a185877 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-h-fail.s +#error_output: cv-avgu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-fail.l b/gas/testsuite/gas/riscv/cv-avgu-h-fail.l new file mode 100644 index 00000000000..7c8f1554713 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.h x32,x32,x32' +.*: Error: illegal operands `cv.avgu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-fail.s b/gas/testsuite/gas/riscv/cv-avgu-h-fail.s new file mode 100644 index 00000000000..a384e97dad0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.h x32, x32, x32 + cv.avgu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-pass.d b/gas/testsuite/gas/riscv/cv-avgu-h-pass.d new file mode 100644 index 00000000000..68e46c1232a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800007b cv.avgu.h zero,zero,zero + 4: 181080fb cv.avgu.h ra,ra,ra + 8: 1821017b cv.avgu.h sp,sp,sp + c: 1884047b cv.avgu.h s0,s0,s0 + 10: 194a0a7b cv.avgu.h s4,s4,s4 + 14: 19ff8ffb cv.avgu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-pass.s b/gas/testsuite/gas/riscv/cv-avgu-h-pass.s new file mode 100644 index 00000000000..7f5cc08c459 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.h x0, x0, x0 + cv.avgu.h x1, x1, x1 + cv.avgu.h x2, x2, x2 + cv.avgu.h x8, x8, x8 + cv.avgu.h x20, x20, x20 + cv.avgu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d new file mode 100644 index 00000000000..89011f4a510 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-b-fail.s +#error_output: cv-avgu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l new file mode 100644 index 00000000000..477e1703fd2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.avgu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s new file mode 100644 index 00000000000..a778c92bcdc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.sc.b x32, x32, x32 + cv.avgu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d new file mode 100644 index 00000000000..05c245d08c1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800507b cv.avgu.sc.b zero,zero,zero + 4: 1810d0fb cv.avgu.sc.b ra,ra,ra + 8: 1821517b cv.avgu.sc.b sp,sp,sp + c: 1884547b cv.avgu.sc.b s0,s0,s0 + 10: 194a5a7b cv.avgu.sc.b s4,s4,s4 + 14: 19ffdffb cv.avgu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s new file mode 100644 index 00000000000..731cb07109e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.sc.b x0, x0, x0 + cv.avgu.sc.b x1, x1, x1 + cv.avgu.sc.b x2, x2, x2 + cv.avgu.sc.b x8, x8, x8 + cv.avgu.sc.b x20, x20, x20 + cv.avgu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d new file mode 100644 index 00000000000..ae77453294a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-h-fail.s +#error_output: cv-avgu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l new file mode 100644 index 00000000000..b4192d02b66 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.avgu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s new file mode 100644 index 00000000000..bd031f155f3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.sc.h x32, x32, x32 + cv.avgu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d new file mode 100644 index 00000000000..048f00a9944 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800407b cv.avgu.sc.h zero,zero,zero + 4: 1810c0fb cv.avgu.sc.h ra,ra,ra + 8: 1821417b cv.avgu.sc.h sp,sp,sp + c: 1884447b cv.avgu.sc.h s0,s0,s0 + 10: 194a4a7b cv.avgu.sc.h s4,s4,s4 + 14: 19ffcffb cv.avgu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s new file mode 100644 index 00000000000..b22a133e9d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.sc.h x0, x0, x0 + cv.avgu.sc.h x1, x1, x1 + cv.avgu.sc.h x2, x2, x2 + cv.avgu.sc.h x8, x8, x8 + cv.avgu.sc.h x20, x20, x20 + cv.avgu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d new file mode 100644 index 00000000000..bace8babc92 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-b-fail.s +#error_output: cv-avgu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l new file mode 100644 index 00000000000..00c22293b6c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.avgu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s new file mode 100644 index 00000000000..c8f9ee5c12a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avgu.sci.b x32, x32, 20 + cv.avgu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.avgu.sci.b x6, x7, -33 + cv.avgu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d new file mode 100644 index 00000000000..b8db390e44a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1940707b cv.avgu.sci.b zero,zero,20 + 4: 1940f0fb cv.avgu.sci.b ra,ra,20 + 8: 1941717b cv.avgu.sci.b sp,sp,20 + c: 1944747b cv.avgu.sci.b s0,s0,20 + 10: 194a7a7b cv.avgu.sci.b s4,s4,20 + 14: 194ffffb cv.avgu.sci.b t6,t6,20 + 18: 1a03f37b cv.avgu.sci.b t1,t2,-32 + 1c: 1803f37b cv.avgu.sci.b t1,t2,0 + 20: 19f3f37b cv.avgu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s new file mode 100644 index 00000000000..b276d7f45b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avgu.sci.b x0, x0, 20 + cv.avgu.sci.b x1, x1, 20 + cv.avgu.sci.b x2, x2, 20 + cv.avgu.sci.b x8, x8, 20 + cv.avgu.sci.b x20, x20, 20 + cv.avgu.sci.b x31, x31, 20 + #Immediate Values Test + cv.avgu.sci.b x6, x7, -32 + cv.avgu.sci.b x6, x7, 0 + cv.avgu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d new file mode 100644 index 00000000000..3826b72f9d2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-h-fail.s +#error_output: cv-avgu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l new file mode 100644 index 00000000000..a4070f4170b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.avgu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s new file mode 100644 index 00000000000..c9ae574d888 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avgu.sci.h x32, x32, 20 + cv.avgu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.avgu.sci.h x6, x7, -33 + cv.avgu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d new file mode 100644 index 00000000000..a34f5dc3718 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1940607b cv.avgu.sci.h zero,zero,20 + 4: 1940e0fb cv.avgu.sci.h ra,ra,20 + 8: 1941617b cv.avgu.sci.h sp,sp,20 + c: 1944647b cv.avgu.sci.h s0,s0,20 + 10: 194a6a7b cv.avgu.sci.h s4,s4,20 + 14: 194feffb cv.avgu.sci.h t6,t6,20 + 18: 1a03e37b cv.avgu.sci.h t1,t2,-32 + 1c: 1803e37b cv.avgu.sci.h t1,t2,0 + 20: 19f3e37b cv.avgu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s new file mode 100644 index 00000000000..cf16ff3eb5c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avgu.sci.h x0, x0, 20 + cv.avgu.sci.h x1, x1, 20 + cv.avgu.sci.h x2, x2, 20 + cv.avgu.sci.h x8, x8, 20 + cv.avgu.sci.h x20, x20, 20 + cv.avgu.sci.h x31, x31, 20 + #Immediate Values Test + cv.avgu.sci.h x6, x7, -32 + cv.avgu.sci.h x6, x7, 0 + cv.avgu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d new file mode 100644 index 00000000000..a4e1f8e1952 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-b-fail.s +#error_output: cv-cmpeq-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l new file mode 100644 index 00000000000..4aac9f46da2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s new file mode 100644 index 00000000000..9b6e33703a3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.b x32, x32, x32 + cv.cmpeq.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d new file mode 100644 index 00000000000..8427be1310a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400107b cv.cmpeq.b zero,zero,zero + 4: 041090fb cv.cmpeq.b ra,ra,ra + 8: 0421117b cv.cmpeq.b sp,sp,sp + c: 0484147b cv.cmpeq.b s0,s0,s0 + 10: 054a1a7b cv.cmpeq.b s4,s4,s4 + 14: 05ff9ffb cv.cmpeq.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s new file mode 100644 index 00000000000..11496e533c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.b x0, x0, x0 + cv.cmpeq.b x1, x1, x1 + cv.cmpeq.b x2, x2, x2 + cv.cmpeq.b x8, x8, x8 + cv.cmpeq.b x20, x20, x20 + cv.cmpeq.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d new file mode 100644 index 00000000000..a3835eff5fa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-h-fail.s +#error_output: cv-cmpeq-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l new file mode 100644 index 00000000000..a4a2d73299c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s new file mode 100644 index 00000000000..7e5f0d0b0d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.h x32, x32, x32 + cv.cmpeq.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d new file mode 100644 index 00000000000..d8833609d57 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400007b cv.cmpeq.h zero,zero,zero + 4: 041080fb cv.cmpeq.h ra,ra,ra + 8: 0421017b cv.cmpeq.h sp,sp,sp + c: 0484047b cv.cmpeq.h s0,s0,s0 + 10: 054a0a7b cv.cmpeq.h s4,s4,s4 + 14: 05ff8ffb cv.cmpeq.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s new file mode 100644 index 00000000000..209aff81770 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.h x0, x0, x0 + cv.cmpeq.h x1, x1, x1 + cv.cmpeq.h x2, x2, x2 + cv.cmpeq.h x8, x8, x8 + cv.cmpeq.h x20, x20, x20 + cv.cmpeq.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d new file mode 100644 index 00000000000..a2a13d2ffdf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-b-fail.s +#error_output: cv-cmpeq-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l new file mode 100644 index 00000000000..43c0f88c42b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s new file mode 100644 index 00000000000..e4923d95943 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.sc.b x32, x32, x32 + cv.cmpeq.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d new file mode 100644 index 00000000000..42f11ec3607 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400507b cv.cmpeq.sc.b zero,zero,zero + 4: 0410d0fb cv.cmpeq.sc.b ra,ra,ra + 8: 0421517b cv.cmpeq.sc.b sp,sp,sp + c: 0484547b cv.cmpeq.sc.b s0,s0,s0 + 10: 054a5a7b cv.cmpeq.sc.b s4,s4,s4 + 14: 05ffdffb cv.cmpeq.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s new file mode 100644 index 00000000000..a67ccd388e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.sc.b x0, x0, x0 + cv.cmpeq.sc.b x1, x1, x1 + cv.cmpeq.sc.b x2, x2, x2 + cv.cmpeq.sc.b x8, x8, x8 + cv.cmpeq.sc.b x20, x20, x20 + cv.cmpeq.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d new file mode 100644 index 00000000000..3d7e3fb0e22 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-h-fail.s +#error_output: cv-cmpeq-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l new file mode 100644 index 00000000000..13275a99112 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s new file mode 100644 index 00000000000..c09e8c9fc21 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.sc.h x32, x32, x32 + cv.cmpeq.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d new file mode 100644 index 00000000000..74afa8410c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400407b cv.cmpeq.sc.h zero,zero,zero + 4: 0410c0fb cv.cmpeq.sc.h ra,ra,ra + 8: 0421417b cv.cmpeq.sc.h sp,sp,sp + c: 0484447b cv.cmpeq.sc.h s0,s0,s0 + 10: 054a4a7b cv.cmpeq.sc.h s4,s4,s4 + 14: 05ffcffb cv.cmpeq.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s new file mode 100644 index 00000000000..f8f2c279618 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.sc.h x0, x0, x0 + cv.cmpeq.sc.h x1, x1, x1 + cv.cmpeq.sc.h x2, x2, x2 + cv.cmpeq.sc.h x8, x8, x8 + cv.cmpeq.sc.h x20, x20, x20 + cv.cmpeq.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d new file mode 100644 index 00000000000..9ceea8712b9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-b-fail.s +#error_output: cv-cmpeq-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l new file mode 100644 index 00000000000..0d488f66ce1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpeq.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s new file mode 100644 index 00000000000..eb02b373284 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpeq.sci.b x32, x32, 20 + cv.cmpeq.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpeq.sci.b x6, x7, -33 + cv.cmpeq.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d new file mode 100644 index 00000000000..11970e7b9ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0540707b cv.cmpeq.sci.b zero,zero,20 + 4: 0540f0fb cv.cmpeq.sci.b ra,ra,20 + 8: 0541717b cv.cmpeq.sci.b sp,sp,20 + c: 0544747b cv.cmpeq.sci.b s0,s0,20 + 10: 054a7a7b cv.cmpeq.sci.b s4,s4,20 + 14: 054ffffb cv.cmpeq.sci.b t6,t6,20 + 18: 0603f37b cv.cmpeq.sci.b t1,t2,-32 + 1c: 0403f37b cv.cmpeq.sci.b t1,t2,0 + 20: 05f3f37b cv.cmpeq.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s new file mode 100644 index 00000000000..891c61def45 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpeq.sci.b x0, x0, 20 + cv.cmpeq.sci.b x1, x1, 20 + cv.cmpeq.sci.b x2, x2, 20 + cv.cmpeq.sci.b x8, x8, 20 + cv.cmpeq.sci.b x20, x20, 20 + cv.cmpeq.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpeq.sci.b x6, x7, -32 + cv.cmpeq.sci.b x6, x7, 0 + cv.cmpeq.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d new file mode 100644 index 00000000000..80d4e28e055 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-h-fail.s +#error_output: cv-cmpeq-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l new file mode 100644 index 00000000000..77a6cd56bf1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpeq.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s new file mode 100644 index 00000000000..ece9bd5b297 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpeq.sci.h x32, x32, 20 + cv.cmpeq.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpeq.sci.h x6, x7, -33 + cv.cmpeq.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d new file mode 100644 index 00000000000..352caee8243 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0540607b cv.cmpeq.sci.h zero,zero,20 + 4: 0540e0fb cv.cmpeq.sci.h ra,ra,20 + 8: 0541617b cv.cmpeq.sci.h sp,sp,20 + c: 0544647b cv.cmpeq.sci.h s0,s0,20 + 10: 054a6a7b cv.cmpeq.sci.h s4,s4,20 + 14: 054feffb cv.cmpeq.sci.h t6,t6,20 + 18: 0603e37b cv.cmpeq.sci.h t1,t2,-32 + 1c: 0403e37b cv.cmpeq.sci.h t1,t2,0 + 20: 05f3e37b cv.cmpeq.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s new file mode 100644 index 00000000000..4eee62b625f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpeq.sci.h x0, x0, 20 + cv.cmpeq.sci.h x1, x1, 20 + cv.cmpeq.sci.h x2, x2, 20 + cv.cmpeq.sci.h x8, x8, 20 + cv.cmpeq.sci.h x20, x20, 20 + cv.cmpeq.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpeq.sci.h x6, x7, -32 + cv.cmpeq.sci.h x6, x7, 0 + cv.cmpeq.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.d new file mode 100644 index 00000000000..9fcf0e70f2b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-b-fail.s +#error_output: cv-cmpge-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.l new file mode 100644 index 00000000000..a08e74fe104 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.s new file mode 100644 index 00000000000..0d5a7453124 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.b x32, x32, x32 + cv.cmpge.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.d new file mode 100644 index 00000000000..da510d7c231 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00107b cv.cmpge.b zero,zero,zero + 4: 1c1090fb cv.cmpge.b ra,ra,ra + 8: 1c21117b cv.cmpge.b sp,sp,sp + c: 1c84147b cv.cmpge.b s0,s0,s0 + 10: 1d4a1a7b cv.cmpge.b s4,s4,s4 + 14: 1dff9ffb cv.cmpge.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.s new file mode 100644 index 00000000000..126d8b52de2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.b x0, x0, x0 + cv.cmpge.b x1, x1, x1 + cv.cmpge.b x2, x2, x2 + cv.cmpge.b x8, x8, x8 + cv.cmpge.b x20, x20, x20 + cv.cmpge.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.d new file mode 100644 index 00000000000..24359f8767d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-h-fail.s +#error_output: cv-cmpge-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.l new file mode 100644 index 00000000000..a9f0019ae95 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.s new file mode 100644 index 00000000000..650213a4591 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.h x32, x32, x32 + cv.cmpge.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.d new file mode 100644 index 00000000000..e1b136d205f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00007b cv.cmpge.h zero,zero,zero + 4: 1c1080fb cv.cmpge.h ra,ra,ra + 8: 1c21017b cv.cmpge.h sp,sp,sp + c: 1c84047b cv.cmpge.h s0,s0,s0 + 10: 1d4a0a7b cv.cmpge.h s4,s4,s4 + 14: 1dff8ffb cv.cmpge.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.s new file mode 100644 index 00000000000..6a6dd7f6aec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.h x0, x0, x0 + cv.cmpge.h x1, x1, x1 + cv.cmpge.h x2, x2, x2 + cv.cmpge.h x8, x8, x8 + cv.cmpge.h x20, x20, x20 + cv.cmpge.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d new file mode 100644 index 00000000000..3ea95c1da24 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-b-fail.s +#error_output: cv-cmpge-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l new file mode 100644 index 00000000000..2d73720e32c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s new file mode 100644 index 00000000000..9c13024b08b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.sc.b x32, x32, x32 + cv.cmpge.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d new file mode 100644 index 00000000000..56c5b1b7a4b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00507b cv.cmpge.sc.b zero,zero,zero + 4: 1c10d0fb cv.cmpge.sc.b ra,ra,ra + 8: 1c21517b cv.cmpge.sc.b sp,sp,sp + c: 1c84547b cv.cmpge.sc.b s0,s0,s0 + 10: 1d4a5a7b cv.cmpge.sc.b s4,s4,s4 + 14: 1dffdffb cv.cmpge.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s new file mode 100644 index 00000000000..d6a61c21eae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.sc.b x0, x0, x0 + cv.cmpge.sc.b x1, x1, x1 + cv.cmpge.sc.b x2, x2, x2 + cv.cmpge.sc.b x8, x8, x8 + cv.cmpge.sc.b x20, x20, x20 + cv.cmpge.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d new file mode 100644 index 00000000000..62060191f52 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-h-fail.s +#error_output: cv-cmpge-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l new file mode 100644 index 00000000000..97c55e41c90 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s new file mode 100644 index 00000000000..93bbb03db2a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.sc.h x32, x32, x32 + cv.cmpge.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d new file mode 100644 index 00000000000..ae3051f8ed0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00407b cv.cmpge.sc.h zero,zero,zero + 4: 1c10c0fb cv.cmpge.sc.h ra,ra,ra + 8: 1c21417b cv.cmpge.sc.h sp,sp,sp + c: 1c84447b cv.cmpge.sc.h s0,s0,s0 + 10: 1d4a4a7b cv.cmpge.sc.h s4,s4,s4 + 14: 1dffcffb cv.cmpge.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s new file mode 100644 index 00000000000..1458f22df06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.sc.h x0, x0, x0 + cv.cmpge.sc.h x1, x1, x1 + cv.cmpge.sc.h x2, x2, x2 + cv.cmpge.sc.h x8, x8, x8 + cv.cmpge.sc.h x20, x20, x20 + cv.cmpge.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d new file mode 100644 index 00000000000..4ce717d3751 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-b-fail.s +#error_output: cv-cmpge-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l new file mode 100644 index 00000000000..cfebdde1262 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpge.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s new file mode 100644 index 00000000000..e87d0d2bbd7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpge.sci.b x32, x32, 20 + cv.cmpge.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpge.sci.b x6, x7, -33 + cv.cmpge.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d new file mode 100644 index 00000000000..8283ca50e95 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1d40707b cv.cmpge.sci.b zero,zero,20 + 4: 1d40f0fb cv.cmpge.sci.b ra,ra,20 + 8: 1d41717b cv.cmpge.sci.b sp,sp,20 + c: 1d44747b cv.cmpge.sci.b s0,s0,20 + 10: 1d4a7a7b cv.cmpge.sci.b s4,s4,20 + 14: 1d4ffffb cv.cmpge.sci.b t6,t6,20 + 18: 1e03f37b cv.cmpge.sci.b t1,t2,-32 + 1c: 1c03f37b cv.cmpge.sci.b t1,t2,0 + 20: 1df3f37b cv.cmpge.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s new file mode 100644 index 00000000000..f78c97537c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpge.sci.b x0, x0, 20 + cv.cmpge.sci.b x1, x1, 20 + cv.cmpge.sci.b x2, x2, 20 + cv.cmpge.sci.b x8, x8, 20 + cv.cmpge.sci.b x20, x20, 20 + cv.cmpge.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpge.sci.b x6, x7, -32 + cv.cmpge.sci.b x6, x7, 0 + cv.cmpge.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d new file mode 100644 index 00000000000..08a4296ba73 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-h-fail.s +#error_output: cv-cmpge-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l new file mode 100644 index 00000000000..b29956b0d6c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpge.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s new file mode 100644 index 00000000000..07ec29ce17f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpge.sci.h x32, x32, 20 + cv.cmpge.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpge.sci.h x6, x7, -33 + cv.cmpge.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d new file mode 100644 index 00000000000..3bb1e1a0d2a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1d40607b cv.cmpge.sci.h zero,zero,20 + 4: 1d40e0fb cv.cmpge.sci.h ra,ra,20 + 8: 1d41617b cv.cmpge.sci.h sp,sp,20 + c: 1d44647b cv.cmpge.sci.h s0,s0,20 + 10: 1d4a6a7b cv.cmpge.sci.h s4,s4,20 + 14: 1d4feffb cv.cmpge.sci.h t6,t6,20 + 18: 1e03e37b cv.cmpge.sci.h t1,t2,-32 + 1c: 1c03e37b cv.cmpge.sci.h t1,t2,0 + 20: 1df3e37b cv.cmpge.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s new file mode 100644 index 00000000000..0410c9bcfd9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpge.sci.h x0, x0, 20 + cv.cmpge.sci.h x1, x1, 20 + cv.cmpge.sci.h x2, x2, 20 + cv.cmpge.sci.h x8, x8, 20 + cv.cmpge.sci.h x20, x20, 20 + cv.cmpge.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpge.sci.h x6, x7, -32 + cv.cmpge.sci.h x6, x7, 0 + cv.cmpge.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d new file mode 100644 index 00000000000..3d3dcf9f5b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-b-fail.s +#error_output: cv-cmpgeu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l new file mode 100644 index 00000000000..a5765fd2abb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s new file mode 100644 index 00000000000..92c5cdcd72b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.b x32, x32, x32 + cv.cmpgeu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d new file mode 100644 index 00000000000..b7e41e6c343 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00107b cv.cmpgeu.b zero,zero,zero + 4: 3c1090fb cv.cmpgeu.b ra,ra,ra + 8: 3c21117b cv.cmpgeu.b sp,sp,sp + c: 3c84147b cv.cmpgeu.b s0,s0,s0 + 10: 3d4a1a7b cv.cmpgeu.b s4,s4,s4 + 14: 3dff9ffb cv.cmpgeu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s new file mode 100644 index 00000000000..a5102117823 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.b x0, x0, x0 + cv.cmpgeu.b x1, x1, x1 + cv.cmpgeu.b x2, x2, x2 + cv.cmpgeu.b x8, x8, x8 + cv.cmpgeu.b x20, x20, x20 + cv.cmpgeu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d new file mode 100644 index 00000000000..d86c835d5f9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-h-fail.s +#error_output: cv-cmpgeu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l new file mode 100644 index 00000000000..237d1505e05 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s new file mode 100644 index 00000000000..e1f496e794b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.h x32, x32, x32 + cv.cmpgeu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d new file mode 100644 index 00000000000..d9b70f85c9f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00007b cv.cmpgeu.h zero,zero,zero + 4: 3c1080fb cv.cmpgeu.h ra,ra,ra + 8: 3c21017b cv.cmpgeu.h sp,sp,sp + c: 3c84047b cv.cmpgeu.h s0,s0,s0 + 10: 3d4a0a7b cv.cmpgeu.h s4,s4,s4 + 14: 3dff8ffb cv.cmpgeu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s new file mode 100644 index 00000000000..845f740d663 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.h x0, x0, x0 + cv.cmpgeu.h x1, x1, x1 + cv.cmpgeu.h x2, x2, x2 + cv.cmpgeu.h x8, x8, x8 + cv.cmpgeu.h x20, x20, x20 + cv.cmpgeu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d new file mode 100644 index 00000000000..4c6d7390ef7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-b-fail.s +#error_output: cv-cmpgeu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l new file mode 100644 index 00000000000..d80803402ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s new file mode 100644 index 00000000000..b2072fb84a9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sc.b x32, x32, x32 + cv.cmpgeu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d new file mode 100644 index 00000000000..2895ffe1f1c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00507b cv.cmpgeu.sc.b zero,zero,zero + 4: 3c10d0fb cv.cmpgeu.sc.b ra,ra,ra + 8: 3c21517b cv.cmpgeu.sc.b sp,sp,sp + c: 3c84547b cv.cmpgeu.sc.b s0,s0,s0 + 10: 3d4a5a7b cv.cmpgeu.sc.b s4,s4,s4 + 14: 3dffdffb cv.cmpgeu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s new file mode 100644 index 00000000000..d9da9a8b4a6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.sc.b x0, x0, x0 + cv.cmpgeu.sc.b x1, x1, x1 + cv.cmpgeu.sc.b x2, x2, x2 + cv.cmpgeu.sc.b x8, x8, x8 + cv.cmpgeu.sc.b x20, x20, x20 + cv.cmpgeu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d new file mode 100644 index 00000000000..e4da8d6c879 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-h-fail.s +#error_output: cv-cmpgeu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l new file mode 100644 index 00000000000..711b5fd0a4f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s new file mode 100644 index 00000000000..1c55aedb1c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sc.h x32, x32, x32 + cv.cmpgeu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d new file mode 100644 index 00000000000..10dde918f71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00407b cv.cmpgeu.sc.h zero,zero,zero + 4: 3c10c0fb cv.cmpgeu.sc.h ra,ra,ra + 8: 3c21417b cv.cmpgeu.sc.h sp,sp,sp + c: 3c84447b cv.cmpgeu.sc.h s0,s0,s0 + 10: 3d4a4a7b cv.cmpgeu.sc.h s4,s4,s4 + 14: 3dffcffb cv.cmpgeu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s new file mode 100644 index 00000000000..98e27220e32 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.sc.h x0, x0, x0 + cv.cmpgeu.sc.h x1, x1, x1 + cv.cmpgeu.sc.h x2, x2, x2 + cv.cmpgeu.sc.h x8, x8, x8 + cv.cmpgeu.sc.h x20, x20, x20 + cv.cmpgeu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d new file mode 100644 index 00000000000..ddd48e4116b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-b-fail.s +#error_output: cv-cmpgeu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l new file mode 100644 index 00000000000..2b5c698f963 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpgeu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s new file mode 100644 index 00000000000..cffa1bedf0b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sci.b x32, x32, 20 + cv.cmpgeu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgeu.sci.b x6, x7, -33 + cv.cmpgeu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d new file mode 100644 index 00000000000..65cb20f6734 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3d40707b cv.cmpgeu.sci.b zero,zero,20 + 4: 3d40f0fb cv.cmpgeu.sci.b ra,ra,20 + 8: 3d41717b cv.cmpgeu.sci.b sp,sp,20 + c: 3d44747b cv.cmpgeu.sci.b s0,s0,20 + 10: 3d4a7a7b cv.cmpgeu.sci.b s4,s4,20 + 14: 3d4ffffb cv.cmpgeu.sci.b t6,t6,20 + 18: 3e03f37b cv.cmpgeu.sci.b t1,t2,-32 + 1c: 3c03f37b cv.cmpgeu.sci.b t1,t2,0 + 20: 3df3f37b cv.cmpgeu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s new file mode 100644 index 00000000000..b05a72cf87e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgeu.sci.b x0, x0, 20 + cv.cmpgeu.sci.b x1, x1, 20 + cv.cmpgeu.sci.b x2, x2, 20 + cv.cmpgeu.sci.b x8, x8, 20 + cv.cmpgeu.sci.b x20, x20, 20 + cv.cmpgeu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpgeu.sci.b x6, x7, -32 + cv.cmpgeu.sci.b x6, x7, 0 + cv.cmpgeu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d new file mode 100644 index 00000000000..8b05795461f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-h-fail.s +#error_output: cv-cmpgeu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l new file mode 100644 index 00000000000..67af34b76b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpgeu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s new file mode 100644 index 00000000000..bb600368395 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sci.h x32, x32, 20 + cv.cmpgeu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgeu.sci.h x6, x7, -33 + cv.cmpgeu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d new file mode 100644 index 00000000000..86303022d4e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3d40607b cv.cmpgeu.sci.h zero,zero,20 + 4: 3d40e0fb cv.cmpgeu.sci.h ra,ra,20 + 8: 3d41617b cv.cmpgeu.sci.h sp,sp,20 + c: 3d44647b cv.cmpgeu.sci.h s0,s0,20 + 10: 3d4a6a7b cv.cmpgeu.sci.h s4,s4,20 + 14: 3d4feffb cv.cmpgeu.sci.h t6,t6,20 + 18: 3e03e37b cv.cmpgeu.sci.h t1,t2,-32 + 1c: 3c03e37b cv.cmpgeu.sci.h t1,t2,0 + 20: 3df3e37b cv.cmpgeu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s new file mode 100644 index 00000000000..442946b26fb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgeu.sci.h x0, x0, 20 + cv.cmpgeu.sci.h x1, x1, 20 + cv.cmpgeu.sci.h x2, x2, 20 + cv.cmpgeu.sci.h x8, x8, 20 + cv.cmpgeu.sci.h x20, x20, 20 + cv.cmpgeu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpgeu.sci.h x6, x7, -32 + cv.cmpgeu.sci.h x6, x7, 0 + cv.cmpgeu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d new file mode 100644 index 00000000000..37c865f2278 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-b-fail.s +#error_output: cv-cmpgt-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l new file mode 100644 index 00000000000..4e68125dad4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s new file mode 100644 index 00000000000..6cf859be6d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.b x32, x32, x32 + cv.cmpgt.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d new file mode 100644 index 00000000000..bf6a0bbf20f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400107b cv.cmpgt.b zero,zero,zero + 4: 141090fb cv.cmpgt.b ra,ra,ra + 8: 1421117b cv.cmpgt.b sp,sp,sp + c: 1484147b cv.cmpgt.b s0,s0,s0 + 10: 154a1a7b cv.cmpgt.b s4,s4,s4 + 14: 15ff9ffb cv.cmpgt.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s new file mode 100644 index 00000000000..9f2f9a82321 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.b x0, x0, x0 + cv.cmpgt.b x1, x1, x1 + cv.cmpgt.b x2, x2, x2 + cv.cmpgt.b x8, x8, x8 + cv.cmpgt.b x20, x20, x20 + cv.cmpgt.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d new file mode 100644 index 00000000000..631a5231bda --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-h-fail.s +#error_output: cv-cmpgt-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l new file mode 100644 index 00000000000..9237078e20a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s new file mode 100644 index 00000000000..5a371c9183b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.h x32, x32, x32 + cv.cmpgt.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d new file mode 100644 index 00000000000..4f661c7560a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400007b cv.cmpgt.h zero,zero,zero + 4: 141080fb cv.cmpgt.h ra,ra,ra + 8: 1421017b cv.cmpgt.h sp,sp,sp + c: 1484047b cv.cmpgt.h s0,s0,s0 + 10: 154a0a7b cv.cmpgt.h s4,s4,s4 + 14: 15ff8ffb cv.cmpgt.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s new file mode 100644 index 00000000000..57ebba6ea32 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.h x0, x0, x0 + cv.cmpgt.h x1, x1, x1 + cv.cmpgt.h x2, x2, x2 + cv.cmpgt.h x8, x8, x8 + cv.cmpgt.h x20, x20, x20 + cv.cmpgt.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d new file mode 100644 index 00000000000..0d75332eaf6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-b-fail.s +#error_output: cv-cmpgt-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l new file mode 100644 index 00000000000..526c0b90ba9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s new file mode 100644 index 00000000000..943b1fffa8f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.sc.b x32, x32, x32 + cv.cmpgt.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d new file mode 100644 index 00000000000..5a6fa4b4db3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400507b cv.cmpgt.sc.b zero,zero,zero + 4: 1410d0fb cv.cmpgt.sc.b ra,ra,ra + 8: 1421517b cv.cmpgt.sc.b sp,sp,sp + c: 1484547b cv.cmpgt.sc.b s0,s0,s0 + 10: 154a5a7b cv.cmpgt.sc.b s4,s4,s4 + 14: 15ffdffb cv.cmpgt.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s new file mode 100644 index 00000000000..64d3f2aac57 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.sc.b x0, x0, x0 + cv.cmpgt.sc.b x1, x1, x1 + cv.cmpgt.sc.b x2, x2, x2 + cv.cmpgt.sc.b x8, x8, x8 + cv.cmpgt.sc.b x20, x20, x20 + cv.cmpgt.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d new file mode 100644 index 00000000000..64ae6551783 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-h-fail.s +#error_output: cv-cmpgt-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l new file mode 100644 index 00000000000..e13663d6149 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s new file mode 100644 index 00000000000..a218dae2ff9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.sc.h x32, x32, x32 + cv.cmpgt.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d new file mode 100644 index 00000000000..5109cf81d22 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400407b cv.cmpgt.sc.h zero,zero,zero + 4: 1410c0fb cv.cmpgt.sc.h ra,ra,ra + 8: 1421417b cv.cmpgt.sc.h sp,sp,sp + c: 1484447b cv.cmpgt.sc.h s0,s0,s0 + 10: 154a4a7b cv.cmpgt.sc.h s4,s4,s4 + 14: 15ffcffb cv.cmpgt.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s new file mode 100644 index 00000000000..1571837994b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.sc.h x0, x0, x0 + cv.cmpgt.sc.h x1, x1, x1 + cv.cmpgt.sc.h x2, x2, x2 + cv.cmpgt.sc.h x8, x8, x8 + cv.cmpgt.sc.h x20, x20, x20 + cv.cmpgt.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d new file mode 100644 index 00000000000..b194ff54b81 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-b-fail.s +#error_output: cv-cmpgt-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l new file mode 100644 index 00000000000..0afcded817f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpgt.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s new file mode 100644 index 00000000000..24eede735b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgt.sci.b x32, x32, 20 + cv.cmpgt.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgt.sci.b x6, x7, -33 + cv.cmpgt.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d new file mode 100644 index 00000000000..944cab92fbb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1540707b cv.cmpgt.sci.b zero,zero,20 + 4: 1540f0fb cv.cmpgt.sci.b ra,ra,20 + 8: 1541717b cv.cmpgt.sci.b sp,sp,20 + c: 1544747b cv.cmpgt.sci.b s0,s0,20 + 10: 154a7a7b cv.cmpgt.sci.b s4,s4,20 + 14: 154ffffb cv.cmpgt.sci.b t6,t6,20 + 18: 1603f37b cv.cmpgt.sci.b t1,t2,-32 + 1c: 1403f37b cv.cmpgt.sci.b t1,t2,0 + 20: 15f3f37b cv.cmpgt.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s new file mode 100644 index 00000000000..62b1dae3c95 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgt.sci.b x0, x0, 20 + cv.cmpgt.sci.b x1, x1, 20 + cv.cmpgt.sci.b x2, x2, 20 + cv.cmpgt.sci.b x8, x8, 20 + cv.cmpgt.sci.b x20, x20, 20 + cv.cmpgt.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpgt.sci.b x6, x7, -32 + cv.cmpgt.sci.b x6, x7, 0 + cv.cmpgt.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d new file mode 100644 index 00000000000..466bb2447d7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-h-fail.s +#error_output: cv-cmpgt-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l new file mode 100644 index 00000000000..cb3234ffa5d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpgt.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s new file mode 100644 index 00000000000..080c6f85615 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgt.sci.h x32, x32, 20 + cv.cmpgt.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgt.sci.h x6, x7, -33 + cv.cmpgt.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d new file mode 100644 index 00000000000..08a0b7ceec7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1540607b cv.cmpgt.sci.h zero,zero,20 + 4: 1540e0fb cv.cmpgt.sci.h ra,ra,20 + 8: 1541617b cv.cmpgt.sci.h sp,sp,20 + c: 1544647b cv.cmpgt.sci.h s0,s0,20 + 10: 154a6a7b cv.cmpgt.sci.h s4,s4,20 + 14: 154feffb cv.cmpgt.sci.h t6,t6,20 + 18: 1603e37b cv.cmpgt.sci.h t1,t2,-32 + 1c: 1403e37b cv.cmpgt.sci.h t1,t2,0 + 20: 15f3e37b cv.cmpgt.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s new file mode 100644 index 00000000000..7b0722efa31 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgt.sci.h x0, x0, 20 + cv.cmpgt.sci.h x1, x1, 20 + cv.cmpgt.sci.h x2, x2, 20 + cv.cmpgt.sci.h x8, x8, 20 + cv.cmpgt.sci.h x20, x20, 20 + cv.cmpgt.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpgt.sci.h x6, x7, -32 + cv.cmpgt.sci.h x6, x7, 0 + cv.cmpgt.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d new file mode 100644 index 00000000000..38720797b14 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-b-fail.s +#error_output: cv-cmpgtu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l new file mode 100644 index 00000000000..dec5965c148 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s new file mode 100644 index 00000000000..bb12cf5f7b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.b x32, x32, x32 + cv.cmpgtu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d new file mode 100644 index 00000000000..e66c93051c7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400107b cv.cmpgtu.b zero,zero,zero + 4: 341090fb cv.cmpgtu.b ra,ra,ra + 8: 3421117b cv.cmpgtu.b sp,sp,sp + c: 3484147b cv.cmpgtu.b s0,s0,s0 + 10: 354a1a7b cv.cmpgtu.b s4,s4,s4 + 14: 35ff9ffb cv.cmpgtu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s new file mode 100644 index 00000000000..e5d782a39fb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.b x0, x0, x0 + cv.cmpgtu.b x1, x1, x1 + cv.cmpgtu.b x2, x2, x2 + cv.cmpgtu.b x8, x8, x8 + cv.cmpgtu.b x20, x20, x20 + cv.cmpgtu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d new file mode 100644 index 00000000000..2ff3d7e3f82 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-h-fail.s +#error_output: cv-cmpgtu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l new file mode 100644 index 00000000000..09b6b0c67fb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s new file mode 100644 index 00000000000..091f250ea41 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.h x32, x32, x32 + cv.cmpgtu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d new file mode 100644 index 00000000000..5f9cee8f926 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400007b cv.cmpgtu.h zero,zero,zero + 4: 341080fb cv.cmpgtu.h ra,ra,ra + 8: 3421017b cv.cmpgtu.h sp,sp,sp + c: 3484047b cv.cmpgtu.h s0,s0,s0 + 10: 354a0a7b cv.cmpgtu.h s4,s4,s4 + 14: 35ff8ffb cv.cmpgtu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s new file mode 100644 index 00000000000..0abafa19fb2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.h x0, x0, x0 + cv.cmpgtu.h x1, x1, x1 + cv.cmpgtu.h x2, x2, x2 + cv.cmpgtu.h x8, x8, x8 + cv.cmpgtu.h x20, x20, x20 + cv.cmpgtu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d new file mode 100644 index 00000000000..bf38c6ac41f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-b-fail.s +#error_output: cv-cmpgtu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l new file mode 100644 index 00000000000..8e61b4687f9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s new file mode 100644 index 00000000000..0a443a7a17a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sc.b x32, x32, x32 + cv.cmpgtu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d new file mode 100644 index 00000000000..95ff81315d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400507b cv.cmpgtu.sc.b zero,zero,zero + 4: 3410d0fb cv.cmpgtu.sc.b ra,ra,ra + 8: 3421517b cv.cmpgtu.sc.b sp,sp,sp + c: 3484547b cv.cmpgtu.sc.b s0,s0,s0 + 10: 354a5a7b cv.cmpgtu.sc.b s4,s4,s4 + 14: 35ffdffb cv.cmpgtu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s new file mode 100644 index 00000000000..d8e0fbd37ec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.sc.b x0, x0, x0 + cv.cmpgtu.sc.b x1, x1, x1 + cv.cmpgtu.sc.b x2, x2, x2 + cv.cmpgtu.sc.b x8, x8, x8 + cv.cmpgtu.sc.b x20, x20, x20 + cv.cmpgtu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d new file mode 100644 index 00000000000..25f05665eb3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-h-fail.s +#error_output: cv-cmpgtu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l new file mode 100644 index 00000000000..db82748d2ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s new file mode 100644 index 00000000000..cfe448a8400 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sc.h x32, x32, x32 + cv.cmpgtu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d new file mode 100644 index 00000000000..864876952a7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400407b cv.cmpgtu.sc.h zero,zero,zero + 4: 3410c0fb cv.cmpgtu.sc.h ra,ra,ra + 8: 3421417b cv.cmpgtu.sc.h sp,sp,sp + c: 3484447b cv.cmpgtu.sc.h s0,s0,s0 + 10: 354a4a7b cv.cmpgtu.sc.h s4,s4,s4 + 14: 35ffcffb cv.cmpgtu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s new file mode 100644 index 00000000000..615a7aad62e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.sc.h x0, x0, x0 + cv.cmpgtu.sc.h x1, x1, x1 + cv.cmpgtu.sc.h x2, x2, x2 + cv.cmpgtu.sc.h x8, x8, x8 + cv.cmpgtu.sc.h x20, x20, x20 + cv.cmpgtu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d new file mode 100644 index 00000000000..91de039f54f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-b-fail.s +#error_output: cv-cmpgtu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l new file mode 100644 index 00000000000..7ffc9612810 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpgtu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s new file mode 100644 index 00000000000..860db56bdfd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sci.b x32, x32, 20 + cv.cmpgtu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgtu.sci.b x6, x7, -33 + cv.cmpgtu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d new file mode 100644 index 00000000000..693074d16bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3540707b cv.cmpgtu.sci.b zero,zero,20 + 4: 3540f0fb cv.cmpgtu.sci.b ra,ra,20 + 8: 3541717b cv.cmpgtu.sci.b sp,sp,20 + c: 3544747b cv.cmpgtu.sci.b s0,s0,20 + 10: 354a7a7b cv.cmpgtu.sci.b s4,s4,20 + 14: 354ffffb cv.cmpgtu.sci.b t6,t6,20 + 18: 3603f37b cv.cmpgtu.sci.b t1,t2,-32 + 1c: 3403f37b cv.cmpgtu.sci.b t1,t2,0 + 20: 35f3f37b cv.cmpgtu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s new file mode 100644 index 00000000000..6887053d355 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgtu.sci.b x0, x0, 20 + cv.cmpgtu.sci.b x1, x1, 20 + cv.cmpgtu.sci.b x2, x2, 20 + cv.cmpgtu.sci.b x8, x8, 20 + cv.cmpgtu.sci.b x20, x20, 20 + cv.cmpgtu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpgtu.sci.b x6, x7, -32 + cv.cmpgtu.sci.b x6, x7, 0 + cv.cmpgtu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d new file mode 100644 index 00000000000..c93f5fb564c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-h-fail.s +#error_output: cv-cmpgtu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l new file mode 100644 index 00000000000..27045b34dbd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpgtu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s new file mode 100644 index 00000000000..4976d6c359b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sci.h x32, x32, 20 + cv.cmpgtu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgtu.sci.h x6, x7, -33 + cv.cmpgtu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d new file mode 100644 index 00000000000..a47504eb00f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3540607b cv.cmpgtu.sci.h zero,zero,20 + 4: 3540e0fb cv.cmpgtu.sci.h ra,ra,20 + 8: 3541617b cv.cmpgtu.sci.h sp,sp,20 + c: 3544647b cv.cmpgtu.sci.h s0,s0,20 + 10: 354a6a7b cv.cmpgtu.sci.h s4,s4,20 + 14: 354feffb cv.cmpgtu.sci.h t6,t6,20 + 18: 3603e37b cv.cmpgtu.sci.h t1,t2,-32 + 1c: 3403e37b cv.cmpgtu.sci.h t1,t2,0 + 20: 35f3e37b cv.cmpgtu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s new file mode 100644 index 00000000000..a06e67e7275 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgtu.sci.h x0, x0, 20 + cv.cmpgtu.sci.h x1, x1, 20 + cv.cmpgtu.sci.h x2, x2, 20 + cv.cmpgtu.sci.h x8, x8, 20 + cv.cmpgtu.sci.h x20, x20, 20 + cv.cmpgtu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpgtu.sci.h x6, x7, -32 + cv.cmpgtu.sci.h x6, x7, 0 + cv.cmpgtu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-fail.d b/gas/testsuite/gas/riscv/cv-cmple-b-fail.d new file mode 100644 index 00000000000..56d85e8d1c1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-b-fail.s +#error_output: cv-cmple-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-fail.l b/gas/testsuite/gas/riscv/cv-cmple-b-fail.l new file mode 100644 index 00000000000..c1ce1e95e57 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.b x32,x32,x32' +.*: Error: illegal operands `cv.cmple.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-fail.s b/gas/testsuite/gas/riscv/cv-cmple-b-fail.s new file mode 100644 index 00000000000..50277474e66 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.b x32, x32, x32 + cv.cmple.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-pass.d b/gas/testsuite/gas/riscv/cv-cmple-b-pass.d new file mode 100644 index 00000000000..d3bd65eb5e1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00107b cv.cmple.b zero,zero,zero + 4: 2c1090fb cv.cmple.b ra,ra,ra + 8: 2c21117b cv.cmple.b sp,sp,sp + c: 2c84147b cv.cmple.b s0,s0,s0 + 10: 2d4a1a7b cv.cmple.b s4,s4,s4 + 14: 2dff9ffb cv.cmple.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-pass.s b/gas/testsuite/gas/riscv/cv-cmple-b-pass.s new file mode 100644 index 00000000000..fdf4eb245f9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.b x0, x0, x0 + cv.cmple.b x1, x1, x1 + cv.cmple.b x2, x2, x2 + cv.cmple.b x8, x8, x8 + cv.cmple.b x20, x20, x20 + cv.cmple.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-fail.d b/gas/testsuite/gas/riscv/cv-cmple-h-fail.d new file mode 100644 index 00000000000..80b2e15dd00 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-h-fail.s +#error_output: cv-cmple-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-fail.l b/gas/testsuite/gas/riscv/cv-cmple-h-fail.l new file mode 100644 index 00000000000..90dc4e90829 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.h x32,x32,x32' +.*: Error: illegal operands `cv.cmple.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-fail.s b/gas/testsuite/gas/riscv/cv-cmple-h-fail.s new file mode 100644 index 00000000000..3cee9fff6ef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.h x32, x32, x32 + cv.cmple.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-pass.d b/gas/testsuite/gas/riscv/cv-cmple-h-pass.d new file mode 100644 index 00000000000..01a893848b9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00007b cv.cmple.h zero,zero,zero + 4: 2c1080fb cv.cmple.h ra,ra,ra + 8: 2c21017b cv.cmple.h sp,sp,sp + c: 2c84047b cv.cmple.h s0,s0,s0 + 10: 2d4a0a7b cv.cmple.h s4,s4,s4 + 14: 2dff8ffb cv.cmple.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-pass.s b/gas/testsuite/gas/riscv/cv-cmple-h-pass.s new file mode 100644 index 00000000000..35c2c462cc7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.h x0, x0, x0 + cv.cmple.h x1, x1, x1 + cv.cmple.h x2, x2, x2 + cv.cmple.h x8, x8, x8 + cv.cmple.h x20, x20, x20 + cv.cmple.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d new file mode 100644 index 00000000000..02fe239e40b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-b-fail.s +#error_output: cv-cmple-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l new file mode 100644 index 00000000000..74b287452ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmple.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s new file mode 100644 index 00000000000..32deb90d22d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.sc.b x32, x32, x32 + cv.cmple.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d new file mode 100644 index 00000000000..2854d872ba1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00507b cv.cmple.sc.b zero,zero,zero + 4: 2c10d0fb cv.cmple.sc.b ra,ra,ra + 8: 2c21517b cv.cmple.sc.b sp,sp,sp + c: 2c84547b cv.cmple.sc.b s0,s0,s0 + 10: 2d4a5a7b cv.cmple.sc.b s4,s4,s4 + 14: 2dffdffb cv.cmple.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s new file mode 100644 index 00000000000..45b55184e03 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.sc.b x0, x0, x0 + cv.cmple.sc.b x1, x1, x1 + cv.cmple.sc.b x2, x2, x2 + cv.cmple.sc.b x8, x8, x8 + cv.cmple.sc.b x20, x20, x20 + cv.cmple.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d new file mode 100644 index 00000000000..1a7744878be --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-h-fail.s +#error_output: cv-cmple-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l new file mode 100644 index 00000000000..781dcb28e9a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmple.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s new file mode 100644 index 00000000000..8a480a2c4e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.sc.h x32, x32, x32 + cv.cmple.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d new file mode 100644 index 00000000000..645fc28f6e0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00407b cv.cmple.sc.h zero,zero,zero + 4: 2c10c0fb cv.cmple.sc.h ra,ra,ra + 8: 2c21417b cv.cmple.sc.h sp,sp,sp + c: 2c84447b cv.cmple.sc.h s0,s0,s0 + 10: 2d4a4a7b cv.cmple.sc.h s4,s4,s4 + 14: 2dffcffb cv.cmple.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s new file mode 100644 index 00000000000..719bd8652bf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.sc.h x0, x0, x0 + cv.cmple.sc.h x1, x1, x1 + cv.cmple.sc.h x2, x2, x2 + cv.cmple.sc.h x8, x8, x8 + cv.cmple.sc.h x20, x20, x20 + cv.cmple.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d new file mode 100644 index 00000000000..9b710343235 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-b-fail.s +#error_output: cv-cmple-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l new file mode 100644 index 00000000000..6fbc895b3ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmple.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s new file mode 100644 index 00000000000..7b461b9ce78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmple.sci.b x32, x32, 20 + cv.cmple.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmple.sci.b x6, x7, -33 + cv.cmple.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d new file mode 100644 index 00000000000..8da8be19c14 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2d40707b cv.cmple.sci.b zero,zero,20 + 4: 2d40f0fb cv.cmple.sci.b ra,ra,20 + 8: 2d41717b cv.cmple.sci.b sp,sp,20 + c: 2d44747b cv.cmple.sci.b s0,s0,20 + 10: 2d4a7a7b cv.cmple.sci.b s4,s4,20 + 14: 2d4ffffb cv.cmple.sci.b t6,t6,20 + 18: 2e03f37b cv.cmple.sci.b t1,t2,-32 + 1c: 2c03f37b cv.cmple.sci.b t1,t2,0 + 20: 2df3f37b cv.cmple.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s new file mode 100644 index 00000000000..8db8a1e3568 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmple.sci.b x0, x0, 20 + cv.cmple.sci.b x1, x1, 20 + cv.cmple.sci.b x2, x2, 20 + cv.cmple.sci.b x8, x8, 20 + cv.cmple.sci.b x20, x20, 20 + cv.cmple.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmple.sci.b x6, x7, -32 + cv.cmple.sci.b x6, x7, 0 + cv.cmple.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d new file mode 100644 index 00000000000..587fab8b388 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-h-fail.s +#error_output: cv-cmple-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l new file mode 100644 index 00000000000..ccbf473dbd3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmple.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s new file mode 100644 index 00000000000..7e8beb8dfae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmple.sci.h x32, x32, 20 + cv.cmple.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmple.sci.h x6, x7, -33 + cv.cmple.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d new file mode 100644 index 00000000000..d4df48d0384 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2d40607b cv.cmple.sci.h zero,zero,20 + 4: 2d40e0fb cv.cmple.sci.h ra,ra,20 + 8: 2d41617b cv.cmple.sci.h sp,sp,20 + c: 2d44647b cv.cmple.sci.h s0,s0,20 + 10: 2d4a6a7b cv.cmple.sci.h s4,s4,20 + 14: 2d4feffb cv.cmple.sci.h t6,t6,20 + 18: 2e03e37b cv.cmple.sci.h t1,t2,-32 + 1c: 2c03e37b cv.cmple.sci.h t1,t2,0 + 20: 2df3e37b cv.cmple.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s new file mode 100644 index 00000000000..83031daecf2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmple.sci.h x0, x0, 20 + cv.cmple.sci.h x1, x1, 20 + cv.cmple.sci.h x2, x2, 20 + cv.cmple.sci.h x8, x8, 20 + cv.cmple.sci.h x20, x20, 20 + cv.cmple.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmple.sci.h x6, x7, -32 + cv.cmple.sci.h x6, x7, 0 + cv.cmple.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d new file mode 100644 index 00000000000..e9b24cf6494 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-b-fail.s +#error_output: cv-cmpleu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l new file mode 100644 index 00000000000..906bb044ca7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s new file mode 100644 index 00000000000..4635be74d74 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.b x32, x32, x32 + cv.cmpleu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d new file mode 100644 index 00000000000..f00d38f3b5d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00107b cv.cmpleu.b zero,zero,zero + 4: 4c1090fb cv.cmpleu.b ra,ra,ra + 8: 4c21117b cv.cmpleu.b sp,sp,sp + c: 4c84147b cv.cmpleu.b s0,s0,s0 + 10: 4d4a1a7b cv.cmpleu.b s4,s4,s4 + 14: 4dff9ffb cv.cmpleu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s new file mode 100644 index 00000000000..7762ca7ab7d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.b x0, x0, x0 + cv.cmpleu.b x1, x1, x1 + cv.cmpleu.b x2, x2, x2 + cv.cmpleu.b x8, x8, x8 + cv.cmpleu.b x20, x20, x20 + cv.cmpleu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d new file mode 100644 index 00000000000..7dcae701bfe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-h-fail.s +#error_output: cv-cmpleu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l new file mode 100644 index 00000000000..1bcab7179eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s new file mode 100644 index 00000000000..2de8808711a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.h x32, x32, x32 + cv.cmpleu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d new file mode 100644 index 00000000000..7cc9870f941 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00007b cv.cmpleu.h zero,zero,zero + 4: 4c1080fb cv.cmpleu.h ra,ra,ra + 8: 4c21017b cv.cmpleu.h sp,sp,sp + c: 4c84047b cv.cmpleu.h s0,s0,s0 + 10: 4d4a0a7b cv.cmpleu.h s4,s4,s4 + 14: 4dff8ffb cv.cmpleu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s new file mode 100644 index 00000000000..3b2ac7beaed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.h x0, x0, x0 + cv.cmpleu.h x1, x1, x1 + cv.cmpleu.h x2, x2, x2 + cv.cmpleu.h x8, x8, x8 + cv.cmpleu.h x20, x20, x20 + cv.cmpleu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d new file mode 100644 index 00000000000..cbf416a1692 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-b-fail.s +#error_output: cv-cmpleu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l new file mode 100644 index 00000000000..5fde1fae238 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s new file mode 100644 index 00000000000..5cd69fd76a4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.sc.b x32, x32, x32 + cv.cmpleu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d new file mode 100644 index 00000000000..e03b38d3659 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00507b cv.cmpleu.sc.b zero,zero,zero + 4: 4c10d0fb cv.cmpleu.sc.b ra,ra,ra + 8: 4c21517b cv.cmpleu.sc.b sp,sp,sp + c: 4c84547b cv.cmpleu.sc.b s0,s0,s0 + 10: 4d4a5a7b cv.cmpleu.sc.b s4,s4,s4 + 14: 4dffdffb cv.cmpleu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s new file mode 100644 index 00000000000..5a99d7b127c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.sc.b x0, x0, x0 + cv.cmpleu.sc.b x1, x1, x1 + cv.cmpleu.sc.b x2, x2, x2 + cv.cmpleu.sc.b x8, x8, x8 + cv.cmpleu.sc.b x20, x20, x20 + cv.cmpleu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d new file mode 100644 index 00000000000..71f51670151 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-h-fail.s +#error_output: cv-cmpleu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l new file mode 100644 index 00000000000..11438240a92 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s new file mode 100644 index 00000000000..632933d7e63 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.sc.h x32, x32, x32 + cv.cmpleu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d new file mode 100644 index 00000000000..96789b9cc85 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00407b cv.cmpleu.sc.h zero,zero,zero + 4: 4c10c0fb cv.cmpleu.sc.h ra,ra,ra + 8: 4c21417b cv.cmpleu.sc.h sp,sp,sp + c: 4c84447b cv.cmpleu.sc.h s0,s0,s0 + 10: 4d4a4a7b cv.cmpleu.sc.h s4,s4,s4 + 14: 4dffcffb cv.cmpleu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s new file mode 100644 index 00000000000..762af31e6e2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.sc.h x0, x0, x0 + cv.cmpleu.sc.h x1, x1, x1 + cv.cmpleu.sc.h x2, x2, x2 + cv.cmpleu.sc.h x8, x8, x8 + cv.cmpleu.sc.h x20, x20, x20 + cv.cmpleu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d new file mode 100644 index 00000000000..aa9257190e0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-b-fail.s +#error_output: cv-cmpleu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l new file mode 100644 index 00000000000..e12d078738b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpleu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s new file mode 100644 index 00000000000..f8ad26f86b0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpleu.sci.b x32, x32, 20 + cv.cmpleu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpleu.sci.b x6, x7, -33 + cv.cmpleu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d new file mode 100644 index 00000000000..13b3cc33236 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4d40707b cv.cmpleu.sci.b zero,zero,20 + 4: 4d40f0fb cv.cmpleu.sci.b ra,ra,20 + 8: 4d41717b cv.cmpleu.sci.b sp,sp,20 + c: 4d44747b cv.cmpleu.sci.b s0,s0,20 + 10: 4d4a7a7b cv.cmpleu.sci.b s4,s4,20 + 14: 4d4ffffb cv.cmpleu.sci.b t6,t6,20 + 18: 4e03f37b cv.cmpleu.sci.b t1,t2,-32 + 1c: 4c03f37b cv.cmpleu.sci.b t1,t2,0 + 20: 4df3f37b cv.cmpleu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s new file mode 100644 index 00000000000..11ed9420585 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpleu.sci.b x0, x0, 20 + cv.cmpleu.sci.b x1, x1, 20 + cv.cmpleu.sci.b x2, x2, 20 + cv.cmpleu.sci.b x8, x8, 20 + cv.cmpleu.sci.b x20, x20, 20 + cv.cmpleu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpleu.sci.b x6, x7, -32 + cv.cmpleu.sci.b x6, x7, 0 + cv.cmpleu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d new file mode 100644 index 00000000000..13b2dd5e2d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-h-fail.s +#error_output: cv-cmpleu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l new file mode 100644 index 00000000000..a7057dff130 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpleu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s new file mode 100644 index 00000000000..fa1467910fb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpleu.sci.h x32, x32, 20 + cv.cmpleu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpleu.sci.h x6, x7, -33 + cv.cmpleu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d new file mode 100644 index 00000000000..b8f0bb62b1b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4d40607b cv.cmpleu.sci.h zero,zero,20 + 4: 4d40e0fb cv.cmpleu.sci.h ra,ra,20 + 8: 4d41617b cv.cmpleu.sci.h sp,sp,20 + c: 4d44647b cv.cmpleu.sci.h s0,s0,20 + 10: 4d4a6a7b cv.cmpleu.sci.h s4,s4,20 + 14: 4d4feffb cv.cmpleu.sci.h t6,t6,20 + 18: 4e03e37b cv.cmpleu.sci.h t1,t2,-32 + 1c: 4c03e37b cv.cmpleu.sci.h t1,t2,0 + 20: 4df3e37b cv.cmpleu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s new file mode 100644 index 00000000000..cc278ce2ccd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpleu.sci.h x0, x0, 20 + cv.cmpleu.sci.h x1, x1, 20 + cv.cmpleu.sci.h x2, x2, 20 + cv.cmpleu.sci.h x8, x8, 20 + cv.cmpleu.sci.h x20, x20, 20 + cv.cmpleu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpleu.sci.h x6, x7, -32 + cv.cmpleu.sci.h x6, x7, 0 + cv.cmpleu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.d new file mode 100644 index 00000000000..fdfaa818019 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-b-fail.s +#error_output: cv-cmplt-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.l new file mode 100644 index 00000000000..0f98b08b92e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.b x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.s new file mode 100644 index 00000000000..a9d537f3a0e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.b x32, x32, x32 + cv.cmplt.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.d new file mode 100644 index 00000000000..685a3494f5a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400107b cv.cmplt.b zero,zero,zero + 4: 241090fb cv.cmplt.b ra,ra,ra + 8: 2421117b cv.cmplt.b sp,sp,sp + c: 2484147b cv.cmplt.b s0,s0,s0 + 10: 254a1a7b cv.cmplt.b s4,s4,s4 + 14: 25ff9ffb cv.cmplt.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.s new file mode 100644 index 00000000000..9f45e2e18c0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.b x0, x0, x0 + cv.cmplt.b x1, x1, x1 + cv.cmplt.b x2, x2, x2 + cv.cmplt.b x8, x8, x8 + cv.cmplt.b x20, x20, x20 + cv.cmplt.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.d new file mode 100644 index 00000000000..83fb4c1cdc2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-h-fail.s +#error_output: cv-cmplt-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.l new file mode 100644 index 00000000000..b2c5298e1e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.h x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.s new file mode 100644 index 00000000000..0726a8edb5d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.h x32, x32, x32 + cv.cmplt.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.d new file mode 100644 index 00000000000..d67387b0c21 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400007b cv.cmplt.h zero,zero,zero + 4: 241080fb cv.cmplt.h ra,ra,ra + 8: 2421017b cv.cmplt.h sp,sp,sp + c: 2484047b cv.cmplt.h s0,s0,s0 + 10: 254a0a7b cv.cmplt.h s4,s4,s4 + 14: 25ff8ffb cv.cmplt.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.s new file mode 100644 index 00000000000..1c7cdac3ada --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.h x0, x0, x0 + cv.cmplt.h x1, x1, x1 + cv.cmplt.h x2, x2, x2 + cv.cmplt.h x8, x8, x8 + cv.cmplt.h x20, x20, x20 + cv.cmplt.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d new file mode 100644 index 00000000000..68a3ffcec33 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-b-fail.s +#error_output: cv-cmplt-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l new file mode 100644 index 00000000000..bc8340f218b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s new file mode 100644 index 00000000000..625d424590c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.sc.b x32, x32, x32 + cv.cmplt.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d new file mode 100644 index 00000000000..52b065592f8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400507b cv.cmplt.sc.b zero,zero,zero + 4: 2410d0fb cv.cmplt.sc.b ra,ra,ra + 8: 2421517b cv.cmplt.sc.b sp,sp,sp + c: 2484547b cv.cmplt.sc.b s0,s0,s0 + 10: 254a5a7b cv.cmplt.sc.b s4,s4,s4 + 14: 25ffdffb cv.cmplt.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s new file mode 100644 index 00000000000..f1220c4781c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.sc.b x0, x0, x0 + cv.cmplt.sc.b x1, x1, x1 + cv.cmplt.sc.b x2, x2, x2 + cv.cmplt.sc.b x8, x8, x8 + cv.cmplt.sc.b x20, x20, x20 + cv.cmplt.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d new file mode 100644 index 00000000000..0e3b1340008 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-h-fail.s +#error_output: cv-cmplt-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l new file mode 100644 index 00000000000..9d7c9e05479 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s new file mode 100644 index 00000000000..ae4a89cbb5e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.sc.h x32, x32, x32 + cv.cmplt.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d new file mode 100644 index 00000000000..1883893c0db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400407b cv.cmplt.sc.h zero,zero,zero + 4: 2410c0fb cv.cmplt.sc.h ra,ra,ra + 8: 2421417b cv.cmplt.sc.h sp,sp,sp + c: 2484447b cv.cmplt.sc.h s0,s0,s0 + 10: 254a4a7b cv.cmplt.sc.h s4,s4,s4 + 14: 25ffcffb cv.cmplt.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s new file mode 100644 index 00000000000..2955c8393af --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.sc.h x0, x0, x0 + cv.cmplt.sc.h x1, x1, x1 + cv.cmplt.sc.h x2, x2, x2 + cv.cmplt.sc.h x8, x8, x8 + cv.cmplt.sc.h x20, x20, x20 + cv.cmplt.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d new file mode 100644 index 00000000000..2f4607e4c1c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-b-fail.s +#error_output: cv-cmplt-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l new file mode 100644 index 00000000000..2d5cdad6b80 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmplt.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s new file mode 100644 index 00000000000..95ffaa84598 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmplt.sci.b x32, x32, 20 + cv.cmplt.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmplt.sci.b x6, x7, -33 + cv.cmplt.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d new file mode 100644 index 00000000000..673b7780646 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2540707b cv.cmplt.sci.b zero,zero,20 + 4: 2540f0fb cv.cmplt.sci.b ra,ra,20 + 8: 2541717b cv.cmplt.sci.b sp,sp,20 + c: 2544747b cv.cmplt.sci.b s0,s0,20 + 10: 254a7a7b cv.cmplt.sci.b s4,s4,20 + 14: 254ffffb cv.cmplt.sci.b t6,t6,20 + 18: 2603f37b cv.cmplt.sci.b t1,t2,-32 + 1c: 2403f37b cv.cmplt.sci.b t1,t2,0 + 20: 25f3f37b cv.cmplt.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s new file mode 100644 index 00000000000..f6037aca241 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmplt.sci.b x0, x0, 20 + cv.cmplt.sci.b x1, x1, 20 + cv.cmplt.sci.b x2, x2, 20 + cv.cmplt.sci.b x8, x8, 20 + cv.cmplt.sci.b x20, x20, 20 + cv.cmplt.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmplt.sci.b x6, x7, -32 + cv.cmplt.sci.b x6, x7, 0 + cv.cmplt.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d new file mode 100644 index 00000000000..8ee7a0d9f97 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-h-fail.s +#error_output: cv-cmplt-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l new file mode 100644 index 00000000000..6be7bcaf461 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmplt.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s new file mode 100644 index 00000000000..8094f165b01 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmplt.sci.h x32, x32, 20 + cv.cmplt.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmplt.sci.h x6, x7, -33 + cv.cmplt.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d new file mode 100644 index 00000000000..63c9702c8e7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2540607b cv.cmplt.sci.h zero,zero,20 + 4: 2540e0fb cv.cmplt.sci.h ra,ra,20 + 8: 2541617b cv.cmplt.sci.h sp,sp,20 + c: 2544647b cv.cmplt.sci.h s0,s0,20 + 10: 254a6a7b cv.cmplt.sci.h s4,s4,20 + 14: 254feffb cv.cmplt.sci.h t6,t6,20 + 18: 2603e37b cv.cmplt.sci.h t1,t2,-32 + 1c: 2403e37b cv.cmplt.sci.h t1,t2,0 + 20: 25f3e37b cv.cmplt.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s new file mode 100644 index 00000000000..0b83b1ba472 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmplt.sci.h x0, x0, 20 + cv.cmplt.sci.h x1, x1, 20 + cv.cmplt.sci.h x2, x2, 20 + cv.cmplt.sci.h x8, x8, 20 + cv.cmplt.sci.h x20, x20, 20 + cv.cmplt.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmplt.sci.h x6, x7, -32 + cv.cmplt.sci.h x6, x7, 0 + cv.cmplt.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d new file mode 100644 index 00000000000..673b52e1ae9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-b-fail.s +#error_output: cv-cmpltu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l new file mode 100644 index 00000000000..199b24d2c5e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s new file mode 100644 index 00000000000..5e1a3a8ea12 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.b x32, x32, x32 + cv.cmpltu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d new file mode 100644 index 00000000000..e21cea508aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400107b cv.cmpltu.b zero,zero,zero + 4: 441090fb cv.cmpltu.b ra,ra,ra + 8: 4421117b cv.cmpltu.b sp,sp,sp + c: 4484147b cv.cmpltu.b s0,s0,s0 + 10: 454a1a7b cv.cmpltu.b s4,s4,s4 + 14: 45ff9ffb cv.cmpltu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s new file mode 100644 index 00000000000..0b0ee26947c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.b x0, x0, x0 + cv.cmpltu.b x1, x1, x1 + cv.cmpltu.b x2, x2, x2 + cv.cmpltu.b x8, x8, x8 + cv.cmpltu.b x20, x20, x20 + cv.cmpltu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d new file mode 100644 index 00000000000..078b893ccac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-h-fail.s +#error_output: cv-cmpltu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l new file mode 100644 index 00000000000..7ec17d16181 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s new file mode 100644 index 00000000000..9aa13b92603 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.h x32, x32, x32 + cv.cmpltu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d new file mode 100644 index 00000000000..28fe225830c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400007b cv.cmpltu.h zero,zero,zero + 4: 441080fb cv.cmpltu.h ra,ra,ra + 8: 4421017b cv.cmpltu.h sp,sp,sp + c: 4484047b cv.cmpltu.h s0,s0,s0 + 10: 454a0a7b cv.cmpltu.h s4,s4,s4 + 14: 45ff8ffb cv.cmpltu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s new file mode 100644 index 00000000000..c39a583ba73 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.h x0, x0, x0 + cv.cmpltu.h x1, x1, x1 + cv.cmpltu.h x2, x2, x2 + cv.cmpltu.h x8, x8, x8 + cv.cmpltu.h x20, x20, x20 + cv.cmpltu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d new file mode 100644 index 00000000000..03c2f74548f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-b-fail.s +#error_output: cv-cmpltu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l new file mode 100644 index 00000000000..0b4c9992e7f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s new file mode 100644 index 00000000000..15ec07644d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.sc.b x32, x32, x32 + cv.cmpltu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d new file mode 100644 index 00000000000..25a96d77a0b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400507b cv.cmpltu.sc.b zero,zero,zero + 4: 4410d0fb cv.cmpltu.sc.b ra,ra,ra + 8: 4421517b cv.cmpltu.sc.b sp,sp,sp + c: 4484547b cv.cmpltu.sc.b s0,s0,s0 + 10: 454a5a7b cv.cmpltu.sc.b s4,s4,s4 + 14: 45ffdffb cv.cmpltu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s new file mode 100644 index 00000000000..65383b469ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.sc.b x0, x0, x0 + cv.cmpltu.sc.b x1, x1, x1 + cv.cmpltu.sc.b x2, x2, x2 + cv.cmpltu.sc.b x8, x8, x8 + cv.cmpltu.sc.b x20, x20, x20 + cv.cmpltu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d new file mode 100644 index 00000000000..d15370610ca --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-h-fail.s +#error_output: cv-cmpltu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l new file mode 100644 index 00000000000..aa73e2dd5e1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s new file mode 100644 index 00000000000..0cd45cc2ca5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.sc.h x32, x32, x32 + cv.cmpltu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d new file mode 100644 index 00000000000..ee438e61d18 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400407b cv.cmpltu.sc.h zero,zero,zero + 4: 4410c0fb cv.cmpltu.sc.h ra,ra,ra + 8: 4421417b cv.cmpltu.sc.h sp,sp,sp + c: 4484447b cv.cmpltu.sc.h s0,s0,s0 + 10: 454a4a7b cv.cmpltu.sc.h s4,s4,s4 + 14: 45ffcffb cv.cmpltu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s new file mode 100644 index 00000000000..6dc3ad7e847 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.sc.h x0, x0, x0 + cv.cmpltu.sc.h x1, x1, x1 + cv.cmpltu.sc.h x2, x2, x2 + cv.cmpltu.sc.h x8, x8, x8 + cv.cmpltu.sc.h x20, x20, x20 + cv.cmpltu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d new file mode 100644 index 00000000000..69de4b22b3d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-b-fail.s +#error_output: cv-cmpltu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l new file mode 100644 index 00000000000..dd6781ceebd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpltu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s new file mode 100644 index 00000000000..d59d4d20c96 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpltu.sci.b x32, x32, 20 + cv.cmpltu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpltu.sci.b x6, x7, -33 + cv.cmpltu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d new file mode 100644 index 00000000000..4af6a14e6d2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4540707b cv.cmpltu.sci.b zero,zero,20 + 4: 4540f0fb cv.cmpltu.sci.b ra,ra,20 + 8: 4541717b cv.cmpltu.sci.b sp,sp,20 + c: 4544747b cv.cmpltu.sci.b s0,s0,20 + 10: 454a7a7b cv.cmpltu.sci.b s4,s4,20 + 14: 454ffffb cv.cmpltu.sci.b t6,t6,20 + 18: 4603f37b cv.cmpltu.sci.b t1,t2,-32 + 1c: 4403f37b cv.cmpltu.sci.b t1,t2,0 + 20: 45f3f37b cv.cmpltu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s new file mode 100644 index 00000000000..cdcb11f4a1e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpltu.sci.b x0, x0, 20 + cv.cmpltu.sci.b x1, x1, 20 + cv.cmpltu.sci.b x2, x2, 20 + cv.cmpltu.sci.b x8, x8, 20 + cv.cmpltu.sci.b x20, x20, 20 + cv.cmpltu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpltu.sci.b x6, x7, -32 + cv.cmpltu.sci.b x6, x7, 0 + cv.cmpltu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d new file mode 100644 index 00000000000..d16856b0510 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-h-fail.s +#error_output: cv-cmpltu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l new file mode 100644 index 00000000000..c3d7101fa1b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpltu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s new file mode 100644 index 00000000000..c6e8560b073 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpltu.sci.h x32, x32, 20 + cv.cmpltu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpltu.sci.h x6, x7, -33 + cv.cmpltu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d new file mode 100644 index 00000000000..6fd35a350c4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4540607b cv.cmpltu.sci.h zero,zero,20 + 4: 4540e0fb cv.cmpltu.sci.h ra,ra,20 + 8: 4541617b cv.cmpltu.sci.h sp,sp,20 + c: 4544647b cv.cmpltu.sci.h s0,s0,20 + 10: 454a6a7b cv.cmpltu.sci.h s4,s4,20 + 14: 454feffb cv.cmpltu.sci.h t6,t6,20 + 18: 4603e37b cv.cmpltu.sci.h t1,t2,-32 + 1c: 4403e37b cv.cmpltu.sci.h t1,t2,0 + 20: 45f3e37b cv.cmpltu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s new file mode 100644 index 00000000000..12fea0cca2b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpltu.sci.h x0, x0, 20 + cv.cmpltu.sci.h x1, x1, 20 + cv.cmpltu.sci.h x2, x2, 20 + cv.cmpltu.sci.h x8, x8, 20 + cv.cmpltu.sci.h x20, x20, 20 + cv.cmpltu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpltu.sci.h x6, x7, -32 + cv.cmpltu.sci.h x6, x7, 0 + cv.cmpltu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.d new file mode 100644 index 00000000000..fd829686b6d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-b-fail.s +#error_output: cv-cmpne-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.l new file mode 100644 index 00000000000..17dd8aad0d5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.s new file mode 100644 index 00000000000..233113481ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.b x32, x32, x32 + cv.cmpne.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.d new file mode 100644 index 00000000000..932a3c6d443 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00107b cv.cmpne.b zero,zero,zero + 4: 0c1090fb cv.cmpne.b ra,ra,ra + 8: 0c21117b cv.cmpne.b sp,sp,sp + c: 0c84147b cv.cmpne.b s0,s0,s0 + 10: 0d4a1a7b cv.cmpne.b s4,s4,s4 + 14: 0dff9ffb cv.cmpne.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.s new file mode 100644 index 00000000000..1aa74bbcaa3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.b x0, x0, x0 + cv.cmpne.b x1, x1, x1 + cv.cmpne.b x2, x2, x2 + cv.cmpne.b x8, x8, x8 + cv.cmpne.b x20, x20, x20 + cv.cmpne.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.d new file mode 100644 index 00000000000..6a1411dc318 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-h-fail.s +#error_output: cv-cmpne-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.l new file mode 100644 index 00000000000..0b53e8f593c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.s new file mode 100644 index 00000000000..e0713463668 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.h x32, x32, x32 + cv.cmpne.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.d new file mode 100644 index 00000000000..93f92d44086 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00007b cv.cmpne.h zero,zero,zero + 4: 0c1080fb cv.cmpne.h ra,ra,ra + 8: 0c21017b cv.cmpne.h sp,sp,sp + c: 0c84047b cv.cmpne.h s0,s0,s0 + 10: 0d4a0a7b cv.cmpne.h s4,s4,s4 + 14: 0dff8ffb cv.cmpne.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.s new file mode 100644 index 00000000000..19fbad0f6c1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.h x0, x0, x0 + cv.cmpne.h x1, x1, x1 + cv.cmpne.h x2, x2, x2 + cv.cmpne.h x8, x8, x8 + cv.cmpne.h x20, x20, x20 + cv.cmpne.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d new file mode 100644 index 00000000000..656a7639808 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-b-fail.s +#error_output: cv-cmpne-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l new file mode 100644 index 00000000000..24afd896558 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s new file mode 100644 index 00000000000..90d11e545a7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.sc.b x32, x32, x32 + cv.cmpne.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d new file mode 100644 index 00000000000..792f8021242 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00507b cv.cmpne.sc.b zero,zero,zero + 4: 0c10d0fb cv.cmpne.sc.b ra,ra,ra + 8: 0c21517b cv.cmpne.sc.b sp,sp,sp + c: 0c84547b cv.cmpne.sc.b s0,s0,s0 + 10: 0d4a5a7b cv.cmpne.sc.b s4,s4,s4 + 14: 0dffdffb cv.cmpne.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s new file mode 100644 index 00000000000..576e327fbc1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.sc.b x0, x0, x0 + cv.cmpne.sc.b x1, x1, x1 + cv.cmpne.sc.b x2, x2, x2 + cv.cmpne.sc.b x8, x8, x8 + cv.cmpne.sc.b x20, x20, x20 + cv.cmpne.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d new file mode 100644 index 00000000000..af3bfdb5ed7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-h-fail.s +#error_output: cv-cmpne-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l new file mode 100644 index 00000000000..34854ac8eee --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s new file mode 100644 index 00000000000..3a14c6acb87 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.sc.h x32, x32, x32 + cv.cmpne.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d new file mode 100644 index 00000000000..83e59b71401 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00407b cv.cmpne.sc.h zero,zero,zero + 4: 0c10c0fb cv.cmpne.sc.h ra,ra,ra + 8: 0c21417b cv.cmpne.sc.h sp,sp,sp + c: 0c84447b cv.cmpne.sc.h s0,s0,s0 + 10: 0d4a4a7b cv.cmpne.sc.h s4,s4,s4 + 14: 0dffcffb cv.cmpne.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s new file mode 100644 index 00000000000..25f87fe9626 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.sc.h x0, x0, x0 + cv.cmpne.sc.h x1, x1, x1 + cv.cmpne.sc.h x2, x2, x2 + cv.cmpne.sc.h x8, x8, x8 + cv.cmpne.sc.h x20, x20, x20 + cv.cmpne.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d new file mode 100644 index 00000000000..cbc805d353b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-b-fail.s +#error_output: cv-cmpne-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l new file mode 100644 index 00000000000..9ad1b198f54 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpne.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s new file mode 100644 index 00000000000..a1b8fe168e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpne.sci.b x32, x32, 20 + cv.cmpne.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpne.sci.b x6, x7, -33 + cv.cmpne.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d new file mode 100644 index 00000000000..1a8b40367dd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0d40707b cv.cmpne.sci.b zero,zero,20 + 4: 0d40f0fb cv.cmpne.sci.b ra,ra,20 + 8: 0d41717b cv.cmpne.sci.b sp,sp,20 + c: 0d44747b cv.cmpne.sci.b s0,s0,20 + 10: 0d4a7a7b cv.cmpne.sci.b s4,s4,20 + 14: 0d4ffffb cv.cmpne.sci.b t6,t6,20 + 18: 0e03f37b cv.cmpne.sci.b t1,t2,-32 + 1c: 0c03f37b cv.cmpne.sci.b t1,t2,0 + 20: 0df3f37b cv.cmpne.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s new file mode 100644 index 00000000000..301a3a024dc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpne.sci.b x0, x0, 20 + cv.cmpne.sci.b x1, x1, 20 + cv.cmpne.sci.b x2, x2, 20 + cv.cmpne.sci.b x8, x8, 20 + cv.cmpne.sci.b x20, x20, 20 + cv.cmpne.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpne.sci.b x6, x7, -32 + cv.cmpne.sci.b x6, x7, 0 + cv.cmpne.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d new file mode 100644 index 00000000000..95e0bb94b43 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-h-fail.s +#error_output: cv-cmpne-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l new file mode 100644 index 00000000000..eba861843c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpne.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s new file mode 100644 index 00000000000..6a1f2f7dd6f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpne.sci.h x32, x32, 20 + cv.cmpne.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpne.sci.h x6, x7, -33 + cv.cmpne.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d new file mode 100644 index 00000000000..f5ed539ffa5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0d40607b cv.cmpne.sci.h zero,zero,20 + 4: 0d40e0fb cv.cmpne.sci.h ra,ra,20 + 8: 0d41617b cv.cmpne.sci.h sp,sp,20 + c: 0d44647b cv.cmpne.sci.h s0,s0,20 + 10: 0d4a6a7b cv.cmpne.sci.h s4,s4,20 + 14: 0d4feffb cv.cmpne.sci.h t6,t6,20 + 18: 0e03e37b cv.cmpne.sci.h t1,t2,-32 + 1c: 0c03e37b cv.cmpne.sci.h t1,t2,0 + 20: 0df3e37b cv.cmpne.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s new file mode 100644 index 00000000000..984ded1e090 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpne.sci.h x0, x0, 20 + cv.cmpne.sci.h x1, x1, 20 + cv.cmpne.sci.h x2, x2, 20 + cv.cmpne.sci.h x8, x8, 20 + cv.cmpne.sci.h x20, x20, 20 + cv.cmpne.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpne.sci.h x6, x7, -32 + cv.cmpne.sci.h x6, x7, 0 + cv.cmpne.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-fail.d b/gas/testsuite/gas/riscv/cv-cplxconj-fail.d new file mode 100644 index 00000000000..89d8b031d1e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxconj-fail.s +#error_output: cv-cplxconj-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-fail.l b/gas/testsuite/gas/riscv/cv-cplxconj-fail.l new file mode 100644 index 00000000000..ed0844fae23 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxconj x32,x32' +.*: Error: illegal operands `cv.cplxconj x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-fail.s b/gas/testsuite/gas/riscv/cv-cplxconj-fail.s new file mode 100644 index 00000000000..04e3716485b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxconj x32, x32 + cv.cplxconj x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-pass.d b/gas/testsuite/gas/riscv/cv-cplxconj-pass.d new file mode 100644 index 00000000000..591bccf5fa0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxconj-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5c00007b cv.cplxconj zero,zero + 4: 5c0080fb cv.cplxconj ra,ra + 8: 5c01017b cv.cplxconj sp,sp + c: 5c04047b cv.cplxconj s0,s0 + 10: 5c0a0a7b cv.cplxconj s4,s4 + 14: 5c0f8ffb cv.cplxconj t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-pass.s b/gas/testsuite/gas/riscv/cv-cplxconj-pass.s new file mode 100644 index 00000000000..36b163b8d08 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxconj x0, x0 + cv.cplxconj x1, x1 + cv.cplxconj x2, x2 + cv.cplxconj x8, x8 + cv.cplxconj x20, x20 + cv.cplxconj x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d new file mode 100644 index 00000000000..9264b535cb7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div2-fail.s +#error_output: cv-cplxmul-i-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l new file mode 100644 index 00000000000..9af5157824d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i.div2 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s new file mode 100644 index 00000000000..d6fa16ff4f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i.div2 x32, x32, x32 + cv.cplxmul.i.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d new file mode 100644 index 00000000000..954d13ab76d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600207b cv.cplxmul.i.div2 zero,zero,zero + 4: 5610a0fb cv.cplxmul.i.div2 ra,ra,ra + 8: 5621217b cv.cplxmul.i.div2 sp,sp,sp + c: 5684247b cv.cplxmul.i.div2 s0,s0,s0 + 10: 574a2a7b cv.cplxmul.i.div2 s4,s4,s4 + 14: 57ffaffb cv.cplxmul.i.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s new file mode 100644 index 00000000000..4eb89da921c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i.div2 x0, x0, x0 + cv.cplxmul.i.div2 x1, x1, x1 + cv.cplxmul.i.div2 x2, x2, x2 + cv.cplxmul.i.div2 x8, x8, x8 + cv.cplxmul.i.div2 x20, x20, x20 + cv.cplxmul.i.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d new file mode 100644 index 00000000000..afe960bd631 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div4-fail.s +#error_output: cv-cplxmul-i-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l new file mode 100644 index 00000000000..c3efbe053eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i.div4 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s new file mode 100644 index 00000000000..e5ea2fc45fd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i.div4 x32, x32, x32 + cv.cplxmul.i.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d new file mode 100644 index 00000000000..74ab02dd3ef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600407b cv.cplxmul.i.div4 zero,zero,zero + 4: 5610c0fb cv.cplxmul.i.div4 ra,ra,ra + 8: 5621417b cv.cplxmul.i.div4 sp,sp,sp + c: 5684447b cv.cplxmul.i.div4 s0,s0,s0 + 10: 574a4a7b cv.cplxmul.i.div4 s4,s4,s4 + 14: 57ffcffb cv.cplxmul.i.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s new file mode 100644 index 00000000000..5d96c06e72d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i.div4 x0, x0, x0 + cv.cplxmul.i.div4 x1, x1, x1 + cv.cplxmul.i.div4 x2, x2, x2 + cv.cplxmul.i.div4 x8, x8, x8 + cv.cplxmul.i.div4 x20, x20, x20 + cv.cplxmul.i.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d new file mode 100644 index 00000000000..99fabfe2cd9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div8-fail.s +#error_output: cv-cplxmul-i-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l new file mode 100644 index 00000000000..cc52645bf80 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i.div8 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s new file mode 100644 index 00000000000..bcd458cd249 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i.div8 x32, x32, x32 + cv.cplxmul.i.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d new file mode 100644 index 00000000000..25c4602a15a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600607b cv.cplxmul.i.div8 zero,zero,zero + 4: 5610e0fb cv.cplxmul.i.div8 ra,ra,ra + 8: 5621617b cv.cplxmul.i.div8 sp,sp,sp + c: 5684647b cv.cplxmul.i.div8 s0,s0,s0 + 10: 574a6a7b cv.cplxmul.i.div8 s4,s4,s4 + 14: 57ffeffb cv.cplxmul.i.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s new file mode 100644 index 00000000000..f01268fb5c0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i.div8 x0, x0, x0 + cv.cplxmul.i.div8 x1, x1, x1 + cv.cplxmul.i.div8 x2, x2, x2 + cv.cplxmul.i.div8 x8, x8, x8 + cv.cplxmul.i.div8 x20, x20, x20 + cv.cplxmul.i.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d new file mode 100644 index 00000000000..54a12007ee9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-fail.s +#error_output: cv-cplxmul-i-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l new file mode 100644 index 00000000000..4d63c3d02b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s new file mode 100644 index 00000000000..3b1cd653850 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i x32, x32, x32 + cv.cplxmul.i x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d new file mode 100644 index 00000000000..72a0b08c1e0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600007b cv.cplxmul.i zero,zero,zero + 4: 561080fb cv.cplxmul.i ra,ra,ra + 8: 5621017b cv.cplxmul.i sp,sp,sp + c: 5684047b cv.cplxmul.i s0,s0,s0 + 10: 574a0a7b cv.cplxmul.i s4,s4,s4 + 14: 57ff8ffb cv.cplxmul.i t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s new file mode 100644 index 00000000000..1384fa157b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i x0, x0, x0 + cv.cplxmul.i x1, x1, x1 + cv.cplxmul.i x2, x2, x2 + cv.cplxmul.i x8, x8, x8 + cv.cplxmul.i x20, x20, x20 + cv.cplxmul.i x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d new file mode 100644 index 00000000000..244ec9ee316 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div2-fail.s +#error_output: cv-cplxmul-r-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l new file mode 100644 index 00000000000..0f6c70cbaa1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r.div2 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s new file mode 100644 index 00000000000..a88cc6b3c73 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r.div2 x32, x32, x32 + cv.cplxmul.r.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d new file mode 100644 index 00000000000..0931e184b30 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400207b cv.cplxmul.r.div2 zero,zero,zero + 4: 5410a0fb cv.cplxmul.r.div2 ra,ra,ra + 8: 5421217b cv.cplxmul.r.div2 sp,sp,sp + c: 5484247b cv.cplxmul.r.div2 s0,s0,s0 + 10: 554a2a7b cv.cplxmul.r.div2 s4,s4,s4 + 14: 55ffaffb cv.cplxmul.r.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s new file mode 100644 index 00000000000..48d694098cc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r.div2 x0, x0, x0 + cv.cplxmul.r.div2 x1, x1, x1 + cv.cplxmul.r.div2 x2, x2, x2 + cv.cplxmul.r.div2 x8, x8, x8 + cv.cplxmul.r.div2 x20, x20, x20 + cv.cplxmul.r.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d new file mode 100644 index 00000000000..10f67de862a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div4-fail.s +#error_output: cv-cplxmul-r-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l new file mode 100644 index 00000000000..3fa875f7a3c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r.div4 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s new file mode 100644 index 00000000000..1af6d1192ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r.div4 x32, x32, x32 + cv.cplxmul.r.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d new file mode 100644 index 00000000000..b1158ee98a3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400407b cv.cplxmul.r.div4 zero,zero,zero + 4: 5410c0fb cv.cplxmul.r.div4 ra,ra,ra + 8: 5421417b cv.cplxmul.r.div4 sp,sp,sp + c: 5484447b cv.cplxmul.r.div4 s0,s0,s0 + 10: 554a4a7b cv.cplxmul.r.div4 s4,s4,s4 + 14: 55ffcffb cv.cplxmul.r.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s new file mode 100644 index 00000000000..5729b88b45d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r.div4 x0, x0, x0 + cv.cplxmul.r.div4 x1, x1, x1 + cv.cplxmul.r.div4 x2, x2, x2 + cv.cplxmul.r.div4 x8, x8, x8 + cv.cplxmul.r.div4 x20, x20, x20 + cv.cplxmul.r.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d new file mode 100644 index 00000000000..a281659185f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div8-fail.s +#error_output: cv-cplxmul-r-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l new file mode 100644 index 00000000000..ba8c9752dad --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r.div8 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s new file mode 100644 index 00000000000..47cdfbe15da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r.div8 x32, x32, x32 + cv.cplxmul.r.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d new file mode 100644 index 00000000000..7bb6e03fcff --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400607b cv.cplxmul.r.div8 zero,zero,zero + 4: 5410e0fb cv.cplxmul.r.div8 ra,ra,ra + 8: 5421617b cv.cplxmul.r.div8 sp,sp,sp + c: 5484647b cv.cplxmul.r.div8 s0,s0,s0 + 10: 554a6a7b cv.cplxmul.r.div8 s4,s4,s4 + 14: 55ffeffb cv.cplxmul.r.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s new file mode 100644 index 00000000000..9c29967f4af --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r.div8 x0, x0, x0 + cv.cplxmul.r.div8 x1, x1, x1 + cv.cplxmul.r.div8 x2, x2, x2 + cv.cplxmul.r.div8 x8, x8, x8 + cv.cplxmul.r.div8 x20, x20, x20 + cv.cplxmul.r.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d new file mode 100644 index 00000000000..9adb2b61d4d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-fail.s +#error_output: cv-cplxmul-r-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l new file mode 100644 index 00000000000..f3f3a9cc542 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s new file mode 100644 index 00000000000..64b3b0d158b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r x32, x32, x32 + cv.cplxmul.r x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d new file mode 100644 index 00000000000..c9baf4e5e21 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400007b cv.cplxmul.r zero,zero,zero + 4: 541080fb cv.cplxmul.r ra,ra,ra + 8: 5421017b cv.cplxmul.r sp,sp,sp + c: 5484047b cv.cplxmul.r s0,s0,s0 + 10: 554a0a7b cv.cplxmul.r s4,s4,s4 + 14: 55ff8ffb cv.cplxmul.r t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s new file mode 100644 index 00000000000..8f588e7edee --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r x0, x0, x0 + cv.cplxmul.r x1, x1, x1 + cv.cplxmul.r x2, x2, x2 + cv.cplxmul.r x8, x8, x8 + cv.cplxmul.r x20, x20, x20 + cv.cplxmul.r x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.d new file mode 100644 index 00000000000..a21ba0453cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-b-fail.s +#error_output: cv-dotsp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.l new file mode 100644 index 00000000000..05e06134148 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.b x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.s new file mode 100644 index 00000000000..233872c9e03 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.b x32, x32, x32 + cv.dotsp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.d new file mode 100644 index 00000000000..dfdbbea1477 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000107b cv.dotsp.b zero,zero,zero + 4: 901090fb cv.dotsp.b ra,ra,ra + 8: 9021117b cv.dotsp.b sp,sp,sp + c: 9084147b cv.dotsp.b s0,s0,s0 + 10: 914a1a7b cv.dotsp.b s4,s4,s4 + 14: 91ff9ffb cv.dotsp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.s new file mode 100644 index 00000000000..e42ccef2344 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.b x0, x0, x0 + cv.dotsp.b x1, x1, x1 + cv.dotsp.b x2, x2, x2 + cv.dotsp.b x8, x8, x8 + cv.dotsp.b x20, x20, x20 + cv.dotsp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.d new file mode 100644 index 00000000000..17ed00fb91e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-h-fail.s +#error_output: cv-dotsp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.l new file mode 100644 index 00000000000..9a4969c3e92 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.h x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.s new file mode 100644 index 00000000000..309d96733e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.h x32, x32, x32 + cv.dotsp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.d new file mode 100644 index 00000000000..664718938f3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000007b cv.dotsp.h zero,zero,zero + 4: 901080fb cv.dotsp.h ra,ra,ra + 8: 9021017b cv.dotsp.h sp,sp,sp + c: 9084047b cv.dotsp.h s0,s0,s0 + 10: 914a0a7b cv.dotsp.h s4,s4,s4 + 14: 91ff8ffb cv.dotsp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.s new file mode 100644 index 00000000000..b9d49cbbfc5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.h x0, x0, x0 + cv.dotsp.h x1, x1, x1 + cv.dotsp.h x2, x2, x2 + cv.dotsp.h x8, x8, x8 + cv.dotsp.h x20, x20, x20 + cv.dotsp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d new file mode 100644 index 00000000000..88976c2469d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-b-fail.s +#error_output: cv-dotsp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l new file mode 100644 index 00000000000..f08b9016d62 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s new file mode 100644 index 00000000000..b45e83cfc31 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.sc.b x32, x32, x32 + cv.dotsp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d new file mode 100644 index 00000000000..701dfe1b75d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000507b cv.dotsp.sc.b zero,zero,zero + 4: 9010d0fb cv.dotsp.sc.b ra,ra,ra + 8: 9021517b cv.dotsp.sc.b sp,sp,sp + c: 9084547b cv.dotsp.sc.b s0,s0,s0 + 10: 914a5a7b cv.dotsp.sc.b s4,s4,s4 + 14: 91ffdffb cv.dotsp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s new file mode 100644 index 00000000000..966a6ca8a8b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.sc.b x0, x0, x0 + cv.dotsp.sc.b x1, x1, x1 + cv.dotsp.sc.b x2, x2, x2 + cv.dotsp.sc.b x8, x8, x8 + cv.dotsp.sc.b x20, x20, x20 + cv.dotsp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d new file mode 100644 index 00000000000..b6e424fcf43 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-h-fail.s +#error_output: cv-dotsp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l new file mode 100644 index 00000000000..16aa43d60bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s new file mode 100644 index 00000000000..935203cae15 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.sc.h x32, x32, x32 + cv.dotsp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d new file mode 100644 index 00000000000..47628f309d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000407b cv.dotsp.sc.h zero,zero,zero + 4: 9010c0fb cv.dotsp.sc.h ra,ra,ra + 8: 9021417b cv.dotsp.sc.h sp,sp,sp + c: 9084447b cv.dotsp.sc.h s0,s0,s0 + 10: 914a4a7b cv.dotsp.sc.h s4,s4,s4 + 14: 91ffcffb cv.dotsp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s new file mode 100644 index 00000000000..a9e6ccc2cb5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.sc.h x0, x0, x0 + cv.dotsp.sc.h x1, x1, x1 + cv.dotsp.sc.h x2, x2, x2 + cv.dotsp.sc.h x8, x8, x8 + cv.dotsp.sc.h x20, x20, x20 + cv.dotsp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d new file mode 100644 index 00000000000..a1736568218 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-b-fail.s +#error_output: cv-dotsp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l new file mode 100644 index 00000000000..76fff08f39b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.dotsp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s new file mode 100644 index 00000000000..475b2207f85 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotsp.sci.b x32, x32, 20 + cv.dotsp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.dotsp.sci.b x6, x7, -33 + cv.dotsp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d new file mode 100644 index 00000000000..f655daffd46 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9140707b cv.dotsp.sci.b zero,zero,20 + 4: 9140f0fb cv.dotsp.sci.b ra,ra,20 + 8: 9141717b cv.dotsp.sci.b sp,sp,20 + c: 9144747b cv.dotsp.sci.b s0,s0,20 + 10: 914a7a7b cv.dotsp.sci.b s4,s4,20 + 14: 914ffffb cv.dotsp.sci.b t6,t6,20 + 18: 9203f37b cv.dotsp.sci.b t1,t2,-32 + 1c: 9003f37b cv.dotsp.sci.b t1,t2,0 + 20: 91f3f37b cv.dotsp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s new file mode 100644 index 00000000000..47bc8405e8f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotsp.sci.b x0, x0, 20 + cv.dotsp.sci.b x1, x1, 20 + cv.dotsp.sci.b x2, x2, 20 + cv.dotsp.sci.b x8, x8, 20 + cv.dotsp.sci.b x20, x20, 20 + cv.dotsp.sci.b x31, x31, 20 + #Immediate Values Test + cv.dotsp.sci.b x6, x7, -32 + cv.dotsp.sci.b x6, x7, 0 + cv.dotsp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d new file mode 100644 index 00000000000..a3b6a1fc521 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-h-fail.s +#error_output: cv-dotsp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l new file mode 100644 index 00000000000..9410a24e1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.dotsp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s new file mode 100644 index 00000000000..ba4a59e29b4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotsp.sci.h x32, x32, 20 + cv.dotsp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.dotsp.sci.h x6, x7, -33 + cv.dotsp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d new file mode 100644 index 00000000000..869060ab27e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9140607b cv.dotsp.sci.h zero,zero,20 + 4: 9140e0fb cv.dotsp.sci.h ra,ra,20 + 8: 9141617b cv.dotsp.sci.h sp,sp,20 + c: 9144647b cv.dotsp.sci.h s0,s0,20 + 10: 914a6a7b cv.dotsp.sci.h s4,s4,20 + 14: 914feffb cv.dotsp.sci.h t6,t6,20 + 18: 9203e37b cv.dotsp.sci.h t1,t2,-32 + 1c: 9003e37b cv.dotsp.sci.h t1,t2,0 + 20: 91f3e37b cv.dotsp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s new file mode 100644 index 00000000000..9503a705697 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotsp.sci.h x0, x0, 20 + cv.dotsp.sci.h x1, x1, 20 + cv.dotsp.sci.h x2, x2, 20 + cv.dotsp.sci.h x8, x8, 20 + cv.dotsp.sci.h x20, x20, 20 + cv.dotsp.sci.h x31, x31, 20 + #Immediate Values Test + cv.dotsp.sci.h x6, x7, -32 + cv.dotsp.sci.h x6, x7, 0 + cv.dotsp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-fail.d b/gas/testsuite/gas/riscv/cv-dotup-b-fail.d new file mode 100644 index 00000000000..50aae60c56e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-b-fail.s +#error_output: cv-dotup-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-fail.l b/gas/testsuite/gas/riscv/cv-dotup-b-fail.l new file mode 100644 index 00000000000..7a3964aece1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.b x32,x32,x32' +.*: Error: illegal operands `cv.dotup.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-fail.s b/gas/testsuite/gas/riscv/cv-dotup-b-fail.s new file mode 100644 index 00000000000..be8a84793ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.b x32, x32, x32 + cv.dotup.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-pass.d b/gas/testsuite/gas/riscv/cv-dotup-b-pass.d new file mode 100644 index 00000000000..64bd7881258 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000107b cv.dotup.b zero,zero,zero + 4: 801090fb cv.dotup.b ra,ra,ra + 8: 8021117b cv.dotup.b sp,sp,sp + c: 8084147b cv.dotup.b s0,s0,s0 + 10: 814a1a7b cv.dotup.b s4,s4,s4 + 14: 81ff9ffb cv.dotup.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-pass.s b/gas/testsuite/gas/riscv/cv-dotup-b-pass.s new file mode 100644 index 00000000000..92b94f9a382 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.b x0, x0, x0 + cv.dotup.b x1, x1, x1 + cv.dotup.b x2, x2, x2 + cv.dotup.b x8, x8, x8 + cv.dotup.b x20, x20, x20 + cv.dotup.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-fail.d b/gas/testsuite/gas/riscv/cv-dotup-h-fail.d new file mode 100644 index 00000000000..5d53fe324e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-h-fail.s +#error_output: cv-dotup-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-fail.l b/gas/testsuite/gas/riscv/cv-dotup-h-fail.l new file mode 100644 index 00000000000..3bc820e3e8b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.h x32,x32,x32' +.*: Error: illegal operands `cv.dotup.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-fail.s b/gas/testsuite/gas/riscv/cv-dotup-h-fail.s new file mode 100644 index 00000000000..7a72d90c6ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.h x32, x32, x32 + cv.dotup.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-pass.d b/gas/testsuite/gas/riscv/cv-dotup-h-pass.d new file mode 100644 index 00000000000..19685293ca3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000007b cv.dotup.h zero,zero,zero + 4: 801080fb cv.dotup.h ra,ra,ra + 8: 8021017b cv.dotup.h sp,sp,sp + c: 8084047b cv.dotup.h s0,s0,s0 + 10: 814a0a7b cv.dotup.h s4,s4,s4 + 14: 81ff8ffb cv.dotup.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-pass.s b/gas/testsuite/gas/riscv/cv-dotup-h-pass.s new file mode 100644 index 00000000000..c5390d114aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.h x0, x0, x0 + cv.dotup.h x1, x1, x1 + cv.dotup.h x2, x2, x2 + cv.dotup.h x8, x8, x8 + cv.dotup.h x20, x20, x20 + cv.dotup.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d new file mode 100644 index 00000000000..dec04b2f32a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-b-fail.s +#error_output: cv-dotup-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l new file mode 100644 index 00000000000..86044aeac47 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.dotup.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s new file mode 100644 index 00000000000..c3265a0f753 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.sc.b x32, x32, x32 + cv.dotup.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d new file mode 100644 index 00000000000..bf81586c92f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000507b cv.dotup.sc.b zero,zero,zero + 4: 8010d0fb cv.dotup.sc.b ra,ra,ra + 8: 8021517b cv.dotup.sc.b sp,sp,sp + c: 8084547b cv.dotup.sc.b s0,s0,s0 + 10: 814a5a7b cv.dotup.sc.b s4,s4,s4 + 14: 81ffdffb cv.dotup.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s new file mode 100644 index 00000000000..126d7e3af2a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.sc.b x0, x0, x0 + cv.dotup.sc.b x1, x1, x1 + cv.dotup.sc.b x2, x2, x2 + cv.dotup.sc.b x8, x8, x8 + cv.dotup.sc.b x20, x20, x20 + cv.dotup.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d new file mode 100644 index 00000000000..746e94a3c70 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-h-fail.s +#error_output: cv-dotup-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l new file mode 100644 index 00000000000..c2264dcdb7c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.dotup.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s new file mode 100644 index 00000000000..659fe959482 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.sc.h x32, x32, x32 + cv.dotup.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d new file mode 100644 index 00000000000..3ecd2d7897e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000407b cv.dotup.sc.h zero,zero,zero + 4: 8010c0fb cv.dotup.sc.h ra,ra,ra + 8: 8021417b cv.dotup.sc.h sp,sp,sp + c: 8084447b cv.dotup.sc.h s0,s0,s0 + 10: 814a4a7b cv.dotup.sc.h s4,s4,s4 + 14: 81ffcffb cv.dotup.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s new file mode 100644 index 00000000000..89ee845f7cb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.sc.h x0, x0, x0 + cv.dotup.sc.h x1, x1, x1 + cv.dotup.sc.h x2, x2, x2 + cv.dotup.sc.h x8, x8, x8 + cv.dotup.sc.h x20, x20, x20 + cv.dotup.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d new file mode 100644 index 00000000000..fc0112e4eb0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-b-fail.s +#error_output: cv-dotup-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l new file mode 100644 index 00000000000..c90d2c625ed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sci.b x32,x32,20' +.*: Error: illegal operands `cv.dotup.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s new file mode 100644 index 00000000000..9fb5dbea8e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotup.sci.b x32, x32, 20 + cv.dotup.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.dotup.sci.b x6, x7, -33 + cv.dotup.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d new file mode 100644 index 00000000000..2359127abf1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8140707b cv.dotup.sci.b zero,zero,20 + 4: 8140f0fb cv.dotup.sci.b ra,ra,20 + 8: 8141717b cv.dotup.sci.b sp,sp,20 + c: 8144747b cv.dotup.sci.b s0,s0,20 + 10: 814a7a7b cv.dotup.sci.b s4,s4,20 + 14: 814ffffb cv.dotup.sci.b t6,t6,20 + 18: 8203f37b cv.dotup.sci.b t1,t2,-32 + 1c: 8003f37b cv.dotup.sci.b t1,t2,0 + 20: 81f3f37b cv.dotup.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s new file mode 100644 index 00000000000..c1f23683125 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotup.sci.b x0, x0, 20 + cv.dotup.sci.b x1, x1, 20 + cv.dotup.sci.b x2, x2, 20 + cv.dotup.sci.b x8, x8, 20 + cv.dotup.sci.b x20, x20, 20 + cv.dotup.sci.b x31, x31, 20 + #Immediate Values Test + cv.dotup.sci.b x6, x7, -32 + cv.dotup.sci.b x6, x7, 0 + cv.dotup.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d new file mode 100644 index 00000000000..8b7808e95ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-h-fail.s +#error_output: cv-dotup-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l new file mode 100644 index 00000000000..5e9b035acea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sci.h x32,x32,20' +.*: Error: illegal operands `cv.dotup.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s new file mode 100644 index 00000000000..ddab1f4389b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotup.sci.h x32, x32, 20 + cv.dotup.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.dotup.sci.h x6, x7, -33 + cv.dotup.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d new file mode 100644 index 00000000000..0f07d542782 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8140607b cv.dotup.sci.h zero,zero,20 + 4: 8140e0fb cv.dotup.sci.h ra,ra,20 + 8: 8141617b cv.dotup.sci.h sp,sp,20 + c: 8144647b cv.dotup.sci.h s0,s0,20 + 10: 814a6a7b cv.dotup.sci.h s4,s4,20 + 14: 814feffb cv.dotup.sci.h t6,t6,20 + 18: 8203e37b cv.dotup.sci.h t1,t2,-32 + 1c: 8003e37b cv.dotup.sci.h t1,t2,0 + 20: 81f3e37b cv.dotup.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s new file mode 100644 index 00000000000..08d2cb1b8e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotup.sci.h x0, x0, 20 + cv.dotup.sci.h x1, x1, 20 + cv.dotup.sci.h x2, x2, 20 + cv.dotup.sci.h x8, x8, 20 + cv.dotup.sci.h x20, x20, 20 + cv.dotup.sci.h x31, x31, 20 + #Immediate Values Test + cv.dotup.sci.h x6, x7, -32 + cv.dotup.sci.h x6, x7, 0 + cv.dotup.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.d new file mode 100644 index 00000000000..7e7df1d80ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-b-fail.s +#error_output: cv-dotusp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.l new file mode 100644 index 00000000000..da8dcc44589 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.b x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.s new file mode 100644 index 00000000000..875e9629d05 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.b x32, x32, x32 + cv.dotusp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.d new file mode 100644 index 00000000000..2f4318efabf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800107b cv.dotusp.b zero,zero,zero + 4: 881090fb cv.dotusp.b ra,ra,ra + 8: 8821117b cv.dotusp.b sp,sp,sp + c: 8884147b cv.dotusp.b s0,s0,s0 + 10: 894a1a7b cv.dotusp.b s4,s4,s4 + 14: 89ff9ffb cv.dotusp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.s new file mode 100644 index 00000000000..b39b8abc5da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.b x0, x0, x0 + cv.dotusp.b x1, x1, x1 + cv.dotusp.b x2, x2, x2 + cv.dotusp.b x8, x8, x8 + cv.dotusp.b x20, x20, x20 + cv.dotusp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.d new file mode 100644 index 00000000000..fdf796e16f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-h-fail.s +#error_output: cv-dotusp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.l new file mode 100644 index 00000000000..3b025c9b718 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.h x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.s new file mode 100644 index 00000000000..cf41e79b32e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.h x32, x32, x32 + cv.dotusp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.d new file mode 100644 index 00000000000..04f45a0f32c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800007b cv.dotusp.h zero,zero,zero + 4: 881080fb cv.dotusp.h ra,ra,ra + 8: 8821017b cv.dotusp.h sp,sp,sp + c: 8884047b cv.dotusp.h s0,s0,s0 + 10: 894a0a7b cv.dotusp.h s4,s4,s4 + 14: 89ff8ffb cv.dotusp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.s new file mode 100644 index 00000000000..8abcb4ea21c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.h x0, x0, x0 + cv.dotusp.h x1, x1, x1 + cv.dotusp.h x2, x2, x2 + cv.dotusp.h x8, x8, x8 + cv.dotusp.h x20, x20, x20 + cv.dotusp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d new file mode 100644 index 00000000000..3caf83969dd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-b-fail.s +#error_output: cv-dotusp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l new file mode 100644 index 00000000000..c1c7d325c99 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s new file mode 100644 index 00000000000..a4a1cac9859 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.sc.b x32, x32, x32 + cv.dotusp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d new file mode 100644 index 00000000000..1932b6cb3d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800507b cv.dotusp.sc.b zero,zero,zero + 4: 8810d0fb cv.dotusp.sc.b ra,ra,ra + 8: 8821517b cv.dotusp.sc.b sp,sp,sp + c: 8884547b cv.dotusp.sc.b s0,s0,s0 + 10: 894a5a7b cv.dotusp.sc.b s4,s4,s4 + 14: 89ffdffb cv.dotusp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s new file mode 100644 index 00000000000..7b8cc4f2b03 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.sc.b x0, x0, x0 + cv.dotusp.sc.b x1, x1, x1 + cv.dotusp.sc.b x2, x2, x2 + cv.dotusp.sc.b x8, x8, x8 + cv.dotusp.sc.b x20, x20, x20 + cv.dotusp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d new file mode 100644 index 00000000000..320d1aa446f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-h-fail.s +#error_output: cv-dotusp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l new file mode 100644 index 00000000000..48e1819aa53 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s new file mode 100644 index 00000000000..a69450163b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.sc.h x32, x32, x32 + cv.dotusp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d new file mode 100644 index 00000000000..3917f85b0a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800407b cv.dotusp.sc.h zero,zero,zero + 4: 8810c0fb cv.dotusp.sc.h ra,ra,ra + 8: 8821417b cv.dotusp.sc.h sp,sp,sp + c: 8884447b cv.dotusp.sc.h s0,s0,s0 + 10: 894a4a7b cv.dotusp.sc.h s4,s4,s4 + 14: 89ffcffb cv.dotusp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s new file mode 100644 index 00000000000..c10f72f2fa4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.sc.h x0, x0, x0 + cv.dotusp.sc.h x1, x1, x1 + cv.dotusp.sc.h x2, x2, x2 + cv.dotusp.sc.h x8, x8, x8 + cv.dotusp.sc.h x20, x20, x20 + cv.dotusp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d new file mode 100644 index 00000000000..604a44d11a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-b-fail.s +#error_output: cv-dotusp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l new file mode 100644 index 00000000000..6e3e7bf28de --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.dotusp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s new file mode 100644 index 00000000000..14a57c61669 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotusp.sci.b x32, x32, 20 + cv.dotusp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.dotusp.sci.b x6, x7, -33 + cv.dotusp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d new file mode 100644 index 00000000000..70c5f7a9ebf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8940707b cv.dotusp.sci.b zero,zero,20 + 4: 8940f0fb cv.dotusp.sci.b ra,ra,20 + 8: 8941717b cv.dotusp.sci.b sp,sp,20 + c: 8944747b cv.dotusp.sci.b s0,s0,20 + 10: 894a7a7b cv.dotusp.sci.b s4,s4,20 + 14: 894ffffb cv.dotusp.sci.b t6,t6,20 + 18: 8a03f37b cv.dotusp.sci.b t1,t2,-32 + 1c: 8803f37b cv.dotusp.sci.b t1,t2,0 + 20: 89f3f37b cv.dotusp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s new file mode 100644 index 00000000000..9ca11c5d868 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotusp.sci.b x0, x0, 20 + cv.dotusp.sci.b x1, x1, 20 + cv.dotusp.sci.b x2, x2, 20 + cv.dotusp.sci.b x8, x8, 20 + cv.dotusp.sci.b x20, x20, 20 + cv.dotusp.sci.b x31, x31, 20 + #Immediate Values Test + cv.dotusp.sci.b x6, x7, -32 + cv.dotusp.sci.b x6, x7, 0 + cv.dotusp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d new file mode 100644 index 00000000000..aa77b1964a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-h-fail.s +#error_output: cv-dotusp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l new file mode 100644 index 00000000000..99f14c09c12 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.dotusp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s new file mode 100644 index 00000000000..0075dd1b822 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotusp.sci.h x32, x32, 20 + cv.dotusp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.dotusp.sci.h x6, x7, -33 + cv.dotusp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d new file mode 100644 index 00000000000..ea7d3fcd967 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8940607b cv.dotusp.sci.h zero,zero,20 + 4: 8940e0fb cv.dotusp.sci.h ra,ra,20 + 8: 8941617b cv.dotusp.sci.h sp,sp,20 + c: 8944647b cv.dotusp.sci.h s0,s0,20 + 10: 894a6a7b cv.dotusp.sci.h s4,s4,20 + 14: 894feffb cv.dotusp.sci.h t6,t6,20 + 18: 8a03e37b cv.dotusp.sci.h t1,t2,-32 + 1c: 8803e37b cv.dotusp.sci.h t1,t2,0 + 20: 89f3e37b cv.dotusp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s new file mode 100644 index 00000000000..49528dc05e1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotusp.sci.h x0, x0, 20 + cv.dotusp.sci.h x1, x1, 20 + cv.dotusp.sci.h x2, x2, 20 + cv.dotusp.sci.h x8, x8, 20 + cv.dotusp.sci.h x20, x20, 20 + cv.dotusp.sci.h x31, x31, 20 + #Immediate Values Test + cv.dotusp.sci.h x6, x7, -32 + cv.dotusp.sci.h x6, x7, 0 + cv.dotusp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extract-b-fail.d b/gas/testsuite/gas/riscv/cv-extract-b-fail.d new file mode 100644 index 00000000000..da65de17617 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-b-fail.s +#error_output: cv-extract-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extract-b-fail.l b/gas/testsuite/gas/riscv/cv-extract-b-fail.l new file mode 100644 index 00000000000..d2e8f29dea4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extract.b x32,x32,20' +.*: Error: illegal operands `cv.extract.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extract-b-fail.s b/gas/testsuite/gas/riscv/cv-extract-b-fail.s new file mode 100644 index 00000000000..6ad92d1db35 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extract.b x32, x32, 20 + cv.extract.b x33, x33, 20 + #Boundary Immediate Values Test + cv.extract.b x6, x7, -33 + cv.extract.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extract-b-pass.d b/gas/testsuite/gas/riscv/cv-extract-b-pass.d new file mode 100644 index 00000000000..fde6ac901a4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940107b cv.extract.b zero,zero,20 + 4: b94090fb cv.extract.b ra,ra,20 + 8: b941117b cv.extract.b sp,sp,20 + c: b944147b cv.extract.b s0,s0,20 + 10: b94a1a7b cv.extract.b s4,s4,20 + 14: b94f9ffb cv.extract.b t6,t6,20 + 18: ba03937b cv.extract.b t1,t2,-32 + 1c: b803937b cv.extract.b t1,t2,0 + 20: b9f3937b cv.extract.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extract-b-pass.s b/gas/testsuite/gas/riscv/cv-extract-b-pass.s new file mode 100644 index 00000000000..d798e4050ae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extract.b x0, x0, 20 + cv.extract.b x1, x1, 20 + cv.extract.b x2, x2, 20 + cv.extract.b x8, x8, 20 + cv.extract.b x20, x20, 20 + cv.extract.b x31, x31, 20 + #Immediate Values Test + cv.extract.b x6, x7, -32 + cv.extract.b x6, x7, 0 + cv.extract.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extract-h-fail.d b/gas/testsuite/gas/riscv/cv-extract-h-fail.d new file mode 100644 index 00000000000..7dac1d9b18d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-h-fail.s +#error_output: cv-extract-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extract-h-fail.l b/gas/testsuite/gas/riscv/cv-extract-h-fail.l new file mode 100644 index 00000000000..488e09399ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extract.h x32,x32,20' +.*: Error: illegal operands `cv.extract.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extract-h-fail.s b/gas/testsuite/gas/riscv/cv-extract-h-fail.s new file mode 100644 index 00000000000..6db2e75de16 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extract.h x32, x32, 20 + cv.extract.h x33, x33, 20 + #Boundary Immediate Values Test + cv.extract.h x6, x7, -33 + cv.extract.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extract-h-pass.d b/gas/testsuite/gas/riscv/cv-extract-h-pass.d new file mode 100644 index 00000000000..67f00cc20c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940007b cv.extract.h zero,zero,20 + 4: b94080fb cv.extract.h ra,ra,20 + 8: b941017b cv.extract.h sp,sp,20 + c: b944047b cv.extract.h s0,s0,20 + 10: b94a0a7b cv.extract.h s4,s4,20 + 14: b94f8ffb cv.extract.h t6,t6,20 + 18: ba03837b cv.extract.h t1,t2,-32 + 1c: b803837b cv.extract.h t1,t2,0 + 20: b9f3837b cv.extract.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extract-h-pass.s b/gas/testsuite/gas/riscv/cv-extract-h-pass.s new file mode 100644 index 00000000000..1962435c26b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extract.h x0, x0, 20 + cv.extract.h x1, x1, 20 + cv.extract.h x2, x2, 20 + cv.extract.h x8, x8, 20 + cv.extract.h x20, x20, 20 + cv.extract.h x31, x31, 20 + #Immediate Values Test + cv.extract.h x6, x7, -32 + cv.extract.h x6, x7, 0 + cv.extract.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-fail.d b/gas/testsuite/gas/riscv/cv-extractu-b-fail.d new file mode 100644 index 00000000000..7c8efc141e1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-b-fail.s +#error_output: cv-extractu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-fail.l b/gas/testsuite/gas/riscv/cv-extractu-b-fail.l new file mode 100644 index 00000000000..41b2642562f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extractu.b x32,x32,20' +.*: Error: illegal operands `cv.extractu.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-fail.s b/gas/testsuite/gas/riscv/cv-extractu-b-fail.s new file mode 100644 index 00000000000..fe37572ae00 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extractu.b x32, x32, 20 + cv.extractu.b x33, x33, 20 + #Boundary Immediate Values Test + cv.extractu.b x6, x7, -33 + cv.extractu.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-pass.d b/gas/testsuite/gas/riscv/cv-extractu-b-pass.d new file mode 100644 index 00000000000..4e87a048cf0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940307b cv.extractu.b zero,zero,20 + 4: b940b0fb cv.extractu.b ra,ra,20 + 8: b941317b cv.extractu.b sp,sp,20 + c: b944347b cv.extractu.b s0,s0,20 + 10: b94a3a7b cv.extractu.b s4,s4,20 + 14: b94fbffb cv.extractu.b t6,t6,20 + 18: ba03b37b cv.extractu.b t1,t2,-32 + 1c: b803b37b cv.extractu.b t1,t2,0 + 20: b9f3b37b cv.extractu.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-pass.s b/gas/testsuite/gas/riscv/cv-extractu-b-pass.s new file mode 100644 index 00000000000..e3711313b2e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extractu.b x0, x0, 20 + cv.extractu.b x1, x1, 20 + cv.extractu.b x2, x2, 20 + cv.extractu.b x8, x8, 20 + cv.extractu.b x20, x20, 20 + cv.extractu.b x31, x31, 20 + #Immediate Values Test + cv.extractu.b x6, x7, -32 + cv.extractu.b x6, x7, 0 + cv.extractu.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-fail.d b/gas/testsuite/gas/riscv/cv-extractu-h-fail.d new file mode 100644 index 00000000000..d4543a9d7ef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-h-fail.s +#error_output: cv-extractu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-fail.l b/gas/testsuite/gas/riscv/cv-extractu-h-fail.l new file mode 100644 index 00000000000..97e195317eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extractu.h x32,x32,20' +.*: Error: illegal operands `cv.extractu.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-fail.s b/gas/testsuite/gas/riscv/cv-extractu-h-fail.s new file mode 100644 index 00000000000..39788e109fd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extractu.h x32, x32, 20 + cv.extractu.h x33, x33, 20 + #Boundary Immediate Values Test + cv.extractu.h x6, x7, -33 + cv.extractu.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-pass.d b/gas/testsuite/gas/riscv/cv-extractu-h-pass.d new file mode 100644 index 00000000000..10652a9f1ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940207b cv.extractu.h zero,zero,20 + 4: b940a0fb cv.extractu.h ra,ra,20 + 8: b941217b cv.extractu.h sp,sp,20 + c: b944247b cv.extractu.h s0,s0,20 + 10: b94a2a7b cv.extractu.h s4,s4,20 + 14: b94faffb cv.extractu.h t6,t6,20 + 18: ba03a37b cv.extractu.h t1,t2,-32 + 1c: b803a37b cv.extractu.h t1,t2,0 + 20: b9f3a37b cv.extractu.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-pass.s b/gas/testsuite/gas/riscv/cv-extractu-h-pass.s new file mode 100644 index 00000000000..d8b32f6e5a4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extractu.h x0, x0, 20 + cv.extractu.h x1, x1, 20 + cv.extractu.h x2, x2, 20 + cv.extractu.h x8, x8, 20 + cv.extractu.h x20, x20, 20 + cv.extractu.h x31, x31, 20 + #Immediate Values Test + cv.extractu.h x6, x7, -32 + cv.extractu.h x6, x7, 0 + cv.extractu.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-insert-b-fail.d b/gas/testsuite/gas/riscv/cv-insert-b-fail.d new file mode 100644 index 00000000000..5d687c43293 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-b-fail.s +#error_output: cv-insert-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-insert-b-fail.l b/gas/testsuite/gas/riscv/cv-insert-b-fail.l new file mode 100644 index 00000000000..7e01fc2a68a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.insert.b x32,x32,20' +.*: Error: illegal operands `cv.insert.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-insert-b-fail.s b/gas/testsuite/gas/riscv/cv-insert-b-fail.s new file mode 100644 index 00000000000..aebdcabfcb7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.insert.b x32, x32, 20 + cv.insert.b x33, x33, 20 + #Boundary Immediate Values Test + cv.insert.b x6, x7, -33 + cv.insert.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-insert-b-pass.d b/gas/testsuite/gas/riscv/cv-insert-b-pass.d new file mode 100644 index 00000000000..4da033ea94a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940507b cv.insert.b zero,zero,20 + 4: b940d0fb cv.insert.b ra,ra,20 + 8: b941517b cv.insert.b sp,sp,20 + c: b944547b cv.insert.b s0,s0,20 + 10: b94a5a7b cv.insert.b s4,s4,20 + 14: b94fdffb cv.insert.b t6,t6,20 + 18: ba03d37b cv.insert.b t1,t2,-32 + 1c: b803d37b cv.insert.b t1,t2,0 + 20: b9f3d37b cv.insert.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-insert-b-pass.s b/gas/testsuite/gas/riscv/cv-insert-b-pass.s new file mode 100644 index 00000000000..a455628ddd8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.insert.b x0, x0, 20 + cv.insert.b x1, x1, 20 + cv.insert.b x2, x2, 20 + cv.insert.b x8, x8, 20 + cv.insert.b x20, x20, 20 + cv.insert.b x31, x31, 20 + #Immediate Values Test + cv.insert.b x6, x7, -32 + cv.insert.b x6, x7, 0 + cv.insert.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-insert-h-fail.d b/gas/testsuite/gas/riscv/cv-insert-h-fail.d new file mode 100644 index 00000000000..db89d6854d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-h-fail.s +#error_output: cv-insert-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-insert-h-fail.l b/gas/testsuite/gas/riscv/cv-insert-h-fail.l new file mode 100644 index 00000000000..efb6bf3c9d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.insert.h x32,x32,20' +.*: Error: illegal operands `cv.insert.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-insert-h-fail.s b/gas/testsuite/gas/riscv/cv-insert-h-fail.s new file mode 100644 index 00000000000..c95958f4279 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.insert.h x32, x32, 20 + cv.insert.h x33, x33, 20 + #Boundary Immediate Values Test + cv.insert.h x6, x7, -33 + cv.insert.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-insert-h-pass.d b/gas/testsuite/gas/riscv/cv-insert-h-pass.d new file mode 100644 index 00000000000..e1c7e673407 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940407b cv.insert.h zero,zero,20 + 4: b940c0fb cv.insert.h ra,ra,20 + 8: b941417b cv.insert.h sp,sp,20 + c: b944447b cv.insert.h s0,s0,20 + 10: b94a4a7b cv.insert.h s4,s4,20 + 14: b94fcffb cv.insert.h t6,t6,20 + 18: ba03c37b cv.insert.h t1,t2,-32 + 1c: b803c37b cv.insert.h t1,t2,0 + 20: b9f3c37b cv.insert.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-insert-h-pass.s b/gas/testsuite/gas/riscv/cv-insert-h-pass.s new file mode 100644 index 00000000000..442e933b768 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.insert.h x0, x0, 20 + cv.insert.h x1, x1, 20 + cv.insert.h x2, x2, 20 + cv.insert.h x8, x8, 20 + cv.insert.h x20, x20, 20 + cv.insert.h x31, x31, 20 + #Immediate Values Test + cv.insert.h x6, x7, -32 + cv.insert.h x6, x7, 0 + cv.insert.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-max-b-fail.d b/gas/testsuite/gas/riscv/cv-max-b-fail.d new file mode 100644 index 00000000000..3e827bd06c0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-b-fail.s +#error_output: cv-max-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-b-fail.l b/gas/testsuite/gas/riscv/cv-max-b-fail.l new file mode 100644 index 00000000000..ffa9db5ce2e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.b x32,x32,x32' +.*: Error: illegal operands `cv.max.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-b-fail.s b/gas/testsuite/gas/riscv/cv-max-b-fail.s new file mode 100644 index 00000000000..6e172d02599 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.b x32, x32, x32 + cv.max.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-b-pass.d b/gas/testsuite/gas/riscv/cv-max-b-pass.d new file mode 100644 index 00000000000..f790247e2e2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000107b cv.max.b zero,zero,zero + 4: 301090fb cv.max.b ra,ra,ra + 8: 3021117b cv.max.b sp,sp,sp + c: 3084147b cv.max.b s0,s0,s0 + 10: 314a1a7b cv.max.b s4,s4,s4 + 14: 31ff9ffb cv.max.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-b-pass.s b/gas/testsuite/gas/riscv/cv-max-b-pass.s new file mode 100644 index 00000000000..c3fbaac0036 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.b x0, x0, x0 + cv.max.b x1, x1, x1 + cv.max.b x2, x2, x2 + cv.max.b x8, x8, x8 + cv.max.b x20, x20, x20 + cv.max.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-h-fail.d b/gas/testsuite/gas/riscv/cv-max-h-fail.d new file mode 100644 index 00000000000..bb263cf5102 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-h-fail.s +#error_output: cv-max-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-h-fail.l b/gas/testsuite/gas/riscv/cv-max-h-fail.l new file mode 100644 index 00000000000..e99ba005a12 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.h x32,x32,x32' +.*: Error: illegal operands `cv.max.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-h-fail.s b/gas/testsuite/gas/riscv/cv-max-h-fail.s new file mode 100644 index 00000000000..a8b7670f0e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.h x32, x32, x32 + cv.max.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-h-pass.d b/gas/testsuite/gas/riscv/cv-max-h-pass.d new file mode 100644 index 00000000000..8fd0bdd2f7c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000007b cv.max.h zero,zero,zero + 4: 301080fb cv.max.h ra,ra,ra + 8: 3021017b cv.max.h sp,sp,sp + c: 3084047b cv.max.h s0,s0,s0 + 10: 314a0a7b cv.max.h s4,s4,s4 + 14: 31ff8ffb cv.max.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-h-pass.s b/gas/testsuite/gas/riscv/cv-max-h-pass.s new file mode 100644 index 00000000000..db8bdcc94b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.h x0, x0, x0 + cv.max.h x1, x1, x1 + cv.max.h x2, x2, x2 + cv.max.h x8, x8, x8 + cv.max.h x20, x20, x20 + cv.max.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.d new file mode 100644 index 00000000000..90623287e4f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-b-fail.s +#error_output: cv-max-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.l new file mode 100644 index 00000000000..62bb8033164 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.max.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.s new file mode 100644 index 00000000000..9856ce452ad --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.sc.b x32, x32, x32 + cv.max.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.d new file mode 100644 index 00000000000..5e77ab30f71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000507b cv.max.sc.b zero,zero,zero + 4: 3010d0fb cv.max.sc.b ra,ra,ra + 8: 3021517b cv.max.sc.b sp,sp,sp + c: 3084547b cv.max.sc.b s0,s0,s0 + 10: 314a5a7b cv.max.sc.b s4,s4,s4 + 14: 31ffdffb cv.max.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.s new file mode 100644 index 00000000000..bd6af1624d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.sc.b x0, x0, x0 + cv.max.sc.b x1, x1, x1 + cv.max.sc.b x2, x2, x2 + cv.max.sc.b x8, x8, x8 + cv.max.sc.b x20, x20, x20 + cv.max.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.d new file mode 100644 index 00000000000..0083bf4c758 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-h-fail.s +#error_output: cv-max-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.l new file mode 100644 index 00000000000..1b60f1d2a9b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.max.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.s new file mode 100644 index 00000000000..cb311e985bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.sc.h x32, x32, x32 + cv.max.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.d new file mode 100644 index 00000000000..6dad313c162 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000407b cv.max.sc.h zero,zero,zero + 4: 3010c0fb cv.max.sc.h ra,ra,ra + 8: 3021417b cv.max.sc.h sp,sp,sp + c: 3084447b cv.max.sc.h s0,s0,s0 + 10: 314a4a7b cv.max.sc.h s4,s4,s4 + 14: 31ffcffb cv.max.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.s new file mode 100644 index 00000000000..73e7b4ed3f5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.sc.h x0, x0, x0 + cv.max.sc.h x1, x1, x1 + cv.max.sc.h x2, x2, x2 + cv.max.sc.h x8, x8, x8 + cv.max.sc.h x20, x20, x20 + cv.max.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.d new file mode 100644 index 00000000000..ff3634b9561 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-b-fail.s +#error_output: cv-max-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.l new file mode 100644 index 00000000000..27fd4658b42 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sci.b x32,x32,20' +.*: Error: illegal operands `cv.max.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.s new file mode 100644 index 00000000000..f6712c3ac94 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.max.sci.b x32, x32, 20 + cv.max.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.max.sci.b x6, x7, -33 + cv.max.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.d new file mode 100644 index 00000000000..e7acdca27b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3140707b cv.max.sci.b zero,zero,20 + 4: 3140f0fb cv.max.sci.b ra,ra,20 + 8: 3141717b cv.max.sci.b sp,sp,20 + c: 3144747b cv.max.sci.b s0,s0,20 + 10: 314a7a7b cv.max.sci.b s4,s4,20 + 14: 314ffffb cv.max.sci.b t6,t6,20 + 18: 3203f37b cv.max.sci.b t1,t2,-32 + 1c: 3003f37b cv.max.sci.b t1,t2,0 + 20: 31f3f37b cv.max.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.s new file mode 100644 index 00000000000..10751b5b3eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.max.sci.b x0, x0, 20 + cv.max.sci.b x1, x1, 20 + cv.max.sci.b x2, x2, 20 + cv.max.sci.b x8, x8, 20 + cv.max.sci.b x20, x20, 20 + cv.max.sci.b x31, x31, 20 + #Immediate Values Test + cv.max.sci.b x6, x7, -32 + cv.max.sci.b x6, x7, 0 + cv.max.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.d new file mode 100644 index 00000000000..a56bdfe3d4a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-h-fail.s +#error_output: cv-max-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.l new file mode 100644 index 00000000000..de60c07a756 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sci.h x32,x32,20' +.*: Error: illegal operands `cv.max.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.s new file mode 100644 index 00000000000..fc8b8dd178f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.max.sci.h x32, x32, 20 + cv.max.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.max.sci.h x6, x7, -33 + cv.max.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.d new file mode 100644 index 00000000000..6c7e4cbcac1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3140607b cv.max.sci.h zero,zero,20 + 4: 3140e0fb cv.max.sci.h ra,ra,20 + 8: 3141617b cv.max.sci.h sp,sp,20 + c: 3144647b cv.max.sci.h s0,s0,20 + 10: 314a6a7b cv.max.sci.h s4,s4,20 + 14: 314feffb cv.max.sci.h t6,t6,20 + 18: 3203e37b cv.max.sci.h t1,t2,-32 + 1c: 3003e37b cv.max.sci.h t1,t2,0 + 20: 31f3e37b cv.max.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.s new file mode 100644 index 00000000000..f0e4c7b0612 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.max.sci.h x0, x0, 20 + cv.max.sci.h x1, x1, 20 + cv.max.sci.h x2, x2, 20 + cv.max.sci.h x8, x8, 20 + cv.max.sci.h x20, x20, 20 + cv.max.sci.h x31, x31, 20 + #Immediate Values Test + cv.max.sci.h x6, x7, -32 + cv.max.sci.h x6, x7, 0 + cv.max.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-fail.d b/gas/testsuite/gas/riscv/cv-maxu-b-fail.d new file mode 100644 index 00000000000..8de9f7b601f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-b-fail.s +#error_output: cv-maxu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-fail.l b/gas/testsuite/gas/riscv/cv-maxu-b-fail.l new file mode 100644 index 00000000000..ac57a2f9361 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.b x32,x32,x32' +.*: Error: illegal operands `cv.maxu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-fail.s b/gas/testsuite/gas/riscv/cv-maxu-b-fail.s new file mode 100644 index 00000000000..aa05e82b980 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.b x32, x32, x32 + cv.maxu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-pass.d b/gas/testsuite/gas/riscv/cv-maxu-b-pass.d new file mode 100644 index 00000000000..b5e7a8cd903 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800107b cv.maxu.b zero,zero,zero + 4: 381090fb cv.maxu.b ra,ra,ra + 8: 3821117b cv.maxu.b sp,sp,sp + c: 3884147b cv.maxu.b s0,s0,s0 + 10: 394a1a7b cv.maxu.b s4,s4,s4 + 14: 39ff9ffb cv.maxu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-pass.s b/gas/testsuite/gas/riscv/cv-maxu-b-pass.s new file mode 100644 index 00000000000..6a87bf969b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.b x0, x0, x0 + cv.maxu.b x1, x1, x1 + cv.maxu.b x2, x2, x2 + cv.maxu.b x8, x8, x8 + cv.maxu.b x20, x20, x20 + cv.maxu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-fail.d b/gas/testsuite/gas/riscv/cv-maxu-h-fail.d new file mode 100644 index 00000000000..b0272e0a31a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-h-fail.s +#error_output: cv-maxu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-fail.l b/gas/testsuite/gas/riscv/cv-maxu-h-fail.l new file mode 100644 index 00000000000..1d530582eaa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.h x32,x32,x32' +.*: Error: illegal operands `cv.maxu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-fail.s b/gas/testsuite/gas/riscv/cv-maxu-h-fail.s new file mode 100644 index 00000000000..f28718085c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.h x32, x32, x32 + cv.maxu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-pass.d b/gas/testsuite/gas/riscv/cv-maxu-h-pass.d new file mode 100644 index 00000000000..9947015ce2e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800007b cv.maxu.h zero,zero,zero + 4: 381080fb cv.maxu.h ra,ra,ra + 8: 3821017b cv.maxu.h sp,sp,sp + c: 3884047b cv.maxu.h s0,s0,s0 + 10: 394a0a7b cv.maxu.h s4,s4,s4 + 14: 39ff8ffb cv.maxu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-pass.s b/gas/testsuite/gas/riscv/cv-maxu-h-pass.s new file mode 100644 index 00000000000..ecafc3afd1c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.h x0, x0, x0 + cv.maxu.h x1, x1, x1 + cv.maxu.h x2, x2, x2 + cv.maxu.h x8, x8, x8 + cv.maxu.h x20, x20, x20 + cv.maxu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d new file mode 100644 index 00000000000..03bbc27c795 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-b-fail.s +#error_output: cv-maxu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l new file mode 100644 index 00000000000..7f1928d30bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.maxu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s new file mode 100644 index 00000000000..68b8f9e4101 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.sc.b x32, x32, x32 + cv.maxu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d new file mode 100644 index 00000000000..717105464d7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800507b cv.maxu.sc.b zero,zero,zero + 4: 3810d0fb cv.maxu.sc.b ra,ra,ra + 8: 3821517b cv.maxu.sc.b sp,sp,sp + c: 3884547b cv.maxu.sc.b s0,s0,s0 + 10: 394a5a7b cv.maxu.sc.b s4,s4,s4 + 14: 39ffdffb cv.maxu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s new file mode 100644 index 00000000000..37273c1beb4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.sc.b x0, x0, x0 + cv.maxu.sc.b x1, x1, x1 + cv.maxu.sc.b x2, x2, x2 + cv.maxu.sc.b x8, x8, x8 + cv.maxu.sc.b x20, x20, x20 + cv.maxu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d new file mode 100644 index 00000000000..024c030fcf6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-h-fail.s +#error_output: cv-maxu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l new file mode 100644 index 00000000000..1fc68d46428 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.maxu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s new file mode 100644 index 00000000000..1dd73f293ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.sc.h x32, x32, x32 + cv.maxu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d new file mode 100644 index 00000000000..5574784a461 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800407b cv.maxu.sc.h zero,zero,zero + 4: 3810c0fb cv.maxu.sc.h ra,ra,ra + 8: 3821417b cv.maxu.sc.h sp,sp,sp + c: 3884447b cv.maxu.sc.h s0,s0,s0 + 10: 394a4a7b cv.maxu.sc.h s4,s4,s4 + 14: 39ffcffb cv.maxu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s new file mode 100644 index 00000000000..5d1c42c962a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.sc.h x0, x0, x0 + cv.maxu.sc.h x1, x1, x1 + cv.maxu.sc.h x2, x2, x2 + cv.maxu.sc.h x8, x8, x8 + cv.maxu.sc.h x20, x20, x20 + cv.maxu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d new file mode 100644 index 00000000000..8db25e2cc74 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-b-fail.s +#error_output: cv-maxu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l new file mode 100644 index 00000000000..ef9234af536 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.maxu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s new file mode 100644 index 00000000000..313ed227da9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.maxu.sci.b x32, x32, 20 + cv.maxu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.maxu.sci.b x6, x7, -33 + cv.maxu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d new file mode 100644 index 00000000000..afb737cafc4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3940707b cv.maxu.sci.b zero,zero,20 + 4: 3940f0fb cv.maxu.sci.b ra,ra,20 + 8: 3941717b cv.maxu.sci.b sp,sp,20 + c: 3944747b cv.maxu.sci.b s0,s0,20 + 10: 394a7a7b cv.maxu.sci.b s4,s4,20 + 14: 394ffffb cv.maxu.sci.b t6,t6,20 + 18: 3a03f37b cv.maxu.sci.b t1,t2,-32 + 1c: 3803f37b cv.maxu.sci.b t1,t2,0 + 20: 39f3f37b cv.maxu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s new file mode 100644 index 00000000000..516b8009979 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.maxu.sci.b x0, x0, 20 + cv.maxu.sci.b x1, x1, 20 + cv.maxu.sci.b x2, x2, 20 + cv.maxu.sci.b x8, x8, 20 + cv.maxu.sci.b x20, x20, 20 + cv.maxu.sci.b x31, x31, 20 + #Immediate Values Test + cv.maxu.sci.b x6, x7, -32 + cv.maxu.sci.b x6, x7, 0 + cv.maxu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d new file mode 100644 index 00000000000..66e84a018b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-h-fail.s +#error_output: cv-maxu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l new file mode 100644 index 00000000000..c179ee08774 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.maxu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s new file mode 100644 index 00000000000..40b56706bdc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.maxu.sci.h x32, x32, 20 + cv.maxu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.maxu.sci.h x6, x7, -33 + cv.maxu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d new file mode 100644 index 00000000000..29d2810b276 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3940607b cv.maxu.sci.h zero,zero,20 + 4: 3940e0fb cv.maxu.sci.h ra,ra,20 + 8: 3941617b cv.maxu.sci.h sp,sp,20 + c: 3944647b cv.maxu.sci.h s0,s0,20 + 10: 394a6a7b cv.maxu.sci.h s4,s4,20 + 14: 394feffb cv.maxu.sci.h t6,t6,20 + 18: 3a03e37b cv.maxu.sci.h t1,t2,-32 + 1c: 3803e37b cv.maxu.sci.h t1,t2,0 + 20: 39f3e37b cv.maxu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s new file mode 100644 index 00000000000..67d6309f659 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.maxu.sci.h x0, x0, 20 + cv.maxu.sci.h x1, x1, 20 + cv.maxu.sci.h x2, x2, 20 + cv.maxu.sci.h x8, x8, 20 + cv.maxu.sci.h x20, x20, 20 + cv.maxu.sci.h x31, x31, 20 + #Immediate Values Test + cv.maxu.sci.h x6, x7, -32 + cv.maxu.sci.h x6, x7, 0 + cv.maxu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-min-b-fail.d b/gas/testsuite/gas/riscv/cv-min-b-fail.d new file mode 100644 index 00000000000..47a5be9790d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-b-fail.s +#error_output: cv-min-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-b-fail.l b/gas/testsuite/gas/riscv/cv-min-b-fail.l new file mode 100644 index 00000000000..3d78d2d91b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.b x32,x32,x32' +.*: Error: illegal operands `cv.min.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-b-fail.s b/gas/testsuite/gas/riscv/cv-min-b-fail.s new file mode 100644 index 00000000000..0d6ed295eed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.b x32, x32, x32 + cv.min.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-b-pass.d b/gas/testsuite/gas/riscv/cv-min-b-pass.d new file mode 100644 index 00000000000..ff8ae63b017 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000107b cv.min.b zero,zero,zero + 4: 201090fb cv.min.b ra,ra,ra + 8: 2021117b cv.min.b sp,sp,sp + c: 2084147b cv.min.b s0,s0,s0 + 10: 214a1a7b cv.min.b s4,s4,s4 + 14: 21ff9ffb cv.min.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-b-pass.s b/gas/testsuite/gas/riscv/cv-min-b-pass.s new file mode 100644 index 00000000000..40af59781be --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.b x0, x0, x0 + cv.min.b x1, x1, x1 + cv.min.b x2, x2, x2 + cv.min.b x8, x8, x8 + cv.min.b x20, x20, x20 + cv.min.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-h-fail.d b/gas/testsuite/gas/riscv/cv-min-h-fail.d new file mode 100644 index 00000000000..25f5ce03f76 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-h-fail.s +#error_output: cv-min-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-h-fail.l b/gas/testsuite/gas/riscv/cv-min-h-fail.l new file mode 100644 index 00000000000..0f959466de8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.h x32,x32,x32' +.*: Error: illegal operands `cv.min.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-h-fail.s b/gas/testsuite/gas/riscv/cv-min-h-fail.s new file mode 100644 index 00000000000..2e30e37c795 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.h x32, x32, x32 + cv.min.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-h-pass.d b/gas/testsuite/gas/riscv/cv-min-h-pass.d new file mode 100644 index 00000000000..f3da47b079b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000007b cv.min.h zero,zero,zero + 4: 201080fb cv.min.h ra,ra,ra + 8: 2021017b cv.min.h sp,sp,sp + c: 2084047b cv.min.h s0,s0,s0 + 10: 214a0a7b cv.min.h s4,s4,s4 + 14: 21ff8ffb cv.min.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-h-pass.s b/gas/testsuite/gas/riscv/cv-min-h-pass.s new file mode 100644 index 00000000000..f3ab4b20b74 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.h x0, x0, x0 + cv.min.h x1, x1, x1 + cv.min.h x2, x2, x2 + cv.min.h x8, x8, x8 + cv.min.h x20, x20, x20 + cv.min.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.d new file mode 100644 index 00000000000..4ebd92a2603 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-b-fail.s +#error_output: cv-min-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.l new file mode 100644 index 00000000000..7f31ec02691 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.min.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.s new file mode 100644 index 00000000000..5b7fdcc7aa1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.sc.b x32, x32, x32 + cv.min.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.d new file mode 100644 index 00000000000..7cc616b5d1d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000507b cv.min.sc.b zero,zero,zero + 4: 2010d0fb cv.min.sc.b ra,ra,ra + 8: 2021517b cv.min.sc.b sp,sp,sp + c: 2084547b cv.min.sc.b s0,s0,s0 + 10: 214a5a7b cv.min.sc.b s4,s4,s4 + 14: 21ffdffb cv.min.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.s new file mode 100644 index 00000000000..671b8d32a6b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.sc.b x0, x0, x0 + cv.min.sc.b x1, x1, x1 + cv.min.sc.b x2, x2, x2 + cv.min.sc.b x8, x8, x8 + cv.min.sc.b x20, x20, x20 + cv.min.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.d new file mode 100644 index 00000000000..33b17fb725b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-h-fail.s +#error_output: cv-min-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.l new file mode 100644 index 00000000000..72ce1e76a29 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.min.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.s new file mode 100644 index 00000000000..5b62233762b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.sc.h x32, x32, x32 + cv.min.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.d new file mode 100644 index 00000000000..2d3f39c03bc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000407b cv.min.sc.h zero,zero,zero + 4: 2010c0fb cv.min.sc.h ra,ra,ra + 8: 2021417b cv.min.sc.h sp,sp,sp + c: 2084447b cv.min.sc.h s0,s0,s0 + 10: 214a4a7b cv.min.sc.h s4,s4,s4 + 14: 21ffcffb cv.min.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.s new file mode 100644 index 00000000000..19ed53f70ad --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.sc.h x0, x0, x0 + cv.min.sc.h x1, x1, x1 + cv.min.sc.h x2, x2, x2 + cv.min.sc.h x8, x8, x8 + cv.min.sc.h x20, x20, x20 + cv.min.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.d new file mode 100644 index 00000000000..7940871392d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-b-fail.s +#error_output: cv-min-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.l new file mode 100644 index 00000000000..204cae31c6a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sci.b x32,x32,20' +.*: Error: illegal operands `cv.min.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.s new file mode 100644 index 00000000000..6144655cdb0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.min.sci.b x32, x32, 20 + cv.min.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.min.sci.b x6, x7, -33 + cv.min.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.d new file mode 100644 index 00000000000..cfb0ac0d739 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2140707b cv.min.sci.b zero,zero,20 + 4: 2140f0fb cv.min.sci.b ra,ra,20 + 8: 2141717b cv.min.sci.b sp,sp,20 + c: 2144747b cv.min.sci.b s0,s0,20 + 10: 214a7a7b cv.min.sci.b s4,s4,20 + 14: 214ffffb cv.min.sci.b t6,t6,20 + 18: 2203f37b cv.min.sci.b t1,t2,-32 + 1c: 2003f37b cv.min.sci.b t1,t2,0 + 20: 21f3f37b cv.min.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.s new file mode 100644 index 00000000000..bef55674ef3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.min.sci.b x0, x0, 20 + cv.min.sci.b x1, x1, 20 + cv.min.sci.b x2, x2, 20 + cv.min.sci.b x8, x8, 20 + cv.min.sci.b x20, x20, 20 + cv.min.sci.b x31, x31, 20 + #Immediate Values Test + cv.min.sci.b x6, x7, -32 + cv.min.sci.b x6, x7, 0 + cv.min.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.d new file mode 100644 index 00000000000..357129735f4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-h-fail.s +#error_output: cv-min-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.l new file mode 100644 index 00000000000..1179f306663 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sci.h x32,x32,20' +.*: Error: illegal operands `cv.min.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.s new file mode 100644 index 00000000000..6e911ce5a68 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.min.sci.h x32, x32, 20 + cv.min.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.min.sci.h x6, x7, -33 + cv.min.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.d new file mode 100644 index 00000000000..ae57846549f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2140607b cv.min.sci.h zero,zero,20 + 4: 2140e0fb cv.min.sci.h ra,ra,20 + 8: 2141617b cv.min.sci.h sp,sp,20 + c: 2144647b cv.min.sci.h s0,s0,20 + 10: 214a6a7b cv.min.sci.h s4,s4,20 + 14: 214feffb cv.min.sci.h t6,t6,20 + 18: 2203e37b cv.min.sci.h t1,t2,-32 + 1c: 2003e37b cv.min.sci.h t1,t2,0 + 20: 21f3e37b cv.min.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.s new file mode 100644 index 00000000000..7f134823fab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.min.sci.h x0, x0, 20 + cv.min.sci.h x1, x1, 20 + cv.min.sci.h x2, x2, 20 + cv.min.sci.h x8, x8, 20 + cv.min.sci.h x20, x20, 20 + cv.min.sci.h x31, x31, 20 + #Immediate Values Test + cv.min.sci.h x6, x7, -32 + cv.min.sci.h x6, x7, 0 + cv.min.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-minu-b-fail.d b/gas/testsuite/gas/riscv/cv-minu-b-fail.d new file mode 100644 index 00000000000..57f2d016ffe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-b-fail.s +#error_output: cv-minu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-b-fail.l b/gas/testsuite/gas/riscv/cv-minu-b-fail.l new file mode 100644 index 00000000000..9971ea8223e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.b x32,x32,x32' +.*: Error: illegal operands `cv.minu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-b-fail.s b/gas/testsuite/gas/riscv/cv-minu-b-fail.s new file mode 100644 index 00000000000..c017c91d7c2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.b x32, x32, x32 + cv.minu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-b-pass.d b/gas/testsuite/gas/riscv/cv-minu-b-pass.d new file mode 100644 index 00000000000..ba9b60730fe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800107b cv.minu.b zero,zero,zero + 4: 281090fb cv.minu.b ra,ra,ra + 8: 2821117b cv.minu.b sp,sp,sp + c: 2884147b cv.minu.b s0,s0,s0 + 10: 294a1a7b cv.minu.b s4,s4,s4 + 14: 29ff9ffb cv.minu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-b-pass.s b/gas/testsuite/gas/riscv/cv-minu-b-pass.s new file mode 100644 index 00000000000..1ac118bd7bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.b x0, x0, x0 + cv.minu.b x1, x1, x1 + cv.minu.b x2, x2, x2 + cv.minu.b x8, x8, x8 + cv.minu.b x20, x20, x20 + cv.minu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-h-fail.d b/gas/testsuite/gas/riscv/cv-minu-h-fail.d new file mode 100644 index 00000000000..30eb8d7f13c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-h-fail.s +#error_output: cv-minu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-h-fail.l b/gas/testsuite/gas/riscv/cv-minu-h-fail.l new file mode 100644 index 00000000000..8916337969a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.h x32,x32,x32' +.*: Error: illegal operands `cv.minu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-h-fail.s b/gas/testsuite/gas/riscv/cv-minu-h-fail.s new file mode 100644 index 00000000000..eb1bd42d06c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.h x32, x32, x32 + cv.minu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-h-pass.d b/gas/testsuite/gas/riscv/cv-minu-h-pass.d new file mode 100644 index 00000000000..5522f4a041d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800007b cv.minu.h zero,zero,zero + 4: 281080fb cv.minu.h ra,ra,ra + 8: 2821017b cv.minu.h sp,sp,sp + c: 2884047b cv.minu.h s0,s0,s0 + 10: 294a0a7b cv.minu.h s4,s4,s4 + 14: 29ff8ffb cv.minu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-h-pass.s b/gas/testsuite/gas/riscv/cv-minu-h-pass.s new file mode 100644 index 00000000000..3c5dbaa63b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.h x0, x0, x0 + cv.minu.h x1, x1, x1 + cv.minu.h x2, x2, x2 + cv.minu.h x8, x8, x8 + cv.minu.h x20, x20, x20 + cv.minu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d new file mode 100644 index 00000000000..5519811ec4e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-b-fail.s +#error_output: cv-minu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l new file mode 100644 index 00000000000..de8c2c89c0e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.minu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s new file mode 100644 index 00000000000..720480b15ed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.sc.b x32, x32, x32 + cv.minu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d new file mode 100644 index 00000000000..d800c269321 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800507b cv.minu.sc.b zero,zero,zero + 4: 2810d0fb cv.minu.sc.b ra,ra,ra + 8: 2821517b cv.minu.sc.b sp,sp,sp + c: 2884547b cv.minu.sc.b s0,s0,s0 + 10: 294a5a7b cv.minu.sc.b s4,s4,s4 + 14: 29ffdffb cv.minu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s new file mode 100644 index 00000000000..3b88a467e27 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.sc.b x0, x0, x0 + cv.minu.sc.b x1, x1, x1 + cv.minu.sc.b x2, x2, x2 + cv.minu.sc.b x8, x8, x8 + cv.minu.sc.b x20, x20, x20 + cv.minu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d new file mode 100644 index 00000000000..a6be722a223 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-h-fail.s +#error_output: cv-minu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l new file mode 100644 index 00000000000..9d66f906a9f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.minu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s new file mode 100644 index 00000000000..5f421663ad7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.sc.h x32, x32, x32 + cv.minu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d new file mode 100644 index 00000000000..cc3029308d5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800407b cv.minu.sc.h zero,zero,zero + 4: 2810c0fb cv.minu.sc.h ra,ra,ra + 8: 2821417b cv.minu.sc.h sp,sp,sp + c: 2884447b cv.minu.sc.h s0,s0,s0 + 10: 294a4a7b cv.minu.sc.h s4,s4,s4 + 14: 29ffcffb cv.minu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s new file mode 100644 index 00000000000..9e752f49385 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.sc.h x0, x0, x0 + cv.minu.sc.h x1, x1, x1 + cv.minu.sc.h x2, x2, x2 + cv.minu.sc.h x8, x8, x8 + cv.minu.sc.h x20, x20, x20 + cv.minu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d new file mode 100644 index 00000000000..1e4119399d6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-b-fail.s +#error_output: cv-minu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l new file mode 100644 index 00000000000..b881f032a13 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.minu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s new file mode 100644 index 00000000000..7ff265eaab5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.minu.sci.b x32, x32, 20 + cv.minu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.minu.sci.b x6, x7, -33 + cv.minu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d new file mode 100644 index 00000000000..9dbb758022e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2940707b cv.minu.sci.b zero,zero,20 + 4: 2940f0fb cv.minu.sci.b ra,ra,20 + 8: 2941717b cv.minu.sci.b sp,sp,20 + c: 2944747b cv.minu.sci.b s0,s0,20 + 10: 294a7a7b cv.minu.sci.b s4,s4,20 + 14: 294ffffb cv.minu.sci.b t6,t6,20 + 18: 2a03f37b cv.minu.sci.b t1,t2,-32 + 1c: 2803f37b cv.minu.sci.b t1,t2,0 + 20: 29f3f37b cv.minu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s new file mode 100644 index 00000000000..4316d1ba725 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.minu.sci.b x0, x0, 20 + cv.minu.sci.b x1, x1, 20 + cv.minu.sci.b x2, x2, 20 + cv.minu.sci.b x8, x8, 20 + cv.minu.sci.b x20, x20, 20 + cv.minu.sci.b x31, x31, 20 + #Immediate Values Test + cv.minu.sci.b x6, x7, -32 + cv.minu.sci.b x6, x7, 0 + cv.minu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d new file mode 100644 index 00000000000..f4f2ce69164 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-h-fail.s +#error_output: cv-minu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l new file mode 100644 index 00000000000..480d2900468 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.minu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s new file mode 100644 index 00000000000..b166efe6960 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.minu.sci.h x32, x32, 20 + cv.minu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.minu.sci.h x6, x7, -33 + cv.minu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d new file mode 100644 index 00000000000..c54d5ba7304 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2940607b cv.minu.sci.h zero,zero,20 + 4: 2940e0fb cv.minu.sci.h ra,ra,20 + 8: 2941617b cv.minu.sci.h sp,sp,20 + c: 2944647b cv.minu.sci.h s0,s0,20 + 10: 294a6a7b cv.minu.sci.h s4,s4,20 + 14: 294feffb cv.minu.sci.h t6,t6,20 + 18: 2a03e37b cv.minu.sci.h t1,t2,-32 + 1c: 2803e37b cv.minu.sci.h t1,t2,0 + 20: 29f3e37b cv.minu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s new file mode 100644 index 00000000000..5511e0dc273 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.minu.sci.h x0, x0, 20 + cv.minu.sci.h x1, x1, 20 + cv.minu.sci.h x2, x2, 20 + cv.minu.sci.h x8, x8, 20 + cv.minu.sci.h x20, x20, 20 + cv.minu.sci.h x31, x31, 20 + #Immediate Values Test + cv.minu.sci.h x6, x7, -32 + cv.minu.sci.h x6, x7, 0 + cv.minu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-or-b-fail.d b/gas/testsuite/gas/riscv/cv-or-b-fail.d new file mode 100644 index 00000000000..a36c9666892 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-b-fail.s +#error_output: cv-or-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-b-fail.l b/gas/testsuite/gas/riscv/cv-or-b-fail.l new file mode 100644 index 00000000000..b74c77f5aec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.b x32,x32,x32' +.*: Error: illegal operands `cv.or.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-b-fail.s b/gas/testsuite/gas/riscv/cv-or-b-fail.s new file mode 100644 index 00000000000..d0d81f550d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.b x32, x32, x32 + cv.or.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-b-pass.d b/gas/testsuite/gas/riscv/cv-or-b-pass.d new file mode 100644 index 00000000000..81699ae29c6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800107b cv.or.b zero,zero,zero + 4: 581090fb cv.or.b ra,ra,ra + 8: 5821117b cv.or.b sp,sp,sp + c: 5884147b cv.or.b s0,s0,s0 + 10: 594a1a7b cv.or.b s4,s4,s4 + 14: 59ff9ffb cv.or.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-b-pass.s b/gas/testsuite/gas/riscv/cv-or-b-pass.s new file mode 100644 index 00000000000..95155723eb2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.b x0, x0, x0 + cv.or.b x1, x1, x1 + cv.or.b x2, x2, x2 + cv.or.b x8, x8, x8 + cv.or.b x20, x20, x20 + cv.or.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-h-fail.d b/gas/testsuite/gas/riscv/cv-or-h-fail.d new file mode 100644 index 00000000000..124aaf29591 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-h-fail.s +#error_output: cv-or-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-h-fail.l b/gas/testsuite/gas/riscv/cv-or-h-fail.l new file mode 100644 index 00000000000..d0c6c34792e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.h x32,x32,x32' +.*: Error: illegal operands `cv.or.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-h-fail.s b/gas/testsuite/gas/riscv/cv-or-h-fail.s new file mode 100644 index 00000000000..b3b72199264 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.h x32, x32, x32 + cv.or.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-h-pass.d b/gas/testsuite/gas/riscv/cv-or-h-pass.d new file mode 100644 index 00000000000..4ba2ffc3cdb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800007b cv.or.h zero,zero,zero + 4: 581080fb cv.or.h ra,ra,ra + 8: 5821017b cv.or.h sp,sp,sp + c: 5884047b cv.or.h s0,s0,s0 + 10: 594a0a7b cv.or.h s4,s4,s4 + 14: 59ff8ffb cv.or.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-h-pass.s b/gas/testsuite/gas/riscv/cv-or-h-pass.s new file mode 100644 index 00000000000..f53d5025440 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.h x0, x0, x0 + cv.or.h x1, x1, x1 + cv.or.h x2, x2, x2 + cv.or.h x8, x8, x8 + cv.or.h x20, x20, x20 + cv.or.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.d new file mode 100644 index 00000000000..f2c713b076c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-b-fail.s +#error_output: cv-or-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.l new file mode 100644 index 00000000000..91efc3051a4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.or.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.s new file mode 100644 index 00000000000..672faf0a6b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.sc.b x32, x32, x32 + cv.or.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.d new file mode 100644 index 00000000000..70bcf754c34 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800507b cv.or.sc.b zero,zero,zero + 4: 5810d0fb cv.or.sc.b ra,ra,ra + 8: 5821517b cv.or.sc.b sp,sp,sp + c: 5884547b cv.or.sc.b s0,s0,s0 + 10: 594a5a7b cv.or.sc.b s4,s4,s4 + 14: 59ffdffb cv.or.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.s new file mode 100644 index 00000000000..69829e57b21 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.sc.b x0, x0, x0 + cv.or.sc.b x1, x1, x1 + cv.or.sc.b x2, x2, x2 + cv.or.sc.b x8, x8, x8 + cv.or.sc.b x20, x20, x20 + cv.or.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.d new file mode 100644 index 00000000000..3a2293c4d2d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-h-fail.s +#error_output: cv-or-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.l new file mode 100644 index 00000000000..18e64bd956a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.or.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.s new file mode 100644 index 00000000000..b3f8574ba52 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.sc.h x32, x32, x32 + cv.or.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.d new file mode 100644 index 00000000000..aed2f98951f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800407b cv.or.sc.h zero,zero,zero + 4: 5810c0fb cv.or.sc.h ra,ra,ra + 8: 5821417b cv.or.sc.h sp,sp,sp + c: 5884447b cv.or.sc.h s0,s0,s0 + 10: 594a4a7b cv.or.sc.h s4,s4,s4 + 14: 59ffcffb cv.or.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.s new file mode 100644 index 00000000000..611d7bbf55d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.sc.h x0, x0, x0 + cv.or.sc.h x1, x1, x1 + cv.or.sc.h x2, x2, x2 + cv.or.sc.h x8, x8, x8 + cv.or.sc.h x20, x20, x20 + cv.or.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.d new file mode 100644 index 00000000000..d7c2b50a442 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-b-fail.s +#error_output: cv-or-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.l new file mode 100644 index 00000000000..475ea370e42 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sci.b x32,x32,20' +.*: Error: illegal operands `cv.or.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.s new file mode 100644 index 00000000000..27cc046d5d7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.or.sci.b x32, x32, 20 + cv.or.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.or.sci.b x6, x7, -33 + cv.or.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.d new file mode 100644 index 00000000000..cd8b8e29f3e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5940707b cv.or.sci.b zero,zero,20 + 4: 5940f0fb cv.or.sci.b ra,ra,20 + 8: 5941717b cv.or.sci.b sp,sp,20 + c: 5944747b cv.or.sci.b s0,s0,20 + 10: 594a7a7b cv.or.sci.b s4,s4,20 + 14: 594ffffb cv.or.sci.b t6,t6,20 + 18: 5a03f37b cv.or.sci.b t1,t2,-32 + 1c: 5803f37b cv.or.sci.b t1,t2,0 + 20: 59f3f37b cv.or.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.s new file mode 100644 index 00000000000..36c55cf5e75 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.or.sci.b x0, x0, 20 + cv.or.sci.b x1, x1, 20 + cv.or.sci.b x2, x2, 20 + cv.or.sci.b x8, x8, 20 + cv.or.sci.b x20, x20, 20 + cv.or.sci.b x31, x31, 20 + #Immediate Values Test + cv.or.sci.b x6, x7, -32 + cv.or.sci.b x6, x7, 0 + cv.or.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.d new file mode 100644 index 00000000000..80c5eb228f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-h-fail.s +#error_output: cv-or-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.l new file mode 100644 index 00000000000..691d6d4354b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sci.h x32,x32,20' +.*: Error: illegal operands `cv.or.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.s new file mode 100644 index 00000000000..178bc1b8069 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.or.sci.h x32, x32, 20 + cv.or.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.or.sci.h x6, x7, -33 + cv.or.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.d new file mode 100644 index 00000000000..dc50e444125 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5940607b cv.or.sci.h zero,zero,20 + 4: 5940e0fb cv.or.sci.h ra,ra,20 + 8: 5941617b cv.or.sci.h sp,sp,20 + c: 5944647b cv.or.sci.h s0,s0,20 + 10: 594a6a7b cv.or.sci.h s4,s4,20 + 14: 594feffb cv.or.sci.h t6,t6,20 + 18: 5a03e37b cv.or.sci.h t1,t2,-32 + 1c: 5803e37b cv.or.sci.h t1,t2,0 + 20: 59f3e37b cv.or.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.s new file mode 100644 index 00000000000..1fc6f304a71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.or.sci.h x0, x0, 20 + cv.or.sci.h x1, x1, 20 + cv.or.sci.h x2, x2, 20 + cv.or.sci.h x8, x8, 20 + cv.or.sci.h x20, x20, 20 + cv.or.sci.h x31, x31, 20 + #Immediate Values Test + cv.or.sci.h x6, x7, -32 + cv.or.sci.h x6, x7, 0 + cv.or.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-pack-fail.d b/gas/testsuite/gas/riscv/cv-pack-fail.d new file mode 100644 index 00000000000..2a11f1f3361 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-fail.s +#error_output: cv-pack-fail.l diff --git a/gas/testsuite/gas/riscv/cv-pack-fail.l b/gas/testsuite/gas/riscv/cv-pack-fail.l new file mode 100644 index 00000000000..9668f1f40c0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.pack x32,x32,x32' +.*: Error: illegal operands `cv.pack x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-pack-fail.s b/gas/testsuite/gas/riscv/cv-pack-fail.s new file mode 100644 index 00000000000..caf3ed7e0bc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.pack x32, x32, x32 + cv.pack x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-pack-h-fail.d b/gas/testsuite/gas/riscv/cv-pack-h-fail.d new file mode 100644 index 00000000000..d84b22e0f7b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-h-fail.s +#error_output: cv-pack-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-pack-h-fail.l b/gas/testsuite/gas/riscv/cv-pack-h-fail.l new file mode 100644 index 00000000000..db35aa977f5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.pack.h x32,x32,x32' +.*: Error: illegal operands `cv.pack.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-pack-h-fail.s b/gas/testsuite/gas/riscv/cv-pack-h-fail.s new file mode 100644 index 00000000000..1b360c55e1d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.pack.h x32, x32, x32 + cv.pack.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-pack-h-pass.d b/gas/testsuite/gas/riscv/cv-pack-h-pass.d new file mode 100644 index 00000000000..962a02a6cc2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: f200007b cv.pack.h zero,zero,zero + 4: f21080fb cv.pack.h ra,ra,ra + 8: f221017b cv.pack.h sp,sp,sp + c: f284047b cv.pack.h s0,s0,s0 + 10: f34a0a7b cv.pack.h s4,s4,s4 + 14: f3ff8ffb cv.pack.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-pack-h-pass.s b/gas/testsuite/gas/riscv/cv-pack-h-pass.s new file mode 100644 index 00000000000..5b06ec1f4fa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.pack.h x0, x0, x0 + cv.pack.h x1, x1, x1 + cv.pack.h x2, x2, x2 + cv.pack.h x8, x8, x8 + cv.pack.h x20, x20, x20 + cv.pack.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-pack-pass.d b/gas/testsuite/gas/riscv/cv-pack-pass.d new file mode 100644 index 00000000000..15d4bfdad81 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: f000007b cv.pack zero,zero,zero + 4: f01080fb cv.pack ra,ra,ra + 8: f021017b cv.pack sp,sp,sp + c: f084047b cv.pack s0,s0,s0 + 10: f14a0a7b cv.pack s4,s4,s4 + 14: f1ff8ffb cv.pack t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-pack-pass.s b/gas/testsuite/gas/riscv/cv-pack-pass.s new file mode 100644 index 00000000000..bde466c1507 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.pack x0, x0, x0 + cv.pack x1, x1, x1 + cv.pack x2, x2, x2 + cv.pack x8, x8, x8 + cv.pack x20, x20, x20 + cv.pack x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-fail.d b/gas/testsuite/gas/riscv/cv-packhi-b-fail.d new file mode 100644 index 00000000000..b347ddc7a1a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packhi-b-fail.s +#error_output: cv-packhi-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-fail.l b/gas/testsuite/gas/riscv/cv-packhi-b-fail.l new file mode 100644 index 00000000000..60cc30ac241 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.packhi.b x32,x32,x32' +.*: Error: illegal operands `cv.packhi.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-fail.s b/gas/testsuite/gas/riscv/cv-packhi-b-fail.s new file mode 100644 index 00000000000..43b6fc82d34 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.packhi.b x32, x32, x32 + cv.packhi.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-pass.d b/gas/testsuite/gas/riscv/cv-packhi-b-pass.d new file mode 100644 index 00000000000..638bb3d1c06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packhi-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: fa00107b cv.packhi.b zero,zero,zero + 4: fa1090fb cv.packhi.b ra,ra,ra + 8: fa21117b cv.packhi.b sp,sp,sp + c: fa84147b cv.packhi.b s0,s0,s0 + 10: fb4a1a7b cv.packhi.b s4,s4,s4 + 14: fbff9ffb cv.packhi.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-pass.s b/gas/testsuite/gas/riscv/cv-packhi-b-pass.s new file mode 100644 index 00000000000..c3a3eebf6c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.packhi.b x0, x0, x0 + cv.packhi.b x1, x1, x1 + cv.packhi.b x2, x2, x2 + cv.packhi.b x8, x8, x8 + cv.packhi.b x20, x20, x20 + cv.packhi.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-fail.d b/gas/testsuite/gas/riscv/cv-packlo-b-fail.d new file mode 100644 index 00000000000..235071eb605 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packlo-b-fail.s +#error_output: cv-packlo-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-fail.l b/gas/testsuite/gas/riscv/cv-packlo-b-fail.l new file mode 100644 index 00000000000..1141174e9e7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.packlo.b x32,x32,x32' +.*: Error: illegal operands `cv.packlo.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-fail.s b/gas/testsuite/gas/riscv/cv-packlo-b-fail.s new file mode 100644 index 00000000000..f39d1ec4faf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.packlo.b x32, x32, x32 + cv.packlo.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-pass.d b/gas/testsuite/gas/riscv/cv-packlo-b-pass.d new file mode 100644 index 00000000000..e45be0c06c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packlo-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: f800107b cv.packlo.b zero,zero,zero + 4: f81090fb cv.packlo.b ra,ra,ra + 8: f821117b cv.packlo.b sp,sp,sp + c: f884147b cv.packlo.b s0,s0,s0 + 10: f94a1a7b cv.packlo.b s4,s4,s4 + 14: f9ff9ffb cv.packlo.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-pass.s b/gas/testsuite/gas/riscv/cv-packlo-b-pass.s new file mode 100644 index 00000000000..9d2a067d3f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.packlo.b x0, x0, x0 + cv.packlo.b x1, x1, x1 + cv.packlo.b x2, x2, x2 + cv.packlo.b x8, x8, x8 + cv.packlo.b x20, x20, x20 + cv.packlo.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d new file mode 100644 index 00000000000..08b17291d28 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-b-fail.s +#error_output: cv-sdotsp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l new file mode 100644 index 00000000000..0171aeac5ed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s new file mode 100644 index 00000000000..2521ee9a886 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.b x32, x32, x32 + cv.sdotsp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d new file mode 100644 index 00000000000..467e7d61600 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800107b cv.sdotsp.b zero,zero,zero + 4: a81090fb cv.sdotsp.b ra,ra,ra + 8: a821117b cv.sdotsp.b sp,sp,sp + c: a884147b cv.sdotsp.b s0,s0,s0 + 10: a94a1a7b cv.sdotsp.b s4,s4,s4 + 14: a9ff9ffb cv.sdotsp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s new file mode 100644 index 00000000000..bf1a7c60eaa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.b x0, x0, x0 + cv.sdotsp.b x1, x1, x1 + cv.sdotsp.b x2, x2, x2 + cv.sdotsp.b x8, x8, x8 + cv.sdotsp.b x20, x20, x20 + cv.sdotsp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d new file mode 100644 index 00000000000..b274d93a817 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-h-fail.s +#error_output: cv-sdotsp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l new file mode 100644 index 00000000000..ae9b66816ae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s new file mode 100644 index 00000000000..067436e8dec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.h x32, x32, x32 + cv.sdotsp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d new file mode 100644 index 00000000000..c428f207831 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800007b cv.sdotsp.h zero,zero,zero + 4: a81080fb cv.sdotsp.h ra,ra,ra + 8: a821017b cv.sdotsp.h sp,sp,sp + c: a884047b cv.sdotsp.h s0,s0,s0 + 10: a94a0a7b cv.sdotsp.h s4,s4,s4 + 14: a9ff8ffb cv.sdotsp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s new file mode 100644 index 00000000000..90efc5b978f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.h x0, x0, x0 + cv.sdotsp.h x1, x1, x1 + cv.sdotsp.h x2, x2, x2 + cv.sdotsp.h x8, x8, x8 + cv.sdotsp.h x20, x20, x20 + cv.sdotsp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d new file mode 100644 index 00000000000..f941a1cf8a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-b-fail.s +#error_output: cv-sdotsp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l new file mode 100644 index 00000000000..020979b381c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s new file mode 100644 index 00000000000..5cd494400c0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.sc.b x32, x32, x32 + cv.sdotsp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d new file mode 100644 index 00000000000..0da4f1a9a66 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800507b cv.sdotsp.sc.b zero,zero,zero + 4: a810d0fb cv.sdotsp.sc.b ra,ra,ra + 8: a821517b cv.sdotsp.sc.b sp,sp,sp + c: a884547b cv.sdotsp.sc.b s0,s0,s0 + 10: a94a5a7b cv.sdotsp.sc.b s4,s4,s4 + 14: a9ffdffb cv.sdotsp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s new file mode 100644 index 00000000000..98e6f5acbbc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.sc.b x0, x0, x0 + cv.sdotsp.sc.b x1, x1, x1 + cv.sdotsp.sc.b x2, x2, x2 + cv.sdotsp.sc.b x8, x8, x8 + cv.sdotsp.sc.b x20, x20, x20 + cv.sdotsp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d new file mode 100644 index 00000000000..467a1636ea5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-h-fail.s +#error_output: cv-sdotsp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l new file mode 100644 index 00000000000..8a24210b195 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s new file mode 100644 index 00000000000..4a73a6e09fc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.sc.h x32, x32, x32 + cv.sdotsp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d new file mode 100644 index 00000000000..3f16823cc43 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800407b cv.sdotsp.sc.h zero,zero,zero + 4: a810c0fb cv.sdotsp.sc.h ra,ra,ra + 8: a821417b cv.sdotsp.sc.h sp,sp,sp + c: a884447b cv.sdotsp.sc.h s0,s0,s0 + 10: a94a4a7b cv.sdotsp.sc.h s4,s4,s4 + 14: a9ffcffb cv.sdotsp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s new file mode 100644 index 00000000000..ad3fac3fc20 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.sc.h x0, x0, x0 + cv.sdotsp.sc.h x1, x1, x1 + cv.sdotsp.sc.h x2, x2, x2 + cv.sdotsp.sc.h x8, x8, x8 + cv.sdotsp.sc.h x20, x20, x20 + cv.sdotsp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d new file mode 100644 index 00000000000..bccf1d0f53f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-b-fail.s +#error_output: cv-sdotsp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l new file mode 100644 index 00000000000..39f53beb9c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sdotsp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s new file mode 100644 index 00000000000..b79605e65f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotsp.sci.b x32, x32, 20 + cv.sdotsp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotsp.sci.b x6, x7, -33 + cv.sdotsp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d new file mode 100644 index 00000000000..b55aa3be231 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a940707b cv.sdotsp.sci.b zero,zero,20 + 4: a940f0fb cv.sdotsp.sci.b ra,ra,20 + 8: a941717b cv.sdotsp.sci.b sp,sp,20 + c: a944747b cv.sdotsp.sci.b s0,s0,20 + 10: a94a7a7b cv.sdotsp.sci.b s4,s4,20 + 14: a94ffffb cv.sdotsp.sci.b t6,t6,20 + 18: aa03f37b cv.sdotsp.sci.b t1,t2,-32 + 1c: a803f37b cv.sdotsp.sci.b t1,t2,0 + 20: a9f3f37b cv.sdotsp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s new file mode 100644 index 00000000000..c9aab8e0628 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotsp.sci.b x0, x0, 20 + cv.sdotsp.sci.b x1, x1, 20 + cv.sdotsp.sci.b x2, x2, 20 + cv.sdotsp.sci.b x8, x8, 20 + cv.sdotsp.sci.b x20, x20, 20 + cv.sdotsp.sci.b x31, x31, 20 + #Immediate Values Test + cv.sdotsp.sci.b x6, x7, -32 + cv.sdotsp.sci.b x6, x7, 0 + cv.sdotsp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d new file mode 100644 index 00000000000..87c79a3689a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-h-fail.s +#error_output: cv-sdotsp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l new file mode 100644 index 00000000000..28dda486916 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sdotsp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s new file mode 100644 index 00000000000..eb0788db611 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotsp.sci.h x32, x32, 20 + cv.sdotsp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotsp.sci.h x6, x7, -33 + cv.sdotsp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d new file mode 100644 index 00000000000..e16cf6117b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a940607b cv.sdotsp.sci.h zero,zero,20 + 4: a940e0fb cv.sdotsp.sci.h ra,ra,20 + 8: a941617b cv.sdotsp.sci.h sp,sp,20 + c: a944647b cv.sdotsp.sci.h s0,s0,20 + 10: a94a6a7b cv.sdotsp.sci.h s4,s4,20 + 14: a94feffb cv.sdotsp.sci.h t6,t6,20 + 18: aa03e37b cv.sdotsp.sci.h t1,t2,-32 + 1c: a803e37b cv.sdotsp.sci.h t1,t2,0 + 20: a9f3e37b cv.sdotsp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s new file mode 100644 index 00000000000..7af38caf002 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotsp.sci.h x0, x0, 20 + cv.sdotsp.sci.h x1, x1, 20 + cv.sdotsp.sci.h x2, x2, 20 + cv.sdotsp.sci.h x8, x8, 20 + cv.sdotsp.sci.h x20, x20, 20 + cv.sdotsp.sci.h x31, x31, 20 + #Immediate Values Test + cv.sdotsp.sci.h x6, x7, -32 + cv.sdotsp.sci.h x6, x7, 0 + cv.sdotsp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.d new file mode 100644 index 00000000000..b3ed1484eef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-b-fail.s +#error_output: cv-sdotup-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.l new file mode 100644 index 00000000000..0230952e061 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.s new file mode 100644 index 00000000000..b92684acf74 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.b x32, x32, x32 + cv.sdotup.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.d new file mode 100644 index 00000000000..382c0e91d35 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800107b cv.sdotup.b zero,zero,zero + 4: 981090fb cv.sdotup.b ra,ra,ra + 8: 9821117b cv.sdotup.b sp,sp,sp + c: 9884147b cv.sdotup.b s0,s0,s0 + 10: 994a1a7b cv.sdotup.b s4,s4,s4 + 14: 99ff9ffb cv.sdotup.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.s new file mode 100644 index 00000000000..eacf6e1293b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.b x0, x0, x0 + cv.sdotup.b x1, x1, x1 + cv.sdotup.b x2, x2, x2 + cv.sdotup.b x8, x8, x8 + cv.sdotup.b x20, x20, x20 + cv.sdotup.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.d new file mode 100644 index 00000000000..d7dec516ad0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-h-fail.s +#error_output: cv-sdotup-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.l new file mode 100644 index 00000000000..cb56228f18c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.s new file mode 100644 index 00000000000..cff83cba145 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.h x32, x32, x32 + cv.sdotup.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.d new file mode 100644 index 00000000000..d217a953196 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800007b cv.sdotup.h zero,zero,zero + 4: 981080fb cv.sdotup.h ra,ra,ra + 8: 9821017b cv.sdotup.h sp,sp,sp + c: 9884047b cv.sdotup.h s0,s0,s0 + 10: 994a0a7b cv.sdotup.h s4,s4,s4 + 14: 99ff8ffb cv.sdotup.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.s new file mode 100644 index 00000000000..cacaa1cdcb8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.h x0, x0, x0 + cv.sdotup.h x1, x1, x1 + cv.sdotup.h x2, x2, x2 + cv.sdotup.h x8, x8, x8 + cv.sdotup.h x20, x20, x20 + cv.sdotup.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d new file mode 100644 index 00000000000..7cdaab2e6e5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-b-fail.s +#error_output: cv-sdotup-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l new file mode 100644 index 00000000000..79ebb6da0ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s new file mode 100644 index 00000000000..2fbae1c01b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.sc.b x32, x32, x32 + cv.sdotup.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d new file mode 100644 index 00000000000..16d7bbcc7ad --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800507b cv.sdotup.sc.b zero,zero,zero + 4: 9810d0fb cv.sdotup.sc.b ra,ra,ra + 8: 9821517b cv.sdotup.sc.b sp,sp,sp + c: 9884547b cv.sdotup.sc.b s0,s0,s0 + 10: 994a5a7b cv.sdotup.sc.b s4,s4,s4 + 14: 99ffdffb cv.sdotup.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s new file mode 100644 index 00000000000..3164734bea0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.sc.b x0, x0, x0 + cv.sdotup.sc.b x1, x1, x1 + cv.sdotup.sc.b x2, x2, x2 + cv.sdotup.sc.b x8, x8, x8 + cv.sdotup.sc.b x20, x20, x20 + cv.sdotup.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d new file mode 100644 index 00000000000..3f669623dfa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-h-fail.s +#error_output: cv-sdotup-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l new file mode 100644 index 00000000000..c770ee8f30d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s new file mode 100644 index 00000000000..9fac8b86bd8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.sc.h x32, x32, x32 + cv.sdotup.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d new file mode 100644 index 00000000000..65ae56d45e0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800407b cv.sdotup.sc.h zero,zero,zero + 4: 9810c0fb cv.sdotup.sc.h ra,ra,ra + 8: 9821417b cv.sdotup.sc.h sp,sp,sp + c: 9884447b cv.sdotup.sc.h s0,s0,s0 + 10: 994a4a7b cv.sdotup.sc.h s4,s4,s4 + 14: 99ffcffb cv.sdotup.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s new file mode 100644 index 00000000000..605c165e4f5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.sc.h x0, x0, x0 + cv.sdotup.sc.h x1, x1, x1 + cv.sdotup.sc.h x2, x2, x2 + cv.sdotup.sc.h x8, x8, x8 + cv.sdotup.sc.h x20, x20, x20 + cv.sdotup.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d new file mode 100644 index 00000000000..38d6910ef12 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-b-fail.s +#error_output: cv-sdotup-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l new file mode 100644 index 00000000000..59ef235acbd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sdotup.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s new file mode 100644 index 00000000000..b3f13638f7b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotup.sci.b x32, x32, 20 + cv.sdotup.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotup.sci.b x6, x7, -33 + cv.sdotup.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d new file mode 100644 index 00000000000..d0137bfd8f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9940707b cv.sdotup.sci.b zero,zero,20 + 4: 9940f0fb cv.sdotup.sci.b ra,ra,20 + 8: 9941717b cv.sdotup.sci.b sp,sp,20 + c: 9944747b cv.sdotup.sci.b s0,s0,20 + 10: 994a7a7b cv.sdotup.sci.b s4,s4,20 + 14: 994ffffb cv.sdotup.sci.b t6,t6,20 + 18: 9a03f37b cv.sdotup.sci.b t1,t2,-32 + 1c: 9803f37b cv.sdotup.sci.b t1,t2,0 + 20: 99f3f37b cv.sdotup.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s new file mode 100644 index 00000000000..71629e42109 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotup.sci.b x0, x0, 20 + cv.sdotup.sci.b x1, x1, 20 + cv.sdotup.sci.b x2, x2, 20 + cv.sdotup.sci.b x8, x8, 20 + cv.sdotup.sci.b x20, x20, 20 + cv.sdotup.sci.b x31, x31, 20 + #Immediate Values Test + cv.sdotup.sci.b x6, x7, -32 + cv.sdotup.sci.b x6, x7, 0 + cv.sdotup.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d new file mode 100644 index 00000000000..6c9fdc096c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-h-fail.s +#error_output: cv-sdotup-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l new file mode 100644 index 00000000000..88518d8c272 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sdotup.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s new file mode 100644 index 00000000000..acf23f7b495 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotup.sci.h x32, x32, 20 + cv.sdotup.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotup.sci.h x6, x7, -33 + cv.sdotup.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d new file mode 100644 index 00000000000..ea4790bcf32 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9940607b cv.sdotup.sci.h zero,zero,20 + 4: 9940e0fb cv.sdotup.sci.h ra,ra,20 + 8: 9941617b cv.sdotup.sci.h sp,sp,20 + c: 9944647b cv.sdotup.sci.h s0,s0,20 + 10: 994a6a7b cv.sdotup.sci.h s4,s4,20 + 14: 994feffb cv.sdotup.sci.h t6,t6,20 + 18: 9a03e37b cv.sdotup.sci.h t1,t2,-32 + 1c: 9803e37b cv.sdotup.sci.h t1,t2,0 + 20: 99f3e37b cv.sdotup.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s new file mode 100644 index 00000000000..72813fb4cb7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotup.sci.h x0, x0, 20 + cv.sdotup.sci.h x1, x1, 20 + cv.sdotup.sci.h x2, x2, 20 + cv.sdotup.sci.h x8, x8, 20 + cv.sdotup.sci.h x20, x20, 20 + cv.sdotup.sci.h x31, x31, 20 + #Immediate Values Test + cv.sdotup.sci.h x6, x7, -32 + cv.sdotup.sci.h x6, x7, 0 + cv.sdotup.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d new file mode 100644 index 00000000000..e49347475aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-b-fail.s +#error_output: cv-sdotusp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l new file mode 100644 index 00000000000..7488a3d54a6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s new file mode 100644 index 00000000000..be0791d85eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.b x32, x32, x32 + cv.sdotusp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d new file mode 100644 index 00000000000..100f465159d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000107b cv.sdotusp.b zero,zero,zero + 4: a01090fb cv.sdotusp.b ra,ra,ra + 8: a021117b cv.sdotusp.b sp,sp,sp + c: a084147b cv.sdotusp.b s0,s0,s0 + 10: a14a1a7b cv.sdotusp.b s4,s4,s4 + 14: a1ff9ffb cv.sdotusp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s new file mode 100644 index 00000000000..413c4a2f8aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.b x0, x0, x0 + cv.sdotusp.b x1, x1, x1 + cv.sdotusp.b x2, x2, x2 + cv.sdotusp.b x8, x8, x8 + cv.sdotusp.b x20, x20, x20 + cv.sdotusp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d new file mode 100644 index 00000000000..0280c032c8d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-h-fail.s +#error_output: cv-sdotusp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l new file mode 100644 index 00000000000..82883936dea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s new file mode 100644 index 00000000000..403423840fb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.h x32, x32, x32 + cv.sdotusp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d new file mode 100644 index 00000000000..91a91e0f4af --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000007b cv.sdotusp.h zero,zero,zero + 4: a01080fb cv.sdotusp.h ra,ra,ra + 8: a021017b cv.sdotusp.h sp,sp,sp + c: a084047b cv.sdotusp.h s0,s0,s0 + 10: a14a0a7b cv.sdotusp.h s4,s4,s4 + 14: a1ff8ffb cv.sdotusp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s new file mode 100644 index 00000000000..4a00c3f01af --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.h x0, x0, x0 + cv.sdotusp.h x1, x1, x1 + cv.sdotusp.h x2, x2, x2 + cv.sdotusp.h x8, x8, x8 + cv.sdotusp.h x20, x20, x20 + cv.sdotusp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d new file mode 100644 index 00000000000..cc58c3f07f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-b-fail.s +#error_output: cv-sdotusp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l new file mode 100644 index 00000000000..0224aea1c52 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s new file mode 100644 index 00000000000..535fe4c5eac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.sc.b x32, x32, x32 + cv.sdotusp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d new file mode 100644 index 00000000000..13adb9518cc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000507b cv.sdotusp.sc.b zero,zero,zero + 4: a010d0fb cv.sdotusp.sc.b ra,ra,ra + 8: a021517b cv.sdotusp.sc.b sp,sp,sp + c: a084547b cv.sdotusp.sc.b s0,s0,s0 + 10: a14a5a7b cv.sdotusp.sc.b s4,s4,s4 + 14: a1ffdffb cv.sdotusp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s new file mode 100644 index 00000000000..47d539c44da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.sc.b x0, x0, x0 + cv.sdotusp.sc.b x1, x1, x1 + cv.sdotusp.sc.b x2, x2, x2 + cv.sdotusp.sc.b x8, x8, x8 + cv.sdotusp.sc.b x20, x20, x20 + cv.sdotusp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.d new file mode 100644 index 00000000000..4ad59775db6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-h-fail.s +#error_output: cv-sdotusp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.l new file mode 100644 index 00000000000..9f55f7dc75d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.s new file mode 100644 index 00000000000..c4f0263f997 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.sc.h x32, x32, x32 + cv.sdotusp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.d new file mode 100644 index 00000000000..3bb37b741d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000407b cv.sdotusp.sc.h zero,zero,zero + 4: a010c0fb cv.sdotusp.sc.h ra,ra,ra + 8: a021417b cv.sdotusp.sc.h sp,sp,sp + c: a084447b cv.sdotusp.sc.h s0,s0,s0 + 10: a14a4a7b cv.sdotusp.sc.h s4,s4,s4 + 14: a1ffcffb cv.sdotusp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.s new file mode 100644 index 00000000000..789edd10728 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.sc.h x0, x0, x0 + cv.sdotusp.sc.h x1, x1, x1 + cv.sdotusp.sc.h x2, x2, x2 + cv.sdotusp.sc.h x8, x8, x8 + cv.sdotusp.sc.h x20, x20, x20 + cv.sdotusp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.d new file mode 100644 index 00000000000..699ff8a151b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-b-fail.s +#error_output: cv-sdotusp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.l new file mode 100644 index 00000000000..efd927e7658 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sdotusp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.s new file mode 100644 index 00000000000..121e86bd1f9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotusp.sci.b x32, x32, 20 + cv.sdotusp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotusp.sci.b x6, x7, -33 + cv.sdotusp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.d new file mode 100644 index 00000000000..9debb0db24d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a140707b cv.sdotusp.sci.b zero,zero,20 + 4: a140f0fb cv.sdotusp.sci.b ra,ra,20 + 8: a141717b cv.sdotusp.sci.b sp,sp,20 + c: a144747b cv.sdotusp.sci.b s0,s0,20 + 10: a14a7a7b cv.sdotusp.sci.b s4,s4,20 + 14: a14ffffb cv.sdotusp.sci.b t6,t6,20 + 18: a203f37b cv.sdotusp.sci.b t1,t2,-32 + 1c: a003f37b cv.sdotusp.sci.b t1,t2,0 + 20: a1f3f37b cv.sdotusp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.s new file mode 100644 index 00000000000..b7be1e357fe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotusp.sci.b x0, x0, 20 + cv.sdotusp.sci.b x1, x1, 20 + cv.sdotusp.sci.b x2, x2, 20 + cv.sdotusp.sci.b x8, x8, 20 + cv.sdotusp.sci.b x20, x20, 20 + cv.sdotusp.sci.b x31, x31, 20 + #Immediate Values Test + cv.sdotusp.sci.b x6, x7, -32 + cv.sdotusp.sci.b x6, x7, 0 + cv.sdotusp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.d new file mode 100644 index 00000000000..2057999f8f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-h-fail.s +#error_output: cv-sdotusp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.l new file mode 100644 index 00000000000..abc1063c15d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sdotusp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.s new file mode 100644 index 00000000000..df2e3e328bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotusp.sci.h x32, x32, 20 + cv.sdotusp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotusp.sci.h x6, x7, -33 + cv.sdotusp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.d new file mode 100644 index 00000000000..57d536bc8b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a140607b cv.sdotusp.sci.h zero,zero,20 + 4: a140e0fb cv.sdotusp.sci.h ra,ra,20 + 8: a141617b cv.sdotusp.sci.h sp,sp,20 + c: a144647b cv.sdotusp.sci.h s0,s0,20 + 10: a14a6a7b cv.sdotusp.sci.h s4,s4,20 + 14: a14feffb cv.sdotusp.sci.h t6,t6,20 + 18: a203e37b cv.sdotusp.sci.h t1,t2,-32 + 1c: a003e37b cv.sdotusp.sci.h t1,t2,0 + 20: a1f3e37b cv.sdotusp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.s new file mode 100644 index 00000000000..fd6631e1c9f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotusp.sci.h x0, x0, 20 + cv.sdotusp.sci.h x1, x1, 20 + cv.sdotusp.sci.h x2, x2, 20 + cv.sdotusp.sci.h x8, x8, 20 + cv.sdotusp.sci.h x20, x20, 20 + cv.sdotusp.sci.h x31, x31, 20 + #Immediate Values Test + cv.sdotusp.sci.h x6, x7, -32 + cv.sdotusp.sci.h x6, x7, 0 + cv.sdotusp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-fail.d b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.d new file mode 100644 index 00000000000..89c0537333a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-b-fail.s +#error_output: cv-shuffle-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-fail.l b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.l new file mode 100644 index 00000000000..6ccb07a2a96 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle.b x32,x32,x32' +.*: Error: illegal operands `cv.shuffle.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-fail.s b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.s new file mode 100644 index 00000000000..f5a24b2af55 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle.b x32, x32, x32 + cv.shuffle.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-pass.d b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.d new file mode 100644 index 00000000000..242717f219d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c000107b cv.shuffle.b zero,zero,zero + 4: c01090fb cv.shuffle.b ra,ra,ra + 8: c021117b cv.shuffle.b sp,sp,sp + c: c084147b cv.shuffle.b s0,s0,s0 + 10: c14a1a7b cv.shuffle.b s4,s4,s4 + 14: c1ff9ffb cv.shuffle.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-pass.s b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.s new file mode 100644 index 00000000000..e908ad5b1e7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle.b x0, x0, x0 + cv.shuffle.b x1, x1, x1 + cv.shuffle.b x2, x2, x2 + cv.shuffle.b x8, x8, x8 + cv.shuffle.b x20, x20, x20 + cv.shuffle.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-fail.d b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.d new file mode 100644 index 00000000000..eb7b53e8b72 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-h-fail.s +#error_output: cv-shuffle-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-fail.l b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.l new file mode 100644 index 00000000000..28004f29675 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle.h x32,x32,x32' +.*: Error: illegal operands `cv.shuffle.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-fail.s b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.s new file mode 100644 index 00000000000..91a805eb945 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle.h x32, x32, x32 + cv.shuffle.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-pass.d b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.d new file mode 100644 index 00000000000..30ac7fa6762 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c000007b cv.shuffle.h zero,zero,zero + 4: c01080fb cv.shuffle.h ra,ra,ra + 8: c021017b cv.shuffle.h sp,sp,sp + c: c084047b cv.shuffle.h s0,s0,s0 + 10: c14a0a7b cv.shuffle.h s4,s4,s4 + 14: c1ff8ffb cv.shuffle.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-pass.s b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.s new file mode 100644 index 00000000000..08afc2bab54 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle.h x0, x0, x0 + cv.shuffle.h x1, x1, x1 + cv.shuffle.h x2, x2, x2 + cv.shuffle.h x8, x8, x8 + cv.shuffle.h x20, x20, x20 + cv.shuffle.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d new file mode 100644 index 00000000000..c23adb87e92 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-sci-h-fail.s +#error_output: cv-shuffle-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l new file mode 100644 index 00000000000..abb30d18eac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle.sci.h x32,x32,20' +.*: Error: illegal operands `cv.shuffle.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s new file mode 100644 index 00000000000..5095a035ccb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shuffle.sci.h x32, x32, 20 + cv.shuffle.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.shuffle.sci.h x6, x7, -33 + cv.shuffle.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d new file mode 100644 index 00000000000..30e5c4360c0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c140607b cv.shuffle.sci.h zero,zero,20 + 4: c140e0fb cv.shuffle.sci.h ra,ra,20 + 8: c141617b cv.shuffle.sci.h sp,sp,20 + c: c144647b cv.shuffle.sci.h s0,s0,20 + 10: c14a6a7b cv.shuffle.sci.h s4,s4,20 + 14: c14feffb cv.shuffle.sci.h t6,t6,20 + 18: c203e37b cv.shuffle.sci.h t1,t2,-32 + 1c: c003e37b cv.shuffle.sci.h t1,t2,0 + 20: c1f3e37b cv.shuffle.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s new file mode 100644 index 00000000000..01ff538f999 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shuffle.sci.h x0, x0, 20 + cv.shuffle.sci.h x1, x1, 20 + cv.shuffle.sci.h x2, x2, 20 + cv.shuffle.sci.h x8, x8, 20 + cv.shuffle.sci.h x20, x20, 20 + cv.shuffle.sci.h x31, x31, 20 + #Immediate Values Test + cv.shuffle.sci.h x6, x7, -32 + cv.shuffle.sci.h x6, x7, 0 + cv.shuffle.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d new file mode 100644 index 00000000000..824204ac1cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-b-fail.s +#error_output: cv-shuffle2-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l new file mode 100644 index 00000000000..94e47f7f8c7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle2.b x32,x32,x32' +.*: Error: illegal operands `cv.shuffle2.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s new file mode 100644 index 00000000000..23f1a259697 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle2.b x32, x32, x32 + cv.shuffle2.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d new file mode 100644 index 00000000000..2d21409fe2d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: e000107b cv.shuffle2.b zero,zero,zero + 4: e01090fb cv.shuffle2.b ra,ra,ra + 8: e021117b cv.shuffle2.b sp,sp,sp + c: e084147b cv.shuffle2.b s0,s0,s0 + 10: e14a1a7b cv.shuffle2.b s4,s4,s4 + 14: e1ff9ffb cv.shuffle2.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s new file mode 100644 index 00000000000..e4e58940ccc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle2.b x0, x0, x0 + cv.shuffle2.b x1, x1, x1 + cv.shuffle2.b x2, x2, x2 + cv.shuffle2.b x8, x8, x8 + cv.shuffle2.b x20, x20, x20 + cv.shuffle2.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d new file mode 100644 index 00000000000..6ae6bdc1808 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-h-fail.s +#error_output: cv-shuffle2-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l new file mode 100644 index 00000000000..31b69598bbf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle2.h x32,x32,x32' +.*: Error: illegal operands `cv.shuffle2.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s new file mode 100644 index 00000000000..96ba440aa64 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle2.h x32, x32, x32 + cv.shuffle2.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d new file mode 100644 index 00000000000..307d6b3554d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: e000007b cv.shuffle2.h zero,zero,zero + 4: e01080fb cv.shuffle2.h ra,ra,ra + 8: e021017b cv.shuffle2.h sp,sp,sp + c: e084047b cv.shuffle2.h s0,s0,s0 + 10: e14a0a7b cv.shuffle2.h s4,s4,s4 + 14: e1ff8ffb cv.shuffle2.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s new file mode 100644 index 00000000000..f3a2ba29bf1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle2.h x0, x0, x0 + cv.shuffle2.h x1, x1, x1 + cv.shuffle2.h x2, x2, x2 + cv.shuffle2.h x8, x8, x8 + cv.shuffle2.h x20, x20, x20 + cv.shuffle2.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d new file mode 100644 index 00000000000..7e736b6b8b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei0-sci-b-fail.s +#error_output: cv-shufflei0-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l new file mode 100644 index 00000000000..fb52a536487 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei0.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei0.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s new file mode 100644 index 00000000000..26c2dcf17e7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei0.sci.b x32, x32, 20 + cv.shufflei0.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei0.sci.b x6, x7, -33 + cv.shufflei0.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d new file mode 100644 index 00000000000..71ed14ce210 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei0-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c140707b cv.shufflei0.sci.b zero,zero,20 + 4: c140f0fb cv.shufflei0.sci.b ra,ra,20 + 8: c141717b cv.shufflei0.sci.b sp,sp,20 + c: c144747b cv.shufflei0.sci.b s0,s0,20 + 10: c14a7a7b cv.shufflei0.sci.b s4,s4,20 + 14: c14ffffb cv.shufflei0.sci.b t6,t6,20 + 18: c203f37b cv.shufflei0.sci.b t1,t2,-32 + 1c: c003f37b cv.shufflei0.sci.b t1,t2,0 + 20: c1f3f37b cv.shufflei0.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s new file mode 100644 index 00000000000..c9d8f466a46 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei0.sci.b x0, x0, 20 + cv.shufflei0.sci.b x1, x1, 20 + cv.shufflei0.sci.b x2, x2, 20 + cv.shufflei0.sci.b x8, x8, 20 + cv.shufflei0.sci.b x20, x20, 20 + cv.shufflei0.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei0.sci.b x6, x7, -32 + cv.shufflei0.sci.b x6, x7, 0 + cv.shufflei0.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d new file mode 100644 index 00000000000..cf94a12cf86 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei1-sci-b-fail.s +#error_output: cv-shufflei1-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l new file mode 100644 index 00000000000..169d3c7aece --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei1.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei1.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s new file mode 100644 index 00000000000..b7ef3dfb6f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei1.sci.b x32, x32, 20 + cv.shufflei1.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei1.sci.b x6, x7, -33 + cv.shufflei1.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d new file mode 100644 index 00000000000..a28668d6839 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei1-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c940707b cv.shufflei1.sci.b zero,zero,20 + 4: c940f0fb cv.shufflei1.sci.b ra,ra,20 + 8: c941717b cv.shufflei1.sci.b sp,sp,20 + c: c944747b cv.shufflei1.sci.b s0,s0,20 + 10: c94a7a7b cv.shufflei1.sci.b s4,s4,20 + 14: c94ffffb cv.shufflei1.sci.b t6,t6,20 + 18: ca03f37b cv.shufflei1.sci.b t1,t2,-32 + 1c: c803f37b cv.shufflei1.sci.b t1,t2,0 + 20: c9f3f37b cv.shufflei1.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s new file mode 100644 index 00000000000..baa3cb425d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei1.sci.b x0, x0, 20 + cv.shufflei1.sci.b x1, x1, 20 + cv.shufflei1.sci.b x2, x2, 20 + cv.shufflei1.sci.b x8, x8, 20 + cv.shufflei1.sci.b x20, x20, 20 + cv.shufflei1.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei1.sci.b x6, x7, -32 + cv.shufflei1.sci.b x6, x7, 0 + cv.shufflei1.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d new file mode 100644 index 00000000000..33aa9b2f899 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei2-sci-b-fail.s +#error_output: cv-shufflei2-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l new file mode 100644 index 00000000000..590f202b88e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei2.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei2.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s new file mode 100644 index 00000000000..bad60f50862 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei2.sci.b x32, x32, 20 + cv.shufflei2.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei2.sci.b x6, x7, -33 + cv.shufflei2.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d new file mode 100644 index 00000000000..b4c0d294109 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei2-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: d140707b cv.shufflei2.sci.b zero,zero,20 + 4: d140f0fb cv.shufflei2.sci.b ra,ra,20 + 8: d141717b cv.shufflei2.sci.b sp,sp,20 + c: d144747b cv.shufflei2.sci.b s0,s0,20 + 10: d14a7a7b cv.shufflei2.sci.b s4,s4,20 + 14: d14ffffb cv.shufflei2.sci.b t6,t6,20 + 18: d203f37b cv.shufflei2.sci.b t1,t2,-32 + 1c: d003f37b cv.shufflei2.sci.b t1,t2,0 + 20: d1f3f37b cv.shufflei2.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s new file mode 100644 index 00000000000..0f46dae4e14 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei2.sci.b x0, x0, 20 + cv.shufflei2.sci.b x1, x1, 20 + cv.shufflei2.sci.b x2, x2, 20 + cv.shufflei2.sci.b x8, x8, 20 + cv.shufflei2.sci.b x20, x20, 20 + cv.shufflei2.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei2.sci.b x6, x7, -32 + cv.shufflei2.sci.b x6, x7, 0 + cv.shufflei2.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d new file mode 100644 index 00000000000..c8ee036ed97 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei3-sci-b-fail.s +#error_output: cv-shufflei3-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l new file mode 100644 index 00000000000..159e85df289 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei3.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei3.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s new file mode 100644 index 00000000000..0908a1b04f8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei3.sci.b x32, x32, 20 + cv.shufflei3.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei3.sci.b x6, x7, -33 + cv.shufflei3.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d new file mode 100644 index 00000000000..7b9603c4dce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei3-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: d940707b cv.shufflei3.sci.b zero,zero,20 + 4: d940f0fb cv.shufflei3.sci.b ra,ra,20 + 8: d941717b cv.shufflei3.sci.b sp,sp,20 + c: d944747b cv.shufflei3.sci.b s0,s0,20 + 10: d94a7a7b cv.shufflei3.sci.b s4,s4,20 + 14: d94ffffb cv.shufflei3.sci.b t6,t6,20 + 18: da03f37b cv.shufflei3.sci.b t1,t2,-32 + 1c: d803f37b cv.shufflei3.sci.b t1,t2,0 + 20: d9f3f37b cv.shufflei3.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s new file mode 100644 index 00000000000..086e8935215 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei3.sci.b x0, x0, 20 + cv.shufflei3.sci.b x1, x1, 20 + cv.shufflei3.sci.b x2, x2, 20 + cv.shufflei3.sci.b x8, x8, 20 + cv.shufflei3.sci.b x20, x20, 20 + cv.shufflei3.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei3.sci.b x6, x7, -32 + cv.shufflei3.sci.b x6, x7, 0 + cv.shufflei3.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.d b/gas/testsuite/gas/riscv/cv-simd-march-fail.d new file mode 100644 index 00000000000..4ae0a97b4ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: cv-simd-march-fail.s +#error_output: cv-simd-march-fail.l diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.l b/gas/testsuite/gas/riscv/cv-simd-march-fail.l new file mode 100644 index 00000000000..efebaa5208b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.l @@ -0,0 +1,221 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `cv.add.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.abs.h x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.abs.b x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extract.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extract.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extractu.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extractu.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.insert.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.insert.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei0.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei1.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei2.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei3.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle2.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle2.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.pack x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.pack.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.packhi.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.packlo.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxconj x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.s b/gas/testsuite/gas/riscv/cv-simd-march-fail.s new file mode 100644 index 00000000000..a63586918cd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.s @@ -0,0 +1,221 @@ +target: + cv.add.h x5, x6, x7 + cv.add.b x5, x6, x7 + cv.add.sc.h x5, x6, x7 + cv.add.sc.b x5, x6, x7 + cv.add.sci.h x6, x7, 20 + cv.add.sci.b x6, x7, 20 + cv.sub.h x5, x6, x7 + cv.sub.b x5, x6, x7 + cv.sub.sc.h x5, x6, x7 + cv.sub.sc.b x5, x6, x7 + cv.sub.sci.h x6, x7, 20 + cv.sub.sci.b x6, x7, 20 + cv.avg.h x5, x6, x7 + cv.avg.b x5, x6, x7 + cv.avg.sc.h x5, x6, x7 + cv.avg.sc.b x5, x6, x7 + cv.avg.sci.h x6, x7, 20 + cv.avg.sci.b x6, x7, 20 + cv.avgu.h x5, x6, x7 + cv.avgu.b x5, x6, x7 + cv.avgu.sc.h x5, x6, x7 + cv.avgu.sc.b x5, x6, x7 + cv.avgu.sci.h x6, x7, 20 + cv.avgu.sci.b x6, x7, 20 + cv.min.h x5, x6, x7 + cv.min.b x5, x6, x7 + cv.min.sc.h x5, x6, x7 + cv.min.sc.b x5, x6, x7 + cv.min.sci.h x6, x7, 20 + cv.min.sci.b x6, x7, 20 + cv.minu.h x5, x6, x7 + cv.minu.b x5, x6, x7 + cv.minu.sc.h x5, x6, x7 + cv.minu.sc.b x5, x6, x7 + cv.minu.sci.h x6, x7, 20 + cv.minu.sci.b x6, x7, 20 + cv.max.h x5, x6, x7 + cv.max.b x5, x6, x7 + cv.max.sc.h x5, x6, x7 + cv.max.sc.b x5, x6, x7 + cv.max.sci.h x6, x7, 20 + cv.max.sci.b x6, x7, 20 + cv.maxu.h x5, x6, x7 + cv.maxu.b x5, x6, x7 + cv.maxu.sc.h x5, x6, x7 + cv.maxu.sc.b x5, x6, x7 + cv.maxu.sci.h x6, x7, 20 + cv.maxu.sci.b x6, x7, 20 + cv.srl.h x5, x6, x7 + cv.srl.b x5, x6, x7 + cv.srl.sc.h x5, x6, x7 + cv.srl.sc.b x5, x6, x7 + cv.srl.sci.h x6, x7, 20 + cv.srl.sci.b x6, x7, 20 + cv.sra.h x5, x6, x7 + cv.sra.b x5, x6, x7 + cv.sra.sc.h x5, x6, x7 + cv.sra.sc.b x5, x6, x7 + cv.sra.sci.h x6, x7, 20 + cv.sra.sci.b x6, x7, 20 + cv.sll.h x5, x6, x7 + cv.sll.b x5, x6, x7 + cv.sll.sc.h x5, x6, x7 + cv.sll.sc.b x5, x6, x7 + cv.sll.sci.h x6, x7, 20 + cv.sll.sci.b x6, x7, 20 + cv.or.h x5, x6, x7 + cv.or.b x5, x6, x7 + cv.or.sc.h x5, x6, x7 + cv.or.sc.b x5, x6, x7 + cv.or.sci.h x6, x7, 20 + cv.or.sci.b x6, x7, 20 + cv.xor.h x5, x6, x7 + cv.xor.b x5, x6, x7 + cv.xor.sc.h x5, x6, x7 + cv.xor.sc.b x5, x6, x7 + cv.xor.sci.h x6, x7, 20 + cv.xor.sci.b x6, x7, 20 + cv.and.h x5, x6, x7 + cv.and.b x5, x6, x7 + cv.and.sc.h x5, x6, x7 + cv.and.sc.b x5, x6, x7 + cv.and.sci.h x6, x7, 20 + cv.and.sci.b x6, x7, 20 + cv.abs.h x6, x7 + cv.abs.b x6, x7 + cv.dotup.h x5, x6, x7 + cv.dotup.b x5, x6, x7 + cv.dotup.sc.h x5, x6, x7 + cv.dotup.sc.b x5, x6, x7 + cv.dotup.sci.h x6, x7, 20 + cv.dotup.sci.b x6, x7, 20 + cv.dotusp.h x5, x6, x7 + cv.dotusp.b x5, x6, x7 + cv.dotusp.sc.h x5, x6, x7 + cv.dotusp.sc.b x5, x6, x7 + cv.dotusp.sci.h x6, x7, 20 + cv.dotusp.sci.b x6, x7, 20 + cv.dotsp.h x5, x6, x7 + cv.dotsp.b x5, x6, x7 + cv.dotsp.sc.h x5, x6, x7 + cv.dotsp.sc.b x5, x6, x7 + cv.dotsp.sci.h x6, x7, 20 + cv.dotsp.sci.b x6, x7, 20 + cv.sdotup.h x5, x6, x7 + cv.sdotup.b x5, x6, x7 + cv.sdotup.sc.h x5, x6, x7 + cv.sdotup.sc.b x5, x6, x7 + cv.sdotup.sci.h x6, x7, 20 + cv.sdotup.sci.b x6, x7, 20 + cv.sdotusp.h x5, x6, x7 + cv.sdotusp.b x5, x6, x7 + cv.sdotusp.sc.h x5, x6, x7 + cv.sdotusp.sc.b x5, x6, x7 + cv.sdotusp.sci.h x6, x7, 20 + cv.sdotusp.sci.b x6, x7, 20 + cv.sdotsp.h x5, x6, x7 + cv.sdotsp.b x5, x6, x7 + cv.sdotsp.sc.h x5, x6, x7 + cv.sdotsp.sc.b x5, x6, x7 + cv.sdotsp.sci.h x6, x7, 20 + cv.sdotsp.sci.b x6, x7, 20 + cv.extract.h x6, x7, 20 + cv.extract.b x6, x7, 20 + cv.extractu.h x6, x7, 20 + cv.extractu.b x6, x7, 20 + cv.insert.h x6, x7, 20 + cv.insert.b x6, x7, 20 + cv.shuffle.h x5, x6, x7 + cv.shuffle.b x5, x6, x7 + cv.shuffle.sci.h x6, x7, 20 + cv.shufflei0.sci.b x6, x7, 20 + cv.shufflei1.sci.b x6, x7, 20 + cv.shufflei2.sci.b x6, x7, 20 + cv.shufflei3.sci.b x6, x7, 20 + cv.shuffle2.h x5, x6, x7 + cv.shuffle2.b x5, x6, x7 + cv.pack x5, x6, x7 + cv.pack.h x5, x6, x7 + cv.packhi.b x5, x6, x7 + cv.packlo.b x5, x6, x7 + cv.cmpeq.h x5, x6, x7 + cv.cmpeq.b x5, x6, x7 + cv.cmpeq.sc.h x5, x6, x7 + cv.cmpeq.sc.b x5, x6, x7 + cv.cmpeq.sci.h x6, x7, 20 + cv.cmpeq.sci.b x6, x7, 20 + cv.cmpne.h x5, x6, x7 + cv.cmpne.b x5, x6, x7 + cv.cmpne.sc.h x5, x6, x7 + cv.cmpne.sc.b x5, x6, x7 + cv.cmpne.sci.h x6, x7, 20 + cv.cmpne.sci.b x6, x7, 20 + cv.cmpgt.h x5, x6, x7 + cv.cmpgt.b x5, x6, x7 + cv.cmpgt.sc.h x5, x6, x7 + cv.cmpgt.sc.b x5, x6, x7 + cv.cmpgt.sci.h x6, x7, 20 + cv.cmpgt.sci.b x6, x7, 20 + cv.cmpge.h x5, x6, x7 + cv.cmpge.b x5, x6, x7 + cv.cmpge.sc.h x5, x6, x7 + cv.cmpge.sc.b x5, x6, x7 + cv.cmpge.sci.h x6, x7, 20 + cv.cmpge.sci.b x6, x7, 20 + cv.cmplt.h x5, x6, x7 + cv.cmplt.b x5, x6, x7 + cv.cmplt.sc.h x5, x6, x7 + cv.cmplt.sc.b x5, x6, x7 + cv.cmplt.sci.h x6, x7, 20 + cv.cmplt.sci.b x6, x7, 20 + cv.cmple.h x5, x6, x7 + cv.cmple.b x5, x6, x7 + cv.cmple.sc.h x5, x6, x7 + cv.cmple.sc.b x5, x6, x7 + cv.cmple.sci.h x6, x7, 20 + cv.cmple.sci.b x6, x7, 20 + cv.cmpgtu.h x5, x6, x7 + cv.cmpgtu.b x5, x6, x7 + cv.cmpgtu.sc.h x5, x6, x7 + cv.cmpgtu.sc.b x5, x6, x7 + cv.cmpgtu.sci.h x6, x7, 20 + cv.cmpgtu.sci.b x6, x7, 20 + cv.cmpgeu.h x5, x6, x7 + cv.cmpgeu.b x5, x6, x7 + cv.cmpgeu.sc.h x5, x6, x7 + cv.cmpgeu.sc.b x5, x6, x7 + cv.cmpgeu.sci.h x6, x7, 20 + cv.cmpgeu.sci.b x6, x7, 20 + cv.cmpltu.h x5, x6, x7 + cv.cmpltu.b x5, x6, x7 + cv.cmpltu.sc.h x5, x6, x7 + cv.cmpltu.sc.b x5, x6, x7 + cv.cmpltu.sci.h x6, x7, 20 + cv.cmpltu.sci.b x6, x7, 20 + cv.cmpleu.h x5, x6, x7 + cv.cmpleu.b x5, x6, x7 + cv.cmpleu.sc.h x5, x6, x7 + cv.cmpleu.sc.b x5, x6, x7 + cv.cmpleu.sci.h x6, x7, 20 + cv.cmpleu.sci.b x6, x7, 20 + cv.cplxmul.r x5, x6, x7 + cv.cplxmul.i x5, x6, x7 + cv.cplxmul.r.div2 x5, x6, x7 + cv.cplxmul.i.div2 x5, x6, x7 + cv.cplxmul.r.div4 x5, x6, x7 + cv.cplxmul.i.div4 x5, x6, x7 + cv.cplxmul.r.div8 x5, x6, x7 + cv.cplxmul.i.div8 x5, x6, x7 + cv.cplxconj x6, x7 + cv.subrotmj x5, x6, x7 + cv.subrotmj.div2 x5, x6, x7 + cv.subrotmj.div4 x5, x6, x7 + cv.subrotmj.div8 x5, x6, x7 + cv.add.div2 x5, x6, x7 + cv.add.div4 x5, x6, x7 + cv.add.div8 x5, x6, x7 + cv.sub.div2 x5, x6, x7 + cv.sub.div4 x5, x6, x7 + cv.sub.div8 x5, x6, x7 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorev.d b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.d new file mode 100644 index 00000000000..fd2437b0bed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.d @@ -0,0 +1,230 @@ +#as: -march=rv32i_xcorev1p0 +#source: cv-simd-march-xcorev.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+007302fb[ ]+cv.add.h t0,t1,t2 +[ ]+4:[ ]+007312fb[ ]+cv.add.b t0,t1,t2 +[ ]+8:[ ]+007342fb[ ]+cv.add.sc.h t0,t1,t2 +[ ]+c:[ ]+007352fb[ ]+cv.add.sc.b t0,t1,t2 +[ ]+10:[ ]+0143e37b[ ]+cv.add.sci.h t1,t2,20 +[ ]+14:[ ]+0143f37b[ ]+cv.add.sci.b t1,t2,20 +[ ]+18:[ ]+087302fb[ ]+cv.sub.h t0,t1,t2 +[ ]+1c:[ ]+087312fb[ ]+cv.sub.b t0,t1,t2 +[ ]+20:[ ]+087342fb[ ]+cv.sub.sc.h t0,t1,t2 +[ ]+24:[ ]+087352fb[ ]+cv.sub.sc.b t0,t1,t2 +[ ]+28:[ ]+0943e37b[ ]+cv.sub.sci.h t1,t2,20 +[ ]+2c:[ ]+0943f37b[ ]+cv.sub.sci.b t1,t2,20 +[ ]+30:[ ]+107302fb[ ]+cv.avg.h t0,t1,t2 +[ ]+34:[ ]+107312fb[ ]+cv.avg.b t0,t1,t2 +[ ]+38:[ ]+107342fb[ ]+cv.avg.sc.h t0,t1,t2 +[ ]+3c:[ ]+107352fb[ ]+cv.avg.sc.b t0,t1,t2 +[ ]+40:[ ]+1143e37b[ ]+cv.avg.sci.h t1,t2,20 +[ ]+44:[ ]+1143f37b[ ]+cv.avg.sci.b t1,t2,20 +[ ]+48:[ ]+187302fb[ ]+cv.avgu.h t0,t1,t2 +[ ]+4c:[ ]+187312fb[ ]+cv.avgu.b t0,t1,t2 +[ ]+50:[ ]+187342fb[ ]+cv.avgu.sc.h t0,t1,t2 +[ ]+54:[ ]+187352fb[ ]+cv.avgu.sc.b t0,t1,t2 +[ ]+58:[ ]+1943e37b[ ]+cv.avgu.sci.h t1,t2,20 +[ ]+5c:[ ]+1943f37b[ ]+cv.avgu.sci.b t1,t2,20 +[ ]+60:[ ]+207302fb[ ]+cv.min.h t0,t1,t2 +[ ]+64:[ ]+207312fb[ ]+cv.min.b t0,t1,t2 +[ ]+68:[ ]+207342fb[ ]+cv.min.sc.h t0,t1,t2 +[ ]+6c:[ ]+207352fb[ ]+cv.min.sc.b t0,t1,t2 +[ ]+70:[ ]+2143e37b[ ]+cv.min.sci.h t1,t2,20 +[ ]+74:[ ]+2143f37b[ ]+cv.min.sci.b t1,t2,20 +[ ]+78:[ ]+287302fb[ ]+cv.minu.h t0,t1,t2 +[ ]+7c:[ ]+287312fb[ ]+cv.minu.b t0,t1,t2 +[ ]+80:[ ]+287342fb[ ]+cv.minu.sc.h t0,t1,t2 +[ ]+84:[ ]+287352fb[ ]+cv.minu.sc.b t0,t1,t2 +[ ]+88:[ ]+2943e37b[ ]+cv.minu.sci.h t1,t2,20 +[ ]+8c:[ ]+2943f37b[ ]+cv.minu.sci.b t1,t2,20 +[ ]+90:[ ]+307302fb[ ]+cv.max.h t0,t1,t2 +[ ]+94:[ ]+307312fb[ ]+cv.max.b t0,t1,t2 +[ ]+98:[ ]+307342fb[ ]+cv.max.sc.h t0,t1,t2 +[ ]+9c:[ ]+307352fb[ ]+cv.max.sc.b t0,t1,t2 +[ ]+a0:[ ]+3143e37b[ ]+cv.max.sci.h t1,t2,20 +[ ]+a4:[ ]+3143f37b[ ]+cv.max.sci.b t1,t2,20 +[ ]+a8:[ ]+387302fb[ ]+cv.maxu.h t0,t1,t2 +[ ]+ac:[ ]+387312fb[ ]+cv.maxu.b t0,t1,t2 +[ ]+b0:[ ]+387342fb[ ]+cv.maxu.sc.h t0,t1,t2 +[ ]+b4:[ ]+387352fb[ ]+cv.maxu.sc.b t0,t1,t2 +[ ]+b8:[ ]+3943e37b[ ]+cv.maxu.sci.h t1,t2,20 +[ ]+bc:[ ]+3943f37b[ ]+cv.maxu.sci.b t1,t2,20 +[ ]+c0:[ ]+407302fb[ ]+cv.srl.h t0,t1,t2 +[ ]+c4:[ ]+407312fb[ ]+cv.srl.b t0,t1,t2 +[ ]+c8:[ ]+407342fb[ ]+cv.srl.sc.h t0,t1,t2 +[ ]+cc:[ ]+407352fb[ ]+cv.srl.sc.b t0,t1,t2 +[ ]+d0:[ ]+4143e37b[ ]+cv.srl.sci.h t1,t2,20 +[ ]+d4:[ ]+4143f37b[ ]+cv.srl.sci.b t1,t2,20 +[ ]+d8:[ ]+487302fb[ ]+cv.sra.h t0,t1,t2 +[ ]+dc:[ ]+487312fb[ ]+cv.sra.b t0,t1,t2 +[ ]+e0:[ ]+487342fb[ ]+cv.sra.sc.h t0,t1,t2 +[ ]+e4:[ ]+487352fb[ ]+cv.sra.sc.b t0,t1,t2 +[ ]+e8:[ ]+4943e37b[ ]+cv.sra.sci.h t1,t2,20 +[ ]+ec:[ ]+4943f37b[ ]+cv.sra.sci.b t1,t2,20 +[ ]+f0:[ ]+507302fb[ ]+cv.sll.h t0,t1,t2 +[ ]+f4:[ ]+507312fb[ ]+cv.sll.b t0,t1,t2 +[ ]+f8:[ ]+507342fb[ ]+cv.sll.sc.h t0,t1,t2 +[ ]+fc:[ ]+507352fb[ ]+cv.sll.sc.b t0,t1,t2 +[ ]+100:[ ]+5143e37b[ ]+cv.sll.sci.h t1,t2,20 +[ ]+104:[ ]+5143f37b[ ]+cv.sll.sci.b t1,t2,20 +[ ]+108:[ ]+587302fb[ ]+cv.or.h t0,t1,t2 +[ ]+10c:[ ]+587312fb[ ]+cv.or.b t0,t1,t2 +[ ]+110:[ ]+587342fb[ ]+cv.or.sc.h t0,t1,t2 +[ ]+114:[ ]+587352fb[ ]+cv.or.sc.b t0,t1,t2 +[ ]+118:[ ]+5943e37b[ ]+cv.or.sci.h t1,t2,20 +[ ]+11c:[ ]+5943f37b[ ]+cv.or.sci.b t1,t2,20 +[ ]+120:[ ]+607302fb[ ]+cv.xor.h t0,t1,t2 +[ ]+124:[ ]+607312fb[ ]+cv.xor.b t0,t1,t2 +[ ]+128:[ ]+607342fb[ ]+cv.xor.sc.h t0,t1,t2 +[ ]+12c:[ ]+607352fb[ ]+cv.xor.sc.b t0,t1,t2 +[ ]+130:[ ]+6143e37b[ ]+cv.xor.sci.h t1,t2,20 +[ ]+134:[ ]+6143f37b[ ]+cv.xor.sci.b t1,t2,20 +[ ]+138:[ ]+687302fb[ ]+cv.and.h t0,t1,t2 +[ ]+13c:[ ]+687312fb[ ]+cv.and.b t0,t1,t2 +[ ]+140:[ ]+687342fb[ ]+cv.and.sc.h t0,t1,t2 +[ ]+144:[ ]+687352fb[ ]+cv.and.sc.b t0,t1,t2 +[ ]+148:[ ]+6943e37b[ ]+cv.and.sci.h t1,t2,20 +[ ]+14c:[ ]+6943f37b[ ]+cv.and.sci.b t1,t2,20 +[ ]+150:[ ]+7003837b[ ]+cv.abs.h t1,t2 +[ ]+154:[ ]+7003937b[ ]+cv.abs.b t1,t2 +[ ]+158:[ ]+807302fb[ ]+cv.dotup.h t0,t1,t2 +[ ]+15c:[ ]+807312fb[ ]+cv.dotup.b t0,t1,t2 +[ ]+160:[ ]+807342fb[ ]+cv.dotup.sc.h t0,t1,t2 +[ ]+164:[ ]+807352fb[ ]+cv.dotup.sc.b t0,t1,t2 +[ ]+168:[ ]+8143e37b[ ]+cv.dotup.sci.h t1,t2,20 +[ ]+16c:[ ]+8143f37b[ ]+cv.dotup.sci.b t1,t2,20 +[ ]+170:[ ]+887302fb[ ]+cv.dotusp.h t0,t1,t2 +[ ]+174:[ ]+887312fb[ ]+cv.dotusp.b t0,t1,t2 +[ ]+178:[ ]+887342fb[ ]+cv.dotusp.sc.h t0,t1,t2 +[ ]+17c:[ ]+887352fb[ ]+cv.dotusp.sc.b t0,t1,t2 +[ ]+180:[ ]+8943e37b[ ]+cv.dotusp.sci.h t1,t2,20 +[ ]+184:[ ]+8943f37b[ ]+cv.dotusp.sci.b t1,t2,20 +[ ]+188:[ ]+907302fb[ ]+cv.dotsp.h t0,t1,t2 +[ ]+18c:[ ]+907312fb[ ]+cv.dotsp.b t0,t1,t2 +[ ]+190:[ ]+907342fb[ ]+cv.dotsp.sc.h t0,t1,t2 +[ ]+194:[ ]+907352fb[ ]+cv.dotsp.sc.b t0,t1,t2 +[ ]+198:[ ]+9143e37b[ ]+cv.dotsp.sci.h t1,t2,20 +[ ]+19c:[ ]+9143f37b[ ]+cv.dotsp.sci.b t1,t2,20 +[ ]+1a0:[ ]+987302fb[ ]+cv.sdotup.h t0,t1,t2 +[ ]+1a4:[ ]+987312fb[ ]+cv.sdotup.b t0,t1,t2 +[ ]+1a8:[ ]+987342fb[ ]+cv.sdotup.sc.h t0,t1,t2 +[ ]+1ac:[ ]+987352fb[ ]+cv.sdotup.sc.b t0,t1,t2 +[ ]+1b0:[ ]+9943e37b[ ]+cv.sdotup.sci.h t1,t2,20 +[ ]+1b4:[ ]+9943f37b[ ]+cv.sdotup.sci.b t1,t2,20 +[ ]+1b8:[ ]+a07302fb[ ]+cv.sdotusp.h t0,t1,t2 +[ ]+1bc:[ ]+a07312fb[ ]+cv.sdotusp.b t0,t1,t2 +[ ]+1c0:[ ]+a07342fb[ ]+cv.sdotusp.sc.h t0,t1,t2 +[ ]+1c4:[ ]+a07352fb[ ]+cv.sdotusp.sc.b t0,t1,t2 +[ ]+1c8:[ ]+a143e37b[ ]+cv.sdotusp.sci.h t1,t2,20 +[ ]+1cc:[ ]+a143f37b[ ]+cv.sdotusp.sci.b t1,t2,20 +[ ]+1d0:[ ]+a87302fb[ ]+cv.sdotsp.h t0,t1,t2 +[ ]+1d4:[ ]+a87312fb[ ]+cv.sdotsp.b t0,t1,t2 +[ ]+1d8:[ ]+a87342fb[ ]+cv.sdotsp.sc.h t0,t1,t2 +[ ]+1dc:[ ]+a87352fb[ ]+cv.sdotsp.sc.b t0,t1,t2 +[ ]+1e0:[ ]+a943e37b[ ]+cv.sdotsp.sci.h t1,t2,20 +[ ]+1e4:[ ]+a943f37b[ ]+cv.sdotsp.sci.b t1,t2,20 +[ ]+1e8:[ ]+b943837b[ ]+cv.extract.h t1,t2,20 +[ ]+1ec:[ ]+b943937b[ ]+cv.extract.b t1,t2,20 +[ ]+1f0:[ ]+b943a37b[ ]+cv.extractu.h t1,t2,20 +[ ]+1f4:[ ]+b943b37b[ ]+cv.extractu.b t1,t2,20 +[ ]+1f8:[ ]+b943c37b[ ]+cv.insert.h t1,t2,20 +[ ]+1fc:[ ]+b943d37b[ ]+cv.insert.b t1,t2,20 +[ ]+200:[ ]+c07302fb[ ]+cv.shuffle.h t0,t1,t2 +[ ]+204:[ ]+c07312fb[ ]+cv.shuffle.b t0,t1,t2 +[ ]+208:[ ]+c143e37b[ ]+cv.shuffle.sci.h t1,t2,20 +[ ]+20c:[ ]+c143f37b[ ]+cv.shufflei0.sci.b t1,t2,20 +[ ]+210:[ ]+c943f37b[ ]+cv.shufflei1.sci.b t1,t2,20 +[ ]+214:[ ]+d143f37b[ ]+cv.shufflei2.sci.b t1,t2,20 +[ ]+218:[ ]+d943f37b[ ]+cv.shufflei3.sci.b t1,t2,20 +[ ]+21c:[ ]+e07302fb[ ]+cv.shuffle2.h t0,t1,t2 +[ ]+220:[ ]+e07312fb[ ]+cv.shuffle2.b t0,t1,t2 +[ ]+224:[ ]+f07302fb[ ]+cv.pack t0,t1,t2 +[ ]+228:[ ]+f27302fb[ ]+cv.pack.h t0,t1,t2 +[ ]+22c:[ ]+fa7312fb[ ]+cv.packhi.b t0,t1,t2 +[ ]+230:[ ]+f87312fb[ ]+cv.packlo.b t0,t1,t2 +[ ]+234:[ ]+047302fb[ ]+cv.cmpeq.h t0,t1,t2 +[ ]+238:[ ]+047312fb[ ]+cv.cmpeq.b t0,t1,t2 +[ ]+23c:[ ]+047342fb[ ]+cv.cmpeq.sc.h t0,t1,t2 +[ ]+240:[ ]+047352fb[ ]+cv.cmpeq.sc.b t0,t1,t2 +[ ]+244:[ ]+0543e37b[ ]+cv.cmpeq.sci.h t1,t2,20 +[ ]+248:[ ]+0543f37b[ ]+cv.cmpeq.sci.b t1,t2,20 +[ ]+24c:[ ]+0c7302fb[ ]+cv.cmpne.h t0,t1,t2 +[ ]+250:[ ]+0c7312fb[ ]+cv.cmpne.b t0,t1,t2 +[ ]+254:[ ]+0c7342fb[ ]+cv.cmpne.sc.h t0,t1,t2 +[ ]+258:[ ]+0c7352fb[ ]+cv.cmpne.sc.b t0,t1,t2 +[ ]+25c:[ ]+0d43e37b[ ]+cv.cmpne.sci.h t1,t2,20 +[ ]+260:[ ]+0d43f37b[ ]+cv.cmpne.sci.b t1,t2,20 +[ ]+264:[ ]+147302fb[ ]+cv.cmpgt.h t0,t1,t2 +[ ]+268:[ ]+147312fb[ ]+cv.cmpgt.b t0,t1,t2 +[ ]+26c:[ ]+147342fb[ ]+cv.cmpgt.sc.h t0,t1,t2 +[ ]+270:[ ]+147352fb[ ]+cv.cmpgt.sc.b t0,t1,t2 +[ ]+274:[ ]+1543e37b[ ]+cv.cmpgt.sci.h t1,t2,20 +[ ]+278:[ ]+1543f37b[ ]+cv.cmpgt.sci.b t1,t2,20 +[ ]+27c:[ ]+1c7302fb[ ]+cv.cmpge.h t0,t1,t2 +[ ]+280:[ ]+1c7312fb[ ]+cv.cmpge.b t0,t1,t2 +[ ]+284:[ ]+1c7342fb[ ]+cv.cmpge.sc.h t0,t1,t2 +[ ]+288:[ ]+1c7352fb[ ]+cv.cmpge.sc.b t0,t1,t2 +[ ]+28c:[ ]+1d43e37b[ ]+cv.cmpge.sci.h t1,t2,20 +[ ]+290:[ ]+1d43f37b[ ]+cv.cmpge.sci.b t1,t2,20 +[ ]+294:[ ]+247302fb[ ]+cv.cmplt.h t0,t1,t2 +[ ]+298:[ ]+247312fb[ ]+cv.cmplt.b t0,t1,t2 +[ ]+29c:[ ]+247342fb[ ]+cv.cmplt.sc.h t0,t1,t2 +[ ]+2a0:[ ]+247352fb[ ]+cv.cmplt.sc.b t0,t1,t2 +[ ]+2a4:[ ]+2543e37b[ ]+cv.cmplt.sci.h t1,t2,20 +[ ]+2a8:[ ]+2543f37b[ ]+cv.cmplt.sci.b t1,t2,20 +[ ]+2ac:[ ]+2c7302fb[ ]+cv.cmple.h t0,t1,t2 +[ ]+2b0:[ ]+2c7312fb[ ]+cv.cmple.b t0,t1,t2 +[ ]+2b4:[ ]+2c7342fb[ ]+cv.cmple.sc.h t0,t1,t2 +[ ]+2b8:[ ]+2c7352fb[ ]+cv.cmple.sc.b t0,t1,t2 +[ ]+2bc:[ ]+2d43e37b[ ]+cv.cmple.sci.h t1,t2,20 +[ ]+2c0:[ ]+2d43f37b[ ]+cv.cmple.sci.b t1,t2,20 +[ ]+2c4:[ ]+347302fb[ ]+cv.cmpgtu.h t0,t1,t2 +[ ]+2c8:[ ]+347312fb[ ]+cv.cmpgtu.b t0,t1,t2 +[ ]+2cc:[ ]+347342fb[ ]+cv.cmpgtu.sc.h t0,t1,t2 +[ ]+2d0:[ ]+347352fb[ ]+cv.cmpgtu.sc.b t0,t1,t2 +[ ]+2d4:[ ]+3543e37b[ ]+cv.cmpgtu.sci.h t1,t2,20 +[ ]+2d8:[ ]+3543f37b[ ]+cv.cmpgtu.sci.b t1,t2,20 +[ ]+2dc:[ ]+3c7302fb[ ]+cv.cmpgeu.h t0,t1,t2 +[ ]+2e0:[ ]+3c7312fb[ ]+cv.cmpgeu.b t0,t1,t2 +[ ]+2e4:[ ]+3c7342fb[ ]+cv.cmpgeu.sc.h t0,t1,t2 +[ ]+2e8:[ ]+3c7352fb[ ]+cv.cmpgeu.sc.b t0,t1,t2 +[ ]+2ec:[ ]+3d43e37b[ ]+cv.cmpgeu.sci.h t1,t2,20 +[ ]+2f0:[ ]+3d43f37b[ ]+cv.cmpgeu.sci.b t1,t2,20 +[ ]+2f4:[ ]+447302fb[ ]+cv.cmpltu.h t0,t1,t2 +[ ]+2f8:[ ]+447312fb[ ]+cv.cmpltu.b t0,t1,t2 +[ ]+2fc:[ ]+447342fb[ ]+cv.cmpltu.sc.h t0,t1,t2 +[ ]+300:[ ]+447352fb[ ]+cv.cmpltu.sc.b t0,t1,t2 +[ ]+304:[ ]+4543e37b[ ]+cv.cmpltu.sci.h t1,t2,20 +[ ]+308:[ ]+4543f37b[ ]+cv.cmpltu.sci.b t1,t2,20 +[ ]+30c:[ ]+4c7302fb[ ]+cv.cmpleu.h t0,t1,t2 +[ ]+310:[ ]+4c7312fb[ ]+cv.cmpleu.b t0,t1,t2 +[ ]+314:[ ]+4c7342fb[ ]+cv.cmpleu.sc.h t0,t1,t2 +[ ]+318:[ ]+4c7352fb[ ]+cv.cmpleu.sc.b t0,t1,t2 +[ ]+31c:[ ]+4d43e37b[ ]+cv.cmpleu.sci.h t1,t2,20 +[ ]+320:[ ]+4d43f37b[ ]+cv.cmpleu.sci.b t1,t2,20 +[ ]+324:[ ]+547302fb[ ]+cv.cplxmul.r t0,t1,t2 +[ ]+328:[ ]+567302fb[ ]+cv.cplxmul.i t0,t1,t2 +[ ]+32c:[ ]+547322fb[ ]+cv.cplxmul.r.div2 t0,t1,t2 +[ ]+330:[ ]+567322fb[ ]+cv.cplxmul.i.div2 t0,t1,t2 +[ ]+334:[ ]+547342fb[ ]+cv.cplxmul.r.div4 t0,t1,t2 +[ ]+338:[ ]+567342fb[ ]+cv.cplxmul.i.div4 t0,t1,t2 +[ ]+33c:[ ]+547362fb[ ]+cv.cplxmul.r.div8 t0,t1,t2 +[ ]+340:[ ]+567362fb[ ]+cv.cplxmul.i.div8 t0,t1,t2 +[ ]+344:[ ]+5c03837b[ ]+cv.cplxconj t1,t2 +[ ]+348:[ ]+647302fb[ ]+cv.subrotmj t0,t1,t2 +[ ]+34c:[ ]+647322fb[ ]+cv.subrotmj.div2 t0,t1,t2 +[ ]+350:[ ]+647342fb[ ]+cv.subrotmj.div4 t0,t1,t2 +[ ]+354:[ ]+647362fb[ ]+cv.subrotmj.div8 t0,t1,t2 +[ ]+358:[ ]+6c7322fb[ ]+cv.add.div2 t0,t1,t2 +[ ]+35c:[ ]+6c7342fb[ ]+cv.add.div4 t0,t1,t2 +[ ]+360:[ ]+6c7362fb[ ]+cv.add.div8 t0,t1,t2 +[ ]+364:[ ]+747322fb[ ]+cv.sub.div2 t0,t1,t2 +[ ]+368:[ ]+747342fb[ ]+cv.sub.div4 t0,t1,t2 +[ ]+36c:[ ]+747362fb[ ]+cv.sub.div8 t0,t1,t2 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorev.s b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.s new file mode 100644 index 00000000000..a63586918cd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.s @@ -0,0 +1,221 @@ +target: + cv.add.h x5, x6, x7 + cv.add.b x5, x6, x7 + cv.add.sc.h x5, x6, x7 + cv.add.sc.b x5, x6, x7 + cv.add.sci.h x6, x7, 20 + cv.add.sci.b x6, x7, 20 + cv.sub.h x5, x6, x7 + cv.sub.b x5, x6, x7 + cv.sub.sc.h x5, x6, x7 + cv.sub.sc.b x5, x6, x7 + cv.sub.sci.h x6, x7, 20 + cv.sub.sci.b x6, x7, 20 + cv.avg.h x5, x6, x7 + cv.avg.b x5, x6, x7 + cv.avg.sc.h x5, x6, x7 + cv.avg.sc.b x5, x6, x7 + cv.avg.sci.h x6, x7, 20 + cv.avg.sci.b x6, x7, 20 + cv.avgu.h x5, x6, x7 + cv.avgu.b x5, x6, x7 + cv.avgu.sc.h x5, x6, x7 + cv.avgu.sc.b x5, x6, x7 + cv.avgu.sci.h x6, x7, 20 + cv.avgu.sci.b x6, x7, 20 + cv.min.h x5, x6, x7 + cv.min.b x5, x6, x7 + cv.min.sc.h x5, x6, x7 + cv.min.sc.b x5, x6, x7 + cv.min.sci.h x6, x7, 20 + cv.min.sci.b x6, x7, 20 + cv.minu.h x5, x6, x7 + cv.minu.b x5, x6, x7 + cv.minu.sc.h x5, x6, x7 + cv.minu.sc.b x5, x6, x7 + cv.minu.sci.h x6, x7, 20 + cv.minu.sci.b x6, x7, 20 + cv.max.h x5, x6, x7 + cv.max.b x5, x6, x7 + cv.max.sc.h x5, x6, x7 + cv.max.sc.b x5, x6, x7 + cv.max.sci.h x6, x7, 20 + cv.max.sci.b x6, x7, 20 + cv.maxu.h x5, x6, x7 + cv.maxu.b x5, x6, x7 + cv.maxu.sc.h x5, x6, x7 + cv.maxu.sc.b x5, x6, x7 + cv.maxu.sci.h x6, x7, 20 + cv.maxu.sci.b x6, x7, 20 + cv.srl.h x5, x6, x7 + cv.srl.b x5, x6, x7 + cv.srl.sc.h x5, x6, x7 + cv.srl.sc.b x5, x6, x7 + cv.srl.sci.h x6, x7, 20 + cv.srl.sci.b x6, x7, 20 + cv.sra.h x5, x6, x7 + cv.sra.b x5, x6, x7 + cv.sra.sc.h x5, x6, x7 + cv.sra.sc.b x5, x6, x7 + cv.sra.sci.h x6, x7, 20 + cv.sra.sci.b x6, x7, 20 + cv.sll.h x5, x6, x7 + cv.sll.b x5, x6, x7 + cv.sll.sc.h x5, x6, x7 + cv.sll.sc.b x5, x6, x7 + cv.sll.sci.h x6, x7, 20 + cv.sll.sci.b x6, x7, 20 + cv.or.h x5, x6, x7 + cv.or.b x5, x6, x7 + cv.or.sc.h x5, x6, x7 + cv.or.sc.b x5, x6, x7 + cv.or.sci.h x6, x7, 20 + cv.or.sci.b x6, x7, 20 + cv.xor.h x5, x6, x7 + cv.xor.b x5, x6, x7 + cv.xor.sc.h x5, x6, x7 + cv.xor.sc.b x5, x6, x7 + cv.xor.sci.h x6, x7, 20 + cv.xor.sci.b x6, x7, 20 + cv.and.h x5, x6, x7 + cv.and.b x5, x6, x7 + cv.and.sc.h x5, x6, x7 + cv.and.sc.b x5, x6, x7 + cv.and.sci.h x6, x7, 20 + cv.and.sci.b x6, x7, 20 + cv.abs.h x6, x7 + cv.abs.b x6, x7 + cv.dotup.h x5, x6, x7 + cv.dotup.b x5, x6, x7 + cv.dotup.sc.h x5, x6, x7 + cv.dotup.sc.b x5, x6, x7 + cv.dotup.sci.h x6, x7, 20 + cv.dotup.sci.b x6, x7, 20 + cv.dotusp.h x5, x6, x7 + cv.dotusp.b x5, x6, x7 + cv.dotusp.sc.h x5, x6, x7 + cv.dotusp.sc.b x5, x6, x7 + cv.dotusp.sci.h x6, x7, 20 + cv.dotusp.sci.b x6, x7, 20 + cv.dotsp.h x5, x6, x7 + cv.dotsp.b x5, x6, x7 + cv.dotsp.sc.h x5, x6, x7 + cv.dotsp.sc.b x5, x6, x7 + cv.dotsp.sci.h x6, x7, 20 + cv.dotsp.sci.b x6, x7, 20 + cv.sdotup.h x5, x6, x7 + cv.sdotup.b x5, x6, x7 + cv.sdotup.sc.h x5, x6, x7 + cv.sdotup.sc.b x5, x6, x7 + cv.sdotup.sci.h x6, x7, 20 + cv.sdotup.sci.b x6, x7, 20 + cv.sdotusp.h x5, x6, x7 + cv.sdotusp.b x5, x6, x7 + cv.sdotusp.sc.h x5, x6, x7 + cv.sdotusp.sc.b x5, x6, x7 + cv.sdotusp.sci.h x6, x7, 20 + cv.sdotusp.sci.b x6, x7, 20 + cv.sdotsp.h x5, x6, x7 + cv.sdotsp.b x5, x6, x7 + cv.sdotsp.sc.h x5, x6, x7 + cv.sdotsp.sc.b x5, x6, x7 + cv.sdotsp.sci.h x6, x7, 20 + cv.sdotsp.sci.b x6, x7, 20 + cv.extract.h x6, x7, 20 + cv.extract.b x6, x7, 20 + cv.extractu.h x6, x7, 20 + cv.extractu.b x6, x7, 20 + cv.insert.h x6, x7, 20 + cv.insert.b x6, x7, 20 + cv.shuffle.h x5, x6, x7 + cv.shuffle.b x5, x6, x7 + cv.shuffle.sci.h x6, x7, 20 + cv.shufflei0.sci.b x6, x7, 20 + cv.shufflei1.sci.b x6, x7, 20 + cv.shufflei2.sci.b x6, x7, 20 + cv.shufflei3.sci.b x6, x7, 20 + cv.shuffle2.h x5, x6, x7 + cv.shuffle2.b x5, x6, x7 + cv.pack x5, x6, x7 + cv.pack.h x5, x6, x7 + cv.packhi.b x5, x6, x7 + cv.packlo.b x5, x6, x7 + cv.cmpeq.h x5, x6, x7 + cv.cmpeq.b x5, x6, x7 + cv.cmpeq.sc.h x5, x6, x7 + cv.cmpeq.sc.b x5, x6, x7 + cv.cmpeq.sci.h x6, x7, 20 + cv.cmpeq.sci.b x6, x7, 20 + cv.cmpne.h x5, x6, x7 + cv.cmpne.b x5, x6, x7 + cv.cmpne.sc.h x5, x6, x7 + cv.cmpne.sc.b x5, x6, x7 + cv.cmpne.sci.h x6, x7, 20 + cv.cmpne.sci.b x6, x7, 20 + cv.cmpgt.h x5, x6, x7 + cv.cmpgt.b x5, x6, x7 + cv.cmpgt.sc.h x5, x6, x7 + cv.cmpgt.sc.b x5, x6, x7 + cv.cmpgt.sci.h x6, x7, 20 + cv.cmpgt.sci.b x6, x7, 20 + cv.cmpge.h x5, x6, x7 + cv.cmpge.b x5, x6, x7 + cv.cmpge.sc.h x5, x6, x7 + cv.cmpge.sc.b x5, x6, x7 + cv.cmpge.sci.h x6, x7, 20 + cv.cmpge.sci.b x6, x7, 20 + cv.cmplt.h x5, x6, x7 + cv.cmplt.b x5, x6, x7 + cv.cmplt.sc.h x5, x6, x7 + cv.cmplt.sc.b x5, x6, x7 + cv.cmplt.sci.h x6, x7, 20 + cv.cmplt.sci.b x6, x7, 20 + cv.cmple.h x5, x6, x7 + cv.cmple.b x5, x6, x7 + cv.cmple.sc.h x5, x6, x7 + cv.cmple.sc.b x5, x6, x7 + cv.cmple.sci.h x6, x7, 20 + cv.cmple.sci.b x6, x7, 20 + cv.cmpgtu.h x5, x6, x7 + cv.cmpgtu.b x5, x6, x7 + cv.cmpgtu.sc.h x5, x6, x7 + cv.cmpgtu.sc.b x5, x6, x7 + cv.cmpgtu.sci.h x6, x7, 20 + cv.cmpgtu.sci.b x6, x7, 20 + cv.cmpgeu.h x5, x6, x7 + cv.cmpgeu.b x5, x6, x7 + cv.cmpgeu.sc.h x5, x6, x7 + cv.cmpgeu.sc.b x5, x6, x7 + cv.cmpgeu.sci.h x6, x7, 20 + cv.cmpgeu.sci.b x6, x7, 20 + cv.cmpltu.h x5, x6, x7 + cv.cmpltu.b x5, x6, x7 + cv.cmpltu.sc.h x5, x6, x7 + cv.cmpltu.sc.b x5, x6, x7 + cv.cmpltu.sci.h x6, x7, 20 + cv.cmpltu.sci.b x6, x7, 20 + cv.cmpleu.h x5, x6, x7 + cv.cmpleu.b x5, x6, x7 + cv.cmpleu.sc.h x5, x6, x7 + cv.cmpleu.sc.b x5, x6, x7 + cv.cmpleu.sci.h x6, x7, 20 + cv.cmpleu.sci.b x6, x7, 20 + cv.cplxmul.r x5, x6, x7 + cv.cplxmul.i x5, x6, x7 + cv.cplxmul.r.div2 x5, x6, x7 + cv.cplxmul.i.div2 x5, x6, x7 + cv.cplxmul.r.div4 x5, x6, x7 + cv.cplxmul.i.div4 x5, x6, x7 + cv.cplxmul.r.div8 x5, x6, x7 + cv.cplxmul.i.div8 x5, x6, x7 + cv.cplxconj x6, x7 + cv.subrotmj x5, x6, x7 + cv.subrotmj.div2 x5, x6, x7 + cv.subrotmj.div4 x5, x6, x7 + cv.subrotmj.div8 x5, x6, x7 + cv.add.div2 x5, x6, x7 + cv.add.div4 x5, x6, x7 + cv.add.div8 x5, x6, x7 + cv.sub.div2 x5, x6, x7 + cv.sub.div4 x5, x6, x7 + cv.sub.div8 x5, x6, x7 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d new file mode 100644 index 00000000000..470a10e1af6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d @@ -0,0 +1,230 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-simd-march-xcorevsimd.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+007302fb[ ]+cv.add.h t0,t1,t2 +[ ]+4:[ ]+007312fb[ ]+cv.add.b t0,t1,t2 +[ ]+8:[ ]+007342fb[ ]+cv.add.sc.h t0,t1,t2 +[ ]+c:[ ]+007352fb[ ]+cv.add.sc.b t0,t1,t2 +[ ]+10:[ ]+0143e37b[ ]+cv.add.sci.h t1,t2,20 +[ ]+14:[ ]+0143f37b[ ]+cv.add.sci.b t1,t2,20 +[ ]+18:[ ]+087302fb[ ]+cv.sub.h t0,t1,t2 +[ ]+1c:[ ]+087312fb[ ]+cv.sub.b t0,t1,t2 +[ ]+20:[ ]+087342fb[ ]+cv.sub.sc.h t0,t1,t2 +[ ]+24:[ ]+087352fb[ ]+cv.sub.sc.b t0,t1,t2 +[ ]+28:[ ]+0943e37b[ ]+cv.sub.sci.h t1,t2,20 +[ ]+2c:[ ]+0943f37b[ ]+cv.sub.sci.b t1,t2,20 +[ ]+30:[ ]+107302fb[ ]+cv.avg.h t0,t1,t2 +[ ]+34:[ ]+107312fb[ ]+cv.avg.b t0,t1,t2 +[ ]+38:[ ]+107342fb[ ]+cv.avg.sc.h t0,t1,t2 +[ ]+3c:[ ]+107352fb[ ]+cv.avg.sc.b t0,t1,t2 +[ ]+40:[ ]+1143e37b[ ]+cv.avg.sci.h t1,t2,20 +[ ]+44:[ ]+1143f37b[ ]+cv.avg.sci.b t1,t2,20 +[ ]+48:[ ]+187302fb[ ]+cv.avgu.h t0,t1,t2 +[ ]+4c:[ ]+187312fb[ ]+cv.avgu.b t0,t1,t2 +[ ]+50:[ ]+187342fb[ ]+cv.avgu.sc.h t0,t1,t2 +[ ]+54:[ ]+187352fb[ ]+cv.avgu.sc.b t0,t1,t2 +[ ]+58:[ ]+1943e37b[ ]+cv.avgu.sci.h t1,t2,20 +[ ]+5c:[ ]+1943f37b[ ]+cv.avgu.sci.b t1,t2,20 +[ ]+60:[ ]+207302fb[ ]+cv.min.h t0,t1,t2 +[ ]+64:[ ]+207312fb[ ]+cv.min.b t0,t1,t2 +[ ]+68:[ ]+207342fb[ ]+cv.min.sc.h t0,t1,t2 +[ ]+6c:[ ]+207352fb[ ]+cv.min.sc.b t0,t1,t2 +[ ]+70:[ ]+2143e37b[ ]+cv.min.sci.h t1,t2,20 +[ ]+74:[ ]+2143f37b[ ]+cv.min.sci.b t1,t2,20 +[ ]+78:[ ]+287302fb[ ]+cv.minu.h t0,t1,t2 +[ ]+7c:[ ]+287312fb[ ]+cv.minu.b t0,t1,t2 +[ ]+80:[ ]+287342fb[ ]+cv.minu.sc.h t0,t1,t2 +[ ]+84:[ ]+287352fb[ ]+cv.minu.sc.b t0,t1,t2 +[ ]+88:[ ]+2943e37b[ ]+cv.minu.sci.h t1,t2,20 +[ ]+8c:[ ]+2943f37b[ ]+cv.minu.sci.b t1,t2,20 +[ ]+90:[ ]+307302fb[ ]+cv.max.h t0,t1,t2 +[ ]+94:[ ]+307312fb[ ]+cv.max.b t0,t1,t2 +[ ]+98:[ ]+307342fb[ ]+cv.max.sc.h t0,t1,t2 +[ ]+9c:[ ]+307352fb[ ]+cv.max.sc.b t0,t1,t2 +[ ]+a0:[ ]+3143e37b[ ]+cv.max.sci.h t1,t2,20 +[ ]+a4:[ ]+3143f37b[ ]+cv.max.sci.b t1,t2,20 +[ ]+a8:[ ]+387302fb[ ]+cv.maxu.h t0,t1,t2 +[ ]+ac:[ ]+387312fb[ ]+cv.maxu.b t0,t1,t2 +[ ]+b0:[ ]+387342fb[ ]+cv.maxu.sc.h t0,t1,t2 +[ ]+b4:[ ]+387352fb[ ]+cv.maxu.sc.b t0,t1,t2 +[ ]+b8:[ ]+3943e37b[ ]+cv.maxu.sci.h t1,t2,20 +[ ]+bc:[ ]+3943f37b[ ]+cv.maxu.sci.b t1,t2,20 +[ ]+c0:[ ]+407302fb[ ]+cv.srl.h t0,t1,t2 +[ ]+c4:[ ]+407312fb[ ]+cv.srl.b t0,t1,t2 +[ ]+c8:[ ]+407342fb[ ]+cv.srl.sc.h t0,t1,t2 +[ ]+cc:[ ]+407352fb[ ]+cv.srl.sc.b t0,t1,t2 +[ ]+d0:[ ]+4143e37b[ ]+cv.srl.sci.h t1,t2,20 +[ ]+d4:[ ]+4143f37b[ ]+cv.srl.sci.b t1,t2,20 +[ ]+d8:[ ]+487302fb[ ]+cv.sra.h t0,t1,t2 +[ ]+dc:[ ]+487312fb[ ]+cv.sra.b t0,t1,t2 +[ ]+e0:[ ]+487342fb[ ]+cv.sra.sc.h t0,t1,t2 +[ ]+e4:[ ]+487352fb[ ]+cv.sra.sc.b t0,t1,t2 +[ ]+e8:[ ]+4943e37b[ ]+cv.sra.sci.h t1,t2,20 +[ ]+ec:[ ]+4943f37b[ ]+cv.sra.sci.b t1,t2,20 +[ ]+f0:[ ]+507302fb[ ]+cv.sll.h t0,t1,t2 +[ ]+f4:[ ]+507312fb[ ]+cv.sll.b t0,t1,t2 +[ ]+f8:[ ]+507342fb[ ]+cv.sll.sc.h t0,t1,t2 +[ ]+fc:[ ]+507352fb[ ]+cv.sll.sc.b t0,t1,t2 +[ ]+100:[ ]+5143e37b[ ]+cv.sll.sci.h t1,t2,20 +[ ]+104:[ ]+5143f37b[ ]+cv.sll.sci.b t1,t2,20 +[ ]+108:[ ]+587302fb[ ]+cv.or.h t0,t1,t2 +[ ]+10c:[ ]+587312fb[ ]+cv.or.b t0,t1,t2 +[ ]+110:[ ]+587342fb[ ]+cv.or.sc.h t0,t1,t2 +[ ]+114:[ ]+587352fb[ ]+cv.or.sc.b t0,t1,t2 +[ ]+118:[ ]+5943e37b[ ]+cv.or.sci.h t1,t2,20 +[ ]+11c:[ ]+5943f37b[ ]+cv.or.sci.b t1,t2,20 +[ ]+120:[ ]+607302fb[ ]+cv.xor.h t0,t1,t2 +[ ]+124:[ ]+607312fb[ ]+cv.xor.b t0,t1,t2 +[ ]+128:[ ]+607342fb[ ]+cv.xor.sc.h t0,t1,t2 +[ ]+12c:[ ]+607352fb[ ]+cv.xor.sc.b t0,t1,t2 +[ ]+130:[ ]+6143e37b[ ]+cv.xor.sci.h t1,t2,20 +[ ]+134:[ ]+6143f37b[ ]+cv.xor.sci.b t1,t2,20 +[ ]+138:[ ]+687302fb[ ]+cv.and.h t0,t1,t2 +[ ]+13c:[ ]+687312fb[ ]+cv.and.b t0,t1,t2 +[ ]+140:[ ]+687342fb[ ]+cv.and.sc.h t0,t1,t2 +[ ]+144:[ ]+687352fb[ ]+cv.and.sc.b t0,t1,t2 +[ ]+148:[ ]+6943e37b[ ]+cv.and.sci.h t1,t2,20 +[ ]+14c:[ ]+6943f37b[ ]+cv.and.sci.b t1,t2,20 +[ ]+150:[ ]+7003837b[ ]+cv.abs.h t1,t2 +[ ]+154:[ ]+7003937b[ ]+cv.abs.b t1,t2 +[ ]+158:[ ]+807302fb[ ]+cv.dotup.h t0,t1,t2 +[ ]+15c:[ ]+807312fb[ ]+cv.dotup.b t0,t1,t2 +[ ]+160:[ ]+807342fb[ ]+cv.dotup.sc.h t0,t1,t2 +[ ]+164:[ ]+807352fb[ ]+cv.dotup.sc.b t0,t1,t2 +[ ]+168:[ ]+8143e37b[ ]+cv.dotup.sci.h t1,t2,20 +[ ]+16c:[ ]+8143f37b[ ]+cv.dotup.sci.b t1,t2,20 +[ ]+170:[ ]+887302fb[ ]+cv.dotusp.h t0,t1,t2 +[ ]+174:[ ]+887312fb[ ]+cv.dotusp.b t0,t1,t2 +[ ]+178:[ ]+887342fb[ ]+cv.dotusp.sc.h t0,t1,t2 +[ ]+17c:[ ]+887352fb[ ]+cv.dotusp.sc.b t0,t1,t2 +[ ]+180:[ ]+8943e37b[ ]+cv.dotusp.sci.h t1,t2,20 +[ ]+184:[ ]+8943f37b[ ]+cv.dotusp.sci.b t1,t2,20 +[ ]+188:[ ]+907302fb[ ]+cv.dotsp.h t0,t1,t2 +[ ]+18c:[ ]+907312fb[ ]+cv.dotsp.b t0,t1,t2 +[ ]+190:[ ]+907342fb[ ]+cv.dotsp.sc.h t0,t1,t2 +[ ]+194:[ ]+907352fb[ ]+cv.dotsp.sc.b t0,t1,t2 +[ ]+198:[ ]+9143e37b[ ]+cv.dotsp.sci.h t1,t2,20 +[ ]+19c:[ ]+9143f37b[ ]+cv.dotsp.sci.b t1,t2,20 +[ ]+1a0:[ ]+987302fb[ ]+cv.sdotup.h t0,t1,t2 +[ ]+1a4:[ ]+987312fb[ ]+cv.sdotup.b t0,t1,t2 +[ ]+1a8:[ ]+987342fb[ ]+cv.sdotup.sc.h t0,t1,t2 +[ ]+1ac:[ ]+987352fb[ ]+cv.sdotup.sc.b t0,t1,t2 +[ ]+1b0:[ ]+9943e37b[ ]+cv.sdotup.sci.h t1,t2,20 +[ ]+1b4:[ ]+9943f37b[ ]+cv.sdotup.sci.b t1,t2,20 +[ ]+1b8:[ ]+a07302fb[ ]+cv.sdotusp.h t0,t1,t2 +[ ]+1bc:[ ]+a07312fb[ ]+cv.sdotusp.b t0,t1,t2 +[ ]+1c0:[ ]+a07342fb[ ]+cv.sdotusp.sc.h t0,t1,t2 +[ ]+1c4:[ ]+a07352fb[ ]+cv.sdotusp.sc.b t0,t1,t2 +[ ]+1c8:[ ]+a143e37b[ ]+cv.sdotusp.sci.h t1,t2,20 +[ ]+1cc:[ ]+a143f37b[ ]+cv.sdotusp.sci.b t1,t2,20 +[ ]+1d0:[ ]+a87302fb[ ]+cv.sdotsp.h t0,t1,t2 +[ ]+1d4:[ ]+a87312fb[ ]+cv.sdotsp.b t0,t1,t2 +[ ]+1d8:[ ]+a87342fb[ ]+cv.sdotsp.sc.h t0,t1,t2 +[ ]+1dc:[ ]+a87352fb[ ]+cv.sdotsp.sc.b t0,t1,t2 +[ ]+1e0:[ ]+a943e37b[ ]+cv.sdotsp.sci.h t1,t2,20 +[ ]+1e4:[ ]+a943f37b[ ]+cv.sdotsp.sci.b t1,t2,20 +[ ]+1e8:[ ]+b943837b[ ]+cv.extract.h t1,t2,20 +[ ]+1ec:[ ]+b943937b[ ]+cv.extract.b t1,t2,20 +[ ]+1f0:[ ]+b943a37b[ ]+cv.extractu.h t1,t2,20 +[ ]+1f4:[ ]+b943b37b[ ]+cv.extractu.b t1,t2,20 +[ ]+1f8:[ ]+b943c37b[ ]+cv.insert.h t1,t2,20 +[ ]+1fc:[ ]+b943d37b[ ]+cv.insert.b t1,t2,20 +[ ]+200:[ ]+c07302fb[ ]+cv.shuffle.h t0,t1,t2 +[ ]+204:[ ]+c07312fb[ ]+cv.shuffle.b t0,t1,t2 +[ ]+208:[ ]+c143e37b[ ]+cv.shuffle.sci.h t1,t2,20 +[ ]+20c:[ ]+c143f37b[ ]+cv.shufflei0.sci.b t1,t2,20 +[ ]+210:[ ]+c943f37b[ ]+cv.shufflei1.sci.b t1,t2,20 +[ ]+214:[ ]+d143f37b[ ]+cv.shufflei2.sci.b t1,t2,20 +[ ]+218:[ ]+d943f37b[ ]+cv.shufflei3.sci.b t1,t2,20 +[ ]+21c:[ ]+e07302fb[ ]+cv.shuffle2.h t0,t1,t2 +[ ]+220:[ ]+e07312fb[ ]+cv.shuffle2.b t0,t1,t2 +[ ]+224:[ ]+f07302fb[ ]+cv.pack t0,t1,t2 +[ ]+228:[ ]+f27302fb[ ]+cv.pack.h t0,t1,t2 +[ ]+22c:[ ]+fa7312fb[ ]+cv.packhi.b t0,t1,t2 +[ ]+230:[ ]+f87312fb[ ]+cv.packlo.b t0,t1,t2 +[ ]+234:[ ]+047302fb[ ]+cv.cmpeq.h t0,t1,t2 +[ ]+238:[ ]+047312fb[ ]+cv.cmpeq.b t0,t1,t2 +[ ]+23c:[ ]+047342fb[ ]+cv.cmpeq.sc.h t0,t1,t2 +[ ]+240:[ ]+047352fb[ ]+cv.cmpeq.sc.b t0,t1,t2 +[ ]+244:[ ]+0543e37b[ ]+cv.cmpeq.sci.h t1,t2,20 +[ ]+248:[ ]+0543f37b[ ]+cv.cmpeq.sci.b t1,t2,20 +[ ]+24c:[ ]+0c7302fb[ ]+cv.cmpne.h t0,t1,t2 +[ ]+250:[ ]+0c7312fb[ ]+cv.cmpne.b t0,t1,t2 +[ ]+254:[ ]+0c7342fb[ ]+cv.cmpne.sc.h t0,t1,t2 +[ ]+258:[ ]+0c7352fb[ ]+cv.cmpne.sc.b t0,t1,t2 +[ ]+25c:[ ]+0d43e37b[ ]+cv.cmpne.sci.h t1,t2,20 +[ ]+260:[ ]+0d43f37b[ ]+cv.cmpne.sci.b t1,t2,20 +[ ]+264:[ ]+147302fb[ ]+cv.cmpgt.h t0,t1,t2 +[ ]+268:[ ]+147312fb[ ]+cv.cmpgt.b t0,t1,t2 +[ ]+26c:[ ]+147342fb[ ]+cv.cmpgt.sc.h t0,t1,t2 +[ ]+270:[ ]+147352fb[ ]+cv.cmpgt.sc.b t0,t1,t2 +[ ]+274:[ ]+1543e37b[ ]+cv.cmpgt.sci.h t1,t2,20 +[ ]+278:[ ]+1543f37b[ ]+cv.cmpgt.sci.b t1,t2,20 +[ ]+27c:[ ]+1c7302fb[ ]+cv.cmpge.h t0,t1,t2 +[ ]+280:[ ]+1c7312fb[ ]+cv.cmpge.b t0,t1,t2 +[ ]+284:[ ]+1c7342fb[ ]+cv.cmpge.sc.h t0,t1,t2 +[ ]+288:[ ]+1c7352fb[ ]+cv.cmpge.sc.b t0,t1,t2 +[ ]+28c:[ ]+1d43e37b[ ]+cv.cmpge.sci.h t1,t2,20 +[ ]+290:[ ]+1d43f37b[ ]+cv.cmpge.sci.b t1,t2,20 +[ ]+294:[ ]+247302fb[ ]+cv.cmplt.h t0,t1,t2 +[ ]+298:[ ]+247312fb[ ]+cv.cmplt.b t0,t1,t2 +[ ]+29c:[ ]+247342fb[ ]+cv.cmplt.sc.h t0,t1,t2 +[ ]+2a0:[ ]+247352fb[ ]+cv.cmplt.sc.b t0,t1,t2 +[ ]+2a4:[ ]+2543e37b[ ]+cv.cmplt.sci.h t1,t2,20 +[ ]+2a8:[ ]+2543f37b[ ]+cv.cmplt.sci.b t1,t2,20 +[ ]+2ac:[ ]+2c7302fb[ ]+cv.cmple.h t0,t1,t2 +[ ]+2b0:[ ]+2c7312fb[ ]+cv.cmple.b t0,t1,t2 +[ ]+2b4:[ ]+2c7342fb[ ]+cv.cmple.sc.h t0,t1,t2 +[ ]+2b8:[ ]+2c7352fb[ ]+cv.cmple.sc.b t0,t1,t2 +[ ]+2bc:[ ]+2d43e37b[ ]+cv.cmple.sci.h t1,t2,20 +[ ]+2c0:[ ]+2d43f37b[ ]+cv.cmple.sci.b t1,t2,20 +[ ]+2c4:[ ]+347302fb[ ]+cv.cmpgtu.h t0,t1,t2 +[ ]+2c8:[ ]+347312fb[ ]+cv.cmpgtu.b t0,t1,t2 +[ ]+2cc:[ ]+347342fb[ ]+cv.cmpgtu.sc.h t0,t1,t2 +[ ]+2d0:[ ]+347352fb[ ]+cv.cmpgtu.sc.b t0,t1,t2 +[ ]+2d4:[ ]+3543e37b[ ]+cv.cmpgtu.sci.h t1,t2,20 +[ ]+2d8:[ ]+3543f37b[ ]+cv.cmpgtu.sci.b t1,t2,20 +[ ]+2dc:[ ]+3c7302fb[ ]+cv.cmpgeu.h t0,t1,t2 +[ ]+2e0:[ ]+3c7312fb[ ]+cv.cmpgeu.b t0,t1,t2 +[ ]+2e4:[ ]+3c7342fb[ ]+cv.cmpgeu.sc.h t0,t1,t2 +[ ]+2e8:[ ]+3c7352fb[ ]+cv.cmpgeu.sc.b t0,t1,t2 +[ ]+2ec:[ ]+3d43e37b[ ]+cv.cmpgeu.sci.h t1,t2,20 +[ ]+2f0:[ ]+3d43f37b[ ]+cv.cmpgeu.sci.b t1,t2,20 +[ ]+2f4:[ ]+447302fb[ ]+cv.cmpltu.h t0,t1,t2 +[ ]+2f8:[ ]+447312fb[ ]+cv.cmpltu.b t0,t1,t2 +[ ]+2fc:[ ]+447342fb[ ]+cv.cmpltu.sc.h t0,t1,t2 +[ ]+300:[ ]+447352fb[ ]+cv.cmpltu.sc.b t0,t1,t2 +[ ]+304:[ ]+4543e37b[ ]+cv.cmpltu.sci.h t1,t2,20 +[ ]+308:[ ]+4543f37b[ ]+cv.cmpltu.sci.b t1,t2,20 +[ ]+30c:[ ]+4c7302fb[ ]+cv.cmpleu.h t0,t1,t2 +[ ]+310:[ ]+4c7312fb[ ]+cv.cmpleu.b t0,t1,t2 +[ ]+314:[ ]+4c7342fb[ ]+cv.cmpleu.sc.h t0,t1,t2 +[ ]+318:[ ]+4c7352fb[ ]+cv.cmpleu.sc.b t0,t1,t2 +[ ]+31c:[ ]+4d43e37b[ ]+cv.cmpleu.sci.h t1,t2,20 +[ ]+320:[ ]+4d43f37b[ ]+cv.cmpleu.sci.b t1,t2,20 +[ ]+324:[ ]+547302fb[ ]+cv.cplxmul.r t0,t1,t2 +[ ]+328:[ ]+567302fb[ ]+cv.cplxmul.i t0,t1,t2 +[ ]+32c:[ ]+547322fb[ ]+cv.cplxmul.r.div2 t0,t1,t2 +[ ]+330:[ ]+567322fb[ ]+cv.cplxmul.i.div2 t0,t1,t2 +[ ]+334:[ ]+547342fb[ ]+cv.cplxmul.r.div4 t0,t1,t2 +[ ]+338:[ ]+567342fb[ ]+cv.cplxmul.i.div4 t0,t1,t2 +[ ]+33c:[ ]+547362fb[ ]+cv.cplxmul.r.div8 t0,t1,t2 +[ ]+340:[ ]+567362fb[ ]+cv.cplxmul.i.div8 t0,t1,t2 +[ ]+344:[ ]+5c03837b[ ]+cv.cplxconj t1,t2 +[ ]+348:[ ]+647302fb[ ]+cv.subrotmj t0,t1,t2 +[ ]+34c:[ ]+647322fb[ ]+cv.subrotmj.div2 t0,t1,t2 +[ ]+350:[ ]+647342fb[ ]+cv.subrotmj.div4 t0,t1,t2 +[ ]+354:[ ]+647362fb[ ]+cv.subrotmj.div8 t0,t1,t2 +[ ]+358:[ ]+6c7322fb[ ]+cv.add.div2 t0,t1,t2 +[ ]+35c:[ ]+6c7342fb[ ]+cv.add.div4 t0,t1,t2 +[ ]+360:[ ]+6c7362fb[ ]+cv.add.div8 t0,t1,t2 +[ ]+364:[ ]+747322fb[ ]+cv.sub.div2 t0,t1,t2 +[ ]+368:[ ]+747342fb[ ]+cv.sub.div4 t0,t1,t2 +[ ]+36c:[ ]+747362fb[ ]+cv.sub.div8 t0,t1,t2 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s new file mode 100644 index 00000000000..a63586918cd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s @@ -0,0 +1,221 @@ +target: + cv.add.h x5, x6, x7 + cv.add.b x5, x6, x7 + cv.add.sc.h x5, x6, x7 + cv.add.sc.b x5, x6, x7 + cv.add.sci.h x6, x7, 20 + cv.add.sci.b x6, x7, 20 + cv.sub.h x5, x6, x7 + cv.sub.b x5, x6, x7 + cv.sub.sc.h x5, x6, x7 + cv.sub.sc.b x5, x6, x7 + cv.sub.sci.h x6, x7, 20 + cv.sub.sci.b x6, x7, 20 + cv.avg.h x5, x6, x7 + cv.avg.b x5, x6, x7 + cv.avg.sc.h x5, x6, x7 + cv.avg.sc.b x5, x6, x7 + cv.avg.sci.h x6, x7, 20 + cv.avg.sci.b x6, x7, 20 + cv.avgu.h x5, x6, x7 + cv.avgu.b x5, x6, x7 + cv.avgu.sc.h x5, x6, x7 + cv.avgu.sc.b x5, x6, x7 + cv.avgu.sci.h x6, x7, 20 + cv.avgu.sci.b x6, x7, 20 + cv.min.h x5, x6, x7 + cv.min.b x5, x6, x7 + cv.min.sc.h x5, x6, x7 + cv.min.sc.b x5, x6, x7 + cv.min.sci.h x6, x7, 20 + cv.min.sci.b x6, x7, 20 + cv.minu.h x5, x6, x7 + cv.minu.b x5, x6, x7 + cv.minu.sc.h x5, x6, x7 + cv.minu.sc.b x5, x6, x7 + cv.minu.sci.h x6, x7, 20 + cv.minu.sci.b x6, x7, 20 + cv.max.h x5, x6, x7 + cv.max.b x5, x6, x7 + cv.max.sc.h x5, x6, x7 + cv.max.sc.b x5, x6, x7 + cv.max.sci.h x6, x7, 20 + cv.max.sci.b x6, x7, 20 + cv.maxu.h x5, x6, x7 + cv.maxu.b x5, x6, x7 + cv.maxu.sc.h x5, x6, x7 + cv.maxu.sc.b x5, x6, x7 + cv.maxu.sci.h x6, x7, 20 + cv.maxu.sci.b x6, x7, 20 + cv.srl.h x5, x6, x7 + cv.srl.b x5, x6, x7 + cv.srl.sc.h x5, x6, x7 + cv.srl.sc.b x5, x6, x7 + cv.srl.sci.h x6, x7, 20 + cv.srl.sci.b x6, x7, 20 + cv.sra.h x5, x6, x7 + cv.sra.b x5, x6, x7 + cv.sra.sc.h x5, x6, x7 + cv.sra.sc.b x5, x6, x7 + cv.sra.sci.h x6, x7, 20 + cv.sra.sci.b x6, x7, 20 + cv.sll.h x5, x6, x7 + cv.sll.b x5, x6, x7 + cv.sll.sc.h x5, x6, x7 + cv.sll.sc.b x5, x6, x7 + cv.sll.sci.h x6, x7, 20 + cv.sll.sci.b x6, x7, 20 + cv.or.h x5, x6, x7 + cv.or.b x5, x6, x7 + cv.or.sc.h x5, x6, x7 + cv.or.sc.b x5, x6, x7 + cv.or.sci.h x6, x7, 20 + cv.or.sci.b x6, x7, 20 + cv.xor.h x5, x6, x7 + cv.xor.b x5, x6, x7 + cv.xor.sc.h x5, x6, x7 + cv.xor.sc.b x5, x6, x7 + cv.xor.sci.h x6, x7, 20 + cv.xor.sci.b x6, x7, 20 + cv.and.h x5, x6, x7 + cv.and.b x5, x6, x7 + cv.and.sc.h x5, x6, x7 + cv.and.sc.b x5, x6, x7 + cv.and.sci.h x6, x7, 20 + cv.and.sci.b x6, x7, 20 + cv.abs.h x6, x7 + cv.abs.b x6, x7 + cv.dotup.h x5, x6, x7 + cv.dotup.b x5, x6, x7 + cv.dotup.sc.h x5, x6, x7 + cv.dotup.sc.b x5, x6, x7 + cv.dotup.sci.h x6, x7, 20 + cv.dotup.sci.b x6, x7, 20 + cv.dotusp.h x5, x6, x7 + cv.dotusp.b x5, x6, x7 + cv.dotusp.sc.h x5, x6, x7 + cv.dotusp.sc.b x5, x6, x7 + cv.dotusp.sci.h x6, x7, 20 + cv.dotusp.sci.b x6, x7, 20 + cv.dotsp.h x5, x6, x7 + cv.dotsp.b x5, x6, x7 + cv.dotsp.sc.h x5, x6, x7 + cv.dotsp.sc.b x5, x6, x7 + cv.dotsp.sci.h x6, x7, 20 + cv.dotsp.sci.b x6, x7, 20 + cv.sdotup.h x5, x6, x7 + cv.sdotup.b x5, x6, x7 + cv.sdotup.sc.h x5, x6, x7 + cv.sdotup.sc.b x5, x6, x7 + cv.sdotup.sci.h x6, x7, 20 + cv.sdotup.sci.b x6, x7, 20 + cv.sdotusp.h x5, x6, x7 + cv.sdotusp.b x5, x6, x7 + cv.sdotusp.sc.h x5, x6, x7 + cv.sdotusp.sc.b x5, x6, x7 + cv.sdotusp.sci.h x6, x7, 20 + cv.sdotusp.sci.b x6, x7, 20 + cv.sdotsp.h x5, x6, x7 + cv.sdotsp.b x5, x6, x7 + cv.sdotsp.sc.h x5, x6, x7 + cv.sdotsp.sc.b x5, x6, x7 + cv.sdotsp.sci.h x6, x7, 20 + cv.sdotsp.sci.b x6, x7, 20 + cv.extract.h x6, x7, 20 + cv.extract.b x6, x7, 20 + cv.extractu.h x6, x7, 20 + cv.extractu.b x6, x7, 20 + cv.insert.h x6, x7, 20 + cv.insert.b x6, x7, 20 + cv.shuffle.h x5, x6, x7 + cv.shuffle.b x5, x6, x7 + cv.shuffle.sci.h x6, x7, 20 + cv.shufflei0.sci.b x6, x7, 20 + cv.shufflei1.sci.b x6, x7, 20 + cv.shufflei2.sci.b x6, x7, 20 + cv.shufflei3.sci.b x6, x7, 20 + cv.shuffle2.h x5, x6, x7 + cv.shuffle2.b x5, x6, x7 + cv.pack x5, x6, x7 + cv.pack.h x5, x6, x7 + cv.packhi.b x5, x6, x7 + cv.packlo.b x5, x6, x7 + cv.cmpeq.h x5, x6, x7 + cv.cmpeq.b x5, x6, x7 + cv.cmpeq.sc.h x5, x6, x7 + cv.cmpeq.sc.b x5, x6, x7 + cv.cmpeq.sci.h x6, x7, 20 + cv.cmpeq.sci.b x6, x7, 20 + cv.cmpne.h x5, x6, x7 + cv.cmpne.b x5, x6, x7 + cv.cmpne.sc.h x5, x6, x7 + cv.cmpne.sc.b x5, x6, x7 + cv.cmpne.sci.h x6, x7, 20 + cv.cmpne.sci.b x6, x7, 20 + cv.cmpgt.h x5, x6, x7 + cv.cmpgt.b x5, x6, x7 + cv.cmpgt.sc.h x5, x6, x7 + cv.cmpgt.sc.b x5, x6, x7 + cv.cmpgt.sci.h x6, x7, 20 + cv.cmpgt.sci.b x6, x7, 20 + cv.cmpge.h x5, x6, x7 + cv.cmpge.b x5, x6, x7 + cv.cmpge.sc.h x5, x6, x7 + cv.cmpge.sc.b x5, x6, x7 + cv.cmpge.sci.h x6, x7, 20 + cv.cmpge.sci.b x6, x7, 20 + cv.cmplt.h x5, x6, x7 + cv.cmplt.b x5, x6, x7 + cv.cmplt.sc.h x5, x6, x7 + cv.cmplt.sc.b x5, x6, x7 + cv.cmplt.sci.h x6, x7, 20 + cv.cmplt.sci.b x6, x7, 20 + cv.cmple.h x5, x6, x7 + cv.cmple.b x5, x6, x7 + cv.cmple.sc.h x5, x6, x7 + cv.cmple.sc.b x5, x6, x7 + cv.cmple.sci.h x6, x7, 20 + cv.cmple.sci.b x6, x7, 20 + cv.cmpgtu.h x5, x6, x7 + cv.cmpgtu.b x5, x6, x7 + cv.cmpgtu.sc.h x5, x6, x7 + cv.cmpgtu.sc.b x5, x6, x7 + cv.cmpgtu.sci.h x6, x7, 20 + cv.cmpgtu.sci.b x6, x7, 20 + cv.cmpgeu.h x5, x6, x7 + cv.cmpgeu.b x5, x6, x7 + cv.cmpgeu.sc.h x5, x6, x7 + cv.cmpgeu.sc.b x5, x6, x7 + cv.cmpgeu.sci.h x6, x7, 20 + cv.cmpgeu.sci.b x6, x7, 20 + cv.cmpltu.h x5, x6, x7 + cv.cmpltu.b x5, x6, x7 + cv.cmpltu.sc.h x5, x6, x7 + cv.cmpltu.sc.b x5, x6, x7 + cv.cmpltu.sci.h x6, x7, 20 + cv.cmpltu.sci.b x6, x7, 20 + cv.cmpleu.h x5, x6, x7 + cv.cmpleu.b x5, x6, x7 + cv.cmpleu.sc.h x5, x6, x7 + cv.cmpleu.sc.b x5, x6, x7 + cv.cmpleu.sci.h x6, x7, 20 + cv.cmpleu.sci.b x6, x7, 20 + cv.cplxmul.r x5, x6, x7 + cv.cplxmul.i x5, x6, x7 + cv.cplxmul.r.div2 x5, x6, x7 + cv.cplxmul.i.div2 x5, x6, x7 + cv.cplxmul.r.div4 x5, x6, x7 + cv.cplxmul.i.div4 x5, x6, x7 + cv.cplxmul.r.div8 x5, x6, x7 + cv.cplxmul.i.div8 x5, x6, x7 + cv.cplxconj x6, x7 + cv.subrotmj x5, x6, x7 + cv.subrotmj.div2 x5, x6, x7 + cv.subrotmj.div4 x5, x6, x7 + cv.subrotmj.div8 x5, x6, x7 + cv.add.div2 x5, x6, x7 + cv.add.div4 x5, x6, x7 + cv.add.div8 x5, x6, x7 + cv.sub.div2 x5, x6, x7 + cv.sub.div4 x5, x6, x7 + cv.sub.div8 x5, x6, x7 diff --git a/gas/testsuite/gas/riscv/cv-sll-b-fail.d b/gas/testsuite/gas/riscv/cv-sll-b-fail.d new file mode 100644 index 00000000000..4d84e74ad62 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-b-fail.s +#error_output: cv-sll-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-b-fail.l b/gas/testsuite/gas/riscv/cv-sll-b-fail.l new file mode 100644 index 00000000000..4bf8b2b1f97 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.b x32,x32,x32' +.*: Error: illegal operands `cv.sll.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-b-fail.s b/gas/testsuite/gas/riscv/cv-sll-b-fail.s new file mode 100644 index 00000000000..c64950c5ef6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.b x32, x32, x32 + cv.sll.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-b-pass.d b/gas/testsuite/gas/riscv/cv-sll-b-pass.d new file mode 100644 index 00000000000..791b7824f91 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000107b cv.sll.b zero,zero,zero + 4: 501090fb cv.sll.b ra,ra,ra + 8: 5021117b cv.sll.b sp,sp,sp + c: 5084147b cv.sll.b s0,s0,s0 + 10: 514a1a7b cv.sll.b s4,s4,s4 + 14: 51ff9ffb cv.sll.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-b-pass.s b/gas/testsuite/gas/riscv/cv-sll-b-pass.s new file mode 100644 index 00000000000..929d3c607dc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.b x0, x0, x0 + cv.sll.b x1, x1, x1 + cv.sll.b x2, x2, x2 + cv.sll.b x8, x8, x8 + cv.sll.b x20, x20, x20 + cv.sll.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-h-fail.d b/gas/testsuite/gas/riscv/cv-sll-h-fail.d new file mode 100644 index 00000000000..873a39e8c9e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-h-fail.s +#error_output: cv-sll-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-h-fail.l b/gas/testsuite/gas/riscv/cv-sll-h-fail.l new file mode 100644 index 00000000000..3ea79744e4f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.h x32,x32,x32' +.*: Error: illegal operands `cv.sll.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-h-fail.s b/gas/testsuite/gas/riscv/cv-sll-h-fail.s new file mode 100644 index 00000000000..a47ce4c06dd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.h x32, x32, x32 + cv.sll.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-h-pass.d b/gas/testsuite/gas/riscv/cv-sll-h-pass.d new file mode 100644 index 00000000000..c863dca01b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000007b cv.sll.h zero,zero,zero + 4: 501080fb cv.sll.h ra,ra,ra + 8: 5021017b cv.sll.h sp,sp,sp + c: 5084047b cv.sll.h s0,s0,s0 + 10: 514a0a7b cv.sll.h s4,s4,s4 + 14: 51ff8ffb cv.sll.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-h-pass.s b/gas/testsuite/gas/riscv/cv-sll-h-pass.s new file mode 100644 index 00000000000..4fa2c8c2b07 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.h x0, x0, x0 + cv.sll.h x1, x1, x1 + cv.sll.h x2, x2, x2 + cv.sll.h x8, x8, x8 + cv.sll.h x20, x20, x20 + cv.sll.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.d new file mode 100644 index 00000000000..b11ce4113c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-b-fail.s +#error_output: cv-sll-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.l new file mode 100644 index 00000000000..ce3d6df659a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sll.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.s new file mode 100644 index 00000000000..faeb0c7cd66 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.sc.b x32, x32, x32 + cv.sll.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.d new file mode 100644 index 00000000000..3b42197ea03 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000507b cv.sll.sc.b zero,zero,zero + 4: 5010d0fb cv.sll.sc.b ra,ra,ra + 8: 5021517b cv.sll.sc.b sp,sp,sp + c: 5084547b cv.sll.sc.b s0,s0,s0 + 10: 514a5a7b cv.sll.sc.b s4,s4,s4 + 14: 51ffdffb cv.sll.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.s new file mode 100644 index 00000000000..e8453d8dfd0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.sc.b x0, x0, x0 + cv.sll.sc.b x1, x1, x1 + cv.sll.sc.b x2, x2, x2 + cv.sll.sc.b x8, x8, x8 + cv.sll.sc.b x20, x20, x20 + cv.sll.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.d new file mode 100644 index 00000000000..666a0959175 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-h-fail.s +#error_output: cv-sll-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.l new file mode 100644 index 00000000000..320fa74ec56 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sll.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.s new file mode 100644 index 00000000000..0fa9838b6b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.sc.h x32, x32, x32 + cv.sll.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.d new file mode 100644 index 00000000000..83483a97efe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000407b cv.sll.sc.h zero,zero,zero + 4: 5010c0fb cv.sll.sc.h ra,ra,ra + 8: 5021417b cv.sll.sc.h sp,sp,sp + c: 5084447b cv.sll.sc.h s0,s0,s0 + 10: 514a4a7b cv.sll.sc.h s4,s4,s4 + 14: 51ffcffb cv.sll.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.s new file mode 100644 index 00000000000..d496d672b49 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.sc.h x0, x0, x0 + cv.sll.sc.h x1, x1, x1 + cv.sll.sc.h x2, x2, x2 + cv.sll.sc.h x8, x8, x8 + cv.sll.sc.h x20, x20, x20 + cv.sll.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.d new file mode 100644 index 00000000000..13614f1be02 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-b-fail.s +#error_output: cv-sll-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.l new file mode 100644 index 00000000000..2c65793b0e7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sll.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.s new file mode 100644 index 00000000000..ac98cd356cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sll.sci.b x32, x32, 20 + cv.sll.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sll.sci.b x6, x7, -33 + cv.sll.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.d new file mode 100644 index 00000000000..eeae01cc31e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5140707b cv.sll.sci.b zero,zero,20 + 4: 5140f0fb cv.sll.sci.b ra,ra,20 + 8: 5141717b cv.sll.sci.b sp,sp,20 + c: 5144747b cv.sll.sci.b s0,s0,20 + 10: 514a7a7b cv.sll.sci.b s4,s4,20 + 14: 514ffffb cv.sll.sci.b t6,t6,20 + 18: 5203f37b cv.sll.sci.b t1,t2,-32 + 1c: 5003f37b cv.sll.sci.b t1,t2,0 + 20: 51f3f37b cv.sll.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.s new file mode 100644 index 00000000000..03388ef46a3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sll.sci.b x0, x0, 20 + cv.sll.sci.b x1, x1, 20 + cv.sll.sci.b x2, x2, 20 + cv.sll.sci.b x8, x8, 20 + cv.sll.sci.b x20, x20, 20 + cv.sll.sci.b x31, x31, 20 + #Immediate Values Test + cv.sll.sci.b x6, x7, -32 + cv.sll.sci.b x6, x7, 0 + cv.sll.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.d new file mode 100644 index 00000000000..72b76a3b5c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-h-fail.s +#error_output: cv-sll-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.l new file mode 100644 index 00000000000..091eeb02625 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sll.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.s new file mode 100644 index 00000000000..d95ab013e24 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sll.sci.h x32, x32, 20 + cv.sll.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sll.sci.h x6, x7, -33 + cv.sll.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.d new file mode 100644 index 00000000000..8662bf5fb17 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5140607b cv.sll.sci.h zero,zero,20 + 4: 5140e0fb cv.sll.sci.h ra,ra,20 + 8: 5141617b cv.sll.sci.h sp,sp,20 + c: 5144647b cv.sll.sci.h s0,s0,20 + 10: 514a6a7b cv.sll.sci.h s4,s4,20 + 14: 514feffb cv.sll.sci.h t6,t6,20 + 18: 5203e37b cv.sll.sci.h t1,t2,-32 + 1c: 5003e37b cv.sll.sci.h t1,t2,0 + 20: 51f3e37b cv.sll.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.s new file mode 100644 index 00000000000..e11bdd43354 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sll.sci.h x0, x0, 20 + cv.sll.sci.h x1, x1, 20 + cv.sll.sci.h x2, x2, 20 + cv.sll.sci.h x8, x8, 20 + cv.sll.sci.h x20, x20, 20 + cv.sll.sci.h x31, x31, 20 + #Immediate Values Test + cv.sll.sci.h x6, x7, -32 + cv.sll.sci.h x6, x7, 0 + cv.sll.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sra-b-fail.d b/gas/testsuite/gas/riscv/cv-sra-b-fail.d new file mode 100644 index 00000000000..44f1df2383e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-b-fail.s +#error_output: cv-sra-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-b-fail.l b/gas/testsuite/gas/riscv/cv-sra-b-fail.l new file mode 100644 index 00000000000..e6d5a094539 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.b x32,x32,x32' +.*: Error: illegal operands `cv.sra.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-b-fail.s b/gas/testsuite/gas/riscv/cv-sra-b-fail.s new file mode 100644 index 00000000000..c09838a04ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.b x32, x32, x32 + cv.sra.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-b-pass.d b/gas/testsuite/gas/riscv/cv-sra-b-pass.d new file mode 100644 index 00000000000..63fd5d141d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800107b cv.sra.b zero,zero,zero + 4: 481090fb cv.sra.b ra,ra,ra + 8: 4821117b cv.sra.b sp,sp,sp + c: 4884147b cv.sra.b s0,s0,s0 + 10: 494a1a7b cv.sra.b s4,s4,s4 + 14: 49ff9ffb cv.sra.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-b-pass.s b/gas/testsuite/gas/riscv/cv-sra-b-pass.s new file mode 100644 index 00000000000..0cef7810d49 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.b x0, x0, x0 + cv.sra.b x1, x1, x1 + cv.sra.b x2, x2, x2 + cv.sra.b x8, x8, x8 + cv.sra.b x20, x20, x20 + cv.sra.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-h-fail.d b/gas/testsuite/gas/riscv/cv-sra-h-fail.d new file mode 100644 index 00000000000..ce12e48a5ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-h-fail.s +#error_output: cv-sra-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-h-fail.l b/gas/testsuite/gas/riscv/cv-sra-h-fail.l new file mode 100644 index 00000000000..ddf7b46acb0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.h x32,x32,x32' +.*: Error: illegal operands `cv.sra.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-h-fail.s b/gas/testsuite/gas/riscv/cv-sra-h-fail.s new file mode 100644 index 00000000000..dcbe979c3f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.h x32, x32, x32 + cv.sra.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-h-pass.d b/gas/testsuite/gas/riscv/cv-sra-h-pass.d new file mode 100644 index 00000000000..f1b8530325a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800007b cv.sra.h zero,zero,zero + 4: 481080fb cv.sra.h ra,ra,ra + 8: 4821017b cv.sra.h sp,sp,sp + c: 4884047b cv.sra.h s0,s0,s0 + 10: 494a0a7b cv.sra.h s4,s4,s4 + 14: 49ff8ffb cv.sra.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-h-pass.s b/gas/testsuite/gas/riscv/cv-sra-h-pass.s new file mode 100644 index 00000000000..5dad74333e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.h x0, x0, x0 + cv.sra.h x1, x1, x1 + cv.sra.h x2, x2, x2 + cv.sra.h x8, x8, x8 + cv.sra.h x20, x20, x20 + cv.sra.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d new file mode 100644 index 00000000000..c64ee7d296e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-b-fail.s +#error_output: cv-sra-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l new file mode 100644 index 00000000000..72df02d3a2d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sra.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s new file mode 100644 index 00000000000..5ebdbfb1418 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.sc.b x32, x32, x32 + cv.sra.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d new file mode 100644 index 00000000000..ee518b268ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800507b cv.sra.sc.b zero,zero,zero + 4: 4810d0fb cv.sra.sc.b ra,ra,ra + 8: 4821517b cv.sra.sc.b sp,sp,sp + c: 4884547b cv.sra.sc.b s0,s0,s0 + 10: 494a5a7b cv.sra.sc.b s4,s4,s4 + 14: 49ffdffb cv.sra.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s new file mode 100644 index 00000000000..3ae2c92ec39 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.sc.b x0, x0, x0 + cv.sra.sc.b x1, x1, x1 + cv.sra.sc.b x2, x2, x2 + cv.sra.sc.b x8, x8, x8 + cv.sra.sc.b x20, x20, x20 + cv.sra.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d new file mode 100644 index 00000000000..662d184d8f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-h-fail.s +#error_output: cv-sra-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l new file mode 100644 index 00000000000..68eef579272 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sra.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s new file mode 100644 index 00000000000..3f4dc2b58da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.sc.h x32, x32, x32 + cv.sra.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d new file mode 100644 index 00000000000..31c88094530 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800407b cv.sra.sc.h zero,zero,zero + 4: 4810c0fb cv.sra.sc.h ra,ra,ra + 8: 4821417b cv.sra.sc.h sp,sp,sp + c: 4884447b cv.sra.sc.h s0,s0,s0 + 10: 494a4a7b cv.sra.sc.h s4,s4,s4 + 14: 49ffcffb cv.sra.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s new file mode 100644 index 00000000000..06f73833df3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.sc.h x0, x0, x0 + cv.sra.sc.h x1, x1, x1 + cv.sra.sc.h x2, x2, x2 + cv.sra.sc.h x8, x8, x8 + cv.sra.sc.h x20, x20, x20 + cv.sra.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d new file mode 100644 index 00000000000..3cb8f9cf06d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-b-fail.s +#error_output: cv-sra-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l new file mode 100644 index 00000000000..ed25c4b5da7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sra.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s new file mode 100644 index 00000000000..4809c41c824 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sra.sci.b x32, x32, 20 + cv.sra.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sra.sci.b x6, x7, -33 + cv.sra.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d new file mode 100644 index 00000000000..67f565d96e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4940707b cv.sra.sci.b zero,zero,20 + 4: 4940f0fb cv.sra.sci.b ra,ra,20 + 8: 4941717b cv.sra.sci.b sp,sp,20 + c: 4944747b cv.sra.sci.b s0,s0,20 + 10: 494a7a7b cv.sra.sci.b s4,s4,20 + 14: 494ffffb cv.sra.sci.b t6,t6,20 + 18: 4a03f37b cv.sra.sci.b t1,t2,-32 + 1c: 4803f37b cv.sra.sci.b t1,t2,0 + 20: 49f3f37b cv.sra.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s new file mode 100644 index 00000000000..82bbdba79a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sra.sci.b x0, x0, 20 + cv.sra.sci.b x1, x1, 20 + cv.sra.sci.b x2, x2, 20 + cv.sra.sci.b x8, x8, 20 + cv.sra.sci.b x20, x20, 20 + cv.sra.sci.b x31, x31, 20 + #Immediate Values Test + cv.sra.sci.b x6, x7, -32 + cv.sra.sci.b x6, x7, 0 + cv.sra.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d new file mode 100644 index 00000000000..8a5945017bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-h-fail.s +#error_output: cv-sra-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.l new file mode 100644 index 00000000000..53fb9c011c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sra.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.s new file mode 100644 index 00000000000..50896d2531a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sra.sci.h x32, x32, 20 + cv.sra.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sra.sci.h x6, x7, -33 + cv.sra.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.d new file mode 100644 index 00000000000..41a317dfee7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4940607b cv.sra.sci.h zero,zero,20 + 4: 4940e0fb cv.sra.sci.h ra,ra,20 + 8: 4941617b cv.sra.sci.h sp,sp,20 + c: 4944647b cv.sra.sci.h s0,s0,20 + 10: 494a6a7b cv.sra.sci.h s4,s4,20 + 14: 494feffb cv.sra.sci.h t6,t6,20 + 18: 4a03e37b cv.sra.sci.h t1,t2,-32 + 1c: 4803e37b cv.sra.sci.h t1,t2,0 + 20: 49f3e37b cv.sra.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.s new file mode 100644 index 00000000000..28977cc7987 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sra.sci.h x0, x0, 20 + cv.sra.sci.h x1, x1, 20 + cv.sra.sci.h x2, x2, 20 + cv.sra.sci.h x8, x8, 20 + cv.sra.sci.h x20, x20, 20 + cv.sra.sci.h x31, x31, 20 + #Immediate Values Test + cv.sra.sci.h x6, x7, -32 + cv.sra.sci.h x6, x7, 0 + cv.sra.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-srl-b-fail.d b/gas/testsuite/gas/riscv/cv-srl-b-fail.d new file mode 100644 index 00000000000..a667b8030c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-b-fail.s +#error_output: cv-srl-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-b-fail.l b/gas/testsuite/gas/riscv/cv-srl-b-fail.l new file mode 100644 index 00000000000..2e8ea987dac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.b x32,x32,x32' +.*: Error: illegal operands `cv.srl.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-b-fail.s b/gas/testsuite/gas/riscv/cv-srl-b-fail.s new file mode 100644 index 00000000000..da928163404 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.b x32, x32, x32 + cv.srl.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-b-pass.d b/gas/testsuite/gas/riscv/cv-srl-b-pass.d new file mode 100644 index 00000000000..fa1b2634e7a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000107b cv.srl.b zero,zero,zero + 4: 401090fb cv.srl.b ra,ra,ra + 8: 4021117b cv.srl.b sp,sp,sp + c: 4084147b cv.srl.b s0,s0,s0 + 10: 414a1a7b cv.srl.b s4,s4,s4 + 14: 41ff9ffb cv.srl.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-b-pass.s b/gas/testsuite/gas/riscv/cv-srl-b-pass.s new file mode 100644 index 00000000000..63127105513 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.b x0, x0, x0 + cv.srl.b x1, x1, x1 + cv.srl.b x2, x2, x2 + cv.srl.b x8, x8, x8 + cv.srl.b x20, x20, x20 + cv.srl.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-h-fail.d b/gas/testsuite/gas/riscv/cv-srl-h-fail.d new file mode 100644 index 00000000000..2d06e42c589 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-h-fail.s +#error_output: cv-srl-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-h-fail.l b/gas/testsuite/gas/riscv/cv-srl-h-fail.l new file mode 100644 index 00000000000..427b72b5219 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.h x32,x32,x32' +.*: Error: illegal operands `cv.srl.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-h-fail.s b/gas/testsuite/gas/riscv/cv-srl-h-fail.s new file mode 100644 index 00000000000..56519e489e1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.h x32, x32, x32 + cv.srl.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-h-pass.d b/gas/testsuite/gas/riscv/cv-srl-h-pass.d new file mode 100644 index 00000000000..c4a52f41cc5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000007b cv.srl.h zero,zero,zero + 4: 401080fb cv.srl.h ra,ra,ra + 8: 4021017b cv.srl.h sp,sp,sp + c: 4084047b cv.srl.h s0,s0,s0 + 10: 414a0a7b cv.srl.h s4,s4,s4 + 14: 41ff8ffb cv.srl.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-h-pass.s b/gas/testsuite/gas/riscv/cv-srl-h-pass.s new file mode 100644 index 00000000000..c63c5af091d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.h x0, x0, x0 + cv.srl.h x1, x1, x1 + cv.srl.h x2, x2, x2 + cv.srl.h x8, x8, x8 + cv.srl.h x20, x20, x20 + cv.srl.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.d new file mode 100644 index 00000000000..d9db74f70f4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-b-fail.s +#error_output: cv-srl-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.l new file mode 100644 index 00000000000..48f43ede7bc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.srl.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.s new file mode 100644 index 00000000000..a70ef1704a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.sc.b x32, x32, x32 + cv.srl.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.d new file mode 100644 index 00000000000..900d6563907 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000507b cv.srl.sc.b zero,zero,zero + 4: 4010d0fb cv.srl.sc.b ra,ra,ra + 8: 4021517b cv.srl.sc.b sp,sp,sp + c: 4084547b cv.srl.sc.b s0,s0,s0 + 10: 414a5a7b cv.srl.sc.b s4,s4,s4 + 14: 41ffdffb cv.srl.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.s new file mode 100644 index 00000000000..b104a06f284 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.sc.b x0, x0, x0 + cv.srl.sc.b x1, x1, x1 + cv.srl.sc.b x2, x2, x2 + cv.srl.sc.b x8, x8, x8 + cv.srl.sc.b x20, x20, x20 + cv.srl.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.d new file mode 100644 index 00000000000..b32a509a9b4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-h-fail.s +#error_output: cv-srl-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.l new file mode 100644 index 00000000000..721754b3854 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.srl.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.s new file mode 100644 index 00000000000..95ef1a18e2d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.sc.h x32, x32, x32 + cv.srl.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.d new file mode 100644 index 00000000000..0f7cd11ad6b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000407b cv.srl.sc.h zero,zero,zero + 4: 4010c0fb cv.srl.sc.h ra,ra,ra + 8: 4021417b cv.srl.sc.h sp,sp,sp + c: 4084447b cv.srl.sc.h s0,s0,s0 + 10: 414a4a7b cv.srl.sc.h s4,s4,s4 + 14: 41ffcffb cv.srl.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.s new file mode 100644 index 00000000000..e961105803b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.sc.h x0, x0, x0 + cv.srl.sc.h x1, x1, x1 + cv.srl.sc.h x2, x2, x2 + cv.srl.sc.h x8, x8, x8 + cv.srl.sc.h x20, x20, x20 + cv.srl.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.d new file mode 100644 index 00000000000..d362aa54f31 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-b-fail.s +#error_output: cv-srl-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.l new file mode 100644 index 00000000000..b2af4b773c4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sci.b x32,x32,20' +.*: Error: illegal operands `cv.srl.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.s new file mode 100644 index 00000000000..24618209ed8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.srl.sci.b x32, x32, 20 + cv.srl.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.srl.sci.b x6, x7, -33 + cv.srl.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.d new file mode 100644 index 00000000000..bd70fb90d26 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4140707b cv.srl.sci.b zero,zero,20 + 4: 4140f0fb cv.srl.sci.b ra,ra,20 + 8: 4141717b cv.srl.sci.b sp,sp,20 + c: 4144747b cv.srl.sci.b s0,s0,20 + 10: 414a7a7b cv.srl.sci.b s4,s4,20 + 14: 414ffffb cv.srl.sci.b t6,t6,20 + 18: 4203f37b cv.srl.sci.b t1,t2,-32 + 1c: 4003f37b cv.srl.sci.b t1,t2,0 + 20: 41f3f37b cv.srl.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.s new file mode 100644 index 00000000000..b5e7af2bcf6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.srl.sci.b x0, x0, 20 + cv.srl.sci.b x1, x1, 20 + cv.srl.sci.b x2, x2, 20 + cv.srl.sci.b x8, x8, 20 + cv.srl.sci.b x20, x20, 20 + cv.srl.sci.b x31, x31, 20 + #Immediate Values Test + cv.srl.sci.b x6, x7, -32 + cv.srl.sci.b x6, x7, 0 + cv.srl.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.d new file mode 100644 index 00000000000..f185f6b0cc4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-h-fail.s +#error_output: cv-srl-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.l new file mode 100644 index 00000000000..d7bc65aa577 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sci.h x32,x32,20' +.*: Error: illegal operands `cv.srl.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.s new file mode 100644 index 00000000000..d0b61b5904f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.srl.sci.h x32, x32, 20 + cv.srl.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.srl.sci.h x6, x7, -33 + cv.srl.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.d new file mode 100644 index 00000000000..0a1541319a5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4140607b cv.srl.sci.h zero,zero,20 + 4: 4140e0fb cv.srl.sci.h ra,ra,20 + 8: 4141617b cv.srl.sci.h sp,sp,20 + c: 4144647b cv.srl.sci.h s0,s0,20 + 10: 414a6a7b cv.srl.sci.h s4,s4,20 + 14: 414feffb cv.srl.sci.h t6,t6,20 + 18: 4203e37b cv.srl.sci.h t1,t2,-32 + 1c: 4003e37b cv.srl.sci.h t1,t2,0 + 20: 41f3e37b cv.srl.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.s new file mode 100644 index 00000000000..862629a13b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.srl.sci.h x0, x0, 20 + cv.srl.sci.h x1, x1, 20 + cv.srl.sci.h x2, x2, 20 + cv.srl.sci.h x8, x8, 20 + cv.srl.sci.h x20, x20, 20 + cv.srl.sci.h x31, x31, 20 + #Immediate Values Test + cv.srl.sci.h x6, x7, -32 + cv.srl.sci.h x6, x7, 0 + cv.srl.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sub-b-fail.d b/gas/testsuite/gas/riscv/cv-sub-b-fail.d new file mode 100644 index 00000000000..9ede9c593cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-b-fail.s +#error_output: cv-sub-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-b-fail.l b/gas/testsuite/gas/riscv/cv-sub-b-fail.l new file mode 100644 index 00000000000..02dc7c9c35c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.b x32,x32,x32' +.*: Error: illegal operands `cv.sub.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-b-fail.s b/gas/testsuite/gas/riscv/cv-sub-b-fail.s new file mode 100644 index 00000000000..ca21cbf80a4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.b x32, x32, x32 + cv.sub.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-b-pass.d b/gas/testsuite/gas/riscv/cv-sub-b-pass.d new file mode 100644 index 00000000000..b96bab91c0f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800107b cv.sub.b zero,zero,zero + 4: 081090fb cv.sub.b ra,ra,ra + 8: 0821117b cv.sub.b sp,sp,sp + c: 0884147b cv.sub.b s0,s0,s0 + 10: 094a1a7b cv.sub.b s4,s4,s4 + 14: 09ff9ffb cv.sub.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-b-pass.s b/gas/testsuite/gas/riscv/cv-sub-b-pass.s new file mode 100644 index 00000000000..99f9c1ef13b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.b x0, x0, x0 + cv.sub.b x1, x1, x1 + cv.sub.b x2, x2, x2 + cv.sub.b x8, x8, x8 + cv.sub.b x20, x20, x20 + cv.sub.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-fail.d b/gas/testsuite/gas/riscv/cv-sub-div2-fail.d new file mode 100644 index 00000000000..0102fcfe70b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div2-fail.s +#error_output: cv-sub-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-fail.l b/gas/testsuite/gas/riscv/cv-sub-div2-fail.l new file mode 100644 index 00000000000..7776bd5850f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.div2 x32,x32,x32' +.*: Error: illegal operands `cv.sub.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-fail.s b/gas/testsuite/gas/riscv/cv-sub-div2-fail.s new file mode 100644 index 00000000000..e1c33a6fd21 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.div2 x32, x32, x32 + cv.sub.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-pass.d b/gas/testsuite/gas/riscv/cv-sub-div2-pass.d new file mode 100644 index 00000000000..63d2a344a4e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7400207b cv.sub.div2 zero,zero,zero + 4: 7410a0fb cv.sub.div2 ra,ra,ra + 8: 7421217b cv.sub.div2 sp,sp,sp + c: 7484247b cv.sub.div2 s0,s0,s0 + 10: 754a2a7b cv.sub.div2 s4,s4,s4 + 14: 75ffaffb cv.sub.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-pass.s b/gas/testsuite/gas/riscv/cv-sub-div2-pass.s new file mode 100644 index 00000000000..7ca4507d27d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.div2 x0, x0, x0 + cv.sub.div2 x1, x1, x1 + cv.sub.div2 x2, x2, x2 + cv.sub.div2 x8, x8, x8 + cv.sub.div2 x20, x20, x20 + cv.sub.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-fail.d b/gas/testsuite/gas/riscv/cv-sub-div4-fail.d new file mode 100644 index 00000000000..ed6f5cf7429 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div4-fail.s +#error_output: cv-sub-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-fail.l b/gas/testsuite/gas/riscv/cv-sub-div4-fail.l new file mode 100644 index 00000000000..886d6783979 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.div4 x32,x32,x32' +.*: Error: illegal operands `cv.sub.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-fail.s b/gas/testsuite/gas/riscv/cv-sub-div4-fail.s new file mode 100644 index 00000000000..8e7a639f9a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.div4 x32, x32, x32 + cv.sub.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-pass.d b/gas/testsuite/gas/riscv/cv-sub-div4-pass.d new file mode 100644 index 00000000000..2f8558bb90a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7400407b cv.sub.div4 zero,zero,zero + 4: 7410c0fb cv.sub.div4 ra,ra,ra + 8: 7421417b cv.sub.div4 sp,sp,sp + c: 7484447b cv.sub.div4 s0,s0,s0 + 10: 754a4a7b cv.sub.div4 s4,s4,s4 + 14: 75ffcffb cv.sub.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-pass.s b/gas/testsuite/gas/riscv/cv-sub-div4-pass.s new file mode 100644 index 00000000000..8e6ad0c8a64 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.div4 x0, x0, x0 + cv.sub.div4 x1, x1, x1 + cv.sub.div4 x2, x2, x2 + cv.sub.div4 x8, x8, x8 + cv.sub.div4 x20, x20, x20 + cv.sub.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-fail.d b/gas/testsuite/gas/riscv/cv-sub-div8-fail.d new file mode 100644 index 00000000000..71496a671fb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div8-fail.s +#error_output: cv-sub-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-fail.l b/gas/testsuite/gas/riscv/cv-sub-div8-fail.l new file mode 100644 index 00000000000..c6141b1dc69 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.div8 x32,x32,x32' +.*: Error: illegal operands `cv.sub.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-fail.s b/gas/testsuite/gas/riscv/cv-sub-div8-fail.s new file mode 100644 index 00000000000..f642daefd3a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.div8 x32, x32, x32 + cv.sub.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-pass.d b/gas/testsuite/gas/riscv/cv-sub-div8-pass.d new file mode 100644 index 00000000000..bc8e0351764 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7400607b cv.sub.div8 zero,zero,zero + 4: 7410e0fb cv.sub.div8 ra,ra,ra + 8: 7421617b cv.sub.div8 sp,sp,sp + c: 7484647b cv.sub.div8 s0,s0,s0 + 10: 754a6a7b cv.sub.div8 s4,s4,s4 + 14: 75ffeffb cv.sub.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-pass.s b/gas/testsuite/gas/riscv/cv-sub-div8-pass.s new file mode 100644 index 00000000000..1d38695d203 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.div8 x0, x0, x0 + cv.sub.div8 x1, x1, x1 + cv.sub.div8 x2, x2, x2 + cv.sub.div8 x8, x8, x8 + cv.sub.div8 x20, x20, x20 + cv.sub.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-h-fail.d b/gas/testsuite/gas/riscv/cv-sub-h-fail.d new file mode 100644 index 00000000000..477c7f70f4b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-h-fail.s +#error_output: cv-sub-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-h-fail.l b/gas/testsuite/gas/riscv/cv-sub-h-fail.l new file mode 100644 index 00000000000..36728c3b84b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.h x32,x32,x32' +.*: Error: illegal operands `cv.sub.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-h-fail.s b/gas/testsuite/gas/riscv/cv-sub-h-fail.s new file mode 100644 index 00000000000..63a218290f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.h x32, x32, x32 + cv.sub.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-h-pass.d b/gas/testsuite/gas/riscv/cv-sub-h-pass.d new file mode 100644 index 00000000000..923c8c0d87e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800007b cv.sub.h zero,zero,zero + 4: 081080fb cv.sub.h ra,ra,ra + 8: 0821017b cv.sub.h sp,sp,sp + c: 0884047b cv.sub.h s0,s0,s0 + 10: 094a0a7b cv.sub.h s4,s4,s4 + 14: 09ff8ffb cv.sub.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-h-pass.s b/gas/testsuite/gas/riscv/cv-sub-h-pass.s new file mode 100644 index 00000000000..61fc9f949a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.h x0, x0, x0 + cv.sub.h x1, x1, x1 + cv.sub.h x2, x2, x2 + cv.sub.h x8, x8, x8 + cv.sub.h x20, x20, x20 + cv.sub.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.d new file mode 100644 index 00000000000..0e7f88a9dd3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-b-fail.s +#error_output: cv-sub-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.l new file mode 100644 index 00000000000..785f3c7c3be --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sub.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.s new file mode 100644 index 00000000000..83942ae2290 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.sc.b x32, x32, x32 + cv.sub.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.d new file mode 100644 index 00000000000..45d0391cc6c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800507b cv.sub.sc.b zero,zero,zero + 4: 0810d0fb cv.sub.sc.b ra,ra,ra + 8: 0821517b cv.sub.sc.b sp,sp,sp + c: 0884547b cv.sub.sc.b s0,s0,s0 + 10: 094a5a7b cv.sub.sc.b s4,s4,s4 + 14: 09ffdffb cv.sub.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.s new file mode 100644 index 00000000000..2d0170cdfef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.sc.b x0, x0, x0 + cv.sub.sc.b x1, x1, x1 + cv.sub.sc.b x2, x2, x2 + cv.sub.sc.b x8, x8, x8 + cv.sub.sc.b x20, x20, x20 + cv.sub.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.d new file mode 100644 index 00000000000..102c3ceec1d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-h-fail.s +#error_output: cv-sub-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.l new file mode 100644 index 00000000000..5d5c6b67ac2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sub.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.s new file mode 100644 index 00000000000..cc48b52fa2c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.sc.h x32, x32, x32 + cv.sub.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.d new file mode 100644 index 00000000000..e4f98086107 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800407b cv.sub.sc.h zero,zero,zero + 4: 0810c0fb cv.sub.sc.h ra,ra,ra + 8: 0821417b cv.sub.sc.h sp,sp,sp + c: 0884447b cv.sub.sc.h s0,s0,s0 + 10: 094a4a7b cv.sub.sc.h s4,s4,s4 + 14: 09ffcffb cv.sub.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.s new file mode 100644 index 00000000000..5608febce85 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.sc.h x0, x0, x0 + cv.sub.sc.h x1, x1, x1 + cv.sub.sc.h x2, x2, x2 + cv.sub.sc.h x8, x8, x8 + cv.sub.sc.h x20, x20, x20 + cv.sub.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.d new file mode 100644 index 00000000000..74cb4e1f284 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-b-fail.s +#error_output: cv-sub-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.l new file mode 100644 index 00000000000..d45c4089d7c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sub.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.s new file mode 100644 index 00000000000..efacb4d76ff --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sub.sci.b x32, x32, 20 + cv.sub.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sub.sci.b x6, x7, -33 + cv.sub.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.d new file mode 100644 index 00000000000..d28d68678c4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0940707b cv.sub.sci.b zero,zero,20 + 4: 0940f0fb cv.sub.sci.b ra,ra,20 + 8: 0941717b cv.sub.sci.b sp,sp,20 + c: 0944747b cv.sub.sci.b s0,s0,20 + 10: 094a7a7b cv.sub.sci.b s4,s4,20 + 14: 094ffffb cv.sub.sci.b t6,t6,20 + 18: 0a03f37b cv.sub.sci.b t1,t2,-32 + 1c: 0803f37b cv.sub.sci.b t1,t2,0 + 20: 09f3f37b cv.sub.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.s new file mode 100644 index 00000000000..ef41450b53f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sub.sci.b x0, x0, 20 + cv.sub.sci.b x1, x1, 20 + cv.sub.sci.b x2, x2, 20 + cv.sub.sci.b x8, x8, 20 + cv.sub.sci.b x20, x20, 20 + cv.sub.sci.b x31, x31, 20 + #Immediate Values Test + cv.sub.sci.b x6, x7, -32 + cv.sub.sci.b x6, x7, 0 + cv.sub.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.d new file mode 100644 index 00000000000..51aed159ba7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-h-fail.s +#error_output: cv-sub-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.l new file mode 100644 index 00000000000..ff9425a4435 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sub.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.s new file mode 100644 index 00000000000..bdd60606d7a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sub.sci.h x32, x32, 20 + cv.sub.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sub.sci.h x6, x7, -33 + cv.sub.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.d new file mode 100644 index 00000000000..832507864b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0940607b cv.sub.sci.h zero,zero,20 + 4: 0940e0fb cv.sub.sci.h ra,ra,20 + 8: 0941617b cv.sub.sci.h sp,sp,20 + c: 0944647b cv.sub.sci.h s0,s0,20 + 10: 094a6a7b cv.sub.sci.h s4,s4,20 + 14: 094feffb cv.sub.sci.h t6,t6,20 + 18: 0a03e37b cv.sub.sci.h t1,t2,-32 + 1c: 0803e37b cv.sub.sci.h t1,t2,0 + 20: 09f3e37b cv.sub.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.s new file mode 100644 index 00000000000..7b74356abc7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sub.sci.h x0, x0, 20 + cv.sub.sci.h x1, x1, 20 + cv.sub.sci.h x2, x2, 20 + cv.sub.sci.h x8, x8, 20 + cv.sub.sci.h x20, x20, 20 + cv.sub.sci.h x31, x31, 20 + #Immediate Values Test + cv.sub.sci.h x6, x7, -32 + cv.sub.sci.h x6, x7, 0 + cv.sub.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.d new file mode 100644 index 00000000000..93d6f25710f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div2-fail.s +#error_output: cv-subrotmj-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.l new file mode 100644 index 00000000000..324fe88cfc7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj.div2 x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.s new file mode 100644 index 00000000000..b8a95a56588 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj.div2 x32, x32, x32 + cv.subrotmj.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.d new file mode 100644 index 00000000000..f7e2851fa6b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400207b cv.subrotmj.div2 zero,zero,zero + 4: 6410a0fb cv.subrotmj.div2 ra,ra,ra + 8: 6421217b cv.subrotmj.div2 sp,sp,sp + c: 6484247b cv.subrotmj.div2 s0,s0,s0 + 10: 654a2a7b cv.subrotmj.div2 s4,s4,s4 + 14: 65ffaffb cv.subrotmj.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.s new file mode 100644 index 00000000000..809fc2d0cbb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj.div2 x0, x0, x0 + cv.subrotmj.div2 x1, x1, x1 + cv.subrotmj.div2 x2, x2, x2 + cv.subrotmj.div2 x8, x8, x8 + cv.subrotmj.div2 x20, x20, x20 + cv.subrotmj.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.d new file mode 100644 index 00000000000..fc97b73b537 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div4-fail.s +#error_output: cv-subrotmj-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.l new file mode 100644 index 00000000000..73b9e0eea13 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj.div4 x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.s new file mode 100644 index 00000000000..e9620aad3fd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj.div4 x32, x32, x32 + cv.subrotmj.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.d new file mode 100644 index 00000000000..a4521a1d420 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400407b cv.subrotmj.div4 zero,zero,zero + 4: 6410c0fb cv.subrotmj.div4 ra,ra,ra + 8: 6421417b cv.subrotmj.div4 sp,sp,sp + c: 6484447b cv.subrotmj.div4 s0,s0,s0 + 10: 654a4a7b cv.subrotmj.div4 s4,s4,s4 + 14: 65ffcffb cv.subrotmj.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.s new file mode 100644 index 00000000000..a6272be9b73 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj.div4 x0, x0, x0 + cv.subrotmj.div4 x1, x1, x1 + cv.subrotmj.div4 x2, x2, x2 + cv.subrotmj.div4 x8, x8, x8 + cv.subrotmj.div4 x20, x20, x20 + cv.subrotmj.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.d new file mode 100644 index 00000000000..fb4e316737d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div8-fail.s +#error_output: cv-subrotmj-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.l new file mode 100644 index 00000000000..558de39886d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj.div8 x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.s new file mode 100644 index 00000000000..4b3b54dd45c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj.div8 x32, x32, x32 + cv.subrotmj.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.d new file mode 100644 index 00000000000..70486913156 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400607b cv.subrotmj.div8 zero,zero,zero + 4: 6410e0fb cv.subrotmj.div8 ra,ra,ra + 8: 6421617b cv.subrotmj.div8 sp,sp,sp + c: 6484647b cv.subrotmj.div8 s0,s0,s0 + 10: 654a6a7b cv.subrotmj.div8 s4,s4,s4 + 14: 65ffeffb cv.subrotmj.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.s new file mode 100644 index 00000000000..4dbabd5df19 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj.div8 x0, x0, x0 + cv.subrotmj.div8 x1, x1, x1 + cv.subrotmj.div8 x2, x2, x2 + cv.subrotmj.div8 x8, x8, x8 + cv.subrotmj.div8 x20, x20, x20 + cv.subrotmj.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-fail.d new file mode 100644 index 00000000000..6cacbb17391 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-fail.s +#error_output: cv-subrotmj-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-fail.l new file mode 100644 index 00000000000..1e7f31b1221 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-fail.s new file mode 100644 index 00000000000..2b05cfcbb48 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj x32, x32, x32 + cv.subrotmj x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-pass.d new file mode 100644 index 00000000000..3f07f1c1fe5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400007b cv.subrotmj zero,zero,zero + 4: 641080fb cv.subrotmj ra,ra,ra + 8: 6421017b cv.subrotmj sp,sp,sp + c: 6484047b cv.subrotmj s0,s0,s0 + 10: 654a0a7b cv.subrotmj s4,s4,s4 + 14: 65ff8ffb cv.subrotmj t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-pass.s new file mode 100644 index 00000000000..838f4d3e677 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj x0, x0, x0 + cv.subrotmj x1, x1, x1 + cv.subrotmj x2, x2, x2 + cv.subrotmj x8, x8, x8 + cv.subrotmj x20, x20, x20 + cv.subrotmj x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-b-fail.d b/gas/testsuite/gas/riscv/cv-xor-b-fail.d new file mode 100644 index 00000000000..1a244431bc7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-b-fail.s +#error_output: cv-xor-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-b-fail.l b/gas/testsuite/gas/riscv/cv-xor-b-fail.l new file mode 100644 index 00000000000..85aba380181 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.b x32,x32,x32' +.*: Error: illegal operands `cv.xor.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-b-fail.s b/gas/testsuite/gas/riscv/cv-xor-b-fail.s new file mode 100644 index 00000000000..c159d6895a9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.b x32, x32, x32 + cv.xor.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-b-pass.d b/gas/testsuite/gas/riscv/cv-xor-b-pass.d new file mode 100644 index 00000000000..5b0dd5cb230 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000107b cv.xor.b zero,zero,zero + 4: 601090fb cv.xor.b ra,ra,ra + 8: 6021117b cv.xor.b sp,sp,sp + c: 6084147b cv.xor.b s0,s0,s0 + 10: 614a1a7b cv.xor.b s4,s4,s4 + 14: 61ff9ffb cv.xor.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-b-pass.s b/gas/testsuite/gas/riscv/cv-xor-b-pass.s new file mode 100644 index 00000000000..8300bbe3d50 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.b x0, x0, x0 + cv.xor.b x1, x1, x1 + cv.xor.b x2, x2, x2 + cv.xor.b x8, x8, x8 + cv.xor.b x20, x20, x20 + cv.xor.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-h-fail.d b/gas/testsuite/gas/riscv/cv-xor-h-fail.d new file mode 100644 index 00000000000..9aee6b64c6f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-h-fail.s +#error_output: cv-xor-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-h-fail.l b/gas/testsuite/gas/riscv/cv-xor-h-fail.l new file mode 100644 index 00000000000..e17ec8a240d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.h x32,x32,x32' +.*: Error: illegal operands `cv.xor.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-h-fail.s b/gas/testsuite/gas/riscv/cv-xor-h-fail.s new file mode 100644 index 00000000000..67f8d5c6ba0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.h x32, x32, x32 + cv.xor.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-h-pass.d b/gas/testsuite/gas/riscv/cv-xor-h-pass.d new file mode 100644 index 00000000000..b6cb78d76bb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000007b cv.xor.h zero,zero,zero + 4: 601080fb cv.xor.h ra,ra,ra + 8: 6021017b cv.xor.h sp,sp,sp + c: 6084047b cv.xor.h s0,s0,s0 + 10: 614a0a7b cv.xor.h s4,s4,s4 + 14: 61ff8ffb cv.xor.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-h-pass.s b/gas/testsuite/gas/riscv/cv-xor-h-pass.s new file mode 100644 index 00000000000..ac68ef1167d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.h x0, x0, x0 + cv.xor.h x1, x1, x1 + cv.xor.h x2, x2, x2 + cv.xor.h x8, x8, x8 + cv.xor.h x20, x20, x20 + cv.xor.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.d new file mode 100644 index 00000000000..bd7c5c156e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-b-fail.s +#error_output: cv-xor-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.l new file mode 100644 index 00000000000..91a28985589 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.xor.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s new file mode 100644 index 00000000000..a6bcb1bcb78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.sc.b x32, x32, x32 + cv.xor.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d new file mode 100644 index 00000000000..c6535c8fab1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000507b cv.xor.sc.b zero,zero,zero + 4: 6010d0fb cv.xor.sc.b ra,ra,ra + 8: 6021517b cv.xor.sc.b sp,sp,sp + c: 6084547b cv.xor.sc.b s0,s0,s0 + 10: 614a5a7b cv.xor.sc.b s4,s4,s4 + 14: 61ffdffb cv.xor.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s new file mode 100644 index 00000000000..ebda07f7c41 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.sc.b x0, x0, x0 + cv.xor.sc.b x1, x1, x1 + cv.xor.sc.b x2, x2, x2 + cv.xor.sc.b x8, x8, x8 + cv.xor.sc.b x20, x20, x20 + cv.xor.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d new file mode 100644 index 00000000000..522bfa09423 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-h-fail.s +#error_output: cv-xor-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l new file mode 100644 index 00000000000..b2417b49029 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.xor.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s new file mode 100644 index 00000000000..26905c966b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.sc.h x32, x32, x32 + cv.xor.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d new file mode 100644 index 00000000000..ee2d378de75 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000407b cv.xor.sc.h zero,zero,zero + 4: 6010c0fb cv.xor.sc.h ra,ra,ra + 8: 6021417b cv.xor.sc.h sp,sp,sp + c: 6084447b cv.xor.sc.h s0,s0,s0 + 10: 614a4a7b cv.xor.sc.h s4,s4,s4 + 14: 61ffcffb cv.xor.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s new file mode 100644 index 00000000000..ee2f8c9b6a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.sc.h x0, x0, x0 + cv.xor.sc.h x1, x1, x1 + cv.xor.sc.h x2, x2, x2 + cv.xor.sc.h x8, x8, x8 + cv.xor.sc.h x20, x20, x20 + cv.xor.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d new file mode 100644 index 00000000000..545b4eee78c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-b-fail.s +#error_output: cv-xor-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l new file mode 100644 index 00000000000..64e90bac715 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sci.b x32,x32,20' +.*: Error: illegal operands `cv.xor.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s new file mode 100644 index 00000000000..2b1ad6a16db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.xor.sci.b x32, x32, 20 + cv.xor.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.xor.sci.b x6, x7, -33 + cv.xor.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d new file mode 100644 index 00000000000..e6f720d4fe9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6140707b cv.xor.sci.b zero,zero,20 + 4: 6140f0fb cv.xor.sci.b ra,ra,20 + 8: 6141717b cv.xor.sci.b sp,sp,20 + c: 6144747b cv.xor.sci.b s0,s0,20 + 10: 614a7a7b cv.xor.sci.b s4,s4,20 + 14: 614ffffb cv.xor.sci.b t6,t6,20 + 18: 6203f37b cv.xor.sci.b t1,t2,-32 + 1c: 6003f37b cv.xor.sci.b t1,t2,0 + 20: 61f3f37b cv.xor.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s new file mode 100644 index 00000000000..c46e1738dfc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.xor.sci.b x0, x0, 20 + cv.xor.sci.b x1, x1, 20 + cv.xor.sci.b x2, x2, 20 + cv.xor.sci.b x8, x8, 20 + cv.xor.sci.b x20, x20, 20 + cv.xor.sci.b x31, x31, 20 + #Immediate Values Test + cv.xor.sci.b x6, x7, -32 + cv.xor.sci.b x6, x7, 0 + cv.xor.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d new file mode 100644 index 00000000000..c857be75b05 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-h-fail.s +#error_output: cv-xor-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l new file mode 100644 index 00000000000..a4124657858 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sci.h x32,x32,20' +.*: Error: illegal operands `cv.xor.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s new file mode 100644 index 00000000000..c100f21df04 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.xor.sci.h x32, x32, 20 + cv.xor.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.xor.sci.h x6, x7, -33 + cv.xor.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d new file mode 100644 index 00000000000..9de3c0e2084 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6140607b cv.xor.sci.h zero,zero,20 + 4: 6140e0fb cv.xor.sci.h ra,ra,20 + 8: 6141617b cv.xor.sci.h sp,sp,20 + c: 6144647b cv.xor.sci.h s0,s0,20 + 10: 614a6a7b cv.xor.sci.h s4,s4,20 + 14: 614feffb cv.xor.sci.h t6,t6,20 + 18: 6203e37b cv.xor.sci.h t1,t2,-32 + 1c: 6003e37b cv.xor.sci.h t1,t2,0 + 20: 61f3e37b cv.xor.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s new file mode 100644 index 00000000000..016147ad4ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.xor.sci.h x0, x0, 20 + cv.xor.sci.h x1, x1, 20 + cv.xor.sci.h x2, x2, 20 + cv.xor.sci.h x8, x8, 20 + cv.xor.sci.h x20, x20, 20 + cv.xor.sci.h x31, x31, 20 + #Immediate Values Test + cv.xor.sci.h x6, x7, -32 + cv.xor.sci.h x6, x7, 0 + cv.xor.sci.h x6, x7, 31 -- GitLab