diff --git a/gas/testsuite/gas/riscv/cv-abs-b-fail.d b/gas/testsuite/gas/riscv/cv-abs-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..07b58a636a0bfe914e5dce226e99e50f4fcc4d6f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-b-fail.s +#error_output: cv-abs-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-abs-b-fail.l b/gas/testsuite/gas/riscv/cv-abs-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..93156ef3807ffcdcb873b769978b46141755d804 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.abs.b x32,x32' +.*: Error: illegal operands `cv.abs.b x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-abs-b-fail.s b/gas/testsuite/gas/riscv/cv-abs-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e2dfb8e054ff138d3fe458d0d514727f366b8201 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.abs.b x32, x32 + cv.abs.b x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-abs-b-pass.d b/gas/testsuite/gas/riscv/cv-abs-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..656b1f5c011357a95fb3b302608f047a9e4768c7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7000107b cv.abs.b zero,zero + 4: 700090fb cv.abs.b ra,ra + 8: 7001117b cv.abs.b sp,sp + c: 7004147b cv.abs.b s0,s0 + 10: 700a1a7b cv.abs.b s4,s4 + 14: 700f9ffb cv.abs.b t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-abs-b-pass.s b/gas/testsuite/gas/riscv/cv-abs-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..6ea328015fedd1b42a574de7d792f1df51084f32 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.abs.b x0, x0 + cv.abs.b x1, x1 + cv.abs.b x2, x2 + cv.abs.b x8, x8 + cv.abs.b x20, x20 + cv.abs.b x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-abs-h-fail.d b/gas/testsuite/gas/riscv/cv-abs-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8e2da38188e26966581abaecd741be91a85387d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-h-fail.s +#error_output: cv-abs-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-abs-h-fail.l b/gas/testsuite/gas/riscv/cv-abs-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..74867e1b6115664a3d5e67c3601cd15844530528 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.abs.h x32,x32' +.*: Error: illegal operands `cv.abs.h x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-abs-h-fail.s b/gas/testsuite/gas/riscv/cv-abs-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..930e79ae5bca2040034469b9f5fa2a92bfe4939a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.abs.h x32, x32 + cv.abs.h x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-abs-h-pass.d b/gas/testsuite/gas/riscv/cv-abs-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..c86318c4bfdf3af6c991b24f6f8fb9026c9117cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-abs-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7000007b cv.abs.h zero,zero + 4: 700080fb cv.abs.h ra,ra + 8: 7001017b cv.abs.h sp,sp + c: 7004047b cv.abs.h s0,s0 + 10: 700a0a7b cv.abs.h s4,s4 + 14: 700f8ffb cv.abs.h t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-abs-h-pass.s b/gas/testsuite/gas/riscv/cv-abs-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..050f403799c29f267c66d101dd3f7b1d9e238b78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-abs-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.abs.h x0, x0 + cv.abs.h x1, x1 + cv.abs.h x2, x2 + cv.abs.h x8, x8 + cv.abs.h x20, x20 + cv.abs.h x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-b-fail.d b/gas/testsuite/gas/riscv/cv-add-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..c9f3cb58070698a3e194e6fbe709568dbc85d147 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-b-fail.s +#error_output: cv-add-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-b-fail.l b/gas/testsuite/gas/riscv/cv-add-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..e43a2c5536b9477c04b375bab3c885c47e3c6194 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.b x32,x32,x32' +.*: Error: illegal operands `cv.add.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-b-fail.s b/gas/testsuite/gas/riscv/cv-add-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..193a295e8586534a9155d86d10e7991f3d424141 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.b x32, x32, x32 + cv.add.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-b-pass.d b/gas/testsuite/gas/riscv/cv-add-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..dc3dfca91da17e727fbbb7bffb8e08c38a69d5f3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000107b cv.add.b zero,zero,zero + 4: 001090fb cv.add.b ra,ra,ra + 8: 0021117b cv.add.b sp,sp,sp + c: 0084147b cv.add.b s0,s0,s0 + 10: 014a1a7b cv.add.b s4,s4,s4 + 14: 01ff9ffb cv.add.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-b-pass.s b/gas/testsuite/gas/riscv/cv-add-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..2cdf11e26d860df41b2995ced04ea5badbfefae5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.b x0, x0, x0 + cv.add.b x1, x1, x1 + cv.add.b x2, x2, x2 + cv.add.b x8, x8, x8 + cv.add.b x20, x20, x20 + cv.add.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-div2-fail.d b/gas/testsuite/gas/riscv/cv-add-div2-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..80764a83175a74bfde9665a49185066c668e9acc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div2-fail.s +#error_output: cv-add-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-div2-fail.l b/gas/testsuite/gas/riscv/cv-add-div2-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..aaf581ef21d37b048b07a8160817ab17e17be4c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.div2 x32,x32,x32' +.*: Error: illegal operands `cv.add.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-div2-fail.s b/gas/testsuite/gas/riscv/cv-add-div2-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..dbf1be61ca31f876d7ec1da217836d1a44352615 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.div2 x32, x32, x32 + cv.add.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-div2-pass.d b/gas/testsuite/gas/riscv/cv-add-div2-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..42e242dedab0d13be01890c8b09813cf1669a352 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6c00207b cv.add.div2 zero,zero,zero + 4: 6c10a0fb cv.add.div2 ra,ra,ra + 8: 6c21217b cv.add.div2 sp,sp,sp + c: 6c84247b cv.add.div2 s0,s0,s0 + 10: 6d4a2a7b cv.add.div2 s4,s4,s4 + 14: 6dffaffb cv.add.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-div2-pass.s b/gas/testsuite/gas/riscv/cv-add-div2-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..396bda9ee77bf6e6bfa11d1d347e4ea2bd35dd54 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.div2 x0, x0, x0 + cv.add.div2 x1, x1, x1 + cv.add.div2 x2, x2, x2 + cv.add.div2 x8, x8, x8 + cv.add.div2 x20, x20, x20 + cv.add.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-div4-fail.d b/gas/testsuite/gas/riscv/cv-add-div4-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..0a355fd470ce8e42e7ab26eaf6fcec40f28fb82e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div4-fail.s +#error_output: cv-add-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-div4-fail.l b/gas/testsuite/gas/riscv/cv-add-div4-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..4f91c5031c8743289acee561eaf77b5d28dc089c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.div4 x32,x32,x32' +.*: Error: illegal operands `cv.add.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-div4-fail.s b/gas/testsuite/gas/riscv/cv-add-div4-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..7dd658bdcda76f35b130a0cd6f6df8143ecbfbd5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.div4 x32, x32, x32 + cv.add.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-div4-pass.d b/gas/testsuite/gas/riscv/cv-add-div4-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..bde5d4dbe9634694f47b9bded10693ff43838f91 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6c00407b cv.add.div4 zero,zero,zero + 4: 6c10c0fb cv.add.div4 ra,ra,ra + 8: 6c21417b cv.add.div4 sp,sp,sp + c: 6c84447b cv.add.div4 s0,s0,s0 + 10: 6d4a4a7b cv.add.div4 s4,s4,s4 + 14: 6dffcffb cv.add.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-div4-pass.s b/gas/testsuite/gas/riscv/cv-add-div4-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e4587ce815c9ad0903e6705571918bddbf597aef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.div4 x0, x0, x0 + cv.add.div4 x1, x1, x1 + cv.add.div4 x2, x2, x2 + cv.add.div4 x8, x8, x8 + cv.add.div4 x20, x20, x20 + cv.add.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-div8-fail.d b/gas/testsuite/gas/riscv/cv-add-div8-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..34702f30b50ba326a562ddac3f18a99408385651 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div8-fail.s +#error_output: cv-add-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-div8-fail.l b/gas/testsuite/gas/riscv/cv-add-div8-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b5628ada078cecc2990e83b1dc7d5e336adf51da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.div8 x32,x32,x32' +.*: Error: illegal operands `cv.add.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-div8-fail.s b/gas/testsuite/gas/riscv/cv-add-div8-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..bedbed050a87372a3443e6efaa0a1bb872f530e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.div8 x32, x32, x32 + cv.add.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-div8-pass.d b/gas/testsuite/gas/riscv/cv-add-div8-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..7ca740337265e19e0320fb1b2c2ca48df5b0c411 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6c00607b cv.add.div8 zero,zero,zero + 4: 6c10e0fb cv.add.div8 ra,ra,ra + 8: 6c21617b cv.add.div8 sp,sp,sp + c: 6c84647b cv.add.div8 s0,s0,s0 + 10: 6d4a6a7b cv.add.div8 s4,s4,s4 + 14: 6dffeffb cv.add.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-div8-pass.s b/gas/testsuite/gas/riscv/cv-add-div8-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..2472f00f34bca0ff2c86caddaba166be10d8aa06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.div8 x0, x0, x0 + cv.add.div8 x1, x1, x1 + cv.add.div8 x2, x2, x2 + cv.add.div8 x8, x8, x8 + cv.add.div8 x20, x20, x20 + cv.add.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-h-fail.d b/gas/testsuite/gas/riscv/cv-add-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..f63d128606e66c244258563ad1ffa4758ad8bd1f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-h-fail.s +#error_output: cv-add-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-h-fail.l b/gas/testsuite/gas/riscv/cv-add-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a82b28674ac4b9595a9578fa4ab37856efd8d71f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.h x32,x32,x32' +.*: Error: illegal operands `cv.add.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-h-fail.s b/gas/testsuite/gas/riscv/cv-add-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..148bf21959fb6979b0dce518225fb7f0bd2a14c0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.h x32, x32, x32 + cv.add.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-h-pass.d b/gas/testsuite/gas/riscv/cv-add-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3b40dac0bafd2537c6906316619d1cc8a06051da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000007b cv.add.h zero,zero,zero + 4: 001080fb cv.add.h ra,ra,ra + 8: 0021017b cv.add.h sp,sp,sp + c: 0084047b cv.add.h s0,s0,s0 + 10: 014a0a7b cv.add.h s4,s4,s4 + 14: 01ff8ffb cv.add.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-h-pass.s b/gas/testsuite/gas/riscv/cv-add-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..2a4bd6942a71a382d2e9e57c5b15eee850d4f177 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.h x0, x0, x0 + cv.add.h x1, x1, x1 + cv.add.h x2, x2, x2 + cv.add.h x8, x8, x8 + cv.add.h x20, x20, x20 + cv.add.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..780f083563301bcccf84be3d1b2fcf5730a90b79 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-b-fail.s +#error_output: cv-add-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..20b1f4fa1dde701c64cee42a9feff02f3cadb264 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.add.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..2a89aca5751f08463c7458170ce6556ea9e415d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.sc.b x32, x32, x32 + cv.add.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..10694b5fa0cddecdb6887dfcef1ef127d4e27576 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000507b cv.add.sc.b zero,zero,zero + 4: 0010d0fb cv.add.sc.b ra,ra,ra + 8: 0021517b cv.add.sc.b sp,sp,sp + c: 0084547b cv.add.sc.b s0,s0,s0 + 10: 014a5a7b cv.add.sc.b s4,s4,s4 + 14: 01ffdffb cv.add.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4a3401d7a5fa2d80588167b5d909d6a38f8bb86c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.sc.b x0, x0, x0 + cv.add.sc.b x1, x1, x1 + cv.add.sc.b x2, x2, x2 + cv.add.sc.b x8, x8, x8 + cv.add.sc.b x20, x20, x20 + cv.add.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..20219670a06741ed76ee03fb92ff7a49889ca078 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-h-fail.s +#error_output: cv-add-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..eaba711f44a5417471959b8a5c688ed76ec67ebe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.add.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9fc87c807d626a085ad538b494e4aac3f83881dc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.add.sc.h x32, x32, x32 + cv.add.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f7ae0be50abb571596ace2f69b16fb4f29866773 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0000407b cv.add.sc.h zero,zero,zero + 4: 0010c0fb cv.add.sc.h ra,ra,ra + 8: 0021417b cv.add.sc.h sp,sp,sp + c: 0084447b cv.add.sc.h s0,s0,s0 + 10: 014a4a7b cv.add.sc.h s4,s4,s4 + 14: 01ffcffb cv.add.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-add-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7aeee046c477179c04c0b0b87ed32f907c7ace3c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.add.sc.h x0, x0, x0 + cv.add.sc.h x1, x1, x1 + cv.add.sc.h x2, x2, x2 + cv.add.sc.h x8, x8, x8 + cv.add.sc.h x20, x20, x20 + cv.add.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..68c1ace4f6de608831fde586c00406523bb25915 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-b-fail.s +#error_output: cv-add-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c3f90cce75989939cee9724e7bc2647eb72b0743 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sci.b x32,x32,20' +.*: Error: illegal operands `cv.add.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..4aa7c516c00d043d69ef287e1b2b3a19579f8423 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.add.sci.b x32, x32, 20 + cv.add.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.add.sci.b x6, x7, -33 + cv.add.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d272fdcd0e332a4bf3c20500e44371165c5232cc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0140707b cv.add.sci.b zero,zero,20 + 4: 0140f0fb cv.add.sci.b ra,ra,20 + 8: 0141717b cv.add.sci.b sp,sp,20 + c: 0144747b cv.add.sci.b s0,s0,20 + 10: 014a7a7b cv.add.sci.b s4,s4,20 + 14: 014ffffb cv.add.sci.b t6,t6,20 + 18: 0203f37b cv.add.sci.b t1,t2,-32 + 1c: 0003f37b cv.add.sci.b t1,t2,0 + 20: 01f3f37b cv.add.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1261bd2801e999d78c8cf149d9cc0188d4fb1467 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.add.sci.b x0, x0, 20 + cv.add.sci.b x1, x1, 20 + cv.add.sci.b x2, x2, 20 + cv.add.sci.b x8, x8, 20 + cv.add.sci.b x20, x20, 20 + cv.add.sci.b x31, x31, 20 + #Immediate Values Test + cv.add.sci.b x6, x7, -32 + cv.add.sci.b x6, x7, 0 + cv.add.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..890c232e52567de342cffd46c3238819f33a5d94 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-h-fail.s +#error_output: cv-add-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..2f0656f83a364e52d32aed8b181de6184d5d6168 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sci.h x32,x32,20' +.*: Error: illegal operands `cv.add.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..7a1cf469a2333e73462a293e46a8bce55dc24250 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.add.sci.h x32, x32, 20 + cv.add.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.add.sci.h x6, x7, -33 + cv.add.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..074068fdf8630cd0672ebf111064d0b4af8d5fd6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-add-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0140607b cv.add.sci.h zero,zero,20 + 4: 0140e0fb cv.add.sci.h ra,ra,20 + 8: 0141617b cv.add.sci.h sp,sp,20 + c: 0144647b cv.add.sci.h s0,s0,20 + 10: 014a6a7b cv.add.sci.h s4,s4,20 + 14: 014feffb cv.add.sci.h t6,t6,20 + 18: 0203e37b cv.add.sci.h t1,t2,-32 + 1c: 0003e37b cv.add.sci.h t1,t2,0 + 20: 01f3e37b cv.add.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..027ca49550eceafc21c531e95953117fa0ddb6aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.add.sci.h x0, x0, 20 + cv.add.sci.h x1, x1, 20 + cv.add.sci.h x2, x2, 20 + cv.add.sci.h x8, x8, 20 + cv.add.sci.h x20, x20, 20 + cv.add.sci.h x31, x31, 20 + #Immediate Values Test + cv.add.sci.h x6, x7, -32 + cv.add.sci.h x6, x7, 0 + cv.add.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-add-sci-h-reg-fail.l b/gas/testsuite/gas/riscv/cv-add-sci-h-reg-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..24742faa4455591f01dc2cd04c1ce93185d7c3e2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-add-sci-h-reg-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.add.sci.h x32, x32, 20' +.*: Error: illegal operands `cv.add.sci.h x33, x33, 20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-and-b-fail.d b/gas/testsuite/gas/riscv/cv-and-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b22747dcc724aab89c4b810174603cdcb2a7266f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-b-fail.s +#error_output: cv-and-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-b-fail.l b/gas/testsuite/gas/riscv/cv-and-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..18102aad53f5f3a1a062316312b5bb6cbb136945 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.b x32,x32,x32' +.*: Error: illegal operands `cv.and.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-b-fail.s b/gas/testsuite/gas/riscv/cv-and-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..192fd54d16f6d430aa8539d244d3ea57e295d62d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.b x32, x32, x32 + cv.and.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-b-pass.d b/gas/testsuite/gas/riscv/cv-and-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..7ec010b2de9ca869198f41a7a751622440601619 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800107b cv.and.b zero,zero,zero + 4: 681090fb cv.and.b ra,ra,ra + 8: 6821117b cv.and.b sp,sp,sp + c: 6884147b cv.and.b s0,s0,s0 + 10: 694a1a7b cv.and.b s4,s4,s4 + 14: 69ff9ffb cv.and.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-b-pass.s b/gas/testsuite/gas/riscv/cv-and-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7a84aa939750cf5abf2f8da6e2f16656e7124926 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.b x0, x0, x0 + cv.and.b x1, x1, x1 + cv.and.b x2, x2, x2 + cv.and.b x8, x8, x8 + cv.and.b x20, x20, x20 + cv.and.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-h-fail.d b/gas/testsuite/gas/riscv/cv-and-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a704b663c7d96e69447eaa0de62c56984dc8ecf4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-h-fail.s +#error_output: cv-and-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-h-fail.l b/gas/testsuite/gas/riscv/cv-and-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a12d6a349db67622a6c675030f34cb248837334b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.h x32,x32,x32' +.*: Error: illegal operands `cv.and.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-h-fail.s b/gas/testsuite/gas/riscv/cv-and-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..98a278b3e3bebbbe652365d4aff1f426ab4a7041 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.h x32, x32, x32 + cv.and.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-h-pass.d b/gas/testsuite/gas/riscv/cv-and-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..1f9b57df1c588ea85f33cfc5510d20573376f242 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800007b cv.and.h zero,zero,zero + 4: 681080fb cv.and.h ra,ra,ra + 8: 6821017b cv.and.h sp,sp,sp + c: 6884047b cv.and.h s0,s0,s0 + 10: 694a0a7b cv.and.h s4,s4,s4 + 14: 69ff8ffb cv.and.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-h-pass.s b/gas/testsuite/gas/riscv/cv-and-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..2d3149b667aedd50a2925e7f281df3058662aa9d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.h x0, x0, x0 + cv.and.h x1, x1, x1 + cv.and.h x2, x2, x2 + cv.and.h x8, x8, x8 + cv.and.h x20, x20, x20 + cv.and.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8a1cfa4e3336a39955958c0455084d68bc22f26d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-b-fail.s +#error_output: cv-and-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..cf9dd0e29351614d62e93437418dab1ea4c90426 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.and.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..780f7532e9b1f71d50a1ec032025c1e07ff75467 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.sc.b x32, x32, x32 + cv.and.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..bdece4adc7e084a7346c508ff6456c63f29fd33c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800507b cv.and.sc.b zero,zero,zero + 4: 6810d0fb cv.and.sc.b ra,ra,ra + 8: 6821517b cv.and.sc.b sp,sp,sp + c: 6884547b cv.and.sc.b s0,s0,s0 + 10: 694a5a7b cv.and.sc.b s4,s4,s4 + 14: 69ffdffb cv.and.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..a4e742fe76e2cc239659b8be5f047f3557da926f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.sc.b x0, x0, x0 + cv.and.sc.b x1, x1, x1 + cv.and.sc.b x2, x2, x2 + cv.and.sc.b x8, x8, x8 + cv.and.sc.b x20, x20, x20 + cv.and.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..e65195da989be25bc81546a849d9fa68a706b6b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-h-fail.s +#error_output: cv-and-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..cc0e3329db6f8672267e741479f02c3898112235 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.and.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c09eb0d1abc2cc6a121239ed01930cbad5fa7b04 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.and.sc.h x32, x32, x32 + cv.and.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..8beb2b34ca8f3498bb1f03b2b4b90fb0d75f1e7c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6800407b cv.and.sc.h zero,zero,zero + 4: 6810c0fb cv.and.sc.h ra,ra,ra + 8: 6821417b cv.and.sc.h sp,sp,sp + c: 6884447b cv.and.sc.h s0,s0,s0 + 10: 694a4a7b cv.and.sc.h s4,s4,s4 + 14: 69ffcffb cv.and.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-and-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..28830c19bee3ba70e75e6a235ac016bdd4980874 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.and.sc.h x0, x0, x0 + cv.and.sc.h x1, x1, x1 + cv.and.sc.h x2, x2, x2 + cv.and.sc.h x8, x8, x8 + cv.and.sc.h x20, x20, x20 + cv.and.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7df594b5dfcb042c617db63b52ead2db510d4163 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-b-fail.s +#error_output: cv-and-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a259452d78d929dfcc1d5e25dcb61c77178651ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sci.b x32,x32,20' +.*: Error: illegal operands `cv.and.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c250ed176da8c95ec653572ea33cf60ece690710 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.and.sci.b x32, x32, 20 + cv.and.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.and.sci.b x6, x7, -33 + cv.and.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..de6b9c5436d672cf9c3876aa9e2b7c4a16f80606 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6940707b cv.and.sci.b zero,zero,20 + 4: 6940f0fb cv.and.sci.b ra,ra,20 + 8: 6941717b cv.and.sci.b sp,sp,20 + c: 6944747b cv.and.sci.b s0,s0,20 + 10: 694a7a7b cv.and.sci.b s4,s4,20 + 14: 694ffffb cv.and.sci.b t6,t6,20 + 18: 6a03f37b cv.and.sci.b t1,t2,-32 + 1c: 6803f37b cv.and.sci.b t1,t2,0 + 20: 69f3f37b cv.and.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4db2d1d79a7c441254a224dc47189b7ec047d8b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.and.sci.b x0, x0, 20 + cv.and.sci.b x1, x1, 20 + cv.and.sci.b x2, x2, 20 + cv.and.sci.b x8, x8, 20 + cv.and.sci.b x20, x20, 20 + cv.and.sci.b x31, x31, 20 + #Immediate Values Test + cv.and.sci.b x6, x7, -32 + cv.and.sci.b x6, x7, 0 + cv.and.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..bf970ff736a0c03b2aea2e18029fcc0777bd8b6a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-h-fail.s +#error_output: cv-and-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..3564a7fce868538ab2fea244881b059af3f1f68e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.and.sci.h x32,x32,20' +.*: Error: illegal operands `cv.and.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..25b85f2a3e93e90189388b150548e4184e2034e1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.and.sci.h x32, x32, 20 + cv.and.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.and.sci.h x6, x7, -33 + cv.and.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..0af22c73a633cf7acd0c50b834e9e08807accd35 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-and-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6940607b cv.and.sci.h zero,zero,20 + 4: 6940e0fb cv.and.sci.h ra,ra,20 + 8: 6941617b cv.and.sci.h sp,sp,20 + c: 6944647b cv.and.sci.h s0,s0,20 + 10: 694a6a7b cv.and.sci.h s4,s4,20 + 14: 694feffb cv.and.sci.h t6,t6,20 + 18: 6a03e37b cv.and.sci.h t1,t2,-32 + 1c: 6803e37b cv.and.sci.h t1,t2,0 + 20: 69f3e37b cv.and.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-and-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4abb2f3daa8b22292de26e19007348a15db918f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-and-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.and.sci.h x0, x0, 20 + cv.and.sci.h x1, x1, 20 + cv.and.sci.h x2, x2, 20 + cv.and.sci.h x8, x8, 20 + cv.and.sci.h x20, x20, 20 + cv.and.sci.h x31, x31, 20 + #Immediate Values Test + cv.and.sci.h x6, x7, -32 + cv.and.sci.h x6, x7, 0 + cv.and.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avg-b-fail.d b/gas/testsuite/gas/riscv/cv-avg-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..bb375b5cd7bbef7f0fbbe893b3916e0bd154fc85 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-b-fail.s +#error_output: cv-avg-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-b-fail.l b/gas/testsuite/gas/riscv/cv-avg-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7b693315d5ee0aac6d76bfc801f0804519a7f872 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.b x32,x32,x32' +.*: Error: illegal operands `cv.avg.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-b-fail.s b/gas/testsuite/gas/riscv/cv-avg-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..93711991590610b09e484a7f88567132396b6fa5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.b x32, x32, x32 + cv.avg.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-b-pass.d b/gas/testsuite/gas/riscv/cv-avg-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f53777e530d0b8d6af2899b75346721d21c6ad70 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000107b cv.avg.b zero,zero,zero + 4: 101090fb cv.avg.b ra,ra,ra + 8: 1021117b cv.avg.b sp,sp,sp + c: 1084147b cv.avg.b s0,s0,s0 + 10: 114a1a7b cv.avg.b s4,s4,s4 + 14: 11ff9ffb cv.avg.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-b-pass.s b/gas/testsuite/gas/riscv/cv-avg-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1829a24774baaf2b8ff9541e2cdaf53e31ad6fa0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.b x0, x0, x0 + cv.avg.b x1, x1, x1 + cv.avg.b x2, x2, x2 + cv.avg.b x8, x8, x8 + cv.avg.b x20, x20, x20 + cv.avg.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-h-fail.d b/gas/testsuite/gas/riscv/cv-avg-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..f68974ce4c9f0e956feac270f676fb5b46c2d558 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-h-fail.s +#error_output: cv-avg-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-h-fail.l b/gas/testsuite/gas/riscv/cv-avg-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..387e31e1f043871d93672cba2f1be1078091f10a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.h x32,x32,x32' +.*: Error: illegal operands `cv.avg.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-h-fail.s b/gas/testsuite/gas/riscv/cv-avg-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9a9171b76aa6793f7278daa93307f2e1b7b94338 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.h x32, x32, x32 + cv.avg.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-h-pass.d b/gas/testsuite/gas/riscv/cv-avg-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..dbd588ce80dab819b24bac7cf6a153e8af9ecadc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000007b cv.avg.h zero,zero,zero + 4: 101080fb cv.avg.h ra,ra,ra + 8: 1021017b cv.avg.h sp,sp,sp + c: 1084047b cv.avg.h s0,s0,s0 + 10: 114a0a7b cv.avg.h s4,s4,s4 + 14: 11ff8ffb cv.avg.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-h-pass.s b/gas/testsuite/gas/riscv/cv-avg-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..6572f47bc24c110e1eeb7bb4c35ff4c50d407dab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.h x0, x0, x0 + cv.avg.h x1, x1, x1 + cv.avg.h x2, x2, x2 + cv.avg.h x8, x8, x8 + cv.avg.h x20, x20, x20 + cv.avg.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..050cd52587875f30a40856e9e05a5a1bbf532023 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-b-fail.s +#error_output: cv-avg-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..dd22457c92d859379a3f2343c0983642f9e67839 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.avg.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b4fcc7157f045a4209f8b94b89d4e3203826c2e6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.sc.b x32, x32, x32 + cv.avg.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..7a381d1aa85121fe72eb7370caf56b1b56a2c730 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000507b cv.avg.sc.b zero,zero,zero + 4: 1010d0fb cv.avg.sc.b ra,ra,ra + 8: 1021517b cv.avg.sc.b sp,sp,sp + c: 1084547b cv.avg.sc.b s0,s0,s0 + 10: 114a5a7b cv.avg.sc.b s4,s4,s4 + 14: 11ffdffb cv.avg.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..65417deec84d33f6214aa8dff483683f35e09e76 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.sc.b x0, x0, x0 + cv.avg.sc.b x1, x1, x1 + cv.avg.sc.b x2, x2, x2 + cv.avg.sc.b x8, x8, x8 + cv.avg.sc.b x20, x20, x20 + cv.avg.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..ff804203b77f7075688ab297d55cbe91efc443c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-h-fail.s +#error_output: cv-avg-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..3df6422a9d431e32b32608db05f45b996ebd7c72 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.avg.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..f0e769cee1b2b53fed8808ca0ceafe4cbb179b4d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avg.sc.h x32, x32, x32 + cv.avg.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..6f7e88554359cd1e6a99f324e7735d2e1babe9f5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1000407b cv.avg.sc.h zero,zero,zero + 4: 1010c0fb cv.avg.sc.h ra,ra,ra + 8: 1021417b cv.avg.sc.h sp,sp,sp + c: 1084447b cv.avg.sc.h s0,s0,s0 + 10: 114a4a7b cv.avg.sc.h s4,s4,s4 + 14: 11ffcffb cv.avg.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..6642c8e983665b0b5eb9b631f1b4cc6eb6311f51 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avg.sc.h x0, x0, x0 + cv.avg.sc.h x1, x1, x1 + cv.avg.sc.h x2, x2, x2 + cv.avg.sc.h x8, x8, x8 + cv.avg.sc.h x20, x20, x20 + cv.avg.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..11aa6e0c706fbe73baab2e21a440b9477587d32e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-b-fail.s +#error_output: cv-avg-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1d66f52499bcc6f4b686a037c246364664dc0557 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sci.b x32,x32,20' +.*: Error: illegal operands `cv.avg.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5eed74ad3c63a7613fd2f170bddcd4ca239a7409 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avg.sci.b x32, x32, 20 + cv.avg.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.avg.sci.b x6, x7, -33 + cv.avg.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..9ebc5f5b0e44986933b9ddb83a949b00eb6cb6dd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1140707b cv.avg.sci.b zero,zero,20 + 4: 1140f0fb cv.avg.sci.b ra,ra,20 + 8: 1141717b cv.avg.sci.b sp,sp,20 + c: 1144747b cv.avg.sci.b s0,s0,20 + 10: 114a7a7b cv.avg.sci.b s4,s4,20 + 14: 114ffffb cv.avg.sci.b t6,t6,20 + 18: 1203f37b cv.avg.sci.b t1,t2,-32 + 1c: 1003f37b cv.avg.sci.b t1,t2,0 + 20: 11f3f37b cv.avg.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..726677aaa973619e97fcef697542aef65d3bc26a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avg.sci.b x0, x0, 20 + cv.avg.sci.b x1, x1, 20 + cv.avg.sci.b x2, x2, 20 + cv.avg.sci.b x8, x8, 20 + cv.avg.sci.b x20, x20, 20 + cv.avg.sci.b x31, x31, 20 + #Immediate Values Test + cv.avg.sci.b x6, x7, -32 + cv.avg.sci.b x6, x7, 0 + cv.avg.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..5f60742606442ea6fb2b26518fd6a02ea9af8f71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-h-fail.s +#error_output: cv-avg-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a5bc7a5cdb947dc87c5e31ee8b2ea4c04f28b193 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avg.sci.h x32,x32,20' +.*: Error: illegal operands `cv.avg.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..ae476ed9475dc08db772b4cc6945a8422362b70e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avg.sci.h x32, x32, 20 + cv.avg.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.avg.sci.h x6, x7, -33 + cv.avg.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d4304f53bea8414e48d5a12fa2ee575ce5680ebe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avg-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1140607b cv.avg.sci.h zero,zero,20 + 4: 1140e0fb cv.avg.sci.h ra,ra,20 + 8: 1141617b cv.avg.sci.h sp,sp,20 + c: 1144647b cv.avg.sci.h s0,s0,20 + 10: 114a6a7b cv.avg.sci.h s4,s4,20 + 14: 114feffb cv.avg.sci.h t6,t6,20 + 18: 1203e37b cv.avg.sci.h t1,t2,-32 + 1c: 1003e37b cv.avg.sci.h t1,t2,0 + 20: 11f3e37b cv.avg.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..831c7812e69002846c0d762bd9317e736647503f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avg-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avg.sci.h x0, x0, 20 + cv.avg.sci.h x1, x1, 20 + cv.avg.sci.h x2, x2, 20 + cv.avg.sci.h x8, x8, 20 + cv.avg.sci.h x20, x20, 20 + cv.avg.sci.h x31, x31, 20 + #Immediate Values Test + cv.avg.sci.h x6, x7, -32 + cv.avg.sci.h x6, x7, 0 + cv.avg.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-fail.d b/gas/testsuite/gas/riscv/cv-avgu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..25450d4ebbdde6b8e4b7e518069dc73198815575 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-b-fail.s +#error_output: cv-avgu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-fail.l b/gas/testsuite/gas/riscv/cv-avgu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..945d5b11ad7e846992944091c6e2427065ff000f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.b x32,x32,x32' +.*: Error: illegal operands `cv.avgu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-fail.s b/gas/testsuite/gas/riscv/cv-avgu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b82b8f11107615a17a61b57f076d45656be97ecd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.b x32, x32, x32 + cv.avgu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-pass.d b/gas/testsuite/gas/riscv/cv-avgu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b10162c7e22b59347cdff3c8eb097e07b83d5940 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800107b cv.avgu.b zero,zero,zero + 4: 181090fb cv.avgu.b ra,ra,ra + 8: 1821117b cv.avgu.b sp,sp,sp + c: 1884147b cv.avgu.b s0,s0,s0 + 10: 194a1a7b cv.avgu.b s4,s4,s4 + 14: 19ff9ffb cv.avgu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-b-pass.s b/gas/testsuite/gas/riscv/cv-avgu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b36cadcaf2d976b9d8f50f72e961970f52cb3ae4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.b x0, x0, x0 + cv.avgu.b x1, x1, x1 + cv.avgu.b x2, x2, x2 + cv.avgu.b x8, x8, x8 + cv.avgu.b x20, x20, x20 + cv.avgu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-fail.d b/gas/testsuite/gas/riscv/cv-avgu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..dd95a185877be955a2bb3a487584352b3d0e1f5b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-h-fail.s +#error_output: cv-avgu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-fail.l b/gas/testsuite/gas/riscv/cv-avgu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7c8f1554713f268b10a371de4df3b60fc3a7a096 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.h x32,x32,x32' +.*: Error: illegal operands `cv.avgu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-fail.s b/gas/testsuite/gas/riscv/cv-avgu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a384e97dad04de3559eb9aeb78dc8d3b1c67e4b7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.h x32, x32, x32 + cv.avgu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-pass.d b/gas/testsuite/gas/riscv/cv-avgu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..68e46c1232a6b28d3999869ee08979c8e1cebf64 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800007b cv.avgu.h zero,zero,zero + 4: 181080fb cv.avgu.h ra,ra,ra + 8: 1821017b cv.avgu.h sp,sp,sp + c: 1884047b cv.avgu.h s0,s0,s0 + 10: 194a0a7b cv.avgu.h s4,s4,s4 + 14: 19ff8ffb cv.avgu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-h-pass.s b/gas/testsuite/gas/riscv/cv-avgu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7f5cc08c4598bec3c098b75dfaa1686ef8bbbc80 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.h x0, x0, x0 + cv.avgu.h x1, x1, x1 + cv.avgu.h x2, x2, x2 + cv.avgu.h x8, x8, x8 + cv.avgu.h x20, x20, x20 + cv.avgu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..89011f4a5106a283b282770b611afc9c8cb60d7c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-b-fail.s +#error_output: cv-avgu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..477e1703fd2c8bc03474e538628bed40a4d9877c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.avgu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a778c92bcdcd6f862cf5a16ba6704f332bf56ce3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.sc.b x32, x32, x32 + cv.avgu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..05c245d08c1a3e768cb36be2415c8553800beddf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800507b cv.avgu.sc.b zero,zero,zero + 4: 1810d0fb cv.avgu.sc.b ra,ra,ra + 8: 1821517b cv.avgu.sc.b sp,sp,sp + c: 1884547b cv.avgu.sc.b s0,s0,s0 + 10: 194a5a7b cv.avgu.sc.b s4,s4,s4 + 14: 19ffdffb cv.avgu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..731cb07109e7ede7582adef6a75171b6a7c0e012 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.sc.b x0, x0, x0 + cv.avgu.sc.b x1, x1, x1 + cv.avgu.sc.b x2, x2, x2 + cv.avgu.sc.b x8, x8, x8 + cv.avgu.sc.b x20, x20, x20 + cv.avgu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..ae77453294ad0e86ea575b6c648c8c971c5beef1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-h-fail.s +#error_output: cv-avgu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b4192d02b66ea5a82ecaad91770d37fb0d81e8fa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.avgu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..bd031f155f3835ec6600040343fc6940ee988237 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.avgu.sc.h x32, x32, x32 + cv.avgu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..048f00a994431ddfbb000fad87a8c8d99461e280 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1800407b cv.avgu.sc.h zero,zero,zero + 4: 1810c0fb cv.avgu.sc.h ra,ra,ra + 8: 1821417b cv.avgu.sc.h sp,sp,sp + c: 1884447b cv.avgu.sc.h s0,s0,s0 + 10: 194a4a7b cv.avgu.sc.h s4,s4,s4 + 14: 19ffcffb cv.avgu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b22a133e9d908777296d57b826c8e0024cfa53e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.avgu.sc.h x0, x0, x0 + cv.avgu.sc.h x1, x1, x1 + cv.avgu.sc.h x2, x2, x2 + cv.avgu.sc.h x8, x8, x8 + cv.avgu.sc.h x20, x20, x20 + cv.avgu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..bace8babc9205e2babe835ee7a506a503c524054 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-b-fail.s +#error_output: cv-avgu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..00c22293b6c4f6f24a0325b7fbb647397c348e97 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.avgu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c8f9ee5c12ad4e417c53939f992f0284c9978ba3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avgu.sci.b x32, x32, 20 + cv.avgu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.avgu.sci.b x6, x7, -33 + cv.avgu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b8db390e44ae9873506ebb8f964d362ea0115f78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1940707b cv.avgu.sci.b zero,zero,20 + 4: 1940f0fb cv.avgu.sci.b ra,ra,20 + 8: 1941717b cv.avgu.sci.b sp,sp,20 + c: 1944747b cv.avgu.sci.b s0,s0,20 + 10: 194a7a7b cv.avgu.sci.b s4,s4,20 + 14: 194ffffb cv.avgu.sci.b t6,t6,20 + 18: 1a03f37b cv.avgu.sci.b t1,t2,-32 + 1c: 1803f37b cv.avgu.sci.b t1,t2,0 + 20: 19f3f37b cv.avgu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b276d7f45b6c513a2cc7d7f64258d65334aacca0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avgu.sci.b x0, x0, 20 + cv.avgu.sci.b x1, x1, 20 + cv.avgu.sci.b x2, x2, 20 + cv.avgu.sci.b x8, x8, 20 + cv.avgu.sci.b x20, x20, 20 + cv.avgu.sci.b x31, x31, 20 + #Immediate Values Test + cv.avgu.sci.b x6, x7, -32 + cv.avgu.sci.b x6, x7, 0 + cv.avgu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3826b72f9d2d692179c4a21f7c58c83995281e2c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-h-fail.s +#error_output: cv-avgu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a4070f4170b38a6566801d810e1b12c7d5fe8889 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.avgu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.avgu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c9ae574d88847cf47a1a81d1c41d382e0fb2ed2d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.avgu.sci.h x32, x32, 20 + cv.avgu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.avgu.sci.h x6, x7, -33 + cv.avgu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..a34f5dc371818b529287dba3be2fbcd2fe63412c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-avgu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1940607b cv.avgu.sci.h zero,zero,20 + 4: 1940e0fb cv.avgu.sci.h ra,ra,20 + 8: 1941617b cv.avgu.sci.h sp,sp,20 + c: 1944647b cv.avgu.sci.h s0,s0,20 + 10: 194a6a7b cv.avgu.sci.h s4,s4,20 + 14: 194feffb cv.avgu.sci.h t6,t6,20 + 18: 1a03e37b cv.avgu.sci.h t1,t2,-32 + 1c: 1803e37b cv.avgu.sci.h t1,t2,0 + 20: 19f3e37b cv.avgu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..cf16ff3eb5cdd02a2ee216d7681a64ad72cb9019 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-avgu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.avgu.sci.h x0, x0, 20 + cv.avgu.sci.h x1, x1, 20 + cv.avgu.sci.h x2, x2, 20 + cv.avgu.sci.h x8, x8, 20 + cv.avgu.sci.h x20, x20, 20 + cv.avgu.sci.h x31, x31, 20 + #Immediate Values Test + cv.avgu.sci.h x6, x7, -32 + cv.avgu.sci.h x6, x7, 0 + cv.avgu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a4e1f8e19527fded680a4cd0bd48dde4cad38506 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-b-fail.s +#error_output: cv-cmpeq-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..4aac9f46da2e1d80c73e0b7409e70f08fcf5b47b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9b6e33703a32575e7562755f82a9ba1f176c7c99 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.b x32, x32, x32 + cv.cmpeq.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..8427be1310a0bf69ee88f4c4434088fa21a30f00 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400107b cv.cmpeq.b zero,zero,zero + 4: 041090fb cv.cmpeq.b ra,ra,ra + 8: 0421117b cv.cmpeq.b sp,sp,sp + c: 0484147b cv.cmpeq.b s0,s0,s0 + 10: 054a1a7b cv.cmpeq.b s4,s4,s4 + 14: 05ff9ffb cv.cmpeq.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..11496e533c99ab221c068d4eb6bf2938ccfec65e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.b x0, x0, x0 + cv.cmpeq.b x1, x1, x1 + cv.cmpeq.b x2, x2, x2 + cv.cmpeq.b x8, x8, x8 + cv.cmpeq.b x20, x20, x20 + cv.cmpeq.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a3835eff5fa07e6499e95dd599dadac41de6cb0e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-h-fail.s +#error_output: cv-cmpeq-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a4a2d73299caa4e80d4c879fe66524c88cc828d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..7e5f0d0b0d12da231d365004a8f1e9248bb47f9d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.h x32, x32, x32 + cv.cmpeq.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d8833609d570b9ad0ea09afddebe02fa8c23f6b0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400007b cv.cmpeq.h zero,zero,zero + 4: 041080fb cv.cmpeq.h ra,ra,ra + 8: 0421017b cv.cmpeq.h sp,sp,sp + c: 0484047b cv.cmpeq.h s0,s0,s0 + 10: 054a0a7b cv.cmpeq.h s4,s4,s4 + 14: 05ff8ffb cv.cmpeq.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..209aff817702ff10b473c00f3e69c7df11744d0d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.h x0, x0, x0 + cv.cmpeq.h x1, x1, x1 + cv.cmpeq.h x2, x2, x2 + cv.cmpeq.h x8, x8, x8 + cv.cmpeq.h x20, x20, x20 + cv.cmpeq.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a2a13d2ffdf5a48417867e9f463c9d01ff5ea0ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-b-fail.s +#error_output: cv-cmpeq-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..43c0f88c42b8acc1ce61ebac2c68fb4a5005f3b9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e4923d9594382e69ec6bb387e8341c1f19baa39e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.sc.b x32, x32, x32 + cv.cmpeq.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..42f11ec3607156e9303f0ef7b287f90253cbd9ff --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400507b cv.cmpeq.sc.b zero,zero,zero + 4: 0410d0fb cv.cmpeq.sc.b ra,ra,ra + 8: 0421517b cv.cmpeq.sc.b sp,sp,sp + c: 0484547b cv.cmpeq.sc.b s0,s0,s0 + 10: 054a5a7b cv.cmpeq.sc.b s4,s4,s4 + 14: 05ffdffb cv.cmpeq.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..a67ccd388e91817e8cb6d5fe6abadc741897cfa0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.sc.b x0, x0, x0 + cv.cmpeq.sc.b x1, x1, x1 + cv.cmpeq.sc.b x2, x2, x2 + cv.cmpeq.sc.b x8, x8, x8 + cv.cmpeq.sc.b x20, x20, x20 + cv.cmpeq.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3d7e3fb0e222545b25e8a6c8a91a94516fb63725 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-h-fail.s +#error_output: cv-cmpeq-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..13275a99112e892820bff9ef53c8767729216f6a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpeq.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c09e8c9fc214ecb68b5dd38d4f62a03b8d92ac82 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpeq.sc.h x32, x32, x32 + cv.cmpeq.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..74afa8410c9c0d5a21d103121e06f6b531991097 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0400407b cv.cmpeq.sc.h zero,zero,zero + 4: 0410c0fb cv.cmpeq.sc.h ra,ra,ra + 8: 0421417b cv.cmpeq.sc.h sp,sp,sp + c: 0484447b cv.cmpeq.sc.h s0,s0,s0 + 10: 054a4a7b cv.cmpeq.sc.h s4,s4,s4 + 14: 05ffcffb cv.cmpeq.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f8f2c279618464c676a65228d777c01c6585723b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpeq.sc.h x0, x0, x0 + cv.cmpeq.sc.h x1, x1, x1 + cv.cmpeq.sc.h x2, x2, x2 + cv.cmpeq.sc.h x8, x8, x8 + cv.cmpeq.sc.h x20, x20, x20 + cv.cmpeq.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..9ceea8712b9607b1d1b11031a99edde61916008d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-b-fail.s +#error_output: cv-cmpeq-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0d488f66ce123394cb524f9234534397af81ca37 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpeq.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..eb02b37328425a6eb1ad5269adae8154f41cf853 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpeq.sci.b x32, x32, 20 + cv.cmpeq.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpeq.sci.b x6, x7, -33 + cv.cmpeq.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..11970e7b9abe000564f787524992efbec7cb8cb0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0540707b cv.cmpeq.sci.b zero,zero,20 + 4: 0540f0fb cv.cmpeq.sci.b ra,ra,20 + 8: 0541717b cv.cmpeq.sci.b sp,sp,20 + c: 0544747b cv.cmpeq.sci.b s0,s0,20 + 10: 054a7a7b cv.cmpeq.sci.b s4,s4,20 + 14: 054ffffb cv.cmpeq.sci.b t6,t6,20 + 18: 0603f37b cv.cmpeq.sci.b t1,t2,-32 + 1c: 0403f37b cv.cmpeq.sci.b t1,t2,0 + 20: 05f3f37b cv.cmpeq.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..891c61def45497e1a4ff4583c3dad16deee80d23 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpeq.sci.b x0, x0, 20 + cv.cmpeq.sci.b x1, x1, 20 + cv.cmpeq.sci.b x2, x2, 20 + cv.cmpeq.sci.b x8, x8, 20 + cv.cmpeq.sci.b x20, x20, 20 + cv.cmpeq.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpeq.sci.b x6, x7, -32 + cv.cmpeq.sci.b x6, x7, 0 + cv.cmpeq.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..80d4e28e055c2556a09970dd4db9bfa517c23cae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-h-fail.s +#error_output: cv-cmpeq-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..77a6cd56bf16a578407cc923e56e7d5680d82f6b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpeq.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpeq.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..ece9bd5b297835ab375e850e62156015dda55dcc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpeq.sci.h x32, x32, 20 + cv.cmpeq.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpeq.sci.h x6, x7, -33 + cv.cmpeq.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..352caee8243afcb6e64203702b6fe914bebaee6f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpeq-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0540607b cv.cmpeq.sci.h zero,zero,20 + 4: 0540e0fb cv.cmpeq.sci.h ra,ra,20 + 8: 0541617b cv.cmpeq.sci.h sp,sp,20 + c: 0544647b cv.cmpeq.sci.h s0,s0,20 + 10: 054a6a7b cv.cmpeq.sci.h s4,s4,20 + 14: 054feffb cv.cmpeq.sci.h t6,t6,20 + 18: 0603e37b cv.cmpeq.sci.h t1,t2,-32 + 1c: 0403e37b cv.cmpeq.sci.h t1,t2,0 + 20: 05f3e37b cv.cmpeq.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4eee62b625f2536bcd3028bce8eb1f9a5e4d38b0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpeq-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpeq.sci.h x0, x0, 20 + cv.cmpeq.sci.h x1, x1, 20 + cv.cmpeq.sci.h x2, x2, 20 + cv.cmpeq.sci.h x8, x8, 20 + cv.cmpeq.sci.h x20, x20, 20 + cv.cmpeq.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpeq.sci.h x6, x7, -32 + cv.cmpeq.sci.h x6, x7, 0 + cv.cmpeq.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..9fcf0e70f2b2149ddbe81cce5991d6642f33ebec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-b-fail.s +#error_output: cv-cmpge-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a08e74fe104ffbb1f2252051730360c22df7995b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0d5a7453124ce670e1ec5a2462fc51d0366eddea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.b x32, x32, x32 + cv.cmpge.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..da510d7c2311251ad363b3502a2c0fe0b6cee9a5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00107b cv.cmpge.b zero,zero,zero + 4: 1c1090fb cv.cmpge.b ra,ra,ra + 8: 1c21117b cv.cmpge.b sp,sp,sp + c: 1c84147b cv.cmpge.b s0,s0,s0 + 10: 1d4a1a7b cv.cmpge.b s4,s4,s4 + 14: 1dff9ffb cv.cmpge.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..126d8b52de2c2db4dee2c39dfed70202eb16230d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.b x0, x0, x0 + cv.cmpge.b x1, x1, x1 + cv.cmpge.b x2, x2, x2 + cv.cmpge.b x8, x8, x8 + cv.cmpge.b x20, x20, x20 + cv.cmpge.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..24359f8767d1fdc2d1a3d6586f386e7f7948365f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-h-fail.s +#error_output: cv-cmpge-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a9f0019ae9528c9ded6004b3ed21520c464ccb72 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..650213a4591b7adcb556a023cae6c603cb78a7bc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.h x32, x32, x32 + cv.cmpge.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e1b136d205f76962b8c240d25ebf487b289f22f9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00007b cv.cmpge.h zero,zero,zero + 4: 1c1080fb cv.cmpge.h ra,ra,ra + 8: 1c21017b cv.cmpge.h sp,sp,sp + c: 1c84047b cv.cmpge.h s0,s0,s0 + 10: 1d4a0a7b cv.cmpge.h s4,s4,s4 + 14: 1dff8ffb cv.cmpge.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..6a6dd7f6aecd6f6c329fc2363c9aa988fc5446b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.h x0, x0, x0 + cv.cmpge.h x1, x1, x1 + cv.cmpge.h x2, x2, x2 + cv.cmpge.h x8, x8, x8 + cv.cmpge.h x20, x20, x20 + cv.cmpge.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3ea95c1da24215a6444cd680d66dc99b028eeebf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-b-fail.s +#error_output: cv-cmpge-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..2d73720e32cfa940b916267e5fc409f17eefb2f9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9c13024b08b1d954f383cef083a6d29e7635eec5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.sc.b x32, x32, x32 + cv.cmpge.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..56c5b1b7a4bd7cb468c48417d8d75bb4ee730e06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00507b cv.cmpge.sc.b zero,zero,zero + 4: 1c10d0fb cv.cmpge.sc.b ra,ra,ra + 8: 1c21517b cv.cmpge.sc.b sp,sp,sp + c: 1c84547b cv.cmpge.sc.b s0,s0,s0 + 10: 1d4a5a7b cv.cmpge.sc.b s4,s4,s4 + 14: 1dffdffb cv.cmpge.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..d6a61c21eae441573fe2fc7eb15f374f6f0348d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.sc.b x0, x0, x0 + cv.cmpge.sc.b x1, x1, x1 + cv.cmpge.sc.b x2, x2, x2 + cv.cmpge.sc.b x8, x8, x8 + cv.cmpge.sc.b x20, x20, x20 + cv.cmpge.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..62060191f529572dfba9742dc7ec08e80e0db9f2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-h-fail.s +#error_output: cv-cmpge-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..97c55e41c9083ce23de846b0ba58b8474ed4ea37 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpge.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..93bbb03db2ad8df6560f17c373e903bc41515e9d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpge.sc.h x32, x32, x32 + cv.cmpge.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ae3051f8ed054705dda1e29dd16ab31996ebc1b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1c00407b cv.cmpge.sc.h zero,zero,zero + 4: 1c10c0fb cv.cmpge.sc.h ra,ra,ra + 8: 1c21417b cv.cmpge.sc.h sp,sp,sp + c: 1c84447b cv.cmpge.sc.h s0,s0,s0 + 10: 1d4a4a7b cv.cmpge.sc.h s4,s4,s4 + 14: 1dffcffb cv.cmpge.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1458f22df0648b3b992ec7abc776cb2ed1514312 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpge.sc.h x0, x0, x0 + cv.cmpge.sc.h x1, x1, x1 + cv.cmpge.sc.h x2, x2, x2 + cv.cmpge.sc.h x8, x8, x8 + cv.cmpge.sc.h x20, x20, x20 + cv.cmpge.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..4ce717d375143277edacebe90f8ac536db23ba83 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-b-fail.s +#error_output: cv-cmpge-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..cfebdde1262a4be066047b57840ee6bb6a5e211d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpge.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e87d0d2bbd78758ab85a6fe46fda9ac45bb7c123 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpge.sci.b x32, x32, 20 + cv.cmpge.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpge.sci.b x6, x7, -33 + cv.cmpge.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..8283ca50e9561fec68f79c97e7c7a682da5f4bca --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1d40707b cv.cmpge.sci.b zero,zero,20 + 4: 1d40f0fb cv.cmpge.sci.b ra,ra,20 + 8: 1d41717b cv.cmpge.sci.b sp,sp,20 + c: 1d44747b cv.cmpge.sci.b s0,s0,20 + 10: 1d4a7a7b cv.cmpge.sci.b s4,s4,20 + 14: 1d4ffffb cv.cmpge.sci.b t6,t6,20 + 18: 1e03f37b cv.cmpge.sci.b t1,t2,-32 + 1c: 1c03f37b cv.cmpge.sci.b t1,t2,0 + 20: 1df3f37b cv.cmpge.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f78c97537c81fb2cd9692720c63b13f8b2df1fec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpge.sci.b x0, x0, 20 + cv.cmpge.sci.b x1, x1, 20 + cv.cmpge.sci.b x2, x2, 20 + cv.cmpge.sci.b x8, x8, 20 + cv.cmpge.sci.b x20, x20, 20 + cv.cmpge.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpge.sci.b x6, x7, -32 + cv.cmpge.sci.b x6, x7, 0 + cv.cmpge.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..08a4296ba736310eb3d985ec1cbb6fcc68da4cf3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-h-fail.s +#error_output: cv-cmpge-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b29956b0d6c6330a7c4e905334339c9e95a0eb29 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpge.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpge.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..07ec29ce17f5c2b21f1b574ed58e5bda0d4b0818 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpge.sci.h x32, x32, 20 + cv.cmpge.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpge.sci.h x6, x7, -33 + cv.cmpge.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3bb1e1a0d2a769a968466bf6017226a77c42a4a7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpge-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1d40607b cv.cmpge.sci.h zero,zero,20 + 4: 1d40e0fb cv.cmpge.sci.h ra,ra,20 + 8: 1d41617b cv.cmpge.sci.h sp,sp,20 + c: 1d44647b cv.cmpge.sci.h s0,s0,20 + 10: 1d4a6a7b cv.cmpge.sci.h s4,s4,20 + 14: 1d4feffb cv.cmpge.sci.h t6,t6,20 + 18: 1e03e37b cv.cmpge.sci.h t1,t2,-32 + 1c: 1c03e37b cv.cmpge.sci.h t1,t2,0 + 20: 1df3e37b cv.cmpge.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..0410c9bcfd93abbc7651fb90f3961ff58314779b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpge-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpge.sci.h x0, x0, 20 + cv.cmpge.sci.h x1, x1, 20 + cv.cmpge.sci.h x2, x2, 20 + cv.cmpge.sci.h x8, x8, 20 + cv.cmpge.sci.h x20, x20, 20 + cv.cmpge.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpge.sci.h x6, x7, -32 + cv.cmpge.sci.h x6, x7, 0 + cv.cmpge.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3d3dcf9f5b693f91b3d6ab522e39c2f38d8d9761 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-b-fail.s +#error_output: cv-cmpgeu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a5765fd2abbeedfdb022b79614ab7a07ee65e4e6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..92c5cdcd72b1327747eff3dde873763b90cd54d6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.b x32, x32, x32 + cv.cmpgeu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b7e41e6c343013c9a1bec85632f7a7818dd652e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00107b cv.cmpgeu.b zero,zero,zero + 4: 3c1090fb cv.cmpgeu.b ra,ra,ra + 8: 3c21117b cv.cmpgeu.b sp,sp,sp + c: 3c84147b cv.cmpgeu.b s0,s0,s0 + 10: 3d4a1a7b cv.cmpgeu.b s4,s4,s4 + 14: 3dff9ffb cv.cmpgeu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..a5102117823cfe8248657fedb5a561c6d3aee95b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.b x0, x0, x0 + cv.cmpgeu.b x1, x1, x1 + cv.cmpgeu.b x2, x2, x2 + cv.cmpgeu.b x8, x8, x8 + cv.cmpgeu.b x20, x20, x20 + cv.cmpgeu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d86c835d5f95fdad46bbc04644cbbff3b140545c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-h-fail.s +#error_output: cv-cmpgeu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..237d1505e056e82d846137dc94f471fbd977b706 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e1f496e794b63c39dca883869b774ab14cfc4e40 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.h x32, x32, x32 + cv.cmpgeu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d9b70f85c9f70727b0667e0fa0304e3be0a86a43 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00007b cv.cmpgeu.h zero,zero,zero + 4: 3c1080fb cv.cmpgeu.h ra,ra,ra + 8: 3c21017b cv.cmpgeu.h sp,sp,sp + c: 3c84047b cv.cmpgeu.h s0,s0,s0 + 10: 3d4a0a7b cv.cmpgeu.h s4,s4,s4 + 14: 3dff8ffb cv.cmpgeu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..845f740d6630b46b8dc4d23355e592ded5347d59 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.h x0, x0, x0 + cv.cmpgeu.h x1, x1, x1 + cv.cmpgeu.h x2, x2, x2 + cv.cmpgeu.h x8, x8, x8 + cv.cmpgeu.h x20, x20, x20 + cv.cmpgeu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..4c6d7390ef7acfe1c183d08e9ced9ab436982fdf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-b-fail.s +#error_output: cv-cmpgeu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..d80803402ba6a6b4815ff3ad83a7126580d37beb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b2072fb84a9e0ff28a5376a0ed4020286f5c16b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sc.b x32, x32, x32 + cv.cmpgeu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..2895ffe1f1ca96460f1c426a97ff33630cedd7b9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00507b cv.cmpgeu.sc.b zero,zero,zero + 4: 3c10d0fb cv.cmpgeu.sc.b ra,ra,ra + 8: 3c21517b cv.cmpgeu.sc.b sp,sp,sp + c: 3c84547b cv.cmpgeu.sc.b s0,s0,s0 + 10: 3d4a5a7b cv.cmpgeu.sc.b s4,s4,s4 + 14: 3dffdffb cv.cmpgeu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..d9da9a8b4a645e91c9f25095e6614cad217a3ef7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.sc.b x0, x0, x0 + cv.cmpgeu.sc.b x1, x1, x1 + cv.cmpgeu.sc.b x2, x2, x2 + cv.cmpgeu.sc.b x8, x8, x8 + cv.cmpgeu.sc.b x20, x20, x20 + cv.cmpgeu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..e4da8d6c87994c3ffc74b997adf598b45f17b214 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-h-fail.s +#error_output: cv-cmpgeu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..711b5fd0a4f60308e89bf5838c4f7eaf33deebda --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgeu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..1c55aedb1c5fa6551018748c4f437355a9aab228 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sc.h x32, x32, x32 + cv.cmpgeu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..10dde918f7154735a2ab4f07d1115cb4d797d735 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3c00407b cv.cmpgeu.sc.h zero,zero,zero + 4: 3c10c0fb cv.cmpgeu.sc.h ra,ra,ra + 8: 3c21417b cv.cmpgeu.sc.h sp,sp,sp + c: 3c84447b cv.cmpgeu.sc.h s0,s0,s0 + 10: 3d4a4a7b cv.cmpgeu.sc.h s4,s4,s4 + 14: 3dffcffb cv.cmpgeu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..98e27220e32316d9ec6b80fa8029fb186cd2187e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgeu.sc.h x0, x0, x0 + cv.cmpgeu.sc.h x1, x1, x1 + cv.cmpgeu.sc.h x2, x2, x2 + cv.cmpgeu.sc.h x8, x8, x8 + cv.cmpgeu.sc.h x20, x20, x20 + cv.cmpgeu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..ddd48e4116bdcb6695e3b91e7cc2e74b785c6cc5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-b-fail.s +#error_output: cv-cmpgeu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..2b5c698f963655011ddeb13fa220392eb3f9c153 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpgeu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..cffa1bedf0b73d2af49e9e320c66fb79e8761ce6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sci.b x32, x32, 20 + cv.cmpgeu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgeu.sci.b x6, x7, -33 + cv.cmpgeu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..65cb20f6734db83f9d4ebc6f7b7514a68e1b0774 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3d40707b cv.cmpgeu.sci.b zero,zero,20 + 4: 3d40f0fb cv.cmpgeu.sci.b ra,ra,20 + 8: 3d41717b cv.cmpgeu.sci.b sp,sp,20 + c: 3d44747b cv.cmpgeu.sci.b s0,s0,20 + 10: 3d4a7a7b cv.cmpgeu.sci.b s4,s4,20 + 14: 3d4ffffb cv.cmpgeu.sci.b t6,t6,20 + 18: 3e03f37b cv.cmpgeu.sci.b t1,t2,-32 + 1c: 3c03f37b cv.cmpgeu.sci.b t1,t2,0 + 20: 3df3f37b cv.cmpgeu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b05a72cf87e5ab358b0e2485d81a4770596b34bf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgeu.sci.b x0, x0, 20 + cv.cmpgeu.sci.b x1, x1, 20 + cv.cmpgeu.sci.b x2, x2, 20 + cv.cmpgeu.sci.b x8, x8, 20 + cv.cmpgeu.sci.b x20, x20, 20 + cv.cmpgeu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpgeu.sci.b x6, x7, -32 + cv.cmpgeu.sci.b x6, x7, 0 + cv.cmpgeu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8b05795461f6ea5947d74dfb6f06cd7a431a8416 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-h-fail.s +#error_output: cv-cmpgeu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..67af34b76b853ad92d9a9eefdbde716550d14d50 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgeu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpgeu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..bb600368395caf51eb896a5c721badd2d15e9a86 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgeu.sci.h x32, x32, 20 + cv.cmpgeu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgeu.sci.h x6, x7, -33 + cv.cmpgeu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..86303022d4eb8c2eb2fbbec2105f0c3e689f8d82 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgeu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3d40607b cv.cmpgeu.sci.h zero,zero,20 + 4: 3d40e0fb cv.cmpgeu.sci.h ra,ra,20 + 8: 3d41617b cv.cmpgeu.sci.h sp,sp,20 + c: 3d44647b cv.cmpgeu.sci.h s0,s0,20 + 10: 3d4a6a7b cv.cmpgeu.sci.h s4,s4,20 + 14: 3d4feffb cv.cmpgeu.sci.h t6,t6,20 + 18: 3e03e37b cv.cmpgeu.sci.h t1,t2,-32 + 1c: 3c03e37b cv.cmpgeu.sci.h t1,t2,0 + 20: 3df3e37b cv.cmpgeu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..442946b26fb756524c5922ac4f6d430f265ef231 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgeu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgeu.sci.h x0, x0, 20 + cv.cmpgeu.sci.h x1, x1, 20 + cv.cmpgeu.sci.h x2, x2, 20 + cv.cmpgeu.sci.h x8, x8, 20 + cv.cmpgeu.sci.h x20, x20, 20 + cv.cmpgeu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpgeu.sci.h x6, x7, -32 + cv.cmpgeu.sci.h x6, x7, 0 + cv.cmpgeu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..37c865f22786cee60b23899b51ecaf7e8842918e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-b-fail.s +#error_output: cv-cmpgt-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..4e68125dad43295d70e6f400ebc2df2be1dc1358 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..6cf859be6d80370e9bff12b86a7d405ee9cc52b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.b x32, x32, x32 + cv.cmpgt.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..bf6a0bbf20f43ccca302070aff91b4dc783172bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400107b cv.cmpgt.b zero,zero,zero + 4: 141090fb cv.cmpgt.b ra,ra,ra + 8: 1421117b cv.cmpgt.b sp,sp,sp + c: 1484147b cv.cmpgt.b s0,s0,s0 + 10: 154a1a7b cv.cmpgt.b s4,s4,s4 + 14: 15ff9ffb cv.cmpgt.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..9f2f9a82321ebe25782552520a1659531dc3798c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.b x0, x0, x0 + cv.cmpgt.b x1, x1, x1 + cv.cmpgt.b x2, x2, x2 + cv.cmpgt.b x8, x8, x8 + cv.cmpgt.b x20, x20, x20 + cv.cmpgt.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..631a5231bda55928013bc1c9c0cc6f2a846045df --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-h-fail.s +#error_output: cv-cmpgt-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9237078e20a0736078b432d20c82affb2ce29626 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5a371c9183b16ca262ea99b7325f30abdefbfbd9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.h x32, x32, x32 + cv.cmpgt.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..4f661c7560a978d9651fcd4846024d006e557fb7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400007b cv.cmpgt.h zero,zero,zero + 4: 141080fb cv.cmpgt.h ra,ra,ra + 8: 1421017b cv.cmpgt.h sp,sp,sp + c: 1484047b cv.cmpgt.h s0,s0,s0 + 10: 154a0a7b cv.cmpgt.h s4,s4,s4 + 14: 15ff8ffb cv.cmpgt.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..57ebba6ea322b7d291484db40f61eeaa47cfcb90 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.h x0, x0, x0 + cv.cmpgt.h x1, x1, x1 + cv.cmpgt.h x2, x2, x2 + cv.cmpgt.h x8, x8, x8 + cv.cmpgt.h x20, x20, x20 + cv.cmpgt.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..0d75332eaf63132f5da0c06bfa1f7fee5762a917 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-b-fail.s +#error_output: cv-cmpgt-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..526c0b90ba96bdc2ad6e2fc55a757a37081129f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..943b1fffa8f4b6d2205704a6e47dc0ac2526b579 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.sc.b x32, x32, x32 + cv.cmpgt.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..5a6fa4b4db3c0cbeab3119aa914276713611eb74 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400507b cv.cmpgt.sc.b zero,zero,zero + 4: 1410d0fb cv.cmpgt.sc.b ra,ra,ra + 8: 1421517b cv.cmpgt.sc.b sp,sp,sp + c: 1484547b cv.cmpgt.sc.b s0,s0,s0 + 10: 154a5a7b cv.cmpgt.sc.b s4,s4,s4 + 14: 15ffdffb cv.cmpgt.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..64d3f2aac57c51fffaec5b662815fcfc90a274e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.sc.b x0, x0, x0 + cv.cmpgt.sc.b x1, x1, x1 + cv.cmpgt.sc.b x2, x2, x2 + cv.cmpgt.sc.b x8, x8, x8 + cv.cmpgt.sc.b x20, x20, x20 + cv.cmpgt.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..64ae6551783212d32222ed16b39237beb8f90939 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-h-fail.s +#error_output: cv-cmpgt-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..e13663d6149fb7e240bdac2b2906331816e0e01d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgt.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a218dae2ff9bd6b32b1e4bc505193211273a8538 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgt.sc.h x32, x32, x32 + cv.cmpgt.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..5109cf81d2245bc7cebb84e79b4be428907da45a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1400407b cv.cmpgt.sc.h zero,zero,zero + 4: 1410c0fb cv.cmpgt.sc.h ra,ra,ra + 8: 1421417b cv.cmpgt.sc.h sp,sp,sp + c: 1484447b cv.cmpgt.sc.h s0,s0,s0 + 10: 154a4a7b cv.cmpgt.sc.h s4,s4,s4 + 14: 15ffcffb cv.cmpgt.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1571837994b4bc8335227531cd5f1a3c906f5bff --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgt.sc.h x0, x0, x0 + cv.cmpgt.sc.h x1, x1, x1 + cv.cmpgt.sc.h x2, x2, x2 + cv.cmpgt.sc.h x8, x8, x8 + cv.cmpgt.sc.h x20, x20, x20 + cv.cmpgt.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b194ff54b81cd612df4bf0326b175c74e4af9e92 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-b-fail.s +#error_output: cv-cmpgt-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0afcded817f341d82c999d47bee84a6cb141d616 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpgt.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..24eede735b51bda2eea59e5cb00ffe3622ac0709 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgt.sci.b x32, x32, 20 + cv.cmpgt.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgt.sci.b x6, x7, -33 + cv.cmpgt.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..944cab92fbb09d8ba2fda2c130b3c0206d51294d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1540707b cv.cmpgt.sci.b zero,zero,20 + 4: 1540f0fb cv.cmpgt.sci.b ra,ra,20 + 8: 1541717b cv.cmpgt.sci.b sp,sp,20 + c: 1544747b cv.cmpgt.sci.b s0,s0,20 + 10: 154a7a7b cv.cmpgt.sci.b s4,s4,20 + 14: 154ffffb cv.cmpgt.sci.b t6,t6,20 + 18: 1603f37b cv.cmpgt.sci.b t1,t2,-32 + 1c: 1403f37b cv.cmpgt.sci.b t1,t2,0 + 20: 15f3f37b cv.cmpgt.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..62b1dae3c958b1a125ebdb70bc815be5b5f704a5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgt.sci.b x0, x0, 20 + cv.cmpgt.sci.b x1, x1, 20 + cv.cmpgt.sci.b x2, x2, 20 + cv.cmpgt.sci.b x8, x8, 20 + cv.cmpgt.sci.b x20, x20, 20 + cv.cmpgt.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpgt.sci.b x6, x7, -32 + cv.cmpgt.sci.b x6, x7, 0 + cv.cmpgt.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..466bb2447d7c04c12e2caee7b82ba9d633e62a63 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-h-fail.s +#error_output: cv-cmpgt-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..cb3234ffa5dc714ba5cbeb5838d5b72702b1fc22 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgt.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpgt.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..080c6f85615613fe66f6ec7081b77304176a37df --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgt.sci.h x32, x32, 20 + cv.cmpgt.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgt.sci.h x6, x7, -33 + cv.cmpgt.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..08a0b7ceec736e8db26cc3e00a5d09bcf8ca5eea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgt-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 1540607b cv.cmpgt.sci.h zero,zero,20 + 4: 1540e0fb cv.cmpgt.sci.h ra,ra,20 + 8: 1541617b cv.cmpgt.sci.h sp,sp,20 + c: 1544647b cv.cmpgt.sci.h s0,s0,20 + 10: 154a6a7b cv.cmpgt.sci.h s4,s4,20 + 14: 154feffb cv.cmpgt.sci.h t6,t6,20 + 18: 1603e37b cv.cmpgt.sci.h t1,t2,-32 + 1c: 1403e37b cv.cmpgt.sci.h t1,t2,0 + 20: 15f3e37b cv.cmpgt.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7b0722efa313bf35aa22cd8d35cd6094b2212dd9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgt-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgt.sci.h x0, x0, 20 + cv.cmpgt.sci.h x1, x1, 20 + cv.cmpgt.sci.h x2, x2, 20 + cv.cmpgt.sci.h x8, x8, 20 + cv.cmpgt.sci.h x20, x20, 20 + cv.cmpgt.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpgt.sci.h x6, x7, -32 + cv.cmpgt.sci.h x6, x7, 0 + cv.cmpgt.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..38720797b14d1fc67c712b98d5eb8c96ec1b6931 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-b-fail.s +#error_output: cv-cmpgtu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..dec5965c1488324ba4bf8a5f303cd51c4688dfe0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..bb12cf5f7b88ace1ad04d2d8c5c45f0953fedd14 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.b x32, x32, x32 + cv.cmpgtu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e66c93051c7b1e2c62bace7d16daba732e94e706 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400107b cv.cmpgtu.b zero,zero,zero + 4: 341090fb cv.cmpgtu.b ra,ra,ra + 8: 3421117b cv.cmpgtu.b sp,sp,sp + c: 3484147b cv.cmpgtu.b s0,s0,s0 + 10: 354a1a7b cv.cmpgtu.b s4,s4,s4 + 14: 35ff9ffb cv.cmpgtu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e5d782a39fb8abfae680004b11ed6d6deff85c30 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.b x0, x0, x0 + cv.cmpgtu.b x1, x1, x1 + cv.cmpgtu.b x2, x2, x2 + cv.cmpgtu.b x8, x8, x8 + cv.cmpgtu.b x20, x20, x20 + cv.cmpgtu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..2ff3d7e3f822de24e91d39f40e3a120eeaa9fd52 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-h-fail.s +#error_output: cv-cmpgtu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..09b6b0c67fb4b5d0a3ae2594eeceb13da153f6ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..091f250ea419ee9f1b17d5bdacbf7efdcea26d06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.h x32, x32, x32 + cv.cmpgtu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..5f9cee8f926bb364c735d38f715f7adfe2d6bfed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400007b cv.cmpgtu.h zero,zero,zero + 4: 341080fb cv.cmpgtu.h ra,ra,ra + 8: 3421017b cv.cmpgtu.h sp,sp,sp + c: 3484047b cv.cmpgtu.h s0,s0,s0 + 10: 354a0a7b cv.cmpgtu.h s4,s4,s4 + 14: 35ff8ffb cv.cmpgtu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..0abafa19fb2622275cf21e467a11bc2b85a8072c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.h x0, x0, x0 + cv.cmpgtu.h x1, x1, x1 + cv.cmpgtu.h x2, x2, x2 + cv.cmpgtu.h x8, x8, x8 + cv.cmpgtu.h x20, x20, x20 + cv.cmpgtu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..bf38c6ac41f9badf4ea815bc7785efe9bc55250f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-b-fail.s +#error_output: cv-cmpgtu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..8e61b4687f9ffc419f540382bbba72c635393ac5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0a443a7a17a423973e4251bf9ee8cab40b60e0db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sc.b x32, x32, x32 + cv.cmpgtu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..95ff81315d476393f7958161f9129d6b3c0d6487 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400507b cv.cmpgtu.sc.b zero,zero,zero + 4: 3410d0fb cv.cmpgtu.sc.b ra,ra,ra + 8: 3421517b cv.cmpgtu.sc.b sp,sp,sp + c: 3484547b cv.cmpgtu.sc.b s0,s0,s0 + 10: 354a5a7b cv.cmpgtu.sc.b s4,s4,s4 + 14: 35ffdffb cv.cmpgtu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..d8e0fbd37ec188020bc4a0b3e236bf6980d306f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.sc.b x0, x0, x0 + cv.cmpgtu.sc.b x1, x1, x1 + cv.cmpgtu.sc.b x2, x2, x2 + cv.cmpgtu.sc.b x8, x8, x8 + cv.cmpgtu.sc.b x20, x20, x20 + cv.cmpgtu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..25f05665eb3e47e2ab8ff03bbb9761faa9cc0cda --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-h-fail.s +#error_output: cv-cmpgtu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..db82748d2ab4f5f3b5131d7c46eb658e13cb2e95 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpgtu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..cfe448a8400b6a668c1219cd5c4a63488bc0c50d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sc.h x32, x32, x32 + cv.cmpgtu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..864876952a707aea301028213a5c8d91207feb5e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3400407b cv.cmpgtu.sc.h zero,zero,zero + 4: 3410c0fb cv.cmpgtu.sc.h ra,ra,ra + 8: 3421417b cv.cmpgtu.sc.h sp,sp,sp + c: 3484447b cv.cmpgtu.sc.h s0,s0,s0 + 10: 354a4a7b cv.cmpgtu.sc.h s4,s4,s4 + 14: 35ffcffb cv.cmpgtu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..615a7aad62e2e9dc431dfe57405102ff3eb855df --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpgtu.sc.h x0, x0, x0 + cv.cmpgtu.sc.h x1, x1, x1 + cv.cmpgtu.sc.h x2, x2, x2 + cv.cmpgtu.sc.h x8, x8, x8 + cv.cmpgtu.sc.h x20, x20, x20 + cv.cmpgtu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..91de039f54f1e1a71c378a04e4079d0d759144aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-b-fail.s +#error_output: cv-cmpgtu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7ffc96128100ad9b1c48f2c11e84e1add1e471e2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpgtu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..860db56bdfdbf0877907847eaf54ae993c7156d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sci.b x32, x32, 20 + cv.cmpgtu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgtu.sci.b x6, x7, -33 + cv.cmpgtu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..693074d16bda0702858fef159d16a38938ce8ffb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3540707b cv.cmpgtu.sci.b zero,zero,20 + 4: 3540f0fb cv.cmpgtu.sci.b ra,ra,20 + 8: 3541717b cv.cmpgtu.sci.b sp,sp,20 + c: 3544747b cv.cmpgtu.sci.b s0,s0,20 + 10: 354a7a7b cv.cmpgtu.sci.b s4,s4,20 + 14: 354ffffb cv.cmpgtu.sci.b t6,t6,20 + 18: 3603f37b cv.cmpgtu.sci.b t1,t2,-32 + 1c: 3403f37b cv.cmpgtu.sci.b t1,t2,0 + 20: 35f3f37b cv.cmpgtu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..6887053d3551712a1a49672ef5d6c5f93398ec11 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgtu.sci.b x0, x0, 20 + cv.cmpgtu.sci.b x1, x1, 20 + cv.cmpgtu.sci.b x2, x2, 20 + cv.cmpgtu.sci.b x8, x8, 20 + cv.cmpgtu.sci.b x20, x20, 20 + cv.cmpgtu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpgtu.sci.b x6, x7, -32 + cv.cmpgtu.sci.b x6, x7, 0 + cv.cmpgtu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..c93f5fb564c49bd334240620177f874f8f9b7577 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-h-fail.s +#error_output: cv-cmpgtu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..27045b34dbdd421678ee836404c6868cf7495a55 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpgtu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpgtu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..4976d6c359b5ff131b128c8c01ff59ccbca064e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpgtu.sci.h x32, x32, 20 + cv.cmpgtu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpgtu.sci.h x6, x7, -33 + cv.cmpgtu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..a47504eb00fb333843525b208c298b750704be2a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpgtu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3540607b cv.cmpgtu.sci.h zero,zero,20 + 4: 3540e0fb cv.cmpgtu.sci.h ra,ra,20 + 8: 3541617b cv.cmpgtu.sci.h sp,sp,20 + c: 3544647b cv.cmpgtu.sci.h s0,s0,20 + 10: 354a6a7b cv.cmpgtu.sci.h s4,s4,20 + 14: 354feffb cv.cmpgtu.sci.h t6,t6,20 + 18: 3603e37b cv.cmpgtu.sci.h t1,t2,-32 + 1c: 3403e37b cv.cmpgtu.sci.h t1,t2,0 + 20: 35f3e37b cv.cmpgtu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..a06e67e727512690dee8f29291654330a69582d2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpgtu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpgtu.sci.h x0, x0, 20 + cv.cmpgtu.sci.h x1, x1, 20 + cv.cmpgtu.sci.h x2, x2, 20 + cv.cmpgtu.sci.h x8, x8, 20 + cv.cmpgtu.sci.h x20, x20, 20 + cv.cmpgtu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpgtu.sci.h x6, x7, -32 + cv.cmpgtu.sci.h x6, x7, 0 + cv.cmpgtu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-fail.d b/gas/testsuite/gas/riscv/cv-cmple-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..56d85e8d1c1f5d9fcbacbee4511a35110aed4c23 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-b-fail.s +#error_output: cv-cmple-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-fail.l b/gas/testsuite/gas/riscv/cv-cmple-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c1ce1e95e57f0ceb14d6ab2c8eac6f5f1709c8e0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.b x32,x32,x32' +.*: Error: illegal operands `cv.cmple.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-fail.s b/gas/testsuite/gas/riscv/cv-cmple-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..50277474e665f13a652c848860e776c7eb86c120 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.b x32, x32, x32 + cv.cmple.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-pass.d b/gas/testsuite/gas/riscv/cv-cmple-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d3bd65eb5e1c6c78b9537b119d804f1f1b7ffcbf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00107b cv.cmple.b zero,zero,zero + 4: 2c1090fb cv.cmple.b ra,ra,ra + 8: 2c21117b cv.cmple.b sp,sp,sp + c: 2c84147b cv.cmple.b s0,s0,s0 + 10: 2d4a1a7b cv.cmple.b s4,s4,s4 + 14: 2dff9ffb cv.cmple.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-b-pass.s b/gas/testsuite/gas/riscv/cv-cmple-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..fdf4eb245f92c85706732f280ba2b42d9088f5bf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.b x0, x0, x0 + cv.cmple.b x1, x1, x1 + cv.cmple.b x2, x2, x2 + cv.cmple.b x8, x8, x8 + cv.cmple.b x20, x20, x20 + cv.cmple.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-fail.d b/gas/testsuite/gas/riscv/cv-cmple-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..80b2e15dd0052a19fccf9da3d808e69d7969adc9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-h-fail.s +#error_output: cv-cmple-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-fail.l b/gas/testsuite/gas/riscv/cv-cmple-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..90dc4e90829143fac1a57e96784959458baf143a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.h x32,x32,x32' +.*: Error: illegal operands `cv.cmple.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-fail.s b/gas/testsuite/gas/riscv/cv-cmple-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..3cee9fff6ef76d82fc023ac142a15ca85a91f4ef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.h x32, x32, x32 + cv.cmple.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-pass.d b/gas/testsuite/gas/riscv/cv-cmple-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..01a893848b9b0cb63d4aa467ab3ab5d3bd47835f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00007b cv.cmple.h zero,zero,zero + 4: 2c1080fb cv.cmple.h ra,ra,ra + 8: 2c21017b cv.cmple.h sp,sp,sp + c: 2c84047b cv.cmple.h s0,s0,s0 + 10: 2d4a0a7b cv.cmple.h s4,s4,s4 + 14: 2dff8ffb cv.cmple.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-h-pass.s b/gas/testsuite/gas/riscv/cv-cmple-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..35c2c462cc73973c42c8a6483413393da0df18e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.h x0, x0, x0 + cv.cmple.h x1, x1, x1 + cv.cmple.h x2, x2, x2 + cv.cmple.h x8, x8, x8 + cv.cmple.h x20, x20, x20 + cv.cmple.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..02fe239e40b119f35e020f2b033909bd55d19f6e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-b-fail.s +#error_output: cv-cmple-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..74b287452ea6663623a6cffb4db8874fc91e3004 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmple.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..32deb90d22db2c995affc53870f4b7ee1831fcc6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.sc.b x32, x32, x32 + cv.cmple.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..2854d872ba198d15d2844bfcbc522522ac13b024 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00507b cv.cmple.sc.b zero,zero,zero + 4: 2c10d0fb cv.cmple.sc.b ra,ra,ra + 8: 2c21517b cv.cmple.sc.b sp,sp,sp + c: 2c84547b cv.cmple.sc.b s0,s0,s0 + 10: 2d4a5a7b cv.cmple.sc.b s4,s4,s4 + 14: 2dffdffb cv.cmple.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..45b55184e03b49da7d725e2f9a35c446c37fdb02 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.sc.b x0, x0, x0 + cv.cmple.sc.b x1, x1, x1 + cv.cmple.sc.b x2, x2, x2 + cv.cmple.sc.b x8, x8, x8 + cv.cmple.sc.b x20, x20, x20 + cv.cmple.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..1a7744878be1a124f9fcb0a2d465de29b37c8ed8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-h-fail.s +#error_output: cv-cmple-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..781dcb28e9a29bbcd845ff86bcaeb031a2ed4cb9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmple.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..8a480a2c4e4738579700e115b7543d26fd89238b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmple.sc.h x32, x32, x32 + cv.cmple.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..645fc28f6e0605042fdf76b8735f13b81d97ef9a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2c00407b cv.cmple.sc.h zero,zero,zero + 4: 2c10c0fb cv.cmple.sc.h ra,ra,ra + 8: 2c21417b cv.cmple.sc.h sp,sp,sp + c: 2c84447b cv.cmple.sc.h s0,s0,s0 + 10: 2d4a4a7b cv.cmple.sc.h s4,s4,s4 + 14: 2dffcffb cv.cmple.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..719bd8652bff24b538922c0b35d5c64499bf19b7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmple.sc.h x0, x0, x0 + cv.cmple.sc.h x1, x1, x1 + cv.cmple.sc.h x2, x2, x2 + cv.cmple.sc.h x8, x8, x8 + cv.cmple.sc.h x20, x20, x20 + cv.cmple.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..9b71034323525d2da4433ed552f61414bba4ae68 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-b-fail.s +#error_output: cv-cmple-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..6fbc895b3ea3f2e2f626244631e9428801242084 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmple.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..7b461b9ce787c0b77b90da7f961b9851e7ee85ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmple.sci.b x32, x32, 20 + cv.cmple.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmple.sci.b x6, x7, -33 + cv.cmple.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..8da8be19c147730c761d489e18b9e0013fb909ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2d40707b cv.cmple.sci.b zero,zero,20 + 4: 2d40f0fb cv.cmple.sci.b ra,ra,20 + 8: 2d41717b cv.cmple.sci.b sp,sp,20 + c: 2d44747b cv.cmple.sci.b s0,s0,20 + 10: 2d4a7a7b cv.cmple.sci.b s4,s4,20 + 14: 2d4ffffb cv.cmple.sci.b t6,t6,20 + 18: 2e03f37b cv.cmple.sci.b t1,t2,-32 + 1c: 2c03f37b cv.cmple.sci.b t1,t2,0 + 20: 2df3f37b cv.cmple.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..8db8a1e3568fd5dbfbc0570bc48d40774d2753b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmple.sci.b x0, x0, 20 + cv.cmple.sci.b x1, x1, 20 + cv.cmple.sci.b x2, x2, 20 + cv.cmple.sci.b x8, x8, 20 + cv.cmple.sci.b x20, x20, 20 + cv.cmple.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmple.sci.b x6, x7, -32 + cv.cmple.sci.b x6, x7, 0 + cv.cmple.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..587fab8b388ed93ef79bc950d4acbc58d5efa8cc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-h-fail.s +#error_output: cv-cmple-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ccbf473dbd3dc5c45f4d75bf0fa4f71c9a277b1d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmple.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmple.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..7e8beb8dfae68133c35ead1a78116a8bedcebd90 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmple.sci.h x32, x32, 20 + cv.cmple.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmple.sci.h x6, x7, -33 + cv.cmple.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d4df48d03849850c8d96324d3464e830e811b0e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmple-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2d40607b cv.cmple.sci.h zero,zero,20 + 4: 2d40e0fb cv.cmple.sci.h ra,ra,20 + 8: 2d41617b cv.cmple.sci.h sp,sp,20 + c: 2d44647b cv.cmple.sci.h s0,s0,20 + 10: 2d4a6a7b cv.cmple.sci.h s4,s4,20 + 14: 2d4feffb cv.cmple.sci.h t6,t6,20 + 18: 2e03e37b cv.cmple.sci.h t1,t2,-32 + 1c: 2c03e37b cv.cmple.sci.h t1,t2,0 + 20: 2df3e37b cv.cmple.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..83031daecf2dc9d2524b4d4c5faef4b6b0ffc63d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmple-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmple.sci.h x0, x0, 20 + cv.cmple.sci.h x1, x1, 20 + cv.cmple.sci.h x2, x2, 20 + cv.cmple.sci.h x8, x8, 20 + cv.cmple.sci.h x20, x20, 20 + cv.cmple.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmple.sci.h x6, x7, -32 + cv.cmple.sci.h x6, x7, 0 + cv.cmple.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..e9b24cf64943ea7c6f43c040e8f16ad9ff622b47 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-b-fail.s +#error_output: cv-cmpleu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..906bb044ca7790a245e5c2c6bcb59a846e091369 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..4635be74d748a90d271ba56cdd5cf632c4b5d9bc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.b x32, x32, x32 + cv.cmpleu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f00d38f3b5dda2bc40076d1000e56264b953b0e2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00107b cv.cmpleu.b zero,zero,zero + 4: 4c1090fb cv.cmpleu.b ra,ra,ra + 8: 4c21117b cv.cmpleu.b sp,sp,sp + c: 4c84147b cv.cmpleu.b s0,s0,s0 + 10: 4d4a1a7b cv.cmpleu.b s4,s4,s4 + 14: 4dff9ffb cv.cmpleu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7762ca7ab7d58beb168173a11ef963e2c11151a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.b x0, x0, x0 + cv.cmpleu.b x1, x1, x1 + cv.cmpleu.b x2, x2, x2 + cv.cmpleu.b x8, x8, x8 + cv.cmpleu.b x20, x20, x20 + cv.cmpleu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7dcae701bfece1ccf6a8fddb2f61f3994a15d460 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-h-fail.s +#error_output: cv-cmpleu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1bcab7179eb037f43003bcf8fe8d01074380f558 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..2de8808711a584ef34bf4e0c1414e92a2bccf2b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.h x32, x32, x32 + cv.cmpleu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..7cc9870f94141398c34da056ce135d2a3072d1c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00007b cv.cmpleu.h zero,zero,zero + 4: 4c1080fb cv.cmpleu.h ra,ra,ra + 8: 4c21017b cv.cmpleu.h sp,sp,sp + c: 4c84047b cv.cmpleu.h s0,s0,s0 + 10: 4d4a0a7b cv.cmpleu.h s4,s4,s4 + 14: 4dff8ffb cv.cmpleu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..3b2ac7beaed699100d20fd47d91ec89b1e653d75 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.h x0, x0, x0 + cv.cmpleu.h x1, x1, x1 + cv.cmpleu.h x2, x2, x2 + cv.cmpleu.h x8, x8, x8 + cv.cmpleu.h x20, x20, x20 + cv.cmpleu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..cbf416a16927f23d6a7f7ce656c225eefba65200 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-b-fail.s +#error_output: cv-cmpleu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..5fde1fae238c6a8f15b945dfd0ad7b84e2b0ad9c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5cd69fd76a4bd9b3ac3a856a67de97e21812a6b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.sc.b x32, x32, x32 + cv.cmpleu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e03b38d3659c17cb845a2451fc5f5c96cfbea499 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00507b cv.cmpleu.sc.b zero,zero,zero + 4: 4c10d0fb cv.cmpleu.sc.b ra,ra,ra + 8: 4c21517b cv.cmpleu.sc.b sp,sp,sp + c: 4c84547b cv.cmpleu.sc.b s0,s0,s0 + 10: 4d4a5a7b cv.cmpleu.sc.b s4,s4,s4 + 14: 4dffdffb cv.cmpleu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5a99d7b127c15512fd0fbff8a7a1e91857829523 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.sc.b x0, x0, x0 + cv.cmpleu.sc.b x1, x1, x1 + cv.cmpleu.sc.b x2, x2, x2 + cv.cmpleu.sc.b x8, x8, x8 + cv.cmpleu.sc.b x20, x20, x20 + cv.cmpleu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..71f51670151e5b6b85851230ed355ec243d35f30 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-h-fail.s +#error_output: cv-cmpleu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..11438240a92599e7f95b50ac836202fd7ac5d7e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpleu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..632933d7e6313ecab603762b7b512b20b5b70a31 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpleu.sc.h x32, x32, x32 + cv.cmpleu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..96789b9cc855d7756bed2c326084c23edca42696 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4c00407b cv.cmpleu.sc.h zero,zero,zero + 4: 4c10c0fb cv.cmpleu.sc.h ra,ra,ra + 8: 4c21417b cv.cmpleu.sc.h sp,sp,sp + c: 4c84447b cv.cmpleu.sc.h s0,s0,s0 + 10: 4d4a4a7b cv.cmpleu.sc.h s4,s4,s4 + 14: 4dffcffb cv.cmpleu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..762af31e6e2ae1144043e46f19e78bb976560aa4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpleu.sc.h x0, x0, x0 + cv.cmpleu.sc.h x1, x1, x1 + cv.cmpleu.sc.h x2, x2, x2 + cv.cmpleu.sc.h x8, x8, x8 + cv.cmpleu.sc.h x20, x20, x20 + cv.cmpleu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..aa9257190e0176da0b9d57fc53e94b7cfc873505 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-b-fail.s +#error_output: cv-cmpleu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..e12d078738b1c2f03f2adb87935c3188864706da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpleu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..f8ad26f86b0f9f71f11aa4fcdc966ee529d22aa5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpleu.sci.b x32, x32, 20 + cv.cmpleu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpleu.sci.b x6, x7, -33 + cv.cmpleu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..13b3cc3323614efd9d4ec59a582eb2812d40e37f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4d40707b cv.cmpleu.sci.b zero,zero,20 + 4: 4d40f0fb cv.cmpleu.sci.b ra,ra,20 + 8: 4d41717b cv.cmpleu.sci.b sp,sp,20 + c: 4d44747b cv.cmpleu.sci.b s0,s0,20 + 10: 4d4a7a7b cv.cmpleu.sci.b s4,s4,20 + 14: 4d4ffffb cv.cmpleu.sci.b t6,t6,20 + 18: 4e03f37b cv.cmpleu.sci.b t1,t2,-32 + 1c: 4c03f37b cv.cmpleu.sci.b t1,t2,0 + 20: 4df3f37b cv.cmpleu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..11ed9420585806299487ee81e16fd436f1ff7d41 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpleu.sci.b x0, x0, 20 + cv.cmpleu.sci.b x1, x1, 20 + cv.cmpleu.sci.b x2, x2, 20 + cv.cmpleu.sci.b x8, x8, 20 + cv.cmpleu.sci.b x20, x20, 20 + cv.cmpleu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpleu.sci.b x6, x7, -32 + cv.cmpleu.sci.b x6, x7, 0 + cv.cmpleu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..13b2dd5e2d8d9a6f46222fa6a89a31c0e8575fb2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-h-fail.s +#error_output: cv-cmpleu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a7057dff130d65092b294316ef9b8a682c3783ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpleu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpleu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..fa1467910fbc9b299eabd74cbdbf0039b7ad8c03 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpleu.sci.h x32, x32, 20 + cv.cmpleu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpleu.sci.h x6, x7, -33 + cv.cmpleu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b8f0bb62b1b480813175c8ff34a274922dde1a31 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpleu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4d40607b cv.cmpleu.sci.h zero,zero,20 + 4: 4d40e0fb cv.cmpleu.sci.h ra,ra,20 + 8: 4d41617b cv.cmpleu.sci.h sp,sp,20 + c: 4d44647b cv.cmpleu.sci.h s0,s0,20 + 10: 4d4a6a7b cv.cmpleu.sci.h s4,s4,20 + 14: 4d4feffb cv.cmpleu.sci.h t6,t6,20 + 18: 4e03e37b cv.cmpleu.sci.h t1,t2,-32 + 1c: 4c03e37b cv.cmpleu.sci.h t1,t2,0 + 20: 4df3e37b cv.cmpleu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..cc278ce2ccdd0399ae1f3e81ab0db1d9382e20e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpleu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpleu.sci.h x0, x0, 20 + cv.cmpleu.sci.h x1, x1, 20 + cv.cmpleu.sci.h x2, x2, 20 + cv.cmpleu.sci.h x8, x8, 20 + cv.cmpleu.sci.h x20, x20, 20 + cv.cmpleu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpleu.sci.h x6, x7, -32 + cv.cmpleu.sci.h x6, x7, 0 + cv.cmpleu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..fdfaa8180194dd7410d91885b11186e73688ebb0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-b-fail.s +#error_output: cv-cmplt-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0f98b08b92e8fe0e90efe99bdf0df6feed7549ef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.b x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a9d537f3a0e63b3f24cc66f2b2540ce611627b92 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.b x32, x32, x32 + cv.cmplt.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..685a3494f5a7a6b216d1d34aa9b40b5cfb7908cb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400107b cv.cmplt.b zero,zero,zero + 4: 241090fb cv.cmplt.b ra,ra,ra + 8: 2421117b cv.cmplt.b sp,sp,sp + c: 2484147b cv.cmplt.b s0,s0,s0 + 10: 254a1a7b cv.cmplt.b s4,s4,s4 + 14: 25ff9ffb cv.cmplt.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-b-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..9f45e2e18c0ae7dca2dc00ac8d0f756d180dd0ad --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.b x0, x0, x0 + cv.cmplt.b x1, x1, x1 + cv.cmplt.b x2, x2, x2 + cv.cmplt.b x8, x8, x8 + cv.cmplt.b x20, x20, x20 + cv.cmplt.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..83fb4c1cdc22e632ebe47603b6369640aaf15efe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-h-fail.s +#error_output: cv-cmplt-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b2c5298e1e3890d177354080afaea5da2013236e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.h x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0726a8edb5d8ac8476dc9cf8e3c98bce531de74f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.h x32, x32, x32 + cv.cmplt.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d67387b0c213819bb59d2e86c18137449437685d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400007b cv.cmplt.h zero,zero,zero + 4: 241080fb cv.cmplt.h ra,ra,ra + 8: 2421017b cv.cmplt.h sp,sp,sp + c: 2484047b cv.cmplt.h s0,s0,s0 + 10: 254a0a7b cv.cmplt.h s4,s4,s4 + 14: 25ff8ffb cv.cmplt.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-h-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1c7cdac3adacf5278a1481461cccac095b8480f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.h x0, x0, x0 + cv.cmplt.h x1, x1, x1 + cv.cmplt.h x2, x2, x2 + cv.cmplt.h x8, x8, x8 + cv.cmplt.h x20, x20, x20 + cv.cmplt.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..68a3ffcec338885808f6b95b6d3086171c9266b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-b-fail.s +#error_output: cv-cmplt-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..bc8340f218b506c3c9c9037a4337d470b04bc99e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..625d424590c9ef7560be3b8e90c0a7f702cbaffb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.sc.b x32, x32, x32 + cv.cmplt.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..52b065592f8bb2b2234776f6119a26ccab1f5266 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400507b cv.cmplt.sc.b zero,zero,zero + 4: 2410d0fb cv.cmplt.sc.b ra,ra,ra + 8: 2421517b cv.cmplt.sc.b sp,sp,sp + c: 2484547b cv.cmplt.sc.b s0,s0,s0 + 10: 254a5a7b cv.cmplt.sc.b s4,s4,s4 + 14: 25ffdffb cv.cmplt.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f1220c4781c8d31da48b655b17136a3043f0ef78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.sc.b x0, x0, x0 + cv.cmplt.sc.b x1, x1, x1 + cv.cmplt.sc.b x2, x2, x2 + cv.cmplt.sc.b x8, x8, x8 + cv.cmplt.sc.b x20, x20, x20 + cv.cmplt.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..0e3b134000860df88ea9138c9ecee1f35a16589a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-h-fail.s +#error_output: cv-cmplt-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9d7c9e054799f70bba420c5ede35bfb37b536af4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmplt.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..ae4a89cbb5e238e9082084a3924d8de837c4a8b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmplt.sc.h x32, x32, x32 + cv.cmplt.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..1883893c0db9718cd3bee80c3eb218d0618b12b0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2400407b cv.cmplt.sc.h zero,zero,zero + 4: 2410c0fb cv.cmplt.sc.h ra,ra,ra + 8: 2421417b cv.cmplt.sc.h sp,sp,sp + c: 2484447b cv.cmplt.sc.h s0,s0,s0 + 10: 254a4a7b cv.cmplt.sc.h s4,s4,s4 + 14: 25ffcffb cv.cmplt.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..2955c8393afc8fc3fd5378d6fb0bcde872207e11 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmplt.sc.h x0, x0, x0 + cv.cmplt.sc.h x1, x1, x1 + cv.cmplt.sc.h x2, x2, x2 + cv.cmplt.sc.h x8, x8, x8 + cv.cmplt.sc.h x20, x20, x20 + cv.cmplt.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..2f4607e4c1c6f5ace86f3095a8cad19390ee7ded --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-b-fail.s +#error_output: cv-cmplt-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..2d5cdad6b800c285eca11206778fb03e4294bec3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmplt.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..95ffaa84598ce72f54aa5fcf123bad8b71be69d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmplt.sci.b x32, x32, 20 + cv.cmplt.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmplt.sci.b x6, x7, -33 + cv.cmplt.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..673b7780646e768595844ef76fc39bb83e9e260b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2540707b cv.cmplt.sci.b zero,zero,20 + 4: 2540f0fb cv.cmplt.sci.b ra,ra,20 + 8: 2541717b cv.cmplt.sci.b sp,sp,20 + c: 2544747b cv.cmplt.sci.b s0,s0,20 + 10: 254a7a7b cv.cmplt.sci.b s4,s4,20 + 14: 254ffffb cv.cmplt.sci.b t6,t6,20 + 18: 2603f37b cv.cmplt.sci.b t1,t2,-32 + 1c: 2403f37b cv.cmplt.sci.b t1,t2,0 + 20: 25f3f37b cv.cmplt.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f6037aca241b0e3184f599402038d86da7ffc6be --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmplt.sci.b x0, x0, 20 + cv.cmplt.sci.b x1, x1, 20 + cv.cmplt.sci.b x2, x2, 20 + cv.cmplt.sci.b x8, x8, 20 + cv.cmplt.sci.b x20, x20, 20 + cv.cmplt.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmplt.sci.b x6, x7, -32 + cv.cmplt.sci.b x6, x7, 0 + cv.cmplt.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8ee7a0d9f979aa90fd1d26a6d99a976678e9c209 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-h-fail.s +#error_output: cv-cmplt-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..6be7bcaf461c55de84de8cef7156c021b792fdab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmplt.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmplt.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..8094f165b019ffb95c45599eae65e321f33e388b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmplt.sci.h x32, x32, 20 + cv.cmplt.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmplt.sci.h x6, x7, -33 + cv.cmplt.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..63c9702c8e7bbbd9ae5cd0038a1eeaa04d192f05 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmplt-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2540607b cv.cmplt.sci.h zero,zero,20 + 4: 2540e0fb cv.cmplt.sci.h ra,ra,20 + 8: 2541617b cv.cmplt.sci.h sp,sp,20 + c: 2544647b cv.cmplt.sci.h s0,s0,20 + 10: 254a6a7b cv.cmplt.sci.h s4,s4,20 + 14: 254feffb cv.cmplt.sci.h t6,t6,20 + 18: 2603e37b cv.cmplt.sci.h t1,t2,-32 + 1c: 2403e37b cv.cmplt.sci.h t1,t2,0 + 20: 25f3e37b cv.cmplt.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..0b83b1ba472e985f31971e848455d78bb28262fb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmplt-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmplt.sci.h x0, x0, 20 + cv.cmplt.sci.h x1, x1, 20 + cv.cmplt.sci.h x2, x2, 20 + cv.cmplt.sci.h x8, x8, 20 + cv.cmplt.sci.h x20, x20, 20 + cv.cmplt.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmplt.sci.h x6, x7, -32 + cv.cmplt.sci.h x6, x7, 0 + cv.cmplt.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..673b52e1ae9a8ef7a2e03dd54c95e3cd3d9cd6aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-b-fail.s +#error_output: cv-cmpltu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..199b24d2c5ee19a111c9558b5a2df88ad22fadc6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5e1a3a8ea127b77f7417874a358d5ea0edb10680 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.b x32, x32, x32 + cv.cmpltu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e21cea508aad9df031a0dfe3c7ce784b39c7af2d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400107b cv.cmpltu.b zero,zero,zero + 4: 441090fb cv.cmpltu.b ra,ra,ra + 8: 4421117b cv.cmpltu.b sp,sp,sp + c: 4484147b cv.cmpltu.b s0,s0,s0 + 10: 454a1a7b cv.cmpltu.b s4,s4,s4 + 14: 45ff9ffb cv.cmpltu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..0b0ee26947c297dc75cd748a96000b76476ffa91 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.b x0, x0, x0 + cv.cmpltu.b x1, x1, x1 + cv.cmpltu.b x2, x2, x2 + cv.cmpltu.b x8, x8, x8 + cv.cmpltu.b x20, x20, x20 + cv.cmpltu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..078b893ccac1d76fab8b66e921c30f4774ee59ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-h-fail.s +#error_output: cv-cmpltu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7ec17d16181fe7bda6337f9ccf2652a24948cb8b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9aa13b92603365dec0f5980f0693d18b02ef076a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.h x32, x32, x32 + cv.cmpltu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..28fe225830c51ee8db74eab1a8ca55e8adf66535 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400007b cv.cmpltu.h zero,zero,zero + 4: 441080fb cv.cmpltu.h ra,ra,ra + 8: 4421017b cv.cmpltu.h sp,sp,sp + c: 4484047b cv.cmpltu.h s0,s0,s0 + 10: 454a0a7b cv.cmpltu.h s4,s4,s4 + 14: 45ff8ffb cv.cmpltu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c39a583ba732fa3c64ff9ac096bfc652166d158f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.h x0, x0, x0 + cv.cmpltu.h x1, x1, x1 + cv.cmpltu.h x2, x2, x2 + cv.cmpltu.h x8, x8, x8 + cv.cmpltu.h x20, x20, x20 + cv.cmpltu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..03c2f74548fe309a94d7e5c79fd99d9793e570fa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-b-fail.s +#error_output: cv-cmpltu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0b4c9992e7f41a056fdb54a33ec2c073f7117a44 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..15ec07644d91b39b44859c069152285a9673e9eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.sc.b x32, x32, x32 + cv.cmpltu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..25a96d77a0b5f5d3d964ccf25a005a2b808dd384 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400507b cv.cmpltu.sc.b zero,zero,zero + 4: 4410d0fb cv.cmpltu.sc.b ra,ra,ra + 8: 4421517b cv.cmpltu.sc.b sp,sp,sp + c: 4484547b cv.cmpltu.sc.b s0,s0,s0 + 10: 454a5a7b cv.cmpltu.sc.b s4,s4,s4 + 14: 45ffdffb cv.cmpltu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..65383b469ba85e6f530ab9d58d8c01e623dd34dc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.sc.b x0, x0, x0 + cv.cmpltu.sc.b x1, x1, x1 + cv.cmpltu.sc.b x2, x2, x2 + cv.cmpltu.sc.b x8, x8, x8 + cv.cmpltu.sc.b x20, x20, x20 + cv.cmpltu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d15370610ca192a5e5f4a8482449706d6735ac0b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-h-fail.s +#error_output: cv-cmpltu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..aa73e2dd5e16dab21fb7da76058ca146966d517d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpltu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0cd45cc2ca55f31fc341aa10a764421866b45ee5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpltu.sc.h x32, x32, x32 + cv.cmpltu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ee438e61d18687adeef5594b7ad88bbd55d410d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4400407b cv.cmpltu.sc.h zero,zero,zero + 4: 4410c0fb cv.cmpltu.sc.h ra,ra,ra + 8: 4421417b cv.cmpltu.sc.h sp,sp,sp + c: 4484447b cv.cmpltu.sc.h s0,s0,s0 + 10: 454a4a7b cv.cmpltu.sc.h s4,s4,s4 + 14: 45ffcffb cv.cmpltu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..6dc3ad7e8473e584918d7ccb3a93cfb989ed1b26 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpltu.sc.h x0, x0, x0 + cv.cmpltu.sc.h x1, x1, x1 + cv.cmpltu.sc.h x2, x2, x2 + cv.cmpltu.sc.h x8, x8, x8 + cv.cmpltu.sc.h x20, x20, x20 + cv.cmpltu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..69de4b22b3d56f7fd3f485563654b3e2ee17303a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-b-fail.s +#error_output: cv-cmpltu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..dd6781ceebd73f56baecb819522aadabdff52b63 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpltu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..d59d4d20c964a2f1479a2ec145d3756b2cba4f78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpltu.sci.b x32, x32, 20 + cv.cmpltu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpltu.sci.b x6, x7, -33 + cv.cmpltu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..4af6a14e6d2bac02b28e7732018530ed3e68a69a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4540707b cv.cmpltu.sci.b zero,zero,20 + 4: 4540f0fb cv.cmpltu.sci.b ra,ra,20 + 8: 4541717b cv.cmpltu.sci.b sp,sp,20 + c: 4544747b cv.cmpltu.sci.b s0,s0,20 + 10: 454a7a7b cv.cmpltu.sci.b s4,s4,20 + 14: 454ffffb cv.cmpltu.sci.b t6,t6,20 + 18: 4603f37b cv.cmpltu.sci.b t1,t2,-32 + 1c: 4403f37b cv.cmpltu.sci.b t1,t2,0 + 20: 45f3f37b cv.cmpltu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..cdcb11f4a1e856538effb1287568b18c9cb0997c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpltu.sci.b x0, x0, 20 + cv.cmpltu.sci.b x1, x1, 20 + cv.cmpltu.sci.b x2, x2, 20 + cv.cmpltu.sci.b x8, x8, 20 + cv.cmpltu.sci.b x20, x20, 20 + cv.cmpltu.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpltu.sci.b x6, x7, -32 + cv.cmpltu.sci.b x6, x7, 0 + cv.cmpltu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d16856b05102ce49797d96410558486bbaa12b0c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-h-fail.s +#error_output: cv-cmpltu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c3d7101fa1bfb305182d2d6354fdb1ce13fbbb8a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpltu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpltu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c6e8560b07335dd6e08d9b053a42e020b7593da1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpltu.sci.h x32, x32, 20 + cv.cmpltu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpltu.sci.h x6, x7, -33 + cv.cmpltu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..6fd35a350c4cf6866fb13e13892feac09b7eccc3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpltu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4540607b cv.cmpltu.sci.h zero,zero,20 + 4: 4540e0fb cv.cmpltu.sci.h ra,ra,20 + 8: 4541617b cv.cmpltu.sci.h sp,sp,20 + c: 4544647b cv.cmpltu.sci.h s0,s0,20 + 10: 454a6a7b cv.cmpltu.sci.h s4,s4,20 + 14: 454feffb cv.cmpltu.sci.h t6,t6,20 + 18: 4603e37b cv.cmpltu.sci.h t1,t2,-32 + 1c: 4403e37b cv.cmpltu.sci.h t1,t2,0 + 20: 45f3e37b cv.cmpltu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..12fea0cca2b68e0209fedf061021fca52de510f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpltu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpltu.sci.h x0, x0, 20 + cv.cmpltu.sci.h x1, x1, 20 + cv.cmpltu.sci.h x2, x2, 20 + cv.cmpltu.sci.h x8, x8, 20 + cv.cmpltu.sci.h x20, x20, 20 + cv.cmpltu.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpltu.sci.h x6, x7, -32 + cv.cmpltu.sci.h x6, x7, 0 + cv.cmpltu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..fd829686b6d6c866526092b9c3974bc70d770cac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-b-fail.s +#error_output: cv-cmpne-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..17dd8aad0d5566327bde86d76fed32e051d015d0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..233113481ac91437eebe9f677f970a733a18f214 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.b x32, x32, x32 + cv.cmpne.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..932a3c6d4437100537672ca0b1bb6470b7d443d5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00107b cv.cmpne.b zero,zero,zero + 4: 0c1090fb cv.cmpne.b ra,ra,ra + 8: 0c21117b cv.cmpne.b sp,sp,sp + c: 0c84147b cv.cmpne.b s0,s0,s0 + 10: 0d4a1a7b cv.cmpne.b s4,s4,s4 + 14: 0dff9ffb cv.cmpne.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1aa74bbcaa34cf1651b8d75162a859bafd85f4f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.b x0, x0, x0 + cv.cmpne.b x1, x1, x1 + cv.cmpne.b x2, x2, x2 + cv.cmpne.b x8, x8, x8 + cv.cmpne.b x20, x20, x20 + cv.cmpne.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..6a1411dc3188d980a617bc5b0d2a83263e9759f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-h-fail.s +#error_output: cv-cmpne-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0b53e8f593c9a70d96b611baac1138e2f69e87d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e071346366899ee4f45c741d640b9942ee4e9001 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.h x32, x32, x32 + cv.cmpne.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..93f92d44086132cefd2bf2401490c2cfc5764583 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00007b cv.cmpne.h zero,zero,zero + 4: 0c1080fb cv.cmpne.h ra,ra,ra + 8: 0c21017b cv.cmpne.h sp,sp,sp + c: 0c84047b cv.cmpne.h s0,s0,s0 + 10: 0d4a0a7b cv.cmpne.h s4,s4,s4 + 14: 0dff8ffb cv.cmpne.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..19fbad0f6c1cf5af5f6526319ace6423adbc88ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.h x0, x0, x0 + cv.cmpne.h x1, x1, x1 + cv.cmpne.h x2, x2, x2 + cv.cmpne.h x8, x8, x8 + cv.cmpne.h x20, x20, x20 + cv.cmpne.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..656a7639808a364e010f19acdf2a452218334157 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-b-fail.s +#error_output: cv-cmpne-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..24afd89655890db7138c50061f53f7cb2261c618 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..90d11e545a74bbd4c80c2a10fee11720ea7855b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.sc.b x32, x32, x32 + cv.cmpne.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..792f8021242b73e172b99b8a132e638a1f216f61 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00507b cv.cmpne.sc.b zero,zero,zero + 4: 0c10d0fb cv.cmpne.sc.b ra,ra,ra + 8: 0c21517b cv.cmpne.sc.b sp,sp,sp + c: 0c84547b cv.cmpne.sc.b s0,s0,s0 + 10: 0d4a5a7b cv.cmpne.sc.b s4,s4,s4 + 14: 0dffdffb cv.cmpne.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..576e327fbc1835cf53f4b11916ce671a1b9964a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.sc.b x0, x0, x0 + cv.cmpne.sc.b x1, x1, x1 + cv.cmpne.sc.b x2, x2, x2 + cv.cmpne.sc.b x8, x8, x8 + cv.cmpne.sc.b x20, x20, x20 + cv.cmpne.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..af3bfdb5ed7a709d8dfe2785f149a11c4db1fbe6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-h-fail.s +#error_output: cv-cmpne-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..34854ac8eeecc6e24275b6ef4ca6bf8685a1a2e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.cmpne.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..3a14c6acb87b2eac904a0e5129d2a1495984ed09 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cmpne.sc.h x32, x32, x32 + cv.cmpne.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..83e59b71401134eb5417af7bc24c64b833ade7f4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0c00407b cv.cmpne.sc.h zero,zero,zero + 4: 0c10c0fb cv.cmpne.sc.h ra,ra,ra + 8: 0c21417b cv.cmpne.sc.h sp,sp,sp + c: 0c84447b cv.cmpne.sc.h s0,s0,s0 + 10: 0d4a4a7b cv.cmpne.sc.h s4,s4,s4 + 14: 0dffcffb cv.cmpne.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..25f87fe96266ed5e6203c1b0c2f22abd0585d663 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cmpne.sc.h x0, x0, x0 + cv.cmpne.sc.h x1, x1, x1 + cv.cmpne.sc.h x2, x2, x2 + cv.cmpne.sc.h x8, x8, x8 + cv.cmpne.sc.h x20, x20, x20 + cv.cmpne.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..cbc805d353b67086edd3bc1aea0fea3e3a96c26e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-b-fail.s +#error_output: cv-cmpne-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9ad1b198f54f6eda7755c4e966eb7ebf9d6df710 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sci.b x32,x32,20' +.*: Error: illegal operands `cv.cmpne.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a1b8fe168e8fb26728962e1dcfe670ce92a46381 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpne.sci.b x32, x32, 20 + cv.cmpne.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpne.sci.b x6, x7, -33 + cv.cmpne.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..1a8b40367dd87d701327d52c7f460c9c2d62f849 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0d40707b cv.cmpne.sci.b zero,zero,20 + 4: 0d40f0fb cv.cmpne.sci.b ra,ra,20 + 8: 0d41717b cv.cmpne.sci.b sp,sp,20 + c: 0d44747b cv.cmpne.sci.b s0,s0,20 + 10: 0d4a7a7b cv.cmpne.sci.b s4,s4,20 + 14: 0d4ffffb cv.cmpne.sci.b t6,t6,20 + 18: 0e03f37b cv.cmpne.sci.b t1,t2,-32 + 1c: 0c03f37b cv.cmpne.sci.b t1,t2,0 + 20: 0df3f37b cv.cmpne.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..301a3a024dc4e9a9b36b77d341a7e716a40c5172 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpne.sci.b x0, x0, 20 + cv.cmpne.sci.b x1, x1, 20 + cv.cmpne.sci.b x2, x2, 20 + cv.cmpne.sci.b x8, x8, 20 + cv.cmpne.sci.b x20, x20, 20 + cv.cmpne.sci.b x31, x31, 20 + #Immediate Values Test + cv.cmpne.sci.b x6, x7, -32 + cv.cmpne.sci.b x6, x7, 0 + cv.cmpne.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..95e0bb94b439de28bd839e6b157838827eacc97c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-h-fail.s +#error_output: cv-cmpne-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..eba861843c8a16b607b65b29660e78ce197e8c69 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cmpne.sci.h x32,x32,20' +.*: Error: illegal operands `cv.cmpne.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..6a1f2f7dd6fa84a620ded72222cd480ac8fe04e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.cmpne.sci.h x32, x32, 20 + cv.cmpne.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.cmpne.sci.h x6, x7, -33 + cv.cmpne.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f5ed539ffa59388cb385a0147d08896bbd8553f2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cmpne-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0d40607b cv.cmpne.sci.h zero,zero,20 + 4: 0d40e0fb cv.cmpne.sci.h ra,ra,20 + 8: 0d41617b cv.cmpne.sci.h sp,sp,20 + c: 0d44647b cv.cmpne.sci.h s0,s0,20 + 10: 0d4a6a7b cv.cmpne.sci.h s4,s4,20 + 14: 0d4feffb cv.cmpne.sci.h t6,t6,20 + 18: 0e03e37b cv.cmpne.sci.h t1,t2,-32 + 1c: 0c03e37b cv.cmpne.sci.h t1,t2,0 + 20: 0df3e37b cv.cmpne.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..984ded1e0903170268fd21d585f0b6c8c33d0cef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cmpne-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.cmpne.sci.h x0, x0, 20 + cv.cmpne.sci.h x1, x1, 20 + cv.cmpne.sci.h x2, x2, 20 + cv.cmpne.sci.h x8, x8, 20 + cv.cmpne.sci.h x20, x20, 20 + cv.cmpne.sci.h x31, x31, 20 + #Immediate Values Test + cv.cmpne.sci.h x6, x7, -32 + cv.cmpne.sci.h x6, x7, 0 + cv.cmpne.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-fail.d b/gas/testsuite/gas/riscv/cv-cplxconj-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..89d8b031d1eeca23bf6b4916c9e228fdc77c25cb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxconj-fail.s +#error_output: cv-cplxconj-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-fail.l b/gas/testsuite/gas/riscv/cv-cplxconj-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ed0844fae23382ec5b3e8282c9785332218420ec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxconj x32,x32' +.*: Error: illegal operands `cv.cplxconj x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-fail.s b/gas/testsuite/gas/riscv/cv-cplxconj-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..04e3716485bba81177714dffcb9a14c7ef5f96b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxconj x32, x32 + cv.cplxconj x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-pass.d b/gas/testsuite/gas/riscv/cv-cplxconj-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..591bccf5fa05a049e7a527cc8c50a1559efd1bdd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxconj-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5c00007b cv.cplxconj zero,zero + 4: 5c0080fb cv.cplxconj ra,ra + 8: 5c01017b cv.cplxconj sp,sp + c: 5c04047b cv.cplxconj s0,s0 + 10: 5c0a0a7b cv.cplxconj s4,s4 + 14: 5c0f8ffb cv.cplxconj t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxconj-pass.s b/gas/testsuite/gas/riscv/cv-cplxconj-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..36b163b8d08f46e4b89ea298f9d16f48e748a640 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxconj-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxconj x0, x0 + cv.cplxconj x1, x1 + cv.cplxconj x2, x2 + cv.cplxconj x8, x8 + cv.cplxconj x20, x20 + cv.cplxconj x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..9264b535cb77e5fcee98dcf1f2cb8bfa5c5bafb1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div2-fail.s +#error_output: cv-cplxmul-i-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9af5157824dee564ed90bd3d4c1c7a6d13920e44 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i.div2 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..d6fa16ff4f1a65122718a2b5f028a9a9e935fd9e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i.div2 x32, x32, x32 + cv.cplxmul.i.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..954d13ab76d23db4a66c155bb1ca99c71a0bf457 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600207b cv.cplxmul.i.div2 zero,zero,zero + 4: 5610a0fb cv.cplxmul.i.div2 ra,ra,ra + 8: 5621217b cv.cplxmul.i.div2 sp,sp,sp + c: 5684247b cv.cplxmul.i.div2 s0,s0,s0 + 10: 574a2a7b cv.cplxmul.i.div2 s4,s4,s4 + 14: 57ffaffb cv.cplxmul.i.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4eb89da921c4ae8295cae1655d3aa554c6b62a25 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i.div2 x0, x0, x0 + cv.cplxmul.i.div2 x1, x1, x1 + cv.cplxmul.i.div2 x2, x2, x2 + cv.cplxmul.i.div2 x8, x8, x8 + cv.cplxmul.i.div2 x20, x20, x20 + cv.cplxmul.i.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..afe960bd6319006e529b877b17fcf227f6bf7411 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div4-fail.s +#error_output: cv-cplxmul-i-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c3efbe053ebc18002490a68490bd719959c352db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i.div4 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e5ea2fc45fd12928df276a8574b7f75ad2d4c8e6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i.div4 x32, x32, x32 + cv.cplxmul.i.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..74ab02dd3ef8b62f0a9aaf2aa695e530f9fc5d1b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600407b cv.cplxmul.i.div4 zero,zero,zero + 4: 5610c0fb cv.cplxmul.i.div4 ra,ra,ra + 8: 5621417b cv.cplxmul.i.div4 sp,sp,sp + c: 5684447b cv.cplxmul.i.div4 s0,s0,s0 + 10: 574a4a7b cv.cplxmul.i.div4 s4,s4,s4 + 14: 57ffcffb cv.cplxmul.i.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5d96c06e72d47f17fefa93ceac20da33836c5342 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i.div4 x0, x0, x0 + cv.cplxmul.i.div4 x1, x1, x1 + cv.cplxmul.i.div4 x2, x2, x2 + cv.cplxmul.i.div4 x8, x8, x8 + cv.cplxmul.i.div4 x20, x20, x20 + cv.cplxmul.i.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..99fabfe2cd9a1c35ed971647aec6ecefdb15c388 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div8-fail.s +#error_output: cv-cplxmul-i-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..cc52645bf80bc3d1206d0d91f045730596f017eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i.div8 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..bcd458cd249d37c878699cf6838156c4ad200e0b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i.div8 x32, x32, x32 + cv.cplxmul.i.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..25c4602a15add338675e27187d52c270d7d83035 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600607b cv.cplxmul.i.div8 zero,zero,zero + 4: 5610e0fb cv.cplxmul.i.div8 ra,ra,ra + 8: 5621617b cv.cplxmul.i.div8 sp,sp,sp + c: 5684647b cv.cplxmul.i.div8 s0,s0,s0 + 10: 574a6a7b cv.cplxmul.i.div8 s4,s4,s4 + 14: 57ffeffb cv.cplxmul.i.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f01268fb5c0576b8f6936a709661bfb1733ecae1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i.div8 x0, x0, x0 + cv.cplxmul.i.div8 x1, x1, x1 + cv.cplxmul.i.div8 x2, x2, x2 + cv.cplxmul.i.div8 x8, x8, x8 + cv.cplxmul.i.div8 x20, x20, x20 + cv.cplxmul.i.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..54a12007ee909d5e1973f5d7412fb1fd01257d08 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-fail.s +#error_output: cv-cplxmul-i-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..4d63c3d02b5315b4d2d3379467686f3354a6dd75 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.i x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.i x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..3b1cd653850d99b98123e154f1c5153b8cb349d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.i x32, x32, x32 + cv.cplxmul.i x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..72a0b08c1e0a3bd80c95af3a518a05c3152296e5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-i-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5600007b cv.cplxmul.i zero,zero,zero + 4: 561080fb cv.cplxmul.i ra,ra,ra + 8: 5621017b cv.cplxmul.i sp,sp,sp + c: 5684047b cv.cplxmul.i s0,s0,s0 + 10: 574a0a7b cv.cplxmul.i s4,s4,s4 + 14: 57ff8ffb cv.cplxmul.i t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1384fa157b1707302c5bd45549029edbc9d92815 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-i-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.i x0, x0, x0 + cv.cplxmul.i x1, x1, x1 + cv.cplxmul.i x2, x2, x2 + cv.cplxmul.i x8, x8, x8 + cv.cplxmul.i x20, x20, x20 + cv.cplxmul.i x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..244ec9ee3169aa95de235653a1e3ed59ecbad3af --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div2-fail.s +#error_output: cv-cplxmul-r-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0f6c70cbaa197a782ba22be841241ea123ed292a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r.div2 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a88cc6b3c73bcaa248378b348cec3fec348cb17a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r.div2 x32, x32, x32 + cv.cplxmul.r.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..0931e184b30aec3e1cdff07a63f89f0b0e60fcbb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400207b cv.cplxmul.r.div2 zero,zero,zero + 4: 5410a0fb cv.cplxmul.r.div2 ra,ra,ra + 8: 5421217b cv.cplxmul.r.div2 sp,sp,sp + c: 5484247b cv.cplxmul.r.div2 s0,s0,s0 + 10: 554a2a7b cv.cplxmul.r.div2 s4,s4,s4 + 14: 55ffaffb cv.cplxmul.r.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..48d694098cc7a0dc8db14d062afed0bb7ea9837f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r.div2 x0, x0, x0 + cv.cplxmul.r.div2 x1, x1, x1 + cv.cplxmul.r.div2 x2, x2, x2 + cv.cplxmul.r.div2 x8, x8, x8 + cv.cplxmul.r.div2 x20, x20, x20 + cv.cplxmul.r.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..10f67de862ab38b33af93648600c3a238b66e116 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div4-fail.s +#error_output: cv-cplxmul-r-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..3fa875f7a3c8bbc1c0737b9fb9d267a4f7ce3c4b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r.div4 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..1af6d1192abd30d59cd9e16c8abaeac7f9a7f8a1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r.div4 x32, x32, x32 + cv.cplxmul.r.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b1158ee98a322c32ef8de12744e551fa4391f4e0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400407b cv.cplxmul.r.div4 zero,zero,zero + 4: 5410c0fb cv.cplxmul.r.div4 ra,ra,ra + 8: 5421417b cv.cplxmul.r.div4 sp,sp,sp + c: 5484447b cv.cplxmul.r.div4 s0,s0,s0 + 10: 554a4a7b cv.cplxmul.r.div4 s4,s4,s4 + 14: 55ffcffb cv.cplxmul.r.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5729b88b45d4030b5edcf169c883b9994292527d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r.div4 x0, x0, x0 + cv.cplxmul.r.div4 x1, x1, x1 + cv.cplxmul.r.div4 x2, x2, x2 + cv.cplxmul.r.div4 x8, x8, x8 + cv.cplxmul.r.div4 x20, x20, x20 + cv.cplxmul.r.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a281659185fc2d41f468d4dfca9ed9778a897487 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div8-fail.s +#error_output: cv-cplxmul-r-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ba8c9752dad7eafed977b712e342cf4b8c5b29ec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r.div8 x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..47cdfbe15da277c09ffc54a2153b1a160c20464a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r.div8 x32, x32, x32 + cv.cplxmul.r.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..7bb6e03fcff8ebbaa10e6bc074598feb1b238dbd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400607b cv.cplxmul.r.div8 zero,zero,zero + 4: 5410e0fb cv.cplxmul.r.div8 ra,ra,ra + 8: 5421617b cv.cplxmul.r.div8 sp,sp,sp + c: 5484647b cv.cplxmul.r.div8 s0,s0,s0 + 10: 554a6a7b cv.cplxmul.r.div8 s4,s4,s4 + 14: 55ffeffb cv.cplxmul.r.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..9c29967f4af2394a5db14f4f25bc8196037a44e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r.div8 x0, x0, x0 + cv.cplxmul.r.div8 x1, x1, x1 + cv.cplxmul.r.div8 x2, x2, x2 + cv.cplxmul.r.div8 x8, x8, x8 + cv.cplxmul.r.div8 x20, x20, x20 + cv.cplxmul.r.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..9adb2b61d4d369b5f684021d0fffe281b180452a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-fail.s +#error_output: cv-cplxmul-r-fail.l diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..f3f3a9cc5429484081004023814c3c79c396917c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.cplxmul.r x32,x32,x32' +.*: Error: illegal operands `cv.cplxmul.r x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..64b3b0d158bf7ea3d9d379bd71a1e745eb9c64ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.cplxmul.r x32, x32, x32 + cv.cplxmul.r x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..c9baf4e5e2148ad8fb5874979202fa4714b66f2c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-cplxmul-r-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5400007b cv.cplxmul.r zero,zero,zero + 4: 541080fb cv.cplxmul.r ra,ra,ra + 8: 5421017b cv.cplxmul.r sp,sp,sp + c: 5484047b cv.cplxmul.r s0,s0,s0 + 10: 554a0a7b cv.cplxmul.r s4,s4,s4 + 14: 55ff8ffb cv.cplxmul.r t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..8f588e7edee90e5145cdcb47c31c64f6fd200990 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-cplxmul-r-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.cplxmul.r x0, x0, x0 + cv.cplxmul.r x1, x1, x1 + cv.cplxmul.r x2, x2, x2 + cv.cplxmul.r x8, x8, x8 + cv.cplxmul.r x20, x20, x20 + cv.cplxmul.r x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a21ba0453cfe154ba0e9e41b551cd5d8b8408326 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-b-fail.s +#error_output: cv-dotsp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..05e061341487696b8acccaa186dd1122a81b1d92 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.b x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..233872c9e037221f40d294de44c2555021baa7ca --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.b x32, x32, x32 + cv.dotsp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..dfdbbea1477721911f7869b96e0f5e043b5942ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000107b cv.dotsp.b zero,zero,zero + 4: 901090fb cv.dotsp.b ra,ra,ra + 8: 9021117b cv.dotsp.b sp,sp,sp + c: 9084147b cv.dotsp.b s0,s0,s0 + 10: 914a1a7b cv.dotsp.b s4,s4,s4 + 14: 91ff9ffb cv.dotsp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e42ccef2344af43dc92db886d49cbaced5c73f9c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.b x0, x0, x0 + cv.dotsp.b x1, x1, x1 + cv.dotsp.b x2, x2, x2 + cv.dotsp.b x8, x8, x8 + cv.dotsp.b x20, x20, x20 + cv.dotsp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..17ed00fb91e733e140e6f1a1ea080b2a51c6912a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-h-fail.s +#error_output: cv-dotsp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9a4969c3e922006d769a597c735dc63cf55443b0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.h x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..309d96733e47b094218aa978409382da322017fd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.h x32, x32, x32 + cv.dotsp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..664718938f38cd4dd6107df7ad9aa80d2919c7ca --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000007b cv.dotsp.h zero,zero,zero + 4: 901080fb cv.dotsp.h ra,ra,ra + 8: 9021017b cv.dotsp.h sp,sp,sp + c: 9084047b cv.dotsp.h s0,s0,s0 + 10: 914a0a7b cv.dotsp.h s4,s4,s4 + 14: 91ff8ffb cv.dotsp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b9d49cbbfc564aa61dcd392c432fe4581cdb6dd6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.h x0, x0, x0 + cv.dotsp.h x1, x1, x1 + cv.dotsp.h x2, x2, x2 + cv.dotsp.h x8, x8, x8 + cv.dotsp.h x20, x20, x20 + cv.dotsp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..88976c2469de1dbd9e7e33f2bde1453a77e78f63 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-b-fail.s +#error_output: cv-dotsp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..f08b9016d620e39c9eee6f240907b04f34ba82cc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b45e83cfc31bb34d9c3d6e86417139d6539eea33 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.sc.b x32, x32, x32 + cv.dotsp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..701dfe1b75d19f4e6a298f1cb5e36521665f88bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000507b cv.dotsp.sc.b zero,zero,zero + 4: 9010d0fb cv.dotsp.sc.b ra,ra,ra + 8: 9021517b cv.dotsp.sc.b sp,sp,sp + c: 9084547b cv.dotsp.sc.b s0,s0,s0 + 10: 914a5a7b cv.dotsp.sc.b s4,s4,s4 + 14: 91ffdffb cv.dotsp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..966a6ca8a8b80f50d9066422d6dde74651e1f560 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.sc.b x0, x0, x0 + cv.dotsp.sc.b x1, x1, x1 + cv.dotsp.sc.b x2, x2, x2 + cv.dotsp.sc.b x8, x8, x8 + cv.dotsp.sc.b x20, x20, x20 + cv.dotsp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b6e424fcf439aafc3bc340556b9b8ab961e59043 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-h-fail.s +#error_output: cv-dotsp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..16aa43d60bddffecba6233ab5300a9cf21e635b0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.dotsp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..935203cae15df6b89c8c64affc57ab6ebf0a4e59 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotsp.sc.h x32, x32, x32 + cv.dotsp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..47628f309d8dfc348a50c20fcd3116675a30dc8f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9000407b cv.dotsp.sc.h zero,zero,zero + 4: 9010c0fb cv.dotsp.sc.h ra,ra,ra + 8: 9021417b cv.dotsp.sc.h sp,sp,sp + c: 9084447b cv.dotsp.sc.h s0,s0,s0 + 10: 914a4a7b cv.dotsp.sc.h s4,s4,s4 + 14: 91ffcffb cv.dotsp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..a9e6ccc2cb5447be9a58f723b18b35130b96e038 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotsp.sc.h x0, x0, x0 + cv.dotsp.sc.h x1, x1, x1 + cv.dotsp.sc.h x2, x2, x2 + cv.dotsp.sc.h x8, x8, x8 + cv.dotsp.sc.h x20, x20, x20 + cv.dotsp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a17365682182a048d07e77d18384bf1e330e6f05 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-b-fail.s +#error_output: cv-dotsp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..76fff08f39b41a33e5649930a9f47faef6852dbf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.dotsp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..475b2207f85498a5c67d3b1ffa34189d35402367 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotsp.sci.b x32, x32, 20 + cv.dotsp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.dotsp.sci.b x6, x7, -33 + cv.dotsp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f655daffd463c709713def9c1b8b15f0a46dab3a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9140707b cv.dotsp.sci.b zero,zero,20 + 4: 9140f0fb cv.dotsp.sci.b ra,ra,20 + 8: 9141717b cv.dotsp.sci.b sp,sp,20 + c: 9144747b cv.dotsp.sci.b s0,s0,20 + 10: 914a7a7b cv.dotsp.sci.b s4,s4,20 + 14: 914ffffb cv.dotsp.sci.b t6,t6,20 + 18: 9203f37b cv.dotsp.sci.b t1,t2,-32 + 1c: 9003f37b cv.dotsp.sci.b t1,t2,0 + 20: 91f3f37b cv.dotsp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..47bc8405e8f48b89997d09a98d045bc1a3358446 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotsp.sci.b x0, x0, 20 + cv.dotsp.sci.b x1, x1, 20 + cv.dotsp.sci.b x2, x2, 20 + cv.dotsp.sci.b x8, x8, 20 + cv.dotsp.sci.b x20, x20, 20 + cv.dotsp.sci.b x31, x31, 20 + #Immediate Values Test + cv.dotsp.sci.b x6, x7, -32 + cv.dotsp.sci.b x6, x7, 0 + cv.dotsp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a3b6a1fc521c593ad483b3f226a823c280bbf2f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-h-fail.s +#error_output: cv-dotsp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9410a24e1c945e68323d416df7969856ab8f1003 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotsp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.dotsp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..ba4a59e29b42f2d665040ea959de20ccbfd5ffc6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotsp.sci.h x32, x32, 20 + cv.dotsp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.dotsp.sci.h x6, x7, -33 + cv.dotsp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..869060ab27e1f20adf6032463a4bb31deba92200 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotsp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9140607b cv.dotsp.sci.h zero,zero,20 + 4: 9140e0fb cv.dotsp.sci.h ra,ra,20 + 8: 9141617b cv.dotsp.sci.h sp,sp,20 + c: 9144647b cv.dotsp.sci.h s0,s0,20 + 10: 914a6a7b cv.dotsp.sci.h s4,s4,20 + 14: 914feffb cv.dotsp.sci.h t6,t6,20 + 18: 9203e37b cv.dotsp.sci.h t1,t2,-32 + 1c: 9003e37b cv.dotsp.sci.h t1,t2,0 + 20: 91f3e37b cv.dotsp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..9503a70569721e776885807dc729de8b93655364 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotsp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotsp.sci.h x0, x0, 20 + cv.dotsp.sci.h x1, x1, 20 + cv.dotsp.sci.h x2, x2, 20 + cv.dotsp.sci.h x8, x8, 20 + cv.dotsp.sci.h x20, x20, 20 + cv.dotsp.sci.h x31, x31, 20 + #Immediate Values Test + cv.dotsp.sci.h x6, x7, -32 + cv.dotsp.sci.h x6, x7, 0 + cv.dotsp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-fail.d b/gas/testsuite/gas/riscv/cv-dotup-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..50aae60c56e8aaa6178e2b306e6b3d57b457ec71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-b-fail.s +#error_output: cv-dotup-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-fail.l b/gas/testsuite/gas/riscv/cv-dotup-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7a3964aece111c6424e59dcd4d54b5a982c29938 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.b x32,x32,x32' +.*: Error: illegal operands `cv.dotup.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-fail.s b/gas/testsuite/gas/riscv/cv-dotup-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..be8a84793ab66f38db9f49e21e16cdc32c749ac5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.b x32, x32, x32 + cv.dotup.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-pass.d b/gas/testsuite/gas/riscv/cv-dotup-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..64bd7881258b9820e0a3a748674c16b8d4cf1b4e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000107b cv.dotup.b zero,zero,zero + 4: 801090fb cv.dotup.b ra,ra,ra + 8: 8021117b cv.dotup.b sp,sp,sp + c: 8084147b cv.dotup.b s0,s0,s0 + 10: 814a1a7b cv.dotup.b s4,s4,s4 + 14: 81ff9ffb cv.dotup.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-b-pass.s b/gas/testsuite/gas/riscv/cv-dotup-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..92b94f9a382eac014cf02650d535bc28a57217b4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.b x0, x0, x0 + cv.dotup.b x1, x1, x1 + cv.dotup.b x2, x2, x2 + cv.dotup.b x8, x8, x8 + cv.dotup.b x20, x20, x20 + cv.dotup.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-fail.d b/gas/testsuite/gas/riscv/cv-dotup-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..5d53fe324e4f47e20a7aeea92ed1668625105865 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-h-fail.s +#error_output: cv-dotup-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-fail.l b/gas/testsuite/gas/riscv/cv-dotup-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..3bc820e3e8b6d49ba0e228067245b64726fe6c35 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.h x32,x32,x32' +.*: Error: illegal operands `cv.dotup.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-fail.s b/gas/testsuite/gas/riscv/cv-dotup-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..7a72d90c6ea97ff45b7c1b1e6053225eb5915c86 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.h x32, x32, x32 + cv.dotup.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-pass.d b/gas/testsuite/gas/riscv/cv-dotup-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..19685293ca33438d78ff7b6b16d20213b83d7361 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000007b cv.dotup.h zero,zero,zero + 4: 801080fb cv.dotup.h ra,ra,ra + 8: 8021017b cv.dotup.h sp,sp,sp + c: 8084047b cv.dotup.h s0,s0,s0 + 10: 814a0a7b cv.dotup.h s4,s4,s4 + 14: 81ff8ffb cv.dotup.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-h-pass.s b/gas/testsuite/gas/riscv/cv-dotup-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c5390d114aaf93a5e595d29d9628051225f58358 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.h x0, x0, x0 + cv.dotup.h x1, x1, x1 + cv.dotup.h x2, x2, x2 + cv.dotup.h x8, x8, x8 + cv.dotup.h x20, x20, x20 + cv.dotup.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..dec04b2f32a9e9d5e64edc31952f2a18df5ed8f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-b-fail.s +#error_output: cv-dotup-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..86044aeac47ee6c95a318972c3d49f12cad36bd0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.dotup.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c3265a0f753ba3fb290dc191d6108a6744a14ea7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.sc.b x32, x32, x32 + cv.dotup.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..bf81586c92f7b4ce9ef1065e8b2dcff7adb6460a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000507b cv.dotup.sc.b zero,zero,zero + 4: 8010d0fb cv.dotup.sc.b ra,ra,ra + 8: 8021517b cv.dotup.sc.b sp,sp,sp + c: 8084547b cv.dotup.sc.b s0,s0,s0 + 10: 814a5a7b cv.dotup.sc.b s4,s4,s4 + 14: 81ffdffb cv.dotup.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..126d7e3af2afbeb52f8b1709dbf2be648caaf60a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.sc.b x0, x0, x0 + cv.dotup.sc.b x1, x1, x1 + cv.dotup.sc.b x2, x2, x2 + cv.dotup.sc.b x8, x8, x8 + cv.dotup.sc.b x20, x20, x20 + cv.dotup.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..746e94a3c70377febe1b34937079f79fd961f2b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-h-fail.s +#error_output: cv-dotup-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c2264dcdb7c18e1caaddc4d261db01bd8f462a4f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.dotup.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..659fe95948270a37e36f2ed383b137eb30768452 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotup.sc.h x32, x32, x32 + cv.dotup.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3ecd2d7897ed9392e49e53f5d272b53a914066e7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8000407b cv.dotup.sc.h zero,zero,zero + 4: 8010c0fb cv.dotup.sc.h ra,ra,ra + 8: 8021417b cv.dotup.sc.h sp,sp,sp + c: 8084447b cv.dotup.sc.h s0,s0,s0 + 10: 814a4a7b cv.dotup.sc.h s4,s4,s4 + 14: 81ffcffb cv.dotup.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..89ee845f7cb36f8625c7f8eba106aacfeb47394d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotup.sc.h x0, x0, x0 + cv.dotup.sc.h x1, x1, x1 + cv.dotup.sc.h x2, x2, x2 + cv.dotup.sc.h x8, x8, x8 + cv.dotup.sc.h x20, x20, x20 + cv.dotup.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..fc0112e4eb0350bedbd68482f1f325284d90b768 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-b-fail.s +#error_output: cv-dotup-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c90d2c625edcabfa5f72f2f6ce9e1b315ded0b89 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sci.b x32,x32,20' +.*: Error: illegal operands `cv.dotup.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9fb5dbea8e480ac414ca28cb857984f08c14089d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotup.sci.b x32, x32, 20 + cv.dotup.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.dotup.sci.b x6, x7, -33 + cv.dotup.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..2359127abf18327831249375e7f01a1da0b7da8a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8140707b cv.dotup.sci.b zero,zero,20 + 4: 8140f0fb cv.dotup.sci.b ra,ra,20 + 8: 8141717b cv.dotup.sci.b sp,sp,20 + c: 8144747b cv.dotup.sci.b s0,s0,20 + 10: 814a7a7b cv.dotup.sci.b s4,s4,20 + 14: 814ffffb cv.dotup.sci.b t6,t6,20 + 18: 8203f37b cv.dotup.sci.b t1,t2,-32 + 1c: 8003f37b cv.dotup.sci.b t1,t2,0 + 20: 81f3f37b cv.dotup.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c1f236831258a1c4d7f6323f0f2e3708aa4b63b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotup.sci.b x0, x0, 20 + cv.dotup.sci.b x1, x1, 20 + cv.dotup.sci.b x2, x2, 20 + cv.dotup.sci.b x8, x8, 20 + cv.dotup.sci.b x20, x20, 20 + cv.dotup.sci.b x31, x31, 20 + #Immediate Values Test + cv.dotup.sci.b x6, x7, -32 + cv.dotup.sci.b x6, x7, 0 + cv.dotup.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8b7808e95ea868cee0871057105cc460b757ce87 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-h-fail.s +#error_output: cv-dotup-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..5e9b035aceab58942024a11366d9809b6690f63f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotup.sci.h x32,x32,20' +.*: Error: illegal operands `cv.dotup.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..ddab1f4389b84457dab2a2067a3eab0ae0a2afcf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotup.sci.h x32, x32, 20 + cv.dotup.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.dotup.sci.h x6, x7, -33 + cv.dotup.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..0f07d542782e948dd2ce8a81590928f81f6bdf3c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotup-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8140607b cv.dotup.sci.h zero,zero,20 + 4: 8140e0fb cv.dotup.sci.h ra,ra,20 + 8: 8141617b cv.dotup.sci.h sp,sp,20 + c: 8144647b cv.dotup.sci.h s0,s0,20 + 10: 814a6a7b cv.dotup.sci.h s4,s4,20 + 14: 814feffb cv.dotup.sci.h t6,t6,20 + 18: 8203e37b cv.dotup.sci.h t1,t2,-32 + 1c: 8003e37b cv.dotup.sci.h t1,t2,0 + 20: 81f3e37b cv.dotup.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..08d2cb1b8e8f45ce1fc0e1c23a8c14c49848a997 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotup-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotup.sci.h x0, x0, 20 + cv.dotup.sci.h x1, x1, 20 + cv.dotup.sci.h x2, x2, 20 + cv.dotup.sci.h x8, x8, 20 + cv.dotup.sci.h x20, x20, 20 + cv.dotup.sci.h x31, x31, 20 + #Immediate Values Test + cv.dotup.sci.h x6, x7, -32 + cv.dotup.sci.h x6, x7, 0 + cv.dotup.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7e7df1d80ac75d7182a97c3c414408dd907215a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-b-fail.s +#error_output: cv-dotusp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..da8dcc445894a09d5a9d2312f42b9deeebc46b32 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.b x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..875e9629d057b7ef5ce2b32fe4670d035542a73e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.b x32, x32, x32 + cv.dotusp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..2f4318efabf230fdaac3eac622eec2cedf098442 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800107b cv.dotusp.b zero,zero,zero + 4: 881090fb cv.dotusp.b ra,ra,ra + 8: 8821117b cv.dotusp.b sp,sp,sp + c: 8884147b cv.dotusp.b s0,s0,s0 + 10: 894a1a7b cv.dotusp.b s4,s4,s4 + 14: 89ff9ffb cv.dotusp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b39b8abc5da6f87d838c924d693738e080e6c65e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.b x0, x0, x0 + cv.dotusp.b x1, x1, x1 + cv.dotusp.b x2, x2, x2 + cv.dotusp.b x8, x8, x8 + cv.dotusp.b x20, x20, x20 + cv.dotusp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..fdf796e16f7bbc92011481228cf3f61520419055 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-h-fail.s +#error_output: cv-dotusp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..3b025c9b7189f8a3ae3882d46b82978b1c6a3fef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.h x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..cf41e79b32eea298fe28a2072c50dca1306e9ad8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.h x32, x32, x32 + cv.dotusp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..04f45a0f32c526dfea73dc39cb4c9a9b8f252a04 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800007b cv.dotusp.h zero,zero,zero + 4: 881080fb cv.dotusp.h ra,ra,ra + 8: 8821017b cv.dotusp.h sp,sp,sp + c: 8884047b cv.dotusp.h s0,s0,s0 + 10: 894a0a7b cv.dotusp.h s4,s4,s4 + 14: 89ff8ffb cv.dotusp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..8abcb4ea21c4c334390dd5a87e62475e4a61d179 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.h x0, x0, x0 + cv.dotusp.h x1, x1, x1 + cv.dotusp.h x2, x2, x2 + cv.dotusp.h x8, x8, x8 + cv.dotusp.h x20, x20, x20 + cv.dotusp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3caf83969dd27292714a06b0426dda05fd3d2c9e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-b-fail.s +#error_output: cv-dotusp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c1c7d325c9904408998d162477841ea3537e9e35 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a4a1cac98598c7416a836d17604cec91cd4d3301 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.sc.b x32, x32, x32 + cv.dotusp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..1932b6cb3d82900d4c66385b05695164b888c3d2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800507b cv.dotusp.sc.b zero,zero,zero + 4: 8810d0fb cv.dotusp.sc.b ra,ra,ra + 8: 8821517b cv.dotusp.sc.b sp,sp,sp + c: 8884547b cv.dotusp.sc.b s0,s0,s0 + 10: 894a5a7b cv.dotusp.sc.b s4,s4,s4 + 14: 89ffdffb cv.dotusp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7b8cc4f2b0391705ef064d9d6b4e560a8469b113 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.sc.b x0, x0, x0 + cv.dotusp.sc.b x1, x1, x1 + cv.dotusp.sc.b x2, x2, x2 + cv.dotusp.sc.b x8, x8, x8 + cv.dotusp.sc.b x20, x20, x20 + cv.dotusp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..320d1aa446fe26df57e6d0a7da97d74fb9f4eef8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-h-fail.s +#error_output: cv-dotusp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..48e1819aa5362e0d6df2fda52361bcc63d7475fc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.dotusp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a69450163b5718cfff28f58e4ad11baf186fc83e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.dotusp.sc.h x32, x32, x32 + cv.dotusp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3917f85b0a05b28f85bee1ec903dcb5e7c7cb014 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8800407b cv.dotusp.sc.h zero,zero,zero + 4: 8810c0fb cv.dotusp.sc.h ra,ra,ra + 8: 8821417b cv.dotusp.sc.h sp,sp,sp + c: 8884447b cv.dotusp.sc.h s0,s0,s0 + 10: 894a4a7b cv.dotusp.sc.h s4,s4,s4 + 14: 89ffcffb cv.dotusp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c10f72f2fa4d5968b67a7351682d135d4a7e9f1f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.dotusp.sc.h x0, x0, x0 + cv.dotusp.sc.h x1, x1, x1 + cv.dotusp.sc.h x2, x2, x2 + cv.dotusp.sc.h x8, x8, x8 + cv.dotusp.sc.h x20, x20, x20 + cv.dotusp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..604a44d11a2f6e33c7f697468cfd1a62b53833ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-b-fail.s +#error_output: cv-dotusp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..6e3e7bf28deda8f7b530728c36374847265f8a8b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.dotusp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..14a57c61669ca55451faf3c8b60eabe514833153 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotusp.sci.b x32, x32, 20 + cv.dotusp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.dotusp.sci.b x6, x7, -33 + cv.dotusp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..70c5f7a9ebfb6afd20ed868009ec3007c0317fb8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8940707b cv.dotusp.sci.b zero,zero,20 + 4: 8940f0fb cv.dotusp.sci.b ra,ra,20 + 8: 8941717b cv.dotusp.sci.b sp,sp,20 + c: 8944747b cv.dotusp.sci.b s0,s0,20 + 10: 894a7a7b cv.dotusp.sci.b s4,s4,20 + 14: 894ffffb cv.dotusp.sci.b t6,t6,20 + 18: 8a03f37b cv.dotusp.sci.b t1,t2,-32 + 1c: 8803f37b cv.dotusp.sci.b t1,t2,0 + 20: 89f3f37b cv.dotusp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..9ca11c5d86887da7e6e05f989f421ab89d18076f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotusp.sci.b x0, x0, 20 + cv.dotusp.sci.b x1, x1, 20 + cv.dotusp.sci.b x2, x2, 20 + cv.dotusp.sci.b x8, x8, 20 + cv.dotusp.sci.b x20, x20, 20 + cv.dotusp.sci.b x31, x31, 20 + #Immediate Values Test + cv.dotusp.sci.b x6, x7, -32 + cv.dotusp.sci.b x6, x7, 0 + cv.dotusp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..aa77b1964a062399bd3b43843c45623f09912261 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-h-fail.s +#error_output: cv-dotusp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..99f14c09c125f01c35ab71494c26d19d61e0bb8b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.dotusp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.dotusp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0075dd1b82269943512aa186c4a612b94d73d03d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.dotusp.sci.h x32, x32, 20 + cv.dotusp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.dotusp.sci.h x6, x7, -33 + cv.dotusp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ea7d3fcd967571371a0b4ac545c80363983cb240 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-dotusp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 8940607b cv.dotusp.sci.h zero,zero,20 + 4: 8940e0fb cv.dotusp.sci.h ra,ra,20 + 8: 8941617b cv.dotusp.sci.h sp,sp,20 + c: 8944647b cv.dotusp.sci.h s0,s0,20 + 10: 894a6a7b cv.dotusp.sci.h s4,s4,20 + 14: 894feffb cv.dotusp.sci.h t6,t6,20 + 18: 8a03e37b cv.dotusp.sci.h t1,t2,-32 + 1c: 8803e37b cv.dotusp.sci.h t1,t2,0 + 20: 89f3e37b cv.dotusp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..49528dc05e10a46ff25c612ab2c09a7d5a6019d7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-dotusp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.dotusp.sci.h x0, x0, 20 + cv.dotusp.sci.h x1, x1, 20 + cv.dotusp.sci.h x2, x2, 20 + cv.dotusp.sci.h x8, x8, 20 + cv.dotusp.sci.h x20, x20, 20 + cv.dotusp.sci.h x31, x31, 20 + #Immediate Values Test + cv.dotusp.sci.h x6, x7, -32 + cv.dotusp.sci.h x6, x7, 0 + cv.dotusp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extract-b-fail.d b/gas/testsuite/gas/riscv/cv-extract-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..da65de17617dc4945e48dea8676b52c317e7c462 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-b-fail.s +#error_output: cv-extract-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extract-b-fail.l b/gas/testsuite/gas/riscv/cv-extract-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..d2e8f29dea4ee0d7ad6de1de5d7e30341f1abf52 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extract.b x32,x32,20' +.*: Error: illegal operands `cv.extract.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extract-b-fail.s b/gas/testsuite/gas/riscv/cv-extract-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..6ad92d1db356309d037dd665e5215ec074de946e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extract.b x32, x32, 20 + cv.extract.b x33, x33, 20 + #Boundary Immediate Values Test + cv.extract.b x6, x7, -33 + cv.extract.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extract-b-pass.d b/gas/testsuite/gas/riscv/cv-extract-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..fde6ac901a4dc475826bdf8dc13573e76da684cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940107b cv.extract.b zero,zero,20 + 4: b94090fb cv.extract.b ra,ra,20 + 8: b941117b cv.extract.b sp,sp,20 + c: b944147b cv.extract.b s0,s0,20 + 10: b94a1a7b cv.extract.b s4,s4,20 + 14: b94f9ffb cv.extract.b t6,t6,20 + 18: ba03937b cv.extract.b t1,t2,-32 + 1c: b803937b cv.extract.b t1,t2,0 + 20: b9f3937b cv.extract.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extract-b-pass.s b/gas/testsuite/gas/riscv/cv-extract-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..d798e4050ae0ea22d11ea9e4671ef573aa2d0c72 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extract.b x0, x0, 20 + cv.extract.b x1, x1, 20 + cv.extract.b x2, x2, 20 + cv.extract.b x8, x8, 20 + cv.extract.b x20, x20, 20 + cv.extract.b x31, x31, 20 + #Immediate Values Test + cv.extract.b x6, x7, -32 + cv.extract.b x6, x7, 0 + cv.extract.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extract-h-fail.d b/gas/testsuite/gas/riscv/cv-extract-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7dac1d9b18d6fcf18b8dbd4c62e78ce10f83dfff --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-h-fail.s +#error_output: cv-extract-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extract-h-fail.l b/gas/testsuite/gas/riscv/cv-extract-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..488e09399cea2bd3212334800c6d1d8aef40faaa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extract.h x32,x32,20' +.*: Error: illegal operands `cv.extract.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extract-h-fail.s b/gas/testsuite/gas/riscv/cv-extract-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..6db2e75de1628eddc885b07895ac7dd802ed13d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extract.h x32, x32, 20 + cv.extract.h x33, x33, 20 + #Boundary Immediate Values Test + cv.extract.h x6, x7, -33 + cv.extract.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extract-h-pass.d b/gas/testsuite/gas/riscv/cv-extract-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..67f00cc20c3393ca497be438b722730e5992eba5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extract-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940007b cv.extract.h zero,zero,20 + 4: b94080fb cv.extract.h ra,ra,20 + 8: b941017b cv.extract.h sp,sp,20 + c: b944047b cv.extract.h s0,s0,20 + 10: b94a0a7b cv.extract.h s4,s4,20 + 14: b94f8ffb cv.extract.h t6,t6,20 + 18: ba03837b cv.extract.h t1,t2,-32 + 1c: b803837b cv.extract.h t1,t2,0 + 20: b9f3837b cv.extract.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extract-h-pass.s b/gas/testsuite/gas/riscv/cv-extract-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1962435c26b909c3b6b8e669cad372927e3680e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extract-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extract.h x0, x0, 20 + cv.extract.h x1, x1, 20 + cv.extract.h x2, x2, 20 + cv.extract.h x8, x8, 20 + cv.extract.h x20, x20, 20 + cv.extract.h x31, x31, 20 + #Immediate Values Test + cv.extract.h x6, x7, -32 + cv.extract.h x6, x7, 0 + cv.extract.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-fail.d b/gas/testsuite/gas/riscv/cv-extractu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7c8efc141e1a8e505fbd7c4b201a50038f267779 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-b-fail.s +#error_output: cv-extractu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-fail.l b/gas/testsuite/gas/riscv/cv-extractu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..41b2642562f634acd1c3c6936442ae195297542e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extractu.b x32,x32,20' +.*: Error: illegal operands `cv.extractu.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-fail.s b/gas/testsuite/gas/riscv/cv-extractu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..fe37572ae00be5d0a8561c10ccb53b69b3401c9f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extractu.b x32, x32, 20 + cv.extractu.b x33, x33, 20 + #Boundary Immediate Values Test + cv.extractu.b x6, x7, -33 + cv.extractu.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-pass.d b/gas/testsuite/gas/riscv/cv-extractu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..4e87a048cf06991e7f0d611123170ebc7b2628c2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940307b cv.extractu.b zero,zero,20 + 4: b940b0fb cv.extractu.b ra,ra,20 + 8: b941317b cv.extractu.b sp,sp,20 + c: b944347b cv.extractu.b s0,s0,20 + 10: b94a3a7b cv.extractu.b s4,s4,20 + 14: b94fbffb cv.extractu.b t6,t6,20 + 18: ba03b37b cv.extractu.b t1,t2,-32 + 1c: b803b37b cv.extractu.b t1,t2,0 + 20: b9f3b37b cv.extractu.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-b-pass.s b/gas/testsuite/gas/riscv/cv-extractu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e3711313b2e7eeb06fd1e0ae720bbf439473f42e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extractu.b x0, x0, 20 + cv.extractu.b x1, x1, 20 + cv.extractu.b x2, x2, 20 + cv.extractu.b x8, x8, 20 + cv.extractu.b x20, x20, 20 + cv.extractu.b x31, x31, 20 + #Immediate Values Test + cv.extractu.b x6, x7, -32 + cv.extractu.b x6, x7, 0 + cv.extractu.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-fail.d b/gas/testsuite/gas/riscv/cv-extractu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d4543a9d7ef81c3fc3e65199fc29b0c9fc83a604 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-h-fail.s +#error_output: cv-extractu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-fail.l b/gas/testsuite/gas/riscv/cv-extractu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..97e195317eb4f22480879d2be5d70773d2e271f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.extractu.h x32,x32,20' +.*: Error: illegal operands `cv.extractu.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-fail.s b/gas/testsuite/gas/riscv/cv-extractu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..39788e109fd1dd988bed21a79fc0e7d73169b433 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.extractu.h x32, x32, 20 + cv.extractu.h x33, x33, 20 + #Boundary Immediate Values Test + cv.extractu.h x6, x7, -33 + cv.extractu.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-pass.d b/gas/testsuite/gas/riscv/cv-extractu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..10652a9f1ea50ced812855bed068a3f5d78ff9a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-extractu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940207b cv.extractu.h zero,zero,20 + 4: b940a0fb cv.extractu.h ra,ra,20 + 8: b941217b cv.extractu.h sp,sp,20 + c: b944247b cv.extractu.h s0,s0,20 + 10: b94a2a7b cv.extractu.h s4,s4,20 + 14: b94faffb cv.extractu.h t6,t6,20 + 18: ba03a37b cv.extractu.h t1,t2,-32 + 1c: b803a37b cv.extractu.h t1,t2,0 + 20: b9f3a37b cv.extractu.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-extractu-h-pass.s b/gas/testsuite/gas/riscv/cv-extractu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..d8b32f6e5a45e40ff1e01097a0a8c0500ebe298f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-extractu-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.extractu.h x0, x0, 20 + cv.extractu.h x1, x1, 20 + cv.extractu.h x2, x2, 20 + cv.extractu.h x8, x8, 20 + cv.extractu.h x20, x20, 20 + cv.extractu.h x31, x31, 20 + #Immediate Values Test + cv.extractu.h x6, x7, -32 + cv.extractu.h x6, x7, 0 + cv.extractu.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-insert-b-fail.d b/gas/testsuite/gas/riscv/cv-insert-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..5d687c4329312eea2160a5643ea6bc39bd5b3aee --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-b-fail.s +#error_output: cv-insert-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-insert-b-fail.l b/gas/testsuite/gas/riscv/cv-insert-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7e01fc2a68a4fc8d67aa8e686a400a383493c585 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.insert.b x32,x32,20' +.*: Error: illegal operands `cv.insert.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-insert-b-fail.s b/gas/testsuite/gas/riscv/cv-insert-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..aebdcabfcb79359b6ad5648f3c9939af9e8eda78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.insert.b x32, x32, 20 + cv.insert.b x33, x33, 20 + #Boundary Immediate Values Test + cv.insert.b x6, x7, -33 + cv.insert.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-insert-b-pass.d b/gas/testsuite/gas/riscv/cv-insert-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..4da033ea94aaa9bedaa822588542504bc8782b84 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940507b cv.insert.b zero,zero,20 + 4: b940d0fb cv.insert.b ra,ra,20 + 8: b941517b cv.insert.b sp,sp,20 + c: b944547b cv.insert.b s0,s0,20 + 10: b94a5a7b cv.insert.b s4,s4,20 + 14: b94fdffb cv.insert.b t6,t6,20 + 18: ba03d37b cv.insert.b t1,t2,-32 + 1c: b803d37b cv.insert.b t1,t2,0 + 20: b9f3d37b cv.insert.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-insert-b-pass.s b/gas/testsuite/gas/riscv/cv-insert-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..a455628ddd8f1f9fbc78ac0ba9b30a674eb0b6f9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.insert.b x0, x0, 20 + cv.insert.b x1, x1, 20 + cv.insert.b x2, x2, 20 + cv.insert.b x8, x8, 20 + cv.insert.b x20, x20, 20 + cv.insert.b x31, x31, 20 + #Immediate Values Test + cv.insert.b x6, x7, -32 + cv.insert.b x6, x7, 0 + cv.insert.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-insert-h-fail.d b/gas/testsuite/gas/riscv/cv-insert-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..db89d6854d8076f8f184c2f4bc43ba70351ed9ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-h-fail.s +#error_output: cv-insert-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-insert-h-fail.l b/gas/testsuite/gas/riscv/cv-insert-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..efb6bf3c9d46cc1ce37fa31a87785004fddc9d3b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.insert.h x32,x32,20' +.*: Error: illegal operands `cv.insert.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-insert-h-fail.s b/gas/testsuite/gas/riscv/cv-insert-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c95958f4279e443ccaa295beeb62288d4e1d04c2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.insert.h x32, x32, 20 + cv.insert.h x33, x33, 20 + #Boundary Immediate Values Test + cv.insert.h x6, x7, -33 + cv.insert.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-insert-h-pass.d b/gas/testsuite/gas/riscv/cv-insert-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e1c7e673407e3a6888da5e38a044ff1e19d4224f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-insert-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: b940407b cv.insert.h zero,zero,20 + 4: b940c0fb cv.insert.h ra,ra,20 + 8: b941417b cv.insert.h sp,sp,20 + c: b944447b cv.insert.h s0,s0,20 + 10: b94a4a7b cv.insert.h s4,s4,20 + 14: b94fcffb cv.insert.h t6,t6,20 + 18: ba03c37b cv.insert.h t1,t2,-32 + 1c: b803c37b cv.insert.h t1,t2,0 + 20: b9f3c37b cv.insert.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-insert-h-pass.s b/gas/testsuite/gas/riscv/cv-insert-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..442e933b768d89fe869da57713250e7f9104e9fe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-insert-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.insert.h x0, x0, 20 + cv.insert.h x1, x1, 20 + cv.insert.h x2, x2, 20 + cv.insert.h x8, x8, 20 + cv.insert.h x20, x20, 20 + cv.insert.h x31, x31, 20 + #Immediate Values Test + cv.insert.h x6, x7, -32 + cv.insert.h x6, x7, 0 + cv.insert.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-max-b-fail.d b/gas/testsuite/gas/riscv/cv-max-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3e827bd06c00da8c96f4b6e46401aa60869e0b9d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-b-fail.s +#error_output: cv-max-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-b-fail.l b/gas/testsuite/gas/riscv/cv-max-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ffa9db5ce2eb6c6b1972f8b54b5003413d817d6e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.b x32,x32,x32' +.*: Error: illegal operands `cv.max.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-b-fail.s b/gas/testsuite/gas/riscv/cv-max-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..6e172d02599fc6d1522f745bf01683923eb0ae6d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.b x32, x32, x32 + cv.max.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-b-pass.d b/gas/testsuite/gas/riscv/cv-max-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f790247e2e2b5e959e3e313d6741264130180928 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000107b cv.max.b zero,zero,zero + 4: 301090fb cv.max.b ra,ra,ra + 8: 3021117b cv.max.b sp,sp,sp + c: 3084147b cv.max.b s0,s0,s0 + 10: 314a1a7b cv.max.b s4,s4,s4 + 14: 31ff9ffb cv.max.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-b-pass.s b/gas/testsuite/gas/riscv/cv-max-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c3fbaac00363ee14ad7ea7d31389572ad36628f8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.b x0, x0, x0 + cv.max.b x1, x1, x1 + cv.max.b x2, x2, x2 + cv.max.b x8, x8, x8 + cv.max.b x20, x20, x20 + cv.max.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-h-fail.d b/gas/testsuite/gas/riscv/cv-max-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..bb263cf5102194708689469a9056481c2de830b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-h-fail.s +#error_output: cv-max-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-h-fail.l b/gas/testsuite/gas/riscv/cv-max-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..e99ba005a12351f7e65d168a3f0b59e966e18008 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.h x32,x32,x32' +.*: Error: illegal operands `cv.max.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-h-fail.s b/gas/testsuite/gas/riscv/cv-max-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a8b7670f0e33730bd82c4d3fa68f1326c8418b82 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.h x32, x32, x32 + cv.max.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-h-pass.d b/gas/testsuite/gas/riscv/cv-max-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..8fd0bdd2f7cf0cfae526f7aea1e9c153685e68ea --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000007b cv.max.h zero,zero,zero + 4: 301080fb cv.max.h ra,ra,ra + 8: 3021017b cv.max.h sp,sp,sp + c: 3084047b cv.max.h s0,s0,s0 + 10: 314a0a7b cv.max.h s4,s4,s4 + 14: 31ff8ffb cv.max.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-h-pass.s b/gas/testsuite/gas/riscv/cv-max-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..db8bdcc94b543b4f1e4baf0b7c4d84e63d855ed9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.h x0, x0, x0 + cv.max.h x1, x1, x1 + cv.max.h x2, x2, x2 + cv.max.h x8, x8, x8 + cv.max.h x20, x20, x20 + cv.max.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..90623287e4f1efa72205c1398b34336460141254 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-b-fail.s +#error_output: cv-max-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..62bb8033164556fcc4fa8f2f7c432f2600261689 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.max.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9856ce452ad4b8f287cdf2070728757e63fa8b74 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.sc.b x32, x32, x32 + cv.max.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..5e77ab30f71766fd9a68624558ba38ef4cc8b9d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000507b cv.max.sc.b zero,zero,zero + 4: 3010d0fb cv.max.sc.b ra,ra,ra + 8: 3021517b cv.max.sc.b sp,sp,sp + c: 3084547b cv.max.sc.b s0,s0,s0 + 10: 314a5a7b cv.max.sc.b s4,s4,s4 + 14: 31ffdffb cv.max.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..bd6af1624d92b27fe8035e554561d1fed08ea731 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.sc.b x0, x0, x0 + cv.max.sc.b x1, x1, x1 + cv.max.sc.b x2, x2, x2 + cv.max.sc.b x8, x8, x8 + cv.max.sc.b x20, x20, x20 + cv.max.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..0083bf4c75805bfecc6b1b358f10634e526f515a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-h-fail.s +#error_output: cv-max-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1b60f1d2a9be1423e1b4795c5b05d80d12a879b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.max.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..cb311e985bd0ebb6b59a94e351eebb2518f92c94 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.max.sc.h x32, x32, x32 + cv.max.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..6dad313c16225fc67c6ac09166e78480882ea266 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3000407b cv.max.sc.h zero,zero,zero + 4: 3010c0fb cv.max.sc.h ra,ra,ra + 8: 3021417b cv.max.sc.h sp,sp,sp + c: 3084447b cv.max.sc.h s0,s0,s0 + 10: 314a4a7b cv.max.sc.h s4,s4,s4 + 14: 31ffcffb cv.max.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-max-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..73e7b4ed3f57c1034b6af133f7180f316a2e4a61 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.max.sc.h x0, x0, x0 + cv.max.sc.h x1, x1, x1 + cv.max.sc.h x2, x2, x2 + cv.max.sc.h x8, x8, x8 + cv.max.sc.h x20, x20, x20 + cv.max.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..ff3634b956121bf9be2aca0584639371571d8975 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-b-fail.s +#error_output: cv-max-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..27fd4658b42c9dadb4b737a7c2ffffe2a0fc50df --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sci.b x32,x32,20' +.*: Error: illegal operands `cv.max.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..f6712c3ac94a2467f91ab8a97b7bba74c759375c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.max.sci.b x32, x32, 20 + cv.max.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.max.sci.b x6, x7, -33 + cv.max.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e7acdca27b569ef5f7530603d9a7eaaac268bda6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3140707b cv.max.sci.b zero,zero,20 + 4: 3140f0fb cv.max.sci.b ra,ra,20 + 8: 3141717b cv.max.sci.b sp,sp,20 + c: 3144747b cv.max.sci.b s0,s0,20 + 10: 314a7a7b cv.max.sci.b s4,s4,20 + 14: 314ffffb cv.max.sci.b t6,t6,20 + 18: 3203f37b cv.max.sci.b t1,t2,-32 + 1c: 3003f37b cv.max.sci.b t1,t2,0 + 20: 31f3f37b cv.max.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..10751b5b3eb88f909aa5c854a636604fd0354a3f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.max.sci.b x0, x0, 20 + cv.max.sci.b x1, x1, 20 + cv.max.sci.b x2, x2, 20 + cv.max.sci.b x8, x8, 20 + cv.max.sci.b x20, x20, 20 + cv.max.sci.b x31, x31, 20 + #Immediate Values Test + cv.max.sci.b x6, x7, -32 + cv.max.sci.b x6, x7, 0 + cv.max.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a56bdfe3d4a648cc7f98c1f54d62df6b59d073df --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-h-fail.s +#error_output: cv-max-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..de60c07a756ace245efc50269f4735162633cb42 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.max.sci.h x32,x32,20' +.*: Error: illegal operands `cv.max.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..fc8b8dd178f5ba4a3b37cca2cb646eeb213437af --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.max.sci.h x32, x32, 20 + cv.max.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.max.sci.h x6, x7, -33 + cv.max.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..6c7e4cbcac159fecaf230cdef483a28c0a711aaf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-max-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3140607b cv.max.sci.h zero,zero,20 + 4: 3140e0fb cv.max.sci.h ra,ra,20 + 8: 3141617b cv.max.sci.h sp,sp,20 + c: 3144647b cv.max.sci.h s0,s0,20 + 10: 314a6a7b cv.max.sci.h s4,s4,20 + 14: 314feffb cv.max.sci.h t6,t6,20 + 18: 3203e37b cv.max.sci.h t1,t2,-32 + 1c: 3003e37b cv.max.sci.h t1,t2,0 + 20: 31f3e37b cv.max.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-max-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f0e4c7b06127441272b4e1c7751eb7af64a2954c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-max-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.max.sci.h x0, x0, 20 + cv.max.sci.h x1, x1, 20 + cv.max.sci.h x2, x2, 20 + cv.max.sci.h x8, x8, 20 + cv.max.sci.h x20, x20, 20 + cv.max.sci.h x31, x31, 20 + #Immediate Values Test + cv.max.sci.h x6, x7, -32 + cv.max.sci.h x6, x7, 0 + cv.max.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-fail.d b/gas/testsuite/gas/riscv/cv-maxu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8de9f7b601fb045ceeea9708ecb62c9e4595c3f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-b-fail.s +#error_output: cv-maxu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-fail.l b/gas/testsuite/gas/riscv/cv-maxu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ac57a2f9361207b9b72de5cb8f8cdd065926334e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.b x32,x32,x32' +.*: Error: illegal operands `cv.maxu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-fail.s b/gas/testsuite/gas/riscv/cv-maxu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..aa05e82b980f78caa7fe1985154068811f17da00 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.b x32, x32, x32 + cv.maxu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-pass.d b/gas/testsuite/gas/riscv/cv-maxu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b5e7a8cd9036d389926da47e5f0710401f9518fe --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800107b cv.maxu.b zero,zero,zero + 4: 381090fb cv.maxu.b ra,ra,ra + 8: 3821117b cv.maxu.b sp,sp,sp + c: 3884147b cv.maxu.b s0,s0,s0 + 10: 394a1a7b cv.maxu.b s4,s4,s4 + 14: 39ff9ffb cv.maxu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-b-pass.s b/gas/testsuite/gas/riscv/cv-maxu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..6a87bf969b29ac3770c024dd0d350d432de6fa71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.b x0, x0, x0 + cv.maxu.b x1, x1, x1 + cv.maxu.b x2, x2, x2 + cv.maxu.b x8, x8, x8 + cv.maxu.b x20, x20, x20 + cv.maxu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-fail.d b/gas/testsuite/gas/riscv/cv-maxu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b0272e0a31a4169f96e0bfc340e6ffa6fdb63d42 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-h-fail.s +#error_output: cv-maxu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-fail.l b/gas/testsuite/gas/riscv/cv-maxu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1d530582eaab6da162dea37007a0917dc24f46c4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.h x32,x32,x32' +.*: Error: illegal operands `cv.maxu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-fail.s b/gas/testsuite/gas/riscv/cv-maxu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..f28718085c5ef983d1f25d249a9f1d81ba36b5d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.h x32, x32, x32 + cv.maxu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-pass.d b/gas/testsuite/gas/riscv/cv-maxu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..9947015ce2e363db664270e217cb2f964ed9e430 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800007b cv.maxu.h zero,zero,zero + 4: 381080fb cv.maxu.h ra,ra,ra + 8: 3821017b cv.maxu.h sp,sp,sp + c: 3884047b cv.maxu.h s0,s0,s0 + 10: 394a0a7b cv.maxu.h s4,s4,s4 + 14: 39ff8ffb cv.maxu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-h-pass.s b/gas/testsuite/gas/riscv/cv-maxu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..ecafc3afd1c451099e41ad8287c9adfeedacb571 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.h x0, x0, x0 + cv.maxu.h x1, x1, x1 + cv.maxu.h x2, x2, x2 + cv.maxu.h x8, x8, x8 + cv.maxu.h x20, x20, x20 + cv.maxu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..03bbc27c7953e62ce5d192d0aaea115e58cd552f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-b-fail.s +#error_output: cv-maxu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7f1928d30bdf05e542c0cdbd310de83c925477ae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.maxu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..68b8f9e41019a30cf39bbb55c272db8c87711622 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.sc.b x32, x32, x32 + cv.maxu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..717105464d7aff61daf8b4be81061e30275906b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800507b cv.maxu.sc.b zero,zero,zero + 4: 3810d0fb cv.maxu.sc.b ra,ra,ra + 8: 3821517b cv.maxu.sc.b sp,sp,sp + c: 3884547b cv.maxu.sc.b s0,s0,s0 + 10: 394a5a7b cv.maxu.sc.b s4,s4,s4 + 14: 39ffdffb cv.maxu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..37273c1beb44b56da7caad9bb21de74fc60e7c4f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.sc.b x0, x0, x0 + cv.maxu.sc.b x1, x1, x1 + cv.maxu.sc.b x2, x2, x2 + cv.maxu.sc.b x8, x8, x8 + cv.maxu.sc.b x20, x20, x20 + cv.maxu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..024c030fcf63057da5b9e21d5d0445c13c92cac6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-h-fail.s +#error_output: cv-maxu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1fc68d464286963083dd1cb7a4d60a1b19442e9b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.maxu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..1dd73f293cee89d7057eab96ad582b846ebfea2e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.maxu.sc.h x32, x32, x32 + cv.maxu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..5574784a461c587f31a3e5fbf0c520e5411a4e33 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3800407b cv.maxu.sc.h zero,zero,zero + 4: 3810c0fb cv.maxu.sc.h ra,ra,ra + 8: 3821417b cv.maxu.sc.h sp,sp,sp + c: 3884447b cv.maxu.sc.h s0,s0,s0 + 10: 394a4a7b cv.maxu.sc.h s4,s4,s4 + 14: 39ffcffb cv.maxu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5d1c42c962a65b8a65f69c5f0ecbb38ed56d77dd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.maxu.sc.h x0, x0, x0 + cv.maxu.sc.h x1, x1, x1 + cv.maxu.sc.h x2, x2, x2 + cv.maxu.sc.h x8, x8, x8 + cv.maxu.sc.h x20, x20, x20 + cv.maxu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8db25e2cc74fc7356399c660fb631511e54bae4b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-b-fail.s +#error_output: cv-maxu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ef9234af536362399117077a60015a3338ebda0c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.maxu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..313ed227da997036b047036e7373037a7b9cd7ef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.maxu.sci.b x32, x32, 20 + cv.maxu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.maxu.sci.b x6, x7, -33 + cv.maxu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..afb737cafc4a23eb75c6c91354a47fdeacd59bd4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3940707b cv.maxu.sci.b zero,zero,20 + 4: 3940f0fb cv.maxu.sci.b ra,ra,20 + 8: 3941717b cv.maxu.sci.b sp,sp,20 + c: 3944747b cv.maxu.sci.b s0,s0,20 + 10: 394a7a7b cv.maxu.sci.b s4,s4,20 + 14: 394ffffb cv.maxu.sci.b t6,t6,20 + 18: 3a03f37b cv.maxu.sci.b t1,t2,-32 + 1c: 3803f37b cv.maxu.sci.b t1,t2,0 + 20: 39f3f37b cv.maxu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..516b8009979473f1fdfba8d78be6a40d63e9bff3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.maxu.sci.b x0, x0, 20 + cv.maxu.sci.b x1, x1, 20 + cv.maxu.sci.b x2, x2, 20 + cv.maxu.sci.b x8, x8, 20 + cv.maxu.sci.b x20, x20, 20 + cv.maxu.sci.b x31, x31, 20 + #Immediate Values Test + cv.maxu.sci.b x6, x7, -32 + cv.maxu.sci.b x6, x7, 0 + cv.maxu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..66e84a018b38c9d78ac646c7b53a9c3e1808f9d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-h-fail.s +#error_output: cv-maxu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c179ee0877462e59fb1c3d40551c8357b66e5185 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.maxu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.maxu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..40b56706bdc6ed5d9d3c3b2f46a5cf15255e0f3a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.maxu.sci.h x32, x32, 20 + cv.maxu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.maxu.sci.h x6, x7, -33 + cv.maxu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..29d2810b2762c13a1bf874b1b4b4078150af7c3f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-maxu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 3940607b cv.maxu.sci.h zero,zero,20 + 4: 3940e0fb cv.maxu.sci.h ra,ra,20 + 8: 3941617b cv.maxu.sci.h sp,sp,20 + c: 3944647b cv.maxu.sci.h s0,s0,20 + 10: 394a6a7b cv.maxu.sci.h s4,s4,20 + 14: 394feffb cv.maxu.sci.h t6,t6,20 + 18: 3a03e37b cv.maxu.sci.h t1,t2,-32 + 1c: 3803e37b cv.maxu.sci.h t1,t2,0 + 20: 39f3e37b cv.maxu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..67d6309f659366c3412d001cdbeab1f9fc4bd6b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-maxu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.maxu.sci.h x0, x0, 20 + cv.maxu.sci.h x1, x1, 20 + cv.maxu.sci.h x2, x2, 20 + cv.maxu.sci.h x8, x8, 20 + cv.maxu.sci.h x20, x20, 20 + cv.maxu.sci.h x31, x31, 20 + #Immediate Values Test + cv.maxu.sci.h x6, x7, -32 + cv.maxu.sci.h x6, x7, 0 + cv.maxu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-min-b-fail.d b/gas/testsuite/gas/riscv/cv-min-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..47a5be9790d18ef0e0f9951f3b0dffa1ef34cd33 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-b-fail.s +#error_output: cv-min-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-b-fail.l b/gas/testsuite/gas/riscv/cv-min-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..3d78d2d91b8e9bef79517156080eff71fb41180b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.b x32,x32,x32' +.*: Error: illegal operands `cv.min.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-b-fail.s b/gas/testsuite/gas/riscv/cv-min-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0d6ed295eed05c729b904ba9f144c5731dc33819 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.b x32, x32, x32 + cv.min.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-b-pass.d b/gas/testsuite/gas/riscv/cv-min-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ff8ae63b01712470a46cf02cea8dd745773e643a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000107b cv.min.b zero,zero,zero + 4: 201090fb cv.min.b ra,ra,ra + 8: 2021117b cv.min.b sp,sp,sp + c: 2084147b cv.min.b s0,s0,s0 + 10: 214a1a7b cv.min.b s4,s4,s4 + 14: 21ff9ffb cv.min.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-b-pass.s b/gas/testsuite/gas/riscv/cv-min-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..40af59781be5660cbda2f36bd4536da0a322faf1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.b x0, x0, x0 + cv.min.b x1, x1, x1 + cv.min.b x2, x2, x2 + cv.min.b x8, x8, x8 + cv.min.b x20, x20, x20 + cv.min.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-h-fail.d b/gas/testsuite/gas/riscv/cv-min-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..25f5ce03f7608b509e93ebfea85c9e2183c8d755 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-h-fail.s +#error_output: cv-min-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-h-fail.l b/gas/testsuite/gas/riscv/cv-min-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0f959466de858308caa9e3d72900619af50003d7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.h x32,x32,x32' +.*: Error: illegal operands `cv.min.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-h-fail.s b/gas/testsuite/gas/riscv/cv-min-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..2e30e37c7954b7e389c8ebe6fc7bc60bea14bcfb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.h x32, x32, x32 + cv.min.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-h-pass.d b/gas/testsuite/gas/riscv/cv-min-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f3da47b079be6a88bfceecfae05518b2b0741db2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000007b cv.min.h zero,zero,zero + 4: 201080fb cv.min.h ra,ra,ra + 8: 2021017b cv.min.h sp,sp,sp + c: 2084047b cv.min.h s0,s0,s0 + 10: 214a0a7b cv.min.h s4,s4,s4 + 14: 21ff8ffb cv.min.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-h-pass.s b/gas/testsuite/gas/riscv/cv-min-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f3ab4b20b74b7f2ee19fd2dab2f3d7d10505319d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.h x0, x0, x0 + cv.min.h x1, x1, x1 + cv.min.h x2, x2, x2 + cv.min.h x8, x8, x8 + cv.min.h x20, x20, x20 + cv.min.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..4ebd92a2603c91cb3735e2f0c47dd4bc4c63d5ad --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-b-fail.s +#error_output: cv-min-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7f31ec02691612175d5ecf33ba018efa5ff8fbd6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.min.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5b7fdcc7aa11bf777a81110f6a8f91a43cda0d37 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.sc.b x32, x32, x32 + cv.min.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..7cc616b5d1d2fec51ee9ec31747e216e345da2b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000507b cv.min.sc.b zero,zero,zero + 4: 2010d0fb cv.min.sc.b ra,ra,ra + 8: 2021517b cv.min.sc.b sp,sp,sp + c: 2084547b cv.min.sc.b s0,s0,s0 + 10: 214a5a7b cv.min.sc.b s4,s4,s4 + 14: 21ffdffb cv.min.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..671b8d32a6bb20be48a324829b6ffc08050ec733 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.sc.b x0, x0, x0 + cv.min.sc.b x1, x1, x1 + cv.min.sc.b x2, x2, x2 + cv.min.sc.b x8, x8, x8 + cv.min.sc.b x20, x20, x20 + cv.min.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..33b17fb725bdbde5db6d341c4c0125dbd5fff49d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-h-fail.s +#error_output: cv-min-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..72ce1e76a292d296c9779c3c6653e83e6349b57e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.min.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5b62233762bf520e0002de5737a056f469ed87e5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.min.sc.h x32, x32, x32 + cv.min.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..2d3f39c03bcbfa73edbe3a0846dd2f6d362cff29 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2000407b cv.min.sc.h zero,zero,zero + 4: 2010c0fb cv.min.sc.h ra,ra,ra + 8: 2021417b cv.min.sc.h sp,sp,sp + c: 2084447b cv.min.sc.h s0,s0,s0 + 10: 214a4a7b cv.min.sc.h s4,s4,s4 + 14: 21ffcffb cv.min.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-min-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..19ed53f70add003da3f0a738b99055560f8bdc29 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.min.sc.h x0, x0, x0 + cv.min.sc.h x1, x1, x1 + cv.min.sc.h x2, x2, x2 + cv.min.sc.h x8, x8, x8 + cv.min.sc.h x20, x20, x20 + cv.min.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7940871392d4a77ce47cc0c78223ce6a801d37cb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-b-fail.s +#error_output: cv-min-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..204cae31c6aa11cbf221abfc6d82fcb581d1fbf7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sci.b x32,x32,20' +.*: Error: illegal operands `cv.min.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..6144655cdb0adacc33ba33608906e1b2ba24feb9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.min.sci.b x32, x32, 20 + cv.min.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.min.sci.b x6, x7, -33 + cv.min.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..cfb0ac0d7394f92f61b244b8e3994895715e8550 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2140707b cv.min.sci.b zero,zero,20 + 4: 2140f0fb cv.min.sci.b ra,ra,20 + 8: 2141717b cv.min.sci.b sp,sp,20 + c: 2144747b cv.min.sci.b s0,s0,20 + 10: 214a7a7b cv.min.sci.b s4,s4,20 + 14: 214ffffb cv.min.sci.b t6,t6,20 + 18: 2203f37b cv.min.sci.b t1,t2,-32 + 1c: 2003f37b cv.min.sci.b t1,t2,0 + 20: 21f3f37b cv.min.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..bef55674ef3db36311ef7553fc9daf99c98e16a7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.min.sci.b x0, x0, 20 + cv.min.sci.b x1, x1, 20 + cv.min.sci.b x2, x2, 20 + cv.min.sci.b x8, x8, 20 + cv.min.sci.b x20, x20, 20 + cv.min.sci.b x31, x31, 20 + #Immediate Values Test + cv.min.sci.b x6, x7, -32 + cv.min.sci.b x6, x7, 0 + cv.min.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..357129735f4463511947f7b316049868183d7ef3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-h-fail.s +#error_output: cv-min-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1179f3066630f4dd3ee63cb1a82ea128ee31896a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.min.sci.h x32,x32,20' +.*: Error: illegal operands `cv.min.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..6e911ce5a682390d4730cf551c55b36230b2546a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.min.sci.h x32, x32, 20 + cv.min.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.min.sci.h x6, x7, -33 + cv.min.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ae57846549f8489b6366c490f3b1172bb90614c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-min-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2140607b cv.min.sci.h zero,zero,20 + 4: 2140e0fb cv.min.sci.h ra,ra,20 + 8: 2141617b cv.min.sci.h sp,sp,20 + c: 2144647b cv.min.sci.h s0,s0,20 + 10: 214a6a7b cv.min.sci.h s4,s4,20 + 14: 214feffb cv.min.sci.h t6,t6,20 + 18: 2203e37b cv.min.sci.h t1,t2,-32 + 1c: 2003e37b cv.min.sci.h t1,t2,0 + 20: 21f3e37b cv.min.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-min-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7f134823fabedacd0ce33608ad2d3624f9613683 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-min-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.min.sci.h x0, x0, 20 + cv.min.sci.h x1, x1, 20 + cv.min.sci.h x2, x2, 20 + cv.min.sci.h x8, x8, 20 + cv.min.sci.h x20, x20, 20 + cv.min.sci.h x31, x31, 20 + #Immediate Values Test + cv.min.sci.h x6, x7, -32 + cv.min.sci.h x6, x7, 0 + cv.min.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-minu-b-fail.d b/gas/testsuite/gas/riscv/cv-minu-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..57f2d016ffe7e1e83ceea4743a4b560199ec119d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-b-fail.s +#error_output: cv-minu-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-b-fail.l b/gas/testsuite/gas/riscv/cv-minu-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9971ea8223ece14362a69b1c85db31a7fdf26914 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.b x32,x32,x32' +.*: Error: illegal operands `cv.minu.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-b-fail.s b/gas/testsuite/gas/riscv/cv-minu-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c017c91d7c215dac91934d42b4382c7320318b8f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.b x32, x32, x32 + cv.minu.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-b-pass.d b/gas/testsuite/gas/riscv/cv-minu-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ba9b60730feff3d789eabe946117beb095bf40d5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800107b cv.minu.b zero,zero,zero + 4: 281090fb cv.minu.b ra,ra,ra + 8: 2821117b cv.minu.b sp,sp,sp + c: 2884147b cv.minu.b s0,s0,s0 + 10: 294a1a7b cv.minu.b s4,s4,s4 + 14: 29ff9ffb cv.minu.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-b-pass.s b/gas/testsuite/gas/riscv/cv-minu-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1ac118bd7bd20b0226fa8affb6306b0db7b34de4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.b x0, x0, x0 + cv.minu.b x1, x1, x1 + cv.minu.b x2, x2, x2 + cv.minu.b x8, x8, x8 + cv.minu.b x20, x20, x20 + cv.minu.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-h-fail.d b/gas/testsuite/gas/riscv/cv-minu-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..30eb8d7f13cfc1e9787d2776d339c2adab2b1b93 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-h-fail.s +#error_output: cv-minu-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-h-fail.l b/gas/testsuite/gas/riscv/cv-minu-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..8916337969a9b5ea947e9ea9184511a3ff13a768 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.h x32,x32,x32' +.*: Error: illegal operands `cv.minu.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-h-fail.s b/gas/testsuite/gas/riscv/cv-minu-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..eb1bd42d06ce65af0688bdd6b25225f2193ef559 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.h x32, x32, x32 + cv.minu.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-h-pass.d b/gas/testsuite/gas/riscv/cv-minu-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..5522f4a041d4dafdf38f992a4576e52b1bb3c6b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800007b cv.minu.h zero,zero,zero + 4: 281080fb cv.minu.h ra,ra,ra + 8: 2821017b cv.minu.h sp,sp,sp + c: 2884047b cv.minu.h s0,s0,s0 + 10: 294a0a7b cv.minu.h s4,s4,s4 + 14: 29ff8ffb cv.minu.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-h-pass.s b/gas/testsuite/gas/riscv/cv-minu-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..3c5dbaa63b5b92338de4f208466e45a036af5a94 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.h x0, x0, x0 + cv.minu.h x1, x1, x1 + cv.minu.h x2, x2, x2 + cv.minu.h x8, x8, x8 + cv.minu.h x20, x20, x20 + cv.minu.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..5519811ec4eb647d2d0b535c65d156653299b79a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-b-fail.s +#error_output: cv-minu-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..de8c2c89c0ed2ab5b687a22810a461428ba39ccb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.minu.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..720480b15ed068dd21eae1b2a1d72e39074ff76d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.sc.b x32, x32, x32 + cv.minu.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d800c2693211b6bdb812dfb09199551d81757157 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800507b cv.minu.sc.b zero,zero,zero + 4: 2810d0fb cv.minu.sc.b ra,ra,ra + 8: 2821517b cv.minu.sc.b sp,sp,sp + c: 2884547b cv.minu.sc.b s0,s0,s0 + 10: 294a5a7b cv.minu.sc.b s4,s4,s4 + 14: 29ffdffb cv.minu.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..3b88a467e2716c5e5fffd003c157de812cee87a9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.sc.b x0, x0, x0 + cv.minu.sc.b x1, x1, x1 + cv.minu.sc.b x2, x2, x2 + cv.minu.sc.b x8, x8, x8 + cv.minu.sc.b x20, x20, x20 + cv.minu.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a6be722a22384795056085873213bc8882846777 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-h-fail.s +#error_output: cv-minu-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9d66f906a9fe923f6ce26f424509791488d46eda --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.minu.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5f421663ad7a692ccad3893c041fb0ed2e74f35b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.minu.sc.h x32, x32, x32 + cv.minu.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..cc3029308d57d7b5656b547132ed41c5cc6fdac1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2800407b cv.minu.sc.h zero,zero,zero + 4: 2810c0fb cv.minu.sc.h ra,ra,ra + 8: 2821417b cv.minu.sc.h sp,sp,sp + c: 2884447b cv.minu.sc.h s0,s0,s0 + 10: 294a4a7b cv.minu.sc.h s4,s4,s4 + 14: 29ffcffb cv.minu.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..9e752f493852b00faf8566545f93da924e5eacef --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.minu.sc.h x0, x0, x0 + cv.minu.sc.h x1, x1, x1 + cv.minu.sc.h x2, x2, x2 + cv.minu.sc.h x8, x8, x8 + cv.minu.sc.h x20, x20, x20 + cv.minu.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..1e4119399d6450f1110a6947014c8ba0eb17670d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-b-fail.s +#error_output: cv-minu-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b881f032a132b37681b95d1f2e09d69e54d01bf2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sci.b x32,x32,20' +.*: Error: illegal operands `cv.minu.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..7ff265eaab50aaf34326c004b1f4c324ef4baa8a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.minu.sci.b x32, x32, 20 + cv.minu.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.minu.sci.b x6, x7, -33 + cv.minu.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..9dbb758022e60d04e3bab5cdcb89534a6e859b42 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2940707b cv.minu.sci.b zero,zero,20 + 4: 2940f0fb cv.minu.sci.b ra,ra,20 + 8: 2941717b cv.minu.sci.b sp,sp,20 + c: 2944747b cv.minu.sci.b s0,s0,20 + 10: 294a7a7b cv.minu.sci.b s4,s4,20 + 14: 294ffffb cv.minu.sci.b t6,t6,20 + 18: 2a03f37b cv.minu.sci.b t1,t2,-32 + 1c: 2803f37b cv.minu.sci.b t1,t2,0 + 20: 29f3f37b cv.minu.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4316d1ba72557dac115fbdbb09b831f258bb8641 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.minu.sci.b x0, x0, 20 + cv.minu.sci.b x1, x1, 20 + cv.minu.sci.b x2, x2, 20 + cv.minu.sci.b x8, x8, 20 + cv.minu.sci.b x20, x20, 20 + cv.minu.sci.b x31, x31, 20 + #Immediate Values Test + cv.minu.sci.b x6, x7, -32 + cv.minu.sci.b x6, x7, 0 + cv.minu.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..f4f2ce69164563eb71fe325619dba3f245e81edc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-h-fail.s +#error_output: cv-minu-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..480d2900468fb22ed1dc42062835886666c0550f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.minu.sci.h x32,x32,20' +.*: Error: illegal operands `cv.minu.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b166efe69605c5b9708b6d6f2b44023e6d69fd8a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.minu.sci.h x32, x32, 20 + cv.minu.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.minu.sci.h x6, x7, -33 + cv.minu.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..c54d5ba73040ce10937b8f21117348d4dfcaec3c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-minu-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 2940607b cv.minu.sci.h zero,zero,20 + 4: 2940e0fb cv.minu.sci.h ra,ra,20 + 8: 2941617b cv.minu.sci.h sp,sp,20 + c: 2944647b cv.minu.sci.h s0,s0,20 + 10: 294a6a7b cv.minu.sci.h s4,s4,20 + 14: 294feffb cv.minu.sci.h t6,t6,20 + 18: 2a03e37b cv.minu.sci.h t1,t2,-32 + 1c: 2803e37b cv.minu.sci.h t1,t2,0 + 20: 29f3e37b cv.minu.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5511e0dc273c7e25bf98f0f7ffd574ab49698605 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-minu-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.minu.sci.h x0, x0, 20 + cv.minu.sci.h x1, x1, 20 + cv.minu.sci.h x2, x2, 20 + cv.minu.sci.h x8, x8, 20 + cv.minu.sci.h x20, x20, 20 + cv.minu.sci.h x31, x31, 20 + #Immediate Values Test + cv.minu.sci.h x6, x7, -32 + cv.minu.sci.h x6, x7, 0 + cv.minu.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-or-b-fail.d b/gas/testsuite/gas/riscv/cv-or-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a36c966689200108a1c829ce103f48905ee7b430 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-b-fail.s +#error_output: cv-or-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-b-fail.l b/gas/testsuite/gas/riscv/cv-or-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b74c77f5aecab9048f9990fef8c3fa00c047cd90 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.b x32,x32,x32' +.*: Error: illegal operands `cv.or.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-b-fail.s b/gas/testsuite/gas/riscv/cv-or-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..d0d81f550d4107b018dbee6933f1484f1d72ec40 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.b x32, x32, x32 + cv.or.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-b-pass.d b/gas/testsuite/gas/riscv/cv-or-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..81699ae29c6a1a534f17bede895c130048a385e6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800107b cv.or.b zero,zero,zero + 4: 581090fb cv.or.b ra,ra,ra + 8: 5821117b cv.or.b sp,sp,sp + c: 5884147b cv.or.b s0,s0,s0 + 10: 594a1a7b cv.or.b s4,s4,s4 + 14: 59ff9ffb cv.or.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-b-pass.s b/gas/testsuite/gas/riscv/cv-or-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..95155723eb238e97da59edf2cf492acba19d1891 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.b x0, x0, x0 + cv.or.b x1, x1, x1 + cv.or.b x2, x2, x2 + cv.or.b x8, x8, x8 + cv.or.b x20, x20, x20 + cv.or.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-h-fail.d b/gas/testsuite/gas/riscv/cv-or-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..124aaf29591433f01a848d52834f742ac3215bab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-h-fail.s +#error_output: cv-or-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-h-fail.l b/gas/testsuite/gas/riscv/cv-or-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..d0c6c34792ed33a784e71f13c82c68e7cefc4bd1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.h x32,x32,x32' +.*: Error: illegal operands `cv.or.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-h-fail.s b/gas/testsuite/gas/riscv/cv-or-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b3b72199264719e08064f696b08bc34f391c4746 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.h x32, x32, x32 + cv.or.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-h-pass.d b/gas/testsuite/gas/riscv/cv-or-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..4ba2ffc3cdb36668b1e2afd7e35b3600b2617977 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800007b cv.or.h zero,zero,zero + 4: 581080fb cv.or.h ra,ra,ra + 8: 5821017b cv.or.h sp,sp,sp + c: 5884047b cv.or.h s0,s0,s0 + 10: 594a0a7b cv.or.h s4,s4,s4 + 14: 59ff8ffb cv.or.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-h-pass.s b/gas/testsuite/gas/riscv/cv-or-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f53d50254409014a20815315a82978923fb64fd8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.h x0, x0, x0 + cv.or.h x1, x1, x1 + cv.or.h x2, x2, x2 + cv.or.h x8, x8, x8 + cv.or.h x20, x20, x20 + cv.or.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..f2c713b076c4d58fd47c2df5c0023bfd686e3a1f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-b-fail.s +#error_output: cv-or-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..91efc3051a428be4ef9b4510267f7aa357dedfde --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.or.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..672faf0a6b6c48d6078e1011f0aa0d300bd83838 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.sc.b x32, x32, x32 + cv.or.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..70bcf754c34c281f121cedba50d294ddf3fcff34 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800507b cv.or.sc.b zero,zero,zero + 4: 5810d0fb cv.or.sc.b ra,ra,ra + 8: 5821517b cv.or.sc.b sp,sp,sp + c: 5884547b cv.or.sc.b s0,s0,s0 + 10: 594a5a7b cv.or.sc.b s4,s4,s4 + 14: 59ffdffb cv.or.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..69829e57b2120e3df83d5be40959dc38139bacf7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.sc.b x0, x0, x0 + cv.or.sc.b x1, x1, x1 + cv.or.sc.b x2, x2, x2 + cv.or.sc.b x8, x8, x8 + cv.or.sc.b x20, x20, x20 + cv.or.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3a2293c4d2ddcd7aec07b8b2ea6e9836fbabc26c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-h-fail.s +#error_output: cv-or-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..18e64bd956a6f1596ebb94d911962f005a4cc692 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.or.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b3f8574ba52a871e10bf23ddc822c6f4e8ace05a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.or.sc.h x32, x32, x32 + cv.or.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..aed2f98951f4ac9038c562500a55d35f542946c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5800407b cv.or.sc.h zero,zero,zero + 4: 5810c0fb cv.or.sc.h ra,ra,ra + 8: 5821417b cv.or.sc.h sp,sp,sp + c: 5884447b cv.or.sc.h s0,s0,s0 + 10: 594a4a7b cv.or.sc.h s4,s4,s4 + 14: 59ffcffb cv.or.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-or-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..611d7bbf55d4324fab3ee6025d813ffea41c37da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.or.sc.h x0, x0, x0 + cv.or.sc.h x1, x1, x1 + cv.or.sc.h x2, x2, x2 + cv.or.sc.h x8, x8, x8 + cv.or.sc.h x20, x20, x20 + cv.or.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d7c2b50a4422bf12c424fb6fc9d5a151488c0a3b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-b-fail.s +#error_output: cv-or-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..475ea370e42878b930414a7693b7695f6b069444 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sci.b x32,x32,20' +.*: Error: illegal operands `cv.or.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..27cc046d5d7063841a5984254c3d3bcdea7db1f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.or.sci.b x32, x32, 20 + cv.or.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.or.sci.b x6, x7, -33 + cv.or.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..cd8b8e29f3e43b2870ab1c6c874c7b376979e142 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5940707b cv.or.sci.b zero,zero,20 + 4: 5940f0fb cv.or.sci.b ra,ra,20 + 8: 5941717b cv.or.sci.b sp,sp,20 + c: 5944747b cv.or.sci.b s0,s0,20 + 10: 594a7a7b cv.or.sci.b s4,s4,20 + 14: 594ffffb cv.or.sci.b t6,t6,20 + 18: 5a03f37b cv.or.sci.b t1,t2,-32 + 1c: 5803f37b cv.or.sci.b t1,t2,0 + 20: 59f3f37b cv.or.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..36c55cf5e7549c10dcd792b421021f53cb5fe90d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.or.sci.b x0, x0, 20 + cv.or.sci.b x1, x1, 20 + cv.or.sci.b x2, x2, 20 + cv.or.sci.b x8, x8, 20 + cv.or.sci.b x20, x20, 20 + cv.or.sci.b x31, x31, 20 + #Immediate Values Test + cv.or.sci.b x6, x7, -32 + cv.or.sci.b x6, x7, 0 + cv.or.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..80c5eb228f05ce76eb6f14b24f957d0c75e7acab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-h-fail.s +#error_output: cv-or-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..691d6d4354b9c3ab2c854fccc663990dd2f7f435 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.or.sci.h x32,x32,20' +.*: Error: illegal operands `cv.or.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..178bc1b806999b608d17af26cc275acb6622f335 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.or.sci.h x32, x32, 20 + cv.or.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.or.sci.h x6, x7, -33 + cv.or.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..dc50e44412523872de3cd6f592bb70b576cab350 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-or-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5940607b cv.or.sci.h zero,zero,20 + 4: 5940e0fb cv.or.sci.h ra,ra,20 + 8: 5941617b cv.or.sci.h sp,sp,20 + c: 5944647b cv.or.sci.h s0,s0,20 + 10: 594a6a7b cv.or.sci.h s4,s4,20 + 14: 594feffb cv.or.sci.h t6,t6,20 + 18: 5a03e37b cv.or.sci.h t1,t2,-32 + 1c: 5803e37b cv.or.sci.h t1,t2,0 + 20: 59f3e37b cv.or.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-or-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1fc6f304a71fcbc1a3f672ddce3f18297c8548e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-or-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.or.sci.h x0, x0, 20 + cv.or.sci.h x1, x1, 20 + cv.or.sci.h x2, x2, 20 + cv.or.sci.h x8, x8, 20 + cv.or.sci.h x20, x20, 20 + cv.or.sci.h x31, x31, 20 + #Immediate Values Test + cv.or.sci.h x6, x7, -32 + cv.or.sci.h x6, x7, 0 + cv.or.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-pack-fail.d b/gas/testsuite/gas/riscv/cv-pack-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..2a11f1f336178247960a425082d1ac9e4bfe2401 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-fail.s +#error_output: cv-pack-fail.l diff --git a/gas/testsuite/gas/riscv/cv-pack-fail.l b/gas/testsuite/gas/riscv/cv-pack-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9668f1f40c0c49289ff3da44c9ae093d35b3ebca --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.pack x32,x32,x32' +.*: Error: illegal operands `cv.pack x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-pack-fail.s b/gas/testsuite/gas/riscv/cv-pack-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..caf3ed7e0bcb8953705ca9d61542587f8ad9a98f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.pack x32, x32, x32 + cv.pack x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-pack-h-fail.d b/gas/testsuite/gas/riscv/cv-pack-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d84b22e0f7be9147cbac34a699469338ca5a23d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-h-fail.s +#error_output: cv-pack-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-pack-h-fail.l b/gas/testsuite/gas/riscv/cv-pack-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..db35aa977f563b81ba844e28f577c562ed96342d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.pack.h x32,x32,x32' +.*: Error: illegal operands `cv.pack.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-pack-h-fail.s b/gas/testsuite/gas/riscv/cv-pack-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..1b360c55e1d3fc79ab6bb7d7a2367568a50231fc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.pack.h x32, x32, x32 + cv.pack.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-pack-h-pass.d b/gas/testsuite/gas/riscv/cv-pack-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..962a02a6cc2350e634f7281a6aa0b069199fb262 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: f200007b cv.pack.h zero,zero,zero + 4: f21080fb cv.pack.h ra,ra,ra + 8: f221017b cv.pack.h sp,sp,sp + c: f284047b cv.pack.h s0,s0,s0 + 10: f34a0a7b cv.pack.h s4,s4,s4 + 14: f3ff8ffb cv.pack.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-pack-h-pass.s b/gas/testsuite/gas/riscv/cv-pack-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5b06ec1f4fad3b9bb039f567d0872b88c000b5b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.pack.h x0, x0, x0 + cv.pack.h x1, x1, x1 + cv.pack.h x2, x2, x2 + cv.pack.h x8, x8, x8 + cv.pack.h x20, x20, x20 + cv.pack.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-pack-pass.d b/gas/testsuite/gas/riscv/cv-pack-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..15d4bfdad81adc67cfbf9bed02cd3be4c1faae1f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-pack-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: f000007b cv.pack zero,zero,zero + 4: f01080fb cv.pack ra,ra,ra + 8: f021017b cv.pack sp,sp,sp + c: f084047b cv.pack s0,s0,s0 + 10: f14a0a7b cv.pack s4,s4,s4 + 14: f1ff8ffb cv.pack t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-pack-pass.s b/gas/testsuite/gas/riscv/cv-pack-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..bde466c1507efe8cbc733531e06949588129682d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-pack-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.pack x0, x0, x0 + cv.pack x1, x1, x1 + cv.pack x2, x2, x2 + cv.pack x8, x8, x8 + cv.pack x20, x20, x20 + cv.pack x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-fail.d b/gas/testsuite/gas/riscv/cv-packhi-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b347ddc7a1a1227d91ee6d3d97f31168f0483d16 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packhi-b-fail.s +#error_output: cv-packhi-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-fail.l b/gas/testsuite/gas/riscv/cv-packhi-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..60cc30ac241e8c429d674dc9ea203d864019e81d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.packhi.b x32,x32,x32' +.*: Error: illegal operands `cv.packhi.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-fail.s b/gas/testsuite/gas/riscv/cv-packhi-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..43b6fc82d34e12a1e346db95c763175f383f3cf5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.packhi.b x32, x32, x32 + cv.packhi.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-pass.d b/gas/testsuite/gas/riscv/cv-packhi-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..638bb3d1c0673b1b8702d484a6e9ea99ab368ab9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packhi-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: fa00107b cv.packhi.b zero,zero,zero + 4: fa1090fb cv.packhi.b ra,ra,ra + 8: fa21117b cv.packhi.b sp,sp,sp + c: fa84147b cv.packhi.b s0,s0,s0 + 10: fb4a1a7b cv.packhi.b s4,s4,s4 + 14: fbff9ffb cv.packhi.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-packhi-b-pass.s b/gas/testsuite/gas/riscv/cv-packhi-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c3a3eebf6c59325b9ba66329e9db68262e5e84d7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packhi-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.packhi.b x0, x0, x0 + cv.packhi.b x1, x1, x1 + cv.packhi.b x2, x2, x2 + cv.packhi.b x8, x8, x8 + cv.packhi.b x20, x20, x20 + cv.packhi.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-fail.d b/gas/testsuite/gas/riscv/cv-packlo-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..235071eb605952f2acde8e63fd3b9c1272b5ae29 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packlo-b-fail.s +#error_output: cv-packlo-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-fail.l b/gas/testsuite/gas/riscv/cv-packlo-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1141174e9e705fe562cca6c0747748b186d2861a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.packlo.b x32,x32,x32' +.*: Error: illegal operands `cv.packlo.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-fail.s b/gas/testsuite/gas/riscv/cv-packlo-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..f39d1ec4faf210fb5caaf33811936f90ebea5678 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.packlo.b x32, x32, x32 + cv.packlo.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-pass.d b/gas/testsuite/gas/riscv/cv-packlo-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e45be0c06c391ffd70c92b881819e99cb22e1d7a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-packlo-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: f800107b cv.packlo.b zero,zero,zero + 4: f81090fb cv.packlo.b ra,ra,ra + 8: f821117b cv.packlo.b sp,sp,sp + c: f884147b cv.packlo.b s0,s0,s0 + 10: f94a1a7b cv.packlo.b s4,s4,s4 + 14: f9ff9ffb cv.packlo.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-packlo-b-pass.s b/gas/testsuite/gas/riscv/cv-packlo-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..9d2a067d3f02f41255cb9e9b315a72f71b1b15b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-packlo-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.packlo.b x0, x0, x0 + cv.packlo.b x1, x1, x1 + cv.packlo.b x2, x2, x2 + cv.packlo.b x8, x8, x8 + cv.packlo.b x20, x20, x20 + cv.packlo.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..08b17291d28e468679cfebef727ef0f5c0170c61 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-b-fail.s +#error_output: cv-sdotsp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0171aeac5edaab0a0a3e2939eea7fa9de1c773b0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..2521ee9a886a73845f64d92b3b2d41b45864f484 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.b x32, x32, x32 + cv.sdotsp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..467e7d61600cc170ac22da527dc3c57d0a2df66d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800107b cv.sdotsp.b zero,zero,zero + 4: a81090fb cv.sdotsp.b ra,ra,ra + 8: a821117b cv.sdotsp.b sp,sp,sp + c: a884147b cv.sdotsp.b s0,s0,s0 + 10: a94a1a7b cv.sdotsp.b s4,s4,s4 + 14: a9ff9ffb cv.sdotsp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..bf1a7c60eaa352d3cbe830034ff9aea61e0a8f44 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.b x0, x0, x0 + cv.sdotsp.b x1, x1, x1 + cv.sdotsp.b x2, x2, x2 + cv.sdotsp.b x8, x8, x8 + cv.sdotsp.b x20, x20, x20 + cv.sdotsp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b274d93a817915382f8f08976f506389ddc9399f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-h-fail.s +#error_output: cv-sdotsp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ae9b66816ae6632a216333fc4e185215a6e29bf9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..067436e8dec2acbf06a5d178ac12ec6fe2168811 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.h x32, x32, x32 + cv.sdotsp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..c428f207831015d2557e8b5c1e66ec8fd55adcf8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800007b cv.sdotsp.h zero,zero,zero + 4: a81080fb cv.sdotsp.h ra,ra,ra + 8: a821017b cv.sdotsp.h sp,sp,sp + c: a884047b cv.sdotsp.h s0,s0,s0 + 10: a94a0a7b cv.sdotsp.h s4,s4,s4 + 14: a9ff8ffb cv.sdotsp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..90efc5b978f43692522e484efb5d6ca074471ba5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.h x0, x0, x0 + cv.sdotsp.h x1, x1, x1 + cv.sdotsp.h x2, x2, x2 + cv.sdotsp.h x8, x8, x8 + cv.sdotsp.h x20, x20, x20 + cv.sdotsp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..f941a1cf8a8d181121c53ff028a891cd670467fd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-b-fail.s +#error_output: cv-sdotsp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..020979b381cfc31c36866f910dd3ece26b3f5385 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5cd494400c0ed4678bd2b02c271fd73e1c231d1c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.sc.b x32, x32, x32 + cv.sdotsp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..0da4f1a9a660a7a32fbbfdb12c34025241e9659d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800507b cv.sdotsp.sc.b zero,zero,zero + 4: a810d0fb cv.sdotsp.sc.b ra,ra,ra + 8: a821517b cv.sdotsp.sc.b sp,sp,sp + c: a884547b cv.sdotsp.sc.b s0,s0,s0 + 10: a94a5a7b cv.sdotsp.sc.b s4,s4,s4 + 14: a9ffdffb cv.sdotsp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..98e6f5acbbc843a4be32d470685b975e816b5504 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.sc.b x0, x0, x0 + cv.sdotsp.sc.b x1, x1, x1 + cv.sdotsp.sc.b x2, x2, x2 + cv.sdotsp.sc.b x8, x8, x8 + cv.sdotsp.sc.b x20, x20, x20 + cv.sdotsp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..467a1636ea5c89ed8b8418516acf5ddb90d0be70 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-h-fail.s +#error_output: cv-sdotsp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..8a24210b195e5f6318069c5cd6912ee8b51985da --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotsp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..4a73a6e09fc3bf4434021f49f7dfd0e60a343d8e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotsp.sc.h x32, x32, x32 + cv.sdotsp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3f16823cc4379deb6e795368fdb25cb54caf88b9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a800407b cv.sdotsp.sc.h zero,zero,zero + 4: a810c0fb cv.sdotsp.sc.h ra,ra,ra + 8: a821417b cv.sdotsp.sc.h sp,sp,sp + c: a884447b cv.sdotsp.sc.h s0,s0,s0 + 10: a94a4a7b cv.sdotsp.sc.h s4,s4,s4 + 14: a9ffcffb cv.sdotsp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..ad3fac3fc2041b8f50a6d4fd4c60c053c562bccc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotsp.sc.h x0, x0, x0 + cv.sdotsp.sc.h x1, x1, x1 + cv.sdotsp.sc.h x2, x2, x2 + cv.sdotsp.sc.h x8, x8, x8 + cv.sdotsp.sc.h x20, x20, x20 + cv.sdotsp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..bccf1d0f53f72a2ad006f90db146be8a82b9e64d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-b-fail.s +#error_output: cv-sdotsp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..39f53beb9c32a9c1c52293e3079571b659894d31 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sdotsp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b79605e65f0e65149e6a29e983d6cb5912927e6d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotsp.sci.b x32, x32, 20 + cv.sdotsp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotsp.sci.b x6, x7, -33 + cv.sdotsp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b55aa3be2318e0d8d3a825889980bf9852d48149 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a940707b cv.sdotsp.sci.b zero,zero,20 + 4: a940f0fb cv.sdotsp.sci.b ra,ra,20 + 8: a941717b cv.sdotsp.sci.b sp,sp,20 + c: a944747b cv.sdotsp.sci.b s0,s0,20 + 10: a94a7a7b cv.sdotsp.sci.b s4,s4,20 + 14: a94ffffb cv.sdotsp.sci.b t6,t6,20 + 18: aa03f37b cv.sdotsp.sci.b t1,t2,-32 + 1c: a803f37b cv.sdotsp.sci.b t1,t2,0 + 20: a9f3f37b cv.sdotsp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c9aab8e06286f7a367025f8f62b843667b0e4ce0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotsp.sci.b x0, x0, 20 + cv.sdotsp.sci.b x1, x1, 20 + cv.sdotsp.sci.b x2, x2, 20 + cv.sdotsp.sci.b x8, x8, 20 + cv.sdotsp.sci.b x20, x20, 20 + cv.sdotsp.sci.b x31, x31, 20 + #Immediate Values Test + cv.sdotsp.sci.b x6, x7, -32 + cv.sdotsp.sci.b x6, x7, 0 + cv.sdotsp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..87c79a3689ab180a1b8d0b35ead9b30b0d9e4c5f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-h-fail.s +#error_output: cv-sdotsp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..28dda48691611403fab1f6d824bb660ca47c532e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotsp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sdotsp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..eb0788db611e872ce2b737f52487db2035ab5477 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotsp.sci.h x32, x32, 20 + cv.sdotsp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotsp.sci.h x6, x7, -33 + cv.sdotsp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e16cf6117b819ad6764f1eec47bea272bfcc6d01 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotsp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a940607b cv.sdotsp.sci.h zero,zero,20 + 4: a940e0fb cv.sdotsp.sci.h ra,ra,20 + 8: a941617b cv.sdotsp.sci.h sp,sp,20 + c: a944647b cv.sdotsp.sci.h s0,s0,20 + 10: a94a6a7b cv.sdotsp.sci.h s4,s4,20 + 14: a94feffb cv.sdotsp.sci.h t6,t6,20 + 18: aa03e37b cv.sdotsp.sci.h t1,t2,-32 + 1c: a803e37b cv.sdotsp.sci.h t1,t2,0 + 20: a9f3e37b cv.sdotsp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7af38caf00218d60e13926196c9129ab57f62439 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotsp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotsp.sci.h x0, x0, 20 + cv.sdotsp.sci.h x1, x1, 20 + cv.sdotsp.sci.h x2, x2, 20 + cv.sdotsp.sci.h x8, x8, 20 + cv.sdotsp.sci.h x20, x20, 20 + cv.sdotsp.sci.h x31, x31, 20 + #Immediate Values Test + cv.sdotsp.sci.h x6, x7, -32 + cv.sdotsp.sci.h x6, x7, 0 + cv.sdotsp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b3ed1484eef8b25974c3d1bc35d7f7853dae5adf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-b-fail.s +#error_output: cv-sdotup-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0230952e0612049731612d921a12d561fceb5aec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b92684acf7453106af57c7151b1abe416d9f9ee9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.b x32, x32, x32 + cv.sdotup.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..382c0e91d357920b6bf39b1f3dadd694bab26297 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800107b cv.sdotup.b zero,zero,zero + 4: 981090fb cv.sdotup.b ra,ra,ra + 8: 9821117b cv.sdotup.b sp,sp,sp + c: 9884147b cv.sdotup.b s0,s0,s0 + 10: 994a1a7b cv.sdotup.b s4,s4,s4 + 14: 99ff9ffb cv.sdotup.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..eacf6e1293be5192415717415e15b402822cc870 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.b x0, x0, x0 + cv.sdotup.b x1, x1, x1 + cv.sdotup.b x2, x2, x2 + cv.sdotup.b x8, x8, x8 + cv.sdotup.b x20, x20, x20 + cv.sdotup.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d7dec516ad0e954d6c8f2f25e6669ccb48f263f8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-h-fail.s +#error_output: cv-sdotup-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..cb56228f18c2fe492b5274c4da92625626b85860 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..cff83cba14568ebbe2a8f39b7c43aa21f7325532 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.h x32, x32, x32 + cv.sdotup.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d217a9531965d738b41cce7f2c7b705369842b79 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800007b cv.sdotup.h zero,zero,zero + 4: 981080fb cv.sdotup.h ra,ra,ra + 8: 9821017b cv.sdotup.h sp,sp,sp + c: 9884047b cv.sdotup.h s0,s0,s0 + 10: 994a0a7b cv.sdotup.h s4,s4,s4 + 14: 99ff8ffb cv.sdotup.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..cacaa1cdcb89649900d98b310a0e5bf179548378 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.h x0, x0, x0 + cv.sdotup.h x1, x1, x1 + cv.sdotup.h x2, x2, x2 + cv.sdotup.h x8, x8, x8 + cv.sdotup.h x20, x20, x20 + cv.sdotup.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7cdaab2e6e5649726a9d1c2f339031e11f8337a5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-b-fail.s +#error_output: cv-sdotup-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..79ebb6da0ace5801a176c36038a4dfe946f87c34 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..2fbae1c01b3790ed7826e6846e05e41af78d0bda --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.sc.b x32, x32, x32 + cv.sdotup.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..16d7bbcc7adb56f93828a4c1f9910e17ae37b76a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800507b cv.sdotup.sc.b zero,zero,zero + 4: 9810d0fb cv.sdotup.sc.b ra,ra,ra + 8: 9821517b cv.sdotup.sc.b sp,sp,sp + c: 9884547b cv.sdotup.sc.b s0,s0,s0 + 10: 994a5a7b cv.sdotup.sc.b s4,s4,s4 + 14: 99ffdffb cv.sdotup.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..3164734bea05d59fe73d431c64381c1c8be49a26 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.sc.b x0, x0, x0 + cv.sdotup.sc.b x1, x1, x1 + cv.sdotup.sc.b x2, x2, x2 + cv.sdotup.sc.b x8, x8, x8 + cv.sdotup.sc.b x20, x20, x20 + cv.sdotup.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3f669623dfaaf02aadb930a5a5935e943054be5a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-h-fail.s +#error_output: cv-sdotup-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c770ee8f30dc651dc57bdac193101e5e7cc43801 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotup.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..9fac8b86bd8abef7c8c3a0a9cc949ac403f1ac6a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotup.sc.h x32, x32, x32 + cv.sdotup.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..65ae56d45e069008511d5d9a67e8afb961e22bcc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9800407b cv.sdotup.sc.h zero,zero,zero + 4: 9810c0fb cv.sdotup.sc.h ra,ra,ra + 8: 9821417b cv.sdotup.sc.h sp,sp,sp + c: 9884447b cv.sdotup.sc.h s0,s0,s0 + 10: 994a4a7b cv.sdotup.sc.h s4,s4,s4 + 14: 99ffcffb cv.sdotup.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..605c165e4f53ea991165deba700fad220f79f45f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotup.sc.h x0, x0, x0 + cv.sdotup.sc.h x1, x1, x1 + cv.sdotup.sc.h x2, x2, x2 + cv.sdotup.sc.h x8, x8, x8 + cv.sdotup.sc.h x20, x20, x20 + cv.sdotup.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..38d6910ef12721f5d37f659fcd9ec641b01ae122 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-b-fail.s +#error_output: cv-sdotup-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..59ef235acbdb377d9744237098a434db526a9ee1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sdotup.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b3f13638f7ba28bb6e0a140471abad8798adac32 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotup.sci.b x32, x32, 20 + cv.sdotup.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotup.sci.b x6, x7, -33 + cv.sdotup.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d0137bfd8f6b5614787ac5ec30456359fc993e90 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9940707b cv.sdotup.sci.b zero,zero,20 + 4: 9940f0fb cv.sdotup.sci.b ra,ra,20 + 8: 9941717b cv.sdotup.sci.b sp,sp,20 + c: 9944747b cv.sdotup.sci.b s0,s0,20 + 10: 994a7a7b cv.sdotup.sci.b s4,s4,20 + 14: 994ffffb cv.sdotup.sci.b t6,t6,20 + 18: 9a03f37b cv.sdotup.sci.b t1,t2,-32 + 1c: 9803f37b cv.sdotup.sci.b t1,t2,0 + 20: 99f3f37b cv.sdotup.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..71629e421093e37ff3451a15b47235fcda243fa5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotup.sci.b x0, x0, 20 + cv.sdotup.sci.b x1, x1, 20 + cv.sdotup.sci.b x2, x2, 20 + cv.sdotup.sci.b x8, x8, 20 + cv.sdotup.sci.b x20, x20, 20 + cv.sdotup.sci.b x31, x31, 20 + #Immediate Values Test + cv.sdotup.sci.b x6, x7, -32 + cv.sdotup.sci.b x6, x7, 0 + cv.sdotup.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..6c9fdc096c34fa33927504c466a5cd3953f7d5ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-h-fail.s +#error_output: cv-sdotup-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..88518d8c272e535e23921848372179fe50f4f625 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotup.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sdotup.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..acf23f7b4957e1600a7ede419cae3ba65978cbf2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotup.sci.h x32, x32, 20 + cv.sdotup.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotup.sci.h x6, x7, -33 + cv.sdotup.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ea4790bcf327b0ae0443e88e36482119f0337d74 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotup-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 9940607b cv.sdotup.sci.h zero,zero,20 + 4: 9940e0fb cv.sdotup.sci.h ra,ra,20 + 8: 9941617b cv.sdotup.sci.h sp,sp,20 + c: 9944647b cv.sdotup.sci.h s0,s0,20 + 10: 994a6a7b cv.sdotup.sci.h s4,s4,20 + 14: 994feffb cv.sdotup.sci.h t6,t6,20 + 18: 9a03e37b cv.sdotup.sci.h t1,t2,-32 + 1c: 9803e37b cv.sdotup.sci.h t1,t2,0 + 20: 99f3e37b cv.sdotup.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..72813fb4cb77acd75b813619c1016e93eeb77748 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotup-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotup.sci.h x0, x0, 20 + cv.sdotup.sci.h x1, x1, 20 + cv.sdotup.sci.h x2, x2, 20 + cv.sdotup.sci.h x8, x8, 20 + cv.sdotup.sci.h x20, x20, 20 + cv.sdotup.sci.h x31, x31, 20 + #Immediate Values Test + cv.sdotup.sci.h x6, x7, -32 + cv.sdotup.sci.h x6, x7, 0 + cv.sdotup.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..e49347475aab24f4135f821e3d064949e138d101 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-b-fail.s +#error_output: cv-sdotusp-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7488a3d54a6fd53148b733fca84db7ecb9f97be8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..be0791d85eb61c2b572452704ae75adb713e2a51 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.b x32, x32, x32 + cv.sdotusp.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..100f465159d3d4e3576e280f0a7974c7829700f4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000107b cv.sdotusp.b zero,zero,zero + 4: a01090fb cv.sdotusp.b ra,ra,ra + 8: a021117b cv.sdotusp.b sp,sp,sp + c: a084147b cv.sdotusp.b s0,s0,s0 + 10: a14a1a7b cv.sdotusp.b s4,s4,s4 + 14: a1ff9ffb cv.sdotusp.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..413c4a2f8aa5d4f23c7d2adeb6aeab7179003b02 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.b x0, x0, x0 + cv.sdotusp.b x1, x1, x1 + cv.sdotusp.b x2, x2, x2 + cv.sdotusp.b x8, x8, x8 + cv.sdotusp.b x20, x20, x20 + cv.sdotusp.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..0280c032c8db3910c030092b36a99e878f5023b8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-h-fail.s +#error_output: cv-sdotusp-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..82883936deaf3aec1e208e187a9d2aa4103123f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..403423840fb80073f6171f6ae12d85cff3774204 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.h x32, x32, x32 + cv.sdotusp.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..91a91e0f4afecdfab96234c5d0893ee81f8e3659 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000007b cv.sdotusp.h zero,zero,zero + 4: a01080fb cv.sdotusp.h ra,ra,ra + 8: a021017b cv.sdotusp.h sp,sp,sp + c: a084047b cv.sdotusp.h s0,s0,s0 + 10: a14a0a7b cv.sdotusp.h s4,s4,s4 + 14: a1ff8ffb cv.sdotusp.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4a00c3f01af4dad08383312771582346cf3f7d2e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.h x0, x0, x0 + cv.sdotusp.h x1, x1, x1 + cv.sdotusp.h x2, x2, x2 + cv.sdotusp.h x8, x8, x8 + cv.sdotusp.h x20, x20, x20 + cv.sdotusp.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..cc58c3f07f19b6e778cec976daa6643d479cc72f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-b-fail.s +#error_output: cv-sdotusp-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..0224aea1c52ada1f5a84e4ac5e922dc0450de668 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..535fe4c5eac4df5930d6864388f00688918430b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.sc.b x32, x32, x32 + cv.sdotusp.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..13adb9518ccffb2eeab68fbc9c14ed839afbe2a3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000507b cv.sdotusp.sc.b zero,zero,zero + 4: a010d0fb cv.sdotusp.sc.b ra,ra,ra + 8: a021517b cv.sdotusp.sc.b sp,sp,sp + c: a084547b cv.sdotusp.sc.b s0,s0,s0 + 10: a14a5a7b cv.sdotusp.sc.b s4,s4,s4 + 14: a1ffdffb cv.sdotusp.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..47d539c44dad37823d54e1bb4204f98b04a11a91 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.sc.b x0, x0, x0 + cv.sdotusp.sc.b x1, x1, x1 + cv.sdotusp.sc.b x2, x2, x2 + cv.sdotusp.sc.b x8, x8, x8 + cv.sdotusp.sc.b x20, x20, x20 + cv.sdotusp.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..4ad59775db6585daa9ceaa76294def35b3073ef0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-h-fail.s +#error_output: cv-sdotusp-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..9f55f7dc75ddcac4d2a740aa13e019b17666ea36 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sdotusp.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c4f0263f997992e1fbeaf9f2a293e6436b686e8e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sdotusp.sc.h x32, x32, x32 + cv.sdotusp.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3bb37b741d91da106d34c4c2e7e4535248d17d0e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a000407b cv.sdotusp.sc.h zero,zero,zero + 4: a010c0fb cv.sdotusp.sc.h ra,ra,ra + 8: a021417b cv.sdotusp.sc.h sp,sp,sp + c: a084447b cv.sdotusp.sc.h s0,s0,s0 + 10: a14a4a7b cv.sdotusp.sc.h s4,s4,s4 + 14: a1ffcffb cv.sdotusp.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..789edd107285231ce01f567d65809eaa15eb10ac --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sdotusp.sc.h x0, x0, x0 + cv.sdotusp.sc.h x1, x1, x1 + cv.sdotusp.sc.h x2, x2, x2 + cv.sdotusp.sc.h x8, x8, x8 + cv.sdotusp.sc.h x20, x20, x20 + cv.sdotusp.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..699ff8a151b176569b1217bc81ed154b89996c94 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-b-fail.s +#error_output: cv-sdotusp-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..efd927e7658db95b0edddd58b533c1f24adb2321 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sdotusp.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..121e86bd1f93bb4e47c4d0f706d58c5e515e9259 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotusp.sci.b x32, x32, 20 + cv.sdotusp.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotusp.sci.b x6, x7, -33 + cv.sdotusp.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..9debb0db24ddddc600e5487d9ea1f26eb42d5cf4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a140707b cv.sdotusp.sci.b zero,zero,20 + 4: a140f0fb cv.sdotusp.sci.b ra,ra,20 + 8: a141717b cv.sdotusp.sci.b sp,sp,20 + c: a144747b cv.sdotusp.sci.b s0,s0,20 + 10: a14a7a7b cv.sdotusp.sci.b s4,s4,20 + 14: a14ffffb cv.sdotusp.sci.b t6,t6,20 + 18: a203f37b cv.sdotusp.sci.b t1,t2,-32 + 1c: a003f37b cv.sdotusp.sci.b t1,t2,0 + 20: a1f3f37b cv.sdotusp.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b7be1e357fe56ab597e72f9ef1fb774978e397f2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotusp.sci.b x0, x0, 20 + cv.sdotusp.sci.b x1, x1, 20 + cv.sdotusp.sci.b x2, x2, 20 + cv.sdotusp.sci.b x8, x8, 20 + cv.sdotusp.sci.b x20, x20, 20 + cv.sdotusp.sci.b x31, x31, 20 + #Immediate Values Test + cv.sdotusp.sci.b x6, x7, -32 + cv.sdotusp.sci.b x6, x7, 0 + cv.sdotusp.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..2057999f8f67340547661271e4c42baa8961d672 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-h-fail.s +#error_output: cv-sdotusp-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..abc1063c15d4f067ec1c875761a8e40311712a0e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sdotusp.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sdotusp.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..df2e3e328bdd61cadc71d6a1d3ef22d2d1f20d42 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sdotusp.sci.h x32, x32, 20 + cv.sdotusp.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sdotusp.sci.h x6, x7, -33 + cv.sdotusp.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..57d536bc8b8b761a0515ea0768e068b2e4dc7791 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sdotusp-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: a140607b cv.sdotusp.sci.h zero,zero,20 + 4: a140e0fb cv.sdotusp.sci.h ra,ra,20 + 8: a141617b cv.sdotusp.sci.h sp,sp,20 + c: a144647b cv.sdotusp.sci.h s0,s0,20 + 10: a14a6a7b cv.sdotusp.sci.h s4,s4,20 + 14: a14feffb cv.sdotusp.sci.h t6,t6,20 + 18: a203e37b cv.sdotusp.sci.h t1,t2,-32 + 1c: a003e37b cv.sdotusp.sci.h t1,t2,0 + 20: a1f3e37b cv.sdotusp.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..fd6631e1c9fbb7f36c94ff6d8f2483ccec7d28fd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sdotusp-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sdotusp.sci.h x0, x0, 20 + cv.sdotusp.sci.h x1, x1, 20 + cv.sdotusp.sci.h x2, x2, 20 + cv.sdotusp.sci.h x8, x8, 20 + cv.sdotusp.sci.h x20, x20, 20 + cv.sdotusp.sci.h x31, x31, 20 + #Immediate Values Test + cv.sdotusp.sci.h x6, x7, -32 + cv.sdotusp.sci.h x6, x7, 0 + cv.sdotusp.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-fail.d b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..89c0537333a6cb9d1353a5b26aa80e2915c23d2b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-b-fail.s +#error_output: cv-shuffle-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-fail.l b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..6ccb07a2a9687074978e961607bda228d57d23ca --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle.b x32,x32,x32' +.*: Error: illegal operands `cv.shuffle.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-fail.s b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..f5a24b2af550db632b9de6578a9d2017395dbe6e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle.b x32, x32, x32 + cv.shuffle.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-pass.d b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..242717f219d77830688af7a75f6bb511cfad1571 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c000107b cv.shuffle.b zero,zero,zero + 4: c01090fb cv.shuffle.b ra,ra,ra + 8: c021117b cv.shuffle.b sp,sp,sp + c: c084147b cv.shuffle.b s0,s0,s0 + 10: c14a1a7b cv.shuffle.b s4,s4,s4 + 14: c1ff9ffb cv.shuffle.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-b-pass.s b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e908ad5b1e79ff8475e72972447ed3145a69ae39 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle.b x0, x0, x0 + cv.shuffle.b x1, x1, x1 + cv.shuffle.b x2, x2, x2 + cv.shuffle.b x8, x8, x8 + cv.shuffle.b x20, x20, x20 + cv.shuffle.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-fail.d b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..eb7b53e8b72e3a38f87e667e5721b3e445cf3389 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-h-fail.s +#error_output: cv-shuffle-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-fail.l b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..28004f29675ba9be5cafb57a5f41b69d9f1126c4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle.h x32,x32,x32' +.*: Error: illegal operands `cv.shuffle.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-fail.s b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..91a805eb9456d1e89ba6afb41dc823a67aae0bf0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle.h x32, x32, x32 + cv.shuffle.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-pass.d b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..30ac7fa67622a1fc43e3fb261e938c34f31d3856 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c000007b cv.shuffle.h zero,zero,zero + 4: c01080fb cv.shuffle.h ra,ra,ra + 8: c021017b cv.shuffle.h sp,sp,sp + c: c084047b cv.shuffle.h s0,s0,s0 + 10: c14a0a7b cv.shuffle.h s4,s4,s4 + 14: c1ff8ffb cv.shuffle.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-h-pass.s b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..08afc2bab54c05f8ce6add207cc797c7a27321e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle.h x0, x0, x0 + cv.shuffle.h x1, x1, x1 + cv.shuffle.h x2, x2, x2 + cv.shuffle.h x8, x8, x8 + cv.shuffle.h x20, x20, x20 + cv.shuffle.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..c23adb87e92bd195599b3cb45126a5c1e76112a0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-sci-h-fail.s +#error_output: cv-shuffle-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..abb30d18eac5a197d12e8089c09c2021f95d685a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle.sci.h x32,x32,20' +.*: Error: illegal operands `cv.shuffle.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5095a035ccbae4af5b8d4bd2902162e4d5835a01 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shuffle.sci.h x32, x32, 20 + cv.shuffle.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.shuffle.sci.h x6, x7, -33 + cv.shuffle.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..30e5c4360c03e85eec4d0884639423155e85813e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c140607b cv.shuffle.sci.h zero,zero,20 + 4: c140e0fb cv.shuffle.sci.h ra,ra,20 + 8: c141617b cv.shuffle.sci.h sp,sp,20 + c: c144647b cv.shuffle.sci.h s0,s0,20 + 10: c14a6a7b cv.shuffle.sci.h s4,s4,20 + 14: c14feffb cv.shuffle.sci.h t6,t6,20 + 18: c203e37b cv.shuffle.sci.h t1,t2,-32 + 1c: c003e37b cv.shuffle.sci.h t1,t2,0 + 20: c1f3e37b cv.shuffle.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..01ff538f999110dc4b970ae49dfa45e0bca096d9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shuffle.sci.h x0, x0, 20 + cv.shuffle.sci.h x1, x1, 20 + cv.shuffle.sci.h x2, x2, 20 + cv.shuffle.sci.h x8, x8, 20 + cv.shuffle.sci.h x20, x20, 20 + cv.shuffle.sci.h x31, x31, 20 + #Immediate Values Test + cv.shuffle.sci.h x6, x7, -32 + cv.shuffle.sci.h x6, x7, 0 + cv.shuffle.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..824204ac1cf71d5280bf1b4d9a06e07d7f27f3db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-b-fail.s +#error_output: cv-shuffle2-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..94e47f7f8c762a11b742ae2ecef29025f4dbbed1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle2.b x32,x32,x32' +.*: Error: illegal operands `cv.shuffle2.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..23f1a2596973145068d48666fa73177ad2e21e49 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle2.b x32, x32, x32 + cv.shuffle2.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..2d21409fe2d8ed0dd797b7732ffeeeed1a1539f5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: e000107b cv.shuffle2.b zero,zero,zero + 4: e01090fb cv.shuffle2.b ra,ra,ra + 8: e021117b cv.shuffle2.b sp,sp,sp + c: e084147b cv.shuffle2.b s0,s0,s0 + 10: e14a1a7b cv.shuffle2.b s4,s4,s4 + 14: e1ff9ffb cv.shuffle2.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e4e58940ccc1020b695066fd2f65d3b439cb99c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle2.b x0, x0, x0 + cv.shuffle2.b x1, x1, x1 + cv.shuffle2.b x2, x2, x2 + cv.shuffle2.b x8, x8, x8 + cv.shuffle2.b x20, x20, x20 + cv.shuffle2.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..6ae6bdc180808cd724a1866d66dc4aa034257178 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-h-fail.s +#error_output: cv-shuffle2-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..31b69598bbfe83300fa22f22c7278cce468c06d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shuffle2.h x32,x32,x32' +.*: Error: illegal operands `cv.shuffle2.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..96ba440aa64e23b14dde0dae6089443772cb3e68 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.shuffle2.h x32, x32, x32 + cv.shuffle2.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..307d6b3554d32d6c6732013e602695dd217b2333 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shuffle2-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: e000007b cv.shuffle2.h zero,zero,zero + 4: e01080fb cv.shuffle2.h ra,ra,ra + 8: e021017b cv.shuffle2.h sp,sp,sp + c: e084047b cv.shuffle2.h s0,s0,s0 + 10: e14a0a7b cv.shuffle2.h s4,s4,s4 + 14: e1ff8ffb cv.shuffle2.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..f3a2ba29bf11a0f2684741c0dac9992e7af86354 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shuffle2-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.shuffle2.h x0, x0, x0 + cv.shuffle2.h x1, x1, x1 + cv.shuffle2.h x2, x2, x2 + cv.shuffle2.h x8, x8, x8 + cv.shuffle2.h x20, x20, x20 + cv.shuffle2.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..7e736b6b8b11b875c48b6616892cb535975a450d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei0-sci-b-fail.s +#error_output: cv-shufflei0-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..fb52a536487a7cba012f6442eb03d1545bcc1615 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei0.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei0.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..26c2dcf17e7dfcdffb9cf581745d9c447511c18e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei0.sci.b x32, x32, 20 + cv.shufflei0.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei0.sci.b x6, x7, -33 + cv.shufflei0.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..71ed14ce2109697675588e201d829a4d1d1a5c35 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei0-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c140707b cv.shufflei0.sci.b zero,zero,20 + 4: c140f0fb cv.shufflei0.sci.b ra,ra,20 + 8: c141717b cv.shufflei0.sci.b sp,sp,20 + c: c144747b cv.shufflei0.sci.b s0,s0,20 + 10: c14a7a7b cv.shufflei0.sci.b s4,s4,20 + 14: c14ffffb cv.shufflei0.sci.b t6,t6,20 + 18: c203f37b cv.shufflei0.sci.b t1,t2,-32 + 1c: c003f37b cv.shufflei0.sci.b t1,t2,0 + 20: c1f3f37b cv.shufflei0.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c9d8f466a460d3cac4b02c640b7348623e18ad71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei0-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei0.sci.b x0, x0, 20 + cv.shufflei0.sci.b x1, x1, 20 + cv.shufflei0.sci.b x2, x2, 20 + cv.shufflei0.sci.b x8, x8, 20 + cv.shufflei0.sci.b x20, x20, 20 + cv.shufflei0.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei0.sci.b x6, x7, -32 + cv.shufflei0.sci.b x6, x7, 0 + cv.shufflei0.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..cf94a12cf8623016b56b3cfc62005779f77b5ebb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei1-sci-b-fail.s +#error_output: cv-shufflei1-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..169d3c7aece0592692e7bce59cd9674ce449833e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei1.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei1.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b7ef3dfb6f17a746e4bab56c3344da0a31608dfa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei1.sci.b x32, x32, 20 + cv.shufflei1.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei1.sci.b x6, x7, -33 + cv.shufflei1.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..a28668d6839cb6ab507e68dc6603587f78dee437 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei1-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: c940707b cv.shufflei1.sci.b zero,zero,20 + 4: c940f0fb cv.shufflei1.sci.b ra,ra,20 + 8: c941717b cv.shufflei1.sci.b sp,sp,20 + c: c944747b cv.shufflei1.sci.b s0,s0,20 + 10: c94a7a7b cv.shufflei1.sci.b s4,s4,20 + 14: c94ffffb cv.shufflei1.sci.b t6,t6,20 + 18: ca03f37b cv.shufflei1.sci.b t1,t2,-32 + 1c: c803f37b cv.shufflei1.sci.b t1,t2,0 + 20: c9f3f37b cv.shufflei1.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..baa3cb425d45154aa8dd6e6fab9bc56a9222a4ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei1-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei1.sci.b x0, x0, 20 + cv.shufflei1.sci.b x1, x1, 20 + cv.shufflei1.sci.b x2, x2, 20 + cv.shufflei1.sci.b x8, x8, 20 + cv.shufflei1.sci.b x20, x20, 20 + cv.shufflei1.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei1.sci.b x6, x7, -32 + cv.shufflei1.sci.b x6, x7, 0 + cv.shufflei1.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..33aa9b2f899e6c843346223885ed78bce9ef598a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei2-sci-b-fail.s +#error_output: cv-shufflei2-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..590f202b88e27beafdf80d3edac087544f332363 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei2.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei2.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..bad60f50862a2422cee79c6a28834c5d9451ca46 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei2.sci.b x32, x32, 20 + cv.shufflei2.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei2.sci.b x6, x7, -33 + cv.shufflei2.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b4c0d294109d0830e053555f4020c016315818b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei2-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: d140707b cv.shufflei2.sci.b zero,zero,20 + 4: d140f0fb cv.shufflei2.sci.b ra,ra,20 + 8: d141717b cv.shufflei2.sci.b sp,sp,20 + c: d144747b cv.shufflei2.sci.b s0,s0,20 + 10: d14a7a7b cv.shufflei2.sci.b s4,s4,20 + 14: d14ffffb cv.shufflei2.sci.b t6,t6,20 + 18: d203f37b cv.shufflei2.sci.b t1,t2,-32 + 1c: d003f37b cv.shufflei2.sci.b t1,t2,0 + 20: d1f3f37b cv.shufflei2.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..0f46dae4e14af45e05e3a33f477cb5b617045c0b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei2-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei2.sci.b x0, x0, 20 + cv.shufflei2.sci.b x1, x1, 20 + cv.shufflei2.sci.b x2, x2, 20 + cv.shufflei2.sci.b x8, x8, 20 + cv.shufflei2.sci.b x20, x20, 20 + cv.shufflei2.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei2.sci.b x6, x7, -32 + cv.shufflei2.sci.b x6, x7, 0 + cv.shufflei2.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..c8ee036ed97f0eec7a78e45becd68e5dbd8f8f8a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei3-sci-b-fail.s +#error_output: cv-shufflei3-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..159e85df289de122c79934a901d3f790d980dad0 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.shufflei3.sci.b x32,x32,20' +.*: Error: illegal operands `cv.shufflei3.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0908a1b04f8b2fb28b9b9941023354442712c87c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.shufflei3.sci.b x32, x32, 20 + cv.shufflei3.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.shufflei3.sci.b x6, x7, -33 + cv.shufflei3.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..7b9603c4dce3071dcd0ff5a7fee4464503bde182 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-shufflei3-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: d940707b cv.shufflei3.sci.b zero,zero,20 + 4: d940f0fb cv.shufflei3.sci.b ra,ra,20 + 8: d941717b cv.shufflei3.sci.b sp,sp,20 + c: d944747b cv.shufflei3.sci.b s0,s0,20 + 10: d94a7a7b cv.shufflei3.sci.b s4,s4,20 + 14: d94ffffb cv.shufflei3.sci.b t6,t6,20 + 18: da03f37b cv.shufflei3.sci.b t1,t2,-32 + 1c: d803f37b cv.shufflei3.sci.b t1,t2,0 + 20: d9f3f37b cv.shufflei3.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..086e8935215f82169219170d9c73c6caeca45921 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-shufflei3-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.shufflei3.sci.b x0, x0, 20 + cv.shufflei3.sci.b x1, x1, 20 + cv.shufflei3.sci.b x2, x2, 20 + cv.shufflei3.sci.b x8, x8, 20 + cv.shufflei3.sci.b x20, x20, 20 + cv.shufflei3.sci.b x31, x31, 20 + #Immediate Values Test + cv.shufflei3.sci.b x6, x7, -32 + cv.shufflei3.sci.b x6, x7, 0 + cv.shufflei3.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.d b/gas/testsuite/gas/riscv/cv-simd-march-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..4ae0a97b4cea44a3d391272d8bee8329716b1fe7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: cv-simd-march-fail.s +#error_output: cv-simd-march-fail.l diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.l b/gas/testsuite/gas/riscv/cv-simd-march-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..efebaa5208b9f70323c0312a32fce32a69e0b31e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.l @@ -0,0 +1,221 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `cv.add.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avg.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.avgu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.min.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.minu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.max.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.maxu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.srl.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sra.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sll.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.or.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.xor.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.and.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.abs.h x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.abs.b x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotup.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotusp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.dotsp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotup.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotusp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sdotsp.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extract.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extract.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extractu.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.extractu.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.insert.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.insert.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei0.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei1.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei2.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shufflei3.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle2.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.shuffle2.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.pack x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.pack.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.packhi.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.packlo.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpeq.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpne.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgt.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpge.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmplt.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmple.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgtu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpgeu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpltu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sc.h x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sc.b x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sci.h x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cmpleu.sci.b x6,x7,20', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.r.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxmul.i.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.cplxconj x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.subrotmj.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.add.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.div2 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.div4 x5,x6,x7', extension `xcorevsimd' or `xcorev' required +.*: Error: unrecognized opcode `cv.sub.div8 x5,x6,x7', extension `xcorevsimd' or `xcorev' required diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.s b/gas/testsuite/gas/riscv/cv-simd-march-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a63586918cd81769edafec3188ca1e142fca38ae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.s @@ -0,0 +1,221 @@ +target: + cv.add.h x5, x6, x7 + cv.add.b x5, x6, x7 + cv.add.sc.h x5, x6, x7 + cv.add.sc.b x5, x6, x7 + cv.add.sci.h x6, x7, 20 + cv.add.sci.b x6, x7, 20 + cv.sub.h x5, x6, x7 + cv.sub.b x5, x6, x7 + cv.sub.sc.h x5, x6, x7 + cv.sub.sc.b x5, x6, x7 + cv.sub.sci.h x6, x7, 20 + cv.sub.sci.b x6, x7, 20 + cv.avg.h x5, x6, x7 + cv.avg.b x5, x6, x7 + cv.avg.sc.h x5, x6, x7 + cv.avg.sc.b x5, x6, x7 + cv.avg.sci.h x6, x7, 20 + cv.avg.sci.b x6, x7, 20 + cv.avgu.h x5, x6, x7 + cv.avgu.b x5, x6, x7 + cv.avgu.sc.h x5, x6, x7 + cv.avgu.sc.b x5, x6, x7 + cv.avgu.sci.h x6, x7, 20 + cv.avgu.sci.b x6, x7, 20 + cv.min.h x5, x6, x7 + cv.min.b x5, x6, x7 + cv.min.sc.h x5, x6, x7 + cv.min.sc.b x5, x6, x7 + cv.min.sci.h x6, x7, 20 + cv.min.sci.b x6, x7, 20 + cv.minu.h x5, x6, x7 + cv.minu.b x5, x6, x7 + cv.minu.sc.h x5, x6, x7 + cv.minu.sc.b x5, x6, x7 + cv.minu.sci.h x6, x7, 20 + cv.minu.sci.b x6, x7, 20 + cv.max.h x5, x6, x7 + cv.max.b x5, x6, x7 + cv.max.sc.h x5, x6, x7 + cv.max.sc.b x5, x6, x7 + cv.max.sci.h x6, x7, 20 + cv.max.sci.b x6, x7, 20 + cv.maxu.h x5, x6, x7 + cv.maxu.b x5, x6, x7 + cv.maxu.sc.h x5, x6, x7 + cv.maxu.sc.b x5, x6, x7 + cv.maxu.sci.h x6, x7, 20 + cv.maxu.sci.b x6, x7, 20 + cv.srl.h x5, x6, x7 + cv.srl.b x5, x6, x7 + cv.srl.sc.h x5, x6, x7 + cv.srl.sc.b x5, x6, x7 + cv.srl.sci.h x6, x7, 20 + cv.srl.sci.b x6, x7, 20 + cv.sra.h x5, x6, x7 + cv.sra.b x5, x6, x7 + cv.sra.sc.h x5, x6, x7 + cv.sra.sc.b x5, x6, x7 + cv.sra.sci.h x6, x7, 20 + cv.sra.sci.b x6, x7, 20 + cv.sll.h x5, x6, x7 + cv.sll.b x5, x6, x7 + cv.sll.sc.h x5, x6, x7 + cv.sll.sc.b x5, x6, x7 + cv.sll.sci.h x6, x7, 20 + cv.sll.sci.b x6, x7, 20 + cv.or.h x5, x6, x7 + cv.or.b x5, x6, x7 + cv.or.sc.h x5, x6, x7 + cv.or.sc.b x5, x6, x7 + cv.or.sci.h x6, x7, 20 + cv.or.sci.b x6, x7, 20 + cv.xor.h x5, x6, x7 + cv.xor.b x5, x6, x7 + cv.xor.sc.h x5, x6, x7 + cv.xor.sc.b x5, x6, x7 + cv.xor.sci.h x6, x7, 20 + cv.xor.sci.b x6, x7, 20 + cv.and.h x5, x6, x7 + cv.and.b x5, x6, x7 + cv.and.sc.h x5, x6, x7 + cv.and.sc.b x5, x6, x7 + cv.and.sci.h x6, x7, 20 + cv.and.sci.b x6, x7, 20 + cv.abs.h x6, x7 + cv.abs.b x6, x7 + cv.dotup.h x5, x6, x7 + cv.dotup.b x5, x6, x7 + cv.dotup.sc.h x5, x6, x7 + cv.dotup.sc.b x5, x6, x7 + cv.dotup.sci.h x6, x7, 20 + cv.dotup.sci.b x6, x7, 20 + cv.dotusp.h x5, x6, x7 + cv.dotusp.b x5, x6, x7 + cv.dotusp.sc.h x5, x6, x7 + cv.dotusp.sc.b x5, x6, x7 + cv.dotusp.sci.h x6, x7, 20 + cv.dotusp.sci.b x6, x7, 20 + cv.dotsp.h x5, x6, x7 + cv.dotsp.b x5, x6, x7 + cv.dotsp.sc.h x5, x6, x7 + cv.dotsp.sc.b x5, x6, x7 + cv.dotsp.sci.h x6, x7, 20 + cv.dotsp.sci.b x6, x7, 20 + cv.sdotup.h x5, x6, x7 + cv.sdotup.b x5, x6, x7 + cv.sdotup.sc.h x5, x6, x7 + cv.sdotup.sc.b x5, x6, x7 + cv.sdotup.sci.h x6, x7, 20 + cv.sdotup.sci.b x6, x7, 20 + cv.sdotusp.h x5, x6, x7 + cv.sdotusp.b x5, x6, x7 + cv.sdotusp.sc.h x5, x6, x7 + cv.sdotusp.sc.b x5, x6, x7 + cv.sdotusp.sci.h x6, x7, 20 + cv.sdotusp.sci.b x6, x7, 20 + cv.sdotsp.h x5, x6, x7 + cv.sdotsp.b x5, x6, x7 + cv.sdotsp.sc.h x5, x6, x7 + cv.sdotsp.sc.b x5, x6, x7 + cv.sdotsp.sci.h x6, x7, 20 + cv.sdotsp.sci.b x6, x7, 20 + cv.extract.h x6, x7, 20 + cv.extract.b x6, x7, 20 + cv.extractu.h x6, x7, 20 + cv.extractu.b x6, x7, 20 + cv.insert.h x6, x7, 20 + cv.insert.b x6, x7, 20 + cv.shuffle.h x5, x6, x7 + cv.shuffle.b x5, x6, x7 + cv.shuffle.sci.h x6, x7, 20 + cv.shufflei0.sci.b x6, x7, 20 + cv.shufflei1.sci.b x6, x7, 20 + cv.shufflei2.sci.b x6, x7, 20 + cv.shufflei3.sci.b x6, x7, 20 + cv.shuffle2.h x5, x6, x7 + cv.shuffle2.b x5, x6, x7 + cv.pack x5, x6, x7 + cv.pack.h x5, x6, x7 + cv.packhi.b x5, x6, x7 + cv.packlo.b x5, x6, x7 + cv.cmpeq.h x5, x6, x7 + cv.cmpeq.b x5, x6, x7 + cv.cmpeq.sc.h x5, x6, x7 + cv.cmpeq.sc.b x5, x6, x7 + cv.cmpeq.sci.h x6, x7, 20 + cv.cmpeq.sci.b x6, x7, 20 + cv.cmpne.h x5, x6, x7 + cv.cmpne.b x5, x6, x7 + cv.cmpne.sc.h x5, x6, x7 + cv.cmpne.sc.b x5, x6, x7 + cv.cmpne.sci.h x6, x7, 20 + cv.cmpne.sci.b x6, x7, 20 + cv.cmpgt.h x5, x6, x7 + cv.cmpgt.b x5, x6, x7 + cv.cmpgt.sc.h x5, x6, x7 + cv.cmpgt.sc.b x5, x6, x7 + cv.cmpgt.sci.h x6, x7, 20 + cv.cmpgt.sci.b x6, x7, 20 + cv.cmpge.h x5, x6, x7 + cv.cmpge.b x5, x6, x7 + cv.cmpge.sc.h x5, x6, x7 + cv.cmpge.sc.b x5, x6, x7 + cv.cmpge.sci.h x6, x7, 20 + cv.cmpge.sci.b x6, x7, 20 + cv.cmplt.h x5, x6, x7 + cv.cmplt.b x5, x6, x7 + cv.cmplt.sc.h x5, x6, x7 + cv.cmplt.sc.b x5, x6, x7 + cv.cmplt.sci.h x6, x7, 20 + cv.cmplt.sci.b x6, x7, 20 + cv.cmple.h x5, x6, x7 + cv.cmple.b x5, x6, x7 + cv.cmple.sc.h x5, x6, x7 + cv.cmple.sc.b x5, x6, x7 + cv.cmple.sci.h x6, x7, 20 + cv.cmple.sci.b x6, x7, 20 + cv.cmpgtu.h x5, x6, x7 + cv.cmpgtu.b x5, x6, x7 + cv.cmpgtu.sc.h x5, x6, x7 + cv.cmpgtu.sc.b x5, x6, x7 + cv.cmpgtu.sci.h x6, x7, 20 + cv.cmpgtu.sci.b x6, x7, 20 + cv.cmpgeu.h x5, x6, x7 + cv.cmpgeu.b x5, x6, x7 + cv.cmpgeu.sc.h x5, x6, x7 + cv.cmpgeu.sc.b x5, x6, x7 + cv.cmpgeu.sci.h x6, x7, 20 + cv.cmpgeu.sci.b x6, x7, 20 + cv.cmpltu.h x5, x6, x7 + cv.cmpltu.b x5, x6, x7 + cv.cmpltu.sc.h x5, x6, x7 + cv.cmpltu.sc.b x5, x6, x7 + cv.cmpltu.sci.h x6, x7, 20 + cv.cmpltu.sci.b x6, x7, 20 + cv.cmpleu.h x5, x6, x7 + cv.cmpleu.b x5, x6, x7 + cv.cmpleu.sc.h x5, x6, x7 + cv.cmpleu.sc.b x5, x6, x7 + cv.cmpleu.sci.h x6, x7, 20 + cv.cmpleu.sci.b x6, x7, 20 + cv.cplxmul.r x5, x6, x7 + cv.cplxmul.i x5, x6, x7 + cv.cplxmul.r.div2 x5, x6, x7 + cv.cplxmul.i.div2 x5, x6, x7 + cv.cplxmul.r.div4 x5, x6, x7 + cv.cplxmul.i.div4 x5, x6, x7 + cv.cplxmul.r.div8 x5, x6, x7 + cv.cplxmul.i.div8 x5, x6, x7 + cv.cplxconj x6, x7 + cv.subrotmj x5, x6, x7 + cv.subrotmj.div2 x5, x6, x7 + cv.subrotmj.div4 x5, x6, x7 + cv.subrotmj.div8 x5, x6, x7 + cv.add.div2 x5, x6, x7 + cv.add.div4 x5, x6, x7 + cv.add.div8 x5, x6, x7 + cv.sub.div2 x5, x6, x7 + cv.sub.div4 x5, x6, x7 + cv.sub.div8 x5, x6, x7 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorev.d b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.d new file mode 100644 index 0000000000000000000000000000000000000000..fd2437b0bed2222a8e471f9f6b626aa597c87348 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.d @@ -0,0 +1,230 @@ +#as: -march=rv32i_xcorev1p0 +#source: cv-simd-march-xcorev.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+007302fb[ ]+cv.add.h t0,t1,t2 +[ ]+4:[ ]+007312fb[ ]+cv.add.b t0,t1,t2 +[ ]+8:[ ]+007342fb[ ]+cv.add.sc.h t0,t1,t2 +[ ]+c:[ ]+007352fb[ ]+cv.add.sc.b t0,t1,t2 +[ ]+10:[ ]+0143e37b[ ]+cv.add.sci.h t1,t2,20 +[ ]+14:[ ]+0143f37b[ ]+cv.add.sci.b t1,t2,20 +[ ]+18:[ ]+087302fb[ ]+cv.sub.h t0,t1,t2 +[ ]+1c:[ ]+087312fb[ ]+cv.sub.b t0,t1,t2 +[ ]+20:[ ]+087342fb[ ]+cv.sub.sc.h t0,t1,t2 +[ ]+24:[ ]+087352fb[ ]+cv.sub.sc.b t0,t1,t2 +[ ]+28:[ ]+0943e37b[ ]+cv.sub.sci.h t1,t2,20 +[ ]+2c:[ ]+0943f37b[ ]+cv.sub.sci.b t1,t2,20 +[ ]+30:[ ]+107302fb[ ]+cv.avg.h t0,t1,t2 +[ ]+34:[ ]+107312fb[ ]+cv.avg.b t0,t1,t2 +[ ]+38:[ ]+107342fb[ ]+cv.avg.sc.h t0,t1,t2 +[ ]+3c:[ ]+107352fb[ ]+cv.avg.sc.b t0,t1,t2 +[ ]+40:[ ]+1143e37b[ ]+cv.avg.sci.h t1,t2,20 +[ ]+44:[ ]+1143f37b[ ]+cv.avg.sci.b t1,t2,20 +[ ]+48:[ ]+187302fb[ ]+cv.avgu.h t0,t1,t2 +[ ]+4c:[ ]+187312fb[ ]+cv.avgu.b t0,t1,t2 +[ ]+50:[ ]+187342fb[ ]+cv.avgu.sc.h t0,t1,t2 +[ ]+54:[ ]+187352fb[ ]+cv.avgu.sc.b t0,t1,t2 +[ ]+58:[ ]+1943e37b[ ]+cv.avgu.sci.h t1,t2,20 +[ ]+5c:[ ]+1943f37b[ ]+cv.avgu.sci.b t1,t2,20 +[ ]+60:[ ]+207302fb[ ]+cv.min.h t0,t1,t2 +[ ]+64:[ ]+207312fb[ ]+cv.min.b t0,t1,t2 +[ ]+68:[ ]+207342fb[ ]+cv.min.sc.h t0,t1,t2 +[ ]+6c:[ ]+207352fb[ ]+cv.min.sc.b t0,t1,t2 +[ ]+70:[ ]+2143e37b[ ]+cv.min.sci.h t1,t2,20 +[ ]+74:[ ]+2143f37b[ ]+cv.min.sci.b t1,t2,20 +[ ]+78:[ ]+287302fb[ ]+cv.minu.h t0,t1,t2 +[ ]+7c:[ ]+287312fb[ ]+cv.minu.b t0,t1,t2 +[ ]+80:[ ]+287342fb[ ]+cv.minu.sc.h t0,t1,t2 +[ ]+84:[ ]+287352fb[ ]+cv.minu.sc.b t0,t1,t2 +[ ]+88:[ ]+2943e37b[ ]+cv.minu.sci.h t1,t2,20 +[ ]+8c:[ ]+2943f37b[ ]+cv.minu.sci.b t1,t2,20 +[ ]+90:[ ]+307302fb[ ]+cv.max.h t0,t1,t2 +[ ]+94:[ ]+307312fb[ ]+cv.max.b t0,t1,t2 +[ ]+98:[ ]+307342fb[ ]+cv.max.sc.h t0,t1,t2 +[ ]+9c:[ ]+307352fb[ ]+cv.max.sc.b t0,t1,t2 +[ ]+a0:[ ]+3143e37b[ ]+cv.max.sci.h t1,t2,20 +[ ]+a4:[ ]+3143f37b[ ]+cv.max.sci.b t1,t2,20 +[ ]+a8:[ ]+387302fb[ ]+cv.maxu.h t0,t1,t2 +[ ]+ac:[ ]+387312fb[ ]+cv.maxu.b t0,t1,t2 +[ ]+b0:[ ]+387342fb[ ]+cv.maxu.sc.h t0,t1,t2 +[ ]+b4:[ ]+387352fb[ ]+cv.maxu.sc.b t0,t1,t2 +[ ]+b8:[ ]+3943e37b[ ]+cv.maxu.sci.h t1,t2,20 +[ ]+bc:[ ]+3943f37b[ ]+cv.maxu.sci.b t1,t2,20 +[ ]+c0:[ ]+407302fb[ ]+cv.srl.h t0,t1,t2 +[ ]+c4:[ ]+407312fb[ ]+cv.srl.b t0,t1,t2 +[ ]+c8:[ ]+407342fb[ ]+cv.srl.sc.h t0,t1,t2 +[ ]+cc:[ ]+407352fb[ ]+cv.srl.sc.b t0,t1,t2 +[ ]+d0:[ ]+4143e37b[ ]+cv.srl.sci.h t1,t2,20 +[ ]+d4:[ ]+4143f37b[ ]+cv.srl.sci.b t1,t2,20 +[ ]+d8:[ ]+487302fb[ ]+cv.sra.h t0,t1,t2 +[ ]+dc:[ ]+487312fb[ ]+cv.sra.b t0,t1,t2 +[ ]+e0:[ ]+487342fb[ ]+cv.sra.sc.h t0,t1,t2 +[ ]+e4:[ ]+487352fb[ ]+cv.sra.sc.b t0,t1,t2 +[ ]+e8:[ ]+4943e37b[ ]+cv.sra.sci.h t1,t2,20 +[ ]+ec:[ ]+4943f37b[ ]+cv.sra.sci.b t1,t2,20 +[ ]+f0:[ ]+507302fb[ ]+cv.sll.h t0,t1,t2 +[ ]+f4:[ ]+507312fb[ ]+cv.sll.b t0,t1,t2 +[ ]+f8:[ ]+507342fb[ ]+cv.sll.sc.h t0,t1,t2 +[ ]+fc:[ ]+507352fb[ ]+cv.sll.sc.b t0,t1,t2 +[ ]+100:[ ]+5143e37b[ ]+cv.sll.sci.h t1,t2,20 +[ ]+104:[ ]+5143f37b[ ]+cv.sll.sci.b t1,t2,20 +[ ]+108:[ ]+587302fb[ ]+cv.or.h t0,t1,t2 +[ ]+10c:[ ]+587312fb[ ]+cv.or.b t0,t1,t2 +[ ]+110:[ ]+587342fb[ ]+cv.or.sc.h t0,t1,t2 +[ ]+114:[ ]+587352fb[ ]+cv.or.sc.b t0,t1,t2 +[ ]+118:[ ]+5943e37b[ ]+cv.or.sci.h t1,t2,20 +[ ]+11c:[ ]+5943f37b[ ]+cv.or.sci.b t1,t2,20 +[ ]+120:[ ]+607302fb[ ]+cv.xor.h t0,t1,t2 +[ ]+124:[ ]+607312fb[ ]+cv.xor.b t0,t1,t2 +[ ]+128:[ ]+607342fb[ ]+cv.xor.sc.h t0,t1,t2 +[ ]+12c:[ ]+607352fb[ ]+cv.xor.sc.b t0,t1,t2 +[ ]+130:[ ]+6143e37b[ ]+cv.xor.sci.h t1,t2,20 +[ ]+134:[ ]+6143f37b[ ]+cv.xor.sci.b t1,t2,20 +[ ]+138:[ ]+687302fb[ ]+cv.and.h t0,t1,t2 +[ ]+13c:[ ]+687312fb[ ]+cv.and.b t0,t1,t2 +[ ]+140:[ ]+687342fb[ ]+cv.and.sc.h t0,t1,t2 +[ ]+144:[ ]+687352fb[ ]+cv.and.sc.b t0,t1,t2 +[ ]+148:[ ]+6943e37b[ ]+cv.and.sci.h t1,t2,20 +[ ]+14c:[ ]+6943f37b[ ]+cv.and.sci.b t1,t2,20 +[ ]+150:[ ]+7003837b[ ]+cv.abs.h t1,t2 +[ ]+154:[ ]+7003937b[ ]+cv.abs.b t1,t2 +[ ]+158:[ ]+807302fb[ ]+cv.dotup.h t0,t1,t2 +[ ]+15c:[ ]+807312fb[ ]+cv.dotup.b t0,t1,t2 +[ ]+160:[ ]+807342fb[ ]+cv.dotup.sc.h t0,t1,t2 +[ ]+164:[ ]+807352fb[ ]+cv.dotup.sc.b t0,t1,t2 +[ ]+168:[ ]+8143e37b[ ]+cv.dotup.sci.h t1,t2,20 +[ ]+16c:[ ]+8143f37b[ ]+cv.dotup.sci.b t1,t2,20 +[ ]+170:[ ]+887302fb[ ]+cv.dotusp.h t0,t1,t2 +[ ]+174:[ ]+887312fb[ ]+cv.dotusp.b t0,t1,t2 +[ ]+178:[ ]+887342fb[ ]+cv.dotusp.sc.h t0,t1,t2 +[ ]+17c:[ ]+887352fb[ ]+cv.dotusp.sc.b t0,t1,t2 +[ ]+180:[ ]+8943e37b[ ]+cv.dotusp.sci.h t1,t2,20 +[ ]+184:[ ]+8943f37b[ ]+cv.dotusp.sci.b t1,t2,20 +[ ]+188:[ ]+907302fb[ ]+cv.dotsp.h t0,t1,t2 +[ ]+18c:[ ]+907312fb[ ]+cv.dotsp.b t0,t1,t2 +[ ]+190:[ ]+907342fb[ ]+cv.dotsp.sc.h t0,t1,t2 +[ ]+194:[ ]+907352fb[ ]+cv.dotsp.sc.b t0,t1,t2 +[ ]+198:[ ]+9143e37b[ ]+cv.dotsp.sci.h t1,t2,20 +[ ]+19c:[ ]+9143f37b[ ]+cv.dotsp.sci.b t1,t2,20 +[ ]+1a0:[ ]+987302fb[ ]+cv.sdotup.h t0,t1,t2 +[ ]+1a4:[ ]+987312fb[ ]+cv.sdotup.b t0,t1,t2 +[ ]+1a8:[ ]+987342fb[ ]+cv.sdotup.sc.h t0,t1,t2 +[ ]+1ac:[ ]+987352fb[ ]+cv.sdotup.sc.b t0,t1,t2 +[ ]+1b0:[ ]+9943e37b[ ]+cv.sdotup.sci.h t1,t2,20 +[ ]+1b4:[ ]+9943f37b[ ]+cv.sdotup.sci.b t1,t2,20 +[ ]+1b8:[ ]+a07302fb[ ]+cv.sdotusp.h t0,t1,t2 +[ ]+1bc:[ ]+a07312fb[ ]+cv.sdotusp.b t0,t1,t2 +[ ]+1c0:[ ]+a07342fb[ ]+cv.sdotusp.sc.h t0,t1,t2 +[ ]+1c4:[ ]+a07352fb[ ]+cv.sdotusp.sc.b t0,t1,t2 +[ ]+1c8:[ ]+a143e37b[ ]+cv.sdotusp.sci.h t1,t2,20 +[ ]+1cc:[ ]+a143f37b[ ]+cv.sdotusp.sci.b t1,t2,20 +[ ]+1d0:[ ]+a87302fb[ ]+cv.sdotsp.h t0,t1,t2 +[ ]+1d4:[ ]+a87312fb[ ]+cv.sdotsp.b t0,t1,t2 +[ ]+1d8:[ ]+a87342fb[ ]+cv.sdotsp.sc.h t0,t1,t2 +[ ]+1dc:[ ]+a87352fb[ ]+cv.sdotsp.sc.b t0,t1,t2 +[ ]+1e0:[ ]+a943e37b[ ]+cv.sdotsp.sci.h t1,t2,20 +[ ]+1e4:[ ]+a943f37b[ ]+cv.sdotsp.sci.b t1,t2,20 +[ ]+1e8:[ ]+b943837b[ ]+cv.extract.h t1,t2,20 +[ ]+1ec:[ ]+b943937b[ ]+cv.extract.b t1,t2,20 +[ ]+1f0:[ ]+b943a37b[ ]+cv.extractu.h t1,t2,20 +[ ]+1f4:[ ]+b943b37b[ ]+cv.extractu.b t1,t2,20 +[ ]+1f8:[ ]+b943c37b[ ]+cv.insert.h t1,t2,20 +[ ]+1fc:[ ]+b943d37b[ ]+cv.insert.b t1,t2,20 +[ ]+200:[ ]+c07302fb[ ]+cv.shuffle.h t0,t1,t2 +[ ]+204:[ ]+c07312fb[ ]+cv.shuffle.b t0,t1,t2 +[ ]+208:[ ]+c143e37b[ ]+cv.shuffle.sci.h t1,t2,20 +[ ]+20c:[ ]+c143f37b[ ]+cv.shufflei0.sci.b t1,t2,20 +[ ]+210:[ ]+c943f37b[ ]+cv.shufflei1.sci.b t1,t2,20 +[ ]+214:[ ]+d143f37b[ ]+cv.shufflei2.sci.b t1,t2,20 +[ ]+218:[ ]+d943f37b[ ]+cv.shufflei3.sci.b t1,t2,20 +[ ]+21c:[ ]+e07302fb[ ]+cv.shuffle2.h t0,t1,t2 +[ ]+220:[ ]+e07312fb[ ]+cv.shuffle2.b t0,t1,t2 +[ ]+224:[ ]+f07302fb[ ]+cv.pack t0,t1,t2 +[ ]+228:[ ]+f27302fb[ ]+cv.pack.h t0,t1,t2 +[ ]+22c:[ ]+fa7312fb[ ]+cv.packhi.b t0,t1,t2 +[ ]+230:[ ]+f87312fb[ ]+cv.packlo.b t0,t1,t2 +[ ]+234:[ ]+047302fb[ ]+cv.cmpeq.h t0,t1,t2 +[ ]+238:[ ]+047312fb[ ]+cv.cmpeq.b t0,t1,t2 +[ ]+23c:[ ]+047342fb[ ]+cv.cmpeq.sc.h t0,t1,t2 +[ ]+240:[ ]+047352fb[ ]+cv.cmpeq.sc.b t0,t1,t2 +[ ]+244:[ ]+0543e37b[ ]+cv.cmpeq.sci.h t1,t2,20 +[ ]+248:[ ]+0543f37b[ ]+cv.cmpeq.sci.b t1,t2,20 +[ ]+24c:[ ]+0c7302fb[ ]+cv.cmpne.h t0,t1,t2 +[ ]+250:[ ]+0c7312fb[ ]+cv.cmpne.b t0,t1,t2 +[ ]+254:[ ]+0c7342fb[ ]+cv.cmpne.sc.h t0,t1,t2 +[ ]+258:[ ]+0c7352fb[ ]+cv.cmpne.sc.b t0,t1,t2 +[ ]+25c:[ ]+0d43e37b[ ]+cv.cmpne.sci.h t1,t2,20 +[ ]+260:[ ]+0d43f37b[ ]+cv.cmpne.sci.b t1,t2,20 +[ ]+264:[ ]+147302fb[ ]+cv.cmpgt.h t0,t1,t2 +[ ]+268:[ ]+147312fb[ ]+cv.cmpgt.b t0,t1,t2 +[ ]+26c:[ ]+147342fb[ ]+cv.cmpgt.sc.h t0,t1,t2 +[ ]+270:[ ]+147352fb[ ]+cv.cmpgt.sc.b t0,t1,t2 +[ ]+274:[ ]+1543e37b[ ]+cv.cmpgt.sci.h t1,t2,20 +[ ]+278:[ ]+1543f37b[ ]+cv.cmpgt.sci.b t1,t2,20 +[ ]+27c:[ ]+1c7302fb[ ]+cv.cmpge.h t0,t1,t2 +[ ]+280:[ ]+1c7312fb[ ]+cv.cmpge.b t0,t1,t2 +[ ]+284:[ ]+1c7342fb[ ]+cv.cmpge.sc.h t0,t1,t2 +[ ]+288:[ ]+1c7352fb[ ]+cv.cmpge.sc.b t0,t1,t2 +[ ]+28c:[ ]+1d43e37b[ ]+cv.cmpge.sci.h t1,t2,20 +[ ]+290:[ ]+1d43f37b[ ]+cv.cmpge.sci.b t1,t2,20 +[ ]+294:[ ]+247302fb[ ]+cv.cmplt.h t0,t1,t2 +[ ]+298:[ ]+247312fb[ ]+cv.cmplt.b t0,t1,t2 +[ ]+29c:[ ]+247342fb[ ]+cv.cmplt.sc.h t0,t1,t2 +[ ]+2a0:[ ]+247352fb[ ]+cv.cmplt.sc.b t0,t1,t2 +[ ]+2a4:[ ]+2543e37b[ ]+cv.cmplt.sci.h t1,t2,20 +[ ]+2a8:[ ]+2543f37b[ ]+cv.cmplt.sci.b t1,t2,20 +[ ]+2ac:[ ]+2c7302fb[ ]+cv.cmple.h t0,t1,t2 +[ ]+2b0:[ ]+2c7312fb[ ]+cv.cmple.b t0,t1,t2 +[ ]+2b4:[ ]+2c7342fb[ ]+cv.cmple.sc.h t0,t1,t2 +[ ]+2b8:[ ]+2c7352fb[ ]+cv.cmple.sc.b t0,t1,t2 +[ ]+2bc:[ ]+2d43e37b[ ]+cv.cmple.sci.h t1,t2,20 +[ ]+2c0:[ ]+2d43f37b[ ]+cv.cmple.sci.b t1,t2,20 +[ ]+2c4:[ ]+347302fb[ ]+cv.cmpgtu.h t0,t1,t2 +[ ]+2c8:[ ]+347312fb[ ]+cv.cmpgtu.b t0,t1,t2 +[ ]+2cc:[ ]+347342fb[ ]+cv.cmpgtu.sc.h t0,t1,t2 +[ ]+2d0:[ ]+347352fb[ ]+cv.cmpgtu.sc.b t0,t1,t2 +[ ]+2d4:[ ]+3543e37b[ ]+cv.cmpgtu.sci.h t1,t2,20 +[ ]+2d8:[ ]+3543f37b[ ]+cv.cmpgtu.sci.b t1,t2,20 +[ ]+2dc:[ ]+3c7302fb[ ]+cv.cmpgeu.h t0,t1,t2 +[ ]+2e0:[ ]+3c7312fb[ ]+cv.cmpgeu.b t0,t1,t2 +[ ]+2e4:[ ]+3c7342fb[ ]+cv.cmpgeu.sc.h t0,t1,t2 +[ ]+2e8:[ ]+3c7352fb[ ]+cv.cmpgeu.sc.b t0,t1,t2 +[ ]+2ec:[ ]+3d43e37b[ ]+cv.cmpgeu.sci.h t1,t2,20 +[ ]+2f0:[ ]+3d43f37b[ ]+cv.cmpgeu.sci.b t1,t2,20 +[ ]+2f4:[ ]+447302fb[ ]+cv.cmpltu.h t0,t1,t2 +[ ]+2f8:[ ]+447312fb[ ]+cv.cmpltu.b t0,t1,t2 +[ ]+2fc:[ ]+447342fb[ ]+cv.cmpltu.sc.h t0,t1,t2 +[ ]+300:[ ]+447352fb[ ]+cv.cmpltu.sc.b t0,t1,t2 +[ ]+304:[ ]+4543e37b[ ]+cv.cmpltu.sci.h t1,t2,20 +[ ]+308:[ ]+4543f37b[ ]+cv.cmpltu.sci.b t1,t2,20 +[ ]+30c:[ ]+4c7302fb[ ]+cv.cmpleu.h t0,t1,t2 +[ ]+310:[ ]+4c7312fb[ ]+cv.cmpleu.b t0,t1,t2 +[ ]+314:[ ]+4c7342fb[ ]+cv.cmpleu.sc.h t0,t1,t2 +[ ]+318:[ ]+4c7352fb[ ]+cv.cmpleu.sc.b t0,t1,t2 +[ ]+31c:[ ]+4d43e37b[ ]+cv.cmpleu.sci.h t1,t2,20 +[ ]+320:[ ]+4d43f37b[ ]+cv.cmpleu.sci.b t1,t2,20 +[ ]+324:[ ]+547302fb[ ]+cv.cplxmul.r t0,t1,t2 +[ ]+328:[ ]+567302fb[ ]+cv.cplxmul.i t0,t1,t2 +[ ]+32c:[ ]+547322fb[ ]+cv.cplxmul.r.div2 t0,t1,t2 +[ ]+330:[ ]+567322fb[ ]+cv.cplxmul.i.div2 t0,t1,t2 +[ ]+334:[ ]+547342fb[ ]+cv.cplxmul.r.div4 t0,t1,t2 +[ ]+338:[ ]+567342fb[ ]+cv.cplxmul.i.div4 t0,t1,t2 +[ ]+33c:[ ]+547362fb[ ]+cv.cplxmul.r.div8 t0,t1,t2 +[ ]+340:[ ]+567362fb[ ]+cv.cplxmul.i.div8 t0,t1,t2 +[ ]+344:[ ]+5c03837b[ ]+cv.cplxconj t1,t2 +[ ]+348:[ ]+647302fb[ ]+cv.subrotmj t0,t1,t2 +[ ]+34c:[ ]+647322fb[ ]+cv.subrotmj.div2 t0,t1,t2 +[ ]+350:[ ]+647342fb[ ]+cv.subrotmj.div4 t0,t1,t2 +[ ]+354:[ ]+647362fb[ ]+cv.subrotmj.div8 t0,t1,t2 +[ ]+358:[ ]+6c7322fb[ ]+cv.add.div2 t0,t1,t2 +[ ]+35c:[ ]+6c7342fb[ ]+cv.add.div4 t0,t1,t2 +[ ]+360:[ ]+6c7362fb[ ]+cv.add.div8 t0,t1,t2 +[ ]+364:[ ]+747322fb[ ]+cv.sub.div2 t0,t1,t2 +[ ]+368:[ ]+747342fb[ ]+cv.sub.div4 t0,t1,t2 +[ ]+36c:[ ]+747362fb[ ]+cv.sub.div8 t0,t1,t2 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorev.s b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.s new file mode 100644 index 0000000000000000000000000000000000000000..a63586918cd81769edafec3188ca1e142fca38ae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorev.s @@ -0,0 +1,221 @@ +target: + cv.add.h x5, x6, x7 + cv.add.b x5, x6, x7 + cv.add.sc.h x5, x6, x7 + cv.add.sc.b x5, x6, x7 + cv.add.sci.h x6, x7, 20 + cv.add.sci.b x6, x7, 20 + cv.sub.h x5, x6, x7 + cv.sub.b x5, x6, x7 + cv.sub.sc.h x5, x6, x7 + cv.sub.sc.b x5, x6, x7 + cv.sub.sci.h x6, x7, 20 + cv.sub.sci.b x6, x7, 20 + cv.avg.h x5, x6, x7 + cv.avg.b x5, x6, x7 + cv.avg.sc.h x5, x6, x7 + cv.avg.sc.b x5, x6, x7 + cv.avg.sci.h x6, x7, 20 + cv.avg.sci.b x6, x7, 20 + cv.avgu.h x5, x6, x7 + cv.avgu.b x5, x6, x7 + cv.avgu.sc.h x5, x6, x7 + cv.avgu.sc.b x5, x6, x7 + cv.avgu.sci.h x6, x7, 20 + cv.avgu.sci.b x6, x7, 20 + cv.min.h x5, x6, x7 + cv.min.b x5, x6, x7 + cv.min.sc.h x5, x6, x7 + cv.min.sc.b x5, x6, x7 + cv.min.sci.h x6, x7, 20 + cv.min.sci.b x6, x7, 20 + cv.minu.h x5, x6, x7 + cv.minu.b x5, x6, x7 + cv.minu.sc.h x5, x6, x7 + cv.minu.sc.b x5, x6, x7 + cv.minu.sci.h x6, x7, 20 + cv.minu.sci.b x6, x7, 20 + cv.max.h x5, x6, x7 + cv.max.b x5, x6, x7 + cv.max.sc.h x5, x6, x7 + cv.max.sc.b x5, x6, x7 + cv.max.sci.h x6, x7, 20 + cv.max.sci.b x6, x7, 20 + cv.maxu.h x5, x6, x7 + cv.maxu.b x5, x6, x7 + cv.maxu.sc.h x5, x6, x7 + cv.maxu.sc.b x5, x6, x7 + cv.maxu.sci.h x6, x7, 20 + cv.maxu.sci.b x6, x7, 20 + cv.srl.h x5, x6, x7 + cv.srl.b x5, x6, x7 + cv.srl.sc.h x5, x6, x7 + cv.srl.sc.b x5, x6, x7 + cv.srl.sci.h x6, x7, 20 + cv.srl.sci.b x6, x7, 20 + cv.sra.h x5, x6, x7 + cv.sra.b x5, x6, x7 + cv.sra.sc.h x5, x6, x7 + cv.sra.sc.b x5, x6, x7 + cv.sra.sci.h x6, x7, 20 + cv.sra.sci.b x6, x7, 20 + cv.sll.h x5, x6, x7 + cv.sll.b x5, x6, x7 + cv.sll.sc.h x5, x6, x7 + cv.sll.sc.b x5, x6, x7 + cv.sll.sci.h x6, x7, 20 + cv.sll.sci.b x6, x7, 20 + cv.or.h x5, x6, x7 + cv.or.b x5, x6, x7 + cv.or.sc.h x5, x6, x7 + cv.or.sc.b x5, x6, x7 + cv.or.sci.h x6, x7, 20 + cv.or.sci.b x6, x7, 20 + cv.xor.h x5, x6, x7 + cv.xor.b x5, x6, x7 + cv.xor.sc.h x5, x6, x7 + cv.xor.sc.b x5, x6, x7 + cv.xor.sci.h x6, x7, 20 + cv.xor.sci.b x6, x7, 20 + cv.and.h x5, x6, x7 + cv.and.b x5, x6, x7 + cv.and.sc.h x5, x6, x7 + cv.and.sc.b x5, x6, x7 + cv.and.sci.h x6, x7, 20 + cv.and.sci.b x6, x7, 20 + cv.abs.h x6, x7 + cv.abs.b x6, x7 + cv.dotup.h x5, x6, x7 + cv.dotup.b x5, x6, x7 + cv.dotup.sc.h x5, x6, x7 + cv.dotup.sc.b x5, x6, x7 + cv.dotup.sci.h x6, x7, 20 + cv.dotup.sci.b x6, x7, 20 + cv.dotusp.h x5, x6, x7 + cv.dotusp.b x5, x6, x7 + cv.dotusp.sc.h x5, x6, x7 + cv.dotusp.sc.b x5, x6, x7 + cv.dotusp.sci.h x6, x7, 20 + cv.dotusp.sci.b x6, x7, 20 + cv.dotsp.h x5, x6, x7 + cv.dotsp.b x5, x6, x7 + cv.dotsp.sc.h x5, x6, x7 + cv.dotsp.sc.b x5, x6, x7 + cv.dotsp.sci.h x6, x7, 20 + cv.dotsp.sci.b x6, x7, 20 + cv.sdotup.h x5, x6, x7 + cv.sdotup.b x5, x6, x7 + cv.sdotup.sc.h x5, x6, x7 + cv.sdotup.sc.b x5, x6, x7 + cv.sdotup.sci.h x6, x7, 20 + cv.sdotup.sci.b x6, x7, 20 + cv.sdotusp.h x5, x6, x7 + cv.sdotusp.b x5, x6, x7 + cv.sdotusp.sc.h x5, x6, x7 + cv.sdotusp.sc.b x5, x6, x7 + cv.sdotusp.sci.h x6, x7, 20 + cv.sdotusp.sci.b x6, x7, 20 + cv.sdotsp.h x5, x6, x7 + cv.sdotsp.b x5, x6, x7 + cv.sdotsp.sc.h x5, x6, x7 + cv.sdotsp.sc.b x5, x6, x7 + cv.sdotsp.sci.h x6, x7, 20 + cv.sdotsp.sci.b x6, x7, 20 + cv.extract.h x6, x7, 20 + cv.extract.b x6, x7, 20 + cv.extractu.h x6, x7, 20 + cv.extractu.b x6, x7, 20 + cv.insert.h x6, x7, 20 + cv.insert.b x6, x7, 20 + cv.shuffle.h x5, x6, x7 + cv.shuffle.b x5, x6, x7 + cv.shuffle.sci.h x6, x7, 20 + cv.shufflei0.sci.b x6, x7, 20 + cv.shufflei1.sci.b x6, x7, 20 + cv.shufflei2.sci.b x6, x7, 20 + cv.shufflei3.sci.b x6, x7, 20 + cv.shuffle2.h x5, x6, x7 + cv.shuffle2.b x5, x6, x7 + cv.pack x5, x6, x7 + cv.pack.h x5, x6, x7 + cv.packhi.b x5, x6, x7 + cv.packlo.b x5, x6, x7 + cv.cmpeq.h x5, x6, x7 + cv.cmpeq.b x5, x6, x7 + cv.cmpeq.sc.h x5, x6, x7 + cv.cmpeq.sc.b x5, x6, x7 + cv.cmpeq.sci.h x6, x7, 20 + cv.cmpeq.sci.b x6, x7, 20 + cv.cmpne.h x5, x6, x7 + cv.cmpne.b x5, x6, x7 + cv.cmpne.sc.h x5, x6, x7 + cv.cmpne.sc.b x5, x6, x7 + cv.cmpne.sci.h x6, x7, 20 + cv.cmpne.sci.b x6, x7, 20 + cv.cmpgt.h x5, x6, x7 + cv.cmpgt.b x5, x6, x7 + cv.cmpgt.sc.h x5, x6, x7 + cv.cmpgt.sc.b x5, x6, x7 + cv.cmpgt.sci.h x6, x7, 20 + cv.cmpgt.sci.b x6, x7, 20 + cv.cmpge.h x5, x6, x7 + cv.cmpge.b x5, x6, x7 + cv.cmpge.sc.h x5, x6, x7 + cv.cmpge.sc.b x5, x6, x7 + cv.cmpge.sci.h x6, x7, 20 + cv.cmpge.sci.b x6, x7, 20 + cv.cmplt.h x5, x6, x7 + cv.cmplt.b x5, x6, x7 + cv.cmplt.sc.h x5, x6, x7 + cv.cmplt.sc.b x5, x6, x7 + cv.cmplt.sci.h x6, x7, 20 + cv.cmplt.sci.b x6, x7, 20 + cv.cmple.h x5, x6, x7 + cv.cmple.b x5, x6, x7 + cv.cmple.sc.h x5, x6, x7 + cv.cmple.sc.b x5, x6, x7 + cv.cmple.sci.h x6, x7, 20 + cv.cmple.sci.b x6, x7, 20 + cv.cmpgtu.h x5, x6, x7 + cv.cmpgtu.b x5, x6, x7 + cv.cmpgtu.sc.h x5, x6, x7 + cv.cmpgtu.sc.b x5, x6, x7 + cv.cmpgtu.sci.h x6, x7, 20 + cv.cmpgtu.sci.b x6, x7, 20 + cv.cmpgeu.h x5, x6, x7 + cv.cmpgeu.b x5, x6, x7 + cv.cmpgeu.sc.h x5, x6, x7 + cv.cmpgeu.sc.b x5, x6, x7 + cv.cmpgeu.sci.h x6, x7, 20 + cv.cmpgeu.sci.b x6, x7, 20 + cv.cmpltu.h x5, x6, x7 + cv.cmpltu.b x5, x6, x7 + cv.cmpltu.sc.h x5, x6, x7 + cv.cmpltu.sc.b x5, x6, x7 + cv.cmpltu.sci.h x6, x7, 20 + cv.cmpltu.sci.b x6, x7, 20 + cv.cmpleu.h x5, x6, x7 + cv.cmpleu.b x5, x6, x7 + cv.cmpleu.sc.h x5, x6, x7 + cv.cmpleu.sc.b x5, x6, x7 + cv.cmpleu.sci.h x6, x7, 20 + cv.cmpleu.sci.b x6, x7, 20 + cv.cplxmul.r x5, x6, x7 + cv.cplxmul.i x5, x6, x7 + cv.cplxmul.r.div2 x5, x6, x7 + cv.cplxmul.i.div2 x5, x6, x7 + cv.cplxmul.r.div4 x5, x6, x7 + cv.cplxmul.i.div4 x5, x6, x7 + cv.cplxmul.r.div8 x5, x6, x7 + cv.cplxmul.i.div8 x5, x6, x7 + cv.cplxconj x6, x7 + cv.subrotmj x5, x6, x7 + cv.subrotmj.div2 x5, x6, x7 + cv.subrotmj.div4 x5, x6, x7 + cv.subrotmj.div8 x5, x6, x7 + cv.add.div2 x5, x6, x7 + cv.add.div4 x5, x6, x7 + cv.add.div8 x5, x6, x7 + cv.sub.div2 x5, x6, x7 + cv.sub.div4 x5, x6, x7 + cv.sub.div8 x5, x6, x7 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d new file mode 100644 index 0000000000000000000000000000000000000000..470a10e1af67e942a880cb602427c8fc6be907b7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.d @@ -0,0 +1,230 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-simd-march-xcorevsimd.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+007302fb[ ]+cv.add.h t0,t1,t2 +[ ]+4:[ ]+007312fb[ ]+cv.add.b t0,t1,t2 +[ ]+8:[ ]+007342fb[ ]+cv.add.sc.h t0,t1,t2 +[ ]+c:[ ]+007352fb[ ]+cv.add.sc.b t0,t1,t2 +[ ]+10:[ ]+0143e37b[ ]+cv.add.sci.h t1,t2,20 +[ ]+14:[ ]+0143f37b[ ]+cv.add.sci.b t1,t2,20 +[ ]+18:[ ]+087302fb[ ]+cv.sub.h t0,t1,t2 +[ ]+1c:[ ]+087312fb[ ]+cv.sub.b t0,t1,t2 +[ ]+20:[ ]+087342fb[ ]+cv.sub.sc.h t0,t1,t2 +[ ]+24:[ ]+087352fb[ ]+cv.sub.sc.b t0,t1,t2 +[ ]+28:[ ]+0943e37b[ ]+cv.sub.sci.h t1,t2,20 +[ ]+2c:[ ]+0943f37b[ ]+cv.sub.sci.b t1,t2,20 +[ ]+30:[ ]+107302fb[ ]+cv.avg.h t0,t1,t2 +[ ]+34:[ ]+107312fb[ ]+cv.avg.b t0,t1,t2 +[ ]+38:[ ]+107342fb[ ]+cv.avg.sc.h t0,t1,t2 +[ ]+3c:[ ]+107352fb[ ]+cv.avg.sc.b t0,t1,t2 +[ ]+40:[ ]+1143e37b[ ]+cv.avg.sci.h t1,t2,20 +[ ]+44:[ ]+1143f37b[ ]+cv.avg.sci.b t1,t2,20 +[ ]+48:[ ]+187302fb[ ]+cv.avgu.h t0,t1,t2 +[ ]+4c:[ ]+187312fb[ ]+cv.avgu.b t0,t1,t2 +[ ]+50:[ ]+187342fb[ ]+cv.avgu.sc.h t0,t1,t2 +[ ]+54:[ ]+187352fb[ ]+cv.avgu.sc.b t0,t1,t2 +[ ]+58:[ ]+1943e37b[ ]+cv.avgu.sci.h t1,t2,20 +[ ]+5c:[ ]+1943f37b[ ]+cv.avgu.sci.b t1,t2,20 +[ ]+60:[ ]+207302fb[ ]+cv.min.h t0,t1,t2 +[ ]+64:[ ]+207312fb[ ]+cv.min.b t0,t1,t2 +[ ]+68:[ ]+207342fb[ ]+cv.min.sc.h t0,t1,t2 +[ ]+6c:[ ]+207352fb[ ]+cv.min.sc.b t0,t1,t2 +[ ]+70:[ ]+2143e37b[ ]+cv.min.sci.h t1,t2,20 +[ ]+74:[ ]+2143f37b[ ]+cv.min.sci.b t1,t2,20 +[ ]+78:[ ]+287302fb[ ]+cv.minu.h t0,t1,t2 +[ ]+7c:[ ]+287312fb[ ]+cv.minu.b t0,t1,t2 +[ ]+80:[ ]+287342fb[ ]+cv.minu.sc.h t0,t1,t2 +[ ]+84:[ ]+287352fb[ ]+cv.minu.sc.b t0,t1,t2 +[ ]+88:[ ]+2943e37b[ ]+cv.minu.sci.h t1,t2,20 +[ ]+8c:[ ]+2943f37b[ ]+cv.minu.sci.b t1,t2,20 +[ ]+90:[ ]+307302fb[ ]+cv.max.h t0,t1,t2 +[ ]+94:[ ]+307312fb[ ]+cv.max.b t0,t1,t2 +[ ]+98:[ ]+307342fb[ ]+cv.max.sc.h t0,t1,t2 +[ ]+9c:[ ]+307352fb[ ]+cv.max.sc.b t0,t1,t2 +[ ]+a0:[ ]+3143e37b[ ]+cv.max.sci.h t1,t2,20 +[ ]+a4:[ ]+3143f37b[ ]+cv.max.sci.b t1,t2,20 +[ ]+a8:[ ]+387302fb[ ]+cv.maxu.h t0,t1,t2 +[ ]+ac:[ ]+387312fb[ ]+cv.maxu.b t0,t1,t2 +[ ]+b0:[ ]+387342fb[ ]+cv.maxu.sc.h t0,t1,t2 +[ ]+b4:[ ]+387352fb[ ]+cv.maxu.sc.b t0,t1,t2 +[ ]+b8:[ ]+3943e37b[ ]+cv.maxu.sci.h t1,t2,20 +[ ]+bc:[ ]+3943f37b[ ]+cv.maxu.sci.b t1,t2,20 +[ ]+c0:[ ]+407302fb[ ]+cv.srl.h t0,t1,t2 +[ ]+c4:[ ]+407312fb[ ]+cv.srl.b t0,t1,t2 +[ ]+c8:[ ]+407342fb[ ]+cv.srl.sc.h t0,t1,t2 +[ ]+cc:[ ]+407352fb[ ]+cv.srl.sc.b t0,t1,t2 +[ ]+d0:[ ]+4143e37b[ ]+cv.srl.sci.h t1,t2,20 +[ ]+d4:[ ]+4143f37b[ ]+cv.srl.sci.b t1,t2,20 +[ ]+d8:[ ]+487302fb[ ]+cv.sra.h t0,t1,t2 +[ ]+dc:[ ]+487312fb[ ]+cv.sra.b t0,t1,t2 +[ ]+e0:[ ]+487342fb[ ]+cv.sra.sc.h t0,t1,t2 +[ ]+e4:[ ]+487352fb[ ]+cv.sra.sc.b t0,t1,t2 +[ ]+e8:[ ]+4943e37b[ ]+cv.sra.sci.h t1,t2,20 +[ ]+ec:[ ]+4943f37b[ ]+cv.sra.sci.b t1,t2,20 +[ ]+f0:[ ]+507302fb[ ]+cv.sll.h t0,t1,t2 +[ ]+f4:[ ]+507312fb[ ]+cv.sll.b t0,t1,t2 +[ ]+f8:[ ]+507342fb[ ]+cv.sll.sc.h t0,t1,t2 +[ ]+fc:[ ]+507352fb[ ]+cv.sll.sc.b t0,t1,t2 +[ ]+100:[ ]+5143e37b[ ]+cv.sll.sci.h t1,t2,20 +[ ]+104:[ ]+5143f37b[ ]+cv.sll.sci.b t1,t2,20 +[ ]+108:[ ]+587302fb[ ]+cv.or.h t0,t1,t2 +[ ]+10c:[ ]+587312fb[ ]+cv.or.b t0,t1,t2 +[ ]+110:[ ]+587342fb[ ]+cv.or.sc.h t0,t1,t2 +[ ]+114:[ ]+587352fb[ ]+cv.or.sc.b t0,t1,t2 +[ ]+118:[ ]+5943e37b[ ]+cv.or.sci.h t1,t2,20 +[ ]+11c:[ ]+5943f37b[ ]+cv.or.sci.b t1,t2,20 +[ ]+120:[ ]+607302fb[ ]+cv.xor.h t0,t1,t2 +[ ]+124:[ ]+607312fb[ ]+cv.xor.b t0,t1,t2 +[ ]+128:[ ]+607342fb[ ]+cv.xor.sc.h t0,t1,t2 +[ ]+12c:[ ]+607352fb[ ]+cv.xor.sc.b t0,t1,t2 +[ ]+130:[ ]+6143e37b[ ]+cv.xor.sci.h t1,t2,20 +[ ]+134:[ ]+6143f37b[ ]+cv.xor.sci.b t1,t2,20 +[ ]+138:[ ]+687302fb[ ]+cv.and.h t0,t1,t2 +[ ]+13c:[ ]+687312fb[ ]+cv.and.b t0,t1,t2 +[ ]+140:[ ]+687342fb[ ]+cv.and.sc.h t0,t1,t2 +[ ]+144:[ ]+687352fb[ ]+cv.and.sc.b t0,t1,t2 +[ ]+148:[ ]+6943e37b[ ]+cv.and.sci.h t1,t2,20 +[ ]+14c:[ ]+6943f37b[ ]+cv.and.sci.b t1,t2,20 +[ ]+150:[ ]+7003837b[ ]+cv.abs.h t1,t2 +[ ]+154:[ ]+7003937b[ ]+cv.abs.b t1,t2 +[ ]+158:[ ]+807302fb[ ]+cv.dotup.h t0,t1,t2 +[ ]+15c:[ ]+807312fb[ ]+cv.dotup.b t0,t1,t2 +[ ]+160:[ ]+807342fb[ ]+cv.dotup.sc.h t0,t1,t2 +[ ]+164:[ ]+807352fb[ ]+cv.dotup.sc.b t0,t1,t2 +[ ]+168:[ ]+8143e37b[ ]+cv.dotup.sci.h t1,t2,20 +[ ]+16c:[ ]+8143f37b[ ]+cv.dotup.sci.b t1,t2,20 +[ ]+170:[ ]+887302fb[ ]+cv.dotusp.h t0,t1,t2 +[ ]+174:[ ]+887312fb[ ]+cv.dotusp.b t0,t1,t2 +[ ]+178:[ ]+887342fb[ ]+cv.dotusp.sc.h t0,t1,t2 +[ ]+17c:[ ]+887352fb[ ]+cv.dotusp.sc.b t0,t1,t2 +[ ]+180:[ ]+8943e37b[ ]+cv.dotusp.sci.h t1,t2,20 +[ ]+184:[ ]+8943f37b[ ]+cv.dotusp.sci.b t1,t2,20 +[ ]+188:[ ]+907302fb[ ]+cv.dotsp.h t0,t1,t2 +[ ]+18c:[ ]+907312fb[ ]+cv.dotsp.b t0,t1,t2 +[ ]+190:[ ]+907342fb[ ]+cv.dotsp.sc.h t0,t1,t2 +[ ]+194:[ ]+907352fb[ ]+cv.dotsp.sc.b t0,t1,t2 +[ ]+198:[ ]+9143e37b[ ]+cv.dotsp.sci.h t1,t2,20 +[ ]+19c:[ ]+9143f37b[ ]+cv.dotsp.sci.b t1,t2,20 +[ ]+1a0:[ ]+987302fb[ ]+cv.sdotup.h t0,t1,t2 +[ ]+1a4:[ ]+987312fb[ ]+cv.sdotup.b t0,t1,t2 +[ ]+1a8:[ ]+987342fb[ ]+cv.sdotup.sc.h t0,t1,t2 +[ ]+1ac:[ ]+987352fb[ ]+cv.sdotup.sc.b t0,t1,t2 +[ ]+1b0:[ ]+9943e37b[ ]+cv.sdotup.sci.h t1,t2,20 +[ ]+1b4:[ ]+9943f37b[ ]+cv.sdotup.sci.b t1,t2,20 +[ ]+1b8:[ ]+a07302fb[ ]+cv.sdotusp.h t0,t1,t2 +[ ]+1bc:[ ]+a07312fb[ ]+cv.sdotusp.b t0,t1,t2 +[ ]+1c0:[ ]+a07342fb[ ]+cv.sdotusp.sc.h t0,t1,t2 +[ ]+1c4:[ ]+a07352fb[ ]+cv.sdotusp.sc.b t0,t1,t2 +[ ]+1c8:[ ]+a143e37b[ ]+cv.sdotusp.sci.h t1,t2,20 +[ ]+1cc:[ ]+a143f37b[ ]+cv.sdotusp.sci.b t1,t2,20 +[ ]+1d0:[ ]+a87302fb[ ]+cv.sdotsp.h t0,t1,t2 +[ ]+1d4:[ ]+a87312fb[ ]+cv.sdotsp.b t0,t1,t2 +[ ]+1d8:[ ]+a87342fb[ ]+cv.sdotsp.sc.h t0,t1,t2 +[ ]+1dc:[ ]+a87352fb[ ]+cv.sdotsp.sc.b t0,t1,t2 +[ ]+1e0:[ ]+a943e37b[ ]+cv.sdotsp.sci.h t1,t2,20 +[ ]+1e4:[ ]+a943f37b[ ]+cv.sdotsp.sci.b t1,t2,20 +[ ]+1e8:[ ]+b943837b[ ]+cv.extract.h t1,t2,20 +[ ]+1ec:[ ]+b943937b[ ]+cv.extract.b t1,t2,20 +[ ]+1f0:[ ]+b943a37b[ ]+cv.extractu.h t1,t2,20 +[ ]+1f4:[ ]+b943b37b[ ]+cv.extractu.b t1,t2,20 +[ ]+1f8:[ ]+b943c37b[ ]+cv.insert.h t1,t2,20 +[ ]+1fc:[ ]+b943d37b[ ]+cv.insert.b t1,t2,20 +[ ]+200:[ ]+c07302fb[ ]+cv.shuffle.h t0,t1,t2 +[ ]+204:[ ]+c07312fb[ ]+cv.shuffle.b t0,t1,t2 +[ ]+208:[ ]+c143e37b[ ]+cv.shuffle.sci.h t1,t2,20 +[ ]+20c:[ ]+c143f37b[ ]+cv.shufflei0.sci.b t1,t2,20 +[ ]+210:[ ]+c943f37b[ ]+cv.shufflei1.sci.b t1,t2,20 +[ ]+214:[ ]+d143f37b[ ]+cv.shufflei2.sci.b t1,t2,20 +[ ]+218:[ ]+d943f37b[ ]+cv.shufflei3.sci.b t1,t2,20 +[ ]+21c:[ ]+e07302fb[ ]+cv.shuffle2.h t0,t1,t2 +[ ]+220:[ ]+e07312fb[ ]+cv.shuffle2.b t0,t1,t2 +[ ]+224:[ ]+f07302fb[ ]+cv.pack t0,t1,t2 +[ ]+228:[ ]+f27302fb[ ]+cv.pack.h t0,t1,t2 +[ ]+22c:[ ]+fa7312fb[ ]+cv.packhi.b t0,t1,t2 +[ ]+230:[ ]+f87312fb[ ]+cv.packlo.b t0,t1,t2 +[ ]+234:[ ]+047302fb[ ]+cv.cmpeq.h t0,t1,t2 +[ ]+238:[ ]+047312fb[ ]+cv.cmpeq.b t0,t1,t2 +[ ]+23c:[ ]+047342fb[ ]+cv.cmpeq.sc.h t0,t1,t2 +[ ]+240:[ ]+047352fb[ ]+cv.cmpeq.sc.b t0,t1,t2 +[ ]+244:[ ]+0543e37b[ ]+cv.cmpeq.sci.h t1,t2,20 +[ ]+248:[ ]+0543f37b[ ]+cv.cmpeq.sci.b t1,t2,20 +[ ]+24c:[ ]+0c7302fb[ ]+cv.cmpne.h t0,t1,t2 +[ ]+250:[ ]+0c7312fb[ ]+cv.cmpne.b t0,t1,t2 +[ ]+254:[ ]+0c7342fb[ ]+cv.cmpne.sc.h t0,t1,t2 +[ ]+258:[ ]+0c7352fb[ ]+cv.cmpne.sc.b t0,t1,t2 +[ ]+25c:[ ]+0d43e37b[ ]+cv.cmpne.sci.h t1,t2,20 +[ ]+260:[ ]+0d43f37b[ ]+cv.cmpne.sci.b t1,t2,20 +[ ]+264:[ ]+147302fb[ ]+cv.cmpgt.h t0,t1,t2 +[ ]+268:[ ]+147312fb[ ]+cv.cmpgt.b t0,t1,t2 +[ ]+26c:[ ]+147342fb[ ]+cv.cmpgt.sc.h t0,t1,t2 +[ ]+270:[ ]+147352fb[ ]+cv.cmpgt.sc.b t0,t1,t2 +[ ]+274:[ ]+1543e37b[ ]+cv.cmpgt.sci.h t1,t2,20 +[ ]+278:[ ]+1543f37b[ ]+cv.cmpgt.sci.b t1,t2,20 +[ ]+27c:[ ]+1c7302fb[ ]+cv.cmpge.h t0,t1,t2 +[ ]+280:[ ]+1c7312fb[ ]+cv.cmpge.b t0,t1,t2 +[ ]+284:[ ]+1c7342fb[ ]+cv.cmpge.sc.h t0,t1,t2 +[ ]+288:[ ]+1c7352fb[ ]+cv.cmpge.sc.b t0,t1,t2 +[ ]+28c:[ ]+1d43e37b[ ]+cv.cmpge.sci.h t1,t2,20 +[ ]+290:[ ]+1d43f37b[ ]+cv.cmpge.sci.b t1,t2,20 +[ ]+294:[ ]+247302fb[ ]+cv.cmplt.h t0,t1,t2 +[ ]+298:[ ]+247312fb[ ]+cv.cmplt.b t0,t1,t2 +[ ]+29c:[ ]+247342fb[ ]+cv.cmplt.sc.h t0,t1,t2 +[ ]+2a0:[ ]+247352fb[ ]+cv.cmplt.sc.b t0,t1,t2 +[ ]+2a4:[ ]+2543e37b[ ]+cv.cmplt.sci.h t1,t2,20 +[ ]+2a8:[ ]+2543f37b[ ]+cv.cmplt.sci.b t1,t2,20 +[ ]+2ac:[ ]+2c7302fb[ ]+cv.cmple.h t0,t1,t2 +[ ]+2b0:[ ]+2c7312fb[ ]+cv.cmple.b t0,t1,t2 +[ ]+2b4:[ ]+2c7342fb[ ]+cv.cmple.sc.h t0,t1,t2 +[ ]+2b8:[ ]+2c7352fb[ ]+cv.cmple.sc.b t0,t1,t2 +[ ]+2bc:[ ]+2d43e37b[ ]+cv.cmple.sci.h t1,t2,20 +[ ]+2c0:[ ]+2d43f37b[ ]+cv.cmple.sci.b t1,t2,20 +[ ]+2c4:[ ]+347302fb[ ]+cv.cmpgtu.h t0,t1,t2 +[ ]+2c8:[ ]+347312fb[ ]+cv.cmpgtu.b t0,t1,t2 +[ ]+2cc:[ ]+347342fb[ ]+cv.cmpgtu.sc.h t0,t1,t2 +[ ]+2d0:[ ]+347352fb[ ]+cv.cmpgtu.sc.b t0,t1,t2 +[ ]+2d4:[ ]+3543e37b[ ]+cv.cmpgtu.sci.h t1,t2,20 +[ ]+2d8:[ ]+3543f37b[ ]+cv.cmpgtu.sci.b t1,t2,20 +[ ]+2dc:[ ]+3c7302fb[ ]+cv.cmpgeu.h t0,t1,t2 +[ ]+2e0:[ ]+3c7312fb[ ]+cv.cmpgeu.b t0,t1,t2 +[ ]+2e4:[ ]+3c7342fb[ ]+cv.cmpgeu.sc.h t0,t1,t2 +[ ]+2e8:[ ]+3c7352fb[ ]+cv.cmpgeu.sc.b t0,t1,t2 +[ ]+2ec:[ ]+3d43e37b[ ]+cv.cmpgeu.sci.h t1,t2,20 +[ ]+2f0:[ ]+3d43f37b[ ]+cv.cmpgeu.sci.b t1,t2,20 +[ ]+2f4:[ ]+447302fb[ ]+cv.cmpltu.h t0,t1,t2 +[ ]+2f8:[ ]+447312fb[ ]+cv.cmpltu.b t0,t1,t2 +[ ]+2fc:[ ]+447342fb[ ]+cv.cmpltu.sc.h t0,t1,t2 +[ ]+300:[ ]+447352fb[ ]+cv.cmpltu.sc.b t0,t1,t2 +[ ]+304:[ ]+4543e37b[ ]+cv.cmpltu.sci.h t1,t2,20 +[ ]+308:[ ]+4543f37b[ ]+cv.cmpltu.sci.b t1,t2,20 +[ ]+30c:[ ]+4c7302fb[ ]+cv.cmpleu.h t0,t1,t2 +[ ]+310:[ ]+4c7312fb[ ]+cv.cmpleu.b t0,t1,t2 +[ ]+314:[ ]+4c7342fb[ ]+cv.cmpleu.sc.h t0,t1,t2 +[ ]+318:[ ]+4c7352fb[ ]+cv.cmpleu.sc.b t0,t1,t2 +[ ]+31c:[ ]+4d43e37b[ ]+cv.cmpleu.sci.h t1,t2,20 +[ ]+320:[ ]+4d43f37b[ ]+cv.cmpleu.sci.b t1,t2,20 +[ ]+324:[ ]+547302fb[ ]+cv.cplxmul.r t0,t1,t2 +[ ]+328:[ ]+567302fb[ ]+cv.cplxmul.i t0,t1,t2 +[ ]+32c:[ ]+547322fb[ ]+cv.cplxmul.r.div2 t0,t1,t2 +[ ]+330:[ ]+567322fb[ ]+cv.cplxmul.i.div2 t0,t1,t2 +[ ]+334:[ ]+547342fb[ ]+cv.cplxmul.r.div4 t0,t1,t2 +[ ]+338:[ ]+567342fb[ ]+cv.cplxmul.i.div4 t0,t1,t2 +[ ]+33c:[ ]+547362fb[ ]+cv.cplxmul.r.div8 t0,t1,t2 +[ ]+340:[ ]+567362fb[ ]+cv.cplxmul.i.div8 t0,t1,t2 +[ ]+344:[ ]+5c03837b[ ]+cv.cplxconj t1,t2 +[ ]+348:[ ]+647302fb[ ]+cv.subrotmj t0,t1,t2 +[ ]+34c:[ ]+647322fb[ ]+cv.subrotmj.div2 t0,t1,t2 +[ ]+350:[ ]+647342fb[ ]+cv.subrotmj.div4 t0,t1,t2 +[ ]+354:[ ]+647362fb[ ]+cv.subrotmj.div8 t0,t1,t2 +[ ]+358:[ ]+6c7322fb[ ]+cv.add.div2 t0,t1,t2 +[ ]+35c:[ ]+6c7342fb[ ]+cv.add.div4 t0,t1,t2 +[ ]+360:[ ]+6c7362fb[ ]+cv.add.div8 t0,t1,t2 +[ ]+364:[ ]+747322fb[ ]+cv.sub.div2 t0,t1,t2 +[ ]+368:[ ]+747342fb[ ]+cv.sub.div4 t0,t1,t2 +[ ]+36c:[ ]+747362fb[ ]+cv.sub.div8 t0,t1,t2 diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s new file mode 100644 index 0000000000000000000000000000000000000000..a63586918cd81769edafec3188ca1e142fca38ae --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-simd-march-xcorevsimd.s @@ -0,0 +1,221 @@ +target: + cv.add.h x5, x6, x7 + cv.add.b x5, x6, x7 + cv.add.sc.h x5, x6, x7 + cv.add.sc.b x5, x6, x7 + cv.add.sci.h x6, x7, 20 + cv.add.sci.b x6, x7, 20 + cv.sub.h x5, x6, x7 + cv.sub.b x5, x6, x7 + cv.sub.sc.h x5, x6, x7 + cv.sub.sc.b x5, x6, x7 + cv.sub.sci.h x6, x7, 20 + cv.sub.sci.b x6, x7, 20 + cv.avg.h x5, x6, x7 + cv.avg.b x5, x6, x7 + cv.avg.sc.h x5, x6, x7 + cv.avg.sc.b x5, x6, x7 + cv.avg.sci.h x6, x7, 20 + cv.avg.sci.b x6, x7, 20 + cv.avgu.h x5, x6, x7 + cv.avgu.b x5, x6, x7 + cv.avgu.sc.h x5, x6, x7 + cv.avgu.sc.b x5, x6, x7 + cv.avgu.sci.h x6, x7, 20 + cv.avgu.sci.b x6, x7, 20 + cv.min.h x5, x6, x7 + cv.min.b x5, x6, x7 + cv.min.sc.h x5, x6, x7 + cv.min.sc.b x5, x6, x7 + cv.min.sci.h x6, x7, 20 + cv.min.sci.b x6, x7, 20 + cv.minu.h x5, x6, x7 + cv.minu.b x5, x6, x7 + cv.minu.sc.h x5, x6, x7 + cv.minu.sc.b x5, x6, x7 + cv.minu.sci.h x6, x7, 20 + cv.minu.sci.b x6, x7, 20 + cv.max.h x5, x6, x7 + cv.max.b x5, x6, x7 + cv.max.sc.h x5, x6, x7 + cv.max.sc.b x5, x6, x7 + cv.max.sci.h x6, x7, 20 + cv.max.sci.b x6, x7, 20 + cv.maxu.h x5, x6, x7 + cv.maxu.b x5, x6, x7 + cv.maxu.sc.h x5, x6, x7 + cv.maxu.sc.b x5, x6, x7 + cv.maxu.sci.h x6, x7, 20 + cv.maxu.sci.b x6, x7, 20 + cv.srl.h x5, x6, x7 + cv.srl.b x5, x6, x7 + cv.srl.sc.h x5, x6, x7 + cv.srl.sc.b x5, x6, x7 + cv.srl.sci.h x6, x7, 20 + cv.srl.sci.b x6, x7, 20 + cv.sra.h x5, x6, x7 + cv.sra.b x5, x6, x7 + cv.sra.sc.h x5, x6, x7 + cv.sra.sc.b x5, x6, x7 + cv.sra.sci.h x6, x7, 20 + cv.sra.sci.b x6, x7, 20 + cv.sll.h x5, x6, x7 + cv.sll.b x5, x6, x7 + cv.sll.sc.h x5, x6, x7 + cv.sll.sc.b x5, x6, x7 + cv.sll.sci.h x6, x7, 20 + cv.sll.sci.b x6, x7, 20 + cv.or.h x5, x6, x7 + cv.or.b x5, x6, x7 + cv.or.sc.h x5, x6, x7 + cv.or.sc.b x5, x6, x7 + cv.or.sci.h x6, x7, 20 + cv.or.sci.b x6, x7, 20 + cv.xor.h x5, x6, x7 + cv.xor.b x5, x6, x7 + cv.xor.sc.h x5, x6, x7 + cv.xor.sc.b x5, x6, x7 + cv.xor.sci.h x6, x7, 20 + cv.xor.sci.b x6, x7, 20 + cv.and.h x5, x6, x7 + cv.and.b x5, x6, x7 + cv.and.sc.h x5, x6, x7 + cv.and.sc.b x5, x6, x7 + cv.and.sci.h x6, x7, 20 + cv.and.sci.b x6, x7, 20 + cv.abs.h x6, x7 + cv.abs.b x6, x7 + cv.dotup.h x5, x6, x7 + cv.dotup.b x5, x6, x7 + cv.dotup.sc.h x5, x6, x7 + cv.dotup.sc.b x5, x6, x7 + cv.dotup.sci.h x6, x7, 20 + cv.dotup.sci.b x6, x7, 20 + cv.dotusp.h x5, x6, x7 + cv.dotusp.b x5, x6, x7 + cv.dotusp.sc.h x5, x6, x7 + cv.dotusp.sc.b x5, x6, x7 + cv.dotusp.sci.h x6, x7, 20 + cv.dotusp.sci.b x6, x7, 20 + cv.dotsp.h x5, x6, x7 + cv.dotsp.b x5, x6, x7 + cv.dotsp.sc.h x5, x6, x7 + cv.dotsp.sc.b x5, x6, x7 + cv.dotsp.sci.h x6, x7, 20 + cv.dotsp.sci.b x6, x7, 20 + cv.sdotup.h x5, x6, x7 + cv.sdotup.b x5, x6, x7 + cv.sdotup.sc.h x5, x6, x7 + cv.sdotup.sc.b x5, x6, x7 + cv.sdotup.sci.h x6, x7, 20 + cv.sdotup.sci.b x6, x7, 20 + cv.sdotusp.h x5, x6, x7 + cv.sdotusp.b x5, x6, x7 + cv.sdotusp.sc.h x5, x6, x7 + cv.sdotusp.sc.b x5, x6, x7 + cv.sdotusp.sci.h x6, x7, 20 + cv.sdotusp.sci.b x6, x7, 20 + cv.sdotsp.h x5, x6, x7 + cv.sdotsp.b x5, x6, x7 + cv.sdotsp.sc.h x5, x6, x7 + cv.sdotsp.sc.b x5, x6, x7 + cv.sdotsp.sci.h x6, x7, 20 + cv.sdotsp.sci.b x6, x7, 20 + cv.extract.h x6, x7, 20 + cv.extract.b x6, x7, 20 + cv.extractu.h x6, x7, 20 + cv.extractu.b x6, x7, 20 + cv.insert.h x6, x7, 20 + cv.insert.b x6, x7, 20 + cv.shuffle.h x5, x6, x7 + cv.shuffle.b x5, x6, x7 + cv.shuffle.sci.h x6, x7, 20 + cv.shufflei0.sci.b x6, x7, 20 + cv.shufflei1.sci.b x6, x7, 20 + cv.shufflei2.sci.b x6, x7, 20 + cv.shufflei3.sci.b x6, x7, 20 + cv.shuffle2.h x5, x6, x7 + cv.shuffle2.b x5, x6, x7 + cv.pack x5, x6, x7 + cv.pack.h x5, x6, x7 + cv.packhi.b x5, x6, x7 + cv.packlo.b x5, x6, x7 + cv.cmpeq.h x5, x6, x7 + cv.cmpeq.b x5, x6, x7 + cv.cmpeq.sc.h x5, x6, x7 + cv.cmpeq.sc.b x5, x6, x7 + cv.cmpeq.sci.h x6, x7, 20 + cv.cmpeq.sci.b x6, x7, 20 + cv.cmpne.h x5, x6, x7 + cv.cmpne.b x5, x6, x7 + cv.cmpne.sc.h x5, x6, x7 + cv.cmpne.sc.b x5, x6, x7 + cv.cmpne.sci.h x6, x7, 20 + cv.cmpne.sci.b x6, x7, 20 + cv.cmpgt.h x5, x6, x7 + cv.cmpgt.b x5, x6, x7 + cv.cmpgt.sc.h x5, x6, x7 + cv.cmpgt.sc.b x5, x6, x7 + cv.cmpgt.sci.h x6, x7, 20 + cv.cmpgt.sci.b x6, x7, 20 + cv.cmpge.h x5, x6, x7 + cv.cmpge.b x5, x6, x7 + cv.cmpge.sc.h x5, x6, x7 + cv.cmpge.sc.b x5, x6, x7 + cv.cmpge.sci.h x6, x7, 20 + cv.cmpge.sci.b x6, x7, 20 + cv.cmplt.h x5, x6, x7 + cv.cmplt.b x5, x6, x7 + cv.cmplt.sc.h x5, x6, x7 + cv.cmplt.sc.b x5, x6, x7 + cv.cmplt.sci.h x6, x7, 20 + cv.cmplt.sci.b x6, x7, 20 + cv.cmple.h x5, x6, x7 + cv.cmple.b x5, x6, x7 + cv.cmple.sc.h x5, x6, x7 + cv.cmple.sc.b x5, x6, x7 + cv.cmple.sci.h x6, x7, 20 + cv.cmple.sci.b x6, x7, 20 + cv.cmpgtu.h x5, x6, x7 + cv.cmpgtu.b x5, x6, x7 + cv.cmpgtu.sc.h x5, x6, x7 + cv.cmpgtu.sc.b x5, x6, x7 + cv.cmpgtu.sci.h x6, x7, 20 + cv.cmpgtu.sci.b x6, x7, 20 + cv.cmpgeu.h x5, x6, x7 + cv.cmpgeu.b x5, x6, x7 + cv.cmpgeu.sc.h x5, x6, x7 + cv.cmpgeu.sc.b x5, x6, x7 + cv.cmpgeu.sci.h x6, x7, 20 + cv.cmpgeu.sci.b x6, x7, 20 + cv.cmpltu.h x5, x6, x7 + cv.cmpltu.b x5, x6, x7 + cv.cmpltu.sc.h x5, x6, x7 + cv.cmpltu.sc.b x5, x6, x7 + cv.cmpltu.sci.h x6, x7, 20 + cv.cmpltu.sci.b x6, x7, 20 + cv.cmpleu.h x5, x6, x7 + cv.cmpleu.b x5, x6, x7 + cv.cmpleu.sc.h x5, x6, x7 + cv.cmpleu.sc.b x5, x6, x7 + cv.cmpleu.sci.h x6, x7, 20 + cv.cmpleu.sci.b x6, x7, 20 + cv.cplxmul.r x5, x6, x7 + cv.cplxmul.i x5, x6, x7 + cv.cplxmul.r.div2 x5, x6, x7 + cv.cplxmul.i.div2 x5, x6, x7 + cv.cplxmul.r.div4 x5, x6, x7 + cv.cplxmul.i.div4 x5, x6, x7 + cv.cplxmul.r.div8 x5, x6, x7 + cv.cplxmul.i.div8 x5, x6, x7 + cv.cplxconj x6, x7 + cv.subrotmj x5, x6, x7 + cv.subrotmj.div2 x5, x6, x7 + cv.subrotmj.div4 x5, x6, x7 + cv.subrotmj.div8 x5, x6, x7 + cv.add.div2 x5, x6, x7 + cv.add.div4 x5, x6, x7 + cv.add.div8 x5, x6, x7 + cv.sub.div2 x5, x6, x7 + cv.sub.div4 x5, x6, x7 + cv.sub.div8 x5, x6, x7 diff --git a/gas/testsuite/gas/riscv/cv-sll-b-fail.d b/gas/testsuite/gas/riscv/cv-sll-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..4d84e74ad62cca0093e456d41955dd6c66298728 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-b-fail.s +#error_output: cv-sll-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-b-fail.l b/gas/testsuite/gas/riscv/cv-sll-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..4bf8b2b1f9784739e744b98f3c93a1b16abc6dc3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.b x32,x32,x32' +.*: Error: illegal operands `cv.sll.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-b-fail.s b/gas/testsuite/gas/riscv/cv-sll-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c64950c5ef6261afc56d2431813bc3e3c011db6a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.b x32, x32, x32 + cv.sll.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-b-pass.d b/gas/testsuite/gas/riscv/cv-sll-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..791b7824f91ce1c04a277cf8af6eb162bd3570a4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000107b cv.sll.b zero,zero,zero + 4: 501090fb cv.sll.b ra,ra,ra + 8: 5021117b cv.sll.b sp,sp,sp + c: 5084147b cv.sll.b s0,s0,s0 + 10: 514a1a7b cv.sll.b s4,s4,s4 + 14: 51ff9ffb cv.sll.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-b-pass.s b/gas/testsuite/gas/riscv/cv-sll-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..929d3c607dc4487980eeffc8069557fe2ec03d87 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.b x0, x0, x0 + cv.sll.b x1, x1, x1 + cv.sll.b x2, x2, x2 + cv.sll.b x8, x8, x8 + cv.sll.b x20, x20, x20 + cv.sll.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-h-fail.d b/gas/testsuite/gas/riscv/cv-sll-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..873a39e8c9e0488fcd808a409f1e1d90c4ba538b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-h-fail.s +#error_output: cv-sll-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-h-fail.l b/gas/testsuite/gas/riscv/cv-sll-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..3ea79744e4f4d34e165830b5b5fe3d4aa3f2f431 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.h x32,x32,x32' +.*: Error: illegal operands `cv.sll.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-h-fail.s b/gas/testsuite/gas/riscv/cv-sll-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a47ce4c06dd7f3807e4b131922eac51e2f117918 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.h x32, x32, x32 + cv.sll.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-h-pass.d b/gas/testsuite/gas/riscv/cv-sll-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..c863dca01b88e890761a8a11f3a20ff8fcea5e6d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000007b cv.sll.h zero,zero,zero + 4: 501080fb cv.sll.h ra,ra,ra + 8: 5021017b cv.sll.h sp,sp,sp + c: 5084047b cv.sll.h s0,s0,s0 + 10: 514a0a7b cv.sll.h s4,s4,s4 + 14: 51ff8ffb cv.sll.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-h-pass.s b/gas/testsuite/gas/riscv/cv-sll-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4fa2c8c2b07e87479861432bd93470c6c8792d79 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.h x0, x0, x0 + cv.sll.h x1, x1, x1 + cv.sll.h x2, x2, x2 + cv.sll.h x8, x8, x8 + cv.sll.h x20, x20, x20 + cv.sll.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b11ce4113c9ae54df7bac0e135d0aa8d0da2115c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-b-fail.s +#error_output: cv-sll-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ce3d6df659af104041b977a3df0f88d59025f326 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sll.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..faeb0c7cd668746b402b0a512e6bfd5699578301 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.sc.b x32, x32, x32 + cv.sll.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3b42197ea031ca6720fab618bdd444d99e6d355d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000507b cv.sll.sc.b zero,zero,zero + 4: 5010d0fb cv.sll.sc.b ra,ra,ra + 8: 5021517b cv.sll.sc.b sp,sp,sp + c: 5084547b cv.sll.sc.b s0,s0,s0 + 10: 514a5a7b cv.sll.sc.b s4,s4,s4 + 14: 51ffdffb cv.sll.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e8453d8dfd0682705a4a02090aaf1af2b46a804a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.sc.b x0, x0, x0 + cv.sll.sc.b x1, x1, x1 + cv.sll.sc.b x2, x2, x2 + cv.sll.sc.b x8, x8, x8 + cv.sll.sc.b x20, x20, x20 + cv.sll.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..666a09591753f6690d9b4099c05d5859ee84c5a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-h-fail.s +#error_output: cv-sll-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..320fa74ec56b3f1a31ad38c0c46e64f0fcedff1f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sll.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..0fa9838b6b6b89a9eb98d5586dd4ebf483cd242a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sll.sc.h x32, x32, x32 + cv.sll.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..83483a97efe9d5eeb9df39cb086a5458d8af254f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5000407b cv.sll.sc.h zero,zero,zero + 4: 5010c0fb cv.sll.sc.h ra,ra,ra + 8: 5021417b cv.sll.sc.h sp,sp,sp + c: 5084447b cv.sll.sc.h s0,s0,s0 + 10: 514a4a7b cv.sll.sc.h s4,s4,s4 + 14: 51ffcffb cv.sll.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..d496d672b49ac6baa00d816c73fb22783fc47abb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sll.sc.h x0, x0, x0 + cv.sll.sc.h x1, x1, x1 + cv.sll.sc.h x2, x2, x2 + cv.sll.sc.h x8, x8, x8 + cv.sll.sc.h x20, x20, x20 + cv.sll.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..13614f1be02062c6de3c9d14ce2a190d812d72c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-b-fail.s +#error_output: cv-sll-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..2c65793b0e77897d380109bdc8ec525ba6d6b230 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sll.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..ac98cd356cf2c8dcd078bc85e1a2476cbd53c256 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sll.sci.b x32, x32, 20 + cv.sll.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sll.sci.b x6, x7, -33 + cv.sll.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..eeae01cc31e6352475dd04a1ae68b6452e084e82 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5140707b cv.sll.sci.b zero,zero,20 + 4: 5140f0fb cv.sll.sci.b ra,ra,20 + 8: 5141717b cv.sll.sci.b sp,sp,20 + c: 5144747b cv.sll.sci.b s0,s0,20 + 10: 514a7a7b cv.sll.sci.b s4,s4,20 + 14: 514ffffb cv.sll.sci.b t6,t6,20 + 18: 5203f37b cv.sll.sci.b t1,t2,-32 + 1c: 5003f37b cv.sll.sci.b t1,t2,0 + 20: 51f3f37b cv.sll.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..03388ef46a31a5beaaf9f38aba17fc44e47f698b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sll.sci.b x0, x0, 20 + cv.sll.sci.b x1, x1, 20 + cv.sll.sci.b x2, x2, 20 + cv.sll.sci.b x8, x8, 20 + cv.sll.sci.b x20, x20, 20 + cv.sll.sci.b x31, x31, 20 + #Immediate Values Test + cv.sll.sci.b x6, x7, -32 + cv.sll.sci.b x6, x7, 0 + cv.sll.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..72b76a3b5c95ae49c7e057d0ad23337a9b5c38ba --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-h-fail.s +#error_output: cv-sll-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..091eeb0262568b8059527e7f18502337dbbd9583 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sll.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sll.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..d95ab013e24add8c8985284a70cc8e4b508d3439 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sll.sci.h x32, x32, 20 + cv.sll.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sll.sci.h x6, x7, -33 + cv.sll.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..8662bf5fb1711280acac27133296e01dce1053d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sll-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 5140607b cv.sll.sci.h zero,zero,20 + 4: 5140e0fb cv.sll.sci.h ra,ra,20 + 8: 5141617b cv.sll.sci.h sp,sp,20 + c: 5144647b cv.sll.sci.h s0,s0,20 + 10: 514a6a7b cv.sll.sci.h s4,s4,20 + 14: 514feffb cv.sll.sci.h t6,t6,20 + 18: 5203e37b cv.sll.sci.h t1,t2,-32 + 1c: 5003e37b cv.sll.sci.h t1,t2,0 + 20: 51f3e37b cv.sll.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e11bdd43354e92091658171aa5f17688a3b08c4f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sll-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sll.sci.h x0, x0, 20 + cv.sll.sci.h x1, x1, 20 + cv.sll.sci.h x2, x2, 20 + cv.sll.sci.h x8, x8, 20 + cv.sll.sci.h x20, x20, 20 + cv.sll.sci.h x31, x31, 20 + #Immediate Values Test + cv.sll.sci.h x6, x7, -32 + cv.sll.sci.h x6, x7, 0 + cv.sll.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sra-b-fail.d b/gas/testsuite/gas/riscv/cv-sra-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..44f1df2383e79677c626fb4b6cb526c9c41c13fc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-b-fail.s +#error_output: cv-sra-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-b-fail.l b/gas/testsuite/gas/riscv/cv-sra-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..e6d5a0945391a8472e05505e719441f2c81899b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.b x32,x32,x32' +.*: Error: illegal operands `cv.sra.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-b-fail.s b/gas/testsuite/gas/riscv/cv-sra-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c09838a04eaa66937c9be868a0e6b11961d8596b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.b x32, x32, x32 + cv.sra.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-b-pass.d b/gas/testsuite/gas/riscv/cv-sra-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..63fd5d141d9cbb05d3178b4fc0bdf2beb78f398d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800107b cv.sra.b zero,zero,zero + 4: 481090fb cv.sra.b ra,ra,ra + 8: 4821117b cv.sra.b sp,sp,sp + c: 4884147b cv.sra.b s0,s0,s0 + 10: 494a1a7b cv.sra.b s4,s4,s4 + 14: 49ff9ffb cv.sra.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-b-pass.s b/gas/testsuite/gas/riscv/cv-sra-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..0cef7810d49c8b8a4abfa67d7c2d9bd2c8b7b0d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.b x0, x0, x0 + cv.sra.b x1, x1, x1 + cv.sra.b x2, x2, x2 + cv.sra.b x8, x8, x8 + cv.sra.b x20, x20, x20 + cv.sra.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-h-fail.d b/gas/testsuite/gas/riscv/cv-sra-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..ce12e48a5baefec5ced28ff1e74ec725236820ce --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-h-fail.s +#error_output: cv-sra-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-h-fail.l b/gas/testsuite/gas/riscv/cv-sra-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ddf7b46acb0638e2a7e9a385d84ba9e076a52fcd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.h x32,x32,x32' +.*: Error: illegal operands `cv.sra.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-h-fail.s b/gas/testsuite/gas/riscv/cv-sra-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..dcbe979c3f613690bb3b479e2e4a2748f14babd1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.h x32, x32, x32 + cv.sra.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-h-pass.d b/gas/testsuite/gas/riscv/cv-sra-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f1b8530325a7e5cae95a650afad2f16145bcd960 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800007b cv.sra.h zero,zero,zero + 4: 481080fb cv.sra.h ra,ra,ra + 8: 4821017b cv.sra.h sp,sp,sp + c: 4884047b cv.sra.h s0,s0,s0 + 10: 494a0a7b cv.sra.h s4,s4,s4 + 14: 49ff8ffb cv.sra.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-h-pass.s b/gas/testsuite/gas/riscv/cv-sra-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5dad74333e8fb477b81359e8ac6fce181680aa7a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.h x0, x0, x0 + cv.sra.h x1, x1, x1 + cv.sra.h x2, x2, x2 + cv.sra.h x8, x8, x8 + cv.sra.h x20, x20, x20 + cv.sra.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..c64ee7d296e8e8eeb62c5a74c1fe14d805d379a6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-b-fail.s +#error_output: cv-sra-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..72df02d3a2d733e95f030b95304ce7a99e5f60b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sra.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..5ebdbfb141868d8c5e37c43449d0700a8f991920 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.sc.b x32, x32, x32 + cv.sra.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ee518b268ea59474918652040ea37476a50f0ab8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800507b cv.sra.sc.b zero,zero,zero + 4: 4810d0fb cv.sra.sc.b ra,ra,ra + 8: 4821517b cv.sra.sc.b sp,sp,sp + c: 4884547b cv.sra.sc.b s0,s0,s0 + 10: 494a5a7b cv.sra.sc.b s4,s4,s4 + 14: 49ffdffb cv.sra.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..3ae2c92ec39f8cbcbb80c4a2fda81e04d3fefb47 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.sc.b x0, x0, x0 + cv.sra.sc.b x1, x1, x1 + cv.sra.sc.b x2, x2, x2 + cv.sra.sc.b x8, x8, x8 + cv.sra.sc.b x20, x20, x20 + cv.sra.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..662d184d8f6d825eed8018ef4deacd6063587c93 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-h-fail.s +#error_output: cv-sra-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..68eef5792728f76f47dbff88eb86c73be4b43a93 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sra.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..3f4dc2b58daa0379b9717a0a6fe234135e849856 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sra.sc.h x32, x32, x32 + cv.sra.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..31c8809453058744886d62f96409c43c2af5b6bd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4800407b cv.sra.sc.h zero,zero,zero + 4: 4810c0fb cv.sra.sc.h ra,ra,ra + 8: 4821417b cv.sra.sc.h sp,sp,sp + c: 4884447b cv.sra.sc.h s0,s0,s0 + 10: 494a4a7b cv.sra.sc.h s4,s4,s4 + 14: 49ffcffb cv.sra.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..06f73833df389743d6909480fe735b5f2eb5b704 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sra.sc.h x0, x0, x0 + cv.sra.sc.h x1, x1, x1 + cv.sra.sc.h x2, x2, x2 + cv.sra.sc.h x8, x8, x8 + cv.sra.sc.h x20, x20, x20 + cv.sra.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..3cb8f9cf06d854cdc8df93cd11ad2ea4eca4967e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-b-fail.s +#error_output: cv-sra-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ed25c4b5da700da0504e4a1d9d8e017219ea0ba6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sra.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..4809c41c8244ef6dd47a32cb13b6940268735409 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sra.sci.b x32, x32, 20 + cv.sra.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sra.sci.b x6, x7, -33 + cv.sra.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..67f565d96e98c74ba98dda0412b7e5883e8ae4c6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4940707b cv.sra.sci.b zero,zero,20 + 4: 4940f0fb cv.sra.sci.b ra,ra,20 + 8: 4941717b cv.sra.sci.b sp,sp,20 + c: 4944747b cv.sra.sci.b s0,s0,20 + 10: 494a7a7b cv.sra.sci.b s4,s4,20 + 14: 494ffffb cv.sra.sci.b t6,t6,20 + 18: 4a03f37b cv.sra.sci.b t1,t2,-32 + 1c: 4803f37b cv.sra.sci.b t1,t2,0 + 20: 49f3f37b cv.sra.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..82bbdba79a8cce122399fab2d17dfc3184d1595d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sra.sci.b x0, x0, 20 + cv.sra.sci.b x1, x1, 20 + cv.sra.sci.b x2, x2, 20 + cv.sra.sci.b x8, x8, 20 + cv.sra.sci.b x20, x20, 20 + cv.sra.sci.b x31, x31, 20 + #Immediate Values Test + cv.sra.sci.b x6, x7, -32 + cv.sra.sci.b x6, x7, 0 + cv.sra.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..8a5945017bd6e3ae4dc8c1c0742810d8905679a3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-h-fail.s +#error_output: cv-sra-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..53fb9c011c582a854723922d0f2a01ed46bc94db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sra.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sra.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..50896d2531a00510b35edcec958543aa5b83d75e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sra.sci.h x32, x32, 20 + cv.sra.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sra.sci.h x6, x7, -33 + cv.sra.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..41a317dfee7ac8908c8af4e75da75492ca49b232 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sra-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4940607b cv.sra.sci.h zero,zero,20 + 4: 4940e0fb cv.sra.sci.h ra,ra,20 + 8: 4941617b cv.sra.sci.h sp,sp,20 + c: 4944647b cv.sra.sci.h s0,s0,20 + 10: 494a6a7b cv.sra.sci.h s4,s4,20 + 14: 494feffb cv.sra.sci.h t6,t6,20 + 18: 4a03e37b cv.sra.sci.h t1,t2,-32 + 1c: 4803e37b cv.sra.sci.h t1,t2,0 + 20: 49f3e37b cv.sra.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..28977cc79870b756fcc476457268699820f2c647 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sra-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sra.sci.h x0, x0, 20 + cv.sra.sci.h x1, x1, 20 + cv.sra.sci.h x2, x2, 20 + cv.sra.sci.h x8, x8, 20 + cv.sra.sci.h x20, x20, 20 + cv.sra.sci.h x31, x31, 20 + #Immediate Values Test + cv.sra.sci.h x6, x7, -32 + cv.sra.sci.h x6, x7, 0 + cv.sra.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-srl-b-fail.d b/gas/testsuite/gas/riscv/cv-srl-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..a667b8030c5b7412b6dcdce7bc2a79ca84ae21df --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-b-fail.s +#error_output: cv-srl-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-b-fail.l b/gas/testsuite/gas/riscv/cv-srl-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..2e8ea987dac242db83a01ccd2687e6346f5e5edf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.b x32,x32,x32' +.*: Error: illegal operands `cv.srl.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-b-fail.s b/gas/testsuite/gas/riscv/cv-srl-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..da928163404e46f583256409c7aec24bd6332c0f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.b x32, x32, x32 + cv.srl.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-b-pass.d b/gas/testsuite/gas/riscv/cv-srl-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..fa1b2634e7a73a603fe64fbfbecd9d226e7d4590 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000107b cv.srl.b zero,zero,zero + 4: 401090fb cv.srl.b ra,ra,ra + 8: 4021117b cv.srl.b sp,sp,sp + c: 4084147b cv.srl.b s0,s0,s0 + 10: 414a1a7b cv.srl.b s4,s4,s4 + 14: 41ff9ffb cv.srl.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-b-pass.s b/gas/testsuite/gas/riscv/cv-srl-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..631271055133fa2450208f783fafe7df5f11c99a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.b x0, x0, x0 + cv.srl.b x1, x1, x1 + cv.srl.b x2, x2, x2 + cv.srl.b x8, x8, x8 + cv.srl.b x20, x20, x20 + cv.srl.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-h-fail.d b/gas/testsuite/gas/riscv/cv-srl-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..2d06e42c58955d8112a8439aab4ae3bc52a34591 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-h-fail.s +#error_output: cv-srl-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-h-fail.l b/gas/testsuite/gas/riscv/cv-srl-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..427b72b521988395336a0316efd3d63159dcea1e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.h x32,x32,x32' +.*: Error: illegal operands `cv.srl.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-h-fail.s b/gas/testsuite/gas/riscv/cv-srl-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..56519e489e174a02c516eb45ff459809228f382b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.h x32, x32, x32 + cv.srl.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-h-pass.d b/gas/testsuite/gas/riscv/cv-srl-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..c4a52f41cc50e97a1344533948e26cf3ec57dbfd --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000007b cv.srl.h zero,zero,zero + 4: 401080fb cv.srl.h ra,ra,ra + 8: 4021017b cv.srl.h sp,sp,sp + c: 4084047b cv.srl.h s0,s0,s0 + 10: 414a0a7b cv.srl.h s4,s4,s4 + 14: 41ff8ffb cv.srl.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-h-pass.s b/gas/testsuite/gas/riscv/cv-srl-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c63c5af091dfbb54e251c96c9176afbdc4159a72 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.h x0, x0, x0 + cv.srl.h x1, x1, x1 + cv.srl.h x2, x2, x2 + cv.srl.h x8, x8, x8 + cv.srl.h x20, x20, x20 + cv.srl.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d9db74f70f459fbb8a625c90a232a029d2d8fef9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-b-fail.s +#error_output: cv-srl-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..48f43ede7bc568d2ff36d77982d2e947e385e251 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.srl.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a70ef1704a27c36afeccce7564c350ebc3d9d51f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.sc.b x32, x32, x32 + cv.srl.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..900d65639075dbaa50ff90d7f7bf75cdf5da44db --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000507b cv.srl.sc.b zero,zero,zero + 4: 4010d0fb cv.srl.sc.b ra,ra,ra + 8: 4021517b cv.srl.sc.b sp,sp,sp + c: 4084547b cv.srl.sc.b s0,s0,s0 + 10: 414a5a7b cv.srl.sc.b s4,s4,s4 + 14: 41ffdffb cv.srl.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b104a06f2844917c1f4d986ccfbc475260c5dea3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.sc.b x0, x0, x0 + cv.srl.sc.b x1, x1, x1 + cv.srl.sc.b x2, x2, x2 + cv.srl.sc.b x8, x8, x8 + cv.srl.sc.b x20, x20, x20 + cv.srl.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..b32a509a9b4858f3f223e02abb7ecbd1c028e1ab --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-h-fail.s +#error_output: cv-srl-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..721754b3854a70635eb350316b6c523b63a8a2b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.srl.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..95ef1a18e2da87bcf56ce8d9e8c82a8c881df314 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.srl.sc.h x32, x32, x32 + cv.srl.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..0f7cd11ad6b51026bc94a35f9b5a4b65359b7589 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4000407b cv.srl.sc.h zero,zero,zero + 4: 4010c0fb cv.srl.sc.h ra,ra,ra + 8: 4021417b cv.srl.sc.h sp,sp,sp + c: 4084447b cv.srl.sc.h s0,s0,s0 + 10: 414a4a7b cv.srl.sc.h s4,s4,s4 + 14: 41ffcffb cv.srl.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..e961105803bed71421aed7fc83c8a56e224377eb --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.srl.sc.h x0, x0, x0 + cv.srl.sc.h x1, x1, x1 + cv.srl.sc.h x2, x2, x2 + cv.srl.sc.h x8, x8, x8 + cv.srl.sc.h x20, x20, x20 + cv.srl.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..d362aa54f312eb04d6518a3b9e89eb9d8fc062c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-b-fail.s +#error_output: cv-srl-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b2af4b773c45e56a9030edc1cd121a349f06cc78 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sci.b x32,x32,20' +.*: Error: illegal operands `cv.srl.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..24618209ed8e27c2783b98ea9aebce96103216f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.srl.sci.b x32, x32, 20 + cv.srl.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.srl.sci.b x6, x7, -33 + cv.srl.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..bd70fb90d26fd427c40ad5aa7ed3607d1a15ae25 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4140707b cv.srl.sci.b zero,zero,20 + 4: 4140f0fb cv.srl.sci.b ra,ra,20 + 8: 4141717b cv.srl.sci.b sp,sp,20 + c: 4144747b cv.srl.sci.b s0,s0,20 + 10: 414a7a7b cv.srl.sci.b s4,s4,20 + 14: 414ffffb cv.srl.sci.b t6,t6,20 + 18: 4203f37b cv.srl.sci.b t1,t2,-32 + 1c: 4003f37b cv.srl.sci.b t1,t2,0 + 20: 41f3f37b cv.srl.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..b5e7af2bcf61934671476addd2ff008060aed138 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.srl.sci.b x0, x0, 20 + cv.srl.sci.b x1, x1, 20 + cv.srl.sci.b x2, x2, 20 + cv.srl.sci.b x8, x8, 20 + cv.srl.sci.b x20, x20, 20 + cv.srl.sci.b x31, x31, 20 + #Immediate Values Test + cv.srl.sci.b x6, x7, -32 + cv.srl.sci.b x6, x7, 0 + cv.srl.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..f185f6b0cc4e0063e5b62e26264bd89a87cd3163 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-h-fail.s +#error_output: cv-srl-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..d7bc65aa5771e2ab1f88d04f05a38532259748c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.srl.sci.h x32,x32,20' +.*: Error: illegal operands `cv.srl.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..d0b61b5904fca855079b449605c6dd82d95fb40f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.srl.sci.h x32, x32, 20 + cv.srl.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.srl.sci.h x6, x7, -33 + cv.srl.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..0a1541319a50410bcc38117c8dcda84f04d6736c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-srl-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 4140607b cv.srl.sci.h zero,zero,20 + 4: 4140e0fb cv.srl.sci.h ra,ra,20 + 8: 4141617b cv.srl.sci.h sp,sp,20 + c: 4144647b cv.srl.sci.h s0,s0,20 + 10: 414a6a7b cv.srl.sci.h s4,s4,20 + 14: 414feffb cv.srl.sci.h t6,t6,20 + 18: 4203e37b cv.srl.sci.h t1,t2,-32 + 1c: 4003e37b cv.srl.sci.h t1,t2,0 + 20: 41f3e37b cv.srl.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..862629a13b531aeff15370d16c99851986867759 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-srl-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.srl.sci.h x0, x0, 20 + cv.srl.sci.h x1, x1, 20 + cv.srl.sci.h x2, x2, 20 + cv.srl.sci.h x8, x8, 20 + cv.srl.sci.h x20, x20, 20 + cv.srl.sci.h x31, x31, 20 + #Immediate Values Test + cv.srl.sci.h x6, x7, -32 + cv.srl.sci.h x6, x7, 0 + cv.srl.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sub-b-fail.d b/gas/testsuite/gas/riscv/cv-sub-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..9ede9c593cf57856f96985732a17235bca814e76 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-b-fail.s +#error_output: cv-sub-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-b-fail.l b/gas/testsuite/gas/riscv/cv-sub-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..02dc7c9c35c46e8117416fedd03b9591c1e3b088 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.b x32,x32,x32' +.*: Error: illegal operands `cv.sub.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-b-fail.s b/gas/testsuite/gas/riscv/cv-sub-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..ca21cbf80a4879d2a513616819b66cf7ba6d2abc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.b x32, x32, x32 + cv.sub.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-b-pass.d b/gas/testsuite/gas/riscv/cv-sub-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b96bab91c0f25ad3b8451804e800d421bab5b98d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800107b cv.sub.b zero,zero,zero + 4: 081090fb cv.sub.b ra,ra,ra + 8: 0821117b cv.sub.b sp,sp,sp + c: 0884147b cv.sub.b s0,s0,s0 + 10: 094a1a7b cv.sub.b s4,s4,s4 + 14: 09ff9ffb cv.sub.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-b-pass.s b/gas/testsuite/gas/riscv/cv-sub-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..99f9c1ef13bde94cd91c8c0320d423e53b1b1f67 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.b x0, x0, x0 + cv.sub.b x1, x1, x1 + cv.sub.b x2, x2, x2 + cv.sub.b x8, x8, x8 + cv.sub.b x20, x20, x20 + cv.sub.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-fail.d b/gas/testsuite/gas/riscv/cv-sub-div2-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..0102fcfe70be57ea5077d9f2ffce8724d4c5b03a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div2-fail.s +#error_output: cv-sub-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-fail.l b/gas/testsuite/gas/riscv/cv-sub-div2-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..7776bd5850fb89e542588d3efcffb773d5ad3c96 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.div2 x32,x32,x32' +.*: Error: illegal operands `cv.sub.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-fail.s b/gas/testsuite/gas/riscv/cv-sub-div2-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e1c33a6fd21484e19a9b6cd06b6b909c0e1dc8b4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.div2 x32, x32, x32 + cv.sub.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-pass.d b/gas/testsuite/gas/riscv/cv-sub-div2-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..63d2a344a4e05407ef268937223cba5e310a4768 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7400207b cv.sub.div2 zero,zero,zero + 4: 7410a0fb cv.sub.div2 ra,ra,ra + 8: 7421217b cv.sub.div2 sp,sp,sp + c: 7484247b cv.sub.div2 s0,s0,s0 + 10: 754a2a7b cv.sub.div2 s4,s4,s4 + 14: 75ffaffb cv.sub.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-div2-pass.s b/gas/testsuite/gas/riscv/cv-sub-div2-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7ca4507d27dd14d5e65fdf3975b33cea0dd1d20f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.div2 x0, x0, x0 + cv.sub.div2 x1, x1, x1 + cv.sub.div2 x2, x2, x2 + cv.sub.div2 x8, x8, x8 + cv.sub.div2 x20, x20, x20 + cv.sub.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-fail.d b/gas/testsuite/gas/riscv/cv-sub-div4-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..ed6f5cf7429816de425dbd1ebd7fcc88bc9281a1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div4-fail.s +#error_output: cv-sub-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-fail.l b/gas/testsuite/gas/riscv/cv-sub-div4-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..886d6783979b1766fd3143bc5b098902f3c563d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.div4 x32,x32,x32' +.*: Error: illegal operands `cv.sub.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-fail.s b/gas/testsuite/gas/riscv/cv-sub-div4-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..8e7a639f9a8b0a46350892411bdd9f77f0b50367 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.div4 x32, x32, x32 + cv.sub.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-pass.d b/gas/testsuite/gas/riscv/cv-sub-div4-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..2f8558bb90a7e54046ac028d0fc3c310b5cfbd37 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7400407b cv.sub.div4 zero,zero,zero + 4: 7410c0fb cv.sub.div4 ra,ra,ra + 8: 7421417b cv.sub.div4 sp,sp,sp + c: 7484447b cv.sub.div4 s0,s0,s0 + 10: 754a4a7b cv.sub.div4 s4,s4,s4 + 14: 75ffcffb cv.sub.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-div4-pass.s b/gas/testsuite/gas/riscv/cv-sub-div4-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..8e6ad0c8a6471ff7a1d2147793c423c86b54e485 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.div4 x0, x0, x0 + cv.sub.div4 x1, x1, x1 + cv.sub.div4 x2, x2, x2 + cv.sub.div4 x8, x8, x8 + cv.sub.div4 x20, x20, x20 + cv.sub.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-fail.d b/gas/testsuite/gas/riscv/cv-sub-div8-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..71496a671fb1f771cc1025931df0b7f77e43ee49 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div8-fail.s +#error_output: cv-sub-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-fail.l b/gas/testsuite/gas/riscv/cv-sub-div8-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..c6141b1dc69198c8be4eed8f28568995ce187b9d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.div8 x32,x32,x32' +.*: Error: illegal operands `cv.sub.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-fail.s b/gas/testsuite/gas/riscv/cv-sub-div8-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..f642daefd3aa27240151a04edf60b0ff3c91537c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.div8 x32, x32, x32 + cv.sub.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-pass.d b/gas/testsuite/gas/riscv/cv-sub-div8-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..bc8e03517640bd00c499faa793b86265e28e0944 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 7400607b cv.sub.div8 zero,zero,zero + 4: 7410e0fb cv.sub.div8 ra,ra,ra + 8: 7421617b cv.sub.div8 sp,sp,sp + c: 7484647b cv.sub.div8 s0,s0,s0 + 10: 754a6a7b cv.sub.div8 s4,s4,s4 + 14: 75ffeffb cv.sub.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-div8-pass.s b/gas/testsuite/gas/riscv/cv-sub-div8-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..1d38695d203d04b17fb688cb730c794443d6b749 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.div8 x0, x0, x0 + cv.sub.div8 x1, x1, x1 + cv.sub.div8 x2, x2, x2 + cv.sub.div8 x8, x8, x8 + cv.sub.div8 x20, x20, x20 + cv.sub.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-h-fail.d b/gas/testsuite/gas/riscv/cv-sub-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..477c7f70f4b845504a5dfa9b1cb2cbbfe4da6b8f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-h-fail.s +#error_output: cv-sub-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-h-fail.l b/gas/testsuite/gas/riscv/cv-sub-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..36728c3b84b872c1b013bc588e2dc044115877e5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.h x32,x32,x32' +.*: Error: illegal operands `cv.sub.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-h-fail.s b/gas/testsuite/gas/riscv/cv-sub-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..63a218290f0f22da3ab0450566fcc368dbb39e71 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.h x32, x32, x32 + cv.sub.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-h-pass.d b/gas/testsuite/gas/riscv/cv-sub-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..923c8c0d87e57a3df65b896a8a27b26dc66f2e27 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800007b cv.sub.h zero,zero,zero + 4: 081080fb cv.sub.h ra,ra,ra + 8: 0821017b cv.sub.h sp,sp,sp + c: 0884047b cv.sub.h s0,s0,s0 + 10: 094a0a7b cv.sub.h s4,s4,s4 + 14: 09ff8ffb cv.sub.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-h-pass.s b/gas/testsuite/gas/riscv/cv-sub-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..61fc9f949a0513dcd13eb814ec0b7d52fec155aa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.h x0, x0, x0 + cv.sub.h x1, x1, x1 + cv.sub.h x2, x2, x2 + cv.sub.h x8, x8, x8 + cv.sub.h x20, x20, x20 + cv.sub.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..0e7f88a9dd3e9659c367f02163626fb79e3b768f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-b-fail.s +#error_output: cv-sub-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..785f3c7c3be99d65bd7dfd3d51a767e35e07856f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.sub.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..83942ae229003a1ba4bf588a77e59092e04474e5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.sc.b x32, x32, x32 + cv.sub.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..45d0391cc6c2c9108e01a4b3ae20b72e776e277a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800507b cv.sub.sc.b zero,zero,zero + 4: 0810d0fb cv.sub.sc.b ra,ra,ra + 8: 0821517b cv.sub.sc.b sp,sp,sp + c: 0884547b cv.sub.sc.b s0,s0,s0 + 10: 094a5a7b cv.sub.sc.b s4,s4,s4 + 14: 09ffdffb cv.sub.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..2d0170cdfef670529e45915472c36b939f3a33fa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.sc.b x0, x0, x0 + cv.sub.sc.b x1, x1, x1 + cv.sub.sc.b x2, x2, x2 + cv.sub.sc.b x8, x8, x8 + cv.sub.sc.b x20, x20, x20 + cv.sub.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..102c3ceec1d240b21561b94639577a4e738949b3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-h-fail.s +#error_output: cv-sub-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..5d5c6b67ac2a41dd9bc5d75d6b68fee1a820b39e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.sub.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..cc48b52fa2ce57c13da5cd9299bc24d53816816f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.sub.sc.h x32, x32, x32 + cv.sub.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e4f9808610772e8ce93b5ae32d20dc2bd0b13f81 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0800407b cv.sub.sc.h zero,zero,zero + 4: 0810c0fb cv.sub.sc.h ra,ra,ra + 8: 0821417b cv.sub.sc.h sp,sp,sp + c: 0884447b cv.sub.sc.h s0,s0,s0 + 10: 094a4a7b cv.sub.sc.h s4,s4,s4 + 14: 09ffcffb cv.sub.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..5608febce85ea92569dbde87910ccebd2d7ce1e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.sub.sc.h x0, x0, x0 + cv.sub.sc.h x1, x1, x1 + cv.sub.sc.h x2, x2, x2 + cv.sub.sc.h x8, x8, x8 + cv.sub.sc.h x20, x20, x20 + cv.sub.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..74cb4e1f284f7ab943b6f5daca98901677b351ed --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-b-fail.s +#error_output: cv-sub-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..d45c4089d7c7839c798d1f65c9a68b4c592d872e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sci.b x32,x32,20' +.*: Error: illegal operands `cv.sub.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..efacb4d76ffe8d0db3b2595c61da21e2b7d75447 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sub.sci.b x32, x32, 20 + cv.sub.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.sub.sci.b x6, x7, -33 + cv.sub.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..d28d68678c4baeea153fa339d34d64d711f980fa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0940707b cv.sub.sci.b zero,zero,20 + 4: 0940f0fb cv.sub.sci.b ra,ra,20 + 8: 0941717b cv.sub.sci.b sp,sp,20 + c: 0944747b cv.sub.sci.b s0,s0,20 + 10: 094a7a7b cv.sub.sci.b s4,s4,20 + 14: 094ffffb cv.sub.sci.b t6,t6,20 + 18: 0a03f37b cv.sub.sci.b t1,t2,-32 + 1c: 0803f37b cv.sub.sci.b t1,t2,0 + 20: 09f3f37b cv.sub.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..ef41450b53f4f88a5cdaf8e5a9a082442b3194f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sub.sci.b x0, x0, 20 + cv.sub.sci.b x1, x1, 20 + cv.sub.sci.b x2, x2, 20 + cv.sub.sci.b x8, x8, 20 + cv.sub.sci.b x20, x20, 20 + cv.sub.sci.b x31, x31, 20 + #Immediate Values Test + cv.sub.sci.b x6, x7, -32 + cv.sub.sci.b x6, x7, 0 + cv.sub.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..51aed159ba771de2984326089fdc0ac586ea5f19 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-h-fail.s +#error_output: cv-sub-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..ff9425a443586273c6bfb9a68d17e667c1b982e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.sub.sci.h x32,x32,20' +.*: Error: illegal operands `cv.sub.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..bdd60606d7af0cbe848980bc956b6bcf72e20def --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.sub.sci.h x32, x32, 20 + cv.sub.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.sub.sci.h x6, x7, -33 + cv.sub.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..832507864b689b871d6421728869b4997e9ccbfa --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-sub-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 0940607b cv.sub.sci.h zero,zero,20 + 4: 0940e0fb cv.sub.sci.h ra,ra,20 + 8: 0941617b cv.sub.sci.h sp,sp,20 + c: 0944647b cv.sub.sci.h s0,s0,20 + 10: 094a6a7b cv.sub.sci.h s4,s4,20 + 14: 094feffb cv.sub.sci.h t6,t6,20 + 18: 0a03e37b cv.sub.sci.h t1,t2,-32 + 1c: 0803e37b cv.sub.sci.h t1,t2,0 + 20: 09f3e37b cv.sub.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..7b74356abc7172912e8a285fafa7b730f1e7d968 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-sub-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.sub.sci.h x0, x0, 20 + cv.sub.sci.h x1, x1, 20 + cv.sub.sci.h x2, x2, 20 + cv.sub.sci.h x8, x8, 20 + cv.sub.sci.h x20, x20, 20 + cv.sub.sci.h x31, x31, 20 + #Immediate Values Test + cv.sub.sci.h x6, x7, -32 + cv.sub.sci.h x6, x7, 0 + cv.sub.sci.h x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..93d6f25710ffedd8cf6fdec36ecc0dcc55d5eef2 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div2-fail.s +#error_output: cv-subrotmj-div2-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..324fe88cfc7f9210b0b76545bef68024147abbb6 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj.div2 x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj.div2 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..b8a95a56588b2c0b03ecebe01f36a0d485970e8c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj.div2 x32, x32, x32 + cv.subrotmj.div2 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..f7e2851fa6b63c814d783c3eed4ea5fe96c99399 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div2-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400207b cv.subrotmj.div2 zero,zero,zero + 4: 6410a0fb cv.subrotmj.div2 ra,ra,ra + 8: 6421217b cv.subrotmj.div2 sp,sp,sp + c: 6484247b cv.subrotmj.div2 s0,s0,s0 + 10: 654a2a7b cv.subrotmj.div2 s4,s4,s4 + 14: 65ffaffb cv.subrotmj.div2 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..809fc2d0cbb40802d67d24cfce0ed3eccec64d1b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div2-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj.div2 x0, x0, x0 + cv.subrotmj.div2 x1, x1, x1 + cv.subrotmj.div2 x2, x2, x2 + cv.subrotmj.div2 x8, x8, x8 + cv.subrotmj.div2 x20, x20, x20 + cv.subrotmj.div2 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..fc97b73b537ee14392d353566bee663a07c87a4e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div4-fail.s +#error_output: cv-subrotmj-div4-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..73b9e0eea133ad8d6832b6923d8e952d8656b7a3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj.div4 x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj.div4 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..e9620aad3fd385234e99895753716fe500ef7a36 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj.div4 x32, x32, x32 + cv.subrotmj.div4 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..a4521a1d420d67960ba8173786aaf26dc4f33c8f --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div4-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400407b cv.subrotmj.div4 zero,zero,zero + 4: 6410c0fb cv.subrotmj.div4 ra,ra,ra + 8: 6421417b cv.subrotmj.div4 sp,sp,sp + c: 6484447b cv.subrotmj.div4 s0,s0,s0 + 10: 654a4a7b cv.subrotmj.div4 s4,s4,s4 + 14: 65ffcffb cv.subrotmj.div4 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..a6272be9b73e565ae9f1c8c3ab4c31d27e283995 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div4-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj.div4 x0, x0, x0 + cv.subrotmj.div4 x1, x1, x1 + cv.subrotmj.div4 x2, x2, x2 + cv.subrotmj.div4 x8, x8, x8 + cv.subrotmj.div4 x20, x20, x20 + cv.subrotmj.div4 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..fb4e316737daca5ccbde7073af5f48105f0e1063 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div8-fail.s +#error_output: cv-subrotmj-div8-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..558de39886db934953f7e31013f030ea94d34c83 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj.div8 x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj.div8 x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..4b3b54dd45ccd5bfc621160221b7891bb81ef4d5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj.div8 x32, x32, x32 + cv.subrotmj.div8 x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..70486913156987dde15a7a029f0f0d9c67c600f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-div8-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400607b cv.subrotmj.div8 zero,zero,zero + 4: 6410e0fb cv.subrotmj.div8 ra,ra,ra + 8: 6421617b cv.subrotmj.div8 sp,sp,sp + c: 6484647b cv.subrotmj.div8 s0,s0,s0 + 10: 654a6a7b cv.subrotmj.div8 s4,s4,s4 + 14: 65ffeffb cv.subrotmj.div8 t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..4dbabd5df19ec9e64d7894954358e7bc4f0120cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-div8-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj.div8 x0, x0, x0 + cv.subrotmj.div8 x1, x1, x1 + cv.subrotmj.div8 x2, x2, x2 + cv.subrotmj.div8 x8, x8, x8 + cv.subrotmj.div8 x20, x20, x20 + cv.subrotmj.div8 x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-fail.d b/gas/testsuite/gas/riscv/cv-subrotmj-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..6cacbb17391bbda62cea180d19ca72f51a177b99 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-fail.s +#error_output: cv-subrotmj-fail.l diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-fail.l b/gas/testsuite/gas/riscv/cv-subrotmj-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..1e7f31b122159ab15424accf23a8d2bf9dd94e6a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.subrotmj x32,x32,x32' +.*: Error: illegal operands `cv.subrotmj x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-fail.s b/gas/testsuite/gas/riscv/cv-subrotmj-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..2b05cfcbb4837f87ac1ffbe6a435b8d2c3053b00 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.subrotmj x32, x32, x32 + cv.subrotmj x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-pass.d b/gas/testsuite/gas/riscv/cv-subrotmj-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..3f07f1c1fe5710f078db266d3dd3aa225e2ce570 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-subrotmj-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6400007b cv.subrotmj zero,zero,zero + 4: 641080fb cv.subrotmj ra,ra,ra + 8: 6421017b cv.subrotmj sp,sp,sp + c: 6484047b cv.subrotmj s0,s0,s0 + 10: 654a0a7b cv.subrotmj s4,s4,s4 + 14: 65ff8ffb cv.subrotmj t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-subrotmj-pass.s b/gas/testsuite/gas/riscv/cv-subrotmj-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..838f4d3e677c496fbe1dbe4e592266cbc8060289 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-subrotmj-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.subrotmj x0, x0, x0 + cv.subrotmj x1, x1, x1 + cv.subrotmj x2, x2, x2 + cv.subrotmj x8, x8, x8 + cv.subrotmj x20, x20, x20 + cv.subrotmj x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-b-fail.d b/gas/testsuite/gas/riscv/cv-xor-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..1a244431bc716f9c81ab086a160d20a7bb0185ec --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-b-fail.s +#error_output: cv-xor-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-b-fail.l b/gas/testsuite/gas/riscv/cv-xor-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..85aba380181fd76010b06f12a063cacaf7cebfd1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.b x32,x32,x32' +.*: Error: illegal operands `cv.xor.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-b-fail.s b/gas/testsuite/gas/riscv/cv-xor-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c159d6895a9fbaf7d9c2244a302e02e112c0bb7e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.b x32, x32, x32 + cv.xor.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-b-pass.d b/gas/testsuite/gas/riscv/cv-xor-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..5b0dd5cb2300b1e1403920e1b4e7fb15abbd14dc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000107b cv.xor.b zero,zero,zero + 4: 601090fb cv.xor.b ra,ra,ra + 8: 6021117b cv.xor.b sp,sp,sp + c: 6084147b cv.xor.b s0,s0,s0 + 10: 614a1a7b cv.xor.b s4,s4,s4 + 14: 61ff9ffb cv.xor.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-b-pass.s b/gas/testsuite/gas/riscv/cv-xor-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..8300bbe3d50315bbaba86cc2f2bc28bd42812f80 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.b x0, x0, x0 + cv.xor.b x1, x1, x1 + cv.xor.b x2, x2, x2 + cv.xor.b x8, x8, x8 + cv.xor.b x20, x20, x20 + cv.xor.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-h-fail.d b/gas/testsuite/gas/riscv/cv-xor-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..9aee6b64c6f2d06f2cfd0131c90a4415540403d5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-h-fail.s +#error_output: cv-xor-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-h-fail.l b/gas/testsuite/gas/riscv/cv-xor-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..e17ec8a240d2b3be031920b3211575ad9cf535cf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.h x32,x32,x32' +.*: Error: illegal operands `cv.xor.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-h-fail.s b/gas/testsuite/gas/riscv/cv-xor-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..67f8d5c6ba0943c7c9caf5f5cf9eadb032d0756d --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.h x32, x32, x32 + cv.xor.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-h-pass.d b/gas/testsuite/gas/riscv/cv-xor-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..b6cb78d76bbedd99df6674722cd4d182b843bb33 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000007b cv.xor.h zero,zero,zero + 4: 601080fb cv.xor.h ra,ra,ra + 8: 6021017b cv.xor.h sp,sp,sp + c: 6084047b cv.xor.h s0,s0,s0 + 10: 614a0a7b cv.xor.h s4,s4,s4 + 14: 61ff8ffb cv.xor.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-h-pass.s b/gas/testsuite/gas/riscv/cv-xor-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..ac68ef1167d11aab305f1b6b55e1435822b6db1e --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.h x0, x0, x0 + cv.xor.h x1, x1, x1 + cv.xor.h x2, x2, x2 + cv.xor.h x8, x8, x8 + cv.xor.h x20, x20, x20 + cv.xor.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..bd7c5c156e4410f17cce7b6a722063c2c667995a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-b-fail.s +#error_output: cv-xor-sc-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..91a289855899a6b51d67773890a78596eaa5acd4 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sc.b x32,x32,x32' +.*: Error: illegal operands `cv.xor.sc.b x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..a6bcb1bcb78d2dc8dc1a85d297c826876eb1fa90 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.sc.b x32, x32, x32 + cv.xor.sc.b x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..c6535c8fab1d9bebda3c4615f72e8d7f124bb220 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000507b cv.xor.sc.b zero,zero,zero + 4: 6010d0fb cv.xor.sc.b ra,ra,ra + 8: 6021517b cv.xor.sc.b sp,sp,sp + c: 6084547b cv.xor.sc.b s0,s0,s0 + 10: 614a5a7b cv.xor.sc.b s4,s4,s4 + 14: 61ffdffb cv.xor.sc.b t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..ebda07f7c41d30fd3339ac085065bebe0dc228c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-b-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.sc.b x0, x0, x0 + cv.xor.sc.b x1, x1, x1 + cv.xor.sc.b x2, x2, x2 + cv.xor.sc.b x8, x8, x8 + cv.xor.sc.b x20, x20, x20 + cv.xor.sc.b x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..522bfa09423d1f7e607c7df9c0a4bdde8ad6d7fc --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-h-fail.s +#error_output: cv-xor-sc-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..b2417b49029ff9f03de2710155aa8bdf5e711bf3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sc.h x32,x32,x32' +.*: Error: illegal operands `cv.xor.sc.h x33,x33,x33' diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..26905c966b5e72597865fa518a6a7aa6ef9f6c5a --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-fail.s @@ -0,0 +1,4 @@ +target: + #Boundary Register Tests + cv.xor.sc.h x32, x32, x32 + cv.xor.sc.h x33, x33, x33 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..ee2d378de75f3aa2ee73206224698aabc654dddf --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.d @@ -0,0 +1,16 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sc-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6000407b cv.xor.sc.h zero,zero,zero + 4: 6010c0fb cv.xor.sc.h ra,ra,ra + 8: 6021417b cv.xor.sc.h sp,sp,sp + c: 6084447b cv.xor.sc.h s0,s0,s0 + 10: 614a4a7b cv.xor.sc.h s4,s4,s4 + 14: 61ffcffb cv.xor.sc.h t6,t6,t6 diff --git a/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..ee2f8c9b6a8b53cf90a182ec795ab3e99f308cff --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sc-h-pass.s @@ -0,0 +1,8 @@ +target: + #Register Tests + cv.xor.sc.h x0, x0, x0 + cv.xor.sc.h x1, x1, x1 + cv.xor.sc.h x2, x2, x2 + cv.xor.sc.h x8, x8, x8 + cv.xor.sc.h x20, x20, x20 + cv.xor.sc.h x31, x31, x31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..545b4eee78cc7d4279c52c58423ec0a485e42c52 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-b-fail.s +#error_output: cv-xor-sci-b-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..64e90bac715254781d22f2694ca791ac457986f3 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sci.b x32,x32,20' +.*: Error: illegal operands `cv.xor.sci.b x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..2b1ad6a16db6d83fd1619d5d9c71f85b70f91b06 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.xor.sci.b x32, x32, 20 + cv.xor.sci.b x33, x33, 20 + #Boundary Immediate Values Test + cv.xor.sci.b x6, x7, -33 + cv.xor.sci.b x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..e6f720d4fe91bd26f644d9fa2ed8a992dfa393e1 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-b-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6140707b cv.xor.sci.b zero,zero,20 + 4: 6140f0fb cv.xor.sci.b ra,ra,20 + 8: 6141717b cv.xor.sci.b sp,sp,20 + c: 6144747b cv.xor.sci.b s0,s0,20 + 10: 614a7a7b cv.xor.sci.b s4,s4,20 + 14: 614ffffb cv.xor.sci.b t6,t6,20 + 18: 6203f37b cv.xor.sci.b t1,t2,-32 + 1c: 6003f37b cv.xor.sci.b t1,t2,0 + 20: 61f3f37b cv.xor.sci.b t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..c46e1738dfc5afd917f5d2349e18956f56717e8c --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-b-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.xor.sci.b x0, x0, 20 + cv.xor.sci.b x1, x1, 20 + cv.xor.sci.b x2, x2, 20 + cv.xor.sci.b x8, x8, 20 + cv.xor.sci.b x20, x20, 20 + cv.xor.sci.b x31, x31, 20 + #Immediate Values Test + cv.xor.sci.b x6, x7, -32 + cv.xor.sci.b x6, x7, 0 + cv.xor.sci.b x6, x7, 31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d new file mode 100644 index 0000000000000000000000000000000000000000..c857be75b051356f147dc58c86c68e7f0d47f0f5 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-h-fail.s +#error_output: cv-xor-sci-h-fail.l diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l new file mode 100644 index 0000000000000000000000000000000000000000..a41246578585fefd98ee8e896893599275bb9e88 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*: Error: illegal operands `cv.xor.sci.h x32,x32,20' +.*: Error: illegal operands `cv.xor.sci.h x33,x33,20' +.*: Error: immediate value must be 6-bit signed, -33 is out of range +.*: Error: immediate value must be 6-bit signed, 32 is out of range diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s new file mode 100644 index 0000000000000000000000000000000000000000..c100f21df04f1615ec8a9a72cef9c50cadc70072 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-fail.s @@ -0,0 +1,7 @@ +target: + #Boundary Register Tests + cv.xor.sci.h x32, x32, 20 + cv.xor.sci.h x33, x33, 20 + #Boundary Immediate Values Test + cv.xor.sci.h x6, x7, -33 + cv.xor.sci.h x6, x7, 32 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d new file mode 100644 index 0000000000000000000000000000000000000000..9de3c0e208462dc398d7f0bbc63d5568849fd44b --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.d @@ -0,0 +1,19 @@ +#as: -march=rv32i_xcorevsimd1p0 +#source: cv-xor-sci-h-pass.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : + 0: 6140607b cv.xor.sci.h zero,zero,20 + 4: 6140e0fb cv.xor.sci.h ra,ra,20 + 8: 6141617b cv.xor.sci.h sp,sp,20 + c: 6144647b cv.xor.sci.h s0,s0,20 + 10: 614a6a7b cv.xor.sci.h s4,s4,20 + 14: 614feffb cv.xor.sci.h t6,t6,20 + 18: 6203e37b cv.xor.sci.h t1,t2,-32 + 1c: 6003e37b cv.xor.sci.h t1,t2,0 + 20: 61f3e37b cv.xor.sci.h t1,t2,31 diff --git a/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s new file mode 100644 index 0000000000000000000000000000000000000000..016147ad4badbf8656f761ec20834d98894a2079 --- /dev/null +++ b/gas/testsuite/gas/riscv/cv-xor-sci-h-pass.s @@ -0,0 +1,12 @@ +target: + #Register Tests + cv.xor.sci.h x0, x0, 20 + cv.xor.sci.h x1, x1, 20 + cv.xor.sci.h x2, x2, 20 + cv.xor.sci.h x8, x8, 20 + cv.xor.sci.h x20, x20, 20 + cv.xor.sci.h x31, x31, 20 + #Immediate Values Test + cv.xor.sci.h x6, x7, -32 + cv.xor.sci.h x6, x7, 0 + cv.xor.sci.h x6, x7, 31