Commit 722fe8fd authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARCv2: mm: THP: Implement flush_pmd_tlb_range() optimization 



Implement the TLB flush routine to evict a sepcific Super TLB entry,
vs. moving to a new ASID on every such flush.

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 12ebc158

arch/arc/include/asm/hugepage.h

+4 −0
Original line number Diff line number Diff line
@@ -74,4 +74,8 @@ extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 
#define __HAVE_ARCH_PGTABLE_WITHDRAW

extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);



#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE

extern void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,

				unsigned long end);



#endif

arch/arc/mm/tlb.c

+20 −0
Original line number Diff line number Diff line
@@ -659,6 +659,26 @@ pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp) 
	return pgtable;

}



void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,

			 unsigned long end)

{

	unsigned int cpu;

	unsigned long flags;



	local_irq_save(flags);



	cpu = smp_processor_id();



	if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {

		unsigned int asid = hw_pid(vma->vm_mm, cpu);



		/* No need to loop here: this will always be for 1 Huge Page */

		tlb_entry_erase(start | _PAGE_HW_SZ | asid);

	}



	local_irq_restore(flags);

}



#endif



/* Read the Cache Build Confuration Registers, Decode them and save into