Commit 2d3fd5ca authored by Gary Rookard's avatar Gary Rookard Committed by Greg Kroah-Hartman
Browse files

Staging: bcm: DDRInit: fixed up some commenting issues. 



I have deleated some unintelligible comments, and made a
few minor white space corrections.

Signed-off-by: Gary Alan Rookard
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 258726b3

drivers/staging/bcm/DDRInit.c

+74 −75
Original line number Diff line number Diff line
@@ -29,17 +29,17 @@ static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {/* DPLL Clock Setting * 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */

	{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020001},

	{0x0F007020, 0x04030107},

	{0x0F007024, 0x02000007},

	{0x0F007028, 0x02020202},

	{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */

	{0x0F00702c, 0x0206060a},

	{0x0F007030, 0x05000000},

	{0x0F007034, 0x00000003},

	{0x0F007038, 0x110a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */

	{0x0F00703C, 0x02101010},/* ROB - 0x02101010,//0x02101018}, */

	{0x0F007040, 0x45751200},/* ROB - 0x45751200,//0x450f1200}, */

	{0x0F007044, 0x110a0d00},/* ROB - 0x110a0d00//0x111f0d00 */

	{0x0F007038, 0x110a0200},

	{0x0F00703C, 0x02101010},

	{0x0F007040, 0x45751200},

	{0x0F007044, 0x110a0d00},

	{0x0F007048, 0x081b0306},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0000001c},
@@ -124,7 +124,6 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {/* DPLL Clock Setting * 
	{0x0f000860, 0x00000000},

	{0x0f000880, 0x000003DD},

	/* Changed source for X-bar and MIPS clock to APLL */

	/* 0x0f000840,0x0FFF1800, */

	{0x0f000840, 0x0FFF1B00},

	{0x0f000870, 0x00000002},

	{0x0F00a044, 0x1fffffff},
@@ -142,8 +141,8 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {/* DPLL Clock Setting * 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020001}, /* POP - 0x00020000 Normal 0x01020000 */

	{0x0F007020, 0x04020107},/* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020001},

	{0x0F007020, 0x04020107},

	{0x0F007024, 0x00000007},

	{0x0F007028, 0x01020201},

	{0x0F00702c, 0x0204040A},
@@ -153,7 +152,7 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {/* DPLL Clock Setting * 
	{0x0F00703C, 0x02030320},

	{0x0F007040, 0x6E7F1200},

	{0x0F007044, 0x01190A00},

	{0x0F007048, 0x06120305},/* 0x02690204 // 0x06120305 */

	{0x0F007048, 0x06120305},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0000001C},

	{0x0F007054, 0x00000000},
@@ -214,17 +213,17 @@ static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {/* DPLL Clock Setting 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */

	{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020001},

	{0x0F007020, 0x04030107},

	{0x0F007024, 0x02000007},

	{0x0F007028, 0x02020202},

	{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */

	{0x0F00702c, 0x0206060a},

	{0x0F007030, 0x05000000},

	{0x0F007034, 0x00000003},

	{0x0F007038, 0x130a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */

	{0x0F00703C, 0x02101012},/* ROB - 0x02101010,//0x02101018}, */

	{0x0F007040, 0x457D1200},/* ROB - 0x45751200,//0x450f1200}, */

	{0x0F007044, 0x11130d00},/*ROB - 0x110a0d00//0x111f0d00 */

	{0x0F007038, 0x130a0200},

	{0x0F00703C, 0x02101012},

	{0x0F007040, 0x457D1200},

	{0x0F007044, 0x11130d00},

	{0x0F007048, 0x040D0306},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0000001c},
@@ -322,8 +321,8 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {/* DPLL Clock Setting 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020000}, /* POP - 0x00020000 Normal 0x01020000 */

	{0x0F007020, 0x04020107},/* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020000},

	{0x0F007020, 0x04020107},

	{0x0F007024, 0x00000007},

	{0x0F007028, 0x01020201},

	{0x0F00702c, 0x0204040A},
@@ -333,7 +332,7 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {/* DPLL Clock Setting 
	{0x0F00703C, 0x02030320},

	{0x0F007040, 0x6E7F1200},

	{0x0F007044, 0x01190A00},

	{0x0F007048, 0x06120305},/* 0x02690204 // 0x06120305 */

	{0x0F007048, 0x06120305},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0100001C},

	{0x0F007054, 0x00000000},
@@ -377,17 +376,17 @@ static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {/* DPLL Clock Setting 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */

	{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020001},

	{0x0F007020, 0x04030107},

	{0x0F007024, 0x02000007},

	{0x0F007028, 0x02020200},

	{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */

	{0x0F00702c, 0x0206060a},

	{0x0F007030, 0x05000000},

	{0x0F007034, 0x00000003},

	{0x0F007038, 0x200a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */

	{0x0F00703C, 0x02101020},/* ROB - 0x02101010,//0x02101018, */

	{0x0F007040, 0x45711200},/* ROB - 0x45751200,//0x450f1200, */

	{0x0F007044, 0x110D0D00},/* ROB - 0x110a0d00//0x111f0d00 */

	{0x0F007038, 0x200a0200},

	{0x0F00703C, 0x02101020},

	{0x0F007040, 0x45711200},

	{0x0F007044, 0x110D0D00},

	{0x0F007048, 0x04080306},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0100001c},
@@ -437,17 +436,17 @@ static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {/* DPLL Clock Setting 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020000},/* POP - 0x00020001 Normal 0x01020001 */

	{0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020000},

	{0x0F007020, 0x04020107},

	{0x0F007024, 0x00000007},

	{0x0F007028, 0x01020200},

	{0x0F00702c, 0x0204040a},/* ROB- 0x0205050a,//0x0206060a */

	{0x0F00702c, 0x0204040a},

	{0x0F007030, 0x06000000},

	{0x0F007034, 0x00000004},

	{0x0F007038, 0x1F080200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */

	{0x0F00703C, 0x0203031F},/* ROB - 0x02101010,//0x02101018, */

	{0x0F007040, 0x6e001200},/* ROB - 0x45751200,//0x450f1200, */

	{0x0F007044, 0x011a0a00},/* ROB - 0x110a0d00//0x111f0d00 */

	{0x0F007038, 0x1F080200},

	{0x0F00703C, 0x0203031F},

	{0x0F007040, 0x6e001200},

	{0x0F007044, 0x011a0a00},

	{0x0F007048, 0x03000305},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0100001c},
@@ -615,17 +614,17 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[] = {/* DPLL Clock Settin 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020001},/* POP - 0x00020001 Normal 0x01020001 */

	{0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020001},

	{0x0F007020, 0x04030107},

	{0x0F007024, 0x02000007},

	{0x0F007028, 0x02020200},

	{0x0F00702c, 0x0206060a},/* ROB- 0x0205050a,//0x0206060a */

	{0x0F00702c, 0x0206060a},

	{0x0F007030, 0x05000000},

	{0x0F007034, 0x00000003},

	{0x0F007038, 0x190a0200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */

	{0x0F00703C, 0x02101017},/* ROB - 0x02101010,//0x02101018, */

	{0x0F007040, 0x45171200},/* ROB - 0x45751200,//0x450f1200, */

	{0x0F007044, 0x11290D00},/* ROB - 0x110a0d00//0x111f0d00 */

	{0x0F007038, 0x190a0200},

	{0x0F00703C, 0x02101017},

	{0x0F007040, 0x45171200},

	{0x0F007044, 0x11290D00},

	{0x0F007048, 0x04080306},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0100001c},
@@ -676,17 +675,17 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[] = {/* DPLL Clock Settin 
	{0x0F007010, 0x01000000},

	{0x0F007014, 0x01000100},

	{0x0F007018, 0x01000000},

	{0x0F00701c, 0x01020000},/* POP - 0x00020001 Normal 0x01020001 */

	{0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */

	{0x0F00701c, 0x01020000},

	{0x0F007020, 0x04020107},

	{0x0F007024, 0x00000007},

	{0x0F007028, 0x01020200},

	{0x0F00702c, 0x0204040a},/* ROB- 0x0205050a,//0x0206060a */

	{0x0F00702c, 0x0204040a},

	{0x0F007030, 0x06000000},

	{0x0F007034, 0x00000004},

	{0x0F007038, 0x1F080200},/* ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 */

	{0x0F00703C, 0x0203031F},/* ROB - 0x02101010,//0x02101018, */

	{0x0F007040, 0x6e001200},/* ROB - 0x45751200,//0x450f1200, */

	{0x0F007044, 0x011a0a00},/* ROB - 0x110a0d00//0x111f0d00 */

	{0x0F007038, 0x1F080200},

	{0x0F00703C, 0x0203031F},

	{0x0F007040, 0x6e001200},

	{0x0F007044, 0x011a0a00},

	{0x0F007048, 0x03000305},

	{0x0F00704c, 0x00000000},

	{0x0F007050, 0x0100001c},