From 38228d5efe18cbe45ea02ebb08b2d2a7e4b68560 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Sun, 7 Jan 2024 13:33:16 -0600 Subject: [PATCH 001/652] [libc] Fix GPU tests not running after recent patches (#77248) Summary: A previous patch added a dependency on the stack protectors, this was not built on the GPU targets so every test was disabled. It turns out that disabled tests still get targets so we need to specifically check if the it is in the target's set of entrypoints before we can use it. Another patch, because the build-bot was down, snuck in that prevented the new math tests from being run. The problem is that the `signal.h` header requires target specific definitions but was being used unconditionally. I have made changes that disable building this header if the file is not defined in the config. This required disbaling the signal_to_string utility, so that will simply be missing from targets that don't define it. --- libc/cmake/modules/LLVMLibCTestRules.cmake | 21 ++++++---- libc/include/CMakeLists.txt | 40 +++++++++++--------- libc/src/__support/StringUtil/CMakeLists.txt | 34 +++++++++-------- 3 files changed, 54 insertions(+), 41 deletions(-) diff --git a/libc/cmake/modules/LLVMLibCTestRules.cmake b/libc/cmake/modules/LLVMLibCTestRules.cmake index b69839afebf8..24f543f6e4c1 100644 --- a/libc/cmake/modules/LLVMLibCTestRules.cmake +++ b/libc/cmake/modules/LLVMLibCTestRules.cmake @@ -498,10 +498,14 @@ function(add_integration_test test_name) libc.src.string.memcpy libc.src.string.memmove libc.src.string.memset - # __stack_chk_fail should always be included to allow building libc with - # stack protector. - libc.src.compiler.__stack_chk_fail ) + + if(libc.src.compiler.__stack_chk_fail IN_LIST TARGET_LLVMLIBC_ENTRYPOINTS) + # __stack_chk_fail should always be included if supported to allow building + # libc with the stack protector enabled. + list(APPEND fq_deps_list libc.src.compiler.__stack_chk_fail) + endif() + list(REMOVE_DUPLICATES fq_deps_list) # TODO: Instead of gathering internal object files from entrypoints, @@ -668,12 +672,15 @@ function(add_libc_hermetic_test test_name) libc.src.string.memmove libc.src.string.memset libc.src.__support.StringUtil.error_to_string - # __stack_chk_fail should always be included to allow building libc with - # stack protector. - libc.src.compiler.__stack_chk_fail ) - if(TARGET libc.src.time.clock) + if(libc.src.compiler.__stack_chk_fail IN_LIST TARGET_LLVMLIBC_ENTRYPOINTS) + # __stack_chk_fail should always be included if supported to allow building + # libc with the stack protector enabled. + list(APPEND fq_deps_list libc.src.compiler.__stack_chk_fail) + endif() + + if(libc.src.time.clock IN_LIST TARGET_LLVMLIBC_ENTRYPOINTS) # We will link in the 'clock' implementation if it exists for test timing. list(APPEND fq_deps_list libc.src.time.clock) endif() diff --git a/libc/include/CMakeLists.txt b/libc/include/CMakeLists.txt index 59c6c4a9bb42..c93693cfc11f 100644 --- a/libc/include/CMakeLists.txt +++ b/libc/include/CMakeLists.txt @@ -184,24 +184,28 @@ add_gen_header( .llvm-libc-macros.generic_error_number_macros ) -add_gen_header( - signal - DEF_FILE signal.h.def - PARAMS - platform_signal=../config/${LIBC_TARGET_OS}/signal.h.in - GEN_HDR signal.h - DATA_FILES - ../config/${LIBC_TARGET_OS}/signal.h.in - DEPENDS - .llvm-libc-macros.signal_macros - .llvm-libc-types.sig_atomic_t - .llvm-libc-types.sigset_t - .llvm-libc-types.struct_sigaction - .llvm-libc-types.union_sigval - .llvm-libc-types.siginfo_t - .llvm-libc-types.stack_t - .llvm-libc-types.pid_t -) +if(EXISTS "${LIBC_SOURCE_DIR}/config/${LIBC_TARGET_OS}/signal.h.in") + add_gen_header( + signal + DEF_FILE signal.h.def + PARAMS + platform_signal=${LIBC_SOURCE_DIR}/config/${LIBC_TARGET_OS}/signal.h.in + GEN_HDR signal.h + DATA_FILES + ${LIBC_SOURCE_DIR}/config/${LIBC_TARGET_OS}/signal.h.in + DEPENDS + .llvm-libc-macros.signal_macros + .llvm-libc-types.sig_atomic_t + .llvm-libc-types.sigset_t + .llvm-libc-types.struct_sigaction + .llvm-libc-types.union_sigval + .llvm-libc-types.siginfo_t + .llvm-libc-types.stack_t + .llvm-libc-types.pid_t + ) +else() + message(STATUS "Skipping header signal.h as the target config is missing") +endif() add_gen_header( stdio diff --git a/libc/src/__support/StringUtil/CMakeLists.txt b/libc/src/__support/StringUtil/CMakeLists.txt index c053966d5418..41b20dc2cb11 100644 --- a/libc/src/__support/StringUtil/CMakeLists.txt +++ b/libc/src/__support/StringUtil/CMakeLists.txt @@ -51,19 +51,21 @@ add_object_library( libc.src.__support.integer_to_string ) -add_object_library( - signal_to_string - HDRS - signal_to_string.h - SRCS - signal_to_string.cpp - DEPENDS - .message_mapper - .platform_signals - libc.include.signal - libc.src.__support.common - libc.src.__support.CPP.span - libc.src.__support.CPP.string_view - libc.src.__support.CPP.stringstream - libc.src.__support.integer_to_string -) +if(TARGET libc.include.signal) + add_object_library( + signal_to_string + HDRS + signal_to_string.h + SRCS + signal_to_string.cpp + DEPENDS + .message_mapper + .platform_signals + libc.include.signal + libc.src.__support.common + libc.src.__support.CPP.span + libc.src.__support.CPP.string_view + libc.src.__support.CPP.stringstream + libc.src.__support.integer_to_string + ) +endif() -- GitLab From fece9818abce9339e3a46ce174c662602e32d593 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Sun, 7 Jan 2024 13:40:10 -0600 Subject: [PATCH 002/652] [libc] Attempt to fix incorrect pathin on Linux builds --- libc/include/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/include/CMakeLists.txt b/libc/include/CMakeLists.txt index c93693cfc11f..2c2d1b9b0fd1 100644 --- a/libc/include/CMakeLists.txt +++ b/libc/include/CMakeLists.txt @@ -189,10 +189,10 @@ if(EXISTS "${LIBC_SOURCE_DIR}/config/${LIBC_TARGET_OS}/signal.h.in") signal DEF_FILE signal.h.def PARAMS - platform_signal=${LIBC_SOURCE_DIR}/config/${LIBC_TARGET_OS}/signal.h.in + platform_signal=../config/${LIBC_TARGET_OS}/signal.h.in GEN_HDR signal.h DATA_FILES - ${LIBC_SOURCE_DIR}/config/${LIBC_TARGET_OS}/signal.h.in + ../config/${LIBC_TARGET_OS}/signal.h.in DEPENDS .llvm-libc-macros.signal_macros .llvm-libc-types.sig_atomic_t -- GitLab From c5e35986d8064775182b03a7e1a7e02f1cf7e4a9 Mon Sep 17 00:00:00 2001 From: Nicholas Mosier Date: Sun, 7 Jan 2024 11:59:49 -0800 Subject: [PATCH 003/652] [lld][ELF][X86] Add missing X86_64_TPOFF64 case in switches (#77208) Close #77201. When linking code with a R_X86_64_TPOFF64 relocation, LLD exits with an 'unknown reloaction' error message due to two missing cases in relocation switch statements. This patch adds in those cases so that LLD successfully links code R_X86_64_TPOFF64 relocations. --- lld/ELF/Arch/X86_64.cpp | 2 ++ lld/test/ELF/x86-64-tls-pie.s | 18 +++++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/lld/ELF/Arch/X86_64.cpp b/lld/ELF/Arch/X86_64.cpp index 2135ac234864..c28e01e48195 100644 --- a/lld/ELF/Arch/X86_64.cpp +++ b/lld/ELF/Arch/X86_64.cpp @@ -358,6 +358,7 @@ RelExpr X86_64::getRelExpr(RelType type, const Symbol &s, case R_X86_64_DTPOFF64: return R_DTPREL; case R_X86_64_TPOFF32: + case R_X86_64_TPOFF64: return R_TPREL; case R_X86_64_TLSDESC_CALL: return R_TLSDESC_CALL; @@ -791,6 +792,7 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { write32le(loc, val); break; case R_X86_64_64: + case R_X86_64_TPOFF64: case R_X86_64_DTPOFF64: case R_X86_64_PC64: case R_X86_64_SIZE64: diff --git a/lld/test/ELF/x86-64-tls-pie.s b/lld/test/ELF/x86-64-tls-pie.s index 5ef0f54f435d..71caa0f49803 100644 --- a/lld/test/ELF/x86-64-tls-pie.s +++ b/lld/test/ELF/x86-64-tls-pie.s @@ -1,14 +1,23 @@ # REQUIRES: x86 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-cloudabi %s -o %t1.o # RUN: ld.lld -pie %t1.o -o %t -# RUN: llvm-readobj -r %t | FileCheck %s +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOCS %s +# RUN: llvm-objdump -d --no-show-raw-insn --no-print-imm-hex --no-leading-addr %t1.o | FileCheck --check-prefix=DIS %s # Bug 27174: R_X86_64_TPOFF32 and R_X86_64_GOTTPOFF relocations should # be eliminated when building a PIE executable, as the static TLS layout # is fixed. # -# CHECK: Relocations [ -# CHECK-NEXT: ] +# RELOCS: Relocations [ +# RELOCS-NEXT: ] +# +# DIS: <_start>: +# DIS-NEXT: movq %fs:0, %rax +# DIS-NEXT: movl $3, (%rax) +# DIS-NEXT: movq %fs:0, %rdx +# DIS-NEXT: movq (%rip), %rcx +# DIS-NEXT: movl $3, (%rdx,%rcx) +# DIS-NEXT: movabsq 0, %rax .globl _start _start: @@ -19,6 +28,9 @@ _start: movq i@GOTTPOFF(%rip), %rcx movl $3, (%rdx,%rcx) + # This additionally tests support for R_X86_64_TPOFF64 relocations. + movabs i@TPOFF, %rax + .section .tbss.i,"awT",@nobits .globl i i: -- GitLab From eabaee0c59110d0e11b33a69db54ccda526b35fd Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sun, 7 Jan 2024 12:09:44 -0800 Subject: [PATCH 004/652] [RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467) R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530 `call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not useful and can be removed now (matching AArch64 and PowerPC). GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09 (70f35d72ef04cd23771875c1661c9975044a749c). Without this patch, unconditionally changing MO_CALL to MO_PLT could create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler and GNU assembler. --- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 +- .../Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 2 - llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll | 24 +- llvm/test/CodeGen/RISCV/addrspacecast.ll | 4 +- llvm/test/CodeGen/RISCV/aext-to-sext.ll | 2 +- llvm/test/CodeGen/RISCV/alloca.ll | 6 +- llvm/test/CodeGen/RISCV/analyze-branch.ll | 8 +- llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 180 +-- llvm/test/CodeGen/RISCV/atomic-load-store.ll | 144 +-- llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll | 18 +- llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll | 20 +- llvm/test/CodeGen/RISCV/atomic-rmw.ll | 1070 ++++++++--------- llvm/test/CodeGen/RISCV/atomic-signext.ll | 278 ++--- .../CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll | 36 +- llvm/test/CodeGen/RISCV/bf16-promote.ll | 14 +- llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll | 68 +- llvm/test/CodeGen/RISCV/bfloat-convert.ll | 74 +- llvm/test/CodeGen/RISCV/bfloat-frem.ll | 4 +- llvm/test/CodeGen/RISCV/bfloat-mem.ll | 8 +- llvm/test/CodeGen/RISCV/bfloat.ll | 76 +- llvm/test/CodeGen/RISCV/bittest.ll | 200 +-- llvm/test/CodeGen/RISCV/byval.ll | 2 +- .../test/CodeGen/RISCV/callee-saved-fpr32s.ll | 12 +- .../test/CodeGen/RISCV/callee-saved-fpr64s.ll | 8 +- llvm/test/CodeGen/RISCV/callee-saved-gprs.ll | 32 +- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 96 +- .../RISCV/calling-conv-ilp32-ilp32f-common.ll | 16 +- ...calling-conv-ilp32-ilp32f-ilp32d-common.ll | 48 +- llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll | 16 +- .../test/CodeGen/RISCV/calling-conv-ilp32d.ll | 12 +- .../calling-conv-ilp32f-ilp32d-common.ll | 10 +- .../RISCV/calling-conv-lp64-lp64f-common.ll | 6 +- .../calling-conv-lp64-lp64f-lp64d-common.ll | 24 +- llvm/test/CodeGen/RISCV/calling-conv-lp64.ll | 16 +- .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 4 +- .../CodeGen/RISCV/calling-conv-sext-zext.ll | 36 +- .../RISCV/calling-conv-vector-on-stack.ll | 2 +- llvm/test/CodeGen/RISCV/calls.ll | 20 +- llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll | 48 +- llvm/test/CodeGen/RISCV/condops.ll | 36 +- llvm/test/CodeGen/RISCV/copysign-casts.ll | 10 +- llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll | 60 +- .../CodeGen/RISCV/ctz_zero_return_test.ll | 50 +- llvm/test/CodeGen/RISCV/div-by-constant.ll | 10 +- llvm/test/CodeGen/RISCV/div.ll | 112 +- .../test/CodeGen/RISCV/double-arith-strict.ll | 96 +- llvm/test/CodeGen/RISCV/double-arith.ll | 160 +-- llvm/test/CodeGen/RISCV/double-br-fcmp.ll | 136 +-- .../test/CodeGen/RISCV/double-calling-conv.ll | 12 +- .../CodeGen/RISCV/double-convert-strict.ll | 92 +- llvm/test/CodeGen/RISCV/double-convert.ll | 264 ++-- llvm/test/CodeGen/RISCV/double-fcmp-strict.ll | 128 +- llvm/test/CodeGen/RISCV/double-fcmp.ll | 64 +- llvm/test/CodeGen/RISCV/double-frem.ll | 8 +- .../CodeGen/RISCV/double-intrinsics-strict.ll | 284 ++--- llvm/test/CodeGen/RISCV/double-intrinsics.ll | 230 ++-- llvm/test/CodeGen/RISCV/double-mem.ll | 16 +- .../CodeGen/RISCV/double-previous-failure.ll | 12 +- .../CodeGen/RISCV/double-round-conv-sat.ll | 96 +- llvm/test/CodeGen/RISCV/double-round-conv.ll | 100 +- .../RISCV/double-stack-spill-restore.ll | 8 +- llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll | 4 +- llvm/test/CodeGen/RISCV/emutls.ll | 12 +- .../RISCV/exception-pointer-register.ll | 12 +- llvm/test/CodeGen/RISCV/fastcc-float.ll | 2 +- llvm/test/CodeGen/RISCV/fastcc-int.ll | 4 +- .../CodeGen/RISCV/fastcc-without-f-reg.ll | 24 +- llvm/test/CodeGen/RISCV/fli-licm.ll | 4 +- llvm/test/CodeGen/RISCV/float-arith-strict.ll | 96 +- llvm/test/CodeGen/RISCV/float-arith.ll | 164 +-- .../RISCV/float-bit-preserving-dagcombines.ll | 48 +- llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 160 +-- .../CodeGen/RISCV/float-convert-strict.ll | 84 +- llvm/test/CodeGen/RISCV/float-convert.ll | 256 ++-- llvm/test/CodeGen/RISCV/float-fcmp-strict.ll | 128 +- llvm/test/CodeGen/RISCV/float-fcmp.ll | 64 +- llvm/test/CodeGen/RISCV/float-frem.ll | 12 +- .../CodeGen/RISCV/float-intrinsics-strict.ll | 284 ++--- llvm/test/CodeGen/RISCV/float-intrinsics.ll | 220 ++-- llvm/test/CodeGen/RISCV/float-mem.ll | 16 +- .../CodeGen/RISCV/float-round-conv-sat.ll | 48 +- llvm/test/CodeGen/RISCV/float-round-conv.ll | 40 +- llvm/test/CodeGen/RISCV/float-zfa.ll | 2 +- llvm/test/CodeGen/RISCV/fmax-fmin.ll | 36 +- .../test/CodeGen/RISCV/fold-addi-loadstore.ll | 8 +- llvm/test/CodeGen/RISCV/forced-atomics.ll | 584 ++++----- llvm/test/CodeGen/RISCV/fp128.ll | 6 +- llvm/test/CodeGen/RISCV/fp16-promote.ll | 20 +- llvm/test/CodeGen/RISCV/fpclamptosat.ll | 212 ++-- llvm/test/CodeGen/RISCV/frame-info.ll | 24 +- llvm/test/CodeGen/RISCV/frame.ll | 4 +- .../CodeGen/RISCV/frameaddr-returnaddr.ll | 4 +- llvm/test/CodeGen/RISCV/ghccc-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/ghccc-rv64.ll | 2 +- .../test/CodeGen/RISCV/ghccc-without-f-reg.ll | 4 +- llvm/test/CodeGen/RISCV/half-arith.ll | 704 +++++------ llvm/test/CodeGen/RISCV/half-br-fcmp.ll | 272 ++--- .../test/CodeGen/RISCV/half-convert-strict.ll | 88 +- llvm/test/CodeGen/RISCV/half-convert.ll | 874 +++++++------- llvm/test/CodeGen/RISCV/half-frem.ll | 16 +- llvm/test/CodeGen/RISCV/half-intrinsics.ll | 536 ++++----- llvm/test/CodeGen/RISCV/half-mem.ll | 32 +- .../test/CodeGen/RISCV/half-round-conv-sat.ll | 96 +- llvm/test/CodeGen/RISCV/half-round-conv.ll | 80 +- .../CodeGen/RISCV/hoist-global-addr-base.ll | 4 +- .../CodeGen/RISCV/interrupt-attr-callee.ll | 18 +- .../CodeGen/RISCV/interrupt-attr-nocall.ll | 12 +- llvm/test/CodeGen/RISCV/interrupt-attr.ll | 24 +- .../RISCV/intrinsic-cttz-elts-vscale.ll | 2 +- llvm/test/CodeGen/RISCV/libcall-tail-calls.ll | 136 +-- llvm/test/CodeGen/RISCV/llvm.exp10.ll | 212 ++-- llvm/test/CodeGen/RISCV/llvm.frexp.ll | 348 +++--- ...e-outliner-and-machine-copy-propagation.ll | 20 +- .../CodeGen/RISCV/machine-outliner-throw.ll | 8 +- .../RISCV/machinelicm-address-pseudos.ll | 4 +- .../CodeGen/RISCV/macro-fusion-lui-addi.ll | 6 +- llvm/test/CodeGen/RISCV/mem.ll | 2 +- llvm/test/CodeGen/RISCV/mem64.ll | 2 +- llvm/test/CodeGen/RISCV/memcpy.ll | 20 +- llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll | 8 +- llvm/test/CodeGen/RISCV/mul.ll | 54 +- llvm/test/CodeGen/RISCV/nest-register.ll | 6 +- llvm/test/CodeGen/RISCV/nomerge.ll | 10 +- .../RISCV/out-of-reach-emergency-slot.mir | 4 +- .../test/CodeGen/RISCV/overflow-intrinsics.ll | 8 +- llvm/test/CodeGen/RISCV/pr51206.ll | 2 +- llvm/test/CodeGen/RISCV/pr63816.ll | 16 +- llvm/test/CodeGen/RISCV/push-pop-popret.ll | 144 +-- .../RISCV/reduce-unnecessary-extension.ll | 16 +- ...regalloc-last-chance-recoloring-failure.ll | 4 +- llvm/test/CodeGen/RISCV/rem.ll | 72 +- llvm/test/CodeGen/RISCV/remat.ll | 8 +- .../CodeGen/RISCV/rv32i-rv64i-float-double.ll | 16 +- llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll | 28 +- llvm/test/CodeGen/RISCV/rv32xtheadbb.ll | 12 +- llvm/test/CodeGen/RISCV/rv32zbb.ll | 30 +- llvm/test/CodeGen/RISCV/rv64-large-stack.ll | 2 +- llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll | 50 +- .../CodeGen/RISCV/rv64-legal-i32/mem64.ll | 2 +- llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll | 32 +- .../RISCV/rv64-legal-i32/rv64xtheadbb.ll | 30 +- .../CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll | 28 +- .../CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll | 4 +- .../test/CodeGen/RISCV/rv64i-complex-float.ll | 4 +- .../CodeGen/RISCV/rv64i-double-softfloat.ll | 8 +- .../CodeGen/RISCV/rv64i-single-softfloat.ll | 4 +- llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 22 +- llvm/test/CodeGen/RISCV/rv64zbb.ll | 36 +- llvm/test/CodeGen/RISCV/rv64zbs.ll | 4 +- .../CodeGen/RISCV/rvv/calling-conv-fastcc.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/calling-conv.ll | 4 +- .../rvv/fixed-vectors-calling-conv-fastcc.ll | 16 +- .../RISCV/rvv/fixed-vectors-calling-conv.ll | 40 +- .../rvv/fixed-vectors-emergency-slot.mir | 2 +- .../RISCV/rvv/fixed-vectors-extract.ll | 4 +- .../CodeGen/RISCV/rvv/fixed-vectors-llrint.ll | 100 +- .../rvv/fixed-vectors-reduction-int-vp.ll | 28 +- .../CodeGen/RISCV/rvv/fpclamptosat_vec.ll | 480 ++++---- .../RISCV/rvv/large-rvv-stack-size.mir | 2 +- llvm/test/CodeGen/RISCV/rvv/localvar.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/memory-args.ll | 2 +- .../CodeGen/RISCV/rvv/no-reserved-frame.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/pr63596.ll | 8 +- .../CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll | 2 +- .../RISCV/rvv/rv32-spill-vector-csr.ll | 4 +- .../RISCV/rvv/rv64-spill-vector-csr.ll | 6 +- .../test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll | 2 +- .../CodeGen/RISCV/rvv/rvv-stack-align.mir | 12 +- .../CodeGen/RISCV/rvv/scalar-stack-align.ll | 4 +- .../RISCV/rvv/vsetvli-insert-crossbb.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll | 4 +- llvm/test/CodeGen/RISCV/select-and.ll | 8 +- llvm/test/CodeGen/RISCV/select-cc.ll | 4 +- llvm/test/CodeGen/RISCV/select-or.ll | 8 +- llvm/test/CodeGen/RISCV/setcc-logic.ll | 112 +- llvm/test/CodeGen/RISCV/sextw-removal.ll | 64 +- llvm/test/CodeGen/RISCV/shadowcallstack.ll | 28 +- llvm/test/CodeGen/RISCV/shifts.ll | 6 +- .../CodeGen/RISCV/short-forward-branch-opt.ll | 16 +- .../CodeGen/RISCV/shrinkwrap-jump-table.ll | 12 +- llvm/test/CodeGen/RISCV/shrinkwrap.ll | 16 +- llvm/test/CodeGen/RISCV/split-sp-adjust.ll | 4 +- .../CodeGen/RISCV/split-udiv-by-constant.ll | 8 +- .../CodeGen/RISCV/split-urem-by-constant.ll | 8 +- llvm/test/CodeGen/RISCV/srem-lkk.ll | 30 +- .../CodeGen/RISCV/srem-seteq-illegal-types.ll | 32 +- llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 110 +- .../CodeGen/RISCV/stack-protector-target.ll | 4 +- ...realignment-with-variable-sized-objects.ll | 4 +- llvm/test/CodeGen/RISCV/stack-realignment.ll | 64 +- llvm/test/CodeGen/RISCV/stack-slot-size.ll | 12 +- llvm/test/CodeGen/RISCV/stack-store-check.ll | 24 +- llvm/test/CodeGen/RISCV/tls-models.ll | 8 +- ...unfold-masked-merge-scalar-variablemask.ll | 8 +- llvm/test/CodeGen/RISCV/urem-lkk.ll | 22 +- .../CodeGen/RISCV/urem-seteq-illegal-types.ll | 24 +- llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 102 +- llvm/test/CodeGen/RISCV/vararg.ll | 60 +- llvm/test/CodeGen/RISCV/vlenb.ll | 4 +- llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll | 8 +- llvm/test/CodeGen/RISCV/zcmp-with-float.ll | 12 +- .../RISCV/zfh-half-intrinsics-strict.ll | 96 +- .../RISCV/zfhmin-half-intrinsics-strict.ll | 96 +- llvm/test/MC/RISCV/function-call.s | 4 +- llvm/test/MC/RISCV/tail-call.s | 2 +- 205 files changed, 6581 insertions(+), 6584 deletions(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 23c2b63c8c83..d616aaeddf41 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2035,9 +2035,8 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) { SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size()); - RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL; - if (Identifier.consume_back("@plt")) - Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; + RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; + (void)Identifier.consume_back("@plt"); MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp index d67351102bc1..64ddae61b1bc 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp @@ -41,8 +41,6 @@ void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { if (HasVariant) OS << '%' << getVariantKindName(getKind()) << '('; Expr->print(OS, MAI); - if (Kind == VK_RISCV_CALL_PLT) - OS << "@plt"; if (HasVariant) OS << ')'; } diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll index 501a3c0ce743..7b110e562e05 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll @@ -167,7 +167,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; RV32-NEXT: andi a0, a0, -16 ; RV32-NEXT: sub a0, sp, a0 ; RV32-NEXT: mv sp, a0 -; RV32-NEXT: call notdead@plt +; RV32-NEXT: call notdead ; RV32-NEXT: mv a0, s1 ; RV32-NEXT: addi sp, s0, -16 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -204,7 +204,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; RV64-NEXT: andi a0, a0, -16 ; RV64-NEXT: sub a0, sp, a0 ; RV64-NEXT: mv sp, a0 -; RV64-NEXT: call notdead@plt +; RV64-NEXT: call notdead ; RV64-NEXT: mv a0, s1 ; RV64-NEXT: addi sp, s0, -32 ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -229,7 +229,7 @@ define void @va1_caller() nounwind { ; RV32-NEXT: lui a3, 261888 ; RV32-NEXT: li a4, 2 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call va1@plt +; RV32-NEXT: call va1 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -241,7 +241,7 @@ define void @va1_caller() nounwind { ; LP64-NEXT: lui a0, %hi(.LCPI3_0) ; LP64-NEXT: ld a1, %lo(.LCPI3_0)(a0) ; LP64-NEXT: li a2, 2 -; LP64-NEXT: call va1@plt +; LP64-NEXT: call va1 ; LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-NEXT: addi sp, sp, 16 ; LP64-NEXT: ret @@ -255,7 +255,7 @@ define void @va1_caller() nounwind { ; LP64F-NEXT: fmv.d.x fa5, a0 ; LP64F-NEXT: li a2, 2 ; LP64F-NEXT: fmv.x.d a1, fa5 -; LP64F-NEXT: call va1@plt +; LP64F-NEXT: call va1 ; LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64F-NEXT: addi sp, sp, 16 ; LP64F-NEXT: ret @@ -269,7 +269,7 @@ define void @va1_caller() nounwind { ; LP64D-NEXT: fmv.d.x fa5, a0 ; LP64D-NEXT: li a2, 2 ; LP64D-NEXT: fmv.x.d a1, fa5 -; LP64D-NEXT: call va1@plt +; LP64D-NEXT: call va1 ; LP64D-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64D-NEXT: addi sp, sp, 16 ; LP64D-NEXT: ret @@ -473,7 +473,7 @@ define void @va2_caller() nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a1, 1 -; RV32-NEXT: call va2@plt +; RV32-NEXT: call va2 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -483,7 +483,7 @@ define void @va2_caller() nounwind { ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: li a1, 1 -; RV64-NEXT: call va2@plt +; RV64-NEXT: call va2 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -701,7 +701,7 @@ define void @va3_caller() nounwind { ; RV32-NEXT: li a0, 2 ; RV32-NEXT: li a1, 1111 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call va3@plt +; RV32-NEXT: call va3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -714,7 +714,7 @@ define void @va3_caller() nounwind { ; RV64-NEXT: addiw a2, a0, -480 ; RV64-NEXT: li a0, 2 ; RV64-NEXT: li a1, 1111 -; RV64-NEXT: call va3@plt +; RV64-NEXT: call va3 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -749,7 +749,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV32-NEXT: lw s0, 0(a0) ; RV32-NEXT: sw a2, 0(a1) ; RV32-NEXT: lw a0, 0(sp) -; RV32-NEXT: call notdead@plt +; RV32-NEXT: call notdead ; RV32-NEXT: lw a0, 4(sp) ; RV32-NEXT: addi a0, a0, 3 ; RV32-NEXT: andi a0, a0, -4 @@ -803,7 +803,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV64-NEXT: lwu a1, 0(sp) ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: or a0, a0, a1 -; RV64-NEXT: call notdead@plt +; RV64-NEXT: call notdead ; RV64-NEXT: ld a0, 8(sp) ; RV64-NEXT: addi a0, a0, 3 ; RV64-NEXT: andi a0, a0, -4 diff --git a/llvm/test/CodeGen/RISCV/addrspacecast.ll b/llvm/test/CodeGen/RISCV/addrspacecast.ll index 7fe041a8ac6a..e55a57a51678 100644 --- a/llvm/test/CodeGen/RISCV/addrspacecast.ll +++ b/llvm/test/CodeGen/RISCV/addrspacecast.ll @@ -26,7 +26,7 @@ define void @cast1(ptr %ptr) { ; RV32I-NEXT: .cfi_def_cfa_offset 16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -37,7 +37,7 @@ define void @cast1(ptr %ptr) { ; RV64I-NEXT: .cfi_def_cfa_offset 16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 -; RV64I-NEXT: call foo@plt +; RV64I-NEXT: call foo ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll index 09803012001c..888ea666d713 100644 --- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll +++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll @@ -19,7 +19,7 @@ define void @quux(i32 signext %arg, i32 signext %arg1) nounwind { ; RV64I-NEXT: subw s0, a1, a0 ; RV64I-NEXT: .LBB0_2: # %bb2 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: call hoge@plt +; RV64I-NEXT: call hoge ; RV64I-NEXT: addiw s0, s0, -1 ; RV64I-NEXT: bnez s0, .LBB0_2 ; RV64I-NEXT: # %bb.3: diff --git a/llvm/test/CodeGen/RISCV/alloca.ll b/llvm/test/CodeGen/RISCV/alloca.ll index 34cac429f305..bcb0592c18f5 100644 --- a/llvm/test/CodeGen/RISCV/alloca.ll +++ b/llvm/test/CodeGen/RISCV/alloca.ll @@ -18,7 +18,7 @@ define void @simple_alloca(i32 %n) nounwind { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: call notdead@plt +; RV32I-NEXT: call notdead ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -45,7 +45,7 @@ define void @scoped_alloca(i32 %n) nounwind { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: call notdead@plt +; RV32I-NEXT: call notdead ; RV32I-NEXT: mv sp, s1 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -91,7 +91,7 @@ define void @alloca_callframe(i32 %n) nounwind { ; RV32I-NEXT: li a6, 7 ; RV32I-NEXT: li a7, 8 ; RV32I-NEXT: sw t0, 0(sp) -; RV32I-NEXT: call func@plt +; RV32I-NEXT: call func ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/analyze-branch.ll b/llvm/test/CodeGen/RISCV/analyze-branch.ll index e33e6b65c6f1..768a11a71706 100644 --- a/llvm/test/CodeGen/RISCV/analyze-branch.ll +++ b/llvm/test/CodeGen/RISCV/analyze-branch.ll @@ -20,13 +20,13 @@ define void @test_bcc_fallthrough_taken(i32 %in) nounwind { ; RV32I-NEXT: li a1, 42 ; RV32I-NEXT: bne a0, a1, .LBB0_3 ; RV32I-NEXT: # %bb.1: # %true -; RV32I-NEXT: call test_true@plt +; RV32I-NEXT: call test_true ; RV32I-NEXT: .LBB0_2: # %true ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB0_3: # %false -; RV32I-NEXT: call test_false@plt +; RV32I-NEXT: call test_false ; RV32I-NEXT: j .LBB0_2 %tst = icmp eq i32 %in, 42 br i1 %tst, label %true, label %false, !prof !0 @@ -52,13 +52,13 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind { ; RV32I-NEXT: li a1, 42 ; RV32I-NEXT: beq a0, a1, .LBB1_3 ; RV32I-NEXT: # %bb.1: # %false -; RV32I-NEXT: call test_false@plt +; RV32I-NEXT: call test_false ; RV32I-NEXT: .LBB1_2: # %true ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB1_3: # %true -; RV32I-NEXT: call test_true@plt +; RV32I-NEXT: call test_true ; RV32I-NEXT: j .LBB1_2 %tst = icmp eq i32 %in, 42 br i1 %tst, label %true, label %false, !prof !1 diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll index eea4cb72938a..46ed01b11584 100644 --- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll @@ -21,7 +21,7 @@ define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -57,7 +57,7 @@ define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -97,7 +97,7 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -156,7 +156,7 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -219,7 +219,7 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -278,7 +278,7 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -341,7 +341,7 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -400,7 +400,7 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -463,7 +463,7 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -522,7 +522,7 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -585,7 +585,7 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -644,7 +644,7 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -707,7 +707,7 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -766,7 +766,7 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -829,7 +829,7 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -865,7 +865,7 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -905,7 +905,7 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -941,7 +941,7 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -981,7 +981,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1017,7 +1017,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1057,7 +1057,7 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounw ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1094,7 +1094,7 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounw ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1135,7 +1135,7 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1196,7 +1196,7 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1261,7 +1261,7 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1322,7 +1322,7 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1387,7 +1387,7 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1448,7 +1448,7 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1513,7 +1513,7 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1574,7 +1574,7 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1639,7 +1639,7 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1700,7 +1700,7 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1765,7 +1765,7 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1826,7 +1826,7 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1891,7 +1891,7 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1928,7 +1928,7 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1969,7 +1969,7 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2006,7 +2006,7 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2047,7 +2047,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2084,7 +2084,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2125,7 +2125,7 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2149,7 +2149,7 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2178,7 +2178,7 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2213,7 +2213,7 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2254,7 +2254,7 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2289,7 +2289,7 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2330,7 +2330,7 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2365,7 +2365,7 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2406,7 +2406,7 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2441,7 +2441,7 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2482,7 +2482,7 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2517,7 +2517,7 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2558,7 +2558,7 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2593,7 +2593,7 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2634,7 +2634,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2658,7 +2658,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2687,7 +2687,7 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 2 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2711,7 +2711,7 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2740,7 +2740,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2764,7 +2764,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2796,7 +2796,7 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounw ; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2812,7 +2812,7 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounw ; RV32IA-NEXT: mv a3, a4 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -2825,7 +2825,7 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounw ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2857,7 +2857,7 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2874,7 +2874,7 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -2887,7 +2887,7 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2930,7 +2930,7 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a6 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2947,7 +2947,7 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a6 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -2960,7 +2960,7 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3003,7 +3003,7 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3020,7 +3020,7 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3033,7 +3033,7 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3076,7 +3076,7 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a6 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3093,7 +3093,7 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a6 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3106,7 +3106,7 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3149,7 +3149,7 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3166,7 +3166,7 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3179,7 +3179,7 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3222,7 +3222,7 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a6 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3239,7 +3239,7 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a6 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3252,7 +3252,7 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3295,7 +3295,7 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3312,7 +3312,7 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3325,7 +3325,7 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3357,7 +3357,7 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a6 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3374,7 +3374,7 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a6 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3387,7 +3387,7 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 2 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3419,7 +3419,7 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a3, a6 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3436,7 +3436,7 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a3, a6 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3449,7 +3449,7 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll index d3488ebed89f..2d1fc21cda89 100644 --- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll +++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll @@ -30,7 +30,7 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_1@plt +; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -45,7 +45,7 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_1@plt +; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -64,7 +64,7 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_1@plt +; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -79,7 +79,7 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_1@plt +; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -98,7 +98,7 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 2 -; RV32I-NEXT: call __atomic_load_1@plt +; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -119,7 +119,7 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 2 -; RV64I-NEXT: call __atomic_load_1@plt +; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -166,7 +166,7 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __atomic_load_1@plt +; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -189,7 +189,7 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __atomic_load_1@plt +; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -242,7 +242,7 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_2@plt +; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -257,7 +257,7 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_2@plt +; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -276,7 +276,7 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_2@plt +; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -291,7 +291,7 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_2@plt +; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -310,7 +310,7 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 2 -; RV32I-NEXT: call __atomic_load_2@plt +; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -331,7 +331,7 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 2 -; RV64I-NEXT: call __atomic_load_2@plt +; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -378,7 +378,7 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __atomic_load_2@plt +; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -401,7 +401,7 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __atomic_load_2@plt +; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -454,7 +454,7 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_4@plt +; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -469,7 +469,7 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_4@plt +; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -488,7 +488,7 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_4@plt +; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -503,7 +503,7 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_4@plt +; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -522,7 +522,7 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 2 -; RV32I-NEXT: call __atomic_load_4@plt +; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -543,7 +543,7 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 2 -; RV64I-NEXT: call __atomic_load_4@plt +; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -590,7 +590,7 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __atomic_load_4@plt +; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -613,7 +613,7 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __atomic_load_4@plt +; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -666,7 +666,7 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_8@plt +; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -676,7 +676,7 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a1, 0 -; RV32IA-NEXT: call __atomic_load_8@plt +; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -686,7 +686,7 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_8@plt +; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -705,7 +705,7 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_8@plt +; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -715,7 +715,7 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a1, 0 -; RV32IA-NEXT: call __atomic_load_8@plt +; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -725,7 +725,7 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_8@plt +; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -744,7 +744,7 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 2 -; RV32I-NEXT: call __atomic_load_8@plt +; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -754,7 +754,7 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a1, 2 -; RV32IA-NEXT: call __atomic_load_8@plt +; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -764,7 +764,7 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 2 -; RV64I-NEXT: call __atomic_load_8@plt +; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -800,7 +800,7 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __atomic_load_8@plt +; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -810,7 +810,7 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a1, 5 -; RV32IA-NEXT: call __atomic_load_8@plt +; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -820,7 +820,7 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __atomic_load_8@plt +; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -860,7 +860,7 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_store_1@plt +; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -875,7 +875,7 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_1@plt +; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -894,7 +894,7 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_store_1@plt +; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -909,7 +909,7 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_1@plt +; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -928,7 +928,7 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_store_1@plt +; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -949,7 +949,7 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_store_1@plt +; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -996,7 +996,7 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_store_1@plt +; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1018,7 +1018,7 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_store_1@plt +; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1070,7 +1070,7 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_store_2@plt +; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1085,7 +1085,7 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_2@plt +; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1104,7 +1104,7 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_store_2@plt +; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1119,7 +1119,7 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_2@plt +; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1138,7 +1138,7 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_store_2@plt +; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1159,7 +1159,7 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_store_2@plt +; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1206,7 +1206,7 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_store_2@plt +; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1228,7 +1228,7 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_store_2@plt +; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1280,7 +1280,7 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_store_4@plt +; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1295,7 +1295,7 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_4@plt +; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1314,7 +1314,7 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_store_4@plt +; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1329,7 +1329,7 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_4@plt +; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1348,7 +1348,7 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_store_4@plt +; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1369,7 +1369,7 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_store_4@plt +; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1416,7 +1416,7 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_store_4@plt +; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1438,7 +1438,7 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_store_4@plt +; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1490,7 +1490,7 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_store_8@plt +; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1500,7 +1500,7 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_store_8@plt +; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -1510,7 +1510,7 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_8@plt +; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1529,7 +1529,7 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_store_8@plt +; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1539,7 +1539,7 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_store_8@plt +; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -1549,7 +1549,7 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_store_8@plt +; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1568,7 +1568,7 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_store_8@plt +; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1578,7 +1578,7 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_store_8@plt +; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -1588,7 +1588,7 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_store_8@plt +; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1624,7 +1624,7 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_store_8@plt +; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1634,7 +1634,7 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_store_8@plt +; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -1644,7 +1644,7 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_store_8@plt +; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll b/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll index 895852b84e00..8d3fc9610926 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll @@ -24,7 +24,7 @@ define void @amoswap_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a3, 5 -; RV32-NEXT: call __atomic_exchange_8@plt +; RV32-NEXT: call __atomic_exchange_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -57,7 +57,7 @@ define void @amoadd_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a3, 5 -; RV32-NEXT: call __atomic_fetch_add_8@plt +; RV32-NEXT: call __atomic_fetch_add_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -90,7 +90,7 @@ define void @amoand_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a3, 5 -; RV32-NEXT: call __atomic_fetch_and_8@plt +; RV32-NEXT: call __atomic_fetch_and_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -123,7 +123,7 @@ define void @amoor_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a3, 5 -; RV32-NEXT: call __atomic_fetch_or_8@plt +; RV32-NEXT: call __atomic_fetch_or_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -156,7 +156,7 @@ define void @amoxor_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a3, 5 -; RV32-NEXT: call __atomic_fetch_or_8@plt +; RV32-NEXT: call __atomic_fetch_or_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -205,7 +205,7 @@ define void @amomax_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a4, 12(sp) ; RV32-NEXT: lw a5, 8(sp) ; RV32-NEXT: bnez a0, .LBB11_6 @@ -281,7 +281,7 @@ define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a4, 12(sp) ; RV32-NEXT: lw a5, 8(sp) ; RV32-NEXT: bnez a0, .LBB13_6 @@ -357,7 +357,7 @@ define void @amomin_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a4, 12(sp) ; RV32-NEXT: lw a5, 8(sp) ; RV32-NEXT: bnez a0, .LBB15_6 @@ -433,7 +433,7 @@ define void @amominu_d_discard(ptr %a, i64 %b) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a4, 12(sp) ; RV32-NEXT: lw a5, 8(sp) ; RV32-NEXT: bnez a0, .LBB17_6 diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll b/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll index 9fcf4c1b0541..4dafd6a08d97 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll @@ -15,7 +15,7 @@ define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -32,7 +32,7 @@ define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -54,7 +54,7 @@ define i64 @atomicrmw_sub_i64_constant(ptr %a) nounwind { ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -66,7 +66,7 @@ define i64 @atomicrmw_sub_i64_constant(ptr %a) nounwind { ; RV32IA-NEXT: li a1, 1 ; RV32IA-NEXT: li a3, 5 ; RV32IA-NEXT: li a2, 0 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -77,7 +77,7 @@ define i64 @atomicrmw_sub_i64_constant(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -98,7 +98,7 @@ define i32 @atomicrmw_sub_i32_neg(ptr %a, i32 %x, i32 %y) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sub a1, a1, a2 ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -115,7 +115,7 @@ define i32 @atomicrmw_sub_i32_neg(ptr %a, i32 %x, i32 %y) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: subw a1, a1, a2 ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -140,7 +140,7 @@ define i64 @atomicrmw_sub_i64_neg(ptr %a, i64 %x, i64 %y) nounwind { ; RV32I-NEXT: sub a2, a2, a5 ; RV32I-NEXT: sub a1, a1, a3 ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -154,7 +154,7 @@ define i64 @atomicrmw_sub_i64_neg(ptr %a, i64 %x, i64 %y) nounwind { ; RV32IA-NEXT: sub a2, a2, a5 ; RV32IA-NEXT: sub a1, a1, a3 ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -165,7 +165,7 @@ define i64 @atomicrmw_sub_i64_neg(ptr %a, i64 %x, i64 %y) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sub a1, a1, a2 ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll index e97a1ea5dfca..d4c067b7b8a4 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -18,7 +18,7 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -48,7 +48,7 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -82,7 +82,7 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -132,7 +132,7 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -186,7 +186,7 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -236,7 +236,7 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -290,7 +290,7 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -340,7 +340,7 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -394,7 +394,7 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -424,7 +424,7 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -462,7 +462,7 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -484,7 +484,7 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -510,7 +510,7 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -543,7 +543,7 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -580,7 +580,7 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -613,7 +613,7 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -650,7 +650,7 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -683,7 +683,7 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -720,7 +720,7 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -753,7 +753,7 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -790,7 +790,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 255 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -811,7 +811,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 255 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -836,7 +836,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 255 ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -867,7 +867,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 255 ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -902,7 +902,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 255 ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -933,7 +933,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 255 ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -968,7 +968,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 255 ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -999,7 +999,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 255 ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1034,7 +1034,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 255 ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1065,7 +1065,7 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 255 ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1099,7 +1099,7 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_add_1@plt +; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1129,7 +1129,7 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_1@plt +; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1163,7 +1163,7 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_add_1@plt +; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1213,7 +1213,7 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_add_1@plt +; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1267,7 +1267,7 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_add_1@plt +; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1317,7 +1317,7 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_add_1@plt +; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1371,7 +1371,7 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_add_1@plt +; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1421,7 +1421,7 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_add_1@plt +; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1475,7 +1475,7 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_add_1@plt +; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1505,7 +1505,7 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_add_1@plt +; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1539,7 +1539,7 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_1@plt +; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1569,7 +1569,7 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_1@plt +; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1603,7 +1603,7 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_sub_1@plt +; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1653,7 +1653,7 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_sub_1@plt +; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1707,7 +1707,7 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_sub_1@plt +; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1757,7 +1757,7 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_sub_1@plt +; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1811,7 +1811,7 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_sub_1@plt +; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1861,7 +1861,7 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_sub_1@plt +; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1915,7 +1915,7 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_sub_1@plt +; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1945,7 +1945,7 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_1@plt +; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1979,7 +1979,7 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_and_1@plt +; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2003,7 +2003,7 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_1@plt +; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2031,7 +2031,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_and_1@plt +; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2069,7 +2069,7 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_and_1@plt +; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2111,7 +2111,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_and_1@plt +; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2149,7 +2149,7 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_and_1@plt +; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2191,7 +2191,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_and_1@plt +; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2229,7 +2229,7 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_and_1@plt +; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2271,7 +2271,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_and_1@plt +; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2309,7 +2309,7 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_and_1@plt +; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2351,7 +2351,7 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_nand_1@plt +; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2382,7 +2382,7 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_1@plt +; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2417,7 +2417,7 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_nand_1@plt +; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2469,7 +2469,7 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_nand_1@plt +; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2525,7 +2525,7 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_nand_1@plt +; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2577,7 +2577,7 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_nand_1@plt +; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2633,7 +2633,7 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_nand_1@plt +; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2685,7 +2685,7 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_nand_1@plt +; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2741,7 +2741,7 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_nand_1@plt +; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2772,7 +2772,7 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_nand_1@plt +; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2807,7 +2807,7 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_or_1@plt +; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2827,7 +2827,7 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_1@plt +; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2851,7 +2851,7 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_or_1@plt +; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2881,7 +2881,7 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_or_1@plt +; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2915,7 +2915,7 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_or_1@plt +; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2945,7 +2945,7 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_or_1@plt +; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2979,7 +2979,7 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_or_1@plt +; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3009,7 +3009,7 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_or_1@plt +; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3043,7 +3043,7 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_or_1@plt +; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3073,7 +3073,7 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_or_1@plt +; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3107,7 +3107,7 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_xor_1@plt +; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3127,7 +3127,7 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_1@plt +; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3151,7 +3151,7 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_xor_1@plt +; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3181,7 +3181,7 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_xor_1@plt +; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3215,7 +3215,7 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_xor_1@plt +; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3245,7 +3245,7 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_xor_1@plt +; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3279,7 +3279,7 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_xor_1@plt +; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3309,7 +3309,7 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_xor_1@plt +; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3343,7 +3343,7 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_xor_1@plt +; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3373,7 +3373,7 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_xor_1@plt +; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3422,7 +3422,7 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB45_4 ; RV32I-NEXT: .LBB45_2: # %atomicrmw.start @@ -3493,7 +3493,7 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB45_4 ; RV64I-NEXT: .LBB45_2: # %atomicrmw.start @@ -3568,7 +3568,7 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB46_4 ; RV32I-NEXT: .LBB46_2: # %atomicrmw.start @@ -3668,7 +3668,7 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start @@ -3772,7 +3772,7 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB47_4 ; RV32I-NEXT: .LBB47_2: # %atomicrmw.start @@ -3872,7 +3872,7 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB47_4 ; RV64I-NEXT: .LBB47_2: # %atomicrmw.start @@ -3976,7 +3976,7 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB48_4 ; RV32I-NEXT: .LBB48_2: # %atomicrmw.start @@ -4076,7 +4076,7 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB48_4 ; RV64I-NEXT: .LBB48_2: # %atomicrmw.start @@ -4180,7 +4180,7 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB49_4 ; RV32I-NEXT: .LBB49_2: # %atomicrmw.start @@ -4251,7 +4251,7 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB49_4 ; RV64I-NEXT: .LBB49_2: # %atomicrmw.start @@ -4326,7 +4326,7 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB50_4 ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start @@ -4397,7 +4397,7 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB50_4 ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start @@ -4472,7 +4472,7 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB51_4 ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start @@ -4572,7 +4572,7 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB51_4 ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start @@ -4676,7 +4676,7 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB52_4 ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start @@ -4776,7 +4776,7 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB52_4 ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start @@ -4880,7 +4880,7 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB53_4 ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start @@ -4980,7 +4980,7 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB53_4 ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start @@ -5084,7 +5084,7 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB54_4 ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start @@ -5155,7 +5155,7 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB54_4 ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start @@ -5229,7 +5229,7 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB55_4 ; RV32I-NEXT: .LBB55_2: # %atomicrmw.start @@ -5293,7 +5293,7 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB55_4 ; RV64I-NEXT: .LBB55_2: # %atomicrmw.start @@ -5361,7 +5361,7 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB56_4 ; RV32I-NEXT: .LBB56_2: # %atomicrmw.start @@ -5449,7 +5449,7 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB56_4 ; RV64I-NEXT: .LBB56_2: # %atomicrmw.start @@ -5541,7 +5541,7 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB57_4 ; RV32I-NEXT: .LBB57_2: # %atomicrmw.start @@ -5629,7 +5629,7 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB57_4 ; RV64I-NEXT: .LBB57_2: # %atomicrmw.start @@ -5721,7 +5721,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB58_4 ; RV32I-NEXT: .LBB58_2: # %atomicrmw.start @@ -5809,7 +5809,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB58_4 ; RV64I-NEXT: .LBB58_2: # %atomicrmw.start @@ -5901,7 +5901,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB59_4 ; RV32I-NEXT: .LBB59_2: # %atomicrmw.start @@ -5965,7 +5965,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB59_4 ; RV64I-NEXT: .LBB59_2: # %atomicrmw.start @@ -6033,7 +6033,7 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB60_4 ; RV32I-NEXT: .LBB60_2: # %atomicrmw.start @@ -6097,7 +6097,7 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB60_4 ; RV64I-NEXT: .LBB60_2: # %atomicrmw.start @@ -6165,7 +6165,7 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB61_4 ; RV32I-NEXT: .LBB61_2: # %atomicrmw.start @@ -6253,7 +6253,7 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB61_4 ; RV64I-NEXT: .LBB61_2: # %atomicrmw.start @@ -6345,7 +6345,7 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB62_4 ; RV32I-NEXT: .LBB62_2: # %atomicrmw.start @@ -6433,7 +6433,7 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB62_4 ; RV64I-NEXT: .LBB62_2: # %atomicrmw.start @@ -6525,7 +6525,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB63_4 ; RV32I-NEXT: .LBB63_2: # %atomicrmw.start @@ -6613,7 +6613,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB63_4 ; RV64I-NEXT: .LBB63_2: # %atomicrmw.start @@ -6705,7 +6705,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB64_4 ; RV32I-NEXT: .LBB64_2: # %atomicrmw.start @@ -6769,7 +6769,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB64_4 ; RV64I-NEXT: .LBB64_2: # %atomicrmw.start @@ -6823,7 +6823,7 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -6854,7 +6854,7 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -6889,7 +6889,7 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -6941,7 +6941,7 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -6997,7 +6997,7 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7049,7 +7049,7 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7105,7 +7105,7 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7157,7 +7157,7 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7213,7 +7213,7 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7244,7 +7244,7 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7283,7 +7283,7 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7306,7 +7306,7 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7333,7 +7333,7 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7368,7 +7368,7 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7407,7 +7407,7 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7442,7 +7442,7 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7481,7 +7481,7 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7516,7 +7516,7 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7555,7 +7555,7 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7590,7 +7590,7 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7630,7 +7630,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7653,7 +7653,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7680,7 +7680,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7714,7 +7714,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7752,7 +7752,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7786,7 +7786,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7824,7 +7824,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7858,7 +7858,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7896,7 +7896,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7930,7 +7930,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7966,7 +7966,7 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_add_2@plt +; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7997,7 +7997,7 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_2@plt +; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8032,7 +8032,7 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_add_2@plt +; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8084,7 +8084,7 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_add_2@plt +; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8140,7 +8140,7 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_add_2@plt +; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8192,7 +8192,7 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_add_2@plt +; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8248,7 +8248,7 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_add_2@plt +; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8300,7 +8300,7 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_add_2@plt +; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8356,7 +8356,7 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_add_2@plt +; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8387,7 +8387,7 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_add_2@plt +; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8422,7 +8422,7 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_2@plt +; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8453,7 +8453,7 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_2@plt +; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8488,7 +8488,7 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_sub_2@plt +; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8540,7 +8540,7 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_sub_2@plt +; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8596,7 +8596,7 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_sub_2@plt +; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8648,7 +8648,7 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_sub_2@plt +; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8704,7 +8704,7 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_sub_2@plt +; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8756,7 +8756,7 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_sub_2@plt +; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8812,7 +8812,7 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_sub_2@plt +; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8843,7 +8843,7 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_2@plt +; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8878,7 +8878,7 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_and_2@plt +; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8903,7 +8903,7 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_2@plt +; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -8932,7 +8932,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_and_2@plt +; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -8972,7 +8972,7 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_and_2@plt +; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9016,7 +9016,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_and_2@plt +; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9056,7 +9056,7 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_and_2@plt +; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9100,7 +9100,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_and_2@plt +; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9140,7 +9140,7 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_and_2@plt +; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9184,7 +9184,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_and_2@plt +; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9224,7 +9224,7 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_and_2@plt +; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9268,7 +9268,7 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_nand_2@plt +; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9300,7 +9300,7 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_2@plt +; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9336,7 +9336,7 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_nand_2@plt +; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9390,7 +9390,7 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_nand_2@plt +; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9448,7 +9448,7 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_nand_2@plt +; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9502,7 +9502,7 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_nand_2@plt +; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9560,7 +9560,7 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_nand_2@plt +; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9614,7 +9614,7 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_nand_2@plt +; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9672,7 +9672,7 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_nand_2@plt +; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9704,7 +9704,7 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_nand_2@plt +; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9740,7 +9740,7 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_or_2@plt +; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9761,7 +9761,7 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_2@plt +; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9786,7 +9786,7 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_or_2@plt +; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9818,7 +9818,7 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_or_2@plt +; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9854,7 +9854,7 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_or_2@plt +; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9886,7 +9886,7 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_or_2@plt +; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9922,7 +9922,7 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_or_2@plt +; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -9954,7 +9954,7 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_or_2@plt +; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -9990,7 +9990,7 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_or_2@plt +; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -10022,7 +10022,7 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_or_2@plt +; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -10058,7 +10058,7 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_xor_2@plt +; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -10079,7 +10079,7 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_2@plt +; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -10104,7 +10104,7 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_xor_2@plt +; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -10136,7 +10136,7 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_xor_2@plt +; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -10172,7 +10172,7 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_xor_2@plt +; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -10204,7 +10204,7 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_xor_2@plt +; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -10240,7 +10240,7 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_xor_2@plt +; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -10272,7 +10272,7 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_xor_2@plt +; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -10308,7 +10308,7 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_xor_2@plt +; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -10340,7 +10340,7 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_xor_2@plt +; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -10391,7 +10391,7 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB110_4 ; RV32I-NEXT: .LBB110_2: # %atomicrmw.start @@ -10464,7 +10464,7 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB110_4 ; RV64I-NEXT: .LBB110_2: # %atomicrmw.start @@ -10541,7 +10541,7 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB111_4 ; RV32I-NEXT: .LBB111_2: # %atomicrmw.start @@ -10645,7 +10645,7 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB111_4 ; RV64I-NEXT: .LBB111_2: # %atomicrmw.start @@ -10753,7 +10753,7 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB112_4 ; RV32I-NEXT: .LBB112_2: # %atomicrmw.start @@ -10857,7 +10857,7 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB112_4 ; RV64I-NEXT: .LBB112_2: # %atomicrmw.start @@ -10965,7 +10965,7 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB113_4 ; RV32I-NEXT: .LBB113_2: # %atomicrmw.start @@ -11069,7 +11069,7 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB113_4 ; RV64I-NEXT: .LBB113_2: # %atomicrmw.start @@ -11177,7 +11177,7 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB114_4 ; RV32I-NEXT: .LBB114_2: # %atomicrmw.start @@ -11250,7 +11250,7 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB114_4 ; RV64I-NEXT: .LBB114_2: # %atomicrmw.start @@ -11327,7 +11327,7 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB115_4 ; RV32I-NEXT: .LBB115_2: # %atomicrmw.start @@ -11400,7 +11400,7 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB115_4 ; RV64I-NEXT: .LBB115_2: # %atomicrmw.start @@ -11477,7 +11477,7 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB116_4 ; RV32I-NEXT: .LBB116_2: # %atomicrmw.start @@ -11581,7 +11581,7 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB116_4 ; RV64I-NEXT: .LBB116_2: # %atomicrmw.start @@ -11689,7 +11689,7 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB117_4 ; RV32I-NEXT: .LBB117_2: # %atomicrmw.start @@ -11793,7 +11793,7 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB117_4 ; RV64I-NEXT: .LBB117_2: # %atomicrmw.start @@ -11901,7 +11901,7 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB118_4 ; RV32I-NEXT: .LBB118_2: # %atomicrmw.start @@ -12005,7 +12005,7 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB118_4 ; RV64I-NEXT: .LBB118_2: # %atomicrmw.start @@ -12113,7 +12113,7 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB119_4 ; RV32I-NEXT: .LBB119_2: # %atomicrmw.start @@ -12186,7 +12186,7 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB119_4 ; RV64I-NEXT: .LBB119_2: # %atomicrmw.start @@ -12265,7 +12265,7 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB120_4 ; RV32I-NEXT: .LBB120_2: # %atomicrmw.start @@ -12334,7 +12334,7 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB120_4 ; RV64I-NEXT: .LBB120_2: # %atomicrmw.start @@ -12407,7 +12407,7 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB121_4 ; RV32I-NEXT: .LBB121_2: # %atomicrmw.start @@ -12501,7 +12501,7 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB121_4 ; RV64I-NEXT: .LBB121_2: # %atomicrmw.start @@ -12599,7 +12599,7 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB122_4 ; RV32I-NEXT: .LBB122_2: # %atomicrmw.start @@ -12693,7 +12693,7 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB122_4 ; RV64I-NEXT: .LBB122_2: # %atomicrmw.start @@ -12791,7 +12791,7 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB123_4 ; RV32I-NEXT: .LBB123_2: # %atomicrmw.start @@ -12885,7 +12885,7 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB123_4 ; RV64I-NEXT: .LBB123_2: # %atomicrmw.start @@ -12983,7 +12983,7 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB124_4 ; RV32I-NEXT: .LBB124_2: # %atomicrmw.start @@ -13052,7 +13052,7 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB124_4 ; RV64I-NEXT: .LBB124_2: # %atomicrmw.start @@ -13125,7 +13125,7 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB125_4 ; RV32I-NEXT: .LBB125_2: # %atomicrmw.start @@ -13194,7 +13194,7 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB125_4 ; RV64I-NEXT: .LBB125_2: # %atomicrmw.start @@ -13267,7 +13267,7 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB126_4 ; RV32I-NEXT: .LBB126_2: # %atomicrmw.start @@ -13361,7 +13361,7 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB126_4 ; RV64I-NEXT: .LBB126_2: # %atomicrmw.start @@ -13459,7 +13459,7 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB127_4 ; RV32I-NEXT: .LBB127_2: # %atomicrmw.start @@ -13553,7 +13553,7 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB127_4 ; RV64I-NEXT: .LBB127_2: # %atomicrmw.start @@ -13651,7 +13651,7 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB128_4 ; RV32I-NEXT: .LBB128_2: # %atomicrmw.start @@ -13745,7 +13745,7 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB128_4 ; RV64I-NEXT: .LBB128_2: # %atomicrmw.start @@ -13843,7 +13843,7 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB129_4 ; RV32I-NEXT: .LBB129_2: # %atomicrmw.start @@ -13912,7 +13912,7 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB129_4 ; RV64I-NEXT: .LBB129_2: # %atomicrmw.start @@ -13968,7 +13968,7 @@ define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_4@plt +; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -13983,7 +13983,7 @@ define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_4@plt +; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14002,7 +14002,7 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_exchange_4@plt +; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14022,7 +14022,7 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_exchange_4@plt +; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14046,7 +14046,7 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_exchange_4@plt +; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14066,7 +14066,7 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_exchange_4@plt +; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14090,7 +14090,7 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_exchange_4@plt +; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14110,7 +14110,7 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_exchange_4@plt +; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14134,7 +14134,7 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_exchange_4@plt +; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14154,7 +14154,7 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_exchange_4@plt +; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14178,7 +14178,7 @@ define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_add_4@plt +; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14193,7 +14193,7 @@ define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_4@plt +; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14212,7 +14212,7 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_add_4@plt +; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14232,7 +14232,7 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_add_4@plt +; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14256,7 +14256,7 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_add_4@plt +; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14276,7 +14276,7 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_add_4@plt +; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14300,7 +14300,7 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_add_4@plt +; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14320,7 +14320,7 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_add_4@plt +; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14344,7 +14344,7 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_add_4@plt +; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14364,7 +14364,7 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_add_4@plt +; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14388,7 +14388,7 @@ define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14404,7 +14404,7 @@ define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14424,7 +14424,7 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14446,7 +14446,7 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14472,7 +14472,7 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14494,7 +14494,7 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14520,7 +14520,7 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14542,7 +14542,7 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14568,7 +14568,7 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14590,7 +14590,7 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14616,7 +14616,7 @@ define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_and_4@plt +; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14631,7 +14631,7 @@ define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_4@plt +; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14650,7 +14650,7 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_and_4@plt +; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14670,7 +14670,7 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_and_4@plt +; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14694,7 +14694,7 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_and_4@plt +; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14714,7 +14714,7 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_and_4@plt +; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14738,7 +14738,7 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_and_4@plt +; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14758,7 +14758,7 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_and_4@plt +; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14782,7 +14782,7 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_and_4@plt +; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14802,7 +14802,7 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_and_4@plt +; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14826,7 +14826,7 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_nand_4@plt +; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14848,7 +14848,7 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_4@plt +; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14874,7 +14874,7 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_nand_4@plt +; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14908,7 +14908,7 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_nand_4@plt +; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -14946,7 +14946,7 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_nand_4@plt +; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -14980,7 +14980,7 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_nand_4@plt +; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15018,7 +15018,7 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_nand_4@plt +; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15052,7 +15052,7 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_nand_4@plt +; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15090,7 +15090,7 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_nand_4@plt +; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15112,7 +15112,7 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_nand_4@plt +; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15138,7 +15138,7 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_or_4@plt +; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15153,7 +15153,7 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_4@plt +; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15172,7 +15172,7 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_or_4@plt +; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15192,7 +15192,7 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_or_4@plt +; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15216,7 +15216,7 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_or_4@plt +; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15236,7 +15236,7 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_or_4@plt +; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15260,7 +15260,7 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_or_4@plt +; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15280,7 +15280,7 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_or_4@plt +; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15304,7 +15304,7 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_or_4@plt +; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15324,7 +15324,7 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_or_4@plt +; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15348,7 +15348,7 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_xor_4@plt +; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15363,7 +15363,7 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_4@plt +; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15382,7 +15382,7 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 2 -; RV32I-NEXT: call __atomic_fetch_xor_4@plt +; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15402,7 +15402,7 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_xor_4@plt +; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15426,7 +15426,7 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 3 -; RV32I-NEXT: call __atomic_fetch_xor_4@plt +; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15446,7 +15446,7 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_xor_4@plt +; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15470,7 +15470,7 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 4 -; RV32I-NEXT: call __atomic_fetch_xor_4@plt +; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15490,7 +15490,7 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_xor_4@plt +; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15514,7 +15514,7 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 -; RV32I-NEXT: call __atomic_fetch_xor_4@plt +; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -15534,7 +15534,7 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_xor_4@plt +; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -15570,7 +15570,7 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB165_4 ; RV32I-NEXT: .LBB165_2: # %atomicrmw.start @@ -15613,7 +15613,7 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB165_4 ; RV64I-NEXT: .LBB165_2: # %atomicrmw.start @@ -15659,7 +15659,7 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB166_4 ; RV32I-NEXT: .LBB166_2: # %atomicrmw.start @@ -15707,7 +15707,7 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB166_4 ; RV64I-NEXT: .LBB166_2: # %atomicrmw.start @@ -15758,7 +15758,7 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB167_4 ; RV32I-NEXT: .LBB167_2: # %atomicrmw.start @@ -15806,7 +15806,7 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB167_4 ; RV64I-NEXT: .LBB167_2: # %atomicrmw.start @@ -15857,7 +15857,7 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB168_4 ; RV32I-NEXT: .LBB168_2: # %atomicrmw.start @@ -15905,7 +15905,7 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB168_4 ; RV64I-NEXT: .LBB168_2: # %atomicrmw.start @@ -15956,7 +15956,7 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB169_4 ; RV32I-NEXT: .LBB169_2: # %atomicrmw.start @@ -16004,7 +16004,7 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB169_4 ; RV64I-NEXT: .LBB169_2: # %atomicrmw.start @@ -16055,7 +16055,7 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB170_4 ; RV32I-NEXT: .LBB170_2: # %atomicrmw.start @@ -16098,7 +16098,7 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB170_4 ; RV64I-NEXT: .LBB170_2: # %atomicrmw.start @@ -16144,7 +16144,7 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB171_4 ; RV32I-NEXT: .LBB171_2: # %atomicrmw.start @@ -16192,7 +16192,7 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB171_4 ; RV64I-NEXT: .LBB171_2: # %atomicrmw.start @@ -16243,7 +16243,7 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB172_4 ; RV32I-NEXT: .LBB172_2: # %atomicrmw.start @@ -16291,7 +16291,7 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB172_4 ; RV64I-NEXT: .LBB172_2: # %atomicrmw.start @@ -16342,7 +16342,7 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB173_4 ; RV32I-NEXT: .LBB173_2: # %atomicrmw.start @@ -16390,7 +16390,7 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB173_4 ; RV64I-NEXT: .LBB173_2: # %atomicrmw.start @@ -16441,7 +16441,7 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB174_4 ; RV32I-NEXT: .LBB174_2: # %atomicrmw.start @@ -16489,7 +16489,7 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB174_4 ; RV64I-NEXT: .LBB174_2: # %atomicrmw.start @@ -16540,7 +16540,7 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB175_4 ; RV32I-NEXT: .LBB175_2: # %atomicrmw.start @@ -16583,7 +16583,7 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB175_4 ; RV64I-NEXT: .LBB175_2: # %atomicrmw.start @@ -16629,7 +16629,7 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB176_4 ; RV32I-NEXT: .LBB176_2: # %atomicrmw.start @@ -16677,7 +16677,7 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB176_4 ; RV64I-NEXT: .LBB176_2: # %atomicrmw.start @@ -16728,7 +16728,7 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB177_4 ; RV32I-NEXT: .LBB177_2: # %atomicrmw.start @@ -16776,7 +16776,7 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB177_4 ; RV64I-NEXT: .LBB177_2: # %atomicrmw.start @@ -16827,7 +16827,7 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB178_4 ; RV32I-NEXT: .LBB178_2: # %atomicrmw.start @@ -16875,7 +16875,7 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB178_4 ; RV64I-NEXT: .LBB178_2: # %atomicrmw.start @@ -16926,7 +16926,7 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB179_4 ; RV32I-NEXT: .LBB179_2: # %atomicrmw.start @@ -16974,7 +16974,7 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB179_4 ; RV64I-NEXT: .LBB179_2: # %atomicrmw.start @@ -17025,7 +17025,7 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB180_4 ; RV32I-NEXT: .LBB180_2: # %atomicrmw.start @@ -17068,7 +17068,7 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB180_4 ; RV64I-NEXT: .LBB180_2: # %atomicrmw.start @@ -17114,7 +17114,7 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB181_4 ; RV32I-NEXT: .LBB181_2: # %atomicrmw.start @@ -17162,7 +17162,7 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB181_4 ; RV64I-NEXT: .LBB181_2: # %atomicrmw.start @@ -17213,7 +17213,7 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB182_4 ; RV32I-NEXT: .LBB182_2: # %atomicrmw.start @@ -17261,7 +17261,7 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB182_4 ; RV64I-NEXT: .LBB182_2: # %atomicrmw.start @@ -17312,7 +17312,7 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB183_4 ; RV32I-NEXT: .LBB183_2: # %atomicrmw.start @@ -17360,7 +17360,7 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB183_4 ; RV64I-NEXT: .LBB183_2: # %atomicrmw.start @@ -17411,7 +17411,7 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB184_4 ; RV32I-NEXT: .LBB184_2: # %atomicrmw.start @@ -17459,7 +17459,7 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB184_4 ; RV64I-NEXT: .LBB184_2: # %atomicrmw.start @@ -17498,7 +17498,7 @@ define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_exchange_8@plt +; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17508,7 +17508,7 @@ define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_exchange_8@plt +; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17518,7 +17518,7 @@ define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_8@plt +; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17537,7 +17537,7 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 2 -; RV32I-NEXT: call __atomic_exchange_8@plt +; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17547,7 +17547,7 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 2 -; RV32IA-NEXT: call __atomic_exchange_8@plt +; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17557,7 +17557,7 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_exchange_8@plt +; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17581,7 +17581,7 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_exchange_8@plt +; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17591,7 +17591,7 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_exchange_8@plt +; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17601,7 +17601,7 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_exchange_8@plt +; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17625,7 +17625,7 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 4 -; RV32I-NEXT: call __atomic_exchange_8@plt +; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17635,7 +17635,7 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 4 -; RV32IA-NEXT: call __atomic_exchange_8@plt +; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17645,7 +17645,7 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_exchange_8@plt +; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17669,7 +17669,7 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_exchange_8@plt +; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17679,7 +17679,7 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_exchange_8@plt +; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17689,7 +17689,7 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_exchange_8@plt +; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17713,7 +17713,7 @@ define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_add_8@plt +; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17723,7 +17723,7 @@ define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_add_8@plt +; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17733,7 +17733,7 @@ define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_8@plt +; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17752,7 +17752,7 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 2 -; RV32I-NEXT: call __atomic_fetch_add_8@plt +; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17762,7 +17762,7 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 2 -; RV32IA-NEXT: call __atomic_fetch_add_8@plt +; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17772,7 +17772,7 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_add_8@plt +; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17796,7 +17796,7 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_fetch_add_8@plt +; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17806,7 +17806,7 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_fetch_add_8@plt +; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17816,7 +17816,7 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_add_8@plt +; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17840,7 +17840,7 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 4 -; RV32I-NEXT: call __atomic_fetch_add_8@plt +; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17850,7 +17850,7 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 4 -; RV32IA-NEXT: call __atomic_fetch_add_8@plt +; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17860,7 +17860,7 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_add_8@plt +; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17884,7 +17884,7 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_fetch_add_8@plt +; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17894,7 +17894,7 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_fetch_add_8@plt +; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17904,7 +17904,7 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_add_8@plt +; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17928,7 +17928,7 @@ define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17938,7 +17938,7 @@ define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17948,7 +17948,7 @@ define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -17968,7 +17968,7 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 2 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -17978,7 +17978,7 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 2 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -17988,7 +17988,7 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18014,7 +18014,7 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18024,7 +18024,7 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18034,7 +18034,7 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18060,7 +18060,7 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 4 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18070,7 +18070,7 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 4 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18080,7 +18080,7 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18106,7 +18106,7 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18116,7 +18116,7 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18126,7 +18126,7 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18152,7 +18152,7 @@ define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_and_8@plt +; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18162,7 +18162,7 @@ define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_and_8@plt +; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18172,7 +18172,7 @@ define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_8@plt +; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18191,7 +18191,7 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 2 -; RV32I-NEXT: call __atomic_fetch_and_8@plt +; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18201,7 +18201,7 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 2 -; RV32IA-NEXT: call __atomic_fetch_and_8@plt +; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18211,7 +18211,7 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_and_8@plt +; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18235,7 +18235,7 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_fetch_and_8@plt +; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18245,7 +18245,7 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_fetch_and_8@plt +; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18255,7 +18255,7 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_and_8@plt +; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18279,7 +18279,7 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 4 -; RV32I-NEXT: call __atomic_fetch_and_8@plt +; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18289,7 +18289,7 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 4 -; RV32IA-NEXT: call __atomic_fetch_and_8@plt +; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18299,7 +18299,7 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_and_8@plt +; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18323,7 +18323,7 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_fetch_and_8@plt +; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18333,7 +18333,7 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_fetch_and_8@plt +; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18343,7 +18343,7 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_and_8@plt +; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18367,7 +18367,7 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_nand_8@plt +; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18377,7 +18377,7 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_nand_8@plt +; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18387,7 +18387,7 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_8@plt +; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18413,7 +18413,7 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 2 -; RV32I-NEXT: call __atomic_fetch_nand_8@plt +; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18423,7 +18423,7 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 2 -; RV32IA-NEXT: call __atomic_fetch_nand_8@plt +; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18433,7 +18433,7 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_nand_8@plt +; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18471,7 +18471,7 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_fetch_nand_8@plt +; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18481,7 +18481,7 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_fetch_nand_8@plt +; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18491,7 +18491,7 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_nand_8@plt +; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18529,7 +18529,7 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 4 -; RV32I-NEXT: call __atomic_fetch_nand_8@plt +; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18539,7 +18539,7 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 4 -; RV32IA-NEXT: call __atomic_fetch_nand_8@plt +; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18549,7 +18549,7 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_nand_8@plt +; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18587,7 +18587,7 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_fetch_nand_8@plt +; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18597,7 +18597,7 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_fetch_nand_8@plt +; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18607,7 +18607,7 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_nand_8@plt +; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18633,7 +18633,7 @@ define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_or_8@plt +; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18643,7 +18643,7 @@ define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_or_8@plt +; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18653,7 +18653,7 @@ define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_8@plt +; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18672,7 +18672,7 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 2 -; RV32I-NEXT: call __atomic_fetch_or_8@plt +; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18682,7 +18682,7 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 2 -; RV32IA-NEXT: call __atomic_fetch_or_8@plt +; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18692,7 +18692,7 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_or_8@plt +; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18716,7 +18716,7 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_fetch_or_8@plt +; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18726,7 +18726,7 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_fetch_or_8@plt +; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18736,7 +18736,7 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_or_8@plt +; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18760,7 +18760,7 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 4 -; RV32I-NEXT: call __atomic_fetch_or_8@plt +; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18770,7 +18770,7 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 4 -; RV32IA-NEXT: call __atomic_fetch_or_8@plt +; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18780,7 +18780,7 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_or_8@plt +; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18804,7 +18804,7 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_fetch_or_8@plt +; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18814,7 +18814,7 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_fetch_or_8@plt +; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18824,7 +18824,7 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_or_8@plt +; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18848,7 +18848,7 @@ define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_xor_8@plt +; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18858,7 +18858,7 @@ define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_xor_8@plt +; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18868,7 +18868,7 @@ define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_8@plt +; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18887,7 +18887,7 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 2 -; RV32I-NEXT: call __atomic_fetch_xor_8@plt +; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18897,7 +18897,7 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 2 -; RV32IA-NEXT: call __atomic_fetch_xor_8@plt +; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18907,7 +18907,7 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 2 -; RV64I-NEXT: call __atomic_fetch_xor_8@plt +; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18931,7 +18931,7 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 3 -; RV32I-NEXT: call __atomic_fetch_xor_8@plt +; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18941,7 +18941,7 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 3 -; RV32IA-NEXT: call __atomic_fetch_xor_8@plt +; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18951,7 +18951,7 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 3 -; RV64I-NEXT: call __atomic_fetch_xor_8@plt +; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -18975,7 +18975,7 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 4 -; RV32I-NEXT: call __atomic_fetch_xor_8@plt +; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -18985,7 +18985,7 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 4 -; RV32IA-NEXT: call __atomic_fetch_xor_8@plt +; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -18995,7 +18995,7 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 4 -; RV64I-NEXT: call __atomic_fetch_xor_8@plt +; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -19019,7 +19019,7 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 5 -; RV32I-NEXT: call __atomic_fetch_xor_8@plt +; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -19029,7 +19029,7 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 5 -; RV32IA-NEXT: call __atomic_fetch_xor_8@plt +; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -19039,7 +19039,7 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 5 -; RV64I-NEXT: call __atomic_fetch_xor_8@plt +; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -19079,7 +19079,7 @@ define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB220_7 @@ -19133,7 +19133,7 @@ define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB220_7 @@ -19183,7 +19183,7 @@ define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB220_4 ; RV64I-NEXT: .LBB220_2: # %atomicrmw.start @@ -19232,7 +19232,7 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB221_7 @@ -19286,7 +19286,7 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 2 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB221_7 @@ -19336,7 +19336,7 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB221_4 ; RV64I-NEXT: .LBB221_2: # %atomicrmw.start @@ -19390,7 +19390,7 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB222_7 @@ -19444,7 +19444,7 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 3 ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB222_7 @@ -19494,7 +19494,7 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB222_4 ; RV64I-NEXT: .LBB222_2: # %atomicrmw.start @@ -19548,7 +19548,7 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 4 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB223_7 @@ -19602,7 +19602,7 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 4 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB223_7 @@ -19652,7 +19652,7 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB223_4 ; RV64I-NEXT: .LBB223_2: # %atomicrmw.start @@ -19706,7 +19706,7 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB224_7 @@ -19760,7 +19760,7 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 5 ; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB224_7 @@ -19810,7 +19810,7 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB224_4 ; RV64I-NEXT: .LBB224_2: # %atomicrmw.start @@ -19864,7 +19864,7 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB225_7 @@ -19918,7 +19918,7 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB225_7 @@ -19968,7 +19968,7 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB225_4 ; RV64I-NEXT: .LBB225_2: # %atomicrmw.start @@ -20017,7 +20017,7 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB226_7 @@ -20071,7 +20071,7 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 2 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB226_7 @@ -20121,7 +20121,7 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB226_4 ; RV64I-NEXT: .LBB226_2: # %atomicrmw.start @@ -20175,7 +20175,7 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB227_7 @@ -20229,7 +20229,7 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 3 ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB227_7 @@ -20279,7 +20279,7 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB227_4 ; RV64I-NEXT: .LBB227_2: # %atomicrmw.start @@ -20333,7 +20333,7 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 4 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB228_7 @@ -20387,7 +20387,7 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 4 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB228_7 @@ -20437,7 +20437,7 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB228_4 ; RV64I-NEXT: .LBB228_2: # %atomicrmw.start @@ -20491,7 +20491,7 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB229_7 @@ -20545,7 +20545,7 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 5 ; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB229_7 @@ -20595,7 +20595,7 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB229_4 ; RV64I-NEXT: .LBB229_2: # %atomicrmw.start @@ -20649,7 +20649,7 @@ define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB230_7 @@ -20703,7 +20703,7 @@ define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB230_7 @@ -20753,7 +20753,7 @@ define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB230_4 ; RV64I-NEXT: .LBB230_2: # %atomicrmw.start @@ -20802,7 +20802,7 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB231_7 @@ -20856,7 +20856,7 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 2 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB231_7 @@ -20906,7 +20906,7 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB231_4 ; RV64I-NEXT: .LBB231_2: # %atomicrmw.start @@ -20960,7 +20960,7 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB232_7 @@ -21014,7 +21014,7 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 3 ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB232_7 @@ -21064,7 +21064,7 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB232_4 ; RV64I-NEXT: .LBB232_2: # %atomicrmw.start @@ -21118,7 +21118,7 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 4 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB233_7 @@ -21172,7 +21172,7 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 4 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB233_7 @@ -21222,7 +21222,7 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB233_4 ; RV64I-NEXT: .LBB233_2: # %atomicrmw.start @@ -21276,7 +21276,7 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB234_7 @@ -21330,7 +21330,7 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 5 ; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB234_7 @@ -21380,7 +21380,7 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB234_4 ; RV64I-NEXT: .LBB234_2: # %atomicrmw.start @@ -21434,7 +21434,7 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB235_7 @@ -21488,7 +21488,7 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB235_7 @@ -21538,7 +21538,7 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB235_4 ; RV64I-NEXT: .LBB235_2: # %atomicrmw.start @@ -21587,7 +21587,7 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB236_7 @@ -21641,7 +21641,7 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 2 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB236_7 @@ -21691,7 +21691,7 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB236_4 ; RV64I-NEXT: .LBB236_2: # %atomicrmw.start @@ -21745,7 +21745,7 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 3 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB237_7 @@ -21799,7 +21799,7 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 3 ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB237_7 @@ -21849,7 +21849,7 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB237_4 ; RV64I-NEXT: .LBB237_2: # %atomicrmw.start @@ -21903,7 +21903,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 4 ; RV32I-NEXT: li a5, 2 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB238_7 @@ -21957,7 +21957,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 4 ; RV32IA-NEXT: li a5, 2 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB238_7 @@ -22007,7 +22007,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB238_4 ; RV64I-NEXT: .LBB238_2: # %atomicrmw.start @@ -22061,7 +22061,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB239_7 @@ -22115,7 +22115,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: li a4, 5 ; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB239_7 @@ -22165,7 +22165,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB239_4 ; RV64I-NEXT: .LBB239_2: # %atomicrmw.start diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll index 2739fde250ee..ef0c27f32801 100644 --- a/llvm/test/CodeGen/RISCV/atomic-signext.ll +++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -14,7 +14,7 @@ define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_1@plt +; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -31,7 +31,7 @@ define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_1@plt +; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -52,7 +52,7 @@ define signext i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_2@plt +; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -69,7 +69,7 @@ define signext i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_2@plt +; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -90,7 +90,7 @@ define signext i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __atomic_load_4@plt +; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -105,7 +105,7 @@ define signext i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __atomic_load_4@plt +; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -126,7 +126,7 @@ define signext i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_1@plt +; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -160,7 +160,7 @@ define signext i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_1@plt +; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -198,7 +198,7 @@ define signext i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_add_1@plt +; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -232,7 +232,7 @@ define signext i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_1@plt +; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -270,7 +270,7 @@ define signext i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_1@plt +; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -304,7 +304,7 @@ define signext i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_1@plt +; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -342,7 +342,7 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_and_1@plt +; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -370,7 +370,7 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_1@plt +; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -402,7 +402,7 @@ define signext i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_nand_1@plt +; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -437,7 +437,7 @@ define signext i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_1@plt +; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -476,7 +476,7 @@ define signext i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_or_1@plt +; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -500,7 +500,7 @@ define signext i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_1@plt +; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -528,7 +528,7 @@ define signext i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_xor_1@plt +; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -552,7 +552,7 @@ define signext i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_1@plt +; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -595,7 +595,7 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB10_4 ; RV32I-NEXT: .LBB10_2: # %atomicrmw.start @@ -669,7 +669,7 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB10_4 ; RV64I-NEXT: .LBB10_2: # %atomicrmw.start @@ -747,7 +747,7 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB11_4 ; RV32I-NEXT: .LBB11_2: # %atomicrmw.start @@ -821,7 +821,7 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB11_4 ; RV64I-NEXT: .LBB11_2: # %atomicrmw.start @@ -898,7 +898,7 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB12_4 ; RV32I-NEXT: .LBB12_2: # %atomicrmw.start @@ -965,7 +965,7 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB12_4 ; RV64I-NEXT: .LBB12_2: # %atomicrmw.start @@ -1036,7 +1036,7 @@ define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB13_4 ; RV32I-NEXT: .LBB13_2: # %atomicrmw.start @@ -1103,7 +1103,7 @@ define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB13_4 ; RV64I-NEXT: .LBB13_2: # %atomicrmw.start @@ -1160,7 +1160,7 @@ define signext i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_2@plt +; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1195,7 +1195,7 @@ define signext i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_2@plt +; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1234,7 +1234,7 @@ define signext i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_add_2@plt +; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1269,7 +1269,7 @@ define signext i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_2@plt +; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1308,7 +1308,7 @@ define signext i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_2@plt +; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1343,7 +1343,7 @@ define signext i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_2@plt +; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1382,7 +1382,7 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_and_2@plt +; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1411,7 +1411,7 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_2@plt +; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1444,7 +1444,7 @@ define signext i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_nand_2@plt +; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1480,7 +1480,7 @@ define signext i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_2@plt +; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1520,7 +1520,7 @@ define signext i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_or_2@plt +; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1545,7 +1545,7 @@ define signext i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_2@plt +; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1574,7 +1574,7 @@ define signext i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_xor_2@plt +; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1599,7 +1599,7 @@ define signext i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_2@plt +; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1643,7 +1643,7 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB21_4 ; RV32I-NEXT: .LBB21_2: # %atomicrmw.start @@ -1719,7 +1719,7 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB21_4 ; RV64I-NEXT: .LBB21_2: # %atomicrmw.start @@ -1799,7 +1799,7 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: bnez a0, .LBB22_4 ; RV32I-NEXT: .LBB22_2: # %atomicrmw.start @@ -1875,7 +1875,7 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: bnez a0, .LBB22_4 ; RV64I-NEXT: .LBB22_2: # %atomicrmw.start @@ -1957,7 +1957,7 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB23_4 ; RV32I-NEXT: .LBB23_2: # %atomicrmw.start @@ -2029,7 +2029,7 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB23_4 ; RV64I-NEXT: .LBB23_2: # %atomicrmw.start @@ -2105,7 +2105,7 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB24_4 ; RV32I-NEXT: .LBB24_2: # %atomicrmw.start @@ -2177,7 +2177,7 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB24_4 ; RV64I-NEXT: .LBB24_2: # %atomicrmw.start @@ -2236,7 +2236,7 @@ define signext i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_4@plt +; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2251,7 +2251,7 @@ define signext i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_4@plt +; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2271,7 +2271,7 @@ define signext i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_add_4@plt +; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2286,7 +2286,7 @@ define signext i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_4@plt +; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2306,7 +2306,7 @@ define signext i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2322,7 +2322,7 @@ define signext i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2343,7 +2343,7 @@ define signext i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_and_4@plt +; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2358,7 +2358,7 @@ define signext i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_4@plt +; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2378,7 +2378,7 @@ define signext i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_nand_4@plt +; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2400,7 +2400,7 @@ define signext i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_4@plt +; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2427,7 +2427,7 @@ define signext i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_or_4@plt +; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2442,7 +2442,7 @@ define signext i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_4@plt +; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2462,7 +2462,7 @@ define signext i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_xor_4@plt +; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2477,7 +2477,7 @@ define signext i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_4@plt +; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2509,7 +2509,7 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB32_4 ; RV32I-NEXT: .LBB32_2: # %atomicrmw.start @@ -2552,7 +2552,7 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB32_4 ; RV64I-NEXT: .LBB32_2: # %atomicrmw.start @@ -2598,7 +2598,7 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB33_4 ; RV32I-NEXT: .LBB33_2: # %atomicrmw.start @@ -2641,7 +2641,7 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB33_4 ; RV64I-NEXT: .LBB33_2: # %atomicrmw.start @@ -2687,7 +2687,7 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB34_4 ; RV32I-NEXT: .LBB34_2: # %atomicrmw.start @@ -2730,7 +2730,7 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB34_4 ; RV64I-NEXT: .LBB34_2: # %atomicrmw.start @@ -2776,7 +2776,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB35_4 ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start @@ -2819,7 +2819,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start @@ -2853,7 +2853,7 @@ define signext i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_exchange_8@plt +; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2863,7 +2863,7 @@ define signext i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_exchange_8@plt +; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -2873,7 +2873,7 @@ define signext i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_8@plt +; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2892,7 +2892,7 @@ define signext i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_add_8@plt +; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2902,7 +2902,7 @@ define signext i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_add_8@plt +; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -2912,7 +2912,7 @@ define signext i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_8@plt +; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2931,7 +2931,7 @@ define signext i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_sub_8@plt +; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2941,7 +2941,7 @@ define signext i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_sub_8@plt +; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -2951,7 +2951,7 @@ define signext i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_8@plt +; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2971,7 +2971,7 @@ define signext i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_and_8@plt +; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2981,7 +2981,7 @@ define signext i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_and_8@plt +; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -2991,7 +2991,7 @@ define signext i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_8@plt +; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3010,7 +3010,7 @@ define signext i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_nand_8@plt +; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3020,7 +3020,7 @@ define signext i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_nand_8@plt +; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3030,7 +3030,7 @@ define signext i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_8@plt +; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3056,7 +3056,7 @@ define signext i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_or_8@plt +; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3066,7 +3066,7 @@ define signext i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_or_8@plt +; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3076,7 +3076,7 @@ define signext i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_8@plt +; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3095,7 +3095,7 @@ define signext i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __atomic_fetch_xor_8@plt +; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3105,7 +3105,7 @@ define signext i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IA-NEXT: li a3, 0 -; RV32IA-NEXT: call __atomic_fetch_xor_8@plt +; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret @@ -3115,7 +3115,7 @@ define signext i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_8@plt +; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3150,7 +3150,7 @@ define signext i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB43_7 @@ -3204,7 +3204,7 @@ define signext i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB43_7 @@ -3254,7 +3254,7 @@ define signext i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB43_4 ; RV64I-NEXT: .LBB43_2: # %atomicrmw.start @@ -3303,7 +3303,7 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB44_7 @@ -3357,7 +3357,7 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB44_7 @@ -3407,7 +3407,7 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB44_4 ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start @@ -3456,7 +3456,7 @@ define signext i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB45_7 @@ -3510,7 +3510,7 @@ define signext i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB45_7 @@ -3560,7 +3560,7 @@ define signext i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB45_4 ; RV64I-NEXT: .LBB45_2: # %atomicrmw.start @@ -3609,7 +3609,7 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a5, 0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB46_7 @@ -3663,7 +3663,7 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: li a4, 0 ; RV32IA-NEXT: li a5, 0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB46_7 @@ -3713,7 +3713,7 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start @@ -3749,7 +3749,7 @@ define signext i8 @cmpxchg_i8_monotonic_monotonic_val0(ptr %ptr, i8 signext %cmp ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -3789,7 +3789,7 @@ define signext i8 @cmpxchg_i8_monotonic_monotonic_val0(ptr %ptr, i8 signext %cmp ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -3834,7 +3834,7 @@ define i1 @cmpxchg_i8_monotonic_monotonic_val1(ptr %ptr, i8 signext %cmp, i8 sig ; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3873,7 +3873,7 @@ define i1 @cmpxchg_i8_monotonic_monotonic_val1(ptr %ptr, i8 signext %cmp, i8 sig ; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3917,7 +3917,7 @@ define signext i16 @cmpxchg_i16_monotonic_monotonic_val0(ptr %ptr, i16 signext % ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -3958,7 +3958,7 @@ define signext i16 @cmpxchg_i16_monotonic_monotonic_val0(ptr %ptr, i16 signext % ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -4004,7 +4004,7 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(ptr %ptr, i16 signext %cmp, i16 ; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4044,7 +4044,7 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(ptr %ptr, i16 signext %cmp, i16 ; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4089,7 +4089,7 @@ define signext i32 @cmpxchg_i32_monotonic_monotonic_val0(ptr %ptr, i32 signext % ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -4115,7 +4115,7 @@ define signext i32 @cmpxchg_i32_monotonic_monotonic_val0(ptr %ptr, i32 signext % ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -4146,7 +4146,7 @@ define i1 @cmpxchg_i32_monotonic_monotonic_val1(ptr %ptr, i32 signext %cmp, i32 ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4172,7 +4172,7 @@ define i1 @cmpxchg_i32_monotonic_monotonic_val1(ptr %ptr, i32 signext %cmp, i32 ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4204,7 +4204,7 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_exchange_4@plt +; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4239,7 +4239,7 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_exchange_4@plt +; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: sext.w a0, a0 @@ -4291,7 +4291,7 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_add_4@plt +; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4326,7 +4326,7 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_add_4@plt +; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: sext.w a0, a0 @@ -4379,7 +4379,7 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_sub_4@plt +; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4414,7 +4414,7 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_sub_4@plt +; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: sext.w a0, a0 @@ -4467,7 +4467,7 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_and_4@plt +; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4502,7 +4502,7 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_and_4@plt +; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: sext.w a0, a0 @@ -4555,7 +4555,7 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_nand_4@plt +; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4597,7 +4597,7 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_nand_4@plt +; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: sext.w a0, a0 @@ -4657,7 +4657,7 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_or_4@plt +; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4692,7 +4692,7 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_or_4@plt +; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: sext.w a0, a0 @@ -4745,7 +4745,7 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a1, 1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __atomic_fetch_xor_4@plt +; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4780,7 +4780,7 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call __atomic_fetch_xor_4@plt +; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: sext.w a0, a0 @@ -4842,7 +4842,7 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: bnez a0, .LBB60_8 ; RV32I-NEXT: .LBB60_3: # %atomicrmw.start @@ -4905,7 +4905,7 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a1, 12(sp) ; RV64I-NEXT: bnez a0, .LBB60_8 ; RV64I-NEXT: .LBB60_3: # %atomicrmw.start @@ -4989,7 +4989,7 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a1, 0(sp) ; RV32I-NEXT: bnez a0, .LBB61_8 ; RV32I-NEXT: .LBB61_3: # %atomicrmw.start @@ -5055,7 +5055,7 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a1, 4(sp) ; RV64I-NEXT: bnez a0, .LBB61_8 ; RV64I-NEXT: .LBB61_3: # %atomicrmw.start @@ -5138,7 +5138,7 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: beqz a0, .LBB62_2 ; RV32I-NEXT: j .LBB62_4 @@ -5188,7 +5188,7 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a1, 12(sp) ; RV64I-NEXT: bnez a0, .LBB62_6 ; RV64I-NEXT: .LBB62_3: # %atomicrmw.start @@ -5266,7 +5266,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a4, 0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a1, 0(sp) ; RV32I-NEXT: bnez a0, .LBB63_8 ; RV32I-NEXT: .LBB63_3: # %atomicrmw.start @@ -5334,7 +5334,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a1, 4(sp) ; RV64I-NEXT: bnez a0, .LBB63_8 ; RV64I-NEXT: .LBB63_3: # %atomicrmw.start diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll index 5f15a9c06710..aa962d68fc52 100644 --- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll @@ -39,7 +39,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 3(sp) ; RV32I-NEXT: beqz a0, .LBB0_1 ; RV32I-NEXT: # %bb.2: # %atomicrmw.end @@ -113,7 +113,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 7(sp) ; RV64I-NEXT: beqz a0, .LBB0_1 ; RV64I-NEXT: # %bb.2: # %atomicrmw.end @@ -195,7 +195,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: beqz a0, .LBB1_1 ; RV32I-NEXT: # %bb.2: # %atomicrmw.end @@ -275,7 +275,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: beqz a0, .LBB1_1 ; RV64I-NEXT: # %bb.2: # %atomicrmw.end @@ -354,7 +354,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: beqz a0, .LBB2_1 ; RV32I-NEXT: # %bb.2: # %atomicrmw.end @@ -414,7 +414,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 4(sp) ; RV64I-NEXT: beqz a0, .LBB2_1 ; RV64I-NEXT: # %bb.2: # %atomicrmw.end @@ -490,7 +490,7 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB3_5 @@ -545,7 +545,7 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; RV32IA-NEXT: li a4, 5 ; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB3_5 @@ -589,7 +589,7 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: beqz a0, .LBB3_1 ; RV64I-NEXT: # %bb.2: # %atomicrmw.end @@ -653,7 +653,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_1@plt +; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: bnez a0, .LBB4_4 ; RV32I-NEXT: .LBB4_2: # %atomicrmw.start @@ -749,7 +749,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_1@plt +; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: bnez a0, .LBB4_4 ; RV64I-NEXT: .LBB4_2: # %atomicrmw.start @@ -853,7 +853,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __atomic_compare_exchange_2@plt +; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: bnez a0, .LBB5_4 ; RV32I-NEXT: .LBB5_2: # %atomicrmw.start @@ -955,7 +955,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __atomic_compare_exchange_2@plt +; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: bnez a0, .LBB5_4 ; RV64I-NEXT: .LBB5_2: # %atomicrmw.start @@ -1054,7 +1054,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_4@plt +; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: bnez a0, .LBB6_4 ; RV32I-NEXT: .LBB6_2: # %atomicrmw.start @@ -1135,7 +1135,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_4@plt +; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: bnez a0, .LBB6_4 ; RV64I-NEXT: .LBB6_2: # %atomicrmw.start @@ -1224,7 +1224,7 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __atomic_compare_exchange_8@plt +; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: bnez a0, .LBB7_7 @@ -1287,7 +1287,7 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; RV32IA-NEXT: li a4, 5 ; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: call __atomic_compare_exchange_8@plt +; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: bnez a0, .LBB7_7 @@ -1345,7 +1345,7 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __atomic_compare_exchange_8@plt +; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: bnez a0, .LBB7_4 ; RV64I-NEXT: .LBB7_2: # %atomicrmw.start diff --git a/llvm/test/CodeGen/RISCV/bf16-promote.ll b/llvm/test/CodeGen/RISCV/bf16-promote.ll index c8fc84729da7..c17450a80de9 100644 --- a/llvm/test/CodeGen/RISCV/bf16-promote.ll +++ b/llvm/test/CodeGen/RISCV/bf16-promote.ll @@ -45,7 +45,7 @@ define void @test_fptrunc_float(float %f, ptr %p) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64-NEXT: mv s0, a0 -; RV64-NEXT: call __truncsfbf2@plt +; RV64-NEXT: call __truncsfbf2 ; RV64-NEXT: fmv.x.w a0, fa0 ; RV64-NEXT: sh a0, 0(s0) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -59,7 +59,7 @@ define void @test_fptrunc_float(float %f, ptr %p) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-NEXT: mv s0, a0 -; RV32-NEXT: call __truncsfbf2@plt +; RV32-NEXT: call __truncsfbf2 ; RV32-NEXT: fmv.x.w a0, fa0 ; RV32-NEXT: sh a0, 0(s0) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -78,7 +78,7 @@ define void @test_fptrunc_double(double %d, ptr %p) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64-NEXT: mv s0, a0 -; RV64-NEXT: call __truncdfbf2@plt +; RV64-NEXT: call __truncdfbf2 ; RV64-NEXT: fmv.x.w a0, fa0 ; RV64-NEXT: sh a0, 0(s0) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -92,7 +92,7 @@ define void @test_fptrunc_double(double %d, ptr %p) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-NEXT: mv s0, a0 -; RV32-NEXT: call __truncdfbf2@plt +; RV32-NEXT: call __truncdfbf2 ; RV32-NEXT: fmv.x.w a0, fa0 ; RV32-NEXT: sh a0, 0(s0) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -118,7 +118,7 @@ define void @test_fadd(ptr %p, ptr %q) nounwind { ; RV64-NEXT: slli a0, a0, 16 ; RV64-NEXT: fmv.w.x fa4, a0 ; RV64-NEXT: fadd.s fa0, fa4, fa5 -; RV64-NEXT: call __truncsfbf2@plt +; RV64-NEXT: call __truncsfbf2 ; RV64-NEXT: fmv.x.w a0, fa0 ; RV64-NEXT: sh a0, 0(s0) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -139,7 +139,7 @@ define void @test_fadd(ptr %p, ptr %q) nounwind { ; RV32-NEXT: slli a0, a0, 16 ; RV32-NEXT: fmv.w.x fa4, a0 ; RV32-NEXT: fadd.s fa0, fa4, fa5 -; RV32-NEXT: call __truncsfbf2@plt +; RV32-NEXT: call __truncsfbf2 ; RV32-NEXT: fmv.x.w a0, fa0 ; RV32-NEXT: sh a0, 0(s0) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -151,4 +151,4 @@ define void @test_fadd(ptr %p, ptr %q) nounwind { %r = fadd bfloat %a, %b store bfloat %r, ptr %p ret void -} \ No newline at end of file +} diff --git a/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll b/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll index 24f26af97770..165aa5f484f7 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll @@ -18,7 +18,7 @@ define void @br_fcmp_false(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB0_2: # %if.else ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_false: ; RV64IZFBFMIN: # %bb.0: @@ -29,7 +29,7 @@ define void @br_fcmp_false(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB0_2: # %if.else ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp false bfloat %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -51,7 +51,7 @@ define void @br_fcmp_oeq(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB1_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_oeq: ; RV64IZFBFMIN: # %bb.0: @@ -64,7 +64,7 @@ define void @br_fcmp_oeq(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB1_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp oeq bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -86,7 +86,7 @@ define void @br_fcmp_oeq_alt(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB2_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_oeq_alt: ; RV64IZFBFMIN: # %bb.0: @@ -99,7 +99,7 @@ define void @br_fcmp_oeq_alt(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB2_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp oeq bfloat %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -121,7 +121,7 @@ define void @br_fcmp_ogt(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB3_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_ogt: ; RV64IZFBFMIN: # %bb.0: @@ -134,7 +134,7 @@ define void @br_fcmp_ogt(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB3_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp ogt bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -156,7 +156,7 @@ define void @br_fcmp_oge(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB4_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_oge: ; RV64IZFBFMIN: # %bb.0: @@ -169,7 +169,7 @@ define void @br_fcmp_oge(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB4_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp oge bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -191,7 +191,7 @@ define void @br_fcmp_olt(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB5_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_olt: ; RV64IZFBFMIN: # %bb.0: @@ -204,7 +204,7 @@ define void @br_fcmp_olt(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB5_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp olt bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -226,7 +226,7 @@ define void @br_fcmp_ole(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB6_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_ole: ; RV64IZFBFMIN: # %bb.0: @@ -239,7 +239,7 @@ define void @br_fcmp_ole(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB6_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp ole bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -263,7 +263,7 @@ define void @br_fcmp_one(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB7_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_one: ; RV64IZFBFMIN: # %bb.0: @@ -278,7 +278,7 @@ define void @br_fcmp_one(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB7_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp one bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -302,7 +302,7 @@ define void @br_fcmp_ord(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB8_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_ord: ; RV64IZFBFMIN: # %bb.0: @@ -317,7 +317,7 @@ define void @br_fcmp_ord(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB8_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp ord bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -341,7 +341,7 @@ define void @br_fcmp_ueq(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB9_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_ueq: ; RV64IZFBFMIN: # %bb.0: @@ -356,7 +356,7 @@ define void @br_fcmp_ueq(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB9_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp ueq bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -378,7 +378,7 @@ define void @br_fcmp_ugt(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB10_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_ugt: ; RV64IZFBFMIN: # %bb.0: @@ -391,7 +391,7 @@ define void @br_fcmp_ugt(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB10_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp ugt bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -413,7 +413,7 @@ define void @br_fcmp_uge(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB11_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_uge: ; RV64IZFBFMIN: # %bb.0: @@ -426,7 +426,7 @@ define void @br_fcmp_uge(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB11_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp uge bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -448,7 +448,7 @@ define void @br_fcmp_ult(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB12_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_ult: ; RV64IZFBFMIN: # %bb.0: @@ -461,7 +461,7 @@ define void @br_fcmp_ult(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB12_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp ult bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -483,7 +483,7 @@ define void @br_fcmp_ule(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB13_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_ule: ; RV64IZFBFMIN: # %bb.0: @@ -496,7 +496,7 @@ define void @br_fcmp_ule(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB13_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp ule bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -518,7 +518,7 @@ define void @br_fcmp_une(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB14_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_une: ; RV64IZFBFMIN: # %bb.0: @@ -531,7 +531,7 @@ define void @br_fcmp_une(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB14_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp une bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -555,7 +555,7 @@ define void @br_fcmp_uno(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB15_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_uno: ; RV64IZFBFMIN: # %bb.0: @@ -570,7 +570,7 @@ define void @br_fcmp_uno(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB15_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp uno bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -590,7 +590,7 @@ define void @br_fcmp_true(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: .LBB16_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call abort@plt +; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_true: ; RV64IZFBFMIN: # %bb.0: @@ -601,7 +601,7 @@ define void @br_fcmp_true(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: .LBB16_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call abort@plt +; RV64IZFBFMIN-NEXT: call abort %1 = fcmp true bfloat %a, %b br i1 %1, label %if.then, label %if.else if.else: diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll index bfa2c3bb4a8b..d533607ad54e 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-convert.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-convert.ll @@ -419,7 +419,7 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind { ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 -; CHECK32ZFBFMIN-NEXT: call __fixsfdi@plt +; CHECK32ZFBFMIN-NEXT: call __fixsfdi ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16 ; CHECK32ZFBFMIN-NEXT: ret @@ -431,7 +431,7 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind { ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: slli a0, a0, 16 ; RV32ID-NEXT: fmv.w.x fa0, a0 -; RV32ID-NEXT: call __fixsfdi@plt +; RV32ID-NEXT: call __fixsfdi ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: ret @@ -465,7 +465,7 @@ define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind { ; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFBFMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFBFMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFBFMIN-NEXT: call __fixsfdi@plt +; RV32IZFBFMIN-NEXT: call __fixsfdi ; RV32IZFBFMIN-NEXT: lui a4, 524288 ; RV32IZFBFMIN-NEXT: lui a2, 524288 ; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_2 @@ -504,7 +504,7 @@ define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind { ; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a0 ; R32IDZFBFMIN-NEXT: fle.s s0, fa5, fs0 ; R32IDZFBFMIN-NEXT: fmv.s fa0, fs0 -; R32IDZFBFMIN-NEXT: call __fixsfdi@plt +; R32IDZFBFMIN-NEXT: call __fixsfdi ; R32IDZFBFMIN-NEXT: lui a4, 524288 ; R32IDZFBFMIN-NEXT: lui a2, 524288 ; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_2 @@ -545,7 +545,7 @@ define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind { ; RV32ID-NEXT: fmv.w.x fa5, a0 ; RV32ID-NEXT: fle.s s0, fa5, fs0 ; RV32ID-NEXT: fmv.s fa0, fs0 -; RV32ID-NEXT: call __fixsfdi@plt +; RV32ID-NEXT: call __fixsfdi ; RV32ID-NEXT: lui a4, 524288 ; RV32ID-NEXT: lui a2, 524288 ; RV32ID-NEXT: beqz s0, .LBB10_2 @@ -606,7 +606,7 @@ define i64 @fcvt_lu_bf16(bfloat %a) nounwind { ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 -; CHECK32ZFBFMIN-NEXT: call __fixunssfdi@plt +; CHECK32ZFBFMIN-NEXT: call __fixunssfdi ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16 ; CHECK32ZFBFMIN-NEXT: ret @@ -618,7 +618,7 @@ define i64 @fcvt_lu_bf16(bfloat %a) nounwind { ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: slli a0, a0, 16 ; RV32ID-NEXT: fmv.w.x fa0, a0 -; RV32ID-NEXT: call __fixunssfdi@plt +; RV32ID-NEXT: call __fixunssfdi ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: ret @@ -655,7 +655,7 @@ define i64 @fcvt_lu_bf16_sat(bfloat %a) nounwind { ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa5, zero ; CHECK32ZFBFMIN-NEXT: fle.s a0, fa5, fa0 ; CHECK32ZFBFMIN-NEXT: neg s1, a0 -; CHECK32ZFBFMIN-NEXT: call __fixunssfdi@plt +; CHECK32ZFBFMIN-NEXT: call __fixunssfdi ; CHECK32ZFBFMIN-NEXT: and a0, s1, a0 ; CHECK32ZFBFMIN-NEXT: or a0, s0, a0 ; CHECK32ZFBFMIN-NEXT: and a1, s1, a1 @@ -682,7 +682,7 @@ define i64 @fcvt_lu_bf16_sat(bfloat %a) nounwind { ; RV32ID-NEXT: fmv.w.x fa5, zero ; RV32ID-NEXT: fle.s a0, fa5, fa0 ; RV32ID-NEXT: neg s1, a0 -; RV32ID-NEXT: call __fixunssfdi@plt +; RV32ID-NEXT: call __fixunssfdi ; RV32ID-NEXT: and a0, s1, a0 ; RV32ID-NEXT: or a0, s0, a0 ; RV32ID-NEXT: and a1, s1, a1 @@ -736,7 +736,7 @@ define bfloat @fcvt_bf16_si(i16 %a) nounwind { ; RV32ID-NEXT: slli a0, a0, 16 ; RV32ID-NEXT: srai a0, a0, 16 ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -760,7 +760,7 @@ define bfloat @fcvt_bf16_si(i16 %a) nounwind { ; RV64ID-NEXT: slli a0, a0, 48 ; RV64ID-NEXT: srai a0, a0, 48 ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -784,7 +784,7 @@ define bfloat @fcvt_bf16_si_signext(i16 signext %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -804,7 +804,7 @@ define bfloat @fcvt_bf16_si_signext(i16 signext %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -832,7 +832,7 @@ define bfloat @fcvt_bf16_ui(i16 %a) nounwind { ; RV32ID-NEXT: slli a0, a0, 16 ; RV32ID-NEXT: srli a0, a0, 16 ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -856,7 +856,7 @@ define bfloat @fcvt_bf16_ui(i16 %a) nounwind { ; RV64ID-NEXT: slli a0, a0, 48 ; RV64ID-NEXT: srli a0, a0, 48 ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -880,7 +880,7 @@ define bfloat @fcvt_bf16_ui_zeroext(i16 zeroext %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -900,7 +900,7 @@ define bfloat @fcvt_bf16_ui_zeroext(i16 zeroext %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -924,7 +924,7 @@ define bfloat @fcvt_bf16_w(i32 %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -945,7 +945,7 @@ define bfloat @fcvt_bf16_w(i32 %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -971,7 +971,7 @@ define bfloat @fcvt_bf16_w_load(ptr %p) nounwind { ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: lw a0, 0(a0) ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -993,7 +993,7 @@ define bfloat @fcvt_bf16_w_load(ptr %p) nounwind { ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: lw a0, 0(a0) ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -1018,7 +1018,7 @@ define bfloat @fcvt_bf16_wu(i32 %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -1040,7 +1040,7 @@ define bfloat @fcvt_bf16_wu(i32 %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -1066,7 +1066,7 @@ define bfloat @fcvt_bf16_wu_load(ptr %p) nounwind { ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: lw a0, 0(a0) ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -1088,7 +1088,7 @@ define bfloat @fcvt_bf16_wu_load(ptr %p) nounwind { ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: lwu a0, 0(a0) ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -1123,7 +1123,7 @@ define bfloat @fcvt_bf16_s(float %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -1141,7 +1141,7 @@ define bfloat @fcvt_bf16_s(float %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -1186,7 +1186,7 @@ define bfloat @fcvt_bf16_d(double %a) nounwind { ; RV32IZFBFMIN: # %bb.0: ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: call __truncdfbf2@plt +; RV32IZFBFMIN-NEXT: call __truncdfbf2 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFBFMIN-NEXT: addi sp, sp, 16 ; RV32IZFBFMIN-NEXT: ret @@ -1201,7 +1201,7 @@ define bfloat @fcvt_bf16_d(double %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __truncdfbf2@plt +; RV32ID-NEXT: call __truncdfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -1214,7 +1214,7 @@ define bfloat @fcvt_bf16_d(double %a) nounwind { ; RV64IZFBFMIN: # %bb.0: ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFBFMIN-NEXT: call __truncdfbf2@plt +; RV64IZFBFMIN-NEXT: call __truncdfbf2 ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFBFMIN-NEXT: addi sp, sp, 16 ; RV64IZFBFMIN-NEXT: ret @@ -1229,7 +1229,7 @@ define bfloat @fcvt_bf16_d(double %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __truncdfbf2@plt +; RV64ID-NEXT: call __truncdfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -1247,7 +1247,7 @@ define double @fcvt_d_bf16(bfloat %a) nounwind { ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 -; RV32IZFBFMIN-NEXT: call __extendsfdf2@plt +; RV32IZFBFMIN-NEXT: call __extendsfdf2 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFBFMIN-NEXT: addi sp, sp, 16 ; RV32IZFBFMIN-NEXT: ret @@ -1271,7 +1271,7 @@ define double @fcvt_d_bf16(bfloat %a) nounwind { ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 -; RV64IZFBFMIN-NEXT: call __extendsfdf2@plt +; RV64IZFBFMIN-NEXT: call __extendsfdf2 ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFBFMIN-NEXT: addi sp, sp, 16 ; RV64IZFBFMIN-NEXT: ret @@ -1363,7 +1363,7 @@ define signext i32 @fcvt_bf16_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32ID-NEXT: mv s0, a1 ; RV32ID-NEXT: addi s1, a0, 1 ; RV32ID-NEXT: fcvt.s.w fa0, s1 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: sh a0, 0(s0) ; RV32ID-NEXT: mv a0, s1 @@ -1390,7 +1390,7 @@ define signext i32 @fcvt_bf16_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64ID-NEXT: mv s0, a1 ; RV64ID-NEXT: addiw s1, a0, 1 ; RV64ID-NEXT: fcvt.s.w fa0, s1 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: sh a0, 0(s0) ; RV64ID-NEXT: mv a0, s1 @@ -1423,7 +1423,7 @@ define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind ; RV32ID-NEXT: mv s0, a1 ; RV32ID-NEXT: addi s1, a0, 1 ; RV32ID-NEXT: fcvt.s.wu fa0, s1 -; RV32ID-NEXT: call __truncsfbf2@plt +; RV32ID-NEXT: call __truncsfbf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: sh a0, 0(s0) ; RV32ID-NEXT: mv a0, s1 @@ -1452,7 +1452,7 @@ define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind ; RV64ID-NEXT: mv s0, a1 ; RV64ID-NEXT: addiw s1, a0, 1 ; RV64ID-NEXT: fcvt.s.wu fa0, s1 -; RV64ID-NEXT: call __truncsfbf2@plt +; RV64ID-NEXT: call __truncsfbf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: sh a0, 0(s0) ; RV64ID-NEXT: mv a0, s1 diff --git a/llvm/test/CodeGen/RISCV/bfloat-frem.ll b/llvm/test/CodeGen/RISCV/bfloat-frem.ll index fd6db9dfc3f7..ac8b99d1ce6d 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-frem.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-frem.ll @@ -11,7 +11,7 @@ define bfloat @frem_bf16(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa1, fa1 -; RV32IZFBFMIN-NEXT: call fmodf@plt +; RV32IZFBFMIN-NEXT: call fmodf ; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFBFMIN-NEXT: addi sp, sp, 16 @@ -23,7 +23,7 @@ define bfloat @frem_bf16(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 ; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa1, fa1 -; RV64IZFBFMIN-NEXT: call fmodf@plt +; RV64IZFBFMIN-NEXT: call fmodf ; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0 ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFBFMIN-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/bfloat-mem.ll b/llvm/test/CodeGen/RISCV/bfloat-mem.ll index 1119611b8212..4b6c0c29d660 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-mem.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-mem.ll @@ -109,7 +109,7 @@ define bfloat @flh_stack(bfloat %a) nounwind { ; RV32IZFBFMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFBFMIN-NEXT: fmv.s fs0, fa0 ; RV32IZFBFMIN-NEXT: addi a0, sp, 4 -; RV32IZFBFMIN-NEXT: call notdead@plt +; RV32IZFBFMIN-NEXT: call notdead ; RV32IZFBFMIN-NEXT: flh fa5, 4(sp) ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fs0 ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5 @@ -127,7 +127,7 @@ define bfloat @flh_stack(bfloat %a) nounwind { ; RV64IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IZFBFMIN-NEXT: fmv.s fs0, fa0 ; RV64IZFBFMIN-NEXT: mv a0, sp -; RV64IZFBFMIN-NEXT: call notdead@plt +; RV64IZFBFMIN-NEXT: call notdead ; RV64IZFBFMIN-NEXT: flh fa5, 0(sp) ; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fs0 ; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5 @@ -155,7 +155,7 @@ define dso_local void @fsh_stack(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5 ; RV32IZFBFMIN-NEXT: fsh fa5, 8(sp) ; RV32IZFBFMIN-NEXT: addi a0, sp, 8 -; RV32IZFBFMIN-NEXT: call notdead@plt +; RV32IZFBFMIN-NEXT: call notdead ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFBFMIN-NEXT: addi sp, sp, 16 ; RV32IZFBFMIN-NEXT: ret @@ -170,7 +170,7 @@ define dso_local void @fsh_stack(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5 ; RV64IZFBFMIN-NEXT: fsh fa5, 4(sp) ; RV64IZFBFMIN-NEXT: addi a0, sp, 4 -; RV64IZFBFMIN-NEXT: call notdead@plt +; RV64IZFBFMIN-NEXT: call notdead ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFBFMIN-NEXT: addi sp, sp, 16 ; RV64IZFBFMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/bfloat.ll b/llvm/test/CodeGen/RISCV/bfloat.ll index d62f35388123..9dc8ce6be1ea 100644 --- a/llvm/test/CodeGen/RISCV/bfloat.ll +++ b/llvm/test/CodeGen/RISCV/bfloat.ll @@ -11,7 +11,7 @@ define bfloat @float_to_bfloat(float %a) nounwind { ; RV32I-ILP32: # %bb.0: ; RV32I-ILP32-NEXT: addi sp, sp, -16 ; RV32I-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-ILP32-NEXT: call __truncsfbf2@plt +; RV32I-ILP32-NEXT: call __truncsfbf2 ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -20,7 +20,7 @@ define bfloat @float_to_bfloat(float %a) nounwind { ; RV64I-LP64: # %bb.0: ; RV64I-LP64-NEXT: addi sp, sp, -16 ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-LP64-NEXT: call __truncsfbf2@plt +; RV64I-LP64-NEXT: call __truncsfbf2 ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -29,7 +29,7 @@ define bfloat @float_to_bfloat(float %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32-NEXT: call __truncsfbf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -40,7 +40,7 @@ define bfloat @float_to_bfloat(float %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __truncsfbf2@plt +; RV64ID-LP64-NEXT: call __truncsfbf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -51,7 +51,7 @@ define bfloat @float_to_bfloat(float %a) nounwind { ; RV32ID-ILP32D: # %bb.0: ; RV32ID-ILP32D-NEXT: addi sp, sp, -16 ; RV32ID-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32D-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32D-NEXT: call __truncsfbf2 ; RV32ID-ILP32D-NEXT: fmv.x.w a0, fa0 ; RV32ID-ILP32D-NEXT: lui a1, 1048560 ; RV32ID-ILP32D-NEXT: or a0, a0, a1 @@ -64,7 +64,7 @@ define bfloat @float_to_bfloat(float %a) nounwind { ; RV64ID-LP64D: # %bb.0: ; RV64ID-LP64D-NEXT: addi sp, sp, -16 ; RV64ID-LP64D-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64D-NEXT: call __truncsfbf2@plt +; RV64ID-LP64D-NEXT: call __truncsfbf2 ; RV64ID-LP64D-NEXT: fmv.x.w a0, fa0 ; RV64ID-LP64D-NEXT: lui a1, 1048560 ; RV64ID-LP64D-NEXT: or a0, a0, a1 @@ -81,7 +81,7 @@ define bfloat @double_to_bfloat(double %a) nounwind { ; RV32I-ILP32: # %bb.0: ; RV32I-ILP32-NEXT: addi sp, sp, -16 ; RV32I-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-ILP32-NEXT: call __truncdfbf2@plt +; RV32I-ILP32-NEXT: call __truncdfbf2 ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -90,7 +90,7 @@ define bfloat @double_to_bfloat(double %a) nounwind { ; RV64I-LP64: # %bb.0: ; RV64I-LP64-NEXT: addi sp, sp, -16 ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-LP64-NEXT: call __truncdfbf2@plt +; RV64I-LP64-NEXT: call __truncdfbf2 ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -99,7 +99,7 @@ define bfloat @double_to_bfloat(double %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __truncdfbf2@plt +; RV32ID-ILP32-NEXT: call __truncdfbf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -110,7 +110,7 @@ define bfloat @double_to_bfloat(double %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __truncdfbf2@plt +; RV64ID-LP64-NEXT: call __truncdfbf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -121,7 +121,7 @@ define bfloat @double_to_bfloat(double %a) nounwind { ; RV32ID-ILP32D: # %bb.0: ; RV32ID-ILP32D-NEXT: addi sp, sp, -16 ; RV32ID-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32D-NEXT: call __truncdfbf2@plt +; RV32ID-ILP32D-NEXT: call __truncdfbf2 ; RV32ID-ILP32D-NEXT: fmv.x.w a0, fa0 ; RV32ID-ILP32D-NEXT: lui a1, 1048560 ; RV32ID-ILP32D-NEXT: or a0, a0, a1 @@ -134,7 +134,7 @@ define bfloat @double_to_bfloat(double %a) nounwind { ; RV64ID-LP64D: # %bb.0: ; RV64ID-LP64D-NEXT: addi sp, sp, -16 ; RV64ID-LP64D-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64D-NEXT: call __truncdfbf2@plt +; RV64ID-LP64D-NEXT: call __truncdfbf2 ; RV64ID-LP64D-NEXT: fmv.x.w a0, fa0 ; RV64ID-LP64D-NEXT: lui a1, 1048560 ; RV64ID-LP64D-NEXT: or a0, a0, a1 @@ -190,7 +190,7 @@ define double @bfloat_to_double(bfloat %a) nounwind { ; RV32I-ILP32-NEXT: addi sp, sp, -16 ; RV32I-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-ILP32-NEXT: slli a0, a0, 16 -; RV32I-ILP32-NEXT: call __extendsfdf2@plt +; RV32I-ILP32-NEXT: call __extendsfdf2 ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -200,7 +200,7 @@ define double @bfloat_to_double(bfloat %a) nounwind { ; RV64I-LP64-NEXT: addi sp, sp, -16 ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-LP64-NEXT: slliw a0, a0, 16 -; RV64I-LP64-NEXT: call __extendsfdf2@plt +; RV64I-LP64-NEXT: call __extendsfdf2 ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -319,8 +319,8 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind { ; RV32I-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-ILP32-NEXT: slli a0, a0, 16 ; RV32I-ILP32-NEXT: slli a1, a1, 16 -; RV32I-ILP32-NEXT: call __addsf3@plt -; RV32I-ILP32-NEXT: call __truncsfbf2@plt +; RV32I-ILP32-NEXT: call __addsf3 +; RV32I-ILP32-NEXT: call __truncsfbf2 ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -331,8 +331,8 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind { ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-LP64-NEXT: slliw a0, a0, 16 ; RV64I-LP64-NEXT: slliw a1, a1, 16 -; RV64I-LP64-NEXT: call __addsf3@plt -; RV64I-LP64-NEXT: call __truncsfbf2@plt +; RV64I-LP64-NEXT: call __addsf3 +; RV64I-LP64-NEXT: call __truncsfbf2 ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -347,7 +347,7 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind { ; RV32ID-ILP32-NEXT: fmv.w.x fa4, a0 ; RV32ID-ILP32-NEXT: fadd.s fa5, fa4, fa5 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32-NEXT: call __truncsfbf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -364,7 +364,7 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind { ; RV64ID-LP64-NEXT: fmv.w.x fa4, a0 ; RV64ID-LP64-NEXT: fadd.s fa5, fa4, fa5 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfbf2@plt +; RV64ID-LP64-NEXT: call __truncsfbf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -382,7 +382,7 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind { ; RV32ID-ILP32D-NEXT: slli a0, a0, 16 ; RV32ID-ILP32D-NEXT: fmv.w.x fa4, a0 ; RV32ID-ILP32D-NEXT: fadd.s fa0, fa4, fa5 -; RV32ID-ILP32D-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32D-NEXT: call __truncsfbf2 ; RV32ID-ILP32D-NEXT: fmv.x.w a0, fa0 ; RV32ID-ILP32D-NEXT: lui a1, 1048560 ; RV32ID-ILP32D-NEXT: or a0, a0, a1 @@ -402,7 +402,7 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind { ; RV64ID-LP64D-NEXT: slli a0, a0, 16 ; RV64ID-LP64D-NEXT: fmv.w.x fa4, a0 ; RV64ID-LP64D-NEXT: fadd.s fa0, fa4, fa5 -; RV64ID-LP64D-NEXT: call __truncsfbf2@plt +; RV64ID-LP64D-NEXT: call __truncsfbf2 ; RV64ID-LP64D-NEXT: fmv.x.w a0, fa0 ; RV64ID-LP64D-NEXT: lui a1, 1048560 ; RV64ID-LP64D-NEXT: or a0, a0, a1 @@ -423,8 +423,8 @@ define bfloat @bfloat_load(ptr %a) nounwind { ; RV32I-ILP32-NEXT: lh a2, 6(a0) ; RV32I-ILP32-NEXT: slli a0, a1, 16 ; RV32I-ILP32-NEXT: slli a1, a2, 16 -; RV32I-ILP32-NEXT: call __addsf3@plt -; RV32I-ILP32-NEXT: call __truncsfbf2@plt +; RV32I-ILP32-NEXT: call __addsf3 +; RV32I-ILP32-NEXT: call __truncsfbf2 ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -437,8 +437,8 @@ define bfloat @bfloat_load(ptr %a) nounwind { ; RV64I-LP64-NEXT: lh a2, 6(a0) ; RV64I-LP64-NEXT: slliw a0, a1, 16 ; RV64I-LP64-NEXT: slliw a1, a2, 16 -; RV64I-LP64-NEXT: call __addsf3@plt -; RV64I-LP64-NEXT: call __truncsfbf2@plt +; RV64I-LP64-NEXT: call __addsf3 +; RV64I-LP64-NEXT: call __truncsfbf2 ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -455,7 +455,7 @@ define bfloat @bfloat_load(ptr %a) nounwind { ; RV32ID-ILP32-NEXT: fmv.w.x fa4, a0 ; RV32ID-ILP32-NEXT: fadd.s fa5, fa4, fa5 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32-NEXT: call __truncsfbf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -474,7 +474,7 @@ define bfloat @bfloat_load(ptr %a) nounwind { ; RV64ID-LP64-NEXT: fmv.w.x fa4, a0 ; RV64ID-LP64-NEXT: fadd.s fa5, fa4, fa5 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfbf2@plt +; RV64ID-LP64-NEXT: call __truncsfbf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -492,7 +492,7 @@ define bfloat @bfloat_load(ptr %a) nounwind { ; RV32ID-ILP32D-NEXT: slli a0, a0, 16 ; RV32ID-ILP32D-NEXT: fmv.w.x fa4, a0 ; RV32ID-ILP32D-NEXT: fadd.s fa0, fa4, fa5 -; RV32ID-ILP32D-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32D-NEXT: call __truncsfbf2 ; RV32ID-ILP32D-NEXT: fmv.x.w a0, fa0 ; RV32ID-ILP32D-NEXT: lui a1, 1048560 ; RV32ID-ILP32D-NEXT: or a0, a0, a1 @@ -512,7 +512,7 @@ define bfloat @bfloat_load(ptr %a) nounwind { ; RV64ID-LP64D-NEXT: slli a0, a0, 16 ; RV64ID-LP64D-NEXT: fmv.w.x fa4, a0 ; RV64ID-LP64D-NEXT: fadd.s fa0, fa4, fa5 -; RV64ID-LP64D-NEXT: call __truncsfbf2@plt +; RV64ID-LP64D-NEXT: call __truncsfbf2 ; RV64ID-LP64D-NEXT: fmv.x.w a0, fa0 ; RV64ID-LP64D-NEXT: lui a1, 1048560 ; RV64ID-LP64D-NEXT: or a0, a0, a1 @@ -536,8 +536,8 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind { ; RV32I-ILP32-NEXT: mv s0, a0 ; RV32I-ILP32-NEXT: slli a0, a1, 16 ; RV32I-ILP32-NEXT: slli a1, a2, 16 -; RV32I-ILP32-NEXT: call __addsf3@plt -; RV32I-ILP32-NEXT: call __truncsfbf2@plt +; RV32I-ILP32-NEXT: call __addsf3 +; RV32I-ILP32-NEXT: call __truncsfbf2 ; RV32I-ILP32-NEXT: sh a0, 0(s0) ; RV32I-ILP32-NEXT: sh a0, 16(s0) ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -553,8 +553,8 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind { ; RV64I-LP64-NEXT: mv s0, a0 ; RV64I-LP64-NEXT: slliw a0, a1, 16 ; RV64I-LP64-NEXT: slliw a1, a2, 16 -; RV64I-LP64-NEXT: call __addsf3@plt -; RV64I-LP64-NEXT: call __truncsfbf2@plt +; RV64I-LP64-NEXT: call __addsf3 +; RV64I-LP64-NEXT: call __truncsfbf2 ; RV64I-LP64-NEXT: sh a0, 0(s0) ; RV64I-LP64-NEXT: sh a0, 16(s0) ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -574,7 +574,7 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind { ; RV32ID-ILP32-NEXT: fmv.w.x fa4, a1 ; RV32ID-ILP32-NEXT: fadd.s fa5, fa4, fa5 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32-NEXT: call __truncsfbf2 ; RV32ID-ILP32-NEXT: sh a0, 0(s0) ; RV32ID-ILP32-NEXT: sh a0, 16(s0) ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -594,7 +594,7 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind { ; RV64ID-LP64-NEXT: fmv.w.x fa4, a1 ; RV64ID-LP64-NEXT: fadd.s fa5, fa4, fa5 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfbf2@plt +; RV64ID-LP64-NEXT: call __truncsfbf2 ; RV64ID-LP64-NEXT: sh a0, 0(s0) ; RV64ID-LP64-NEXT: sh a0, 16(s0) ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -615,7 +615,7 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind { ; RV32ID-ILP32D-NEXT: slli a0, a0, 16 ; RV32ID-ILP32D-NEXT: fmv.w.x fa4, a0 ; RV32ID-ILP32D-NEXT: fadd.s fa0, fa4, fa5 -; RV32ID-ILP32D-NEXT: call __truncsfbf2@plt +; RV32ID-ILP32D-NEXT: call __truncsfbf2 ; RV32ID-ILP32D-NEXT: fmv.x.w a0, fa0 ; RV32ID-ILP32D-NEXT: sh a0, 0(s0) ; RV32ID-ILP32D-NEXT: sh a0, 16(s0) @@ -637,7 +637,7 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind { ; RV64ID-LP64D-NEXT: slli a0, a0, 16 ; RV64ID-LP64D-NEXT: fmv.w.x fa4, a0 ; RV64ID-LP64D-NEXT: fadd.s fa0, fa4, fa5 -; RV64ID-LP64D-NEXT: call __truncsfbf2@plt +; RV64ID-LP64D-NEXT: call __truncsfbf2 ; RV64ID-LP64D-NEXT: fmv.x.w a0, fa0 ; RV64ID-LP64D-NEXT: sh a0, 0(s0) ; RV64ID-LP64D-NEXT: sh a0, 16(s0) diff --git a/llvm/test/CodeGen/RISCV/bittest.ll b/llvm/test/CodeGen/RISCV/bittest.ll index a05c518bbf3a..d280e5ee46b7 100644 --- a/llvm/test/CodeGen/RISCV/bittest.ll +++ b/llvm/test/CodeGen/RISCV/bittest.ll @@ -452,7 +452,7 @@ define void @bittest_switch(i32 signext %0) { ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB14_3 ; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: tail bar ; RV32I-NEXT: .LBB14_3: ; RV32I-NEXT: ret ; @@ -468,7 +468,7 @@ define void @bittest_switch(i32 signext %0) { ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: beqz a0, .LBB14_3 ; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: tail bar ; RV64I-NEXT: .LBB14_3: ; RV64I-NEXT: ret ; @@ -482,7 +482,7 @@ define void @bittest_switch(i32 signext %0) { ; RV32ZBS-NEXT: bext a0, a1, a0 ; RV32ZBS-NEXT: beqz a0, .LBB14_3 ; RV32ZBS-NEXT: # %bb.2: -; RV32ZBS-NEXT: tail bar@plt +; RV32ZBS-NEXT: tail bar ; RV32ZBS-NEXT: .LBB14_3: ; RV32ZBS-NEXT: ret ; @@ -497,7 +497,7 @@ define void @bittest_switch(i32 signext %0) { ; RV64ZBS-NEXT: bext a0, a1, a0 ; RV64ZBS-NEXT: beqz a0, .LBB14_3 ; RV64ZBS-NEXT: # %bb.2: -; RV64ZBS-NEXT: tail bar@plt +; RV64ZBS-NEXT: tail bar ; RV64ZBS-NEXT: .LBB14_3: ; RV64ZBS-NEXT: ret ; @@ -512,7 +512,7 @@ define void @bittest_switch(i32 signext %0) { ; RV32XTHEADBS-NEXT: andi a0, a0, 1 ; RV32XTHEADBS-NEXT: beqz a0, .LBB14_3 ; RV32XTHEADBS-NEXT: # %bb.2: -; RV32XTHEADBS-NEXT: tail bar@plt +; RV32XTHEADBS-NEXT: tail bar ; RV32XTHEADBS-NEXT: .LBB14_3: ; RV32XTHEADBS-NEXT: ret ; @@ -528,7 +528,7 @@ define void @bittest_switch(i32 signext %0) { ; RV64XTHEADBS-NEXT: andi a0, a0, 1 ; RV64XTHEADBS-NEXT: beqz a0, .LBB14_3 ; RV64XTHEADBS-NEXT: # %bb.2: -; RV64XTHEADBS-NEXT: tail bar@plt +; RV64XTHEADBS-NEXT: tail bar ; RV64XTHEADBS-NEXT: .LBB14_3: ; RV64XTHEADBS-NEXT: ret switch i32 %0, label %3 [ @@ -1243,7 +1243,7 @@ define void @bit_10_z_branch_i32(i32 signext %0) { ; CHECK-NEXT: andi a0, a0, 1024 ; CHECK-NEXT: bnez a0, .LBB37_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB37_2: ; CHECK-NEXT: ret %2 = and i32 %0, 1024 @@ -1264,7 +1264,7 @@ define void @bit_10_nz_branch_i32(i32 signext %0) { ; CHECK-NEXT: andi a0, a0, 1024 ; CHECK-NEXT: beqz a0, .LBB38_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB38_2: ; CHECK-NEXT: ret %2 = and i32 %0, 1024 @@ -1285,7 +1285,7 @@ define void @bit_11_z_branch_i32(i32 signext %0) { ; RV32-NEXT: slli a0, a0, 20 ; RV32-NEXT: bltz a0, .LBB39_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB39_2: ; RV32-NEXT: ret ; @@ -1294,7 +1294,7 @@ define void @bit_11_z_branch_i32(i32 signext %0) { ; RV64-NEXT: slli a0, a0, 52 ; RV64-NEXT: bltz a0, .LBB39_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB39_2: ; RV64-NEXT: ret %2 = and i32 %0, 2048 @@ -1315,7 +1315,7 @@ define void @bit_11_nz_branch_i32(i32 signext %0) { ; RV32-NEXT: slli a0, a0, 20 ; RV32-NEXT: bgez a0, .LBB40_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB40_2: ; RV32-NEXT: ret ; @@ -1324,7 +1324,7 @@ define void @bit_11_nz_branch_i32(i32 signext %0) { ; RV64-NEXT: slli a0, a0, 52 ; RV64-NEXT: bgez a0, .LBB40_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB40_2: ; RV64-NEXT: ret %2 = and i32 %0, 2048 @@ -1345,7 +1345,7 @@ define void @bit_24_z_branch_i32(i32 signext %0) { ; RV32-NEXT: slli a0, a0, 7 ; RV32-NEXT: bltz a0, .LBB41_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB41_2: ; RV32-NEXT: ret ; @@ -1354,7 +1354,7 @@ define void @bit_24_z_branch_i32(i32 signext %0) { ; RV64-NEXT: slli a0, a0, 39 ; RV64-NEXT: bltz a0, .LBB41_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB41_2: ; RV64-NEXT: ret %2 = and i32 %0, 16777216 @@ -1375,7 +1375,7 @@ define void @bit_24_nz_branch_i32(i32 signext %0) { ; RV32-NEXT: slli a0, a0, 7 ; RV32-NEXT: bgez a0, .LBB42_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB42_2: ; RV32-NEXT: ret ; @@ -1384,7 +1384,7 @@ define void @bit_24_nz_branch_i32(i32 signext %0) { ; RV64-NEXT: slli a0, a0, 39 ; RV64-NEXT: bgez a0, .LBB42_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB42_2: ; RV64-NEXT: ret %2 = and i32 %0, 16777216 @@ -1404,7 +1404,7 @@ define void @bit_31_z_branch_i32(i32 signext %0) { ; RV32: # %bb.0: ; RV32-NEXT: bltz a0, .LBB43_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB43_2: ; RV32-NEXT: ret ; @@ -1414,7 +1414,7 @@ define void @bit_31_z_branch_i32(i32 signext %0) { ; RV64-NEXT: and a0, a0, a1 ; RV64-NEXT: bnez a0, .LBB43_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB43_2: ; RV64-NEXT: ret %2 = and i32 %0, 2147483648 @@ -1434,7 +1434,7 @@ define void @bit_31_nz_branch_i32(i32 signext %0) { ; RV32: # %bb.0: ; RV32-NEXT: bgez a0, .LBB44_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB44_2: ; RV32-NEXT: ret ; @@ -1444,7 +1444,7 @@ define void @bit_31_nz_branch_i32(i32 signext %0) { ; RV64-NEXT: and a0, a0, a1 ; RV64-NEXT: beqz a0, .LBB44_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB44_2: ; RV64-NEXT: ret %2 = and i32 %0, 2147483648 @@ -1465,7 +1465,7 @@ define void @bit_10_z_branch_i64(i64 %0) { ; CHECK-NEXT: andi a0, a0, 1024 ; CHECK-NEXT: bnez a0, .LBB45_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB45_2: ; CHECK-NEXT: ret %2 = and i64 %0, 1024 @@ -1486,7 +1486,7 @@ define void @bit_10_nz_branch_i64(i64 %0) { ; CHECK-NEXT: andi a0, a0, 1024 ; CHECK-NEXT: beqz a0, .LBB46_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB46_2: ; CHECK-NEXT: ret %2 = and i64 %0, 1024 @@ -1507,7 +1507,7 @@ define void @bit_11_z_branch_i64(i64 %0) { ; RV32-NEXT: slli a0, a0, 20 ; RV32-NEXT: bltz a0, .LBB47_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB47_2: ; RV32-NEXT: ret ; @@ -1516,7 +1516,7 @@ define void @bit_11_z_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 52 ; RV64-NEXT: bltz a0, .LBB47_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB47_2: ; RV64-NEXT: ret %2 = and i64 %0, 2048 @@ -1537,7 +1537,7 @@ define void @bit_11_nz_branch_i64(i64 %0) { ; RV32-NEXT: slli a0, a0, 20 ; RV32-NEXT: bgez a0, .LBB48_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB48_2: ; RV32-NEXT: ret ; @@ -1546,7 +1546,7 @@ define void @bit_11_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 52 ; RV64-NEXT: bgez a0, .LBB48_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB48_2: ; RV64-NEXT: ret %2 = and i64 %0, 2048 @@ -1567,7 +1567,7 @@ define void @bit_24_z_branch_i64(i64 %0) { ; RV32-NEXT: slli a0, a0, 7 ; RV32-NEXT: bltz a0, .LBB49_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB49_2: ; RV32-NEXT: ret ; @@ -1576,7 +1576,7 @@ define void @bit_24_z_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 39 ; RV64-NEXT: bltz a0, .LBB49_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB49_2: ; RV64-NEXT: ret %2 = and i64 %0, 16777216 @@ -1597,7 +1597,7 @@ define void @bit_24_nz_branch_i64(i64 %0) { ; RV32-NEXT: slli a0, a0, 7 ; RV32-NEXT: bgez a0, .LBB50_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB50_2: ; RV32-NEXT: ret ; @@ -1606,7 +1606,7 @@ define void @bit_24_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 39 ; RV64-NEXT: bgez a0, .LBB50_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB50_2: ; RV64-NEXT: ret %2 = and i64 %0, 16777216 @@ -1626,7 +1626,7 @@ define void @bit_31_z_branch_i64(i64 %0) { ; RV32: # %bb.0: ; RV32-NEXT: bltz a0, .LBB51_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB51_2: ; RV32-NEXT: ret ; @@ -1635,7 +1635,7 @@ define void @bit_31_z_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: bltz a0, .LBB51_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB51_2: ; RV64-NEXT: ret %2 = and i64 %0, 2147483648 @@ -1655,7 +1655,7 @@ define void @bit_31_nz_branch_i64(i64 %0) { ; RV32: # %bb.0: ; RV32-NEXT: bgez a0, .LBB52_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB52_2: ; RV32-NEXT: ret ; @@ -1664,7 +1664,7 @@ define void @bit_31_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: bgez a0, .LBB52_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB52_2: ; RV64-NEXT: ret %2 = and i64 %0, 2147483648 @@ -1685,7 +1685,7 @@ define void @bit_32_z_branch_i64(i64 %0) { ; RV32-NEXT: andi a1, a1, 1 ; RV32-NEXT: bnez a1, .LBB53_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB53_2: ; RV32-NEXT: ret ; @@ -1694,7 +1694,7 @@ define void @bit_32_z_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 31 ; RV64-NEXT: bltz a0, .LBB53_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB53_2: ; RV64-NEXT: ret %2 = and i64 %0, 4294967296 @@ -1715,7 +1715,7 @@ define void @bit_32_nz_branch_i64(i64 %0) { ; RV32-NEXT: andi a1, a1, 1 ; RV32-NEXT: beqz a1, .LBB54_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB54_2: ; RV32-NEXT: ret ; @@ -1724,7 +1724,7 @@ define void @bit_32_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 31 ; RV64-NEXT: bgez a0, .LBB54_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB54_2: ; RV64-NEXT: ret %2 = and i64 %0, 4294967296 @@ -1745,7 +1745,7 @@ define void @bit_62_z_branch_i64(i64 %0) { ; RV32-NEXT: slli a1, a1, 1 ; RV32-NEXT: bltz a1, .LBB55_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB55_2: ; RV32-NEXT: ret ; @@ -1754,7 +1754,7 @@ define void @bit_62_z_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: bltz a0, .LBB55_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB55_2: ; RV64-NEXT: ret %2 = and i64 %0, 4611686018427387904 @@ -1775,7 +1775,7 @@ define void @bit_62_nz_branch_i64(i64 %0) { ; RV32-NEXT: slli a1, a1, 1 ; RV32-NEXT: bgez a1, .LBB56_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB56_2: ; RV32-NEXT: ret ; @@ -1784,7 +1784,7 @@ define void @bit_62_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: bgez a0, .LBB56_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB56_2: ; RV64-NEXT: ret %2 = and i64 %0, 4611686018427387904 @@ -1804,7 +1804,7 @@ define void @bit_63_z_branch_i64(i64 %0) { ; RV32: # %bb.0: ; RV32-NEXT: bltz a1, .LBB57_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB57_2: ; RV32-NEXT: ret ; @@ -1812,7 +1812,7 @@ define void @bit_63_z_branch_i64(i64 %0) { ; RV64: # %bb.0: ; RV64-NEXT: bltz a0, .LBB57_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB57_2: ; RV64-NEXT: ret %2 = and i64 %0, 9223372036854775808 @@ -1832,7 +1832,7 @@ define void @bit_63_nz_branch_i64(i64 %0) { ; RV32: # %bb.0: ; RV32-NEXT: bgez a1, .LBB58_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB58_2: ; RV32-NEXT: ret ; @@ -1840,7 +1840,7 @@ define void @bit_63_nz_branch_i64(i64 %0) { ; RV64: # %bb.0: ; RV64-NEXT: bgez a0, .LBB58_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB58_2: ; RV64-NEXT: ret %2 = and i64 %0, 9223372036854775808 @@ -2675,7 +2675,7 @@ define void @bit_10_1_z_branch_i32(i32 signext %0) { ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB89_2: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar %2 = and i32 %0, 1023 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -2694,7 +2694,7 @@ define void @bit_10_1_nz_branch_i32(i32 signext %0) { ; CHECK-NEXT: andi a0, a0, 1023 ; CHECK-NEXT: beqz a0, .LBB90_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB90_2: ; CHECK-NEXT: ret %2 = and i32 %0, 1023 @@ -2717,7 +2717,7 @@ define void @bit_11_1_z_branch_i32(i32 signext %0) { ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB91_2: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar %2 = and i32 %0, 2047 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -2736,7 +2736,7 @@ define void @bit_11_1_nz_branch_i32(i32 signext %0) { ; CHECK-NEXT: andi a0, a0, 2047 ; CHECK-NEXT: beqz a0, .LBB92_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB92_2: ; CHECK-NEXT: ret %2 = and i32 %0, 2047 @@ -2759,7 +2759,7 @@ define void @bit_16_1_z_branch_i32(i32 signext %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB93_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_16_1_z_branch_i32: ; RV64: # %bb.0: @@ -2768,7 +2768,7 @@ define void @bit_16_1_z_branch_i32(i32 signext %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB93_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i32 %0, 65535 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -2787,7 +2787,7 @@ define void @bit_16_1_nz_branch_i32(i32 signext %0) { ; RV32-NEXT: slli a0, a0, 16 ; RV32-NEXT: beqz a0, .LBB94_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB94_2: ; RV32-NEXT: ret ; @@ -2796,7 +2796,7 @@ define void @bit_16_1_nz_branch_i32(i32 signext %0) { ; RV64-NEXT: slli a0, a0, 48 ; RV64-NEXT: beqz a0, .LBB94_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB94_2: ; RV64-NEXT: ret %2 = and i32 %0, 65535 @@ -2819,7 +2819,7 @@ define void @bit_24_1_z_branch_i32(i32 signext %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB95_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_1_z_branch_i32: ; RV64: # %bb.0: @@ -2828,7 +2828,7 @@ define void @bit_24_1_z_branch_i32(i32 signext %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB95_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i32 %0, 16777215 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -2847,7 +2847,7 @@ define void @bit_24_1_nz_branch_i32(i32 signext %0) { ; RV32-NEXT: slli a0, a0, 8 ; RV32-NEXT: beqz a0, .LBB96_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB96_2: ; RV32-NEXT: ret ; @@ -2856,7 +2856,7 @@ define void @bit_24_1_nz_branch_i32(i32 signext %0) { ; RV64-NEXT: slli a0, a0, 40 ; RV64-NEXT: beqz a0, .LBB96_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB96_2: ; RV64-NEXT: ret %2 = and i32 %0, 16777215 @@ -2879,7 +2879,7 @@ define void @bit_31_1_z_branch_i32(i32 signext %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB97_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_1_z_branch_i32: ; RV64: # %bb.0: @@ -2888,7 +2888,7 @@ define void @bit_31_1_z_branch_i32(i32 signext %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB97_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i32 %0, 2147483647 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -2907,7 +2907,7 @@ define void @bit_31_1_nz_branch_i32(i32 signext %0) { ; RV32-NEXT: slli a0, a0, 1 ; RV32-NEXT: beqz a0, .LBB98_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB98_2: ; RV32-NEXT: ret ; @@ -2916,7 +2916,7 @@ define void @bit_31_1_nz_branch_i32(i32 signext %0) { ; RV64-NEXT: slli a0, a0, 33 ; RV64-NEXT: beqz a0, .LBB98_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB98_2: ; RV64-NEXT: ret %2 = and i32 %0, 2147483647 @@ -2938,7 +2938,7 @@ define void @bit_32_1_z_branch_i32(i32 signext %0) { ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB99_2: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar %2 = and i32 %0, 4294967295 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -2956,7 +2956,7 @@ define void @bit_32_1_nz_branch_i32(i32 signext %0) { ; CHECK: # %bb.0: ; CHECK-NEXT: beqz a0, .LBB100_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB100_2: ; CHECK-NEXT: ret %2 = and i32 %0, 4294967295 @@ -2980,7 +2980,7 @@ define void @bit_10_1_z_branch_i64(i64 %0) { ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB101_2: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar %2 = and i64 %0, 1023 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -2999,7 +2999,7 @@ define void @bit_10_1_nz_branch_i64(i64 %0) { ; CHECK-NEXT: andi a0, a0, 1023 ; CHECK-NEXT: beqz a0, .LBB102_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB102_2: ; CHECK-NEXT: ret %2 = and i64 %0, 1023 @@ -3022,7 +3022,7 @@ define void @bit_11_1_z_branch_i64(i64 %0) { ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB103_2: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar %2 = and i64 %0, 2047 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3041,7 +3041,7 @@ define void @bit_11_1_nz_branch_i64(i64 %0) { ; CHECK-NEXT: andi a0, a0, 2047 ; CHECK-NEXT: beqz a0, .LBB104_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB104_2: ; CHECK-NEXT: ret %2 = and i64 %0, 2047 @@ -3064,7 +3064,7 @@ define void @bit_16_1_z_branch_i64(i64 %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB105_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_16_1_z_branch_i64: ; RV64: # %bb.0: @@ -3073,7 +3073,7 @@ define void @bit_16_1_z_branch_i64(i64 %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB105_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i64 %0, 65535 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3092,7 +3092,7 @@ define void @bit_16_1_nz_branch_i64(i64 %0) { ; RV32-NEXT: slli a0, a0, 16 ; RV32-NEXT: beqz a0, .LBB106_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB106_2: ; RV32-NEXT: ret ; @@ -3101,7 +3101,7 @@ define void @bit_16_1_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 48 ; RV64-NEXT: beqz a0, .LBB106_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB106_2: ; RV64-NEXT: ret %2 = and i64 %0, 65535 @@ -3124,7 +3124,7 @@ define void @bit_24_1_z_branch_i64(i64 %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB107_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_1_z_branch_i64: ; RV64: # %bb.0: @@ -3133,7 +3133,7 @@ define void @bit_24_1_z_branch_i64(i64 %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB107_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i64 %0, 16777215 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3152,7 +3152,7 @@ define void @bit_24_1_nz_branch_i64(i64 %0) { ; RV32-NEXT: slli a0, a0, 8 ; RV32-NEXT: beqz a0, .LBB108_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB108_2: ; RV32-NEXT: ret ; @@ -3161,7 +3161,7 @@ define void @bit_24_1_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 40 ; RV64-NEXT: beqz a0, .LBB108_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB108_2: ; RV64-NEXT: ret %2 = and i64 %0, 16777215 @@ -3184,7 +3184,7 @@ define void @bit_31_1_z_branch_i64(i64 %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB109_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_1_z_branch_i64: ; RV64: # %bb.0: @@ -3193,7 +3193,7 @@ define void @bit_31_1_z_branch_i64(i64 %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB109_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i64 %0, 2147483647 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3212,7 +3212,7 @@ define void @bit_31_1_nz_branch_i64(i64 %0) { ; RV32-NEXT: slli a0, a0, 1 ; RV32-NEXT: beqz a0, .LBB110_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB110_2: ; RV32-NEXT: ret ; @@ -3221,7 +3221,7 @@ define void @bit_31_1_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 33 ; RV64-NEXT: beqz a0, .LBB110_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB110_2: ; RV64-NEXT: ret %2 = and i64 %0, 2147483647 @@ -3243,7 +3243,7 @@ define void @bit_32_1_z_branch_i64(i64 %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB111_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_32_1_z_branch_i64: ; RV64: # %bb.0: @@ -3252,7 +3252,7 @@ define void @bit_32_1_z_branch_i64(i64 %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB111_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i64 %0, 4294967295 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3270,7 +3270,7 @@ define void @bit_32_1_nz_branch_i64(i64 %0) { ; RV32: # %bb.0: ; RV32-NEXT: beqz a0, .LBB112_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB112_2: ; RV32-NEXT: ret ; @@ -3279,7 +3279,7 @@ define void @bit_32_1_nz_branch_i64(i64 %0) { ; RV64-NEXT: sext.w a0, a0 ; RV64-NEXT: beqz a0, .LBB112_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB112_2: ; RV64-NEXT: ret %2 = and i64 %0, 4294967295 @@ -3304,7 +3304,7 @@ define void @bit_62_1_z_branch_i64(i64 %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB113_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_62_1_z_branch_i64: ; RV64: # %bb.0: @@ -3313,7 +3313,7 @@ define void @bit_62_1_z_branch_i64(i64 %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB113_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i64 %0, 4611686018427387903 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3334,7 +3334,7 @@ define void @bit_62_1_nz_branch_i64(i64 %0) { ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: beqz a0, .LBB114_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB114_2: ; RV32-NEXT: ret ; @@ -3343,7 +3343,7 @@ define void @bit_62_1_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 2 ; RV64-NEXT: beqz a0, .LBB114_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB114_2: ; RV64-NEXT: ret %2 = and i64 %0, 4611686018427387903 @@ -3368,7 +3368,7 @@ define void @bit_63_1_z_branch_i64(i64 %0) { ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB115_2: -; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: tail bar ; ; RV64-LABEL: bit_63_1_z_branch_i64: ; RV64: # %bb.0: @@ -3377,7 +3377,7 @@ define void @bit_63_1_z_branch_i64(i64 %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB115_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; ; RV32ZBS-LABEL: bit_63_1_z_branch_i64: ; RV32ZBS: # %bb.0: @@ -3387,7 +3387,7 @@ define void @bit_63_1_z_branch_i64(i64 %0) { ; RV32ZBS-NEXT: # %bb.1: ; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: .LBB115_2: -; RV32ZBS-NEXT: tail bar@plt +; RV32ZBS-NEXT: tail bar ; ; RV32XTHEADBS-LABEL: bit_63_1_z_branch_i64: ; RV32XTHEADBS: # %bb.0: @@ -3398,7 +3398,7 @@ define void @bit_63_1_z_branch_i64(i64 %0) { ; RV32XTHEADBS-NEXT: # %bb.1: ; RV32XTHEADBS-NEXT: ret ; RV32XTHEADBS-NEXT: .LBB115_2: -; RV32XTHEADBS-NEXT: tail bar@plt +; RV32XTHEADBS-NEXT: tail bar %2 = and i64 %0, 9223372036854775807 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3419,7 +3419,7 @@ define void @bit_63_1_nz_branch_i64(i64 %0) { ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: beqz a0, .LBB116_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: tail bar ; RV32I-NEXT: .LBB116_2: ; RV32I-NEXT: ret ; @@ -3428,7 +3428,7 @@ define void @bit_63_1_nz_branch_i64(i64 %0) { ; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: beqz a0, .LBB116_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB116_2: ; RV64-NEXT: ret ; @@ -3438,7 +3438,7 @@ define void @bit_63_1_nz_branch_i64(i64 %0) { ; RV32ZBS-NEXT: or a0, a0, a1 ; RV32ZBS-NEXT: beqz a0, .LBB116_2 ; RV32ZBS-NEXT: # %bb.1: -; RV32ZBS-NEXT: tail bar@plt +; RV32ZBS-NEXT: tail bar ; RV32ZBS-NEXT: .LBB116_2: ; RV32ZBS-NEXT: ret ; @@ -3449,7 +3449,7 @@ define void @bit_63_1_nz_branch_i64(i64 %0) { ; RV32XTHEADBS-NEXT: or a0, a0, a1 ; RV32XTHEADBS-NEXT: beqz a0, .LBB116_2 ; RV32XTHEADBS-NEXT: # %bb.1: -; RV32XTHEADBS-NEXT: tail bar@plt +; RV32XTHEADBS-NEXT: tail bar ; RV32XTHEADBS-NEXT: .LBB116_2: ; RV32XTHEADBS-NEXT: ret %2 = and i64 %0, 9223372036854775807 @@ -3472,7 +3472,7 @@ define void @bit_64_1_z_branch_i64(i64 %0) { ; RV32-NEXT: # %bb.1: ; RV32-NEXT: ret ; RV32-NEXT: .LBB117_2: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_64_1_z_branch_i64: ; RV64: # %bb.0: @@ -3480,7 +3480,7 @@ define void @bit_64_1_z_branch_i64(i64 %0) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: ret ; RV64-NEXT: .LBB117_2: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar %2 = and i64 %0, 18446744073709551615 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -3499,7 +3499,7 @@ define void @bit_64_1_nz_branch_i64(i64 %0) { ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: beqz a0, .LBB118_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar@plt +; RV32-NEXT: tail bar ; RV32-NEXT: .LBB118_2: ; RV32-NEXT: ret ; @@ -3507,7 +3507,7 @@ define void @bit_64_1_nz_branch_i64(i64 %0) { ; RV64: # %bb.0: ; RV64-NEXT: beqz a0, .LBB118_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar@plt +; RV64-NEXT: tail bar ; RV64-NEXT: .LBB118_2: ; RV64-NEXT: ret %2 = and i64 %0, 18446744073709551615 diff --git a/llvm/test/CodeGen/RISCV/byval.ll b/llvm/test/CodeGen/RISCV/byval.ll index d300542e0807..9151f3b03e7c 100644 --- a/llvm/test/CodeGen/RISCV/byval.ll +++ b/llvm/test/CodeGen/RISCV/byval.ll @@ -32,7 +32,7 @@ define void @caller() nounwind { ; RV32I-NEXT: lw a0, 4(a0) ; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: addi a0, sp, 12 -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll index 1aa7783fedd2..79e80dac8241 100644 --- a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll @@ -629,7 +629,7 @@ define void @caller() nounwind { ; ILP32-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill ; ILP32-NEXT: flw fa5, 124(s1) ; ILP32-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill -; ILP32-NEXT: call callee@plt +; ILP32-NEXT: call callee ; ILP32-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload ; ILP32-NEXT: fsw fa5, 124(s1) ; ILP32-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload @@ -772,7 +772,7 @@ define void @caller() nounwind { ; LP64-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill ; LP64-NEXT: flw fa5, 124(s1) ; LP64-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill -; LP64-NEXT: call callee@plt +; LP64-NEXT: call callee ; LP64-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload ; LP64-NEXT: fsw fa5, 124(s1) ; LP64-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload @@ -915,7 +915,7 @@ define void @caller() nounwind { ; ILP32F-NEXT: flw fs5, 116(s1) ; ILP32F-NEXT: flw fs6, 120(s1) ; ILP32F-NEXT: flw fs7, 124(s1) -; ILP32F-NEXT: call callee@plt +; ILP32F-NEXT: call callee ; ILP32F-NEXT: fsw fs7, 124(s1) ; ILP32F-NEXT: fsw fs6, 120(s1) ; ILP32F-NEXT: fsw fs5, 116(s1) @@ -1058,7 +1058,7 @@ define void @caller() nounwind { ; LP64F-NEXT: flw fs5, 116(s1) ; LP64F-NEXT: flw fs6, 120(s1) ; LP64F-NEXT: flw fs7, 124(s1) -; LP64F-NEXT: call callee@plt +; LP64F-NEXT: call callee ; LP64F-NEXT: fsw fs7, 124(s1) ; LP64F-NEXT: fsw fs6, 120(s1) ; LP64F-NEXT: fsw fs5, 116(s1) @@ -1201,7 +1201,7 @@ define void @caller() nounwind { ; ILP32D-NEXT: flw fs5, 116(s1) ; ILP32D-NEXT: flw fs6, 120(s1) ; ILP32D-NEXT: flw fs7, 124(s1) -; ILP32D-NEXT: call callee@plt +; ILP32D-NEXT: call callee ; ILP32D-NEXT: fsw fs7, 124(s1) ; ILP32D-NEXT: fsw fs6, 120(s1) ; ILP32D-NEXT: fsw fs5, 116(s1) @@ -1344,7 +1344,7 @@ define void @caller() nounwind { ; LP64D-NEXT: flw fs5, 116(s1) ; LP64D-NEXT: flw fs6, 120(s1) ; LP64D-NEXT: flw fs7, 124(s1) -; LP64D-NEXT: call callee@plt +; LP64D-NEXT: call callee ; LP64D-NEXT: fsw fs7, 124(s1) ; LP64D-NEXT: fsw fs6, 120(s1) ; LP64D-NEXT: fsw fs5, 116(s1) diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll index 40076316bca8..abfa26e8a4f2 100644 --- a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll @@ -433,7 +433,7 @@ define void @caller() nounwind { ; ILP32-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill ; ILP32-NEXT: fld fa5, 248(s1) ; ILP32-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill -; ILP32-NEXT: call callee@plt +; ILP32-NEXT: call callee ; ILP32-NEXT: fld fa5, 0(sp) # 8-byte Folded Reload ; ILP32-NEXT: fsd fa5, 248(s1) ; ILP32-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload @@ -576,7 +576,7 @@ define void @caller() nounwind { ; LP64-NEXT: fsd fa5, 16(sp) # 8-byte Folded Spill ; LP64-NEXT: fld fa5, 248(s1) ; LP64-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill -; LP64-NEXT: call callee@plt +; LP64-NEXT: call callee ; LP64-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload ; LP64-NEXT: fsd fa5, 248(s1) ; LP64-NEXT: fld fa5, 16(sp) # 8-byte Folded Reload @@ -719,7 +719,7 @@ define void @caller() nounwind { ; ILP32D-NEXT: fld fs5, 232(s1) ; ILP32D-NEXT: fld fs6, 240(s1) ; ILP32D-NEXT: fld fs7, 248(s1) -; ILP32D-NEXT: call callee@plt +; ILP32D-NEXT: call callee ; ILP32D-NEXT: fsd fs7, 248(s1) ; ILP32D-NEXT: fsd fs6, 240(s1) ; ILP32D-NEXT: fsd fs5, 232(s1) @@ -862,7 +862,7 @@ define void @caller() nounwind { ; LP64D-NEXT: fld fs5, 232(s1) ; LP64D-NEXT: fld fs6, 240(s1) ; LP64D-NEXT: fld fs7, 248(s1) -; LP64D-NEXT: call callee@plt +; LP64D-NEXT: call callee ; LP64D-NEXT: fsd fs7, 248(s1) ; LP64D-NEXT: fsd fs6, 240(s1) ; LP64D-NEXT: fsd fs5, 232(s1) diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll index 09ecbbc7e8fe..6303a1245677 100644 --- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll @@ -952,7 +952,7 @@ define void @caller() nounwind { ; RV32I-NEXT: lw s11, 116(s5) ; RV32I-NEXT: lw s1, 120(s5) ; RV32I-NEXT: lw s2, 124(s5) -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: sw s2, 124(s5) ; RV32I-NEXT: sw s1, 120(s5) ; RV32I-NEXT: sw s11, 116(s5) @@ -1097,7 +1097,7 @@ define void @caller() nounwind { ; RV32I-WITH-FP-NEXT: lw s4, 116(s6) ; RV32I-WITH-FP-NEXT: lw s5, 120(s6) ; RV32I-WITH-FP-NEXT: lw s7, 124(s6) -; RV32I-WITH-FP-NEXT: call callee@plt +; RV32I-WITH-FP-NEXT: call callee ; RV32I-WITH-FP-NEXT: sw s7, 124(s6) ; RV32I-WITH-FP-NEXT: sw s5, 120(s6) ; RV32I-WITH-FP-NEXT: sw s4, 116(s6) @@ -1229,7 +1229,7 @@ define void @caller() nounwind { ; RV32IZCMP-NEXT: lw s11, 116(s1) ; RV32IZCMP-NEXT: lw s2, 120(s1) ; RV32IZCMP-NEXT: lw s3, 124(s1) -; RV32IZCMP-NEXT: call callee@plt +; RV32IZCMP-NEXT: call callee ; RV32IZCMP-NEXT: sw s3, 124(s1) ; RV32IZCMP-NEXT: sw s2, 120(s1) ; RV32IZCMP-NEXT: sw s11, 116(s1) @@ -1361,7 +1361,7 @@ define void @caller() nounwind { ; RV32IZCMP-WITH-FP-NEXT: lw s4, 116(s1) ; RV32IZCMP-WITH-FP-NEXT: lw s5, 120(s1) ; RV32IZCMP-WITH-FP-NEXT: lw s7, 124(s1) -; RV32IZCMP-WITH-FP-NEXT: call callee@plt +; RV32IZCMP-WITH-FP-NEXT: call callee ; RV32IZCMP-WITH-FP-NEXT: sw s7, 124(s1) ; RV32IZCMP-WITH-FP-NEXT: sw s5, 120(s1) ; RV32IZCMP-WITH-FP-NEXT: sw s4, 116(s1) @@ -1505,7 +1505,7 @@ define void @caller() nounwind { ; RV64I-NEXT: lw s11, 116(s5) ; RV64I-NEXT: lw s1, 120(s5) ; RV64I-NEXT: lw s2, 124(s5) -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: sw s2, 124(s5) ; RV64I-NEXT: sw s1, 120(s5) ; RV64I-NEXT: sw s11, 116(s5) @@ -1650,7 +1650,7 @@ define void @caller() nounwind { ; RV64I-WITH-FP-NEXT: lw s4, 116(s6) ; RV64I-WITH-FP-NEXT: lw s5, 120(s6) ; RV64I-WITH-FP-NEXT: lw s7, 124(s6) -; RV64I-WITH-FP-NEXT: call callee@plt +; RV64I-WITH-FP-NEXT: call callee ; RV64I-WITH-FP-NEXT: sw s7, 124(s6) ; RV64I-WITH-FP-NEXT: sw s5, 120(s6) ; RV64I-WITH-FP-NEXT: sw s4, 116(s6) @@ -1782,7 +1782,7 @@ define void @caller() nounwind { ; RV64IZCMP-NEXT: lw s11, 116(s1) ; RV64IZCMP-NEXT: lw s2, 120(s1) ; RV64IZCMP-NEXT: lw s3, 124(s1) -; RV64IZCMP-NEXT: call callee@plt +; RV64IZCMP-NEXT: call callee ; RV64IZCMP-NEXT: sw s3, 124(s1) ; RV64IZCMP-NEXT: sw s2, 120(s1) ; RV64IZCMP-NEXT: sw s11, 116(s1) @@ -1914,7 +1914,7 @@ define void @caller() nounwind { ; RV64IZCMP-WITH-FP-NEXT: lw s4, 116(s1) ; RV64IZCMP-WITH-FP-NEXT: lw s5, 120(s1) ; RV64IZCMP-WITH-FP-NEXT: lw s7, 124(s1) -; RV64IZCMP-WITH-FP-NEXT: call callee@plt +; RV64IZCMP-WITH-FP-NEXT: call callee ; RV64IZCMP-WITH-FP-NEXT: sw s7, 124(s1) ; RV64IZCMP-WITH-FP-NEXT: sw s5, 120(s1) ; RV64IZCMP-WITH-FP-NEXT: sw s4, 116(s1) @@ -2279,7 +2279,7 @@ define void @varargs(...) { ; RV32I-NEXT: sw a2, 24(sp) ; RV32I-NEXT: sw a1, 20(sp) ; RV32I-NEXT: sw a0, 16(sp) -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: ret @@ -2302,7 +2302,7 @@ define void @varargs(...) { ; RV32I-WITH-FP-NEXT: sw a2, 8(s0) ; RV32I-WITH-FP-NEXT: sw a1, 4(s0) ; RV32I-WITH-FP-NEXT: sw a0, 0(s0) -; RV32I-WITH-FP-NEXT: call callee@plt +; RV32I-WITH-FP-NEXT: call callee ; RV32I-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: addi sp, sp, 48 @@ -2322,7 +2322,7 @@ define void @varargs(...) { ; RV32IZCMP-NEXT: sw a2, 24(sp) ; RV32IZCMP-NEXT: sw a1, 20(sp) ; RV32IZCMP-NEXT: sw a0, 16(sp) -; RV32IZCMP-NEXT: call callee@plt +; RV32IZCMP-NEXT: call callee ; RV32IZCMP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZCMP-NEXT: addi sp, sp, 48 ; RV32IZCMP-NEXT: ret @@ -2345,7 +2345,7 @@ define void @varargs(...) { ; RV32IZCMP-WITH-FP-NEXT: sw a2, 8(s0) ; RV32IZCMP-WITH-FP-NEXT: sw a1, 4(s0) ; RV32IZCMP-WITH-FP-NEXT: sw a0, 0(s0) -; RV32IZCMP-WITH-FP-NEXT: call callee@plt +; RV32IZCMP-WITH-FP-NEXT: call callee ; RV32IZCMP-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZCMP-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 48 @@ -2365,7 +2365,7 @@ define void @varargs(...) { ; RV64I-NEXT: sd a2, 32(sp) ; RV64I-NEXT: sd a1, 24(sp) ; RV64I-NEXT: sd a0, 16(sp) -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: ret @@ -2388,7 +2388,7 @@ define void @varargs(...) { ; RV64I-WITH-FP-NEXT: sd a2, 16(s0) ; RV64I-WITH-FP-NEXT: sd a1, 8(s0) ; RV64I-WITH-FP-NEXT: sd a0, 0(s0) -; RV64I-WITH-FP-NEXT: call callee@plt +; RV64I-WITH-FP-NEXT: call callee ; RV64I-WITH-FP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: addi sp, sp, 80 @@ -2408,7 +2408,7 @@ define void @varargs(...) { ; RV64IZCMP-NEXT: sd a2, 32(sp) ; RV64IZCMP-NEXT: sd a1, 24(sp) ; RV64IZCMP-NEXT: sd a0, 16(sp) -; RV64IZCMP-NEXT: call callee@plt +; RV64IZCMP-NEXT: call callee ; RV64IZCMP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZCMP-NEXT: addi sp, sp, 80 ; RV64IZCMP-NEXT: ret @@ -2431,7 +2431,7 @@ define void @varargs(...) { ; RV64IZCMP-WITH-FP-NEXT: sd a2, 16(s0) ; RV64IZCMP-WITH-FP-NEXT: sd a1, 8(s0) ; RV64IZCMP-WITH-FP-NEXT: sd a0, 0(s0) -; RV64IZCMP-WITH-FP-NEXT: call callee@plt +; RV64IZCMP-WITH-FP-NEXT: call callee ; RV64IZCMP-WITH-FP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZCMP-WITH-FP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 80 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/calling-conv-half.ll index ad4578bda344..c88b2bf596ca 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-half.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-half.ll @@ -21,8 +21,8 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind { ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: add a0, s0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -37,8 +37,8 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: addw a0, s0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -52,7 +52,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind { ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: mv s0, a0 ; RV32IF-NEXT: mv a0, a1 -; RV32IF-NEXT: call __extendhfsf2@plt +; RV32IF-NEXT: call __extendhfsf2 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz ; RV32IF-NEXT: add a0, s0, a0 @@ -68,7 +68,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind { ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64IF-NEXT: mv s0, a0 ; RV64IF-NEXT: mv a0, a1 -; RV64IF-NEXT: call __extendhfsf2@plt +; RV64IF-NEXT: call __extendhfsf2 ; RV64IF-NEXT: fmv.w.x fa5, a0 ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz ; RV64IF-NEXT: addw a0, s0, a0 @@ -83,7 +83,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind { ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ILP32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-ILP32F-NEXT: mv s0, a0 -; RV32-ILP32F-NEXT: call __extendhfsf2@plt +; RV32-ILP32F-NEXT: call __extendhfsf2 ; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-ILP32F-NEXT: add a0, s0, a0 ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -97,7 +97,7 @@ define i32 @callee_half_in_regs(i32 %a, half %b) nounwind { ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64-LP64F-NEXT: mv s0, a0 -; RV64-LP64F-NEXT: call __extendhfsf2@plt +; RV64-LP64F-NEXT: call __extendhfsf2 ; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-LP64F-NEXT: addw a0, s0, a0 ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -130,7 +130,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a0, 1 ; RV32I-NEXT: lui a1, 4 -; RV32I-NEXT: call callee_half_in_regs@plt +; RV32I-NEXT: call callee_half_in_regs ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -141,7 +141,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a0, 1 ; RV64I-NEXT: lui a1, 4 -; RV64I-NEXT: call callee_half_in_regs@plt +; RV64I-NEXT: call callee_half_in_regs ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -152,7 +152,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: li a0, 1 ; RV32IF-NEXT: lui a1, 1048564 -; RV32IF-NEXT: call callee_half_in_regs@plt +; RV32IF-NEXT: call callee_half_in_regs ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -165,7 +165,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV64IF-NEXT: fmv.w.x fa5, a0 ; RV64IF-NEXT: fmv.x.w a1, fa5 ; RV64IF-NEXT: li a0, 1 -; RV64IF-NEXT: call callee_half_in_regs@plt +; RV64IF-NEXT: call callee_half_in_regs ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -177,7 +177,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV32-ILP32F-NEXT: lui a0, 1048564 ; RV32-ILP32F-NEXT: fmv.w.x fa0, a0 ; RV32-ILP32F-NEXT: li a0, 1 -; RV32-ILP32F-NEXT: call callee_half_in_regs@plt +; RV32-ILP32F-NEXT: call callee_half_in_regs ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32F-NEXT: addi sp, sp, 16 ; RV32-ILP32F-NEXT: ret @@ -189,7 +189,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV64-LP64F-NEXT: lui a0, 1048564 ; RV64-LP64F-NEXT: fmv.w.x fa0, a0 ; RV64-LP64F-NEXT: li a0, 1 -; RV64-LP64F-NEXT: call callee_half_in_regs@plt +; RV64-LP64F-NEXT: call callee_half_in_regs ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64F-NEXT: addi sp, sp, 16 ; RV64-LP64F-NEXT: ret @@ -201,7 +201,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV32-ILP32ZFHMIN-NEXT: lui a0, 4 ; RV32-ILP32ZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32-ILP32ZFHMIN-NEXT: li a0, 1 -; RV32-ILP32ZFHMIN-NEXT: call callee_half_in_regs@plt +; RV32-ILP32ZFHMIN-NEXT: call callee_half_in_regs ; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, 16 ; RV32-ILP32ZFHMIN-NEXT: ret @@ -213,7 +213,7 @@ define i32 @caller_half_in_regs() nounwind { ; RV64-LP64ZFHMIN-NEXT: lui a0, 4 ; RV64-LP64ZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV64-LP64ZFHMIN-NEXT: li a0, 1 -; RV64-LP64ZFHMIN-NEXT: call callee_half_in_regs@plt +; RV64-LP64ZFHMIN-NEXT: call callee_half_in_regs ; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16 ; RV64-LP64ZFHMIN-NEXT: ret @@ -229,8 +229,8 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: lhu a0, 16(sp) ; RV32I-NEXT: mv s0, a7 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: add a0, s0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -244,8 +244,8 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: lhu a0, 16(sp) ; RV64I-NEXT: mv s0, a7 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: addw a0, s0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -259,7 +259,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: lhu a0, 16(sp) ; RV32IF-NEXT: mv s0, a7 -; RV32IF-NEXT: call __extendhfsf2@plt +; RV32IF-NEXT: call __extendhfsf2 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz ; RV32IF-NEXT: add a0, s0, a0 @@ -275,7 +275,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64IF-NEXT: lhu a0, 16(sp) ; RV64IF-NEXT: mv s0, a7 -; RV64IF-NEXT: call __extendhfsf2@plt +; RV64IF-NEXT: call __extendhfsf2 ; RV64IF-NEXT: fmv.w.x fa5, a0 ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz ; RV64IF-NEXT: addw a0, s0, a0 @@ -290,7 +290,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ILP32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-ILP32F-NEXT: mv s0, a7 -; RV32-ILP32F-NEXT: call __extendhfsf2@plt +; RV32-ILP32F-NEXT: call __extendhfsf2 ; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-ILP32F-NEXT: add a0, s0, a0 ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -304,7 +304,7 @@ define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-LP64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64-LP64F-NEXT: mv s0, a7 -; RV64-LP64F-NEXT: call __extendhfsf2@plt +; RV64-LP64F-NEXT: call __extendhfsf2 ; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-LP64F-NEXT: addw a0, s0, a0 ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -346,7 +346,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV32I-NEXT: li a6, 7 ; RV32I-NEXT: li a7, 8 ; RV32I-NEXT: sw t0, 0(sp) -; RV32I-NEXT: call callee_half_on_stack@plt +; RV32I-NEXT: call callee_half_on_stack ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -366,7 +366,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV64I-NEXT: li a6, 7 ; RV64I-NEXT: li a7, 8 ; RV64I-NEXT: sd t0, 0(sp) -; RV64I-NEXT: call callee_half_on_stack@plt +; RV64I-NEXT: call callee_half_on_stack ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -386,7 +386,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV32IF-NEXT: li a6, 7 ; RV32IF-NEXT: li a7, 8 ; RV32IF-NEXT: sw t0, 0(sp) -; RV32IF-NEXT: call callee_half_on_stack@plt +; RV32IF-NEXT: call callee_half_on_stack ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -406,7 +406,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV64IF-NEXT: li a6, 7 ; RV64IF-NEXT: li a7, 8 ; RV64IF-NEXT: sw t0, 0(sp) -; RV64IF-NEXT: call callee_half_on_stack@plt +; RV64IF-NEXT: call callee_half_on_stack ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -425,7 +425,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV32-ILP32F-NEXT: li a5, 6 ; RV32-ILP32F-NEXT: li a6, 7 ; RV32-ILP32F-NEXT: li a7, 8 -; RV32-ILP32F-NEXT: call callee_half_on_stack@plt +; RV32-ILP32F-NEXT: call callee_half_on_stack ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32F-NEXT: addi sp, sp, 16 ; RV32-ILP32F-NEXT: ret @@ -444,7 +444,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV64-LP64F-NEXT: li a5, 6 ; RV64-LP64F-NEXT: li a6, 7 ; RV64-LP64F-NEXT: li a7, 8 -; RV64-LP64F-NEXT: call callee_half_on_stack@plt +; RV64-LP64F-NEXT: call callee_half_on_stack ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64F-NEXT: addi sp, sp, 16 ; RV64-LP64F-NEXT: ret @@ -463,7 +463,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV32-ILP32ZFHMIN-NEXT: li a5, 6 ; RV32-ILP32ZFHMIN-NEXT: li a6, 7 ; RV32-ILP32ZFHMIN-NEXT: li a7, 8 -; RV32-ILP32ZFHMIN-NEXT: call callee_half_on_stack@plt +; RV32-ILP32ZFHMIN-NEXT: call callee_half_on_stack ; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, 16 ; RV32-ILP32ZFHMIN-NEXT: ret @@ -482,7 +482,7 @@ define i32 @caller_half_on_stack() nounwind { ; RV64-LP64ZFHMIN-NEXT: li a5, 6 ; RV64-LP64ZFHMIN-NEXT: li a6, 7 ; RV64-LP64ZFHMIN-NEXT: li a7, 8 -; RV64-LP64ZFHMIN-NEXT: call callee_half_on_stack@plt +; RV64-LP64ZFHMIN-NEXT: call callee_half_on_stack ; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, 16 ; RV64-LP64ZFHMIN-NEXT: ret @@ -547,11 +547,11 @@ define i32 @caller_half_ret() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call callee_half_ret@plt +; RV32I-NEXT: call callee_half_ret ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -560,11 +560,11 @@ define i32 @caller_half_ret() nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call callee_half_ret@plt +; RV64I-NEXT: call callee_half_ret ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -573,8 +573,8 @@ define i32 @caller_half_ret() nounwind { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call callee_half_ret@plt -; RV32IF-NEXT: call __extendhfsf2@plt +; RV32IF-NEXT: call callee_half_ret +; RV32IF-NEXT: call __extendhfsf2 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -585,8 +585,8 @@ define i32 @caller_half_ret() nounwind { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call callee_half_ret@plt -; RV64IF-NEXT: call __extendhfsf2@plt +; RV64IF-NEXT: call callee_half_ret +; RV64IF-NEXT: call __extendhfsf2 ; RV64IF-NEXT: fmv.w.x fa5, a0 ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -597,8 +597,8 @@ define i32 @caller_half_ret() nounwind { ; RV32-ILP32F: # %bb.0: ; RV32-ILP32F-NEXT: addi sp, sp, -16 ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ILP32F-NEXT: call callee_half_ret@plt -; RV32-ILP32F-NEXT: call __extendhfsf2@plt +; RV32-ILP32F-NEXT: call callee_half_ret +; RV32-ILP32F-NEXT: call __extendhfsf2 ; RV32-ILP32F-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32F-NEXT: addi sp, sp, 16 @@ -608,8 +608,8 @@ define i32 @caller_half_ret() nounwind { ; RV64-LP64F: # %bb.0: ; RV64-LP64F-NEXT: addi sp, sp, -16 ; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-LP64F-NEXT: call callee_half_ret@plt -; RV64-LP64F-NEXT: call __extendhfsf2@plt +; RV64-LP64F-NEXT: call callee_half_ret +; RV64-LP64F-NEXT: call __extendhfsf2 ; RV64-LP64F-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64F-NEXT: addi sp, sp, 16 @@ -619,7 +619,7 @@ define i32 @caller_half_ret() nounwind { ; RV32-ILP32ZFHMIN: # %bb.0: ; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, -16 ; RV32-ILP32ZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ILP32ZFHMIN-NEXT: call callee_half_ret@plt +; RV32-ILP32ZFHMIN-NEXT: call callee_half_ret ; RV32-ILP32ZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; RV32-ILP32ZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz ; RV32-ILP32ZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -630,7 +630,7 @@ define i32 @caller_half_ret() nounwind { ; RV64-LP64ZFHMIN: # %bb.0: ; RV64-LP64ZFHMIN-NEXT: addi sp, sp, -16 ; RV64-LP64ZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-LP64ZFHMIN-NEXT: call callee_half_ret@plt +; RV64-LP64ZFHMIN-NEXT: call callee_half_ret ; RV64-LP64ZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; RV64-LP64ZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz ; RV64-LP64ZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll index 24e2d31707e9..278187f62cd7 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll @@ -26,7 +26,7 @@ define i32 @callee_double_in_regs(i32 %a, double %b) nounwind { ; RV32I-FPELIM-NEXT: mv s0, a0 ; RV32I-FPELIM-NEXT: mv a0, a1 ; RV32I-FPELIM-NEXT: mv a1, a2 -; RV32I-FPELIM-NEXT: call __fixdfsi@plt +; RV32I-FPELIM-NEXT: call __fixdfsi ; RV32I-FPELIM-NEXT: add a0, s0, a0 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -43,7 +43,7 @@ define i32 @callee_double_in_regs(i32 %a, double %b) nounwind { ; RV32I-WITHFP-NEXT: mv s1, a0 ; RV32I-WITHFP-NEXT: mv a0, a1 ; RV32I-WITHFP-NEXT: mv a1, a2 -; RV32I-WITHFP-NEXT: call __fixdfsi@plt +; RV32I-WITHFP-NEXT: call __fixdfsi ; RV32I-WITHFP-NEXT: add a0, s1, a0 ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -63,7 +63,7 @@ define i32 @caller_double_in_regs() nounwind { ; RV32I-FPELIM-NEXT: li a0, 1 ; RV32I-FPELIM-NEXT: lui a2, 262144 ; RV32I-FPELIM-NEXT: li a1, 0 -; RV32I-FPELIM-NEXT: call callee_double_in_regs@plt +; RV32I-FPELIM-NEXT: call callee_double_in_regs ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -77,7 +77,7 @@ define i32 @caller_double_in_regs() nounwind { ; RV32I-WITHFP-NEXT: li a0, 1 ; RV32I-WITHFP-NEXT: lui a2, 262144 ; RV32I-WITHFP-NEXT: li a1, 0 -; RV32I-WITHFP-NEXT: call callee_double_in_regs@plt +; RV32I-WITHFP-NEXT: call callee_double_in_regs ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -180,7 +180,7 @@ define void @caller_aligned_stack() nounwind { ; RV32I-FPELIM-NEXT: li a6, 4 ; RV32I-FPELIM-NEXT: li a7, 14 ; RV32I-FPELIM-NEXT: sw t0, 32(sp) -; RV32I-FPELIM-NEXT: call callee_aligned_stack@plt +; RV32I-FPELIM-NEXT: call callee_aligned_stack ; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: ret @@ -226,7 +226,7 @@ define void @caller_aligned_stack() nounwind { ; RV32I-WITHFP-NEXT: li a6, 4 ; RV32I-WITHFP-NEXT: li a7, 14 ; RV32I-WITHFP-NEXT: sw t0, -32(s0) -; RV32I-WITHFP-NEXT: call callee_aligned_stack@plt +; RV32I-WITHFP-NEXT: call callee_aligned_stack ; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 64 @@ -265,7 +265,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-FPELIM-NEXT: call callee_small_scalar_ret@plt +; RV32I-FPELIM-NEXT: call callee_small_scalar_ret ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -276,7 +276,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: call callee_small_scalar_ret@plt +; RV32I-WITHFP-NEXT: call callee_small_scalar_ret ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll index 649234efaad9..231ed159ab20 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -54,7 +54,7 @@ define i32 @caller_i64_in_regs() nounwind { ; RV32I-FPELIM-NEXT: li a0, 1 ; RV32I-FPELIM-NEXT: li a1, 2 ; RV32I-FPELIM-NEXT: li a2, 0 -; RV32I-FPELIM-NEXT: call callee_i64_in_regs@plt +; RV32I-FPELIM-NEXT: call callee_i64_in_regs ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -68,7 +68,7 @@ define i32 @caller_i64_in_regs() nounwind { ; RV32I-WITHFP-NEXT: li a0, 1 ; RV32I-WITHFP-NEXT: li a1, 2 ; RV32I-WITHFP-NEXT: li a2, 0 -; RV32I-WITHFP-NEXT: call callee_i64_in_regs@plt +; RV32I-WITHFP-NEXT: call callee_i64_in_regs ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -153,7 +153,7 @@ define i32 @caller_many_scalars() nounwind { ; RV32I-FPELIM-NEXT: li a7, 7 ; RV32I-FPELIM-NEXT: sw zero, 0(sp) ; RV32I-FPELIM-NEXT: li a4, 0 -; RV32I-FPELIM-NEXT: call callee_many_scalars@plt +; RV32I-FPELIM-NEXT: call callee_many_scalars ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -175,7 +175,7 @@ define i32 @caller_many_scalars() nounwind { ; RV32I-WITHFP-NEXT: li a7, 7 ; RV32I-WITHFP-NEXT: sw zero, 0(sp) ; RV32I-WITHFP-NEXT: li a4, 0 -; RV32I-WITHFP-NEXT: call callee_many_scalars@plt +; RV32I-WITHFP-NEXT: call callee_many_scalars ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -257,7 +257,7 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-FPELIM-NEXT: addi a0, sp, 24 ; RV32I-FPELIM-NEXT: mv a1, sp ; RV32I-FPELIM-NEXT: sw a2, 24(sp) -; RV32I-FPELIM-NEXT: call callee_large_scalars@plt +; RV32I-FPELIM-NEXT: call callee_large_scalars ; RV32I-FPELIM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: ret @@ -280,7 +280,7 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-WITHFP-NEXT: addi a0, s0, -24 ; RV32I-WITHFP-NEXT: addi a1, s0, -48 ; RV32I-WITHFP-NEXT: sw a2, -24(s0) -; RV32I-WITHFP-NEXT: call callee_large_scalars@plt +; RV32I-WITHFP-NEXT: call callee_large_scalars ; RV32I-WITHFP-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -375,7 +375,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-FPELIM-NEXT: li a6, 7 ; RV32I-FPELIM-NEXT: addi a7, sp, 40 ; RV32I-FPELIM-NEXT: sw zero, 44(sp) -; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs@plt +; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: ret @@ -408,7 +408,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-WITHFP-NEXT: li a6, 7 ; RV32I-WITHFP-NEXT: addi a7, s0, -24 ; RV32I-WITHFP-NEXT: sw zero, -20(s0) -; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs@plt +; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 64 @@ -429,7 +429,7 @@ define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind { ; RV32I-FPELIM-NEXT: mv a2, a1 ; RV32I-FPELIM-NEXT: mv a1, a0 ; RV32I-FPELIM-NEXT: addi a0, sp, 8 -; RV32I-FPELIM-NEXT: call __floatditf@plt +; RV32I-FPELIM-NEXT: call __floatditf ; RV32I-FPELIM-NEXT: lw a0, 8(sp) ; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 32 @@ -444,7 +444,7 @@ define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind { ; RV32I-WITHFP-NEXT: mv a2, a1 ; RV32I-WITHFP-NEXT: mv a1, a0 ; RV32I-WITHFP-NEXT: addi a0, s0, -24 -; RV32I-WITHFP-NEXT: call __floatditf@plt +; RV32I-WITHFP-NEXT: call __floatditf ; RV32I-WITHFP-NEXT: lw a0, -24(s0) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload @@ -493,7 +493,7 @@ define i32 @caller_small_coerced_struct() nounwind { ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-FPELIM-NEXT: li a0, 1 ; RV32I-FPELIM-NEXT: li a1, 2 -; RV32I-FPELIM-NEXT: call callee_small_coerced_struct@plt +; RV32I-FPELIM-NEXT: call callee_small_coerced_struct ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -506,7 +506,7 @@ define i32 @caller_small_coerced_struct() nounwind { ; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: li a0, 1 ; RV32I-WITHFP-NEXT: li a1, 2 -; RV32I-WITHFP-NEXT: call callee_small_coerced_struct@plt +; RV32I-WITHFP-NEXT: call callee_small_coerced_struct ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -565,7 +565,7 @@ define i32 @caller_large_struct() nounwind { ; RV32I-FPELIM-NEXT: sw a2, 16(sp) ; RV32I-FPELIM-NEXT: sw a3, 20(sp) ; RV32I-FPELIM-NEXT: addi a0, sp, 8 -; RV32I-FPELIM-NEXT: call callee_large_struct@plt +; RV32I-FPELIM-NEXT: call callee_large_struct ; RV32I-FPELIM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: ret @@ -589,7 +589,7 @@ define i32 @caller_large_struct() nounwind { ; RV32I-WITHFP-NEXT: sw a2, -32(s0) ; RV32I-WITHFP-NEXT: sw a3, -28(s0) ; RV32I-WITHFP-NEXT: addi a0, s0, -40 -; RV32I-WITHFP-NEXT: call callee_large_struct@plt +; RV32I-WITHFP-NEXT: call callee_large_struct ; RV32I-WITHFP-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -696,7 +696,7 @@ define void @caller_aligned_stack() nounwind { ; RV32I-FPELIM-NEXT: li a6, 4 ; RV32I-FPELIM-NEXT: li a7, 14 ; RV32I-FPELIM-NEXT: sw t0, 32(sp) -; RV32I-FPELIM-NEXT: call callee_aligned_stack@plt +; RV32I-FPELIM-NEXT: call callee_aligned_stack ; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: ret @@ -739,7 +739,7 @@ define void @caller_aligned_stack() nounwind { ; RV32I-WITHFP-NEXT: li a6, 4 ; RV32I-WITHFP-NEXT: li a7, 14 ; RV32I-WITHFP-NEXT: sw t0, -32(s0) -; RV32I-WITHFP-NEXT: call callee_aligned_stack@plt +; RV32I-WITHFP-NEXT: call callee_aligned_stack ; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 64 @@ -782,7 +782,7 @@ define i32 @caller_small_scalar_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-FPELIM-NEXT: call callee_small_scalar_ret@plt +; RV32I-FPELIM-NEXT: call callee_small_scalar_ret ; RV32I-FPELIM-NEXT: lui a2, 56 ; RV32I-FPELIM-NEXT: addi a2, a2, 580 ; RV32I-FPELIM-NEXT: xor a1, a1, a2 @@ -801,7 +801,7 @@ define i32 @caller_small_scalar_ret() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: call callee_small_scalar_ret@plt +; RV32I-WITHFP-NEXT: call callee_small_scalar_ret ; RV32I-WITHFP-NEXT: lui a2, 56 ; RV32I-WITHFP-NEXT: addi a2, a2, 580 ; RV32I-WITHFP-NEXT: xor a1, a1, a2 @@ -849,7 +849,7 @@ define i32 @caller_small_struct_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-FPELIM-NEXT: call callee_small_struct_ret@plt +; RV32I-FPELIM-NEXT: call callee_small_struct_ret ; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 @@ -861,7 +861,7 @@ define i32 @caller_small_struct_ret() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: call callee_small_struct_ret@plt +; RV32I-WITHFP-NEXT: call callee_small_struct_ret ; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -911,7 +911,7 @@ define void @caller_large_scalar_ret() nounwind { ; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-FPELIM-NEXT: mv a0, sp -; RV32I-FPELIM-NEXT: call callee_large_scalar_ret@plt +; RV32I-FPELIM-NEXT: call callee_large_scalar_ret ; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: ret @@ -923,7 +923,7 @@ define void @caller_large_scalar_ret() nounwind { ; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: addi a0, s0, -32 -; RV32I-WITHFP-NEXT: call callee_large_scalar_ret@plt +; RV32I-WITHFP-NEXT: call callee_large_scalar_ret ; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 32 @@ -981,7 +981,7 @@ define i32 @caller_large_struct_ret() nounwind { ; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-FPELIM-NEXT: addi a0, sp, 8 -; RV32I-FPELIM-NEXT: call callee_large_struct_ret@plt +; RV32I-FPELIM-NEXT: call callee_large_struct_ret ; RV32I-FPELIM-NEXT: lw a0, 8(sp) ; RV32I-FPELIM-NEXT: lw a1, 20(sp) ; RV32I-FPELIM-NEXT: add a0, a0, a1 @@ -996,7 +996,7 @@ define i32 @caller_large_struct_ret() nounwind { ; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: addi a0, s0, -24 -; RV32I-WITHFP-NEXT: call callee_large_struct_ret@plt +; RV32I-WITHFP-NEXT: call callee_large_struct_ret ; RV32I-WITHFP-NEXT: lw a0, -24(s0) ; RV32I-WITHFP-NEXT: lw a1, -12(s0) ; RV32I-WITHFP-NEXT: add a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll index 07acb9fd80a9..1dac139503ba 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll @@ -20,7 +20,7 @@ define i32 @callee_float_in_regs(i32 %a, float %b) nounwind { ; RV32I-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-FPELIM-NEXT: mv s0, a0 ; RV32I-FPELIM-NEXT: mv a0, a1 -; RV32I-FPELIM-NEXT: call __fixsfsi@plt +; RV32I-FPELIM-NEXT: call __fixsfsi ; RV32I-FPELIM-NEXT: add a0, s0, a0 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -36,7 +36,7 @@ define i32 @callee_float_in_regs(i32 %a, float %b) nounwind { ; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: mv s1, a0 ; RV32I-WITHFP-NEXT: mv a0, a1 -; RV32I-WITHFP-NEXT: call __fixsfsi@plt +; RV32I-WITHFP-NEXT: call __fixsfsi ; RV32I-WITHFP-NEXT: add a0, s1, a0 ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -55,7 +55,7 @@ define i32 @caller_float_in_regs() nounwind { ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-FPELIM-NEXT: li a0, 1 ; RV32I-FPELIM-NEXT: lui a1, 262144 -; RV32I-FPELIM-NEXT: call callee_float_in_regs@plt +; RV32I-FPELIM-NEXT: call callee_float_in_regs ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -68,7 +68,7 @@ define i32 @caller_float_in_regs() nounwind { ; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: li a0, 1 ; RV32I-WITHFP-NEXT: lui a1, 262144 -; RV32I-WITHFP-NEXT: call callee_float_in_regs@plt +; RV32I-WITHFP-NEXT: call callee_float_in_regs ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -117,7 +117,7 @@ define i32 @caller_float_on_stack() nounwind { ; RV32I-FPELIM-NEXT: li a3, 0 ; RV32I-FPELIM-NEXT: li a5, 0 ; RV32I-FPELIM-NEXT: li a7, 0 -; RV32I-FPELIM-NEXT: call callee_float_on_stack@plt +; RV32I-FPELIM-NEXT: call callee_float_on_stack ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -138,7 +138,7 @@ define i32 @caller_float_on_stack() nounwind { ; RV32I-WITHFP-NEXT: li a3, 0 ; RV32I-WITHFP-NEXT: li a5, 0 ; RV32I-WITHFP-NEXT: li a7, 0 -; RV32I-WITHFP-NEXT: call callee_float_on_stack@plt +; RV32I-WITHFP-NEXT: call callee_float_on_stack ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -172,7 +172,7 @@ define i32 @caller_tiny_scalar_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret@plt +; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -183,7 +183,7 @@ define i32 @caller_tiny_scalar_ret() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret@plt +; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll index 4897170a82f2..bcceea7ac35b 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll @@ -25,7 +25,7 @@ define i32 @caller_double_in_fpr() nounwind { ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI1_0) ; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI1_0)(a0) ; RV32-ILP32D-NEXT: li a0, 1 -; RV32-ILP32D-NEXT: call callee_double_in_fpr@plt +; RV32-ILP32D-NEXT: call callee_double_in_fpr ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: ret @@ -63,7 +63,7 @@ define i32 @caller_double_in_fpr_exhausted_gprs() nounwind { ; RV32-ILP32D-NEXT: li a3, 0 ; RV32-ILP32D-NEXT: li a5, 0 ; RV32-ILP32D-NEXT: li a7, 0 -; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs@plt +; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: ret @@ -114,7 +114,7 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind { ; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a0) ; RV32-ILP32D-NEXT: lui a1, 262688 ; RV32-ILP32D-NEXT: li a0, 0 -; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs@plt +; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: ret @@ -173,7 +173,7 @@ define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind ; RV32-ILP32D-NEXT: li a3, 0 ; RV32-ILP32D-NEXT: li a5, 0 ; RV32-ILP32D-NEXT: li a7, 0 -; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs@plt +; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: ret @@ -230,7 +230,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind { ; RV32-ILP32D-NEXT: li a3, 0 ; RV32-ILP32D-NEXT: li a5, 0 ; RV32-ILP32D-NEXT: li a7, 0 -; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs@plt +; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: ret @@ -254,7 +254,7 @@ define i32 @caller_double_ret() nounwind { ; RV32-ILP32D: # %bb.0: ; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ILP32D-NEXT: call callee_double_ret@plt +; RV32-ILP32D-NEXT: call callee_double_ret ; RV32-ILP32D-NEXT: fsd fa0, 0(sp) ; RV32-ILP32D-NEXT: lw a0, 0(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll index bb51f71358ad..b0d60a7aaa23 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll @@ -28,7 +28,7 @@ define i32 @caller_float_in_fpr() nounwind { ; RV32-ILP32FD-NEXT: lui a0, 262144 ; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0 ; RV32-ILP32FD-NEXT: li a0, 1 -; RV32-ILP32FD-NEXT: call callee_float_in_fpr@plt +; RV32-ILP32FD-NEXT: call callee_float_in_fpr ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: ret @@ -66,7 +66,7 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind { ; RV32-ILP32FD-NEXT: li a3, 0 ; RV32-ILP32FD-NEXT: li a5, 0 ; RV32-ILP32FD-NEXT: li a7, 0 -; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs@plt +; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: ret @@ -112,7 +112,7 @@ define i32 @caller_float_in_gpr_exhausted_fprs() nounwind { ; RV32-ILP32FD-NEXT: lui a0, 266240 ; RV32-ILP32FD-NEXT: fmv.w.x fa7, a0 ; RV32-ILP32FD-NEXT: lui a0, 266496 -; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs@plt +; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: ret @@ -167,7 +167,7 @@ define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind { ; RV32-ILP32FD-NEXT: li a3, 0 ; RV32-ILP32FD-NEXT: li a5, 0 ; RV32-ILP32FD-NEXT: li a7, 0 -; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs@plt +; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: ret @@ -191,7 +191,7 @@ define i32 @caller_float_ret() nounwind { ; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ILP32FD-NEXT: call callee_float_ret@plt +; RV32-ILP32FD-NEXT: call callee_float_ret ; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0 ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32FD-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll index f424e77182a9..a1d8ea66980d 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll @@ -17,7 +17,7 @@ define i64 @callee_double_in_regs(i64 %a, double %b) nounwind { ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, a1 -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: add a0, s0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -36,7 +36,7 @@ define i64 @caller_double_in_regs() nounwind { ; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: slli a1, a1, 62 ; RV64I-NEXT: li a0, 1 -; RV64I-NEXT: call callee_double_in_regs@plt +; RV64I-NEXT: call callee_double_in_regs ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -58,7 +58,7 @@ define i64 @caller_double_ret() nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call callee_double_ret@plt +; RV64I-NEXT: call callee_double_ret ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll index c2690d15665e..d84711294330 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll @@ -35,7 +35,7 @@ define i64 @caller_i128_in_regs() nounwind { ; RV64I-NEXT: li a0, 1 ; RV64I-NEXT: li a1, 2 ; RV64I-NEXT: li a2, 0 -; RV64I-NEXT: call callee_i128_in_regs@plt +; RV64I-NEXT: call callee_i128_in_regs ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -93,7 +93,7 @@ define i32 @caller_many_scalars() nounwind { ; RV64I-NEXT: li a7, 7 ; RV64I-NEXT: sd zero, 0(sp) ; RV64I-NEXT: li a4, 0 -; RV64I-NEXT: call callee_many_scalars@plt +; RV64I-NEXT: call callee_many_scalars ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret @@ -145,7 +145,7 @@ define i64 @caller_large_scalars() nounwind { ; RV64I-NEXT: addi a0, sp, 32 ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: sd zero, 40(sp) -; RV64I-NEXT: call callee_large_scalars@plt +; RV64I-NEXT: call callee_large_scalars ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: ret @@ -210,7 +210,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind { ; RV64I-NEXT: li a6, 7 ; RV64I-NEXT: addi a7, sp, 48 ; RV64I-NEXT: sd zero, 56(sp) -; RV64I-NEXT: call callee_large_scalars_exhausted_regs@plt +; RV64I-NEXT: call callee_large_scalars_exhausted_regs ; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: ret @@ -227,7 +227,7 @@ define i64 @caller_mixed_scalar_libcalls(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatditf@plt +; RV64I-NEXT: call __floatditf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -261,7 +261,7 @@ define i64 @caller_small_coerced_struct() nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a0, 1 ; RV64I-NEXT: li a1, 2 -; RV64I-NEXT: call callee_small_coerced_struct@plt +; RV64I-NEXT: call callee_small_coerced_struct ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -305,7 +305,7 @@ define i64 @caller_large_struct() nounwind { ; RV64I-NEXT: sd a2, 24(sp) ; RV64I-NEXT: sd a3, 32(sp) ; RV64I-NEXT: addi a0, sp, 8 -; RV64I-NEXT: call callee_large_struct@plt +; RV64I-NEXT: call callee_large_struct ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: ret @@ -375,7 +375,7 @@ define void @caller_aligned_stack() nounwind { ; RV64I-NEXT: li a7, 7 ; RV64I-NEXT: sd a6, 0(sp) ; RV64I-NEXT: li a6, 0 -; RV64I-NEXT: call callee_aligned_stack@plt +; RV64I-NEXT: call callee_aligned_stack ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: ret @@ -400,7 +400,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call callee_small_scalar_ret@plt +; RV64I-NEXT: call callee_small_scalar_ret ; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: xori a0, a0, -2 ; RV64I-NEXT: or a0, a0, a1 @@ -430,7 +430,7 @@ define i64 @caller_small_struct_ret() nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call callee_small_struct_ret@plt +; RV64I-NEXT: call callee_small_struct_ret ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -465,7 +465,7 @@ define void @caller_large_scalar_ret() nounwind { ; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee_large_scalar_ret@plt +; RV64I-NEXT: call callee_large_scalar_ret ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret @@ -507,7 +507,7 @@ define i64 @caller_large_struct_ret() nounwind { ; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a0, sp, 8 -; RV64I-NEXT: call callee_large_struct_ret@plt +; RV64I-NEXT: call callee_large_struct_ret ; RV64I-NEXT: ld a0, 8(sp) ; RV64I-NEXT: ld a1, 32(sp) ; RV64I-NEXT: add a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll index bf98412bc315..c2db8fe5248f 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll @@ -22,7 +22,7 @@ define i64 @callee_float_in_regs(i64 %a, float %b) nounwind { ; RV64I-FPELIM-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-FPELIM-NEXT: mv s0, a0 ; RV64I-FPELIM-NEXT: mv a0, a1 -; RV64I-FPELIM-NEXT: call __fixsfdi@plt +; RV64I-FPELIM-NEXT: call __fixsfdi ; RV64I-FPELIM-NEXT: add a0, s0, a0 ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-FPELIM-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -38,7 +38,7 @@ define i64 @callee_float_in_regs(i64 %a, float %b) nounwind { ; RV64I-WITHFP-NEXT: addi s0, sp, 32 ; RV64I-WITHFP-NEXT: mv s1, a0 ; RV64I-WITHFP-NEXT: mv a0, a1 -; RV64I-WITHFP-NEXT: call __fixsfdi@plt +; RV64I-WITHFP-NEXT: call __fixsfdi ; RV64I-WITHFP-NEXT: add a0, s1, a0 ; RV64I-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -57,7 +57,7 @@ define i64 @caller_float_in_regs() nounwind { ; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-FPELIM-NEXT: li a0, 1 ; RV64I-FPELIM-NEXT: lui a1, 262144 -; RV64I-FPELIM-NEXT: call callee_float_in_regs@plt +; RV64I-FPELIM-NEXT: call callee_float_in_regs ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-FPELIM-NEXT: addi sp, sp, 16 ; RV64I-FPELIM-NEXT: ret @@ -70,7 +70,7 @@ define i64 @caller_float_in_regs() nounwind { ; RV64I-WITHFP-NEXT: addi s0, sp, 16 ; RV64I-WITHFP-NEXT: li a0, 1 ; RV64I-WITHFP-NEXT: lui a1, 262144 -; RV64I-WITHFP-NEXT: call callee_float_in_regs@plt +; RV64I-WITHFP-NEXT: call callee_float_in_regs ; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-WITHFP-NEXT: addi sp, sp, 16 @@ -118,7 +118,7 @@ define i64 @caller_float_on_stack() nounwind { ; RV64I-FPELIM-NEXT: li a3, 0 ; RV64I-FPELIM-NEXT: li a5, 0 ; RV64I-FPELIM-NEXT: li a7, 0 -; RV64I-FPELIM-NEXT: call callee_float_on_stack@plt +; RV64I-FPELIM-NEXT: call callee_float_on_stack ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-FPELIM-NEXT: addi sp, sp, 16 ; RV64I-FPELIM-NEXT: ret @@ -139,7 +139,7 @@ define i64 @caller_float_on_stack() nounwind { ; RV64I-WITHFP-NEXT: li a3, 0 ; RV64I-WITHFP-NEXT: li a5, 0 ; RV64I-WITHFP-NEXT: li a7, 0 -; RV64I-WITHFP-NEXT: call callee_float_on_stack@plt +; RV64I-WITHFP-NEXT: call callee_float_on_stack ; RV64I-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-WITHFP-NEXT: addi sp, sp, 32 @@ -176,7 +176,7 @@ define i64 @caller_tiny_scalar_ret() nounwind { ; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM-NEXT: addi sp, sp, -16 ; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret@plt +; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret ; RV64I-FPELIM-NEXT: sext.w a0, a0 ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-FPELIM-NEXT: addi sp, sp, 16 @@ -188,7 +188,7 @@ define i64 @caller_tiny_scalar_ret() nounwind { ; RV64I-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-WITHFP-NEXT: addi s0, sp, 16 -; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret@plt +; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret ; RV64I-WITHFP-NEXT: sext.w a0, a0 ; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll index a74f7bbe2331..37d9eb6990b0 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll @@ -43,7 +43,7 @@ define float @caller_onstack_f32_noop(float %a) nounwind { ; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a5, 0 ; RV32IF-NEXT: li a7, 0 -; RV32IF-NEXT: call onstack_f32_noop@plt +; RV32IF-NEXT: call onstack_f32_noop ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -70,7 +70,7 @@ define float @caller_onstack_f32_fadd(float %a, float %b) nounwind { ; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a5, 0 ; RV32IF-NEXT: li a7, 0 -; RV32IF-NEXT: call onstack_f32_noop@plt +; RV32IF-NEXT: call onstack_f32_noop ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll b/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll index ac060f9469ac..5bae6b1d7f54 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll @@ -16,7 +16,7 @@ define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call receive_uint8@plt +; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -31,7 +31,7 @@ define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_uint8@plt +; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -57,7 +57,7 @@ define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: call receive_sint8@plt +; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -71,7 +71,7 @@ define signext i8 @ret_callresult_uint8_as_sint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_uint8@plt +; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -96,7 +96,7 @@ define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call receive_anyint32@plt +; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -110,7 +110,7 @@ define signext i32 @ret_callresult_uint8_as_anyint32() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_uint8@plt +; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -133,7 +133,7 @@ define void @pass_sint8_as_uint8(i8 signext %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: andi a0, a0, 255 -; RV32I-NEXT: call receive_uint8@plt +; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -148,7 +148,7 @@ define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_sint8@plt +; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -169,7 +169,7 @@ define void @pass_sint8_as_sint8(i8 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call receive_sint8@plt +; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -182,7 +182,7 @@ define signext i8 @ret_callresult_sint8_as_sint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_sint8@plt +; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -203,7 +203,7 @@ define void @pass_sint8_as_anyint32(i8 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call receive_anyint32@plt +; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -217,7 +217,7 @@ define signext i32 @ret_callresult_sint8_as_anyint32() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_sint8@plt +; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -241,7 +241,7 @@ define void @pass_anyint32_as_uint8(i32 signext %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: andi a0, a0, 255 -; RV32I-NEXT: call receive_uint8@plt +; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -257,7 +257,7 @@ define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_anyint32@plt +; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -284,7 +284,7 @@ define void @pass_anyint32_as_sint8(i32 signext %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: call receive_sint8@plt +; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -298,7 +298,7 @@ define signext i8 @ret_callresult_anyint32_as_sint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_anyint32@plt +; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -321,7 +321,7 @@ define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call receive_anyint32@plt +; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -334,7 +334,7 @@ define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call return_anyint32@plt +; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll b/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll index 3e2af1136529..70cdb6cec244 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll @@ -31,7 +31,7 @@ define void @bar() nounwind { ; CHECK-NEXT: li a6, 0 ; CHECK-NEXT: li a7, 0 ; CHECK-NEXT: vmv.v.i v16, 0 -; CHECK-NEXT: call foo@plt +; CHECK-NEXT: call foo ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, s0, -96 ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll index e3459875362d..365f255dd824 100644 --- a/llvm/test/CodeGen/RISCV/calls.ll +++ b/llvm/test/CodeGen/RISCV/calls.ll @@ -11,7 +11,7 @@ define i32 @test_call_external(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call external_function@plt +; RV32I-NEXT: call external_function ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -20,7 +20,7 @@ define i32 @test_call_external(i32 %a) nounwind { ; RV32I-PIC: # %bb.0: ; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-PIC-NEXT: call external_function@plt +; RV32I-PIC-NEXT: call external_function ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: ret @@ -71,7 +71,7 @@ define i32 @test_call_defined(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call defined_function@plt +; RV32I-NEXT: call defined_function ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -80,7 +80,7 @@ define i32 @test_call_defined(i32 %a) nounwind { ; RV32I-PIC: # %bb.0: ; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-PIC-NEXT: call defined_function@plt +; RV32I-PIC-NEXT: call defined_function ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: ret @@ -178,7 +178,7 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: call fastcc_function@plt +; RV32I-NEXT: call fastcc_function ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -191,7 +191,7 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind { ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-PIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-PIC-NEXT: mv s0, a0 -; RV32I-PIC-NEXT: call fastcc_function@plt +; RV32I-PIC-NEXT: call fastcc_function ; RV32I-PIC-NEXT: mv a0, s0 ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-PIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -219,7 +219,7 @@ define i32 @test_call_external_many_args(i32 %a) nounwind { ; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a7, a0 -; RV32I-NEXT: call external_many_args@plt +; RV32I-NEXT: call external_many_args ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -241,7 +241,7 @@ define i32 @test_call_external_many_args(i32 %a) nounwind { ; RV32I-PIC-NEXT: mv a5, a0 ; RV32I-PIC-NEXT: mv a6, a0 ; RV32I-PIC-NEXT: mv a7, a0 -; RV32I-PIC-NEXT: call external_many_args@plt +; RV32I-PIC-NEXT: call external_many_args ; RV32I-PIC-NEXT: mv a0, s0 ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-PIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -282,7 +282,7 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind { ; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a7, a0 -; RV32I-NEXT: call defined_many_args@plt +; RV32I-NEXT: call defined_many_args ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -300,7 +300,7 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind { ; RV32I-PIC-NEXT: mv a5, a0 ; RV32I-PIC-NEXT: mv a6, a0 ; RV32I-PIC-NEXT: mv a7, a0 -; RV32I-PIC-NEXT: call defined_many_args@plt +; RV32I-PIC-NEXT: call defined_many_args ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll index 7992c2cda28d..2103c3e60b59 100644 --- a/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll +++ b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll @@ -21,11 +21,11 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; CHECK32I-NEXT: mv s0, a1 ; CHECK32I-NEXT: mv s1, a0 -; CHECK32I-NEXT: call func@plt +; CHECK32I-NEXT: call func ; CHECK32I-NEXT: mv s2, a0 ; CHECK32I-NEXT: mv a0, s1 ; CHECK32I-NEXT: mv a1, s0 -; CHECK32I-NEXT: call func@plt +; CHECK32I-NEXT: call func ; CHECK32I-NEXT: add a0, s2, s0 ; CHECK32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -38,10 +38,10 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK32ZCMP: # %bb.0: ; CHECK32ZCMP-NEXT: cm.push {ra, s0-s2}, -16 ; CHECK32ZCMP-NEXT: cm.mvsa01 s1, s0 -; CHECK32ZCMP-NEXT: call func@plt +; CHECK32ZCMP-NEXT: call func ; CHECK32ZCMP-NEXT: mv s2, a0 ; CHECK32ZCMP-NEXT: cm.mva01s s1, s0 -; CHECK32ZCMP-NEXT: call func@plt +; CHECK32ZCMP-NEXT: call func ; CHECK32ZCMP-NEXT: add a0, s2, s0 ; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s2}, 16 ; @@ -54,11 +54,11 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK64I-NEXT: mv s0, a1 ; CHECK64I-NEXT: mv s1, a0 -; CHECK64I-NEXT: call func@plt +; CHECK64I-NEXT: call func ; CHECK64I-NEXT: mv s2, a0 ; CHECK64I-NEXT: mv a0, s1 ; CHECK64I-NEXT: mv a1, s0 -; CHECK64I-NEXT: call func@plt +; CHECK64I-NEXT: call func ; CHECK64I-NEXT: addw a0, s2, s0 ; CHECK64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -71,10 +71,10 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK64ZCMP: # %bb.0: ; CHECK64ZCMP-NEXT: cm.push {ra, s0-s2}, -32 ; CHECK64ZCMP-NEXT: cm.mvsa01 s1, s0 -; CHECK64ZCMP-NEXT: call func@plt +; CHECK64ZCMP-NEXT: call func ; CHECK64ZCMP-NEXT: mv s2, a0 ; CHECK64ZCMP-NEXT: cm.mva01s s1, s0 -; CHECK64ZCMP-NEXT: call func@plt +; CHECK64ZCMP-NEXT: call func ; CHECK64ZCMP-NEXT: addw a0, s2, s0 ; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s2}, 32 %call = call i32 @func(i32 %num, i32 %f) @@ -91,15 +91,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; CHECK32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; CHECK32I-NEXT: mv s0, a1 -; CHECK32I-NEXT: call foo@plt +; CHECK32I-NEXT: call foo ; CHECK32I-NEXT: mv s1, a0 ; CHECK32I-NEXT: mv a0, s0 -; CHECK32I-NEXT: call foo@plt +; CHECK32I-NEXT: call foo ; CHECK32I-NEXT: mv a0, s1 -; CHECK32I-NEXT: call foo@plt +; CHECK32I-NEXT: call foo ; CHECK32I-NEXT: li a0, 1 ; CHECK32I-NEXT: mv a1, s0 -; CHECK32I-NEXT: call func@plt +; CHECK32I-NEXT: call func ; CHECK32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; CHECK32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -110,15 +110,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK32ZCMP: # %bb.0: ; CHECK32ZCMP-NEXT: cm.push {ra, s0-s1}, -16 ; CHECK32ZCMP-NEXT: mv s0, a1 -; CHECK32ZCMP-NEXT: call foo@plt +; CHECK32ZCMP-NEXT: call foo ; CHECK32ZCMP-NEXT: mv s1, a0 ; CHECK32ZCMP-NEXT: mv a0, s0 -; CHECK32ZCMP-NEXT: call foo@plt +; CHECK32ZCMP-NEXT: call foo ; CHECK32ZCMP-NEXT: mv a0, s1 -; CHECK32ZCMP-NEXT: call foo@plt +; CHECK32ZCMP-NEXT: call foo ; CHECK32ZCMP-NEXT: li a0, 1 ; CHECK32ZCMP-NEXT: mv a1, s0 -; CHECK32ZCMP-NEXT: call func@plt +; CHECK32ZCMP-NEXT: call func ; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s1}, 16 ; ; CHECK64I-LABEL: not_zcmp_mv: @@ -128,15 +128,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK64I-NEXT: mv s0, a1 -; CHECK64I-NEXT: call foo@plt +; CHECK64I-NEXT: call foo ; CHECK64I-NEXT: mv s1, a0 ; CHECK64I-NEXT: mv a0, s0 -; CHECK64I-NEXT: call foo@plt +; CHECK64I-NEXT: call foo ; CHECK64I-NEXT: mv a0, s1 -; CHECK64I-NEXT: call foo@plt +; CHECK64I-NEXT: call foo ; CHECK64I-NEXT: li a0, 1 ; CHECK64I-NEXT: mv a1, s0 -; CHECK64I-NEXT: call func@plt +; CHECK64I-NEXT: call func ; CHECK64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -147,15 +147,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind { ; CHECK64ZCMP: # %bb.0: ; CHECK64ZCMP-NEXT: cm.push {ra, s0-s1}, -32 ; CHECK64ZCMP-NEXT: mv s0, a1 -; CHECK64ZCMP-NEXT: call foo@plt +; CHECK64ZCMP-NEXT: call foo ; CHECK64ZCMP-NEXT: mv s1, a0 ; CHECK64ZCMP-NEXT: mv a0, s0 -; CHECK64ZCMP-NEXT: call foo@plt +; CHECK64ZCMP-NEXT: call foo ; CHECK64ZCMP-NEXT: mv a0, s1 -; CHECK64ZCMP-NEXT: call foo@plt +; CHECK64ZCMP-NEXT: call foo ; CHECK64ZCMP-NEXT: li a0, 1 ; CHECK64ZCMP-NEXT: mv a1, s0 -; CHECK64ZCMP-NEXT: call func@plt +; CHECK64ZCMP-NEXT: call func ; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s1}, 32 %call = call i32 @foo(i32 %num) %call1 = call i32 @foo(i32 %f) diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index bce6707781c0..23f219c2487e 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -3092,7 +3092,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou ; RV32I-NEXT: .LBB56_1: # %bb2 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call bar@plt +; RV32I-NEXT: call bar ; RV32I-NEXT: sll s1, s1, s0 ; RV32I-NEXT: bnez a0, .LBB56_1 ; RV32I-NEXT: # %bb.2: # %bb7 @@ -3115,7 +3115,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou ; RV64I-NEXT: .LBB56_1: # %bb2 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call bar@plt +; RV64I-NEXT: call bar ; RV64I-NEXT: sllw s1, s1, s0 ; RV64I-NEXT: bnez a0, .LBB56_1 ; RV64I-NEXT: # %bb.2: # %bb7 @@ -3137,7 +3137,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou ; RV64XVENTANACONDOPS-NEXT: .LBB56_1: # %bb2 ; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64XVENTANACONDOPS-NEXT: mv a0, s1 -; RV64XVENTANACONDOPS-NEXT: call bar@plt +; RV64XVENTANACONDOPS-NEXT: call bar ; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s0 ; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB56_1 ; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb7 @@ -3160,7 +3160,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou ; RV64XTHEADCONDMOV-NEXT: .LBB56_1: # %bb2 ; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64XTHEADCONDMOV-NEXT: sext.w a0, s1 -; RV64XTHEADCONDMOV-NEXT: call bar@plt +; RV64XTHEADCONDMOV-NEXT: call bar ; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s0 ; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB56_1 ; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb7 @@ -3182,7 +3182,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou ; RV32ZICOND-NEXT: .LBB56_1: # %bb2 ; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32ZICOND-NEXT: mv a0, s1 -; RV32ZICOND-NEXT: call bar@plt +; RV32ZICOND-NEXT: call bar ; RV32ZICOND-NEXT: sll s1, s1, s0 ; RV32ZICOND-NEXT: bnez a0, .LBB56_1 ; RV32ZICOND-NEXT: # %bb.2: # %bb7 @@ -3204,7 +3204,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou ; RV64ZICOND-NEXT: .LBB56_1: # %bb2 ; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64ZICOND-NEXT: mv a0, s1 -; RV64ZICOND-NEXT: call bar@plt +; RV64ZICOND-NEXT: call bar ; RV64ZICOND-NEXT: sllw s1, s1, s0 ; RV64ZICOND-NEXT: bnez a0, .LBB56_1 ; RV64ZICOND-NEXT: # %bb.2: # %bb7 @@ -3243,7 +3243,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no ; RV32I-NEXT: .LBB57_1: # %bb2 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call bar@plt +; RV32I-NEXT: call bar ; RV32I-NEXT: sll s1, s1, s0 ; RV32I-NEXT: bnez a0, .LBB57_1 ; RV32I-NEXT: # %bb.2: # %bb7 @@ -3266,7 +3266,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no ; RV64I-NEXT: .LBB57_1: # %bb2 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call bar@plt +; RV64I-NEXT: call bar ; RV64I-NEXT: sllw s1, s1, s0 ; RV64I-NEXT: bnez a0, .LBB57_1 ; RV64I-NEXT: # %bb.2: # %bb7 @@ -3288,7 +3288,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no ; RV64XVENTANACONDOPS-NEXT: .LBB57_1: # %bb2 ; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64XVENTANACONDOPS-NEXT: mv a0, s1 -; RV64XVENTANACONDOPS-NEXT: call bar@plt +; RV64XVENTANACONDOPS-NEXT: call bar ; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s0 ; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB57_1 ; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb7 @@ -3311,7 +3311,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no ; RV64XTHEADCONDMOV-NEXT: .LBB57_1: # %bb2 ; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64XTHEADCONDMOV-NEXT: sext.w a0, s1 -; RV64XTHEADCONDMOV-NEXT: call bar@plt +; RV64XTHEADCONDMOV-NEXT: call bar ; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s0 ; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB57_1 ; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb7 @@ -3333,7 +3333,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no ; RV32ZICOND-NEXT: .LBB57_1: # %bb2 ; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32ZICOND-NEXT: mv a0, s1 -; RV32ZICOND-NEXT: call bar@plt +; RV32ZICOND-NEXT: call bar ; RV32ZICOND-NEXT: sll s1, s1, s0 ; RV32ZICOND-NEXT: bnez a0, .LBB57_1 ; RV32ZICOND-NEXT: # %bb.2: # %bb7 @@ -3355,7 +3355,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no ; RV64ZICOND-NEXT: .LBB57_1: # %bb2 ; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64ZICOND-NEXT: mv a0, s1 -; RV64ZICOND-NEXT: call bar@plt +; RV64ZICOND-NEXT: call bar ; RV64ZICOND-NEXT: sllw s1, s1, s0 ; RV64ZICOND-NEXT: bnez a0, .LBB57_1 ; RV64ZICOND-NEXT: # %bb.2: # %bb7 @@ -3505,7 +3505,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV32I-NEXT: beqz a1, .LBB60_4 ; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call bat@plt +; RV32I-NEXT: call bat ; RV32I-NEXT: .LBB60_4: ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3526,7 +3526,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV64I-NEXT: beqz a1, .LBB60_4 ; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call bat@plt +; RV64I-NEXT: call bat ; RV64I-NEXT: .LBB60_4: ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -3545,7 +3545,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV64XVENTANACONDOPS-NEXT: beqz a1, .LBB60_2 ; RV64XVENTANACONDOPS-NEXT: # %bb.1: ; RV64XVENTANACONDOPS-NEXT: mv a0, s0 -; RV64XVENTANACONDOPS-NEXT: call bat@plt +; RV64XVENTANACONDOPS-NEXT: call bat ; RV64XVENTANACONDOPS-NEXT: .LBB60_2: ; RV64XVENTANACONDOPS-NEXT: mv a0, s0 ; RV64XVENTANACONDOPS-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -3563,7 +3563,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV64XTHEADCONDMOV-NEXT: beqz a1, .LBB60_2 ; RV64XTHEADCONDMOV-NEXT: # %bb.1: ; RV64XTHEADCONDMOV-NEXT: mv a0, s0 -; RV64XTHEADCONDMOV-NEXT: call bat@plt +; RV64XTHEADCONDMOV-NEXT: call bat ; RV64XTHEADCONDMOV-NEXT: .LBB60_2: ; RV64XTHEADCONDMOV-NEXT: mv a0, s0 ; RV64XTHEADCONDMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -3582,7 +3582,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV32ZICOND-NEXT: beqz a1, .LBB60_2 ; RV32ZICOND-NEXT: # %bb.1: ; RV32ZICOND-NEXT: mv a0, s0 -; RV32ZICOND-NEXT: call bat@plt +; RV32ZICOND-NEXT: call bat ; RV32ZICOND-NEXT: .LBB60_2: ; RV32ZICOND-NEXT: mv a0, s0 ; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3601,7 +3601,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV64ZICOND-NEXT: beqz a1, .LBB60_2 ; RV64ZICOND-NEXT: # %bb.1: ; RV64ZICOND-NEXT: mv a0, s0 -; RV64ZICOND-NEXT: call bat@plt +; RV64ZICOND-NEXT: call bat ; RV64ZICOND-NEXT: .LBB60_2: ; RV64ZICOND-NEXT: mv a0, s0 ; RV64ZICOND-NEXT: ld ra, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/copysign-casts.ll b/llvm/test/CodeGen/RISCV/copysign-casts.ll index 931db00d06f8..accd52369fa1 100644 --- a/llvm/test/CodeGen/RISCV/copysign-casts.ll +++ b/llvm/test/CodeGen/RISCV/copysign-casts.ll @@ -164,7 +164,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind { ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.s fa0, fa1 -; RV32IFD-NEXT: call __extendhfsf2@plt +; RV32IFD-NEXT: call __extendhfsf2 ; RV32IFD-NEXT: fcvt.d.s fa5, fa0 ; RV32IFD-NEXT: fsgnj.d fa0, fs0, fa5 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -179,7 +179,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind { ; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: fmv.s fa0, fa1 -; RV64IFD-NEXT: call __extendhfsf2@plt +; RV64IFD-NEXT: call __extendhfsf2 ; RV64IFD-NEXT: fcvt.d.s fa5, fa0 ; RV64IFD-NEXT: fsgnj.d fa0, fs0, fa5 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -265,7 +265,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind { ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: call __extendhfsf2@plt +; RV32IF-NEXT: call __extendhfsf2 ; RV32IF-NEXT: fsgnj.s fa0, fs0, fa0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload @@ -279,7 +279,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind { ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.s fs0, fa0 ; RV32IFD-NEXT: fmv.s fa0, fa1 -; RV32IFD-NEXT: call __extendhfsf2@plt +; RV32IFD-NEXT: call __extendhfsf2 ; RV32IFD-NEXT: fsgnj.s fa0, fs0, fa0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -293,7 +293,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind { ; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.s fs0, fa0 ; RV64IFD-NEXT: fmv.s fa0, fa1 -; RV64IFD-NEXT: call __extendhfsf2@plt +; RV64IFD-NEXT: call __extendhfsf2 ; RV64IFD-NEXT: fsgnj.s fa0, fs0, fa0 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll index da67176e3f0c..455e6e54c9b3 100644 --- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll @@ -244,7 +244,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI2_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0) @@ -268,7 +268,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI2_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI2_0) @@ -381,14 +381,14 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi s3, a1, 1329 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, %hi(.LCPI3_0) ; RV32I-NEXT: addi s4, a0, %lo(.LCPI3_0) ; RV32I-NEXT: neg a0, s2 ; RV32I-NEXT: and a0, s2, a0 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s2, .LBB3_3 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: li a0, 32 @@ -426,7 +426,7 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, %hi(.LCPI3_0) ; RV64I-NEXT: ld a1, %lo(.LCPI3_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI3_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI3_1) @@ -706,7 +706,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI6_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI6_0) @@ -724,7 +724,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI6_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0) @@ -812,14 +812,14 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi s3, a1, 1329 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a0, %hi(.LCPI7_0) ; RV32I-NEXT: addi s4, a0, %lo(.LCPI7_0) ; RV32I-NEXT: neg a0, s1 ; RV32I-NEXT: and a0, s1, a0 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s2, .LBB7_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 27 @@ -850,7 +850,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, %hi(.LCPI7_0) ; RV64I-NEXT: ld a1, %lo(.LCPI7_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI7_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_1) @@ -1191,7 +1191,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1236,7 +1236,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1395,7 +1395,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s3, a1, 257 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: or a0, s2, a0 @@ -1419,7 +1419,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s0, .LBB11_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 @@ -1485,7 +1485,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1862,7 +1862,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1901,7 +1901,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2046,7 +2046,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s3, a1, 257 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: or a0, s2, a0 @@ -2070,7 +2070,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s0, .LBB15_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 @@ -2134,7 +2134,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2484,7 +2484,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -2512,7 +2512,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2598,7 +2598,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { ; RV32XTHEADBB-NEXT: and a0, a0, a1 ; RV32XTHEADBB-NEXT: lui a1, 4112 ; RV32XTHEADBB-NEXT: addi a1, a1, 257 -; RV32XTHEADBB-NEXT: call __mulsi3@plt +; RV32XTHEADBB-NEXT: call __mulsi3 ; RV32XTHEADBB-NEXT: srli a0, a0, 24 ; RV32XTHEADBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32XTHEADBB-NEXT: addi sp, sp, 16 @@ -2626,7 +2626,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { ; RV64XTHEADBB-NEXT: and a0, a0, a1 ; RV64XTHEADBB-NEXT: lui a1, 4112 ; RV64XTHEADBB-NEXT: addiw a1, a1, 257 -; RV64XTHEADBB-NEXT: call __muldi3@plt +; RV64XTHEADBB-NEXT: call __muldi3 ; RV64XTHEADBB-NEXT: srliw a0, a0, 24 ; RV64XTHEADBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64XTHEADBB-NEXT: addi sp, sp, 16 @@ -2666,7 +2666,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli s5, a0, 24 ; RV32I-NEXT: srli a0, s0, 1 ; RV32I-NEXT: and a0, a0, s2 @@ -2679,7 +2679,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: add a0, a0, s5 ; RV32I-NEXT: li a1, 0 @@ -2723,7 +2723,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -2842,7 +2842,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind { ; RV32XTHEADBB-NEXT: lui a1, 4112 ; RV32XTHEADBB-NEXT: addi s1, a1, 257 ; RV32XTHEADBB-NEXT: mv a1, s1 -; RV32XTHEADBB-NEXT: call __mulsi3@plt +; RV32XTHEADBB-NEXT: call __mulsi3 ; RV32XTHEADBB-NEXT: srli s5, a0, 24 ; RV32XTHEADBB-NEXT: srli a0, s0, 1 ; RV32XTHEADBB-NEXT: and a0, a0, s2 @@ -2855,7 +2855,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind { ; RV32XTHEADBB-NEXT: add a0, a0, a1 ; RV32XTHEADBB-NEXT: and a0, a0, s4 ; RV32XTHEADBB-NEXT: mv a1, s1 -; RV32XTHEADBB-NEXT: call __mulsi3@plt +; RV32XTHEADBB-NEXT: call __mulsi3 ; RV32XTHEADBB-NEXT: srli a0, a0, 24 ; RV32XTHEADBB-NEXT: add a0, a0, s5 ; RV32XTHEADBB-NEXT: li a1, 0 @@ -2899,7 +2899,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind { ; RV64XTHEADBB-NEXT: addiw a1, a1, 257 ; RV64XTHEADBB-NEXT: slli a2, a1, 32 ; RV64XTHEADBB-NEXT: add a1, a1, a2 -; RV64XTHEADBB-NEXT: call __muldi3@plt +; RV64XTHEADBB-NEXT: call __muldi3 ; RV64XTHEADBB-NEXT: srli a0, a0, 56 ; RV64XTHEADBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64XTHEADBB-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll index 9bfd30daf7d4..a60fd26f4959 100644 --- a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll +++ b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll @@ -46,14 +46,14 @@ define signext i32 @ctz_dereferencing_pointer(i64* %b) nounwind { ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi s1, a1, 1329 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a0, %hi(.LCPI0_0) ; RV32I-NEXT: addi s3, a0, %lo(.LCPI0_0) ; RV32I-NEXT: neg a0, s4 ; RV32I-NEXT: and a0, s4, a0 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s4, .LBB0_3 ; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: li a0, 32 @@ -91,7 +91,7 @@ define signext i32 @ctz_dereferencing_pointer(i64* %b) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, %hi(.LCPI0_0) ; RV64I-NEXT: ld a1, %lo(.LCPI0_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI0_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI0_1) @@ -144,7 +144,7 @@ define i64 @ctz_dereferencing_pointer_zext(i32* %b) nounwind { ; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI1_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI1_0) @@ -170,7 +170,7 @@ define i64 @ctz_dereferencing_pointer_zext(i32* %b) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI1_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI1_0) @@ -220,7 +220,7 @@ define signext i32 @ctz1(i32 signext %x) nounwind { ; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI2_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0) @@ -245,7 +245,7 @@ define signext i32 @ctz1(i32 signext %x) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI2_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI2_0) @@ -293,7 +293,7 @@ define signext i32 @ctz1_flipped(i32 signext %x) nounwind { ; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI3_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI3_0) @@ -318,7 +318,7 @@ define signext i32 @ctz1_flipped(i32 signext %x) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI3_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI3_0) @@ -364,7 +364,7 @@ define signext i32 @ctz2(i32 signext %x) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI4_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI4_0) @@ -387,7 +387,7 @@ define signext i32 @ctz2(i32 signext %x) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI4_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI4_0) @@ -429,7 +429,7 @@ define signext i32 @ctz3(i32 signext %x) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI5_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI5_0) @@ -452,7 +452,7 @@ define signext i32 @ctz3(i32 signext %x) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI5_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI5_0) @@ -509,14 +509,14 @@ define signext i32 @ctz4(i64 %b) nounwind { ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi s3, a1, 1329 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, %hi(.LCPI6_0) ; RV32I-NEXT: addi s4, a0, %lo(.LCPI6_0) ; RV32I-NEXT: neg a0, s2 ; RV32I-NEXT: and a0, s2, a0 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s2, .LBB6_3 ; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: li a0, 32 @@ -554,7 +554,7 @@ define signext i32 @ctz4(i64 %b) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, %hi(.LCPI6_0) ; RV64I-NEXT: ld a1, %lo(.LCPI6_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI6_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_1) @@ -643,7 +643,7 @@ define signext i32 @ctlz(i64 %b) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s3, a1, 257 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: or a0, s2, a0 @@ -667,7 +667,7 @@ define signext i32 @ctlz(i64 %b) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s0, .LBB7_2 ; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: srli a0, a0, 24 @@ -731,7 +731,7 @@ define signext i32 @ctlz(i64 %b) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -772,7 +772,7 @@ define signext i32 @ctz5(i32 signext %x) nounwind { ; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI8_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI8_0) @@ -797,7 +797,7 @@ define signext i32 @ctz5(i32 signext %x) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI8_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0) @@ -845,7 +845,7 @@ define signext i32 @ctz6(i32 signext %x) nounwind { ; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI9_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI9_0) @@ -870,7 +870,7 @@ define signext i32 @ctz6(i32 signext %x) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI9_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0) @@ -923,7 +923,7 @@ define signext i32 @globalVar() nounwind { ; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI10_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI10_0) @@ -949,7 +949,7 @@ define signext i32 @globalVar() nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI10_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_0) diff --git a/llvm/test/CodeGen/RISCV/div-by-constant.ll b/llvm/test/CodeGen/RISCV/div-by-constant.ll index bf19bbd8b131..91ac7c5ddae3 100644 --- a/llvm/test/CodeGen/RISCV/div-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/div-by-constant.ll @@ -121,7 +121,7 @@ define i64 @udiv64_constant_add(i64 %a) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 7 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __udivdi3@plt +; RV32-NEXT: call __udivdi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -383,7 +383,7 @@ define i64 @sdiv64_constant_no_srai(i64 %a) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 3 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __divdi3@plt +; RV32-NEXT: call __divdi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -407,7 +407,7 @@ define i64 @sdiv64_constant_srai(i64 %a) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 5 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __divdi3@plt +; RV32-NEXT: call __divdi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -432,7 +432,7 @@ define i64 @sdiv64_constant_add_srai(i64 %a) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 15 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __divdi3@plt +; RV32-NEXT: call __divdi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -460,7 +460,7 @@ define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, -3 ; RV32-NEXT: li a3, -1 -; RV32-NEXT: call __divdi3@plt +; RV32-NEXT: call __divdi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll index c455b439f0b1..99c83b99497d 100644 --- a/llvm/test/CodeGen/RISCV/div.ll +++ b/llvm/test/CodeGen/RISCV/div.ll @@ -11,7 +11,7 @@ define i32 @udiv(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: udiv: ; RV32I: # %bb.0: -; RV32I-NEXT: tail __udivsi3@plt +; RV32I-NEXT: tail __udivsi3 ; ; RV32IM-LABEL: udiv: ; RV32IM: # %bb.0: @@ -26,7 +26,7 @@ define i32 @udiv(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -43,7 +43,7 @@ define i32 @udiv_constant(i32 %a) nounwind { ; RV32I-LABEL: udiv_constant: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: tail __udivsi3@plt +; RV32I-NEXT: tail __udivsi3 ; ; RV32IM-LABEL: udiv_constant: ; RV32IM: # %bb.0: @@ -60,7 +60,7 @@ define i32 @udiv_constant(i32 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -107,7 +107,7 @@ define i32 @udiv_constant_lhs(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: li a0, 10 -; RV32I-NEXT: tail __udivsi3@plt +; RV32I-NEXT: tail __udivsi3 ; ; RV32IM-LABEL: udiv_constant_lhs: ; RV32IM: # %bb.0: @@ -122,7 +122,7 @@ define i32 @udiv_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a1, a0, 32 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -141,7 +141,7 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __udivdi3@plt +; RV32I-NEXT: call __udivdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -150,14 +150,14 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IM-NEXT: call __udivdi3@plt +; RV32IM-NEXT: call __udivdi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret ; ; RV64I-LABEL: udiv64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __udivdi3@plt +; RV64I-NEXT: tail __udivdi3 ; ; RV64IM-LABEL: udiv64: ; RV64IM: # %bb.0: @@ -174,7 +174,7 @@ define i64 @udiv64_constant(i64 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __udivdi3@plt +; RV32I-NEXT: call __udivdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -206,7 +206,7 @@ define i64 @udiv64_constant(i64 %a) nounwind { ; RV64I-LABEL: udiv64_constant: ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: tail __udivdi3@plt +; RV64I-NEXT: tail __udivdi3 ; ; RV64IM-LABEL: udiv64_constant: ; RV64IM: # %bb.0: @@ -230,7 +230,7 @@ define i64 @udiv64_constant_lhs(i64 %a) nounwind { ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: li a0, 10 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __udivdi3@plt +; RV32I-NEXT: call __udivdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -243,7 +243,7 @@ define i64 @udiv64_constant_lhs(i64 %a) nounwind { ; RV32IM-NEXT: mv a2, a0 ; RV32IM-NEXT: li a0, 10 ; RV32IM-NEXT: li a1, 0 -; RV32IM-NEXT: call __udivdi3@plt +; RV32IM-NEXT: call __udivdi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -252,7 +252,7 @@ define i64 @udiv64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: tail __udivdi3@plt +; RV64I-NEXT: tail __udivdi3 ; ; RV64IM-LABEL: udiv64_constant_lhs: ; RV64IM: # %bb.0: @@ -270,7 +270,7 @@ define i8 @udiv8(i8 %a, i8 %b) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a1, a1, 255 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -288,7 +288,7 @@ define i8 @udiv8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: andi a1, a1, 255 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -310,7 +310,7 @@ define i8 @udiv8_constant(i8 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -329,7 +329,7 @@ define i8 @udiv8_constant(i8 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -380,7 +380,7 @@ define i8 @udiv8_constant_lhs(i8 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: li a0, 10 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -398,7 +398,7 @@ define i8 @udiv8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -422,7 +422,7 @@ define i16 @udiv16(i16 %a, i16 %b) nounwind { ; RV32I-NEXT: addi a2, a2, -1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -444,7 +444,7 @@ define i16 @udiv16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: addiw a2, a2, -1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -469,7 +469,7 @@ define i16 @udiv16_constant(i16 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -489,7 +489,7 @@ define i16 @udiv16_constant(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -542,7 +542,7 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: li a0, 10 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -562,7 +562,7 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -581,7 +581,7 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind { define i32 @sdiv(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: sdiv: ; RV32I: # %bb.0: -; RV32I-NEXT: tail __divsi3@plt +; RV32I-NEXT: tail __divsi3 ; ; RV32IM-LABEL: sdiv: ; RV32IM: # %bb.0: @@ -594,7 +594,7 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -611,7 +611,7 @@ define i32 @sdiv_constant(i32 %a) nounwind { ; RV32I-LABEL: sdiv_constant: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: tail __divsi3@plt +; RV32I-NEXT: tail __divsi3 ; ; RV32IM-LABEL: sdiv_constant: ; RV32IM: # %bb.0: @@ -629,7 +629,7 @@ define i32 @sdiv_constant(i32 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -725,7 +725,7 @@ define i32 @sdiv_constant_lhs(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: li a0, -10 -; RV32I-NEXT: tail __divsi3@plt +; RV32I-NEXT: tail __divsi3 ; ; RV32IM-LABEL: sdiv_constant_lhs: ; RV32IM: # %bb.0: @@ -739,7 +739,7 @@ define i32 @sdiv_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -758,7 +758,7 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __divdi3@plt +; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -767,14 +767,14 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IM-NEXT: call __divdi3@plt +; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret ; ; RV64I-LABEL: sdiv64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64: ; RV64IM: # %bb.0: @@ -791,7 +791,7 @@ define i64 @sdiv64_constant(i64 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 5 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __divdi3@plt +; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -802,7 +802,7 @@ define i64 @sdiv64_constant(i64 %a) nounwind { ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IM-NEXT: li a2, 5 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __divdi3@plt +; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -810,7 +810,7 @@ define i64 @sdiv64_constant(i64 %a) nounwind { ; RV64I-LABEL: sdiv64_constant: ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64_constant: ; RV64IM: # %bb.0: @@ -834,7 +834,7 @@ define i64 @sdiv64_constant_lhs(i64 %a) nounwind { ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: li a0, 10 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __divdi3@plt +; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -847,7 +847,7 @@ define i64 @sdiv64_constant_lhs(i64 %a) nounwind { ; RV32IM-NEXT: mv a2, a0 ; RV32IM-NEXT: li a0, 10 ; RV32IM-NEXT: li a1, 0 -; RV32IM-NEXT: call __divdi3@plt +; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -856,7 +856,7 @@ define i64 @sdiv64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64_constant_lhs: ; RV64IM: # %bb.0: @@ -878,7 +878,7 @@ define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a3, a2, 31 -; RV32I-NEXT: call __divdi3@plt +; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -890,7 +890,7 @@ define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind { ; RV32IM-NEXT: mv a2, a1 ; RV32IM-NEXT: srai a1, a0, 31 ; RV32IM-NEXT: srai a3, a2, 31 -; RV32IM-NEXT: call __divdi3@plt +; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -899,7 +899,7 @@ define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64_sext_operands: ; RV64IM: # %bb.0: @@ -922,7 +922,7 @@ define i8 @sdiv8(i8 %a, i8 %b) nounwind { ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: srai a1, a1, 24 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -944,7 +944,7 @@ define i8 @sdiv8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: srai a1, a1, 56 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -969,7 +969,7 @@ define i8 @sdiv8_constant(i8 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -993,7 +993,7 @@ define i8 @sdiv8_constant(i8 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1069,7 +1069,7 @@ define i8 @sdiv8_constant_lhs(i8 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a1, a0, 24 ; RV32I-NEXT: li a0, -10 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1089,7 +1089,7 @@ define i8 @sdiv8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a1, a0, 56 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1114,7 +1114,7 @@ define i16 @sdiv16(i16 %a, i16 %b) nounwind { ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: srai a1, a1, 16 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1136,7 +1136,7 @@ define i16 @sdiv16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: srai a1, a1, 48 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1161,7 +1161,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: li a1, 5 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1185,7 +1185,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1261,7 +1261,7 @@ define i16 @sdiv16_constant_lhs(i16 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a1, a0, 16 ; RV32I-NEXT: li a0, -10 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1281,7 +1281,7 @@ define i16 @sdiv16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a1, a0, 48 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-arith-strict.ll b/llvm/test/CodeGen/RISCV/double-arith-strict.ll index c324cc88f84b..186175537772 100644 --- a/llvm/test/CodeGen/RISCV/double-arith-strict.ll +++ b/llvm/test/CodeGen/RISCV/double-arith-strict.ll @@ -50,7 +50,7 @@ define double @fadd_d(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -59,7 +59,7 @@ define double @fadd_d(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -102,7 +102,7 @@ define double @fsub_d(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __subdf3@plt +; RV32I-NEXT: call __subdf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -111,7 +111,7 @@ define double @fsub_d(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __subdf3@plt +; RV64I-NEXT: call __subdf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -154,7 +154,7 @@ define double @fmul_d(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -163,7 +163,7 @@ define double @fmul_d(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -206,7 +206,7 @@ define double @fdiv_d(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __divdf3@plt +; RV32I-NEXT: call __divdf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -215,7 +215,7 @@ define double @fdiv_d(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __divdf3@plt +; RV64I-NEXT: call __divdf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -254,7 +254,7 @@ define double @fsqrt_d(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrt@plt +; RV32I-NEXT: call sqrt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -263,7 +263,7 @@ define double @fsqrt_d(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrt@plt +; RV64I-NEXT: call sqrt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -277,7 +277,7 @@ define double @fmin_d(double %a, double %b) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call fmin@plt +; RV32IFD-NEXT: call fmin ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -286,7 +286,7 @@ define double @fmin_d(double %a, double %b) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call fmin@plt +; RV64IFD-NEXT: call fmin ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -295,7 +295,7 @@ define double @fmin_d(double %a, double %b) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call fmin@plt +; RV32IZFINXZDINX-NEXT: call fmin ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -304,7 +304,7 @@ define double @fmin_d(double %a, double %b) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call fmin@plt +; RV64IZFINXZDINX-NEXT: call fmin ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -313,7 +313,7 @@ define double @fmin_d(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmin@plt +; RV32I-NEXT: call fmin ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -322,7 +322,7 @@ define double @fmin_d(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmin@plt +; RV64I-NEXT: call fmin ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -336,7 +336,7 @@ define double @fmax_d(double %a, double %b) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call fmax@plt +; RV32IFD-NEXT: call fmax ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -345,7 +345,7 @@ define double @fmax_d(double %a, double %b) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call fmax@plt +; RV64IFD-NEXT: call fmax ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -354,7 +354,7 @@ define double @fmax_d(double %a, double %b) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call fmax@plt +; RV32IZFINXZDINX-NEXT: call fmax ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -363,7 +363,7 @@ define double @fmax_d(double %a, double %b) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call fmax@plt +; RV64IZFINXZDINX-NEXT: call fmax ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -372,7 +372,7 @@ define double @fmax_d(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmax@plt +; RV32I-NEXT: call fmax ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -381,7 +381,7 @@ define double @fmax_d(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmax@plt +; RV64I-NEXT: call fmax ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -428,7 +428,7 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -437,7 +437,7 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -508,7 +508,7 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: lui a5, 524288 ; RV32I-NEXT: xor a5, a1, a5 @@ -516,7 +516,7 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -535,13 +535,13 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a2, a0, a1 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -619,14 +619,14 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: lui a5, 524288 ; RV32I-NEXT: xor a2, s5, a5 @@ -635,7 +635,7 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a3, s2 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -656,18 +656,18 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -750,14 +750,14 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: lui a5, 524288 ; RV32I-NEXT: xor a3, s5, a5 @@ -765,7 +765,7 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s4 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -787,17 +787,17 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -872,14 +872,14 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a4, s1 ; RV32I-NEXT: mv a5, s0 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -897,13 +897,13 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -977,7 +977,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: lui a3, 524288 ; RV32I-NEXT: xor a3, a1, a3 @@ -985,7 +985,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a4, s1 ; RV32I-NEXT: mv a5, s0 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1004,13 +1004,13 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a1, a0, a1 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll index 7e2964ef68b1..82ddf06187d3 100644 --- a/llvm/test/CodeGen/RISCV/double-arith.ll +++ b/llvm/test/CodeGen/RISCV/double-arith.ll @@ -51,7 +51,7 @@ define double @fadd_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -60,7 +60,7 @@ define double @fadd_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -102,7 +102,7 @@ define double @fsub_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __subdf3@plt +; RV32I-NEXT: call __subdf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -111,7 +111,7 @@ define double @fsub_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __subdf3@plt +; RV64I-NEXT: call __subdf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -153,7 +153,7 @@ define double @fmul_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -162,7 +162,7 @@ define double @fmul_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -204,7 +204,7 @@ define double @fdiv_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __divdf3@plt +; RV32I-NEXT: call __divdf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -213,7 +213,7 @@ define double @fdiv_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __divdf3@plt +; RV64I-NEXT: call __divdf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -253,7 +253,7 @@ define double @fsqrt_d(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrt@plt +; RV32I-NEXT: call sqrt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -262,7 +262,7 @@ define double @fsqrt_d(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrt@plt +; RV64I-NEXT: call sqrt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -359,11 +359,11 @@ define i32 @fneg_d(double %a, double %b) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a3, a1 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lui a3, 524288 ; RV32I-NEXT: xor a3, a1, a3 ; RV32I-NEXT: mv a2, a0 -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -374,11 +374,11 @@ define i32 @fneg_d(double %a, double %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a1, a0, a1 -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -494,12 +494,12 @@ define double @fabs_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: mv a2, a0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -508,11 +508,11 @@ define double @fabs_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -558,7 +558,7 @@ define double @fmin_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmin@plt +; RV32I-NEXT: call fmin ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -567,7 +567,7 @@ define double @fmin_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmin@plt +; RV64I-NEXT: call fmin ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -611,7 +611,7 @@ define double @fmax_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmax@plt +; RV32I-NEXT: call fmax ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -620,7 +620,7 @@ define double @fmax_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmax@plt +; RV64I-NEXT: call fmax ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -668,7 +668,7 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -677,7 +677,7 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -747,7 +747,7 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: lui a5, 524288 ; RV32I-NEXT: xor a5, a1, a5 @@ -755,7 +755,7 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -774,13 +774,13 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a2, a0, a1 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -858,14 +858,14 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: lui a5, 524288 ; RV32I-NEXT: xor a2, s5, a5 @@ -874,7 +874,7 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a3, s2 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -895,18 +895,18 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -989,14 +989,14 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: lui a5, 524288 ; RV32I-NEXT: xor a3, s5, a5 @@ -1004,7 +1004,7 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s4 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1026,17 +1026,17 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1095,7 +1095,7 @@ define double @fnmadd_d_3(double %a, double %b, double %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1106,7 +1106,7 @@ define double @fnmadd_d_3(double %a, double %b, double %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a0, a0, a1 @@ -1162,7 +1162,7 @@ define double @fnmadd_nsz(double %a, double %b, double %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1173,7 +1173,7 @@ define double @fnmadd_nsz(double %a, double %b, double %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a0, a0, a1 @@ -1245,14 +1245,14 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a4, s1 ; RV32I-NEXT: mv a5, s0 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1270,13 +1270,13 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1350,7 +1350,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: lui a3, 524288 ; RV32I-NEXT: xor a3, a1, a3 @@ -1358,7 +1358,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a4, s1 ; RV32I-NEXT: mv a5, s0 -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1377,13 +1377,13 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a1, a0, a1 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1437,10 +1437,10 @@ define double @fmadd_d_contract(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a5 ; RV32I-NEXT: mv s1, a4 -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1453,9 +1453,9 @@ define double @fmadd_d_contract(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1529,17 +1529,17 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: mv a2, s4 ; RV32I-NEXT: mv a3, s5 -; RV32I-NEXT: call __subdf3@plt +; RV32I-NEXT: call __subdf3 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1561,13 +1561,13 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: mv a1, s2 -; RV64I-NEXT: call __subdf3@plt +; RV64I-NEXT: call __subdf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1650,33 +1650,33 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s3 -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a3, s1 -; RV32I-NEXT: call __subdf3@plt +; RV32I-NEXT: call __subdf3 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1697,24 +1697,24 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __subdf3@plt +; RV64I-NEXT: call __subdf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1796,24 +1796,24 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s5 -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __subdf3@plt +; RV32I-NEXT: call __subdf3 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1834,17 +1834,17 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __subdf3@plt +; RV64I-NEXT: call __subdf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll index f2206d5397f0..2c5505edb1fa 100644 --- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll @@ -21,7 +21,7 @@ define void @br_fcmp_false(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB0_2: # %if.else ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_false: ; RV64IFD: # %bb.0: @@ -32,7 +32,7 @@ define void @br_fcmp_false(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB0_2: # %if.else ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_false: ; RV32IZFINXZDINX: # %bb.0: @@ -43,7 +43,7 @@ define void @br_fcmp_false(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: .LBB0_2: # %if.else ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_false: ; RV64IZFINXZDINX: # %bb.0: @@ -54,7 +54,7 @@ define void @br_fcmp_false(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB0_2: # %if.else ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp false double %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -74,7 +74,7 @@ define void @br_fcmp_oeq(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB1_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_oeq: ; RV64IFD: # %bb.0: @@ -85,7 +85,7 @@ define void @br_fcmp_oeq(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB1_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_oeq: ; RV32IZFINXZDINX: # %bb.0: @@ -106,7 +106,7 @@ define void @br_fcmp_oeq(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB1_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_oeq: ; RV64IZFINXZDINX: # %bb.0: @@ -117,7 +117,7 @@ define void @br_fcmp_oeq(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB1_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp oeq double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -140,7 +140,7 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB2_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_oeq_alt: ; RV64IFD: # %bb.0: @@ -151,7 +151,7 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB2_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_oeq_alt: ; RV32IZFINXZDINX: # %bb.0: @@ -172,7 +172,7 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB2_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_oeq_alt: ; RV64IZFINXZDINX: # %bb.0: @@ -183,7 +183,7 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB2_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp oeq double %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -203,7 +203,7 @@ define void @br_fcmp_ogt(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB3_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_ogt: ; RV64IFD: # %bb.0: @@ -214,7 +214,7 @@ define void @br_fcmp_ogt(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB3_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_ogt: ; RV32IZFINXZDINX: # %bb.0: @@ -235,7 +235,7 @@ define void @br_fcmp_ogt(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB3_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ogt: ; RV64IZFINXZDINX: # %bb.0: @@ -246,7 +246,7 @@ define void @br_fcmp_ogt(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB3_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp ogt double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -266,7 +266,7 @@ define void @br_fcmp_oge(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB4_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_oge: ; RV64IFD: # %bb.0: @@ -277,7 +277,7 @@ define void @br_fcmp_oge(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB4_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_oge: ; RV32IZFINXZDINX: # %bb.0: @@ -298,7 +298,7 @@ define void @br_fcmp_oge(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB4_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_oge: ; RV64IZFINXZDINX: # %bb.0: @@ -309,7 +309,7 @@ define void @br_fcmp_oge(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB4_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp oge double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -329,7 +329,7 @@ define void @br_fcmp_olt(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB5_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_olt: ; RV64IFD: # %bb.0: @@ -340,7 +340,7 @@ define void @br_fcmp_olt(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB5_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_olt: ; RV32IZFINXZDINX: # %bb.0: @@ -361,7 +361,7 @@ define void @br_fcmp_olt(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB5_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_olt: ; RV64IZFINXZDINX: # %bb.0: @@ -372,7 +372,7 @@ define void @br_fcmp_olt(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB5_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp olt double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -392,7 +392,7 @@ define void @br_fcmp_ole(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB6_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_ole: ; RV64IFD: # %bb.0: @@ -403,7 +403,7 @@ define void @br_fcmp_ole(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB6_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_ole: ; RV32IZFINXZDINX: # %bb.0: @@ -424,7 +424,7 @@ define void @br_fcmp_ole(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB6_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ole: ; RV64IZFINXZDINX: # %bb.0: @@ -435,7 +435,7 @@ define void @br_fcmp_ole(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB6_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp ole double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -457,7 +457,7 @@ define void @br_fcmp_one(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB7_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_one: ; RV64IFD: # %bb.0: @@ -470,7 +470,7 @@ define void @br_fcmp_one(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB7_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_one: ; RV32IZFINXZDINX: # %bb.0: @@ -493,7 +493,7 @@ define void @br_fcmp_one(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB7_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_one: ; RV64IZFINXZDINX: # %bb.0: @@ -506,7 +506,7 @@ define void @br_fcmp_one(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB7_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp one double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -528,7 +528,7 @@ define void @br_fcmp_ord(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB8_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_ord: ; RV64IFD: # %bb.0: @@ -541,7 +541,7 @@ define void @br_fcmp_ord(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB8_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_ord: ; RV32IZFINXZDINX: # %bb.0: @@ -564,7 +564,7 @@ define void @br_fcmp_ord(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB8_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ord: ; RV64IZFINXZDINX: # %bb.0: @@ -577,7 +577,7 @@ define void @br_fcmp_ord(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB8_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp ord double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -599,7 +599,7 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB9_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_ueq: ; RV64IFD: # %bb.0: @@ -612,7 +612,7 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB9_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_ueq: ; RV32IZFINXZDINX: # %bb.0: @@ -635,7 +635,7 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB9_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ueq: ; RV64IZFINXZDINX: # %bb.0: @@ -648,7 +648,7 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB9_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp ueq double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -668,7 +668,7 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB10_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_ugt: ; RV64IFD: # %bb.0: @@ -679,7 +679,7 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB10_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_ugt: ; RV32IZFINXZDINX: # %bb.0: @@ -700,7 +700,7 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB10_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ugt: ; RV64IZFINXZDINX: # %bb.0: @@ -711,7 +711,7 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB10_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp ugt double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -731,7 +731,7 @@ define void @br_fcmp_uge(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB11_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_uge: ; RV64IFD: # %bb.0: @@ -742,7 +742,7 @@ define void @br_fcmp_uge(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB11_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_uge: ; RV32IZFINXZDINX: # %bb.0: @@ -763,7 +763,7 @@ define void @br_fcmp_uge(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB11_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_uge: ; RV64IZFINXZDINX: # %bb.0: @@ -774,7 +774,7 @@ define void @br_fcmp_uge(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB11_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp uge double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -794,7 +794,7 @@ define void @br_fcmp_ult(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB12_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_ult: ; RV64IFD: # %bb.0: @@ -805,7 +805,7 @@ define void @br_fcmp_ult(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB12_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_ult: ; RV32IZFINXZDINX: # %bb.0: @@ -826,7 +826,7 @@ define void @br_fcmp_ult(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB12_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ult: ; RV64IZFINXZDINX: # %bb.0: @@ -837,7 +837,7 @@ define void @br_fcmp_ult(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB12_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp ult double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -857,7 +857,7 @@ define void @br_fcmp_ule(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB13_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_ule: ; RV64IFD: # %bb.0: @@ -868,7 +868,7 @@ define void @br_fcmp_ule(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB13_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_ule: ; RV32IZFINXZDINX: # %bb.0: @@ -889,7 +889,7 @@ define void @br_fcmp_ule(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB13_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ule: ; RV64IZFINXZDINX: # %bb.0: @@ -900,7 +900,7 @@ define void @br_fcmp_ule(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB13_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp ule double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -920,7 +920,7 @@ define void @br_fcmp_une(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB14_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_une: ; RV64IFD: # %bb.0: @@ -931,7 +931,7 @@ define void @br_fcmp_une(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB14_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_une: ; RV32IZFINXZDINX: # %bb.0: @@ -952,7 +952,7 @@ define void @br_fcmp_une(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB14_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_une: ; RV64IZFINXZDINX: # %bb.0: @@ -963,7 +963,7 @@ define void @br_fcmp_une(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB14_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp une double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -985,7 +985,7 @@ define void @br_fcmp_uno(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB15_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_uno: ; RV64IFD: # %bb.0: @@ -998,7 +998,7 @@ define void @br_fcmp_uno(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB15_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_uno: ; RV32IZFINXZDINX: # %bb.0: @@ -1021,7 +1021,7 @@ define void @br_fcmp_uno(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; RV32IZFINXZDINX-NEXT: .LBB15_2: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_uno: ; RV64IZFINXZDINX: # %bb.0: @@ -1034,7 +1034,7 @@ define void @br_fcmp_uno(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB15_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp uno double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1054,7 +1054,7 @@ define void @br_fcmp_true(double %a, double %b) nounwind { ; RV32IFD-NEXT: .LBB16_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_true: ; RV64IFD: # %bb.0: @@ -1065,7 +1065,7 @@ define void @br_fcmp_true(double %a, double %b) nounwind { ; RV64IFD-NEXT: .LBB16_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call abort@plt +; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_true: ; RV32IZFINXZDINX: # %bb.0: @@ -1076,7 +1076,7 @@ define void @br_fcmp_true(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: .LBB16_2: # %if.then ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_true: ; RV64IZFINXZDINX: # %bb.0: @@ -1087,7 +1087,7 @@ define void @br_fcmp_true(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: .LBB16_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call abort@plt +; RV64IZFINXZDINX-NEXT: call abort %1 = fcmp true double %a, %b br i1 %1, label %if.then, label %if.else if.else: diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll index ab511e8e6248..d46256b12052 100644 --- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll @@ -62,7 +62,7 @@ define double @caller_double_inreg() nounwind { ; RV32IFD-NEXT: lui a2, 262364 ; RV32IFD-NEXT: addi a3, a2, 655 ; RV32IFD-NEXT: mv a2, a0 -; RV32IFD-NEXT: call callee_double_inreg@plt +; RV32IFD-NEXT: call callee_double_inreg ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -78,7 +78,7 @@ define double @caller_double_inreg() nounwind { ; RV32IZFINXZDINX-NEXT: lui a2, 262364 ; RV32IZFINXZDINX-NEXT: addi a3, a2, 655 ; RV32IZFINXZDINX-NEXT: mv a2, a0 -; RV32IZFINXZDINX-NEXT: call callee_double_inreg@plt +; RV32IZFINXZDINX-NEXT: call callee_double_inreg ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -145,7 +145,7 @@ define double @caller_double_split_reg_stack() nounwind { ; RV32IFD-NEXT: li a2, 0 ; RV32IFD-NEXT: li a4, 0 ; RV32IFD-NEXT: mv a7, a5 -; RV32IFD-NEXT: call callee_double_split_reg_stack@plt +; RV32IFD-NEXT: call callee_double_split_reg_stack ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -167,7 +167,7 @@ define double @caller_double_split_reg_stack() nounwind { ; RV32IZFINXZDINX-NEXT: li a2, 0 ; RV32IZFINXZDINX-NEXT: li a4, 0 ; RV32IZFINXZDINX-NEXT: mv a7, a5 -; RV32IZFINXZDINX-NEXT: call callee_double_split_reg_stack@plt +; RV32IZFINXZDINX-NEXT: call callee_double_split_reg_stack ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -229,7 +229,7 @@ define double @caller_double_stack() nounwind { ; RV32IFD-NEXT: li a3, 0 ; RV32IFD-NEXT: li a5, 0 ; RV32IFD-NEXT: li a7, 0 -; RV32IFD-NEXT: call callee_double_stack@plt +; RV32IFD-NEXT: call callee_double_stack ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: ret @@ -256,7 +256,7 @@ define double @caller_double_stack() nounwind { ; RV32IZFINXZDINX-NEXT: li a3, 0 ; RV32IZFINXZDINX-NEXT: li a5, 0 ; RV32IZFINXZDINX-NEXT: li a7, 0 -; RV32IZFINXZDINX-NEXT: call callee_double_stack@plt +; RV32IZFINXZDINX-NEXT: call callee_double_stack ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 ; RV32IZFINXZDINX-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-convert-strict.ll b/llvm/test/CodeGen/RISCV/double-convert-strict.ll index adbe2c9e9754..967b119581af 100644 --- a/llvm/test/CodeGen/RISCV/double-convert-strict.ll +++ b/llvm/test/CodeGen/RISCV/double-convert-strict.ll @@ -46,7 +46,7 @@ define float @fcvt_s_d(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __truncdfsf2@plt +; RV32I-NEXT: call __truncdfsf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -55,7 +55,7 @@ define float @fcvt_s_d(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __truncdfsf2@plt +; RV64I-NEXT: call __truncdfsf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -90,7 +90,7 @@ define double @fcvt_d_s(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __extendsfdf2@plt +; RV32I-NEXT: call __extendsfdf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -99,7 +99,7 @@ define double @fcvt_d_s(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __extendsfdf2@plt +; RV64I-NEXT: call __extendsfdf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -134,7 +134,7 @@ define i32 @fcvt_w_d(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -143,7 +143,7 @@ define i32 @fcvt_w_d(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixdfsi@plt +; RV64I-NEXT: call __fixdfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -180,7 +180,7 @@ define i32 @fcvt_wu_d(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -189,7 +189,7 @@ define i32 @fcvt_wu_d(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfsi@plt +; RV64I-NEXT: call __fixunsdfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -232,7 +232,7 @@ define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: seqz a1, a0 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -243,7 +243,7 @@ define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfsi@plt +; RV64I-NEXT: call __fixunsdfsi ; RV64I-NEXT: seqz a1, a0 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -281,7 +281,7 @@ define double @fcvt_d_w(i32 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -291,7 +291,7 @@ define double @fcvt_d_w(i32 %a) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -330,7 +330,7 @@ define double @fcvt_d_w_load(ptr %p) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -340,7 +340,7 @@ define double @fcvt_d_w_load(ptr %p) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -375,7 +375,7 @@ define double @fcvt_d_wu(i32 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -385,7 +385,7 @@ define double @fcvt_d_wu(i32 %a) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -430,7 +430,7 @@ define double @fcvt_d_wu_load(ptr %p) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -440,7 +440,7 @@ define double @fcvt_d_wu_load(ptr %p) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -454,7 +454,7 @@ define i64 @fcvt_l_d(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -468,7 +468,7 @@ define i64 @fcvt_l_d(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -482,7 +482,7 @@ define i64 @fcvt_l_d(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixdfdi@plt +; RV32I-NEXT: call __fixdfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -491,7 +491,7 @@ define i64 @fcvt_l_d(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -505,7 +505,7 @@ define i64 @fcvt_lu_d(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -519,7 +519,7 @@ define i64 @fcvt_lu_d(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -533,7 +533,7 @@ define i64 @fcvt_lu_d(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfdi@plt +; RV32I-NEXT: call __fixunsdfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -542,7 +542,7 @@ define i64 @fcvt_lu_d(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -556,7 +556,7 @@ define double @fcvt_d_l(i64 %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __floatdidf@plt +; RV32IFD-NEXT: call __floatdidf ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -570,7 +570,7 @@ define double @fcvt_d_l(i64 %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __floatdidf@plt +; RV32IZFINXZDINX-NEXT: call __floatdidf ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -584,7 +584,7 @@ define double @fcvt_d_l(i64 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatdidf@plt +; RV32I-NEXT: call __floatdidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -593,7 +593,7 @@ define double @fcvt_d_l(i64 %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatdidf@plt +; RV64I-NEXT: call __floatdidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -607,7 +607,7 @@ define double @fcvt_d_lu(i64 %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __floatundidf@plt +; RV32IFD-NEXT: call __floatundidf ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -621,7 +621,7 @@ define double @fcvt_d_lu(i64 %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __floatundidf@plt +; RV32IZFINXZDINX-NEXT: call __floatundidf ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -635,7 +635,7 @@ define double @fcvt_d_lu(i64 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatundidf@plt +; RV32I-NEXT: call __floatundidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -644,7 +644,7 @@ define double @fcvt_d_lu(i64 %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatundidf@plt +; RV64I-NEXT: call __floatundidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -679,7 +679,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -688,7 +688,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -723,7 +723,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -732,7 +732,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -767,7 +767,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -776,7 +776,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -811,7 +811,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -820,7 +820,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -871,7 +871,7 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: sw a1, 4(s0) ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 @@ -890,7 +890,7 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: sd a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -944,7 +944,7 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind str ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: sw a1, 4(s0) ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 @@ -963,7 +963,7 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind str ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: sd a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll index 39ac963051b5..eb8ffe75ef76 100644 --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -38,7 +38,7 @@ define float @fcvt_s_d(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __truncdfsf2@plt +; RV32I-NEXT: call __truncdfsf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -47,7 +47,7 @@ define float @fcvt_s_d(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __truncdfsf2@plt +; RV64I-NEXT: call __truncdfsf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -81,7 +81,7 @@ define double @fcvt_d_s(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __extendsfdf2@plt +; RV32I-NEXT: call __extendsfdf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -90,7 +90,7 @@ define double @fcvt_d_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __extendsfdf2@plt +; RV64I-NEXT: call __extendsfdf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -124,7 +124,7 @@ define i32 @fcvt_w_d(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -133,7 +133,7 @@ define i32 @fcvt_w_d(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixdfsi@plt +; RV64I-NEXT: call __fixdfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -189,17 +189,17 @@ define i32 @fcvt_w_d_sat(double %a) nounwind { ; RV32I-NEXT: lui a3, 269824 ; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1047552 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 794112 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: bgez s4, .LBB3_2 @@ -214,7 +214,7 @@ define i32 @fcvt_w_d_sat(double %a) nounwind { ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s3 @@ -238,10 +238,10 @@ define i32 @fcvt_w_d_sat(double %a) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, -497 ; RV64I-NEXT: slli a1, a1, 53 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui s3, 524288 ; RV64I-NEXT: bgez s2, .LBB3_2 @@ -253,14 +253,14 @@ define i32 @fcvt_w_d_sat(double %a) nounwind { ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: slli a1, a0, 22 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB3_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: addiw s1, s3, -1 ; RV64I-NEXT: .LBB3_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -305,7 +305,7 @@ define i32 @fcvt_wu_d(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -314,7 +314,7 @@ define i32 @fcvt_wu_d(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfsi@plt +; RV64I-NEXT: call __fixunsdfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -356,7 +356,7 @@ define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: seqz a1, a0 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -367,7 +367,7 @@ define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfsi@plt +; RV64I-NEXT: call __fixunsdfsi ; RV64I-NEXT: seqz a1, a0 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -439,19 +439,19 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind { ; RV32I-NEXT: lui a3, 270080 ; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1048064 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: and a0, s3, a0 ; RV32I-NEXT: or a0, s2, a0 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -471,17 +471,17 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a0, 1055 ; RV64I-NEXT: slli a0, a0, 31 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: slli a1, a0, 21 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB6_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, -1 @@ -530,7 +530,7 @@ define double @fcvt_d_w(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -540,7 +540,7 @@ define double @fcvt_d_w(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -578,7 +578,7 @@ define double @fcvt_d_w_load(ptr %p) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -588,7 +588,7 @@ define double @fcvt_d_w_load(ptr %p) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -623,7 +623,7 @@ define double @fcvt_d_wu(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -633,7 +633,7 @@ define double @fcvt_d_wu(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -677,7 +677,7 @@ define double @fcvt_d_wu_load(ptr %p) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -687,7 +687,7 @@ define double @fcvt_d_wu_load(ptr %p) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -701,7 +701,7 @@ define i64 @fcvt_l_d(double %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -715,7 +715,7 @@ define i64 @fcvt_l_d(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -729,7 +729,7 @@ define i64 @fcvt_l_d(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixdfdi@plt +; RV32I-NEXT: call __fixdfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -738,7 +738,7 @@ define i64 @fcvt_l_d(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -757,7 +757,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 ; RV32IFD-NEXT: beqz s0, .LBB12_2 @@ -804,7 +804,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp) -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2) @@ -861,17 +861,17 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: lui a3, 278016 ; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: li a2, -1 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixdfdi@plt +; RV32I-NEXT: call __fixdfdi ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: lui a0, 524288 @@ -887,7 +887,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a1, a0, s5 @@ -919,10 +919,10 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, -481 ; RV64I-NEXT: slli a1, a1, 53 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li s3, -1 ; RV64I-NEXT: bgez s2, .LBB12_2 @@ -933,14 +933,14 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV64I-NEXT: slli a0, a0, 53 ; RV64I-NEXT: addi a1, a0, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB12_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: srli s1, s3, 1 ; RV64I-NEXT: .LBB12_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -962,7 +962,7 @@ define i64 @fcvt_lu_d(double %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -976,7 +976,7 @@ define i64 @fcvt_lu_d(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -990,7 +990,7 @@ define i64 @fcvt_lu_d(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfdi@plt +; RV32I-NEXT: call __fixunsdfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -999,7 +999,7 @@ define i64 @fcvt_lu_d(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1018,7 +1018,7 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s0, a0 -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2) ; RV32IFD-NEXT: and a0, s0, a0 @@ -1052,7 +1052,7 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp) -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0) ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4) @@ -1093,19 +1093,19 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32I-NEXT: lui a3, 278272 ; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: li a2, -1 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixunsdfdi@plt +; RV32I-NEXT: call __fixunsdfdi ; RV32I-NEXT: and a0, s3, a0 ; RV32I-NEXT: or a0, s2, a0 ; RV32I-NEXT: and a1, s3, a1 @@ -1126,17 +1126,17 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: addi s1, a0, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: and s1, s1, a0 ; RV64I-NEXT: li a0, 1087 ; RV64I-NEXT: slli a0, a0, 52 ; RV64I-NEXT: addi a1, a0, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: neg a0, a0 ; RV64I-NEXT: or a0, a0, s1 @@ -1196,7 +1196,7 @@ define i64 @fmv_x_d(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1205,7 +1205,7 @@ define i64 @fmv_x_d(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1219,7 +1219,7 @@ define double @fcvt_d_l(i64 %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __floatdidf@plt +; RV32IFD-NEXT: call __floatdidf ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1233,7 +1233,7 @@ define double @fcvt_d_l(i64 %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __floatdidf@plt +; RV32IZFINXZDINX-NEXT: call __floatdidf ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1247,7 +1247,7 @@ define double @fcvt_d_l(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatdidf@plt +; RV32I-NEXT: call __floatdidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1256,7 +1256,7 @@ define double @fcvt_d_l(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatdidf@plt +; RV64I-NEXT: call __floatdidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1269,7 +1269,7 @@ define double @fcvt_d_lu(i64 %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __floatundidf@plt +; RV32IFD-NEXT: call __floatundidf ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1283,7 +1283,7 @@ define double @fcvt_d_lu(i64 %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __floatundidf@plt +; RV32IZFINXZDINX-NEXT: call __floatundidf ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1297,7 +1297,7 @@ define double @fcvt_d_lu(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatundidf@plt +; RV32I-NEXT: call __floatundidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1306,7 +1306,7 @@ define double @fcvt_d_lu(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatundidf@plt +; RV64I-NEXT: call __floatundidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1364,7 +1364,7 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1373,7 +1373,7 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1409,7 +1409,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1418,7 +1418,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1452,7 +1452,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1461,7 +1461,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1495,7 +1495,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1504,7 +1504,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1538,7 +1538,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1547,7 +1547,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1597,7 +1597,7 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatsidf@plt +; RV32I-NEXT: call __floatsidf ; RV32I-NEXT: sw a1, 4(s0) ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 @@ -1616,7 +1616,7 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatsidf@plt +; RV64I-NEXT: call __floatsidf ; RV64I-NEXT: sd a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1670,7 +1670,7 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatunsidf@plt +; RV32I-NEXT: call __floatunsidf ; RV32I-NEXT: sw a1, 4(s0) ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 @@ -1689,7 +1689,7 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatunsidf@plt +; RV64I-NEXT: call __floatunsidf ; RV64I-NEXT: sd a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1734,7 +1734,7 @@ define signext i16 @fcvt_w_s_i16(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1743,7 +1743,7 @@ define signext i16 @fcvt_w_s_i16(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1831,17 +1831,17 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { ; RV32I-NEXT: addi a3, a0, -64 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 790016 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: bgez s4, .LBB26_2 ; RV32I-NEXT: # %bb.1: # %start @@ -1856,7 +1856,7 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s3 @@ -1881,10 +1881,10 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, -505 ; RV64I-NEXT: slli a1, a1, 53 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: bgez s2, .LBB26_2 ; RV64I-NEXT: # %bb.1: # %start @@ -1894,7 +1894,7 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: slli a1, a0, 38 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB26_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: lui s1, 8 @@ -1902,7 +1902,7 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { ; RV64I-NEXT: .LBB26_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -1951,7 +1951,7 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1960,7 +1960,7 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2028,17 +2028,17 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind { ; RV32I-NEXT: lui a3, 265984 ; RV32I-NEXT: addi a3, a3, -32 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: blez s3, .LBB28_2 @@ -2068,16 +2068,16 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 8312 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: slli a1, a0, 37 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: blez a0, .LBB28_2 @@ -2133,7 +2133,7 @@ define signext i8 @fcvt_w_s_i8(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2142,7 +2142,7 @@ define signext i8 @fcvt_w_s_i8(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2228,17 +2228,17 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a3, 263676 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 787968 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: bgez s4, .LBB30_2 ; RV32I-NEXT: # %bb.1: # %start @@ -2252,7 +2252,7 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind { ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s3 @@ -2277,10 +2277,10 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, -509 ; RV64I-NEXT: slli a1, a1, 53 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: bgez s2, .LBB30_2 ; RV64I-NEXT: # %bb.1: # %start @@ -2289,14 +2289,14 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind { ; RV64I-NEXT: lui a1, 65919 ; RV64I-NEXT: slli a1, a1, 34 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB30_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: li s1, 127 ; RV64I-NEXT: .LBB30_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -2347,7 +2347,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2356,7 +2356,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2425,17 +2425,17 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind { ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 263934 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: blez s3, .LBB32_2 ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: li a0, 255 @@ -2463,15 +2463,15 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a1, 131967 ; RV64I-NEXT: slli a1, a1, 33 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB32_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, 255 @@ -2554,19 +2554,19 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind { ; RV32I-NEXT: lui a3, 270080 ; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1048064 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixunsdfsi@plt +; RV32I-NEXT: call __fixunsdfsi ; RV32I-NEXT: and a0, s3, a0 ; RV32I-NEXT: or a0, s2, a0 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -2586,17 +2586,17 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunsdfdi@plt +; RV64I-NEXT: call __fixunsdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a0, 1055 ; RV64I-NEXT: slli a0, a0, 31 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: slli a1, a0, 21 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB33_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, -1 @@ -2668,17 +2668,17 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind { ; RV32I-NEXT: lui a3, 269824 ; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1047552 -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 794112 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __fixdfsi@plt +; RV32I-NEXT: call __fixdfsi ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: bgez s4, .LBB34_2 @@ -2693,7 +2693,7 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind { ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s3 @@ -2717,10 +2717,10 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, -497 ; RV64I-NEXT: slli a1, a1, 53 -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixdfdi@plt +; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui s3, 524288 ; RV64I-NEXT: bgez s2, .LBB34_2 @@ -2732,14 +2732,14 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind { ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: slli a1, a0, 22 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: blez a0, .LBB34_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: addi s1, s3, -1 ; RV64I-NEXT: .LBB34_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 diff --git a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll index 428f63196bfe..3ae2e997019c 100644 --- a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll +++ b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll @@ -46,7 +46,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -56,7 +56,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -107,7 +107,7 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -117,7 +117,7 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -167,7 +167,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -178,7 +178,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -229,7 +229,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltdf2@plt +; RV32I-NEXT: call __ltdf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -239,7 +239,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltdf2@plt +; RV64I-NEXT: call __ltdf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -289,7 +289,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ledf2@plt +; RV32I-NEXT: call __ledf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -299,7 +299,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ledf2@plt +; RV64I-NEXT: call __ledf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -375,13 +375,13 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: snez s4, a0 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -402,11 +402,11 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: snez s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -456,7 +456,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -466,7 +466,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -545,13 +545,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: seqz s4, a0 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: or a0, a0, s4 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -572,11 +572,11 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: seqz s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: or a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -633,7 +633,7 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ledf2@plt +; RV32I-NEXT: call __ledf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -643,7 +643,7 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ledf2@plt +; RV64I-NEXT: call __ledf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -696,7 +696,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltdf2@plt +; RV32I-NEXT: call __ltdf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -707,7 +707,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltdf2@plt +; RV64I-NEXT: call __ltdf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -761,7 +761,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -771,7 +771,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -824,7 +824,7 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -834,7 +834,7 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -877,7 +877,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __nedf2@plt +; RV32I-NEXT: call __nedf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -887,7 +887,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __nedf2@plt +; RV64I-NEXT: call __nedf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -936,7 +936,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -946,7 +946,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -992,7 +992,7 @@ define i32 @fcmps_oeq(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1002,7 +1002,7 @@ define i32 @fcmps_oeq(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1043,7 +1043,7 @@ define i32 @fcmps_ogt(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1053,7 +1053,7 @@ define i32 @fcmps_ogt(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1093,7 +1093,7 @@ define i32 @fcmps_oge(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1104,7 +1104,7 @@ define i32 @fcmps_oge(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1145,7 +1145,7 @@ define i32 @fcmps_olt(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltdf2@plt +; RV32I-NEXT: call __ltdf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1155,7 +1155,7 @@ define i32 @fcmps_olt(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltdf2@plt +; RV64I-NEXT: call __ltdf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1195,7 +1195,7 @@ define i32 @fcmps_ole(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ledf2@plt +; RV32I-NEXT: call __ledf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1205,7 +1205,7 @@ define i32 @fcmps_ole(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ledf2@plt +; RV64I-NEXT: call __ledf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1260,13 +1260,13 @@ define i32 @fcmps_one(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: snez s4, a0 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -1287,11 +1287,11 @@ define i32 @fcmps_one(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: snez s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1341,7 +1341,7 @@ define i32 @fcmps_ord(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1351,7 +1351,7 @@ define i32 @fcmps_ord(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1409,13 +1409,13 @@ define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: seqz s4, a0 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: or a0, a0, s4 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -1436,11 +1436,11 @@ define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: seqz s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: or a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1487,7 +1487,7 @@ define i32 @fcmps_ugt(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ledf2@plt +; RV32I-NEXT: call __ledf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1497,7 +1497,7 @@ define i32 @fcmps_ugt(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ledf2@plt +; RV64I-NEXT: call __ledf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1540,7 +1540,7 @@ define i32 @fcmps_uge(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltdf2@plt +; RV32I-NEXT: call __ltdf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1551,7 +1551,7 @@ define i32 @fcmps_uge(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltdf2@plt +; RV64I-NEXT: call __ltdf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1595,7 +1595,7 @@ define i32 @fcmps_ult(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1605,7 +1605,7 @@ define i32 @fcmps_ult(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1648,7 +1648,7 @@ define i32 @fcmps_ule(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1658,7 +1658,7 @@ define i32 @fcmps_ule(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1707,7 +1707,7 @@ define i32 @fcmps_une(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __nedf2@plt +; RV32I-NEXT: call __nedf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1717,7 +1717,7 @@ define i32 @fcmps_une(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __nedf2@plt +; RV64I-NEXT: call __nedf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1766,7 +1766,7 @@ define i32 @fcmps_uno(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1776,7 +1776,7 @@ define i32 @fcmps_uno(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll index b1b3c46c4bf5..64a154f450f1 100644 --- a/llvm/test/CodeGen/RISCV/double-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll @@ -67,7 +67,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -77,7 +77,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -117,7 +117,7 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -127,7 +127,7 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -167,7 +167,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -178,7 +178,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -219,7 +219,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltdf2@plt +; RV32I-NEXT: call __ltdf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -229,7 +229,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltdf2@plt +; RV64I-NEXT: call __ltdf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -269,7 +269,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ledf2@plt +; RV32I-NEXT: call __ledf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -279,7 +279,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ledf2@plt +; RV64I-NEXT: call __ledf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -334,13 +334,13 @@ define i32 @fcmp_one(double %a, double %b) nounwind { ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: snez s4, a0 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -361,11 +361,11 @@ define i32 @fcmp_one(double %a, double %b) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: snez s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -415,7 +415,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -425,7 +425,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -483,13 +483,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind { ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: call __eqdf2@plt +; RV32I-NEXT: call __eqdf2 ; RV32I-NEXT: seqz s4, a0 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: or a0, a0, s4 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -510,11 +510,11 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqdf2@plt +; RV64I-NEXT: call __eqdf2 ; RV64I-NEXT: seqz s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: or a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -561,7 +561,7 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ledf2@plt +; RV32I-NEXT: call __ledf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -571,7 +571,7 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ledf2@plt +; RV64I-NEXT: call __ledf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -614,7 +614,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltdf2@plt +; RV32I-NEXT: call __ltdf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -625,7 +625,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltdf2@plt +; RV64I-NEXT: call __ltdf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -669,7 +669,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gedf2@plt +; RV32I-NEXT: call __gedf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -679,7 +679,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gedf2@plt +; RV64I-NEXT: call __gedf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -722,7 +722,7 @@ define i32 @fcmp_ule(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtdf2@plt +; RV32I-NEXT: call __gtdf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -732,7 +732,7 @@ define i32 @fcmp_ule(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtdf2@plt +; RV64I-NEXT: call __gtdf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -775,7 +775,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __nedf2@plt +; RV32I-NEXT: call __nedf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -785,7 +785,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __nedf2@plt +; RV64I-NEXT: call __nedf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -834,7 +834,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unorddf2@plt +; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -844,7 +844,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unorddf2@plt +; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/double-frem.ll b/llvm/test/CodeGen/RISCV/double-frem.ll index 118ded45c0fc..5303e84e5ded 100644 --- a/llvm/test/CodeGen/RISCV/double-frem.ll +++ b/llvm/test/CodeGen/RISCV/double-frem.ll @@ -11,24 +11,24 @@ define double @frem_f64(double %a, double %b) nounwind { ; RV32IFD-LABEL: frem_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail fmod@plt +; RV32IFD-NEXT: tail fmod ; ; RV64IFD-LABEL: frem_f64: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: tail fmod@plt +; RV64IFD-NEXT: tail fmod ; ; RV32IZFINXZDINX-LABEL: frem_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call fmod@plt +; RV32IZFINXZDINX-NEXT: call fmod ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: frem_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail fmod@plt +; RV64IZFINXZDINX-NEXT: tail fmod %1 = frem double %a, %b ret double %1 } diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll index da24e4b7b718..c574f64150a2 100644 --- a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll +++ b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll @@ -50,7 +50,7 @@ define double @sqrt_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrt@plt +; RV32I-NEXT: call sqrt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -59,7 +59,7 @@ define double @sqrt_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrt@plt +; RV64I-NEXT: call sqrt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -74,7 +74,7 @@ define double @powi_f64(double %a, i32 %b) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __powidf2@plt +; RV32IFD-NEXT: call __powidf2 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -84,7 +84,7 @@ define double @powi_f64(double %a, i32 %b) nounwind strictfp { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sext.w a0, a0 -; RV64IFD-NEXT: call __powidf2@plt +; RV64IFD-NEXT: call __powidf2 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -93,7 +93,7 @@ define double @powi_f64(double %a, i32 %b) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __powidf2@plt +; RV32IZFINXZDINX-NEXT: call __powidf2 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -103,7 +103,7 @@ define double @powi_f64(double %a, i32 %b) nounwind strictfp { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: sext.w a1, a1 -; RV64IZFINXZDINX-NEXT: call __powidf2@plt +; RV64IZFINXZDINX-NEXT: call __powidf2 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -112,7 +112,7 @@ define double @powi_f64(double %a, i32 %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __powidf2@plt +; RV32I-NEXT: call __powidf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -122,7 +122,7 @@ define double @powi_f64(double %a, i32 %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __powidf2@plt +; RV64I-NEXT: call __powidf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -137,7 +137,7 @@ define double @sin_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call sin@plt +; RV32IFD-NEXT: call sin ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -146,7 +146,7 @@ define double @sin_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call sin@plt +; RV64IFD-NEXT: call sin ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -155,7 +155,7 @@ define double @sin_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call sin@plt +; RV32IZFINXZDINX-NEXT: call sin ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -164,7 +164,7 @@ define double @sin_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call sin@plt +; RV64IZFINXZDINX-NEXT: call sin ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -173,7 +173,7 @@ define double @sin_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sin@plt +; RV32I-NEXT: call sin ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -182,7 +182,7 @@ define double @sin_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sin@plt +; RV64I-NEXT: call sin ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -197,7 +197,7 @@ define double @cos_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call cos@plt +; RV32IFD-NEXT: call cos ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -206,7 +206,7 @@ define double @cos_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call cos@plt +; RV64IFD-NEXT: call cos ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -215,7 +215,7 @@ define double @cos_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call cos@plt +; RV32IZFINXZDINX-NEXT: call cos ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -224,7 +224,7 @@ define double @cos_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call cos@plt +; RV64IZFINXZDINX-NEXT: call cos ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -233,7 +233,7 @@ define double @cos_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call cos@plt +; RV32I-NEXT: call cos ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -242,7 +242,7 @@ define double @cos_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call cos@plt +; RV64I-NEXT: call cos ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -259,10 +259,10 @@ define double @sincos_f64(double %a) nounwind strictfp { ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: call sin@plt +; RV32IFD-NEXT: call sin ; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs0 -; RV32IFD-NEXT: call cos@plt +; RV32IFD-NEXT: call cos ; RV32IFD-NEXT: fadd.d fa0, fs1, fa0 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload @@ -277,10 +277,10 @@ define double @sincos_f64(double %a) nounwind strictfp { ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs0, fa0 -; RV64IFD-NEXT: call sin@plt +; RV64IFD-NEXT: call sin ; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs0 -; RV64IFD-NEXT: call cos@plt +; RV64IFD-NEXT: call cos ; RV64IFD-NEXT: fadd.d fa0, fs1, fa0 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload @@ -298,14 +298,14 @@ define double @sincos_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: mv s0, a1 ; RV32IZFINXZDINX-NEXT: mv s1, a0 -; RV32IZFINXZDINX-NEXT: call sin@plt +; RV32IZFINXZDINX-NEXT: call sin ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) ; RV32IZFINXZDINX-NEXT: lw s3, 4(sp) ; RV32IZFINXZDINX-NEXT: mv a0, s1 ; RV32IZFINXZDINX-NEXT: mv a1, s0 -; RV32IZFINXZDINX-NEXT: call cos@plt +; RV32IZFINXZDINX-NEXT: call cos ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) @@ -330,10 +330,10 @@ define double @sincos_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv s0, a0 -; RV64IZFINXZDINX-NEXT: call sin@plt +; RV64IZFINXZDINX-NEXT: call sin ; RV64IZFINXZDINX-NEXT: mv s1, a0 ; RV64IZFINXZDINX-NEXT: mv a0, s0 -; RV64IZFINXZDINX-NEXT: call cos@plt +; RV64IZFINXZDINX-NEXT: call cos ; RV64IZFINXZDINX-NEXT: fadd.d a0, s1, a0 ; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -351,17 +351,17 @@ define double @sincos_f64(double %a) nounwind strictfp { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call sin@plt +; RV32I-NEXT: call sin ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call cos@plt +; RV32I-NEXT: call cos ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -377,13 +377,13 @@ define double @sincos_f64(double %a) nounwind strictfp { ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: call sin@plt +; RV64I-NEXT: call sin ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call cos@plt +; RV64I-NEXT: call cos ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -402,7 +402,7 @@ define double @pow_f64(double %a, double %b) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call pow@plt +; RV32IFD-NEXT: call pow ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -411,7 +411,7 @@ define double @pow_f64(double %a, double %b) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call pow@plt +; RV64IFD-NEXT: call pow ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -420,7 +420,7 @@ define double @pow_f64(double %a, double %b) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call pow@plt +; RV32IZFINXZDINX-NEXT: call pow ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -429,7 +429,7 @@ define double @pow_f64(double %a, double %b) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call pow@plt +; RV64IZFINXZDINX-NEXT: call pow ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -438,7 +438,7 @@ define double @pow_f64(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call pow@plt +; RV32I-NEXT: call pow ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -447,7 +447,7 @@ define double @pow_f64(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call pow@plt +; RV64I-NEXT: call pow ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -462,7 +462,7 @@ define double @exp_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call exp@plt +; RV32IFD-NEXT: call exp ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -471,7 +471,7 @@ define double @exp_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call exp@plt +; RV64IFD-NEXT: call exp ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -480,7 +480,7 @@ define double @exp_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call exp@plt +; RV32IZFINXZDINX-NEXT: call exp ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -489,7 +489,7 @@ define double @exp_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call exp@plt +; RV64IZFINXZDINX-NEXT: call exp ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -498,7 +498,7 @@ define double @exp_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call exp@plt +; RV32I-NEXT: call exp ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -507,7 +507,7 @@ define double @exp_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call exp@plt +; RV64I-NEXT: call exp ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -522,7 +522,7 @@ define double @exp2_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call exp2@plt +; RV32IFD-NEXT: call exp2 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -531,7 +531,7 @@ define double @exp2_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call exp2@plt +; RV64IFD-NEXT: call exp2 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -540,7 +540,7 @@ define double @exp2_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call exp2@plt +; RV32IZFINXZDINX-NEXT: call exp2 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -549,7 +549,7 @@ define double @exp2_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call exp2@plt +; RV64IZFINXZDINX-NEXT: call exp2 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -558,7 +558,7 @@ define double @exp2_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call exp2@plt +; RV32I-NEXT: call exp2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -567,7 +567,7 @@ define double @exp2_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call exp2@plt +; RV64I-NEXT: call exp2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -582,7 +582,7 @@ define double @log_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call log@plt +; RV32IFD-NEXT: call log ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -591,7 +591,7 @@ define double @log_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call log@plt +; RV64IFD-NEXT: call log ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -600,7 +600,7 @@ define double @log_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call log@plt +; RV32IZFINXZDINX-NEXT: call log ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -609,7 +609,7 @@ define double @log_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call log@plt +; RV64IZFINXZDINX-NEXT: call log ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -618,7 +618,7 @@ define double @log_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log@plt +; RV32I-NEXT: call log ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -627,7 +627,7 @@ define double @log_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log@plt +; RV64I-NEXT: call log ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -642,7 +642,7 @@ define double @log10_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call log10@plt +; RV32IFD-NEXT: call log10 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -651,7 +651,7 @@ define double @log10_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call log10@plt +; RV64IFD-NEXT: call log10 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -660,7 +660,7 @@ define double @log10_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call log10@plt +; RV32IZFINXZDINX-NEXT: call log10 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -669,7 +669,7 @@ define double @log10_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call log10@plt +; RV64IZFINXZDINX-NEXT: call log10 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -678,7 +678,7 @@ define double @log10_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log10@plt +; RV32I-NEXT: call log10 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -687,7 +687,7 @@ define double @log10_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log10@plt +; RV64I-NEXT: call log10 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -702,7 +702,7 @@ define double @log2_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call log2@plt +; RV32IFD-NEXT: call log2 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -711,7 +711,7 @@ define double @log2_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call log2@plt +; RV64IFD-NEXT: call log2 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -720,7 +720,7 @@ define double @log2_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call log2@plt +; RV32IZFINXZDINX-NEXT: call log2 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -729,7 +729,7 @@ define double @log2_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call log2@plt +; RV64IZFINXZDINX-NEXT: call log2 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -738,7 +738,7 @@ define double @log2_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log2@plt +; RV32I-NEXT: call log2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -747,7 +747,7 @@ define double @log2_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log2@plt +; RV64I-NEXT: call log2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -795,7 +795,7 @@ define double @fma_f64(double %a, double %b, double %c) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -804,7 +804,7 @@ define double @fma_f64(double %a, double %b, double %c) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -856,10 +856,10 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind strictfp { ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a5 ; RV32I-NEXT: mv s1, a4 -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -872,9 +872,9 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind strictfp { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -890,7 +890,7 @@ define double @minnum_f64(double %a, double %b) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call fmin@plt +; RV32IFD-NEXT: call fmin ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -899,7 +899,7 @@ define double @minnum_f64(double %a, double %b) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call fmin@plt +; RV64IFD-NEXT: call fmin ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -908,7 +908,7 @@ define double @minnum_f64(double %a, double %b) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call fmin@plt +; RV32IZFINXZDINX-NEXT: call fmin ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -917,7 +917,7 @@ define double @minnum_f64(double %a, double %b) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call fmin@plt +; RV64IZFINXZDINX-NEXT: call fmin ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -926,7 +926,7 @@ define double @minnum_f64(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmin@plt +; RV32I-NEXT: call fmin ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -935,7 +935,7 @@ define double @minnum_f64(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmin@plt +; RV64I-NEXT: call fmin ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -950,7 +950,7 @@ define double @maxnum_f64(double %a, double %b) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call fmax@plt +; RV32IFD-NEXT: call fmax ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -959,7 +959,7 @@ define double @maxnum_f64(double %a, double %b) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call fmax@plt +; RV64IFD-NEXT: call fmax ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -968,7 +968,7 @@ define double @maxnum_f64(double %a, double %b) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call fmax@plt +; RV32IZFINXZDINX-NEXT: call fmax ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -977,7 +977,7 @@ define double @maxnum_f64(double %a, double %b) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call fmax@plt +; RV64IZFINXZDINX-NEXT: call fmax ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -986,7 +986,7 @@ define double @maxnum_f64(double %a, double %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmax@plt +; RV32I-NEXT: call fmax ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -995,7 +995,7 @@ define double @maxnum_f64(double %a, double %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmax@plt +; RV64I-NEXT: call fmax ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1027,7 +1027,7 @@ define double @floor_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call floor@plt +; RV32IFD-NEXT: call floor ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1036,7 +1036,7 @@ define double @floor_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call floor@plt +; RV64IFD-NEXT: call floor ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1045,7 +1045,7 @@ define double @floor_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call floor@plt +; RV32IZFINXZDINX-NEXT: call floor ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1054,7 +1054,7 @@ define double @floor_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call floor@plt +; RV64IZFINXZDINX-NEXT: call floor ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1063,7 +1063,7 @@ define double @floor_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call floor@plt +; RV32I-NEXT: call floor ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1072,7 +1072,7 @@ define double @floor_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call floor@plt +; RV64I-NEXT: call floor ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1087,7 +1087,7 @@ define double @ceil_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call ceil@plt +; RV32IFD-NEXT: call ceil ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1096,7 +1096,7 @@ define double @ceil_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call ceil@plt +; RV64IFD-NEXT: call ceil ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1105,7 +1105,7 @@ define double @ceil_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call ceil@plt +; RV32IZFINXZDINX-NEXT: call ceil ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1114,7 +1114,7 @@ define double @ceil_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call ceil@plt +; RV64IZFINXZDINX-NEXT: call ceil ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1123,7 +1123,7 @@ define double @ceil_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call ceil@plt +; RV32I-NEXT: call ceil ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1132,7 +1132,7 @@ define double @ceil_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call ceil@plt +; RV64I-NEXT: call ceil ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1147,7 +1147,7 @@ define double @trunc_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call trunc@plt +; RV32IFD-NEXT: call trunc ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1156,7 +1156,7 @@ define double @trunc_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call trunc@plt +; RV64IFD-NEXT: call trunc ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1165,7 +1165,7 @@ define double @trunc_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call trunc@plt +; RV32IZFINXZDINX-NEXT: call trunc ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1174,7 +1174,7 @@ define double @trunc_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call trunc@plt +; RV64IZFINXZDINX-NEXT: call trunc ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1183,7 +1183,7 @@ define double @trunc_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call trunc@plt +; RV32I-NEXT: call trunc ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1192,7 +1192,7 @@ define double @trunc_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call trunc@plt +; RV64I-NEXT: call trunc ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1207,7 +1207,7 @@ define double @rint_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call rint@plt +; RV32IFD-NEXT: call rint ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1216,7 +1216,7 @@ define double @rint_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call rint@plt +; RV64IFD-NEXT: call rint ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1225,7 +1225,7 @@ define double @rint_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call rint@plt +; RV32IZFINXZDINX-NEXT: call rint ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1234,7 +1234,7 @@ define double @rint_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call rint@plt +; RV64IZFINXZDINX-NEXT: call rint ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1243,7 +1243,7 @@ define double @rint_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call rint@plt +; RV32I-NEXT: call rint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1252,7 +1252,7 @@ define double @rint_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call rint@plt +; RV64I-NEXT: call rint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1267,7 +1267,7 @@ define double @nearbyint_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call nearbyint@plt +; RV32IFD-NEXT: call nearbyint ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1276,7 +1276,7 @@ define double @nearbyint_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call nearbyint@plt +; RV64IFD-NEXT: call nearbyint ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1285,7 +1285,7 @@ define double @nearbyint_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call nearbyint@plt +; RV32IZFINXZDINX-NEXT: call nearbyint ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1294,7 +1294,7 @@ define double @nearbyint_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call nearbyint@plt +; RV64IZFINXZDINX-NEXT: call nearbyint ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1303,7 +1303,7 @@ define double @nearbyint_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call nearbyint@plt +; RV32I-NEXT: call nearbyint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1312,7 +1312,7 @@ define double @nearbyint_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call nearbyint@plt +; RV64I-NEXT: call nearbyint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1327,7 +1327,7 @@ define double @round_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call round@plt +; RV32IFD-NEXT: call round ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1336,7 +1336,7 @@ define double @round_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call round@plt +; RV64IFD-NEXT: call round ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1345,7 +1345,7 @@ define double @round_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call round@plt +; RV32IZFINXZDINX-NEXT: call round ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1354,7 +1354,7 @@ define double @round_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call round@plt +; RV64IZFINXZDINX-NEXT: call round ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1363,7 +1363,7 @@ define double @round_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call round@plt +; RV32I-NEXT: call round ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1372,7 +1372,7 @@ define double @round_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call round@plt +; RV64I-NEXT: call round ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1387,7 +1387,7 @@ define double @roundeven_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call roundeven@plt +; RV32IFD-NEXT: call roundeven ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1396,7 +1396,7 @@ define double @roundeven_f64(double %a) nounwind strictfp { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call roundeven@plt +; RV64IFD-NEXT: call roundeven ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1405,7 +1405,7 @@ define double @roundeven_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call roundeven@plt +; RV32IZFINXZDINX-NEXT: call roundeven ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1414,7 +1414,7 @@ define double @roundeven_f64(double %a) nounwind strictfp { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call roundeven@plt +; RV64IZFINXZDINX-NEXT: call roundeven ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1423,7 +1423,7 @@ define double @roundeven_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call roundeven@plt +; RV32I-NEXT: call roundeven ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1432,7 +1432,7 @@ define double @roundeven_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call roundeven@plt +; RV64I-NEXT: call roundeven ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1473,7 +1473,7 @@ define iXLen @lrint_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lrint@plt +; RV32I-NEXT: call lrint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1482,7 +1482,7 @@ define iXLen @lrint_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lrint@plt +; RV64I-NEXT: call lrint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1523,7 +1523,7 @@ define iXLen @lround_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lround@plt +; RV32I-NEXT: call lround ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1532,7 +1532,7 @@ define iXLen @lround_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lround@plt +; RV64I-NEXT: call lround ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1547,7 +1547,7 @@ define i64 @llrint_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call llrint@plt +; RV32IFD-NEXT: call llrint ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1561,7 +1561,7 @@ define i64 @llrint_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call llrint@plt +; RV32IZFINXZDINX-NEXT: call llrint ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1575,7 +1575,7 @@ define i64 @llrint_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llrint@plt +; RV32I-NEXT: call llrint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1584,7 +1584,7 @@ define i64 @llrint_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llrint@plt +; RV64I-NEXT: call llrint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1599,7 +1599,7 @@ define i64 @llround_f64(double %a) nounwind strictfp { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call llround@plt +; RV32IFD-NEXT: call llround ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1613,7 +1613,7 @@ define i64 @llround_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call llround@plt +; RV32IZFINXZDINX-NEXT: call llround ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1627,7 +1627,7 @@ define i64 @llround_f64(double %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llround@plt +; RV32I-NEXT: call llround ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1636,7 +1636,7 @@ define i64 @llround_f64(double %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llround@plt +; RV64I-NEXT: call llround ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll index 36268accc8fd..f290cf0f7736 100644 --- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll @@ -48,7 +48,7 @@ define double @sqrt_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrt@plt +; RV32I-NEXT: call sqrt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -57,7 +57,7 @@ define double @sqrt_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrt@plt +; RV64I-NEXT: call sqrt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -70,14 +70,14 @@ declare double @llvm.powi.f64.i32(double, i32) define double @powi_f64(double %a, i32 %b) nounwind { ; RV32IFD-LABEL: powi_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail __powidf2@plt +; RV32IFD-NEXT: tail __powidf2 ; ; RV64IFD-LABEL: powi_f64: ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sext.w a0, a0 -; RV64IFD-NEXT: call __powidf2@plt +; RV64IFD-NEXT: call __powidf2 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -86,7 +86,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __powidf2@plt +; RV32IZFINXZDINX-NEXT: call __powidf2 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -96,7 +96,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: sext.w a1, a1 -; RV64IZFINXZDINX-NEXT: call __powidf2@plt +; RV64IZFINXZDINX-NEXT: call __powidf2 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -105,7 +105,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __powidf2@plt +; RV32I-NEXT: call __powidf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -115,7 +115,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __powidf2@plt +; RV64I-NEXT: call __powidf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -128,26 +128,26 @@ declare double @llvm.sin.f64(double) define double @sin_f64(double %a) nounwind { ; CHECKIFD-LABEL: sin_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail sin@plt +; CHECKIFD-NEXT: tail sin ; ; RV32IZFINXZDINX-LABEL: sin_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call sin@plt +; RV32IZFINXZDINX-NEXT: call sin ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: sin_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail sin@plt +; RV64IZFINXZDINX-NEXT: tail sin ; ; RV32I-LABEL: sin_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sin@plt +; RV32I-NEXT: call sin ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -156,7 +156,7 @@ define double @sin_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sin@plt +; RV64I-NEXT: call sin ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -169,26 +169,26 @@ declare double @llvm.cos.f64(double) define double @cos_f64(double %a) nounwind { ; CHECKIFD-LABEL: cos_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail cos@plt +; CHECKIFD-NEXT: tail cos ; ; RV32IZFINXZDINX-LABEL: cos_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call cos@plt +; RV32IZFINXZDINX-NEXT: call cos ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: cos_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail cos@plt +; RV64IZFINXZDINX-NEXT: tail cos ; ; RV32I-LABEL: cos_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call cos@plt +; RV32I-NEXT: call cos ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -197,7 +197,7 @@ define double @cos_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call cos@plt +; RV64I-NEXT: call cos ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -214,10 +214,10 @@ define double @sincos_f64(double %a) nounwind { ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: call sin@plt +; RV32IFD-NEXT: call sin ; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs0 -; RV32IFD-NEXT: call cos@plt +; RV32IFD-NEXT: call cos ; RV32IFD-NEXT: fadd.d fa0, fs1, fa0 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload @@ -232,10 +232,10 @@ define double @sincos_f64(double %a) nounwind { ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs0, fa0 -; RV64IFD-NEXT: call sin@plt +; RV64IFD-NEXT: call sin ; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs0 -; RV64IFD-NEXT: call cos@plt +; RV64IFD-NEXT: call cos ; RV64IFD-NEXT: fadd.d fa0, fs1, fa0 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload @@ -253,14 +253,14 @@ define double @sincos_f64(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: mv s0, a1 ; RV32IZFINXZDINX-NEXT: mv s1, a0 -; RV32IZFINXZDINX-NEXT: call sin@plt +; RV32IZFINXZDINX-NEXT: call sin ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) ; RV32IZFINXZDINX-NEXT: lw s3, 4(sp) ; RV32IZFINXZDINX-NEXT: mv a0, s1 ; RV32IZFINXZDINX-NEXT: mv a1, s0 -; RV32IZFINXZDINX-NEXT: call cos@plt +; RV32IZFINXZDINX-NEXT: call cos ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) @@ -285,10 +285,10 @@ define double @sincos_f64(double %a) nounwind { ; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv s0, a0 -; RV64IZFINXZDINX-NEXT: call sin@plt +; RV64IZFINXZDINX-NEXT: call sin ; RV64IZFINXZDINX-NEXT: mv s1, a0 ; RV64IZFINXZDINX-NEXT: mv a0, s0 -; RV64IZFINXZDINX-NEXT: call cos@plt +; RV64IZFINXZDINX-NEXT: call cos ; RV64IZFINXZDINX-NEXT: fadd.d a0, s1, a0 ; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -306,17 +306,17 @@ define double @sincos_f64(double %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call sin@plt +; RV32I-NEXT: call sin ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call cos@plt +; RV32I-NEXT: call cos ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -332,13 +332,13 @@ define double @sincos_f64(double %a) nounwind { ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: call sin@plt +; RV64I-NEXT: call sin ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call cos@plt +; RV64I-NEXT: call cos ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -355,26 +355,26 @@ declare double @llvm.pow.f64(double, double) define double @pow_f64(double %a, double %b) nounwind { ; CHECKIFD-LABEL: pow_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail pow@plt +; CHECKIFD-NEXT: tail pow ; ; RV32IZFINXZDINX-LABEL: pow_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call pow@plt +; RV32IZFINXZDINX-NEXT: call pow ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: pow_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail pow@plt +; RV64IZFINXZDINX-NEXT: tail pow ; ; RV32I-LABEL: pow_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call pow@plt +; RV32I-NEXT: call pow ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -383,7 +383,7 @@ define double @pow_f64(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call pow@plt +; RV64I-NEXT: call pow ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -396,26 +396,26 @@ declare double @llvm.exp.f64(double) define double @exp_f64(double %a) nounwind { ; CHECKIFD-LABEL: exp_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail exp@plt +; CHECKIFD-NEXT: tail exp ; ; RV32IZFINXZDINX-LABEL: exp_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call exp@plt +; RV32IZFINXZDINX-NEXT: call exp ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: exp_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail exp@plt +; RV64IZFINXZDINX-NEXT: tail exp ; ; RV32I-LABEL: exp_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call exp@plt +; RV32I-NEXT: call exp ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -424,7 +424,7 @@ define double @exp_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call exp@plt +; RV64I-NEXT: call exp ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -437,26 +437,26 @@ declare double @llvm.exp2.f64(double) define double @exp2_f64(double %a) nounwind { ; CHECKIFD-LABEL: exp2_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail exp2@plt +; CHECKIFD-NEXT: tail exp2 ; ; RV32IZFINXZDINX-LABEL: exp2_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call exp2@plt +; RV32IZFINXZDINX-NEXT: call exp2 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: exp2_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail exp2@plt +; RV64IZFINXZDINX-NEXT: tail exp2 ; ; RV32I-LABEL: exp2_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call exp2@plt +; RV32I-NEXT: call exp2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -465,7 +465,7 @@ define double @exp2_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call exp2@plt +; RV64I-NEXT: call exp2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -478,26 +478,26 @@ declare double @llvm.log.f64(double) define double @log_f64(double %a) nounwind { ; CHECKIFD-LABEL: log_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail log@plt +; CHECKIFD-NEXT: tail log ; ; RV32IZFINXZDINX-LABEL: log_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call log@plt +; RV32IZFINXZDINX-NEXT: call log ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: log_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail log@plt +; RV64IZFINXZDINX-NEXT: tail log ; ; RV32I-LABEL: log_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log@plt +; RV32I-NEXT: call log ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -506,7 +506,7 @@ define double @log_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log@plt +; RV64I-NEXT: call log ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -519,26 +519,26 @@ declare double @llvm.log10.f64(double) define double @log10_f64(double %a) nounwind { ; CHECKIFD-LABEL: log10_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail log10@plt +; CHECKIFD-NEXT: tail log10 ; ; RV32IZFINXZDINX-LABEL: log10_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call log10@plt +; RV32IZFINXZDINX-NEXT: call log10 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: log10_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail log10@plt +; RV64IZFINXZDINX-NEXT: tail log10 ; ; RV32I-LABEL: log10_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log10@plt +; RV32I-NEXT: call log10 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -547,7 +547,7 @@ define double @log10_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log10@plt +; RV64I-NEXT: call log10 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -560,26 +560,26 @@ declare double @llvm.log2.f64(double) define double @log2_f64(double %a) nounwind { ; CHECKIFD-LABEL: log2_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail log2@plt +; CHECKIFD-NEXT: tail log2 ; ; RV32IZFINXZDINX-LABEL: log2_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call log2@plt +; RV32IZFINXZDINX-NEXT: call log2 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: log2_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail log2@plt +; RV64IZFINXZDINX-NEXT: tail log2 ; ; RV32I-LABEL: log2_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log2@plt +; RV32I-NEXT: call log2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -588,7 +588,7 @@ define double @log2_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log2@plt +; RV64I-NEXT: call log2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -636,7 +636,7 @@ define double @fma_f64(double %a, double %b, double %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fma@plt +; RV32I-NEXT: call fma ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -645,7 +645,7 @@ define double @fma_f64(double %a, double %b, double %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fma@plt +; RV64I-NEXT: call fma ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -697,10 +697,10 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind { ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a5 ; RV32I-NEXT: mv s1, a4 -; RV32I-NEXT: call __muldf3@plt +; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __adddf3@plt +; RV32I-NEXT: call __adddf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -713,9 +713,9 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 -; RV64I-NEXT: call __muldf3@plt +; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __adddf3@plt +; RV64I-NEXT: call __adddf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -795,7 +795,7 @@ define double @minnum_f64(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmin@plt +; RV32I-NEXT: call fmin ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -804,7 +804,7 @@ define double @minnum_f64(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmin@plt +; RV64I-NEXT: call fmin ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -848,7 +848,7 @@ define double @maxnum_f64(double %a, double %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmax@plt +; RV32I-NEXT: call fmax ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -857,7 +857,7 @@ define double @maxnum_f64(double %a, double %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmax@plt +; RV64I-NEXT: call fmax ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -940,7 +940,7 @@ declare double @llvm.floor.f64(double) define double @floor_f64(double %a) nounwind { ; RV32IFD-LABEL: floor_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail floor@plt +; RV32IFD-NEXT: tail floor ; ; RV64IFD-LABEL: floor_f64: ; RV64IFD: # %bb.0: @@ -960,7 +960,7 @@ define double @floor_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call floor@plt +; RV32IZFINXZDINX-NEXT: call floor ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -983,7 +983,7 @@ define double @floor_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call floor@plt +; RV32I-NEXT: call floor ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -992,7 +992,7 @@ define double @floor_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call floor@plt +; RV64I-NEXT: call floor ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1005,7 +1005,7 @@ declare double @llvm.ceil.f64(double) define double @ceil_f64(double %a) nounwind { ; RV32IFD-LABEL: ceil_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail ceil@plt +; RV32IFD-NEXT: tail ceil ; ; RV64IFD-LABEL: ceil_f64: ; RV64IFD: # %bb.0: @@ -1025,7 +1025,7 @@ define double @ceil_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call ceil@plt +; RV32IZFINXZDINX-NEXT: call ceil ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1048,7 +1048,7 @@ define double @ceil_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call ceil@plt +; RV32I-NEXT: call ceil ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1057,7 +1057,7 @@ define double @ceil_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call ceil@plt +; RV64I-NEXT: call ceil ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1070,7 +1070,7 @@ declare double @llvm.trunc.f64(double) define double @trunc_f64(double %a) nounwind { ; RV32IFD-LABEL: trunc_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail trunc@plt +; RV32IFD-NEXT: tail trunc ; ; RV64IFD-LABEL: trunc_f64: ; RV64IFD: # %bb.0: @@ -1090,7 +1090,7 @@ define double @trunc_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call trunc@plt +; RV32IZFINXZDINX-NEXT: call trunc ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1113,7 +1113,7 @@ define double @trunc_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call trunc@plt +; RV32I-NEXT: call trunc ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1122,7 +1122,7 @@ define double @trunc_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call trunc@plt +; RV64I-NEXT: call trunc ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1135,7 +1135,7 @@ declare double @llvm.rint.f64(double) define double @rint_f64(double %a) nounwind { ; RV32IFD-LABEL: rint_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail rint@plt +; RV32IFD-NEXT: tail rint ; ; RV64IFD-LABEL: rint_f64: ; RV64IFD: # %bb.0: @@ -1155,7 +1155,7 @@ define double @rint_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call rint@plt +; RV32IZFINXZDINX-NEXT: call rint ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1178,7 +1178,7 @@ define double @rint_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call rint@plt +; RV32I-NEXT: call rint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1187,7 +1187,7 @@ define double @rint_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call rint@plt +; RV64I-NEXT: call rint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1200,26 +1200,26 @@ declare double @llvm.nearbyint.f64(double) define double @nearbyint_f64(double %a) nounwind { ; CHECKIFD-LABEL: nearbyint_f64: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: tail nearbyint@plt +; CHECKIFD-NEXT: tail nearbyint ; ; RV32IZFINXZDINX-LABEL: nearbyint_f64: ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call nearbyint@plt +; RV32IZFINXZDINX-NEXT: call nearbyint ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: nearbyint_f64: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: tail nearbyint@plt +; RV64IZFINXZDINX-NEXT: tail nearbyint ; ; RV32I-LABEL: nearbyint_f64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call nearbyint@plt +; RV32I-NEXT: call nearbyint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1228,7 +1228,7 @@ define double @nearbyint_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call nearbyint@plt +; RV64I-NEXT: call nearbyint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1241,7 +1241,7 @@ declare double @llvm.round.f64(double) define double @round_f64(double %a) nounwind { ; RV32IFD-LABEL: round_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail round@plt +; RV32IFD-NEXT: tail round ; ; RV64IFD-LABEL: round_f64: ; RV64IFD: # %bb.0: @@ -1261,7 +1261,7 @@ define double @round_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call round@plt +; RV32IZFINXZDINX-NEXT: call round ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1284,7 +1284,7 @@ define double @round_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call round@plt +; RV32I-NEXT: call round ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1293,7 +1293,7 @@ define double @round_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call round@plt +; RV64I-NEXT: call round ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1306,7 +1306,7 @@ declare double @llvm.roundeven.f64(double) define double @roundeven_f64(double %a) nounwind { ; RV32IFD-LABEL: roundeven_f64: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail roundeven@plt +; RV32IFD-NEXT: tail roundeven ; ; RV64IFD-LABEL: roundeven_f64: ; RV64IFD: # %bb.0: @@ -1326,7 +1326,7 @@ define double @roundeven_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call roundeven@plt +; RV32IZFINXZDINX-NEXT: call roundeven ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1349,7 +1349,7 @@ define double @roundeven_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call roundeven@plt +; RV32I-NEXT: call roundeven ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1358,7 +1358,7 @@ define double @roundeven_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call roundeven@plt +; RV64I-NEXT: call roundeven ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1399,7 +1399,7 @@ define iXLen @lrint_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lrint@plt +; RV32I-NEXT: call lrint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1408,7 +1408,7 @@ define iXLen @lrint_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lrint@plt +; RV64I-NEXT: call lrint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1450,7 +1450,7 @@ define iXLen @lround_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lround@plt +; RV32I-NEXT: call lround ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1459,7 +1459,7 @@ define iXLen @lround_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lround@plt +; RV64I-NEXT: call lround ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1493,7 +1493,7 @@ define i32 @lround_i32_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lround@plt +; RV32I-NEXT: call lround ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1502,7 +1502,7 @@ define i32 @lround_i32_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lround@plt +; RV64I-NEXT: call lround ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1517,7 +1517,7 @@ define i64 @llrint_f64(double %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call llrint@plt +; RV32IFD-NEXT: call llrint ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1531,7 +1531,7 @@ define i64 @llrint_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call llrint@plt +; RV32IZFINXZDINX-NEXT: call llrint ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1545,7 +1545,7 @@ define i64 @llrint_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llrint@plt +; RV32I-NEXT: call llrint ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1554,7 +1554,7 @@ define i64 @llrint_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llrint@plt +; RV64I-NEXT: call llrint ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1569,7 +1569,7 @@ define i64 @llround_f64(double %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call llround@plt +; RV32IFD-NEXT: call llround ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1583,7 +1583,7 @@ define i64 @llround_f64(double %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call llround@plt +; RV32IZFINXZDINX-NEXT: call llround ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1597,7 +1597,7 @@ define i64 @llround_f64(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llround@plt +; RV32I-NEXT: call llround ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1606,7 +1606,7 @@ define i64 @llround_f64(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llround@plt +; RV64I-NEXT: call llround ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll index fb043f44beb3..6c6f70d6e2ed 100644 --- a/llvm/test/CodeGen/RISCV/double-mem.ll +++ b/llvm/test/CodeGen/RISCV/double-mem.ll @@ -217,7 +217,7 @@ define dso_local double @fld_stack(double %a) nounwind { ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call notdead@plt +; RV32IFD-NEXT: call notdead ; RV32IFD-NEXT: fld fa5, 8(sp) ; RV32IFD-NEXT: fadd.d fa0, fa5, fs0 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -232,7 +232,7 @@ define dso_local double @fld_stack(double %a) nounwind { ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: addi a0, sp, 8 -; RV64IFD-NEXT: call notdead@plt +; RV64IFD-NEXT: call notdead ; RV64IFD-NEXT: fld fa5, 8(sp) ; RV64IFD-NEXT: fadd.d fa0, fa5, fs0 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -251,7 +251,7 @@ define dso_local double @fld_stack(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: lw s0, 0(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) ; RV32IZFINXZDINX-NEXT: addi a0, sp, 8 -; RV32IZFINXZDINX-NEXT: call notdead@plt +; RV32IZFINXZDINX-NEXT: call notdead ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, s0 @@ -272,7 +272,7 @@ define dso_local double @fld_stack(double %a) nounwind { ; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv s0, a0 ; RV64IZFINXZDINX-NEXT: addi a0, sp, 8 -; RV64IZFINXZDINX-NEXT: call notdead@plt +; RV64IZFINXZDINX-NEXT: call notdead ; RV64IZFINXZDINX-NEXT: ld a0, 8(sp) ; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, s0 ; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -294,7 +294,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind { ; RV32IFD-NEXT: fadd.d fa5, fa0, fa1 ; RV32IFD-NEXT: fsd fa5, 0(sp) ; RV32IFD-NEXT: mv a0, sp -; RV32IFD-NEXT: call notdead@plt +; RV32IFD-NEXT: call notdead ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -306,7 +306,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind { ; RV64IFD-NEXT: fadd.d fa5, fa0, fa1 ; RV64IFD-NEXT: fsd fa5, 0(sp) ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call notdead@plt +; RV64IFD-NEXT: call notdead ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -327,7 +327,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind { ; RV32IZFINXZDINX-NEXT: sw a0, 16(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 20(sp) ; RV32IZFINXZDINX-NEXT: addi a0, sp, 16 -; RV32IZFINXZDINX-NEXT: call notdead@plt +; RV32IZFINXZDINX-NEXT: call notdead ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 ; RV32IZFINXZDINX-NEXT: ret @@ -339,7 +339,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind { ; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1 ; RV64IZFINXZDINX-NEXT: sd a0, 0(sp) ; RV64IZFINXZDINX-NEXT: mv a0, sp -; RV64IZFINXZDINX-NEXT: call notdead@plt +; RV64IZFINXZDINX-NEXT: call notdead ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll index aec27b58e1fc..8b8f538886ed 100644 --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -25,7 +25,7 @@ define i32 @main() nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: li a0, 0 -; RV32IFD-NEXT: call test@plt +; RV32IFD-NEXT: call test ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: fld fa5, 0(sp) @@ -39,9 +39,9 @@ define i32 @main() nounwind { ; RV32IFD-NEXT: flt.d a0, fa4, fa5 ; RV32IFD-NEXT: bnez a0, .LBB1_3 ; RV32IFD-NEXT: # %bb.2: # %if.end -; RV32IFD-NEXT: call exit@plt +; RV32IFD-NEXT: call exit ; RV32IFD-NEXT: .LBB1_3: # %if.then -; RV32IFD-NEXT: call abort@plt +; RV32IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: main: ; RV32IZFINXZDINX: # %bb.0: # %entry @@ -49,7 +49,7 @@ define i32 @main() nounwind { ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: lui a1, 262144 ; RV32IZFINXZDINX-NEXT: li a0, 0 -; RV32IZFINXZDINX-NEXT: call test@plt +; RV32IZFINXZDINX-NEXT: call test ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) @@ -66,9 +66,9 @@ define i32 @main() nounwind { ; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 ; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3 ; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end -; RV32IZFINXZDINX-NEXT: call exit@plt +; RV32IZFINXZDINX-NEXT: call exit ; RV32IZFINXZDINX-NEXT: .LBB1_3: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt +; RV32IZFINXZDINX-NEXT: call abort entry: %call = call double @test(double 2.000000e+00) %cmp = fcmp olt double %call, 2.400000e-01 diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll index 5c5b4bb723b6..b8c6e8450240 100644 --- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll @@ -54,12 +54,12 @@ define i64 @test_floor_si64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: call floor@plt +; RV32IFD-NEXT: call floor ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 ; RV32IFD-NEXT: beqz s0, .LBB1_2 @@ -103,7 +103,7 @@ define i64 @test_floor_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call floor@plt +; RV32IZFINXZDINX-NEXT: call floor ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 8(sp) @@ -112,7 +112,7 @@ define i64 @test_floor_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz s0, .LBB1_2 @@ -201,7 +201,7 @@ define i64 @test_floor_ui64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call floor@plt +; RV32IFD-NEXT: call floor ; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI3_0)(a0) ; RV32IFD-NEXT: flt.d a0, fa5, fa0 @@ -209,7 +209,7 @@ define i64 @test_floor_ui64(double %x) nounwind { ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s1, a0 -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: and a1, s1, a1 @@ -236,7 +236,7 @@ define i64 @test_floor_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call floor@plt +; RV32IZFINXZDINX-NEXT: call floor ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) @@ -244,7 +244,7 @@ define i64 @test_floor_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a2 -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI3_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI3_0)(a2) @@ -320,12 +320,12 @@ define i64 @test_ceil_si64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: call ceil@plt +; RV32IFD-NEXT: call ceil ; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 ; RV32IFD-NEXT: beqz s0, .LBB5_2 @@ -369,7 +369,7 @@ define i64 @test_ceil_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call ceil@plt +; RV32IZFINXZDINX-NEXT: call ceil ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 8(sp) @@ -378,7 +378,7 @@ define i64 @test_ceil_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz s0, .LBB5_2 @@ -467,7 +467,7 @@ define i64 @test_ceil_ui64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call ceil@plt +; RV32IFD-NEXT: call ceil ; RV32IFD-NEXT: lui a0, %hi(.LCPI7_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI7_0)(a0) ; RV32IFD-NEXT: flt.d a0, fa5, fa0 @@ -475,7 +475,7 @@ define i64 @test_ceil_ui64(double %x) nounwind { ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s1, a0 -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: and a1, s1, a1 @@ -502,7 +502,7 @@ define i64 @test_ceil_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call ceil@plt +; RV32IZFINXZDINX-NEXT: call ceil ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) @@ -510,7 +510,7 @@ define i64 @test_ceil_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a2 -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI7_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI7_0)(a2) @@ -586,12 +586,12 @@ define i64 @test_trunc_si64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: call trunc@plt +; RV32IFD-NEXT: call trunc ; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 ; RV32IFD-NEXT: beqz s0, .LBB9_2 @@ -635,7 +635,7 @@ define i64 @test_trunc_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call trunc@plt +; RV32IZFINXZDINX-NEXT: call trunc ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 8(sp) @@ -644,7 +644,7 @@ define i64 @test_trunc_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI9_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz s0, .LBB9_2 @@ -733,7 +733,7 @@ define i64 @test_trunc_ui64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call trunc@plt +; RV32IFD-NEXT: call trunc ; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI11_0)(a0) ; RV32IFD-NEXT: flt.d a0, fa5, fa0 @@ -741,7 +741,7 @@ define i64 @test_trunc_ui64(double %x) nounwind { ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s1, a0 -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: and a1, s1, a1 @@ -768,7 +768,7 @@ define i64 @test_trunc_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call trunc@plt +; RV32IZFINXZDINX-NEXT: call trunc ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) @@ -776,7 +776,7 @@ define i64 @test_trunc_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a2 -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI11_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI11_0)(a2) @@ -852,12 +852,12 @@ define i64 @test_round_si64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: call round@plt +; RV32IFD-NEXT: call round ; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 ; RV32IFD-NEXT: beqz s0, .LBB13_2 @@ -901,7 +901,7 @@ define i64 @test_round_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call round@plt +; RV32IZFINXZDINX-NEXT: call round ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 8(sp) @@ -910,7 +910,7 @@ define i64 @test_round_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI13_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz s0, .LBB13_2 @@ -999,7 +999,7 @@ define i64 @test_round_ui64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call round@plt +; RV32IFD-NEXT: call round ; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI15_0)(a0) ; RV32IFD-NEXT: flt.d a0, fa5, fa0 @@ -1007,7 +1007,7 @@ define i64 @test_round_ui64(double %x) nounwind { ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s1, a0 -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: and a1, s1, a1 @@ -1034,7 +1034,7 @@ define i64 @test_round_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call round@plt +; RV32IZFINXZDINX-NEXT: call round ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) @@ -1042,7 +1042,7 @@ define i64 @test_round_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a2 -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI15_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI15_0)(a2) @@ -1118,12 +1118,12 @@ define i64 @test_roundeven_si64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: call roundeven@plt +; RV32IFD-NEXT: call roundeven ; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 ; RV32IFD-NEXT: beqz s0, .LBB17_2 @@ -1167,7 +1167,7 @@ define i64 @test_roundeven_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call roundeven@plt +; RV32IZFINXZDINX-NEXT: call roundeven ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 8(sp) @@ -1176,7 +1176,7 @@ define i64 @test_roundeven_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI17_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz s0, .LBB17_2 @@ -1265,7 +1265,7 @@ define i64 @test_roundeven_ui64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call roundeven@plt +; RV32IFD-NEXT: call roundeven ; RV32IFD-NEXT: lui a0, %hi(.LCPI19_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI19_0)(a0) ; RV32IFD-NEXT: flt.d a0, fa5, fa0 @@ -1273,7 +1273,7 @@ define i64 @test_roundeven_ui64(double %x) nounwind { ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s1, a0 -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: and a1, s1, a1 @@ -1300,7 +1300,7 @@ define i64 @test_roundeven_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call roundeven@plt +; RV32IZFINXZDINX-NEXT: call roundeven ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) @@ -1308,7 +1308,7 @@ define i64 @test_roundeven_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a2 -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI19_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI19_0)(a2) @@ -1384,12 +1384,12 @@ define i64 @test_rint_si64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: call rint@plt +; RV32IFD-NEXT: call rint ; RV32IFD-NEXT: lui a0, %hi(.LCPI21_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI21_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 ; RV32IFD-NEXT: beqz s0, .LBB21_2 @@ -1433,7 +1433,7 @@ define i64 @test_rint_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call rint@plt +; RV32IZFINXZDINX-NEXT: call rint ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s2, 8(sp) @@ -1442,7 +1442,7 @@ define i64 @test_rint_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI21_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz s0, .LBB21_2 @@ -1531,7 +1531,7 @@ define i64 @test_rint_ui64(double %x) nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call rint@plt +; RV32IFD-NEXT: call rint ; RV32IFD-NEXT: lui a0, %hi(.LCPI23_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI23_0)(a0) ; RV32IFD-NEXT: flt.d a0, fa5, fa0 @@ -1539,7 +1539,7 @@ define i64 @test_rint_ui64(double %x) nounwind { ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s1, a0 -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: and a1, s1, a1 @@ -1566,7 +1566,7 @@ define i64 @test_rint_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call rint@plt +; RV32IZFINXZDINX-NEXT: call rint ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) @@ -1574,7 +1574,7 @@ define i64 @test_rint_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a2 -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI23_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI23_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI23_0)(a2) diff --git a/llvm/test/CodeGen/RISCV/double-round-conv.ll b/llvm/test/CodeGen/RISCV/double-round-conv.ll index 6327afd881a5..094a4105de71 100644 --- a/llvm/test/CodeGen/RISCV/double-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/double-round-conv.ll @@ -106,8 +106,8 @@ define i64 @test_floor_si64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call floor@plt -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call floor +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -123,8 +123,8 @@ define i64 @test_floor_si64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call floor@plt -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call floor +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -236,8 +236,8 @@ define i64 @test_floor_ui64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call floor@plt -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call floor +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -253,8 +253,8 @@ define i64 @test_floor_ui64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call floor@plt -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call floor +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -366,8 +366,8 @@ define i64 @test_ceil_si64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call ceil@plt -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call ceil +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -383,8 +383,8 @@ define i64 @test_ceil_si64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call ceil@plt -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call ceil +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -496,8 +496,8 @@ define i64 @test_ceil_ui64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call ceil@plt -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call ceil +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -513,8 +513,8 @@ define i64 @test_ceil_ui64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call ceil@plt -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call ceil +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -626,8 +626,8 @@ define i64 @test_trunc_si64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call trunc@plt -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call trunc +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -643,8 +643,8 @@ define i64 @test_trunc_si64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call trunc@plt -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call trunc +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -756,8 +756,8 @@ define i64 @test_trunc_ui64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call trunc@plt -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call trunc +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -773,8 +773,8 @@ define i64 @test_trunc_ui64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call trunc@plt -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call trunc +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -886,8 +886,8 @@ define i64 @test_round_si64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call round@plt -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call round +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -903,8 +903,8 @@ define i64 @test_round_si64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call round@plt -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call round +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1016,8 +1016,8 @@ define i64 @test_round_ui64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call round@plt -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call round +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1033,8 +1033,8 @@ define i64 @test_round_ui64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call round@plt -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call round +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1146,8 +1146,8 @@ define i64 @test_roundeven_si64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call roundeven@plt -; RV32IFD-NEXT: call __fixdfdi@plt +; RV32IFD-NEXT: call roundeven +; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1163,8 +1163,8 @@ define i64 @test_roundeven_si64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call roundeven@plt -; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt +; RV32IZFINXZDINX-NEXT: call roundeven +; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1276,8 +1276,8 @@ define i64 @test_roundeven_ui64(double %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call roundeven@plt -; RV32IFD-NEXT: call __fixunsdfdi@plt +; RV32IFD-NEXT: call roundeven +; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1293,8 +1293,8 @@ define i64 @test_roundeven_ui64(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call roundeven@plt -; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt +; RV32IZFINXZDINX-NEXT: call roundeven +; RV32IZFINXZDINX-NEXT: call __fixunsdfdi ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1311,7 +1311,7 @@ define i64 @test_roundeven_ui64(double %x) { define double @test_floor_double(double %x) { ; RV32IFD-LABEL: test_floor_double: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail floor@plt +; RV32IFD-NEXT: tail floor ; ; RV64IFD-LABEL: test_floor_double: ; RV64IFD: # %bb.0: @@ -1333,7 +1333,7 @@ define double @test_floor_double(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call floor@plt +; RV32IZFINXZDINX-NEXT: call floor ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1358,7 +1358,7 @@ define double @test_floor_double(double %x) { define double @test_ceil_double(double %x) { ; RV32IFD-LABEL: test_ceil_double: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail ceil@plt +; RV32IFD-NEXT: tail ceil ; ; RV64IFD-LABEL: test_ceil_double: ; RV64IFD: # %bb.0: @@ -1380,7 +1380,7 @@ define double @test_ceil_double(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call ceil@plt +; RV32IZFINXZDINX-NEXT: call ceil ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1405,7 +1405,7 @@ define double @test_ceil_double(double %x) { define double @test_trunc_double(double %x) { ; RV32IFD-LABEL: test_trunc_double: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail trunc@plt +; RV32IFD-NEXT: tail trunc ; ; RV64IFD-LABEL: test_trunc_double: ; RV64IFD: # %bb.0: @@ -1427,7 +1427,7 @@ define double @test_trunc_double(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call trunc@plt +; RV32IZFINXZDINX-NEXT: call trunc ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1452,7 +1452,7 @@ define double @test_trunc_double(double %x) { define double @test_round_double(double %x) { ; RV32IFD-LABEL: test_round_double: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail round@plt +; RV32IFD-NEXT: tail round ; ; RV64IFD-LABEL: test_round_double: ; RV64IFD: # %bb.0: @@ -1474,7 +1474,7 @@ define double @test_round_double(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call round@plt +; RV32IZFINXZDINX-NEXT: call round ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1499,7 +1499,7 @@ define double @test_round_double(double %x) { define double @test_roundeven_double(double %x) { ; RV32IFD-LABEL: test_roundeven_double: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: tail roundeven@plt +; RV32IFD-NEXT: tail roundeven ; ; RV64IFD-LABEL: test_roundeven_double: ; RV64IFD: # %bb.0: @@ -1521,7 +1521,7 @@ define double @test_roundeven_double(double %x) { ; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINXZDINX-NEXT: call roundeven@plt +; RV32IZFINXZDINX-NEXT: call roundeven ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll index 2fec986f0ba5..aa88a365431a 100644 --- a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll +++ b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll @@ -23,7 +23,7 @@ define double @func(double %d, i32 %n) nounwind { ; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: call func@plt +; RV32IFD-NEXT: call func ; RV32IFD-NEXT: sw a0, 16(sp) ; RV32IFD-NEXT: sw a1, 20(sp) ; RV32IFD-NEXT: fld fa5, 16(sp) @@ -48,7 +48,7 @@ define double @func(double %d, i32 %n) nounwind { ; RV64IFD-NEXT: addiw a1, a1, -1 ; RV64IFD-NEXT: fmv.x.d a0, fa5 ; RV64IFD-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call func@plt +; RV64IFD-NEXT: call func ; RV64IFD-NEXT: fmv.d.x fa5, a0 ; RV64IFD-NEXT: fld fa4, 0(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fadd.d fa5, fa5, fa4 @@ -77,7 +77,7 @@ define double @func(double %d, i32 %n) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp) -; RV32IZFINXZDINX-NEXT: call func@plt +; RV32IZFINXZDINX-NEXT: call func ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp) @@ -108,7 +108,7 @@ define double @func(double %d, i32 %n) nounwind { ; RV64IZFINXZDINX-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: addiw a1, a1, -1 ; RV64IZFINXZDINX-NEXT: mv s0, a0 -; RV64IZFINXZDINX-NEXT: call func@plt +; RV64IZFINXZDINX-NEXT: call func ; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, s0 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll b/llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll index 12606aad215c..c4d932acbcc8 100644 --- a/llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll +++ b/llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll @@ -10,7 +10,7 @@ define void @dwarf() { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: addi a0, sp, 16 -; RV32-NEXT: call foo@plt +; RV32-NEXT: call foo ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -22,7 +22,7 @@ define void @dwarf() { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: addi a0, sp, 16 -; RV64-NEXT: call foo@plt +; RV64-NEXT: call foo ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/emutls.ll b/llvm/test/CodeGen/RISCV/emutls.ll index 9ce985ba4242..4f6e9935b9aa 100644 --- a/llvm/test/CodeGen/RISCV/emutls.ll +++ b/llvm/test/CodeGen/RISCV/emutls.ll @@ -16,7 +16,7 @@ define ptr @get_external_x() nounwind { ; RV32-NEXT: .Lpcrel_hi0: ; RV32-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.external_x) ; RV32-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0) -; RV32-NEXT: call __emutls_get_address@plt +; RV32-NEXT: call __emutls_get_address ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -28,7 +28,7 @@ define ptr @get_external_x() nounwind { ; RV64-NEXT: .Lpcrel_hi0: ; RV64-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.external_x) ; RV64-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) -; RV64-NEXT: call __emutls_get_address@plt +; RV64-NEXT: call __emutls_get_address ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -44,7 +44,7 @@ define ptr @get_y() nounwind { ; RV32-NEXT: .Lpcrel_hi1: ; RV32-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.y) ; RV32-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi1)(a0) -; RV32-NEXT: call __emutls_get_address@plt +; RV32-NEXT: call __emutls_get_address ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -56,7 +56,7 @@ define ptr @get_y() nounwind { ; RV64-NEXT: .Lpcrel_hi1: ; RV64-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.y) ; RV64-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0) -; RV64-NEXT: call __emutls_get_address@plt +; RV64-NEXT: call __emutls_get_address ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -72,7 +72,7 @@ define ptr @get_internal_z() nounwind { ; RV32-NEXT: .Lpcrel_hi2: ; RV32-NEXT: auipc a0, %pcrel_hi(__emutls_v.internal_z) ; RV32-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2) -; RV32-NEXT: call __emutls_get_address@plt +; RV32-NEXT: call __emutls_get_address ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -84,7 +84,7 @@ define ptr @get_internal_z() nounwind { ; RV64-NEXT: .Lpcrel_hi2: ; RV64-NEXT: auipc a0, %pcrel_hi(__emutls_v.internal_z) ; RV64-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2) -; RV64-NEXT: call __emutls_get_address@plt +; RV64-NEXT: call __emutls_get_address ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll index 6c98525d9765..067690333fdb 100644 --- a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll +++ b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll @@ -28,13 +28,13 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 { ; RV32I-NEXT: # %bb.1: # %bb2 ; RV32I-NEXT: .Ltmp0: ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call bar@plt +; RV32I-NEXT: call bar ; RV32I-NEXT: .Ltmp1: ; RV32I-NEXT: j .LBB0_3 ; RV32I-NEXT: .LBB0_2: # %bb1 ; RV32I-NEXT: .Ltmp2: ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: .Ltmp3: ; RV32I-NEXT: .LBB0_3: # %end2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -48,7 +48,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call callee ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call _Unwind_Resume@plt +; RV32I-NEXT: call _Unwind_Resume ; ; RV64I-LABEL: caller: ; RV64I: # %bb.0: # %entry @@ -65,13 +65,13 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 { ; RV64I-NEXT: # %bb.1: # %bb2 ; RV64I-NEXT: .Ltmp0: ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call bar@plt +; RV64I-NEXT: call bar ; RV64I-NEXT: .Ltmp1: ; RV64I-NEXT: j .LBB0_3 ; RV64I-NEXT: .LBB0_2: # %bb1 ; RV64I-NEXT: .Ltmp2: ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call foo@plt +; RV64I-NEXT: call foo ; RV64I-NEXT: .Ltmp3: ; RV64I-NEXT: .LBB0_3: # %end2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -85,7 +85,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call callee ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call _Unwind_Resume@plt +; RV64I-NEXT: call _Unwind_Resume entry: %0 = icmp eq ptr %p, null br i1 %0, label %bb1, label %bb2 diff --git a/llvm/test/CodeGen/RISCV/fastcc-float.ll b/llvm/test/CodeGen/RISCV/fastcc-float.ll index c5daa612c671..488c97d5a450 100644 --- a/llvm/test/CodeGen/RISCV/fastcc-float.ll +++ b/llvm/test/CodeGen/RISCV/fastcc-float.ll @@ -62,7 +62,7 @@ define float @caller(<32 x float> %A) nounwind { ; CHECK-NEXT: fsw fs2, 8(sp) ; CHECK-NEXT: fsw fs1, 4(sp) ; CHECK-NEXT: fsw fs0, 0(sp) -; CHECK-NEXT: call callee@plt +; CHECK-NEXT: call callee ; CHECK-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/fastcc-int.ll b/llvm/test/CodeGen/RISCV/fastcc-int.ll index 0df0ce183c01..e4c41a1aa890 100644 --- a/llvm/test/CodeGen/RISCV/fastcc-int.ll +++ b/llvm/test/CodeGen/RISCV/fastcc-int.ll @@ -44,7 +44,7 @@ define i32 @caller(<16 x i32> %A) nounwind { ; RV32-NEXT: sw s0, 4(sp) ; RV32-NEXT: sw t1, 0(sp) ; RV32-NEXT: mv a0, t0 -; RV32-NEXT: call callee@plt +; RV32-NEXT: call callee ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 32 @@ -75,7 +75,7 @@ define i32 @caller(<16 x i32> %A) nounwind { ; RV64-NEXT: sd s0, 8(sp) ; RV64-NEXT: sd t1, 0(sp) ; RV64-NEXT: mv a0, t0 -; RV64-NEXT: call callee@plt +; RV64-NEXT: call callee ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 48 diff --git a/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll b/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll index e667325db3aa..fb0b34cf796b 100644 --- a/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll +++ b/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll @@ -321,7 +321,7 @@ define half @caller_half_32(<32 x half> %A) nounwind { ; ZHINX32-NEXT: lw t3, 52(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw t4, 48(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw t5, 44(sp) # 4-byte Folded Reload -; ZHINX32-NEXT: call callee_half_32@plt +; ZHINX32-NEXT: call callee_half_32 ; ZHINX32-NEXT: lw ra, 108(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw s0, 104(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw s1, 100(sp) # 4-byte Folded Reload @@ -405,7 +405,7 @@ define half @caller_half_32(<32 x half> %A) nounwind { ; ZHINX64-NEXT: ld t3, 56(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld t4, 48(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld t5, 40(sp) # 8-byte Folded Reload -; ZHINX64-NEXT: call callee_half_32@plt +; ZHINX64-NEXT: call callee_half_32 ; ZHINX64-NEXT: ld ra, 168(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld s0, 160(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld s1, 152(sp) # 8-byte Folded Reload @@ -498,7 +498,7 @@ define half @caller_half_32(<32 x half> %A) nounwind { ; ZFINX32-NEXT: lw a2, 84(sp) # 4-byte Folded Reload ; ZFINX32-NEXT: lw a3, 80(sp) # 4-byte Folded Reload ; ZFINX32-NEXT: lw a4, 76(sp) # 4-byte Folded Reload -; ZFINX32-NEXT: call callee_half_32@plt +; ZFINX32-NEXT: call callee_half_32 ; ZFINX32-NEXT: lui a1, 1048560 ; ZFINX32-NEXT: or a0, a0, a1 ; ZFINX32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload @@ -593,7 +593,7 @@ define half @caller_half_32(<32 x half> %A) nounwind { ; ZFINX64-NEXT: ld a2, 168(sp) # 8-byte Folded Reload ; ZFINX64-NEXT: ld a3, 160(sp) # 8-byte Folded Reload ; ZFINX64-NEXT: ld a4, 152(sp) # 8-byte Folded Reload -; ZFINX64-NEXT: call callee_half_32@plt +; ZFINX64-NEXT: call callee_half_32 ; ZFINX64-NEXT: lui a1, 1048560 ; ZFINX64-NEXT: or a0, a0, a1 ; ZFINX64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload @@ -688,7 +688,7 @@ define half @caller_half_32(<32 x half> %A) nounwind { ; ZDINX32-NEXT: lw a2, 84(sp) # 4-byte Folded Reload ; ZDINX32-NEXT: lw a3, 80(sp) # 4-byte Folded Reload ; ZDINX32-NEXT: lw a4, 76(sp) # 4-byte Folded Reload -; ZDINX32-NEXT: call callee_half_32@plt +; ZDINX32-NEXT: call callee_half_32 ; ZDINX32-NEXT: lui a1, 1048560 ; ZDINX32-NEXT: or a0, a0, a1 ; ZDINX32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload @@ -783,7 +783,7 @@ define half @caller_half_32(<32 x half> %A) nounwind { ; ZDINX64-NEXT: ld a2, 168(sp) # 8-byte Folded Reload ; ZDINX64-NEXT: ld a3, 160(sp) # 8-byte Folded Reload ; ZDINX64-NEXT: ld a4, 152(sp) # 8-byte Folded Reload -; ZDINX64-NEXT: call callee_half_32@plt +; ZDINX64-NEXT: call callee_half_32 ; ZDINX64-NEXT: lui a1, 1048560 ; ZDINX64-NEXT: or a0, a0, a1 ; ZDINX64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload @@ -901,7 +901,7 @@ define float @caller_float_32(<32 x float> %A) nounwind { ; ZHINX32-NEXT: lw t3, 84(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw t4, 80(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw t5, 76(sp) # 4-byte Folded Reload -; ZHINX32-NEXT: call callee_float_32@plt +; ZHINX32-NEXT: call callee_float_32 ; ZHINX32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; ZHINX32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload @@ -985,7 +985,7 @@ define float @caller_float_32(<32 x float> %A) nounwind { ; ZHINX64-NEXT: ld t3, 104(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld t4, 96(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld t5, 88(sp) # 8-byte Folded Reload -; ZHINX64-NEXT: call callee_float_32@plt +; ZHINX64-NEXT: call callee_float_32 ; ZHINX64-NEXT: ld ra, 216(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld s0, 208(sp) # 8-byte Folded Reload ; ZHINX64-NEXT: ld s1, 200(sp) # 8-byte Folded Reload @@ -1069,7 +1069,7 @@ define float @caller_float_32(<32 x float> %A) nounwind { ; ZFINX32-NEXT: lw t3, 84(sp) # 4-byte Folded Reload ; ZFINX32-NEXT: lw t4, 80(sp) # 4-byte Folded Reload ; ZFINX32-NEXT: lw t5, 76(sp) # 4-byte Folded Reload -; ZFINX32-NEXT: call callee_float_32@plt +; ZFINX32-NEXT: call callee_float_32 ; ZFINX32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; ZFINX32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; ZFINX32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload @@ -1153,7 +1153,7 @@ define float @caller_float_32(<32 x float> %A) nounwind { ; ZFINX64-NEXT: ld t3, 104(sp) # 8-byte Folded Reload ; ZFINX64-NEXT: ld t4, 96(sp) # 8-byte Folded Reload ; ZFINX64-NEXT: ld t5, 88(sp) # 8-byte Folded Reload -; ZFINX64-NEXT: call callee_float_32@plt +; ZFINX64-NEXT: call callee_float_32 ; ZFINX64-NEXT: ld ra, 216(sp) # 8-byte Folded Reload ; ZFINX64-NEXT: ld s0, 208(sp) # 8-byte Folded Reload ; ZFINX64-NEXT: ld s1, 200(sp) # 8-byte Folded Reload @@ -1237,7 +1237,7 @@ define float @caller_float_32(<32 x float> %A) nounwind { ; ZDINX32-NEXT: lw t3, 84(sp) # 4-byte Folded Reload ; ZDINX32-NEXT: lw t4, 80(sp) # 4-byte Folded Reload ; ZDINX32-NEXT: lw t5, 76(sp) # 4-byte Folded Reload -; ZDINX32-NEXT: call callee_float_32@plt +; ZDINX32-NEXT: call callee_float_32 ; ZDINX32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; ZDINX32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; ZDINX32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload @@ -1321,7 +1321,7 @@ define float @caller_float_32(<32 x float> %A) nounwind { ; ZDINX64-NEXT: ld t3, 104(sp) # 8-byte Folded Reload ; ZDINX64-NEXT: ld t4, 96(sp) # 8-byte Folded Reload ; ZDINX64-NEXT: ld t5, 88(sp) # 8-byte Folded Reload -; ZDINX64-NEXT: call callee_float_32@plt +; ZDINX64-NEXT: call callee_float_32 ; ZDINX64-NEXT: ld ra, 216(sp) # 8-byte Folded Reload ; ZDINX64-NEXT: ld s0, 208(sp) # 8-byte Folded Reload ; ZDINX64-NEXT: ld s1, 200(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/fli-licm.ll b/llvm/test/CodeGen/RISCV/fli-licm.ll index 4962a146362d..ba6b33c4f0a4 100644 --- a/llvm/test/CodeGen/RISCV/fli-licm.ll +++ b/llvm/test/CodeGen/RISCV/fli-licm.ll @@ -22,7 +22,7 @@ define void @process_nodes(ptr %0) nounwind { ; RV32-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NEXT: fli.s fa0, 1.0 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call do_it@plt +; RV32-NEXT: call do_it ; RV32-NEXT: lw s0, 0(s0) ; RV32-NEXT: bnez s0, .LBB0_2 ; RV32-NEXT: # %bb.3: @@ -44,7 +44,7 @@ define void @process_nodes(ptr %0) nounwind { ; RV64-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NEXT: fli.s fa0, 1.0 ; RV64-NEXT: mv a0, s0 -; RV64-NEXT: call do_it@plt +; RV64-NEXT: call do_it ; RV64-NEXT: ld s0, 0(s0) ; RV64-NEXT: bnez s0, .LBB0_2 ; RV64-NEXT: # %bb.3: diff --git a/llvm/test/CodeGen/RISCV/float-arith-strict.ll b/llvm/test/CodeGen/RISCV/float-arith-strict.ll index 0252c8ca0f72..90ce034eafd3 100644 --- a/llvm/test/CodeGen/RISCV/float-arith-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-arith-strict.ll @@ -26,7 +26,7 @@ define float @fadd_s(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -35,7 +35,7 @@ define float @fadd_s(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -59,7 +59,7 @@ define float @fsub_s(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __subsf3@plt +; RV32I-NEXT: call __subsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -68,7 +68,7 @@ define float @fsub_s(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __subsf3@plt +; RV64I-NEXT: call __subsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -92,7 +92,7 @@ define float @fmul_s(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -101,7 +101,7 @@ define float @fmul_s(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -125,7 +125,7 @@ define float @fdiv_s(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __divsf3@plt +; RV32I-NEXT: call __divsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -134,7 +134,7 @@ define float @fdiv_s(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __divsf3@plt +; RV64I-NEXT: call __divsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -158,7 +158,7 @@ define float @fsqrt_s(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrtf@plt +; RV32I-NEXT: call sqrtf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -167,7 +167,7 @@ define float @fsqrt_s(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrtf@plt +; RV64I-NEXT: call sqrtf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -186,7 +186,7 @@ define float @fmin_s(float %a, float %b) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call fminf@plt +; RV32IF-NEXT: call fminf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -195,7 +195,7 @@ define float @fmin_s(float %a, float %b) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call fminf@plt +; RV64IF-NEXT: call fminf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -204,7 +204,7 @@ define float @fmin_s(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fminf@plt +; RV32I-NEXT: call fminf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -213,7 +213,7 @@ define float @fmin_s(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fminf@plt +; RV64I-NEXT: call fminf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -222,7 +222,7 @@ define float @fmin_s(float %a, float %b) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call fminf@plt +; RV32IZFINX-NEXT: call fminf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -231,7 +231,7 @@ define float @fmin_s(float %a, float %b) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call fminf@plt +; RV64IZFINX-NEXT: call fminf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -245,7 +245,7 @@ define float @fmax_s(float %a, float %b) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call fmaxf@plt +; RV32IF-NEXT: call fmaxf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -254,7 +254,7 @@ define float @fmax_s(float %a, float %b) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call fmaxf@plt +; RV64IF-NEXT: call fmaxf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -263,7 +263,7 @@ define float @fmax_s(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaxf@plt +; RV32I-NEXT: call fmaxf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -272,7 +272,7 @@ define float @fmax_s(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaxf@plt +; RV64I-NEXT: call fmaxf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -281,7 +281,7 @@ define float @fmax_s(float %a, float %b) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call fmaxf@plt +; RV32IZFINX-NEXT: call fmaxf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -290,7 +290,7 @@ define float @fmax_s(float %a, float %b) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call fmaxf@plt +; RV64IZFINX-NEXT: call fmaxf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -309,7 +309,7 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -318,7 +318,7 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -350,12 +350,12 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -372,12 +372,12 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -414,17 +414,17 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp { ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, s2, a2 ; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -442,17 +442,17 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -494,16 +494,16 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, s2, a2 ; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -522,16 +522,16 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -570,12 +570,12 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp { ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a2, s0 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -591,12 +591,12 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -632,12 +632,12 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a1, a0, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a2, s0 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -654,12 +654,12 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a1, a0, a1 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll index 5497827a3f2f..7a7ebe651c08 100644 --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -32,7 +32,7 @@ define float @fadd_s(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -41,7 +41,7 @@ define float @fadd_s(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -64,7 +64,7 @@ define float @fsub_s(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __subsf3@plt +; RV32I-NEXT: call __subsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -73,7 +73,7 @@ define float @fsub_s(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __subsf3@plt +; RV64I-NEXT: call __subsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -96,7 +96,7 @@ define float @fmul_s(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -105,7 +105,7 @@ define float @fmul_s(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -128,7 +128,7 @@ define float @fdiv_s(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __divsf3@plt +; RV32I-NEXT: call __divsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -137,7 +137,7 @@ define float @fdiv_s(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __divsf3@plt +; RV64I-NEXT: call __divsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -162,7 +162,7 @@ define float @fsqrt_s(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrtf@plt +; RV32I-NEXT: call sqrtf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -171,7 +171,7 @@ define float @fsqrt_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrtf@plt +; RV64I-NEXT: call sqrtf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -233,10 +233,10 @@ define i32 @fneg_s(float %a, float %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a1, a0, a1 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -247,10 +247,10 @@ define i32 @fneg_s(float %a, float %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a1, a0, a1 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -281,7 +281,7 @@ define float @fsgnjn_s(float %a, float %b) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: and a0, a0, a1 @@ -299,7 +299,7 @@ define float @fsgnjn_s(float %a, float %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: and a0, a0, a1 @@ -337,11 +337,11 @@ define float @fabs_s(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -350,11 +350,11 @@ define float @fabs_s(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: slli a0, a0, 33 ; RV64I-NEXT: srli a0, a0, 33 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -381,7 +381,7 @@ define float @fmin_s(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fminf@plt +; RV32I-NEXT: call fminf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -390,7 +390,7 @@ define float @fmin_s(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fminf@plt +; RV64I-NEXT: call fminf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -415,7 +415,7 @@ define float @fmax_s(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaxf@plt +; RV32I-NEXT: call fmaxf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -424,7 +424,7 @@ define float @fmax_s(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaxf@plt +; RV64I-NEXT: call fmaxf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -449,7 +449,7 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -458,7 +458,7 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -490,12 +490,12 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -512,12 +512,12 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -555,17 +555,17 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, s2, a2 ; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -583,17 +583,17 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -635,16 +635,16 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: xor a1, s2, a2 ; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -663,16 +663,16 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: xor a1, s2, a2 ; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -717,7 +717,7 @@ define float @fnmadd_s_3(float %a, float %b, float %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -728,7 +728,7 @@ define float @fnmadd_s_3(float %a, float %b, float %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -766,7 +766,7 @@ define float @fnmadd_nsz(float %a, float %b, float %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -777,7 +777,7 @@ define float @fnmadd_nsz(float %a, float %b, float %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -811,12 +811,12 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a2, s0 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -832,12 +832,12 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -873,12 +873,12 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a1, a0, a1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a2, s0 -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -895,12 +895,12 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a1, a0, a1 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -929,9 +929,9 @@ define float @fmadd_s_contract(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2 -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -943,9 +943,9 @@ define float @fmadd_s_contract(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -980,13 +980,13 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: mv a1, s2 -; RV32I-NEXT: call __subsf3@plt +; RV32I-NEXT: call __subsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1005,13 +1005,13 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: mv a1, s2 -; RV64I-NEXT: call __subsf3@plt +; RV64I-NEXT: call __subsf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1052,23 +1052,23 @@ define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __subsf3@plt +; RV32I-NEXT: call __subsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1086,23 +1086,23 @@ define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __subsf3@plt +; RV64I-NEXT: call __subsf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1144,17 +1144,17 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __subsf3@plt +; RV32I-NEXT: call __subsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1172,17 +1172,17 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __subsf3@plt +; RV64I-NEXT: call __subsf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll index 5c50381ad170..6aa6dedba548 100644 --- a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll @@ -89,13 +89,13 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind { ; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32F-NEXT: mv s0, a1 ; RV32F-NEXT: mv s1, a0 -; RV32F-NEXT: call __adddf3@plt +; RV32F-NEXT: call __adddf3 ; RV32F-NEXT: mv a2, a0 ; RV32F-NEXT: slli a1, a1, 1 ; RV32F-NEXT: srli a3, a1, 1 ; RV32F-NEXT: mv a0, s1 ; RV32F-NEXT: mv a1, s0 -; RV32F-NEXT: call __adddf3@plt +; RV32F-NEXT: call __adddf3 ; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -110,13 +110,13 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind { ; RV32ZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32ZFINX-NEXT: mv s0, a1 ; RV32ZFINX-NEXT: mv s1, a0 -; RV32ZFINX-NEXT: call __adddf3@plt +; RV32ZFINX-NEXT: call __adddf3 ; RV32ZFINX-NEXT: mv a2, a0 ; RV32ZFINX-NEXT: slli a1, a1, 1 ; RV32ZFINX-NEXT: srli a3, a1, 1 ; RV32ZFINX-NEXT: mv a0, s1 ; RV32ZFINX-NEXT: mv a1, s0 -; RV32ZFINX-NEXT: call __adddf3@plt +; RV32ZFINX-NEXT: call __adddf3 ; RV32ZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32ZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -147,11 +147,11 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind { ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64F-NEXT: mv s0, a0 -; RV64F-NEXT: call __adddf3@plt +; RV64F-NEXT: call __adddf3 ; RV64F-NEXT: slli a0, a0, 1 ; RV64F-NEXT: srli a1, a0, 1 ; RV64F-NEXT: mv a0, s0 -; RV64F-NEXT: call __adddf3@plt +; RV64F-NEXT: call __adddf3 ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64F-NEXT: addi sp, sp, 16 @@ -163,11 +163,11 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind { ; RV64ZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ZFINX-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64ZFINX-NEXT: mv s0, a0 -; RV64ZFINX-NEXT: call __adddf3@plt +; RV64ZFINX-NEXT: call __adddf3 ; RV64ZFINX-NEXT: slli a0, a0, 1 ; RV64ZFINX-NEXT: srli a1, a0, 1 ; RV64ZFINX-NEXT: mv a0, s0 -; RV64ZFINX-NEXT: call __adddf3@plt +; RV64ZFINX-NEXT: call __adddf3 ; RV64ZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ZFINX-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64ZFINX-NEXT: addi sp, sp, 16 @@ -262,13 +262,13 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind { ; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32F-NEXT: mv s0, a1 ; RV32F-NEXT: mv s1, a0 -; RV32F-NEXT: call __muldf3@plt +; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: mv a2, a0 ; RV32F-NEXT: lui a3, 524288 ; RV32F-NEXT: xor a3, a1, a3 ; RV32F-NEXT: mv a0, s1 ; RV32F-NEXT: mv a1, s0 -; RV32F-NEXT: call __muldf3@plt +; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -283,13 +283,13 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind { ; RV32ZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32ZFINX-NEXT: mv s0, a1 ; RV32ZFINX-NEXT: mv s1, a0 -; RV32ZFINX-NEXT: call __muldf3@plt +; RV32ZFINX-NEXT: call __muldf3 ; RV32ZFINX-NEXT: mv a2, a0 ; RV32ZFINX-NEXT: lui a3, 524288 ; RV32ZFINX-NEXT: xor a3, a1, a3 ; RV32ZFINX-NEXT: mv a0, s1 ; RV32ZFINX-NEXT: mv a1, s0 -; RV32ZFINX-NEXT: call __muldf3@plt +; RV32ZFINX-NEXT: call __muldf3 ; RV32ZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32ZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -320,12 +320,12 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind { ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64F-NEXT: mv s0, a0 -; RV64F-NEXT: call __muldf3@plt +; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: li a1, -1 ; RV64F-NEXT: slli a1, a1, 63 ; RV64F-NEXT: xor a1, a0, a1 ; RV64F-NEXT: mv a0, s0 -; RV64F-NEXT: call __muldf3@plt +; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64F-NEXT: addi sp, sp, 16 @@ -337,12 +337,12 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind { ; RV64ZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ZFINX-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64ZFINX-NEXT: mv s0, a0 -; RV64ZFINX-NEXT: call __muldf3@plt +; RV64ZFINX-NEXT: call __muldf3 ; RV64ZFINX-NEXT: li a1, -1 ; RV64ZFINX-NEXT: slli a1, a1, 63 ; RV64ZFINX-NEXT: xor a1, a0, a1 ; RV64ZFINX-NEXT: mv a0, s0 -; RV64ZFINX-NEXT: call __muldf3@plt +; RV64ZFINX-NEXT: call __muldf3 ; RV64ZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ZFINX-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64ZFINX-NEXT: addi sp, sp, 16 @@ -442,13 +442,13 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind { ; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32F-NEXT: mv s0, a1 ; RV32F-NEXT: mv s1, a0 -; RV32F-NEXT: call __muldf3@plt +; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: mv a2, a0 ; RV32F-NEXT: lui a3, 524288 ; RV32F-NEXT: or a3, a1, a3 ; RV32F-NEXT: mv a0, s1 ; RV32F-NEXT: mv a1, s0 -; RV32F-NEXT: call __muldf3@plt +; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -463,13 +463,13 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind { ; RV32ZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32ZFINX-NEXT: mv s0, a1 ; RV32ZFINX-NEXT: mv s1, a0 -; RV32ZFINX-NEXT: call __muldf3@plt +; RV32ZFINX-NEXT: call __muldf3 ; RV32ZFINX-NEXT: mv a2, a0 ; RV32ZFINX-NEXT: lui a3, 524288 ; RV32ZFINX-NEXT: or a3, a1, a3 ; RV32ZFINX-NEXT: mv a0, s1 ; RV32ZFINX-NEXT: mv a1, s0 -; RV32ZFINX-NEXT: call __muldf3@plt +; RV32ZFINX-NEXT: call __muldf3 ; RV32ZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32ZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -501,12 +501,12 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind { ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64F-NEXT: mv s0, a0 -; RV64F-NEXT: call __muldf3@plt +; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: li a1, -1 ; RV64F-NEXT: slli a1, a1, 63 ; RV64F-NEXT: or a1, a0, a1 ; RV64F-NEXT: mv a0, s0 -; RV64F-NEXT: call __muldf3@plt +; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64F-NEXT: addi sp, sp, 16 @@ -518,12 +518,12 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind { ; RV64ZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ZFINX-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64ZFINX-NEXT: mv s0, a0 -; RV64ZFINX-NEXT: call __muldf3@plt +; RV64ZFINX-NEXT: call __muldf3 ; RV64ZFINX-NEXT: li a1, -1 ; RV64ZFINX-NEXT: slli a1, a1, 63 ; RV64ZFINX-NEXT: or a1, a0, a1 ; RV64ZFINX-NEXT: mv a0, s0 -; RV64ZFINX-NEXT: call __muldf3@plt +; RV64ZFINX-NEXT: call __muldf3 ; RV64ZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ZFINX-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64ZFINX-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll index 71b0f77015b5..35caa627b57b 100644 --- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -22,7 +22,7 @@ define void @br_fcmp_false(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB0_2: # %if.else ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_false: ; RV64IF: # %bb.0: @@ -33,7 +33,7 @@ define void @br_fcmp_false(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB0_2: # %if.else ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_false: ; RV32IZFINX: # %bb.0: @@ -44,7 +44,7 @@ define void @br_fcmp_false(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB0_2: # %if.else ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_false: ; RV64IZFINX: # %bb.0: @@ -55,7 +55,7 @@ define void @br_fcmp_false(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB0_2: # %if.else ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp false float %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -75,7 +75,7 @@ define void @br_fcmp_oeq(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB1_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_oeq: ; RV64IF: # %bb.0: @@ -86,7 +86,7 @@ define void @br_fcmp_oeq(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB1_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_oeq: ; RV32IZFINX: # %bb.0: @@ -97,7 +97,7 @@ define void @br_fcmp_oeq(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB1_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_oeq: ; RV64IZFINX: # %bb.0: @@ -108,7 +108,7 @@ define void @br_fcmp_oeq(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB1_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -131,7 +131,7 @@ define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB2_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_oeq_alt: ; RV64IF: # %bb.0: @@ -142,7 +142,7 @@ define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB2_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_oeq_alt: ; RV32IZFINX: # %bb.0: @@ -153,7 +153,7 @@ define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB2_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_oeq_alt: ; RV64IZFINX: # %bb.0: @@ -164,7 +164,7 @@ define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB2_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -184,7 +184,7 @@ define void @br_fcmp_ogt(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB3_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_ogt: ; RV64IF: # %bb.0: @@ -195,7 +195,7 @@ define void @br_fcmp_ogt(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB3_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_ogt: ; RV32IZFINX: # %bb.0: @@ -206,7 +206,7 @@ define void @br_fcmp_ogt(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB3_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_ogt: ; RV64IZFINX: # %bb.0: @@ -217,7 +217,7 @@ define void @br_fcmp_ogt(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB3_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp ogt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -237,7 +237,7 @@ define void @br_fcmp_oge(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB4_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_oge: ; RV64IF: # %bb.0: @@ -248,7 +248,7 @@ define void @br_fcmp_oge(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB4_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_oge: ; RV32IZFINX: # %bb.0: @@ -259,7 +259,7 @@ define void @br_fcmp_oge(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB4_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_oge: ; RV64IZFINX: # %bb.0: @@ -270,7 +270,7 @@ define void @br_fcmp_oge(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB4_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp oge float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -290,7 +290,7 @@ define void @br_fcmp_olt(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB5_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_olt: ; RV64IF: # %bb.0: @@ -301,7 +301,7 @@ define void @br_fcmp_olt(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB5_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_olt: ; RV32IZFINX: # %bb.0: @@ -312,7 +312,7 @@ define void @br_fcmp_olt(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB5_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_olt: ; RV64IZFINX: # %bb.0: @@ -323,7 +323,7 @@ define void @br_fcmp_olt(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB5_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp olt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -343,7 +343,7 @@ define void @br_fcmp_ole(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB6_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_ole: ; RV64IF: # %bb.0: @@ -354,7 +354,7 @@ define void @br_fcmp_ole(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB6_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_ole: ; RV32IZFINX: # %bb.0: @@ -365,7 +365,7 @@ define void @br_fcmp_ole(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB6_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_ole: ; RV64IZFINX: # %bb.0: @@ -376,7 +376,7 @@ define void @br_fcmp_ole(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB6_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp ole float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -398,7 +398,7 @@ define void @br_fcmp_one(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB7_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_one: ; RV64IF: # %bb.0: @@ -411,7 +411,7 @@ define void @br_fcmp_one(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB7_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_one: ; RV32IZFINX: # %bb.0: @@ -424,7 +424,7 @@ define void @br_fcmp_one(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB7_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_one: ; RV64IZFINX: # %bb.0: @@ -437,7 +437,7 @@ define void @br_fcmp_one(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB7_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp one float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -459,7 +459,7 @@ define void @br_fcmp_ord(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB8_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_ord: ; RV64IF: # %bb.0: @@ -472,7 +472,7 @@ define void @br_fcmp_ord(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB8_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_ord: ; RV32IZFINX: # %bb.0: @@ -485,7 +485,7 @@ define void @br_fcmp_ord(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB8_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_ord: ; RV64IZFINX: # %bb.0: @@ -498,7 +498,7 @@ define void @br_fcmp_ord(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB8_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp ord float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -520,7 +520,7 @@ define void @br_fcmp_ueq(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB9_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_ueq: ; RV64IF: # %bb.0: @@ -533,7 +533,7 @@ define void @br_fcmp_ueq(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB9_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_ueq: ; RV32IZFINX: # %bb.0: @@ -546,7 +546,7 @@ define void @br_fcmp_ueq(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB9_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_ueq: ; RV64IZFINX: # %bb.0: @@ -559,7 +559,7 @@ define void @br_fcmp_ueq(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB9_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp ueq float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -579,7 +579,7 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB10_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_ugt: ; RV64IF: # %bb.0: @@ -590,7 +590,7 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB10_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_ugt: ; RV32IZFINX: # %bb.0: @@ -601,7 +601,7 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB10_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_ugt: ; RV64IZFINX: # %bb.0: @@ -612,7 +612,7 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB10_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp ugt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -632,7 +632,7 @@ define void @br_fcmp_uge(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB11_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_uge: ; RV64IF: # %bb.0: @@ -643,7 +643,7 @@ define void @br_fcmp_uge(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB11_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_uge: ; RV32IZFINX: # %bb.0: @@ -654,7 +654,7 @@ define void @br_fcmp_uge(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB11_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_uge: ; RV64IZFINX: # %bb.0: @@ -665,7 +665,7 @@ define void @br_fcmp_uge(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB11_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp uge float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -685,7 +685,7 @@ define void @br_fcmp_ult(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB12_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_ult: ; RV64IF: # %bb.0: @@ -696,7 +696,7 @@ define void @br_fcmp_ult(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB12_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_ult: ; RV32IZFINX: # %bb.0: @@ -707,7 +707,7 @@ define void @br_fcmp_ult(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB12_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_ult: ; RV64IZFINX: # %bb.0: @@ -718,7 +718,7 @@ define void @br_fcmp_ult(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB12_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp ult float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -738,7 +738,7 @@ define void @br_fcmp_ule(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB13_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_ule: ; RV64IF: # %bb.0: @@ -749,7 +749,7 @@ define void @br_fcmp_ule(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB13_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_ule: ; RV32IZFINX: # %bb.0: @@ -760,7 +760,7 @@ define void @br_fcmp_ule(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB13_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_ule: ; RV64IZFINX: # %bb.0: @@ -771,7 +771,7 @@ define void @br_fcmp_ule(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB13_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp ule float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -791,7 +791,7 @@ define void @br_fcmp_une(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB14_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_une: ; RV64IF: # %bb.0: @@ -802,7 +802,7 @@ define void @br_fcmp_une(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB14_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_une: ; RV32IZFINX: # %bb.0: @@ -813,7 +813,7 @@ define void @br_fcmp_une(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB14_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_une: ; RV64IZFINX: # %bb.0: @@ -824,7 +824,7 @@ define void @br_fcmp_une(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB14_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp une float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -846,7 +846,7 @@ define void @br_fcmp_uno(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB15_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_uno: ; RV64IF: # %bb.0: @@ -859,7 +859,7 @@ define void @br_fcmp_uno(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB15_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_uno: ; RV32IZFINX: # %bb.0: @@ -872,7 +872,7 @@ define void @br_fcmp_uno(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB15_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_uno: ; RV64IZFINX: # %bb.0: @@ -885,7 +885,7 @@ define void @br_fcmp_uno(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB15_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp uno float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -905,7 +905,7 @@ define void @br_fcmp_true(float %a, float %b) nounwind { ; RV32IF-NEXT: .LBB16_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_true: ; RV64IF: # %bb.0: @@ -916,7 +916,7 @@ define void @br_fcmp_true(float %a, float %b) nounwind { ; RV64IF-NEXT: .LBB16_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_true: ; RV32IZFINX: # %bb.0: @@ -927,7 +927,7 @@ define void @br_fcmp_true(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: .LBB16_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_true: ; RV64IZFINX: # %bb.0: @@ -938,7 +938,7 @@ define void @br_fcmp_true(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: .LBB16_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort %1 = fcmp true float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -958,12 +958,12 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.w.x fs0, zero ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call dummy@plt +; RV32IF-NEXT: call dummy ; RV32IF-NEXT: feq.s a0, fa0, fs0 ; RV32IF-NEXT: beqz a0, .LBB17_3 ; RV32IF-NEXT: # %bb.1: # %if.end ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call dummy@plt +; RV32IF-NEXT: call dummy ; RV32IF-NEXT: feq.s a0, fa0, fs0 ; RV32IF-NEXT: beqz a0, .LBB17_3 ; RV32IF-NEXT: # %bb.2: # %if.end4 @@ -973,7 +973,7 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB17_3: # %if.then -; RV32IF-NEXT: call abort@plt +; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_store_load_stack_slot: ; RV64IF: # %bb.0: # %entry @@ -982,12 +982,12 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { ; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.w.x fs0, zero ; RV64IF-NEXT: fmv.s fa0, fs0 -; RV64IF-NEXT: call dummy@plt +; RV64IF-NEXT: call dummy ; RV64IF-NEXT: feq.s a0, fa0, fs0 ; RV64IF-NEXT: beqz a0, .LBB17_3 ; RV64IF-NEXT: # %bb.1: # %if.end ; RV64IF-NEXT: fmv.s fa0, fs0 -; RV64IF-NEXT: call dummy@plt +; RV64IF-NEXT: call dummy ; RV64IF-NEXT: feq.s a0, fa0, fs0 ; RV64IF-NEXT: beqz a0, .LBB17_3 ; RV64IF-NEXT: # %bb.2: # %if.end4 @@ -997,19 +997,19 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB17_3: # %if.then -; RV64IF-NEXT: call abort@plt +; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_store_load_stack_slot: ; RV32IZFINX: # %bb.0: # %entry ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: li a0, 0 -; RV32IZFINX-NEXT: call dummy@plt +; RV32IZFINX-NEXT: call dummy ; RV32IZFINX-NEXT: feq.s a0, a0, zero ; RV32IZFINX-NEXT: beqz a0, .LBB17_3 ; RV32IZFINX-NEXT: # %bb.1: # %if.end ; RV32IZFINX-NEXT: li a0, 0 -; RV32IZFINX-NEXT: call dummy@plt +; RV32IZFINX-NEXT: call dummy ; RV32IZFINX-NEXT: feq.s a0, a0, zero ; RV32IZFINX-NEXT: beqz a0, .LBB17_3 ; RV32IZFINX-NEXT: # %bb.2: # %if.end4 @@ -1018,19 +1018,19 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; RV32IZFINX-NEXT: .LBB17_3: # %if.then -; RV32IZFINX-NEXT: call abort@plt +; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_store_load_stack_slot: ; RV64IZFINX: # %bb.0: # %entry ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: li a0, 0 -; RV64IZFINX-NEXT: call dummy@plt +; RV64IZFINX-NEXT: call dummy ; RV64IZFINX-NEXT: feq.s a0, a0, zero ; RV64IZFINX-NEXT: beqz a0, .LBB17_3 ; RV64IZFINX-NEXT: # %bb.1: # %if.end ; RV64IZFINX-NEXT: li a0, 0 -; RV64IZFINX-NEXT: call dummy@plt +; RV64IZFINX-NEXT: call dummy ; RV64IZFINX-NEXT: feq.s a0, a0, zero ; RV64IZFINX-NEXT: beqz a0, .LBB17_3 ; RV64IZFINX-NEXT: # %bb.2: # %if.end4 @@ -1039,7 +1039,7 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret ; RV64IZFINX-NEXT: .LBB17_3: # %if.then -; RV64IZFINX-NEXT: call abort@plt +; RV64IZFINX-NEXT: call abort entry: %call = call float @dummy(float 0.000000e+00) %cmp = fcmp une float %call, 0.000000e+00 diff --git a/llvm/test/CodeGen/RISCV/float-convert-strict.ll b/llvm/test/CodeGen/RISCV/float-convert-strict.ll index 6168ade0839f..402d6f0362e6 100644 --- a/llvm/test/CodeGen/RISCV/float-convert-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-convert-strict.ll @@ -35,7 +35,7 @@ define i32 @fcvt_w_s(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -44,7 +44,7 @@ define i32 @fcvt_w_s(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixsfsi@plt +; RV64I-NEXT: call __fixsfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -68,7 +68,7 @@ define i32 @fcvt_wu_s(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -77,7 +77,7 @@ define i32 @fcvt_wu_s(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfsi@plt +; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -107,7 +107,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: seqz a1, a0 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -118,7 +118,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfsi@plt +; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: seqz a1, a0 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -145,7 +145,7 @@ define float @fcvt_s_w(i32 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -155,7 +155,7 @@ define float @fcvt_s_w(i32 %a) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -182,7 +182,7 @@ define float @fcvt_s_w_load(ptr %p) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -192,7 +192,7 @@ define float @fcvt_s_w_load(ptr %p) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -216,7 +216,7 @@ define float @fcvt_s_wu(i32 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -226,7 +226,7 @@ define float @fcvt_s_wu(i32 %a) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -265,7 +265,7 @@ define float @fcvt_s_wu_load(ptr %p) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -275,7 +275,7 @@ define float @fcvt_s_wu_load(ptr %p) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -289,7 +289,7 @@ define i64 @fcvt_l_s(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -303,7 +303,7 @@ define i64 @fcvt_l_s(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -317,7 +317,7 @@ define i64 @fcvt_l_s(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixsfdi@plt +; RV32I-NEXT: call __fixsfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -326,7 +326,7 @@ define i64 @fcvt_l_s(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -340,7 +340,7 @@ define i64 @fcvt_lu_s(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -354,7 +354,7 @@ define i64 @fcvt_lu_s(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -368,7 +368,7 @@ define i64 @fcvt_lu_s(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfdi@plt +; RV32I-NEXT: call __fixunssfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -377,7 +377,7 @@ define i64 @fcvt_lu_s(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -391,7 +391,7 @@ define float @fcvt_s_l(i64 %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __floatdisf@plt +; RV32IF-NEXT: call __floatdisf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -405,7 +405,7 @@ define float @fcvt_s_l(i64 %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __floatdisf@plt +; RV32IZFINX-NEXT: call __floatdisf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -419,7 +419,7 @@ define float @fcvt_s_l(i64 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatdisf@plt +; RV32I-NEXT: call __floatdisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -428,7 +428,7 @@ define float @fcvt_s_l(i64 %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatdisf@plt +; RV64I-NEXT: call __floatdisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -442,7 +442,7 @@ define float @fcvt_s_lu(i64 %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __floatundisf@plt +; RV32IF-NEXT: call __floatundisf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -456,7 +456,7 @@ define float @fcvt_s_lu(i64 %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __floatundisf@plt +; RV32IZFINX-NEXT: call __floatundisf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -470,7 +470,7 @@ define float @fcvt_s_lu(i64 %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatundisf@plt +; RV32I-NEXT: call __floatundisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -479,7 +479,7 @@ define float @fcvt_s_lu(i64 %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatundisf@plt +; RV64I-NEXT: call __floatundisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -503,7 +503,7 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -512,7 +512,7 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -536,7 +536,7 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -545,7 +545,7 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -569,7 +569,7 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -578,7 +578,7 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -602,7 +602,7 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -611,7 +611,7 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -661,7 +661,7 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -679,7 +679,7 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind stri ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: sw a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -732,7 +732,7 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind str ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -750,7 +750,7 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind str ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: sw a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll index 235979b12221..f1e444b5b624 100644 --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -27,7 +27,7 @@ define i32 @fcvt_w_s(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -36,7 +36,7 @@ define i32 @fcvt_w_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixsfsi@plt +; RV64I-NEXT: call __fixsfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -73,10 +73,10 @@ define i32 @fcvt_w_s_sat(float %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 847872 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui s3, 524288 ; RV32I-NEXT: bgez s2, .LBB1_2 @@ -86,14 +86,14 @@ define i32 @fcvt_w_s_sat(float %a) nounwind { ; RV32I-NEXT: lui a1, 323584 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB1_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: addi s1, s3, -1 ; RV32I-NEXT: .LBB1_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -115,10 +115,10 @@ define i32 @fcvt_w_s_sat(float %a) nounwind { ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 847872 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui s3, 524288 ; RV64I-NEXT: bgez s2, .LBB1_2 @@ -128,14 +128,14 @@ define i32 @fcvt_w_s_sat(float %a) nounwind { ; RV64I-NEXT: lui a1, 323584 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB1_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: addiw s1, s3, -1 ; RV64I-NEXT: .LBB1_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -167,7 +167,7 @@ define i32 @fcvt_wu_s(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -176,7 +176,7 @@ define i32 @fcvt_wu_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfsi@plt +; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -205,7 +205,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: seqz a1, a0 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -216,7 +216,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfsi@plt +; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: seqz a1, a0 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -277,16 +277,16 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind { ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: and s1, s1, a0 ; RV32I-NEXT: lui a1, 325632 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg a0, a0 ; RV32I-NEXT: or a0, a0, s1 @@ -305,15 +305,15 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a1, 325632 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB4_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, -1 @@ -352,7 +352,7 @@ define i32 @fmv_x_w(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -361,7 +361,7 @@ define i32 @fmv_x_w(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -386,7 +386,7 @@ define float @fcvt_s_w(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -396,7 +396,7 @@ define float @fcvt_s_w(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -422,7 +422,7 @@ define float @fcvt_s_w_load(ptr %p) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -432,7 +432,7 @@ define float @fcvt_s_w_load(ptr %p) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -456,7 +456,7 @@ define float @fcvt_s_wu(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -466,7 +466,7 @@ define float @fcvt_s_wu(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -504,7 +504,7 @@ define float @fcvt_s_wu_load(ptr %p) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -514,7 +514,7 @@ define float @fcvt_s_wu_load(ptr %p) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -540,7 +540,7 @@ define float @fmv_w_x(i32 %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -549,7 +549,7 @@ define float @fmv_w_x(i32 %a, i32 %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -565,7 +565,7 @@ define i64 @fcvt_l_s(float %a) nounwind { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -579,7 +579,7 @@ define i64 @fcvt_l_s(float %a) nounwind { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -593,7 +593,7 @@ define i64 @fcvt_l_s(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixsfdi@plt +; RV32I-NEXT: call __fixsfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -602,7 +602,7 @@ define i64 @fcvt_l_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -621,7 +621,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fa0 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB12_2 @@ -668,7 +668,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32IZFINX-NEXT: lui a0, 913408 ; RV32IZFINX-NEXT: fle.s s1, a0, s0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: lui a2, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB12_2 @@ -717,10 +717,10 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 913408 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfdi@plt +; RV32I-NEXT: call __fixsfdi ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: lui s5, 524288 @@ -731,7 +731,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32I-NEXT: lui a1, 389120 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: blez a0, .LBB12_4 ; RV32I-NEXT: # %bb.3: # %start @@ -739,7 +739,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a1, a0, s3 @@ -770,10 +770,10 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 913408 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li s3, -1 ; RV64I-NEXT: bgez s2, .LBB12_2 @@ -783,14 +783,14 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV64I-NEXT: lui a1, 389120 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB12_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: srli s1, s3, 1 ; RV64I-NEXT: .LBB12_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -812,7 +812,7 @@ define i64 @fcvt_lu_s(float %a) nounwind { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -826,7 +826,7 @@ define i64 @fcvt_lu_s(float %a) nounwind { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -840,7 +840,7 @@ define i64 @fcvt_lu_s(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfdi@plt +; RV32I-NEXT: call __fixunssfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -849,7 +849,7 @@ define i64 @fcvt_lu_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -868,7 +868,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: fle.s a0, fa5, fa0 ; RV32IF-NEXT: neg s0, a0 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2) ; RV32IF-NEXT: and a0, s0, a0 @@ -902,7 +902,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IZFINX-NEXT: fle.s a0, zero, a0 ; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 @@ -936,17 +936,17 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixunssfdi@plt +; RV32I-NEXT: call __fixunssfdi ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: and s3, s2, a0 ; RV32I-NEXT: lui a1, 391168 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg a1, a0 ; RV32I-NEXT: or a0, a1, s3 @@ -968,16 +968,16 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: addi s1, a0, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: and s1, s1, a0 ; RV64I-NEXT: lui a1, 391168 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: neg a0, a0 ; RV64I-NEXT: or a0, a0, s1 @@ -997,7 +997,7 @@ define float @fcvt_s_l(i64 %a) nounwind { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __floatdisf@plt +; RV32IF-NEXT: call __floatdisf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1011,7 +1011,7 @@ define float @fcvt_s_l(i64 %a) nounwind { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __floatdisf@plt +; RV32IZFINX-NEXT: call __floatdisf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1025,7 +1025,7 @@ define float @fcvt_s_l(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatdisf@plt +; RV32I-NEXT: call __floatdisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1034,7 +1034,7 @@ define float @fcvt_s_l(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatdisf@plt +; RV64I-NEXT: call __floatdisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1047,7 +1047,7 @@ define float @fcvt_s_lu(i64 %a) nounwind { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __floatundisf@plt +; RV32IF-NEXT: call __floatundisf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1061,7 +1061,7 @@ define float @fcvt_s_lu(i64 %a) nounwind { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __floatundisf@plt +; RV32IZFINX-NEXT: call __floatundisf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1075,7 +1075,7 @@ define float @fcvt_s_lu(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatundisf@plt +; RV32I-NEXT: call __floatundisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1084,7 +1084,7 @@ define float @fcvt_s_lu(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatundisf@plt +; RV64I-NEXT: call __floatundisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1107,7 +1107,7 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1116,7 +1116,7 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1139,7 +1139,7 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1148,7 +1148,7 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1171,7 +1171,7 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1180,7 +1180,7 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1203,7 +1203,7 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1212,7 +1212,7 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1261,7 +1261,7 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatsisf@plt +; RV32I-NEXT: call __floatsisf ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1279,7 +1279,7 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatsisf@plt +; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: sw a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1332,7 +1332,7 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatunsisf@plt +; RV32I-NEXT: call __floatunsisf ; RV32I-NEXT: sw a0, 0(s0) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1350,7 +1350,7 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatunsisf@plt +; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: sw a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1389,7 +1389,7 @@ define signext i16 @fcvt_w_s_i16(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1398,7 +1398,7 @@ define signext i16 @fcvt_w_s_i16(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1470,10 +1470,10 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 815104 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: bgez s2, .LBB24_2 ; RV32I-NEXT: # %bb.1: # %start @@ -1482,7 +1482,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { ; RV32I-NEXT: lui a0, 290816 ; RV32I-NEXT: addi a1, a0, -512 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB24_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: lui s1, 8 @@ -1490,7 +1490,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { ; RV32I-NEXT: .LBB24_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -1512,10 +1512,10 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 815104 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: bgez s2, .LBB24_2 ; RV64I-NEXT: # %bb.1: # %start @@ -1524,7 +1524,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { ; RV64I-NEXT: lui a0, 290816 ; RV64I-NEXT: addiw a1, a0, -512 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB24_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: lui s1, 8 @@ -1532,7 +1532,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { ; RV64I-NEXT: .LBB24_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -1575,7 +1575,7 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1584,7 +1584,7 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1640,15 +1640,15 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, 292864 ; RV32I-NEXT: addi a1, a0, -256 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: blez a0, .LBB26_2 @@ -1677,15 +1677,15 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 292864 ; RV64I-NEXT: addiw a1, a0, -256 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: blez a0, .LBB26_2 @@ -1735,7 +1735,7 @@ define signext i8 @fcvt_w_s_i8(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1744,7 +1744,7 @@ define signext i8 @fcvt_w_s_i8(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1814,10 +1814,10 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 798720 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: bgez s2, .LBB28_2 ; RV32I-NEXT: # %bb.1: # %start @@ -1825,14 +1825,14 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind { ; RV32I-NEXT: .LBB28_2: # %start ; RV32I-NEXT: lui a1, 274400 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB28_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: li s1, 127 ; RV32I-NEXT: .LBB28_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -1854,10 +1854,10 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 798720 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: bgez s2, .LBB28_2 ; RV64I-NEXT: # %bb.1: # %start @@ -1865,14 +1865,14 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind { ; RV64I-NEXT: .LBB28_2: # %start ; RV64I-NEXT: lui a1, 274400 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB28_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: li s1, 127 ; RV64I-NEXT: .LBB28_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -1915,7 +1915,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1924,7 +1924,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1978,14 +1978,14 @@ define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a1, 276464 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB30_2 ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: li a0, 255 @@ -2012,14 +2012,14 @@ define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a1, 276464 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB30_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, 255 @@ -2091,16 +2091,16 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: and s1, s1, a0 ; RV32I-NEXT: lui a1, 325632 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg a0, a0 ; RV32I-NEXT: or a0, a0, s1 @@ -2119,15 +2119,15 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a1, 325632 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB31_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, -1 @@ -2180,10 +2180,10 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 847872 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui s3, 524288 ; RV32I-NEXT: bgez s2, .LBB32_2 @@ -2193,14 +2193,14 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind { ; RV32I-NEXT: lui a1, 323584 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB32_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: addi s1, s3, -1 ; RV32I-NEXT: .LBB32_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -2222,10 +2222,10 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind { ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 847872 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui s3, 524288 ; RV64I-NEXT: bgez s2, .LBB32_2 @@ -2235,14 +2235,14 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind { ; RV64I-NEXT: lui a1, 323584 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB32_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: addi s1, s3, -1 ; RV64I-NEXT: .LBB32_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 diff --git a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll index 36eb58fe7454..dae9f3e089cf 100644 --- a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll @@ -31,7 +31,7 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -41,7 +41,7 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -74,7 +74,7 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -84,7 +84,7 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -116,7 +116,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -127,7 +127,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -160,7 +160,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltsf2@plt +; RV32I-NEXT: call __ltsf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -170,7 +170,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltsf2@plt +; RV64I-NEXT: call __ltsf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -202,7 +202,7 @@ define i32 @fcmp_ole(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lesf2@plt +; RV32I-NEXT: call __lesf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -212,7 +212,7 @@ define i32 @fcmp_ole(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __lesf2@plt +; RV64I-NEXT: call __lesf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -261,11 +261,11 @@ define i32 @fcmp_one(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: snez s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: and a0, a0, s2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -284,11 +284,11 @@ define i32 @fcmp_one(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: snez s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -321,7 +321,7 @@ define i32 @fcmp_ord(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -331,7 +331,7 @@ define i32 @fcmp_ord(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -382,11 +382,11 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: or a0, a0, s2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -405,11 +405,11 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: or a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -447,7 +447,7 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lesf2@plt +; RV32I-NEXT: call __lesf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -457,7 +457,7 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __lesf2@plt +; RV64I-NEXT: call __lesf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -491,7 +491,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltsf2@plt +; RV32I-NEXT: call __ltsf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -502,7 +502,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltsf2@plt +; RV64I-NEXT: call __ltsf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -537,7 +537,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -547,7 +547,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -581,7 +581,7 @@ define i32 @fcmp_ule(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -591,7 +591,7 @@ define i32 @fcmp_ule(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -618,7 +618,7 @@ define i32 @fcmp_une(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __nesf2@plt +; RV32I-NEXT: call __nesf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -628,7 +628,7 @@ define i32 @fcmp_une(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __nesf2@plt +; RV64I-NEXT: call __nesf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -659,7 +659,7 @@ define i32 @fcmp_uno(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -669,7 +669,7 @@ define i32 @fcmp_uno(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -698,7 +698,7 @@ define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -708,7 +708,7 @@ define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -734,7 +734,7 @@ define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -744,7 +744,7 @@ define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -769,7 +769,7 @@ define i32 @fcmps_oge(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -780,7 +780,7 @@ define i32 @fcmps_oge(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -806,7 +806,7 @@ define i32 @fcmps_olt(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltsf2@plt +; RV32I-NEXT: call __ltsf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -816,7 +816,7 @@ define i32 @fcmps_olt(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltsf2@plt +; RV64I-NEXT: call __ltsf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -841,7 +841,7 @@ define i32 @fcmps_ole(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lesf2@plt +; RV32I-NEXT: call __lesf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -851,7 +851,7 @@ define i32 @fcmps_ole(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __lesf2@plt +; RV64I-NEXT: call __lesf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -885,11 +885,11 @@ define i32 @fcmps_one(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: snez s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: and a0, a0, s2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -908,11 +908,11 @@ define i32 @fcmps_one(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: snez s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -945,7 +945,7 @@ define i32 @fcmps_ord(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -955,7 +955,7 @@ define i32 @fcmps_ord(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -991,11 +991,11 @@ define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: or a0, a0, s2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1014,11 +1014,11 @@ define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: or a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1049,7 +1049,7 @@ define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lesf2@plt +; RV32I-NEXT: call __lesf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1059,7 +1059,7 @@ define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __lesf2@plt +; RV64I-NEXT: call __lesf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1086,7 +1086,7 @@ define i32 @fcmps_uge(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltsf2@plt +; RV32I-NEXT: call __ltsf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1097,7 +1097,7 @@ define i32 @fcmps_uge(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltsf2@plt +; RV64I-NEXT: call __ltsf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1125,7 +1125,7 @@ define i32 @fcmps_ult(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1135,7 +1135,7 @@ define i32 @fcmps_ult(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1162,7 +1162,7 @@ define i32 @fcmps_ule(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1172,7 +1172,7 @@ define i32 @fcmps_ule(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1203,7 +1203,7 @@ define i32 @fcmps_une(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __nesf2@plt +; RV32I-NEXT: call __nesf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1213,7 +1213,7 @@ define i32 @fcmps_une(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __nesf2@plt +; RV64I-NEXT: call __nesf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1244,7 +1244,7 @@ define i32 @fcmps_uno(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1254,7 +1254,7 @@ define i32 @fcmps_uno(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll index b4fbed1321e2..265d553a3e5d 100644 --- a/llvm/test/CodeGen/RISCV/float-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll @@ -52,7 +52,7 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -62,7 +62,7 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -87,7 +87,7 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -97,7 +97,7 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -122,7 +122,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -133,7 +133,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -159,7 +159,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltsf2@plt +; RV32I-NEXT: call __ltsf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -169,7 +169,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltsf2@plt +; RV64I-NEXT: call __ltsf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -194,7 +194,7 @@ define i32 @fcmp_ole(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lesf2@plt +; RV32I-NEXT: call __lesf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -204,7 +204,7 @@ define i32 @fcmp_ole(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __lesf2@plt +; RV64I-NEXT: call __lesf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -238,11 +238,11 @@ define i32 @fcmp_one(float %a, float %b) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: snez s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: and a0, a0, s2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -261,11 +261,11 @@ define i32 @fcmp_one(float %a, float %b) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: snez s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -298,7 +298,7 @@ define i32 @fcmp_ord(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -308,7 +308,7 @@ define i32 @fcmp_ord(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -344,11 +344,11 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: or a0, a0, s2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -367,11 +367,11 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz s2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: or a0, a0, s2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -402,7 +402,7 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lesf2@plt +; RV32I-NEXT: call __lesf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -412,7 +412,7 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __lesf2@plt +; RV64I-NEXT: call __lesf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -439,7 +439,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ltsf2@plt +; RV32I-NEXT: call __ltsf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -450,7 +450,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __ltsf2@plt +; RV64I-NEXT: call __ltsf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -478,7 +478,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -488,7 +488,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -515,7 +515,7 @@ define i32 @fcmp_ule(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: slti a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -525,7 +525,7 @@ define i32 @fcmp_ule(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -552,7 +552,7 @@ define i32 @fcmp_une(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __nesf2@plt +; RV32I-NEXT: call __nesf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -562,7 +562,7 @@ define i32 @fcmp_une(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __nesf2@plt +; RV64I-NEXT: call __nesf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -593,7 +593,7 @@ define i32 @fcmp_uno(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -603,7 +603,7 @@ define i32 @fcmp_uno(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/float-frem.ll b/llvm/test/CodeGen/RISCV/float-frem.ll index 6c15da0cca7b..651b1b116adc 100644 --- a/llvm/test/CodeGen/RISCV/float-frem.ll +++ b/llvm/test/CodeGen/RISCV/float-frem.ll @@ -15,21 +15,21 @@ define float @frem_f32(float %a, float %b) nounwind { ; RV32IF-LABEL: frem_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail fmodf@plt +; RV32IF-NEXT: tail fmodf ; ; RV64IF-LABEL: frem_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail fmodf@plt +; RV64IF-NEXT: tail fmodf ; ; RV32IZFINX-LABEL: frem_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail fmodf@plt +; RV32IZFINX-NEXT: tail fmodf ; ; RV64IZFINX-LABEL: frem_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call fmodf@plt +; RV64IZFINX-NEXT: call fmodf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -38,7 +38,7 @@ define float @frem_f32(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmodf@plt +; RV32I-NEXT: call fmodf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -47,7 +47,7 @@ define float @frem_f32(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmodf@plt +; RV64I-NEXT: call fmodf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll index d149b35f61c8..626db1985bfc 100644 --- a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll @@ -35,7 +35,7 @@ define float @sqrt_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrtf@plt +; RV32I-NEXT: call sqrtf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -44,7 +44,7 @@ define float @sqrt_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrtf@plt +; RV64I-NEXT: call sqrtf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -59,7 +59,7 @@ define float @powi_f32(float %a, i32 %b) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call __powisf2@plt +; RV32IF-NEXT: call __powisf2 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -69,7 +69,7 @@ define float @powi_f32(float %a, i32 %b) nounwind strictfp { ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sext.w a0, a0 -; RV64IF-NEXT: call __powisf2@plt +; RV64IF-NEXT: call __powisf2 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -78,7 +78,7 @@ define float @powi_f32(float %a, i32 %b) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call __powisf2@plt +; RV32IZFINX-NEXT: call __powisf2 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -88,7 +88,7 @@ define float @powi_f32(float %a, i32 %b) nounwind strictfp { ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: sext.w a1, a1 -; RV64IZFINX-NEXT: call __powisf2@plt +; RV64IZFINX-NEXT: call __powisf2 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -97,7 +97,7 @@ define float @powi_f32(float %a, i32 %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __powisf2@plt +; RV32I-NEXT: call __powisf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -107,7 +107,7 @@ define float @powi_f32(float %a, i32 %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __powisf2@plt +; RV64I-NEXT: call __powisf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -122,7 +122,7 @@ define float @sin_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call sinf@plt +; RV32IF-NEXT: call sinf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -131,7 +131,7 @@ define float @sin_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call sinf@plt +; RV64IF-NEXT: call sinf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -140,7 +140,7 @@ define float @sin_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call sinf@plt +; RV32IZFINX-NEXT: call sinf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -149,7 +149,7 @@ define float @sin_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: call sinf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -158,7 +158,7 @@ define float @sin_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sinf@plt +; RV32I-NEXT: call sinf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -167,7 +167,7 @@ define float @sin_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sinf@plt +; RV64I-NEXT: call sinf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -182,7 +182,7 @@ define float @cos_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call cosf@plt +; RV32IF-NEXT: call cosf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -191,7 +191,7 @@ define float @cos_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call cosf@plt +; RV64IF-NEXT: call cosf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -200,7 +200,7 @@ define float @cos_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call cosf@plt +; RV32IZFINX-NEXT: call cosf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -209,7 +209,7 @@ define float @cos_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: call cosf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -218,7 +218,7 @@ define float @cos_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call cosf@plt +; RV32I-NEXT: call cosf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -227,7 +227,7 @@ define float @cos_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call cosf@plt +; RV64I-NEXT: call cosf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -244,10 +244,10 @@ define float @sincos_f32(float %a) nounwind strictfp { ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 -; RV32IF-NEXT: call sinf@plt +; RV32IF-NEXT: call sinf ; RV32IF-NEXT: fmv.s fs1, fa0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call cosf@plt +; RV32IF-NEXT: call cosf ; RV32IF-NEXT: fadd.s fa0, fs1, fa0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload @@ -262,10 +262,10 @@ define float @sincos_f32(float %a) nounwind strictfp { ; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs0, fa0 -; RV64IF-NEXT: call sinf@plt +; RV64IF-NEXT: call sinf ; RV64IF-NEXT: fmv.s fs1, fa0 ; RV64IF-NEXT: fmv.s fa0, fs0 -; RV64IF-NEXT: call cosf@plt +; RV64IF-NEXT: call cosf ; RV64IF-NEXT: fadd.s fa0, fs1, fa0 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload @@ -280,10 +280,10 @@ define float @sincos_f32(float %a) nounwind strictfp { ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 -; RV32IZFINX-NEXT: call sinf@plt +; RV32IZFINX-NEXT: call sinf ; RV32IZFINX-NEXT: mv s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call cosf@plt +; RV32IZFINX-NEXT: call cosf ; RV32IZFINX-NEXT: fadd.s a0, s1, a0 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -298,10 +298,10 @@ define float @sincos_f32(float %a) nounwind strictfp { ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: mv s0, a0 -; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: call sinf ; RV64IZFINX-NEXT: mv s1, a0 ; RV64IZFINX-NEXT: mv a0, s0 -; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: call cosf ; RV64IZFINX-NEXT: fadd.s a0, s1, a0 ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -316,13 +316,13 @@ define float @sincos_f32(float %a) nounwind strictfp { ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: call sinf@plt +; RV32I-NEXT: call sinf ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call cosf@plt +; RV32I-NEXT: call cosf ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -336,13 +336,13 @@ define float @sincos_f32(float %a) nounwind strictfp { ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: call sinf@plt +; RV64I-NEXT: call sinf ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call cosf@plt +; RV64I-NEXT: call cosf ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -361,7 +361,7 @@ define float @pow_f32(float %a, float %b) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call powf@plt +; RV32IF-NEXT: call powf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -370,7 +370,7 @@ define float @pow_f32(float %a, float %b) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call powf@plt +; RV64IF-NEXT: call powf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -379,7 +379,7 @@ define float @pow_f32(float %a, float %b) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call powf@plt +; RV32IZFINX-NEXT: call powf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -388,7 +388,7 @@ define float @pow_f32(float %a, float %b) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call powf@plt +; RV64IZFINX-NEXT: call powf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -397,7 +397,7 @@ define float @pow_f32(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call powf@plt +; RV32I-NEXT: call powf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -406,7 +406,7 @@ define float @pow_f32(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call powf@plt +; RV64I-NEXT: call powf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -421,7 +421,7 @@ define float @exp_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call expf@plt +; RV32IF-NEXT: call expf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -430,7 +430,7 @@ define float @exp_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call expf@plt +; RV64IF-NEXT: call expf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -439,7 +439,7 @@ define float @exp_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call expf@plt +; RV32IZFINX-NEXT: call expf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -448,7 +448,7 @@ define float @exp_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call expf@plt +; RV64IZFINX-NEXT: call expf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -457,7 +457,7 @@ define float @exp_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call expf@plt +; RV32I-NEXT: call expf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -466,7 +466,7 @@ define float @exp_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call expf@plt +; RV64I-NEXT: call expf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -481,7 +481,7 @@ define float @exp2_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call exp2f@plt +; RV32IF-NEXT: call exp2f ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -490,7 +490,7 @@ define float @exp2_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call exp2f@plt +; RV64IF-NEXT: call exp2f ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -499,7 +499,7 @@ define float @exp2_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call exp2f@plt +; RV32IZFINX-NEXT: call exp2f ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -508,7 +508,7 @@ define float @exp2_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call exp2f@plt +; RV64IZFINX-NEXT: call exp2f ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -517,7 +517,7 @@ define float @exp2_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call exp2f@plt +; RV32I-NEXT: call exp2f ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -526,7 +526,7 @@ define float @exp2_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call exp2f@plt +; RV64I-NEXT: call exp2f ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -541,7 +541,7 @@ define float @log_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call logf@plt +; RV32IF-NEXT: call logf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -550,7 +550,7 @@ define float @log_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call logf@plt +; RV64IF-NEXT: call logf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -559,7 +559,7 @@ define float @log_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call logf@plt +; RV32IZFINX-NEXT: call logf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -568,7 +568,7 @@ define float @log_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call logf@plt +; RV64IZFINX-NEXT: call logf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -577,7 +577,7 @@ define float @log_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call logf@plt +; RV32I-NEXT: call logf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -586,7 +586,7 @@ define float @log_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call logf@plt +; RV64I-NEXT: call logf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -601,7 +601,7 @@ define float @log10_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call log10f@plt +; RV32IF-NEXT: call log10f ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -610,7 +610,7 @@ define float @log10_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call log10f@plt +; RV64IF-NEXT: call log10f ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -619,7 +619,7 @@ define float @log10_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call log10f@plt +; RV32IZFINX-NEXT: call log10f ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -628,7 +628,7 @@ define float @log10_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call log10f@plt +; RV64IZFINX-NEXT: call log10f ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -637,7 +637,7 @@ define float @log10_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log10f@plt +; RV32I-NEXT: call log10f ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -646,7 +646,7 @@ define float @log10_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log10f@plt +; RV64I-NEXT: call log10f ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -661,7 +661,7 @@ define float @log2_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call log2f@plt +; RV32IF-NEXT: call log2f ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -670,7 +670,7 @@ define float @log2_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call log2f@plt +; RV64IF-NEXT: call log2f ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -679,7 +679,7 @@ define float @log2_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call log2f@plt +; RV32IZFINX-NEXT: call log2f ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -688,7 +688,7 @@ define float @log2_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call log2f@plt +; RV64IZFINX-NEXT: call log2f ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -697,7 +697,7 @@ define float @log2_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log2f@plt +; RV32I-NEXT: call log2f ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -706,7 +706,7 @@ define float @log2_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log2f@plt +; RV64I-NEXT: call log2f ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -731,7 +731,7 @@ define float @fma_f32(float %a, float %b, float %c) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -740,7 +740,7 @@ define float @fma_f32(float %a, float %b, float %c) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -767,9 +767,9 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2 -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -781,9 +781,9 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -799,7 +799,7 @@ define float @minnum_f32(float %a, float %b) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call fminf@plt +; RV32IF-NEXT: call fminf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -808,7 +808,7 @@ define float @minnum_f32(float %a, float %b) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call fminf@plt +; RV64IF-NEXT: call fminf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -817,7 +817,7 @@ define float @minnum_f32(float %a, float %b) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call fminf@plt +; RV32IZFINX-NEXT: call fminf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -826,7 +826,7 @@ define float @minnum_f32(float %a, float %b) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call fminf@plt +; RV64IZFINX-NEXT: call fminf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -835,7 +835,7 @@ define float @minnum_f32(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fminf@plt +; RV32I-NEXT: call fminf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -844,7 +844,7 @@ define float @minnum_f32(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fminf@plt +; RV64I-NEXT: call fminf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -859,7 +859,7 @@ define float @maxnum_f32(float %a, float %b) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call fmaxf@plt +; RV32IF-NEXT: call fmaxf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -868,7 +868,7 @@ define float @maxnum_f32(float %a, float %b) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call fmaxf@plt +; RV64IF-NEXT: call fmaxf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -877,7 +877,7 @@ define float @maxnum_f32(float %a, float %b) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call fmaxf@plt +; RV32IZFINX-NEXT: call fmaxf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -886,7 +886,7 @@ define float @maxnum_f32(float %a, float %b) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call fmaxf@plt +; RV64IZFINX-NEXT: call fmaxf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -895,7 +895,7 @@ define float @maxnum_f32(float %a, float %b) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaxf@plt +; RV32I-NEXT: call fmaxf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -904,7 +904,7 @@ define float @maxnum_f32(float %a, float %b) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaxf@plt +; RV64I-NEXT: call fmaxf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -936,7 +936,7 @@ define float @floor_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call floorf@plt +; RV32IF-NEXT: call floorf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -945,7 +945,7 @@ define float @floor_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call floorf@plt +; RV64IF-NEXT: call floorf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -954,7 +954,7 @@ define float @floor_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call floorf@plt +; RV32IZFINX-NEXT: call floorf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -963,7 +963,7 @@ define float @floor_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call floorf@plt +; RV64IZFINX-NEXT: call floorf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -972,7 +972,7 @@ define float @floor_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call floorf@plt +; RV32I-NEXT: call floorf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -981,7 +981,7 @@ define float @floor_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call floorf@plt +; RV64I-NEXT: call floorf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -996,7 +996,7 @@ define float @ceil_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call ceilf@plt +; RV32IF-NEXT: call ceilf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1005,7 +1005,7 @@ define float @ceil_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call ceilf@plt +; RV64IF-NEXT: call ceilf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -1014,7 +1014,7 @@ define float @ceil_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call ceilf@plt +; RV32IZFINX-NEXT: call ceilf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1023,7 +1023,7 @@ define float @ceil_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call ceilf@plt +; RV64IZFINX-NEXT: call ceilf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -1032,7 +1032,7 @@ define float @ceil_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call ceilf@plt +; RV32I-NEXT: call ceilf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1041,7 +1041,7 @@ define float @ceil_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call ceilf@plt +; RV64I-NEXT: call ceilf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1056,7 +1056,7 @@ define float @trunc_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call truncf@plt +; RV32IF-NEXT: call truncf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1065,7 +1065,7 @@ define float @trunc_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call truncf@plt +; RV64IF-NEXT: call truncf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -1074,7 +1074,7 @@ define float @trunc_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call truncf@plt +; RV32IZFINX-NEXT: call truncf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1083,7 +1083,7 @@ define float @trunc_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call truncf@plt +; RV64IZFINX-NEXT: call truncf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -1092,7 +1092,7 @@ define float @trunc_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call truncf@plt +; RV32I-NEXT: call truncf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1101,7 +1101,7 @@ define float @trunc_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call truncf@plt +; RV64I-NEXT: call truncf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1116,7 +1116,7 @@ define float @rint_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call rintf@plt +; RV32IF-NEXT: call rintf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1125,7 +1125,7 @@ define float @rint_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call rintf@plt +; RV64IF-NEXT: call rintf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -1134,7 +1134,7 @@ define float @rint_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call rintf@plt +; RV32IZFINX-NEXT: call rintf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1143,7 +1143,7 @@ define float @rint_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call rintf@plt +; RV64IZFINX-NEXT: call rintf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -1152,7 +1152,7 @@ define float @rint_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call rintf@plt +; RV32I-NEXT: call rintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1161,7 +1161,7 @@ define float @rint_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call rintf@plt +; RV64I-NEXT: call rintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1176,7 +1176,7 @@ define float @nearbyint_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call nearbyintf@plt +; RV32IF-NEXT: call nearbyintf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1185,7 +1185,7 @@ define float @nearbyint_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call nearbyintf@plt +; RV64IF-NEXT: call nearbyintf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -1194,7 +1194,7 @@ define float @nearbyint_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call nearbyintf@plt +; RV32IZFINX-NEXT: call nearbyintf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1203,7 +1203,7 @@ define float @nearbyint_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call nearbyintf@plt +; RV64IZFINX-NEXT: call nearbyintf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -1212,7 +1212,7 @@ define float @nearbyint_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call nearbyintf@plt +; RV32I-NEXT: call nearbyintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1221,7 +1221,7 @@ define float @nearbyint_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call nearbyintf@plt +; RV64I-NEXT: call nearbyintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1236,7 +1236,7 @@ define float @round_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call roundf@plt +; RV32IF-NEXT: call roundf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1245,7 +1245,7 @@ define float @round_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call roundf@plt +; RV64IF-NEXT: call roundf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -1254,7 +1254,7 @@ define float @round_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call roundf@plt +; RV32IZFINX-NEXT: call roundf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1263,7 +1263,7 @@ define float @round_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call roundf@plt +; RV64IZFINX-NEXT: call roundf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -1272,7 +1272,7 @@ define float @round_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call roundf@plt +; RV32I-NEXT: call roundf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1281,7 +1281,7 @@ define float @round_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call roundf@plt +; RV64I-NEXT: call roundf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1296,7 +1296,7 @@ define float @roundeven_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call roundevenf@plt +; RV32IF-NEXT: call roundevenf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1305,7 +1305,7 @@ define float @roundeven_f32(float %a) nounwind strictfp { ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call roundevenf@plt +; RV64IF-NEXT: call roundevenf ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -1314,7 +1314,7 @@ define float @roundeven_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call roundevenf@plt +; RV32IZFINX-NEXT: call roundevenf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1323,7 +1323,7 @@ define float @roundeven_f32(float %a) nounwind strictfp { ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call roundevenf@plt +; RV64IZFINX-NEXT: call roundevenf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -1332,7 +1332,7 @@ define float @roundeven_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call roundevenf@plt +; RV32I-NEXT: call roundevenf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1341,7 +1341,7 @@ define float @roundeven_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call roundevenf@plt +; RV64I-NEXT: call roundevenf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1376,7 +1376,7 @@ define iXLen @lrint_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lrintf@plt +; RV32I-NEXT: call lrintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1385,7 +1385,7 @@ define iXLen @lrint_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lrintf@plt +; RV64I-NEXT: call lrintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1420,7 +1420,7 @@ define iXLen @lround_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lroundf@plt +; RV32I-NEXT: call lroundf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1429,7 +1429,7 @@ define iXLen @lround_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lroundf@plt +; RV64I-NEXT: call lroundf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1444,7 +1444,7 @@ define i64 @llrint_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call llrintf@plt +; RV32IF-NEXT: call llrintf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1458,7 +1458,7 @@ define i64 @llrint_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call llrintf@plt +; RV32IZFINX-NEXT: call llrintf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1472,7 +1472,7 @@ define i64 @llrint_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llrintf@plt +; RV32I-NEXT: call llrintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1481,7 +1481,7 @@ define i64 @llrint_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llrintf@plt +; RV64I-NEXT: call llrintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1496,7 +1496,7 @@ define i64 @llround_f32(float %a) nounwind strictfp { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call llroundf@plt +; RV32IF-NEXT: call llroundf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1510,7 +1510,7 @@ define i64 @llround_f32(float %a) nounwind strictfp { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call llroundf@plt +; RV32IZFINX-NEXT: call llroundf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1524,7 +1524,7 @@ define i64 @llround_f32(float %a) nounwind strictfp { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llroundf@plt +; RV32I-NEXT: call llroundf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1533,7 +1533,7 @@ define i64 @llround_f32(float %a) nounwind strictfp { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llroundf@plt +; RV64I-NEXT: call llroundf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll index e7ec2fdaf93f..a00d82942cab 100644 --- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll @@ -49,7 +49,7 @@ define float @sqrt_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sqrtf@plt +; RV32I-NEXT: call sqrtf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -58,7 +58,7 @@ define float @sqrt_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sqrtf@plt +; RV64I-NEXT: call sqrtf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -71,18 +71,18 @@ declare float @llvm.powi.f32.i32(float, i32) define float @powi_f32(float %a, i32 %b) nounwind { ; RV32IF-LABEL: powi_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail __powisf2@plt +; RV32IF-NEXT: tail __powisf2 ; ; RV32IZFINX-LABEL: powi_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail __powisf2@plt +; RV32IZFINX-NEXT: tail __powisf2 ; ; RV64IF-LABEL: powi_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sext.w a0, a0 -; RV64IF-NEXT: call __powisf2@plt +; RV64IF-NEXT: call __powisf2 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -92,7 +92,7 @@ define float @powi_f32(float %a, i32 %b) nounwind { ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: sext.w a1, a1 -; RV64IZFINX-NEXT: call __powisf2@plt +; RV64IZFINX-NEXT: call __powisf2 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -101,7 +101,7 @@ define float @powi_f32(float %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __powisf2@plt +; RV32I-NEXT: call __powisf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -111,7 +111,7 @@ define float @powi_f32(float %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __powisf2@plt +; RV64I-NEXT: call __powisf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -124,21 +124,21 @@ declare float @llvm.sin.f32(float) define float @sin_f32(float %a) nounwind { ; RV32IF-LABEL: sin_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail sinf@plt +; RV32IF-NEXT: tail sinf ; ; RV32IZFINX-LABEL: sin_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail sinf@plt +; RV32IZFINX-NEXT: tail sinf ; ; RV64IF-LABEL: sin_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail sinf@plt +; RV64IF-NEXT: tail sinf ; ; RV64IZFINX-LABEL: sin_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: call sinf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -147,7 +147,7 @@ define float @sin_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call sinf@plt +; RV32I-NEXT: call sinf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -156,7 +156,7 @@ define float @sin_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call sinf@plt +; RV64I-NEXT: call sinf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -169,21 +169,21 @@ declare float @llvm.cos.f32(float) define float @cos_f32(float %a) nounwind { ; RV32IF-LABEL: cos_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail cosf@plt +; RV32IF-NEXT: tail cosf ; ; RV32IZFINX-LABEL: cos_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail cosf@plt +; RV32IZFINX-NEXT: tail cosf ; ; RV64IF-LABEL: cos_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail cosf@plt +; RV64IF-NEXT: tail cosf ; ; RV64IZFINX-LABEL: cos_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: call cosf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -192,7 +192,7 @@ define float @cos_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call cosf@plt +; RV32I-NEXT: call cosf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -201,7 +201,7 @@ define float @cos_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call cosf@plt +; RV64I-NEXT: call cosf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -218,10 +218,10 @@ define float @sincos_f32(float %a) nounwind { ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 -; RV32IF-NEXT: call sinf@plt +; RV32IF-NEXT: call sinf ; RV32IF-NEXT: fmv.s fs1, fa0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call cosf@plt +; RV32IF-NEXT: call cosf ; RV32IF-NEXT: fadd.s fa0, fs1, fa0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload @@ -236,10 +236,10 @@ define float @sincos_f32(float %a) nounwind { ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 -; RV32IZFINX-NEXT: call sinf@plt +; RV32IZFINX-NEXT: call sinf ; RV32IZFINX-NEXT: mv s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call cosf@plt +; RV32IZFINX-NEXT: call cosf ; RV32IZFINX-NEXT: fadd.s a0, s1, a0 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -254,10 +254,10 @@ define float @sincos_f32(float %a) nounwind { ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: mv s0, a0 -; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: call sinf ; RV64IZFINX-NEXT: mv s1, a0 ; RV64IZFINX-NEXT: mv a0, s0 -; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: call cosf ; RV64IZFINX-NEXT: fadd.s a0, s1, a0 ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -272,13 +272,13 @@ define float @sincos_f32(float %a) nounwind { ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: call sinf@plt +; RV32I-NEXT: call sinf ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call cosf@plt +; RV32I-NEXT: call cosf ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -292,13 +292,13 @@ define float @sincos_f32(float %a) nounwind { ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: call sinf@plt +; RV64I-NEXT: call sinf ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call cosf@plt +; RV64I-NEXT: call cosf ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -315,21 +315,21 @@ declare float @llvm.pow.f32(float, float) define float @pow_f32(float %a, float %b) nounwind { ; RV32IF-LABEL: pow_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail powf@plt +; RV32IF-NEXT: tail powf ; ; RV32IZFINX-LABEL: pow_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail powf@plt +; RV32IZFINX-NEXT: tail powf ; ; RV64IF-LABEL: pow_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail powf@plt +; RV64IF-NEXT: tail powf ; ; RV64IZFINX-LABEL: pow_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call powf@plt +; RV64IZFINX-NEXT: call powf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -338,7 +338,7 @@ define float @pow_f32(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call powf@plt +; RV32I-NEXT: call powf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -347,7 +347,7 @@ define float @pow_f32(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call powf@plt +; RV64I-NEXT: call powf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -360,21 +360,21 @@ declare float @llvm.exp.f32(float) define float @exp_f32(float %a) nounwind { ; RV32IF-LABEL: exp_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail expf@plt +; RV32IF-NEXT: tail expf ; ; RV32IZFINX-LABEL: exp_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail expf@plt +; RV32IZFINX-NEXT: tail expf ; ; RV64IF-LABEL: exp_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail expf@plt +; RV64IF-NEXT: tail expf ; ; RV64IZFINX-LABEL: exp_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call expf@plt +; RV64IZFINX-NEXT: call expf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -383,7 +383,7 @@ define float @exp_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call expf@plt +; RV32I-NEXT: call expf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -392,7 +392,7 @@ define float @exp_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call expf@plt +; RV64I-NEXT: call expf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -405,21 +405,21 @@ declare float @llvm.exp2.f32(float) define float @exp2_f32(float %a) nounwind { ; RV32IF-LABEL: exp2_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail exp2f@plt +; RV32IF-NEXT: tail exp2f ; ; RV32IZFINX-LABEL: exp2_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail exp2f@plt +; RV32IZFINX-NEXT: tail exp2f ; ; RV64IF-LABEL: exp2_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail exp2f@plt +; RV64IF-NEXT: tail exp2f ; ; RV64IZFINX-LABEL: exp2_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call exp2f@plt +; RV64IZFINX-NEXT: call exp2f ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -428,7 +428,7 @@ define float @exp2_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call exp2f@plt +; RV32I-NEXT: call exp2f ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -437,7 +437,7 @@ define float @exp2_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call exp2f@plt +; RV64I-NEXT: call exp2f ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -450,21 +450,21 @@ declare float @llvm.log.f32(float) define float @log_f32(float %a) nounwind { ; RV32IF-LABEL: log_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail logf@plt +; RV32IF-NEXT: tail logf ; ; RV32IZFINX-LABEL: log_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail logf@plt +; RV32IZFINX-NEXT: tail logf ; ; RV64IF-LABEL: log_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail logf@plt +; RV64IF-NEXT: tail logf ; ; RV64IZFINX-LABEL: log_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call logf@plt +; RV64IZFINX-NEXT: call logf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -473,7 +473,7 @@ define float @log_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call logf@plt +; RV32I-NEXT: call logf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -482,7 +482,7 @@ define float @log_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call logf@plt +; RV64I-NEXT: call logf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -495,21 +495,21 @@ declare float @llvm.log10.f32(float) define float @log10_f32(float %a) nounwind { ; RV32IF-LABEL: log10_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail log10f@plt +; RV32IF-NEXT: tail log10f ; ; RV32IZFINX-LABEL: log10_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail log10f@plt +; RV32IZFINX-NEXT: tail log10f ; ; RV64IF-LABEL: log10_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail log10f@plt +; RV64IF-NEXT: tail log10f ; ; RV64IZFINX-LABEL: log10_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call log10f@plt +; RV64IZFINX-NEXT: call log10f ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -518,7 +518,7 @@ define float @log10_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log10f@plt +; RV32I-NEXT: call log10f ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -527,7 +527,7 @@ define float @log10_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log10f@plt +; RV64I-NEXT: call log10f ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -540,21 +540,21 @@ declare float @llvm.log2.f32(float) define float @log2_f32(float %a) nounwind { ; RV32IF-LABEL: log2_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail log2f@plt +; RV32IF-NEXT: tail log2f ; ; RV32IZFINX-LABEL: log2_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail log2f@plt +; RV32IZFINX-NEXT: tail log2f ; ; RV64IF-LABEL: log2_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail log2f@plt +; RV64IF-NEXT: tail log2f ; ; RV64IZFINX-LABEL: log2_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call log2f@plt +; RV64IZFINX-NEXT: call log2f ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -563,7 +563,7 @@ define float @log2_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call log2f@plt +; RV32I-NEXT: call log2f ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -572,7 +572,7 @@ define float @log2_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call log2f@plt +; RV64I-NEXT: call log2f ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -607,7 +607,7 @@ define float @fma_f32(float %a, float %b, float %c) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: call fmaf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -616,7 +616,7 @@ define float @fma_f32(float %a, float %b, float %c) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaf@plt +; RV64I-NEXT: call fmaf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -653,9 +653,9 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2 -; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -667,9 +667,9 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 -; RV64I-NEXT: call __mulsf3@plt +; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __addsf3@plt +; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -745,7 +745,7 @@ define float @minnum_f32(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fminf@plt +; RV32I-NEXT: call fminf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -754,7 +754,7 @@ define float @minnum_f32(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fminf@plt +; RV64I-NEXT: call fminf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -789,7 +789,7 @@ define float @maxnum_f32(float %a, float %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call fmaxf@plt +; RV32I-NEXT: call fmaxf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -798,7 +798,7 @@ define float @maxnum_f32(float %a, float %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call fmaxf@plt +; RV64I-NEXT: call fmaxf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -928,7 +928,7 @@ define float @floor_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call floorf@plt +; RV32I-NEXT: call floorf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -937,7 +937,7 @@ define float @floor_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call floorf@plt +; RV64I-NEXT: call floorf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1006,7 +1006,7 @@ define float @ceil_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call ceilf@plt +; RV32I-NEXT: call ceilf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1015,7 +1015,7 @@ define float @ceil_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call ceilf@plt +; RV64I-NEXT: call ceilf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1084,7 +1084,7 @@ define float @trunc_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call truncf@plt +; RV32I-NEXT: call truncf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1093,7 +1093,7 @@ define float @trunc_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call truncf@plt +; RV64I-NEXT: call truncf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1162,7 +1162,7 @@ define float @rint_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call rintf@plt +; RV32I-NEXT: call rintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1171,7 +1171,7 @@ define float @rint_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call rintf@plt +; RV64I-NEXT: call rintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1184,21 +1184,21 @@ declare float @llvm.nearbyint.f32(float) define float @nearbyint_f32(float %a) nounwind { ; RV32IF-LABEL: nearbyint_f32: ; RV32IF: # %bb.0: -; RV32IF-NEXT: tail nearbyintf@plt +; RV32IF-NEXT: tail nearbyintf ; ; RV32IZFINX-LABEL: nearbyint_f32: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: tail nearbyintf@plt +; RV32IZFINX-NEXT: tail nearbyintf ; ; RV64IF-LABEL: nearbyint_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: tail nearbyintf@plt +; RV64IF-NEXT: tail nearbyintf ; ; RV64IZFINX-LABEL: nearbyint_f32: ; RV64IZFINX: # %bb.0: ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINX-NEXT: call nearbyintf@plt +; RV64IZFINX-NEXT: call nearbyintf ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret @@ -1207,7 +1207,7 @@ define float @nearbyint_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call nearbyintf@plt +; RV32I-NEXT: call nearbyintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1216,7 +1216,7 @@ define float @nearbyint_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call nearbyintf@plt +; RV64I-NEXT: call nearbyintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1285,7 +1285,7 @@ define float @round_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call roundf@plt +; RV32I-NEXT: call roundf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1294,7 +1294,7 @@ define float @round_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call roundf@plt +; RV64I-NEXT: call roundf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1363,7 +1363,7 @@ define float @roundeven_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call roundevenf@plt +; RV32I-NEXT: call roundevenf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1372,7 +1372,7 @@ define float @roundeven_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call roundevenf@plt +; RV64I-NEXT: call roundevenf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1407,7 +1407,7 @@ define iXLen @lrint_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lrintf@plt +; RV32I-NEXT: call lrintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1416,7 +1416,7 @@ define iXLen @lrint_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lrintf@plt +; RV64I-NEXT: call lrintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1452,7 +1452,7 @@ define iXLen @lround_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lroundf@plt +; RV32I-NEXT: call lroundf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1461,7 +1461,7 @@ define iXLen @lround_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lroundf@plt +; RV64I-NEXT: call lroundf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1496,7 +1496,7 @@ define i32 @lround_i32_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call lroundf@plt +; RV32I-NEXT: call lroundf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1505,7 +1505,7 @@ define i32 @lround_i32_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call lroundf@plt +; RV64I-NEXT: call lroundf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1520,7 +1520,7 @@ define i64 @llrint_f32(float %a) nounwind { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call llrintf@plt +; RV32IF-NEXT: call llrintf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1529,7 +1529,7 @@ define i64 @llrint_f32(float %a) nounwind { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call llrintf@plt +; RV32IZFINX-NEXT: call llrintf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1548,7 +1548,7 @@ define i64 @llrint_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llrintf@plt +; RV32I-NEXT: call llrintf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1557,7 +1557,7 @@ define i64 @llrint_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llrintf@plt +; RV64I-NEXT: call llrintf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1572,7 +1572,7 @@ define i64 @llround_f32(float %a) nounwind { ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: call llroundf@plt +; RV32IF-NEXT: call llroundf ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1581,7 +1581,7 @@ define i64 @llround_f32(float %a) nounwind { ; RV32IZFINX: # %bb.0: ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: call llroundf@plt +; RV32IZFINX-NEXT: call llroundf ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1600,7 +1600,7 @@ define i64 @llround_f32(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call llroundf@plt +; RV32I-NEXT: call llroundf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1609,7 +1609,7 @@ define i64 @llround_f32(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call llroundf@plt +; RV64I-NEXT: call llroundf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll index b5d5f8e7c7e6..3779d39a753e 100644 --- a/llvm/test/CodeGen/RISCV/float-mem.ll +++ b/llvm/test/CodeGen/RISCV/float-mem.ll @@ -142,7 +142,7 @@ define dso_local float @flw_stack(float %a) nounwind { ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: addi a0, sp, 4 -; RV32IF-NEXT: call notdead@plt +; RV32IF-NEXT: call notdead ; RV32IF-NEXT: flw fa5, 4(sp) ; RV32IF-NEXT: fadd.s fa0, fa5, fs0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -157,7 +157,7 @@ define dso_local float @flw_stack(float %a) nounwind { ; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: mv a0, sp -; RV64IF-NEXT: call notdead@plt +; RV64IF-NEXT: call notdead ; RV64IF-NEXT: flw fa5, 0(sp) ; RV64IF-NEXT: fadd.s fa0, fa5, fs0 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -172,7 +172,7 @@ define dso_local float @flw_stack(float %a) nounwind { ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: addi a0, sp, 4 -; RV32IZFINX-NEXT: call notdead@plt +; RV32IZFINX-NEXT: call notdead ; RV32IZFINX-NEXT: lw a0, 4(sp) ; RV32IZFINX-NEXT: fadd.s a0, a0, s0 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -187,7 +187,7 @@ define dso_local float @flw_stack(float %a) nounwind { ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: mv s0, a0 ; RV64IZFINX-NEXT: addi a0, sp, 12 -; RV64IZFINX-NEXT: call notdead@plt +; RV64IZFINX-NEXT: call notdead ; RV64IZFINX-NEXT: lw a0, 12(sp) ; RV64IZFINX-NEXT: fadd.s a0, a0, s0 ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -209,7 +209,7 @@ define dso_local void @fsw_stack(float %a, float %b) nounwind { ; RV32IF-NEXT: fadd.s fa5, fa0, fa1 ; RV32IF-NEXT: fsw fa5, 8(sp) ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: call notdead@plt +; RV32IF-NEXT: call notdead ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -221,7 +221,7 @@ define dso_local void @fsw_stack(float %a, float %b) nounwind { ; RV64IF-NEXT: fadd.s fa5, fa0, fa1 ; RV64IF-NEXT: fsw fa5, 4(sp) ; RV64IF-NEXT: addi a0, sp, 4 -; RV64IF-NEXT: call notdead@plt +; RV64IF-NEXT: call notdead ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -233,7 +233,7 @@ define dso_local void @fsw_stack(float %a, float %b) nounwind { ; RV32IZFINX-NEXT: fadd.s a0, a0, a1 ; RV32IZFINX-NEXT: sw a0, 8(sp) ; RV32IZFINX-NEXT: addi a0, sp, 8 -; RV32IZFINX-NEXT: call notdead@plt +; RV32IZFINX-NEXT: call notdead ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -245,7 +245,7 @@ define dso_local void @fsw_stack(float %a, float %b) nounwind { ; RV64IZFINX-NEXT: fadd.s a0, a0, a1 ; RV64IZFINX-NEXT: sw a0, 4(sp) ; RV64IZFINX-NEXT: addi a0, sp, 4 -; RV64IZFINX-NEXT: call notdead@plt +; RV64IZFINX-NEXT: call notdead ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINX-NEXT: addi sp, sp, 16 ; RV64IZFINX-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll index d947d0f25cdd..5e99c7eb9056 100644 --- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll @@ -53,7 +53,7 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB1_4 @@ -111,7 +111,7 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s s1, a0, s0 ; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 @@ -197,7 +197,7 @@ define i64 @test_floor_ui64(float %x) nounwind { ; RV32IF-NEXT: fle.s a0, fa5, fs0 ; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI3_0)(a2) ; RV32IF-NEXT: and a0, s0, a0 @@ -240,7 +240,7 @@ define i64 @test_floor_ui64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s a0, zero, s0 ; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI3_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 @@ -313,7 +313,7 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB5_4 @@ -371,7 +371,7 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s s1, a0, s0 ; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 @@ -457,7 +457,7 @@ define i64 @test_ceil_ui64(float %x) nounwind { ; RV32IF-NEXT: fle.s a0, fa5, fs0 ; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI7_0)(a2) ; RV32IF-NEXT: and a0, s0, a0 @@ -500,7 +500,7 @@ define i64 @test_ceil_ui64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s a0, zero, s0 ; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI7_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 @@ -573,7 +573,7 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB9_4 @@ -631,7 +631,7 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s s1, a0, s0 ; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 @@ -717,7 +717,7 @@ define i64 @test_trunc_ui64(float %x) nounwind { ; RV32IF-NEXT: fle.s a0, fa5, fs0 ; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI11_0)(a2) ; RV32IF-NEXT: and a0, s0, a0 @@ -760,7 +760,7 @@ define i64 @test_trunc_ui64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s a0, zero, s0 ; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI11_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 @@ -833,7 +833,7 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB13_4 @@ -891,7 +891,7 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s s1, a0, s0 ; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 @@ -977,7 +977,7 @@ define i64 @test_round_ui64(float %x) nounwind { ; RV32IF-NEXT: fle.s a0, fa5, fs0 ; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI15_0)(a2) ; RV32IF-NEXT: and a0, s0, a0 @@ -1020,7 +1020,7 @@ define i64 @test_round_ui64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s a0, zero, s0 ; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI15_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 @@ -1093,7 +1093,7 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB17_4 @@ -1151,7 +1151,7 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s s1, a0, s0 ; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 @@ -1237,7 +1237,7 @@ define i64 @test_roundeven_ui64(float %x) nounwind { ; RV32IF-NEXT: fle.s a0, fa5, fs0 ; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI19_0)(a2) ; RV32IF-NEXT: and a0, s0, a0 @@ -1280,7 +1280,7 @@ define i64 @test_roundeven_ui64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s a0, zero, s0 ; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI19_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 @@ -1353,7 +1353,7 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB21_4 @@ -1411,7 +1411,7 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s s1, a0, s0 ; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 @@ -1497,7 +1497,7 @@ define i64 @test_rint_ui64(float %x) nounwind { ; RV32IF-NEXT: fle.s a0, fa5, fs0 ; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lui a2, %hi(.LCPI23_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI23_0)(a2) ; RV32IF-NEXT: and a0, s0, a0 @@ -1540,7 +1540,7 @@ define i64 @test_rint_ui64(float %x) nounwind { ; RV32IZFINX-NEXT: fle.s a0, zero, s0 ; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI23_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI23_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 diff --git a/llvm/test/CodeGen/RISCV/float-round-conv.ll b/llvm/test/CodeGen/RISCV/float-round-conv.ll index ed50f867cdb8..1b1344843975 100644 --- a/llvm/test/CodeGen/RISCV/float-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv.ll @@ -100,7 +100,7 @@ define i64 @test_floor_si64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -125,7 +125,7 @@ define i64 @test_floor_si64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -231,7 +231,7 @@ define i64 @test_floor_ui64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -256,7 +256,7 @@ define i64 @test_floor_ui64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -362,7 +362,7 @@ define i64 @test_ceil_si64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -387,7 +387,7 @@ define i64 @test_ceil_si64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -493,7 +493,7 @@ define i64 @test_ceil_ui64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -518,7 +518,7 @@ define i64 @test_ceil_ui64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -624,7 +624,7 @@ define i64 @test_trunc_si64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -649,7 +649,7 @@ define i64 @test_trunc_si64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -755,7 +755,7 @@ define i64 @test_trunc_ui64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -780,7 +780,7 @@ define i64 @test_trunc_ui64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -886,7 +886,7 @@ define i64 @test_round_si64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -911,7 +911,7 @@ define i64 @test_round_si64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1017,7 +1017,7 @@ define i64 @test_round_ui64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1042,7 +1042,7 @@ define i64 @test_round_ui64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1148,7 +1148,7 @@ define i64 @test_roundeven_si64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixsfdi@plt +; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1173,7 +1173,7 @@ define i64 @test_roundeven_si64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: call __fixsfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret @@ -1279,7 +1279,7 @@ define i64 @test_roundeven_ui64(float %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret @@ -1304,7 +1304,7 @@ define i64 @test_roundeven_ui64(float %x) { ; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: .cfi_offset ra, -4 -; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: call __fixunssfdi ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-zfa.ll b/llvm/test/CodeGen/RISCV/float-zfa.ll index 52c9ac7333fc..e5196ead1f88 100644 --- a/llvm/test/CodeGen/RISCV/float-zfa.ll +++ b/llvm/test/CodeGen/RISCV/float-zfa.ll @@ -265,7 +265,7 @@ define void @fli_remat() { ; CHECK: # %bb.0: ; CHECK-NEXT: fli.s fa0, 1.0 ; CHECK-NEXT: fli.s fa1, 1.0 -; CHECK-NEXT: tail foo@plt +; CHECK-NEXT: tail foo tail call void @foo(float 1.000000e+00, float 1.000000e+00) ret void } diff --git a/llvm/test/CodeGen/RISCV/fmax-fmin.ll b/llvm/test/CodeGen/RISCV/fmax-fmin.ll index b67093d72439..9d5729802a0f 100644 --- a/llvm/test/CodeGen/RISCV/fmax-fmin.ll +++ b/llvm/test/CodeGen/RISCV/fmax-fmin.ll @@ -7,7 +7,7 @@ define float @maxnum_f32(float %x, float %y) nounwind { ; R32: # %bb.0: ; R32-NEXT: addi sp, sp, -16 ; R32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; R32-NEXT: call fmaxf@plt +; R32-NEXT: call fmaxf ; R32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; R32-NEXT: addi sp, sp, 16 ; R32-NEXT: ret @@ -16,7 +16,7 @@ define float @maxnum_f32(float %x, float %y) nounwind { ; R64: # %bb.0: ; R64-NEXT: addi sp, sp, -16 ; R64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; R64-NEXT: call fmaxf@plt +; R64-NEXT: call fmaxf ; R64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; R64-NEXT: addi sp, sp, 16 ; R64-NEXT: ret @@ -33,7 +33,7 @@ define float @maxnum_f32_fast(float %x, float %y) nounwind { ; R32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; R32-NEXT: mv s1, a1 ; R32-NEXT: mv s0, a0 -; R32-NEXT: call __gtsf2@plt +; R32-NEXT: call __gtsf2 ; R32-NEXT: bgtz a0, .LBB1_2 ; R32-NEXT: # %bb.1: ; R32-NEXT: mv s0, s1 @@ -53,7 +53,7 @@ define float @maxnum_f32_fast(float %x, float %y) nounwind { ; R64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; R64-NEXT: mv s1, a1 ; R64-NEXT: mv s0, a0 -; R64-NEXT: call __gtsf2@plt +; R64-NEXT: call __gtsf2 ; R64-NEXT: bgtz a0, .LBB1_2 ; R64-NEXT: # %bb.1: ; R64-NEXT: mv s0, s1 @@ -73,7 +73,7 @@ define double @maxnum_f64(double %x, double %y) nounwind { ; R32: # %bb.0: ; R32-NEXT: addi sp, sp, -16 ; R32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; R32-NEXT: call fmax@plt +; R32-NEXT: call fmax ; R32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; R32-NEXT: addi sp, sp, 16 ; R32-NEXT: ret @@ -82,7 +82,7 @@ define double @maxnum_f64(double %x, double %y) nounwind { ; R64: # %bb.0: ; R64-NEXT: addi sp, sp, -16 ; R64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; R64-NEXT: call fmax@plt +; R64-NEXT: call fmax ; R64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; R64-NEXT: addi sp, sp, 16 ; R64-NEXT: ret @@ -103,7 +103,7 @@ define double @maxnum_f64_nnan(double %x, double %y) nounwind { ; R32-NEXT: mv s2, a2 ; R32-NEXT: mv s0, a1 ; R32-NEXT: mv s3, a0 -; R32-NEXT: call __gtdf2@plt +; R32-NEXT: call __gtdf2 ; R32-NEXT: mv a1, a0 ; R32-NEXT: mv a0, s3 ; R32-NEXT: bgtz a1, .LBB3_2 @@ -113,7 +113,7 @@ define double @maxnum_f64_nnan(double %x, double %y) nounwind { ; R32-NEXT: mv a1, s0 ; R32-NEXT: mv a2, s2 ; R32-NEXT: mv a3, s1 -; R32-NEXT: call __gtdf2@plt +; R32-NEXT: call __gtdf2 ; R32-NEXT: bgtz a0, .LBB3_4 ; R32-NEXT: # %bb.3: ; R32-NEXT: mv s0, s1 @@ -136,7 +136,7 @@ define double @maxnum_f64_nnan(double %x, double %y) nounwind { ; R64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; R64-NEXT: mv s1, a1 ; R64-NEXT: mv s0, a0 -; R64-NEXT: call __gtdf2@plt +; R64-NEXT: call __gtdf2 ; R64-NEXT: bgtz a0, .LBB3_2 ; R64-NEXT: # %bb.1: ; R64-NEXT: mv s0, s1 @@ -156,7 +156,7 @@ define float @minnum_f32(float %x, float %y) nounwind { ; R32: # %bb.0: ; R32-NEXT: addi sp, sp, -16 ; R32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; R32-NEXT: call fminf@plt +; R32-NEXT: call fminf ; R32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; R32-NEXT: addi sp, sp, 16 ; R32-NEXT: ret @@ -165,7 +165,7 @@ define float @minnum_f32(float %x, float %y) nounwind { ; R64: # %bb.0: ; R64-NEXT: addi sp, sp, -16 ; R64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; R64-NEXT: call fminf@plt +; R64-NEXT: call fminf ; R64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; R64-NEXT: addi sp, sp, 16 ; R64-NEXT: ret @@ -182,7 +182,7 @@ define float @minnum_f32_nnan(float %x, float %y) nounwind { ; R32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; R32-NEXT: mv s1, a1 ; R32-NEXT: mv s0, a0 -; R32-NEXT: call __ltsf2@plt +; R32-NEXT: call __ltsf2 ; R32-NEXT: bltz a0, .LBB5_2 ; R32-NEXT: # %bb.1: ; R32-NEXT: mv s0, s1 @@ -202,7 +202,7 @@ define float @minnum_f32_nnan(float %x, float %y) nounwind { ; R64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; R64-NEXT: mv s1, a1 ; R64-NEXT: mv s0, a0 -; R64-NEXT: call __ltsf2@plt +; R64-NEXT: call __ltsf2 ; R64-NEXT: bltz a0, .LBB5_2 ; R64-NEXT: # %bb.1: ; R64-NEXT: mv s0, s1 @@ -222,7 +222,7 @@ define double @minnum_f64(double %x, double %y) nounwind { ; R32: # %bb.0: ; R32-NEXT: addi sp, sp, -16 ; R32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; R32-NEXT: call fmin@plt +; R32-NEXT: call fmin ; R32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; R32-NEXT: addi sp, sp, 16 ; R32-NEXT: ret @@ -231,7 +231,7 @@ define double @minnum_f64(double %x, double %y) nounwind { ; R64: # %bb.0: ; R64-NEXT: addi sp, sp, -16 ; R64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; R64-NEXT: call fmin@plt +; R64-NEXT: call fmin ; R64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; R64-NEXT: addi sp, sp, 16 ; R64-NEXT: ret @@ -252,7 +252,7 @@ define double @minnum_f64_fast(double %x, double %y) nounwind { ; R32-NEXT: mv s2, a2 ; R32-NEXT: mv s0, a1 ; R32-NEXT: mv s3, a0 -; R32-NEXT: call __ltdf2@plt +; R32-NEXT: call __ltdf2 ; R32-NEXT: mv a1, a0 ; R32-NEXT: mv a0, s3 ; R32-NEXT: bltz a1, .LBB7_2 @@ -262,7 +262,7 @@ define double @minnum_f64_fast(double %x, double %y) nounwind { ; R32-NEXT: mv a1, s0 ; R32-NEXT: mv a2, s2 ; R32-NEXT: mv a3, s1 -; R32-NEXT: call __ltdf2@plt +; R32-NEXT: call __ltdf2 ; R32-NEXT: bltz a0, .LBB7_4 ; R32-NEXT: # %bb.3: ; R32-NEXT: mv s0, s1 @@ -285,7 +285,7 @@ define double @minnum_f64_fast(double %x, double %y) nounwind { ; R64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; R64-NEXT: mv s1, a1 ; R64-NEXT: mv s0, a0 -; R64-NEXT: call __ltdf2@plt +; R64-NEXT: call __ltdf2 ; R64-NEXT: bltz a0, .LBB7_2 ; R64-NEXT: # %bb.1: ; R64-NEXT: mv s0, s1 diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll index 321857b2104e..7c2f775bca14 100644 --- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll +++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll @@ -773,7 +773,7 @@ define i64 @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind { ; RV32I-NEXT: .LBB20_5: # %for.body ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call f@plt +; RV32I-NEXT: call f ; RV32I-NEXT: lw a0, 12(s7) ; RV32I-NEXT: lw a1, 8(s7) ; RV32I-NEXT: add a0, a0, s4 @@ -838,7 +838,7 @@ define i64 @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind { ; RV32I-MEDIUM-NEXT: .LBB20_5: # %for.body ; RV32I-MEDIUM-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-MEDIUM-NEXT: mv a0, s0 -; RV32I-MEDIUM-NEXT: call f@plt +; RV32I-MEDIUM-NEXT: call f ; RV32I-MEDIUM-NEXT: lw a0, 12(s7) ; RV32I-MEDIUM-NEXT: lw a1, 8(s7) ; RV32I-MEDIUM-NEXT: add a0, a0, s4 @@ -885,7 +885,7 @@ define i64 @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind { ; RV64I-NEXT: .LBB20_2: # %for.body ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call f@plt +; RV64I-NEXT: call f ; RV64I-NEXT: ld a0, 8(s3) ; RV64I-NEXT: addi s1, s1, -1 ; RV64I-NEXT: add s2, a0, s2 @@ -921,7 +921,7 @@ define i64 @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind { ; RV64I-MEDIUM-NEXT: .LBB20_2: # %for.body ; RV64I-MEDIUM-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-MEDIUM-NEXT: mv a0, s0 -; RV64I-MEDIUM-NEXT: call f@plt +; RV64I-MEDIUM-NEXT: call f ; RV64I-MEDIUM-NEXT: ld a0, 8(s3) ; RV64I-MEDIUM-NEXT: addi s1, s1, -1 ; RV64I-MEDIUM-NEXT: add s2, a0, s2 diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll index f2079e314d51..f6a53a9d76dd 100644 --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -14,7 +14,7 @@ define i8 @load8(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_load_1@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_load_1 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -38,7 +38,7 @@ define i8 @load8(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_1@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_1 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -67,7 +67,7 @@ define void @store8(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a2, 5 ; RV32-NO-ATOMIC-NEXT: li a1, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_store_1@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_store_1 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -91,7 +91,7 @@ define void @store8(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a2, 5 ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_1@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_1 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -119,7 +119,7 @@ define i8 @rmw8(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_1@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_1 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -129,7 +129,7 @@ define i8 @rmw8(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_1@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_1 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -139,7 +139,7 @@ define i8 @rmw8(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_1@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_1 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -150,7 +150,7 @@ define i8 @rmw8(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_1@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_1 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -160,7 +160,7 @@ define i8 @rmw8(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_1@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_1 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -170,7 +170,7 @@ define i8 @rmw8(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_1@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_1 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -188,7 +188,7 @@ define i8 @cmpxchg8(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_1@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_1 ; RV32-NO-ATOMIC-NEXT: lbu a0, 11(sp) ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -200,7 +200,7 @@ define i8 @cmpxchg8(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a2, 1 ; RV32-ATOMIC-NEXT: li a1, 0 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_1@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_1 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -211,7 +211,7 @@ define i8 @cmpxchg8(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV32-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_1@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_1 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -225,7 +225,7 @@ define i8 @cmpxchg8(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_1@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_1 ; RV64-NO-ATOMIC-NEXT: lbu a0, 7(sp) ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -237,7 +237,7 @@ define i8 @cmpxchg8(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a2, 1 ; RV64-ATOMIC-NEXT: li a1, 0 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_1@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_1 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -248,7 +248,7 @@ define i8 @cmpxchg8(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV64-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_1@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_1 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -263,7 +263,7 @@ define i16 @load16(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_load_2@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_load_2 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -287,7 +287,7 @@ define i16 @load16(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_2@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_2 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -316,7 +316,7 @@ define void @store16(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a2, 5 ; RV32-NO-ATOMIC-NEXT: li a1, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_store_2@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_store_2 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -340,7 +340,7 @@ define void @store16(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a2, 5 ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_2@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_2 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -368,7 +368,7 @@ define i16 @rmw16(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_2@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_2 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -378,7 +378,7 @@ define i16 @rmw16(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_2@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_2 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -388,7 +388,7 @@ define i16 @rmw16(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_2@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_2 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -399,7 +399,7 @@ define i16 @rmw16(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_2@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_2 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -409,7 +409,7 @@ define i16 @rmw16(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_2@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_2 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -419,7 +419,7 @@ define i16 @rmw16(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_2@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_2 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -437,7 +437,7 @@ define i16 @cmpxchg16(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_2@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_2 ; RV32-NO-ATOMIC-NEXT: lh a0, 10(sp) ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -449,7 +449,7 @@ define i16 @cmpxchg16(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a2, 1 ; RV32-ATOMIC-NEXT: li a1, 0 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_2@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_2 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -460,7 +460,7 @@ define i16 @cmpxchg16(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV32-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_2@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_2 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -474,7 +474,7 @@ define i16 @cmpxchg16(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_2@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_2 ; RV64-NO-ATOMIC-NEXT: lh a0, 6(sp) ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -486,7 +486,7 @@ define i16 @cmpxchg16(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a2, 1 ; RV64-ATOMIC-NEXT: li a1, 0 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_2@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_2 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -497,7 +497,7 @@ define i16 @cmpxchg16(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV64-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_2@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_2 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -512,7 +512,7 @@ define i32 @load32_unordered(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -532,7 +532,7 @@ define i32 @load32_unordered(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -556,7 +556,7 @@ define i32 @load32_monotonic(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -576,7 +576,7 @@ define i32 @load32_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -600,7 +600,7 @@ define i32 @load32_acquire(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 2 -; RV32-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -622,7 +622,7 @@ define i32 @load32_acquire(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 2 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -648,7 +648,7 @@ define i32 @load32_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -672,7 +672,7 @@ define i32 @load32_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -701,7 +701,7 @@ define void @store32_unordered(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 0 ; RV32-NO-ATOMIC-NEXT: li a2, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -722,7 +722,7 @@ define void @store32_unordered(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 ; RV64-NO-ATOMIC-NEXT: li a2, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -747,7 +747,7 @@ define void @store32_monotonic(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 0 ; RV32-NO-ATOMIC-NEXT: li a2, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -768,7 +768,7 @@ define void @store32_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 ; RV64-NO-ATOMIC-NEXT: li a2, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -793,7 +793,7 @@ define void @store32_release(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a2, 3 ; RV32-NO-ATOMIC-NEXT: li a1, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -816,7 +816,7 @@ define void @store32_release(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a2, 3 ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -843,7 +843,7 @@ define void @store32_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a2, 5 ; RV32-NO-ATOMIC-NEXT: li a1, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -867,7 +867,7 @@ define void @store32_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a2, 5 ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -895,7 +895,7 @@ define i32 @rmw32_add_monotonic(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -905,7 +905,7 @@ define i32 @rmw32_add_monotonic(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -915,7 +915,7 @@ define i32 @rmw32_add_monotonic(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -926,7 +926,7 @@ define i32 @rmw32_add_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -936,7 +936,7 @@ define i32 @rmw32_add_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -946,7 +946,7 @@ define i32 @rmw32_add_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -961,7 +961,7 @@ define i32 @rmw32_add_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_add_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -971,7 +971,7 @@ define i32 @rmw32_add_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_add_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -981,7 +981,7 @@ define i32 @rmw32_add_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -992,7 +992,7 @@ define i32 @rmw32_add_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -1002,7 +1002,7 @@ define i32 @rmw32_add_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1012,7 +1012,7 @@ define i32 @rmw32_add_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1027,7 +1027,7 @@ define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_sub_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_sub_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -1037,7 +1037,7 @@ define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_sub_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_sub_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1047,7 +1047,7 @@ define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_sub_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_sub_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1058,7 +1058,7 @@ define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_sub_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_sub_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -1068,7 +1068,7 @@ define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_sub_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_sub_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1078,7 +1078,7 @@ define i32 @rmw32_sub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_sub_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_sub_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1093,7 +1093,7 @@ define i32 @rmw32_and_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_and_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_and_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -1103,7 +1103,7 @@ define i32 @rmw32_and_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_and_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_and_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1113,7 +1113,7 @@ define i32 @rmw32_and_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_and_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_and_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1124,7 +1124,7 @@ define i32 @rmw32_and_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_and_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_and_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -1134,7 +1134,7 @@ define i32 @rmw32_and_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_and_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_and_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1144,7 +1144,7 @@ define i32 @rmw32_and_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_and_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_and_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1159,7 +1159,7 @@ define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_nand_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_nand_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -1169,7 +1169,7 @@ define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_nand_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_nand_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1179,7 +1179,7 @@ define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_nand_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_nand_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1190,7 +1190,7 @@ define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_nand_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_nand_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -1200,7 +1200,7 @@ define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_nand_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_nand_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1210,7 +1210,7 @@ define i32 @rmw32_nand_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_nand_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_nand_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1225,7 +1225,7 @@ define i32 @rmw32_or_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_or_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_or_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -1235,7 +1235,7 @@ define i32 @rmw32_or_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_or_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_or_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1245,7 +1245,7 @@ define i32 @rmw32_or_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_or_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_or_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1256,7 +1256,7 @@ define i32 @rmw32_or_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_or_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_or_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -1266,7 +1266,7 @@ define i32 @rmw32_or_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_or_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_or_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1276,7 +1276,7 @@ define i32 @rmw32_or_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_or_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_or_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1291,7 +1291,7 @@ define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_xor_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_fetch_xor_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -1301,7 +1301,7 @@ define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_xor_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_xor_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1311,7 +1311,7 @@ define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_xor_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_xor_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1322,7 +1322,7 @@ define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_xor_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_xor_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -1332,7 +1332,7 @@ define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_xor_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_xor_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1342,7 +1342,7 @@ define i32 @rmw32_xor_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_xor_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_xor_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1366,7 +1366,7 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB23_4 ; RV32-NO-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start @@ -1389,7 +1389,7 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_max_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_max_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1399,7 +1399,7 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_max_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_max_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1419,7 +1419,7 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB23_4 ; RV64-NO-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start @@ -1443,7 +1443,7 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_max_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_max_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1453,7 +1453,7 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_max_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_max_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1479,7 +1479,7 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV32-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start @@ -1503,7 +1503,7 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_min_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_min_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1513,7 +1513,7 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_min_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_min_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1535,7 +1535,7 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV64-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start @@ -1559,7 +1559,7 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_min_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_min_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1569,7 +1569,7 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_min_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_min_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1594,7 +1594,7 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: beqz a0, .LBB25_1 ; RV32-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -1609,7 +1609,7 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_umax_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_umax_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1619,7 +1619,7 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umax_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umax_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1639,7 +1639,7 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB25_4 ; RV64-NO-ATOMIC-NEXT: .LBB25_2: # %atomicrmw.start @@ -1663,7 +1663,7 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_umax_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_umax_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1673,7 +1673,7 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umax_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umax_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1699,7 +1699,7 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV32-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start @@ -1723,7 +1723,7 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_fetch_and_umin_4@plt +; RV32-ATOMIC-NEXT: call __sync_fetch_and_umin_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1733,7 +1733,7 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umin_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umin_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1755,7 +1755,7 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV64-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start @@ -1779,7 +1779,7 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_umin_4@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_umin_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1789,7 +1789,7 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umin_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umin_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1804,7 +1804,7 @@ define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: li a1, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret @@ -1814,7 +1814,7 @@ define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a1, 1 -; RV32-ATOMIC-NEXT: call __sync_lock_test_and_set_4@plt +; RV32-ATOMIC-NEXT: call __sync_lock_test_and_set_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -1824,7 +1824,7 @@ define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_lock_test_and_set_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_lock_test_and_set_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -1835,7 +1835,7 @@ define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_exchange_4 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -1845,7 +1845,7 @@ define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_lock_test_and_set_4@plt +; RV64-ATOMIC-NEXT: call __sync_lock_test_and_set_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -1855,7 +1855,7 @@ define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_lock_test_and_set_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_lock_test_and_set_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -1876,14 +1876,14 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: lui a1, 260096 ; RV32-NO-ATOMIC-NEXT: mv a0, s1 -; RV32-NO-ATOMIC-NEXT: call __addsf3@plt +; RV32-NO-ATOMIC-NEXT: call __addsf3 ; RV32-NO-ATOMIC-NEXT: mv a2, a0 ; RV32-NO-ATOMIC-NEXT: sw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: mv a1, sp ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: beqz a0, .LBB28_1 ; RV32-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -1906,11 +1906,11 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-NEXT: mv s1, a0 ; RV32-ATOMIC-NEXT: lui a1, 260096 -; RV32-ATOMIC-NEXT: call __addsf3@plt +; RV32-ATOMIC-NEXT: call __addsf3 ; RV32-ATOMIC-NEXT: mv a2, a0 ; RV32-ATOMIC-NEXT: mv a0, s0 ; RV32-ATOMIC-NEXT: mv a1, s1 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-NEXT: bne a0, s1, .LBB28_1 ; RV32-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1931,11 +1931,11 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV32-ATOMIC-TRAILING-NEXT: lui a1, 260096 -; RV32-ATOMIC-TRAILING-NEXT: call __addsf3@plt +; RV32-ATOMIC-TRAILING-NEXT: call __addsf3 ; RV32-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV32-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV32-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-TRAILING-NEXT: bne a0, s1, .LBB28_1 ; RV32-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1956,14 +1956,14 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: lui a1, 260096 ; RV64-NO-ATOMIC-NEXT: mv a0, s1 -; RV64-NO-ATOMIC-NEXT: call __addsf3@plt +; RV64-NO-ATOMIC-NEXT: call __addsf3 ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB28_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -1987,12 +1987,12 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: lui a1, 260096 ; RV64-ATOMIC-NEXT: mv a0, s1 -; RV64-ATOMIC-NEXT: call __addsf3@plt +; RV64-ATOMIC-NEXT: call __addsf3 ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: sext.w s2, s1 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-NEXT: mv s1, a0 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB28_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2017,12 +2017,12 @@ define float @rmw32_fadd_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: lui a1, 260096 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s1 -; RV64-ATOMIC-TRAILING-NEXT: call __addsf3@plt +; RV64-ATOMIC-TRAILING-NEXT: call __addsf3 ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: sext.w s2, s1 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB28_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end @@ -2050,14 +2050,14 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: lui a1, 784384 ; RV32-NO-ATOMIC-NEXT: mv a0, s1 -; RV32-NO-ATOMIC-NEXT: call __addsf3@plt +; RV32-NO-ATOMIC-NEXT: call __addsf3 ; RV32-NO-ATOMIC-NEXT: mv a2, a0 ; RV32-NO-ATOMIC-NEXT: sw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: mv a1, sp ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: beqz a0, .LBB29_1 ; RV32-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2080,11 +2080,11 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-NEXT: mv s1, a0 ; RV32-ATOMIC-NEXT: lui a1, 784384 -; RV32-ATOMIC-NEXT: call __addsf3@plt +; RV32-ATOMIC-NEXT: call __addsf3 ; RV32-ATOMIC-NEXT: mv a2, a0 ; RV32-ATOMIC-NEXT: mv a0, s0 ; RV32-ATOMIC-NEXT: mv a1, s1 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-NEXT: bne a0, s1, .LBB29_1 ; RV32-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2105,11 +2105,11 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV32-ATOMIC-TRAILING-NEXT: lui a1, 784384 -; RV32-ATOMIC-TRAILING-NEXT: call __addsf3@plt +; RV32-ATOMIC-TRAILING-NEXT: call __addsf3 ; RV32-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV32-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV32-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-TRAILING-NEXT: bne a0, s1, .LBB29_1 ; RV32-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2130,14 +2130,14 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: lui a1, 784384 ; RV64-NO-ATOMIC-NEXT: mv a0, s1 -; RV64-NO-ATOMIC-NEXT: call __addsf3@plt +; RV64-NO-ATOMIC-NEXT: call __addsf3 ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB29_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2161,12 +2161,12 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: lui a1, 784384 ; RV64-ATOMIC-NEXT: mv a0, s1 -; RV64-ATOMIC-NEXT: call __addsf3@plt +; RV64-ATOMIC-NEXT: call __addsf3 ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: sext.w s2, s1 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-NEXT: mv s1, a0 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB29_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2191,12 +2191,12 @@ define float @rmw32_fsub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: lui a1, 784384 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s1 -; RV64-ATOMIC-TRAILING-NEXT: call __addsf3@plt +; RV64-ATOMIC-TRAILING-NEXT: call __addsf3 ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: sext.w s2, s1 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB29_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end @@ -2224,14 +2224,14 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: lui a1, 260096 ; RV32-NO-ATOMIC-NEXT: mv a0, s1 -; RV32-NO-ATOMIC-NEXT: call fminf@plt +; RV32-NO-ATOMIC-NEXT: call fminf ; RV32-NO-ATOMIC-NEXT: mv a2, a0 ; RV32-NO-ATOMIC-NEXT: sw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: mv a1, sp ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: beqz a0, .LBB30_1 ; RV32-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2254,11 +2254,11 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-NEXT: mv s1, a0 ; RV32-ATOMIC-NEXT: lui a1, 260096 -; RV32-ATOMIC-NEXT: call fminf@plt +; RV32-ATOMIC-NEXT: call fminf ; RV32-ATOMIC-NEXT: mv a2, a0 ; RV32-ATOMIC-NEXT: mv a0, s0 ; RV32-ATOMIC-NEXT: mv a1, s1 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-NEXT: bne a0, s1, .LBB30_1 ; RV32-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2279,11 +2279,11 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV32-ATOMIC-TRAILING-NEXT: lui a1, 260096 -; RV32-ATOMIC-TRAILING-NEXT: call fminf@plt +; RV32-ATOMIC-TRAILING-NEXT: call fminf ; RV32-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV32-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV32-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-TRAILING-NEXT: bne a0, s1, .LBB30_1 ; RV32-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2304,14 +2304,14 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: lui a1, 260096 ; RV64-NO-ATOMIC-NEXT: mv a0, s1 -; RV64-NO-ATOMIC-NEXT: call fminf@plt +; RV64-NO-ATOMIC-NEXT: call fminf ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB30_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2335,12 +2335,12 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: lui a1, 260096 ; RV64-ATOMIC-NEXT: mv a0, s1 -; RV64-ATOMIC-NEXT: call fminf@plt +; RV64-ATOMIC-NEXT: call fminf ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: sext.w s2, s1 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-NEXT: mv s1, a0 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB30_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2365,12 +2365,12 @@ define float @rmw32_fmin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: lui a1, 260096 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s1 -; RV64-ATOMIC-TRAILING-NEXT: call fminf@plt +; RV64-ATOMIC-TRAILING-NEXT: call fminf ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: sext.w s2, s1 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB30_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end @@ -2398,14 +2398,14 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: lui a1, 260096 ; RV32-NO-ATOMIC-NEXT: mv a0, s1 -; RV32-NO-ATOMIC-NEXT: call fmaxf@plt +; RV32-NO-ATOMIC-NEXT: call fmaxf ; RV32-NO-ATOMIC-NEXT: mv a2, a0 ; RV32-NO-ATOMIC-NEXT: sw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: mv a1, sp ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw s1, 0(sp) ; RV32-NO-ATOMIC-NEXT: beqz a0, .LBB31_1 ; RV32-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2428,11 +2428,11 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-NEXT: mv s1, a0 ; RV32-ATOMIC-NEXT: lui a1, 260096 -; RV32-ATOMIC-NEXT: call fmaxf@plt +; RV32-ATOMIC-NEXT: call fmaxf ; RV32-ATOMIC-NEXT: mv a2, a0 ; RV32-ATOMIC-NEXT: mv a0, s0 ; RV32-ATOMIC-NEXT: mv a1, s1 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-NEXT: bne a0, s1, .LBB31_1 ; RV32-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2453,11 +2453,11 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV32-ATOMIC-TRAILING-NEXT: lui a1, 260096 -; RV32-ATOMIC-TRAILING-NEXT: call fmaxf@plt +; RV32-ATOMIC-TRAILING-NEXT: call fmaxf ; RV32-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV32-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV32-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-TRAILING-NEXT: bne a0, s1, .LBB31_1 ; RV32-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2478,14 +2478,14 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: lui a1, 260096 ; RV64-NO-ATOMIC-NEXT: mv a0, s1 -; RV64-NO-ATOMIC-NEXT: call fmaxf@plt +; RV64-NO-ATOMIC-NEXT: call fmaxf ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw s1, 4(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB31_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2509,12 +2509,12 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: lui a1, 260096 ; RV64-ATOMIC-NEXT: mv a0, s1 -; RV64-ATOMIC-NEXT: call fmaxf@plt +; RV64-ATOMIC-NEXT: call fmaxf ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: sext.w s2, s1 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-NEXT: mv s1, a0 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB31_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -2539,12 +2539,12 @@ define float @rmw32_fmax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: lui a1, 260096 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s1 -; RV64-ATOMIC-TRAILING-NEXT: call fmaxf@plt +; RV64-ATOMIC-TRAILING-NEXT: call fmaxf ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: sext.w s2, s1 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-TRAILING-NEXT: mv s1, a0 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB31_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end @@ -2569,7 +2569,7 @@ define i32 @cmpxchg32_monotonic(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a3, 0 ; RV32-NO-ATOMIC-NEXT: li a4, 0 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw a0, 8(sp) ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -2581,7 +2581,7 @@ define i32 @cmpxchg32_monotonic(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a2, 1 ; RV32-ATOMIC-NEXT: li a1, 0 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -2592,7 +2592,7 @@ define i32 @cmpxchg32_monotonic(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV32-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -2606,7 +2606,7 @@ define i32 @cmpxchg32_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a3, 0 ; RV64-NO-ATOMIC-NEXT: li a4, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw a0, 4(sp) ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -2618,7 +2618,7 @@ define i32 @cmpxchg32_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a2, 1 ; RV64-ATOMIC-NEXT: li a1, 0 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -2629,7 +2629,7 @@ define i32 @cmpxchg32_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV64-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -2648,7 +2648,7 @@ define i32 @cmpxchg32_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 -; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV32-NO-ATOMIC-NEXT: lw a0, 8(sp) ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -2660,7 +2660,7 @@ define i32 @cmpxchg32_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: li a2, 1 ; RV32-ATOMIC-NEXT: li a1, 0 -; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-NEXT: ret @@ -2671,7 +2671,7 @@ define i32 @cmpxchg32_seq_cst(ptr %p) nounwind { ; RV32-ATOMIC-TRAILING-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV32-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV32-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV32-ATOMIC-TRAILING-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: ret @@ -2685,7 +2685,7 @@ define i32 @cmpxchg32_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4 ; RV64-NO-ATOMIC-NEXT: lw a0, 4(sp) ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -2697,7 +2697,7 @@ define i32 @cmpxchg32_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a2, 1 ; RV64-ATOMIC-NEXT: li a1, 0 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -2708,7 +2708,7 @@ define i32 @cmpxchg32_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV64-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_4 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -2723,7 +2723,7 @@ define i64 @load64_unordered(ptr %p) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a1, 0 -; RV32-NEXT: call __atomic_load_8@plt +; RV32-NEXT: call __atomic_load_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2733,7 +2733,7 @@ define i64 @load64_unordered(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -2757,7 +2757,7 @@ define i64 @load64_monotonic(ptr %p) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a1, 0 -; RV32-NEXT: call __atomic_load_8@plt +; RV32-NEXT: call __atomic_load_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2767,7 +2767,7 @@ define i64 @load64_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -2791,7 +2791,7 @@ define i64 @load64_acquire(ptr %p) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a1, 2 -; RV32-NEXT: call __atomic_load_8@plt +; RV32-NEXT: call __atomic_load_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2801,7 +2801,7 @@ define i64 @load64_acquire(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 2 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -2827,7 +2827,7 @@ define i64 @load64_seq_cst(ptr %p) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a1, 5 -; RV32-NEXT: call __atomic_load_8@plt +; RV32-NEXT: call __atomic_load_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2837,7 +2837,7 @@ define i64 @load64_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_load_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_load_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -2867,7 +2867,7 @@ define void @store64_unordered(ptr %p) nounwind { ; RV32-NEXT: li a1, 0 ; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __atomic_store_8@plt +; RV32-NEXT: call __atomic_store_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2878,7 +2878,7 @@ define void @store64_unordered(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 ; RV64-NO-ATOMIC-NEXT: li a2, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -2904,7 +2904,7 @@ define void @store64_monotonic(ptr %p) nounwind { ; RV32-NEXT: li a1, 0 ; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __atomic_store_8@plt +; RV32-NEXT: call __atomic_store_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2915,7 +2915,7 @@ define void @store64_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 0 ; RV64-NO-ATOMIC-NEXT: li a2, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -2941,7 +2941,7 @@ define void @store64_release(ptr %p) nounwind { ; RV32-NEXT: li a3, 3 ; RV32-NEXT: li a1, 0 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_store_8@plt +; RV32-NEXT: call __atomic_store_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2952,7 +2952,7 @@ define void @store64_release(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a2, 3 ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -2980,7 +2980,7 @@ define void @store64(ptr %p) nounwind { ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a1, 0 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_store_8@plt +; RV32-NEXT: call __atomic_store_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -2991,7 +2991,7 @@ define void @store64(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a2, 5 ; RV64-NO-ATOMIC-NEXT: li a1, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_store_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_store_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3020,7 +3020,7 @@ define i64 @rmw64_monotonic(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __atomic_fetch_add_8@plt +; RV32-NEXT: call __atomic_fetch_add_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3031,7 +3031,7 @@ define i64 @rmw64_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3041,7 +3041,7 @@ define i64 @rmw64_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3051,7 +3051,7 @@ define i64 @rmw64_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3067,7 +3067,7 @@ define i64 @rmw64_add_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_fetch_add_8@plt +; RV32-NEXT: call __atomic_fetch_add_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3078,7 +3078,7 @@ define i64 @rmw64_add_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_add_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3088,7 +3088,7 @@ define i64 @rmw64_add_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_add_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3098,7 +3098,7 @@ define i64 @rmw64_add_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_add_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3114,7 +3114,7 @@ define i64 @rmw64_sub_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_fetch_sub_8@plt +; RV32-NEXT: call __atomic_fetch_sub_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3125,7 +3125,7 @@ define i64 @rmw64_sub_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_sub_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_sub_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3135,7 +3135,7 @@ define i64 @rmw64_sub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_sub_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_sub_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3145,7 +3145,7 @@ define i64 @rmw64_sub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_sub_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_sub_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3161,7 +3161,7 @@ define i64 @rmw64_and_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_fetch_and_8@plt +; RV32-NEXT: call __atomic_fetch_and_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3172,7 +3172,7 @@ define i64 @rmw64_and_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_and_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_and_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3182,7 +3182,7 @@ define i64 @rmw64_and_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_and_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_and_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3192,7 +3192,7 @@ define i64 @rmw64_and_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_and_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_and_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3208,7 +3208,7 @@ define i64 @rmw64_nand_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_fetch_nand_8@plt +; RV32-NEXT: call __atomic_fetch_nand_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3219,7 +3219,7 @@ define i64 @rmw64_nand_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_nand_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_nand_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3229,7 +3229,7 @@ define i64 @rmw64_nand_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_nand_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_nand_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3239,7 +3239,7 @@ define i64 @rmw64_nand_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_nand_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_nand_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3255,7 +3255,7 @@ define i64 @rmw64_or_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_fetch_or_8@plt +; RV32-NEXT: call __atomic_fetch_or_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3266,7 +3266,7 @@ define i64 @rmw64_or_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_or_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_or_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3276,7 +3276,7 @@ define i64 @rmw64_or_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_or_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_or_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3286,7 +3286,7 @@ define i64 @rmw64_or_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_or_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_or_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3302,7 +3302,7 @@ define i64 @rmw64_xor_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_fetch_xor_8@plt +; RV32-NEXT: call __atomic_fetch_xor_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3313,7 +3313,7 @@ define i64 @rmw64_xor_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_xor_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_fetch_xor_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3323,7 +3323,7 @@ define i64 @rmw64_xor_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_xor_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_xor_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3333,7 +3333,7 @@ define i64 @rmw64_xor_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_xor_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_xor_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3361,7 +3361,7 @@ define i64 @rmw64_max_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a4, 0(sp) ; RV32-NEXT: bnez a0, .LBB49_6 @@ -3405,7 +3405,7 @@ define i64 @rmw64_max_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB49_4 ; RV64-NO-ATOMIC-NEXT: .LBB49_2: # %atomicrmw.start @@ -3428,7 +3428,7 @@ define i64 @rmw64_max_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_max_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_max_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3438,7 +3438,7 @@ define i64 @rmw64_max_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_max_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_max_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3466,7 +3466,7 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a4, 0(sp) ; RV32-NEXT: bnez a0, .LBB50_6 @@ -3511,7 +3511,7 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB50_4 ; RV64-NO-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start @@ -3535,7 +3535,7 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_min_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_min_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3545,7 +3545,7 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_min_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_min_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3573,7 +3573,7 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a4, 0(sp) ; RV32-NEXT: bnez a0, .LBB51_4 @@ -3612,7 +3612,7 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB51_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -3627,7 +3627,7 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_umax_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_umax_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3637,7 +3637,7 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umax_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umax_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3665,7 +3665,7 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a4, 0(sp) ; RV32-NEXT: bnez a0, .LBB52_4 @@ -3704,7 +3704,7 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB52_4 ; RV64-NO-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start @@ -3728,7 +3728,7 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_fetch_and_umin_8@plt +; RV64-ATOMIC-NEXT: call __sync_fetch_and_umin_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3738,7 +3738,7 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umin_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_fetch_and_umin_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3754,7 +3754,7 @@ define i64 @rmw64_xchg_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a3, 5 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __atomic_exchange_8@plt +; RV32-NEXT: call __atomic_exchange_8 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -3765,7 +3765,7 @@ define i64 @rmw64_xchg_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: li a1, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-NO-ATOMIC-NEXT: ret @@ -3775,7 +3775,7 @@ define i64 @rmw64_xchg_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a1, 1 -; RV64-ATOMIC-NEXT: call __sync_lock_test_and_set_8@plt +; RV64-ATOMIC-NEXT: call __sync_lock_test_and_set_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -3785,7 +3785,7 @@ define i64 @rmw64_xchg_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a1, 1 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_lock_test_and_set_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_lock_test_and_set_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -3810,7 +3810,7 @@ define double @rmw64_fadd_seq_cst(ptr %p) nounwind { ; RV32-NEXT: mv a0, s2 ; RV32-NEXT: mv a1, s1 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __adddf3@plt +; RV32-NEXT: call __adddf3 ; RV32-NEXT: mv a2, a0 ; RV32-NEXT: mv a3, a1 ; RV32-NEXT: sw s2, 8(sp) @@ -3819,7 +3819,7 @@ define double @rmw64_fadd_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw s1, 12(sp) ; RV32-NEXT: lw s2, 8(sp) ; RV32-NEXT: beqz a0, .LBB54_1 @@ -3848,14 +3848,14 @@ define double @rmw64_fadd_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 ; RV64-NO-ATOMIC-NEXT: mv a1, s1 -; RV64-NO-ATOMIC-NEXT: call __adddf3@plt +; RV64-NO-ATOMIC-NEXT: call __adddf3 ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sd s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB54_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -3882,11 +3882,11 @@ define double @rmw64_fadd_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 ; RV64-ATOMIC-NEXT: mv a1, s1 -; RV64-ATOMIC-NEXT: call __adddf3@plt +; RV64-ATOMIC-NEXT: call __adddf3 ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB54_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -3911,11 +3911,11 @@ define double @rmw64_fadd_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: mv s2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV64-ATOMIC-TRAILING-NEXT: call __adddf3@plt +; RV64-ATOMIC-TRAILING-NEXT: call __adddf3 ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB54_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -3945,7 +3945,7 @@ define double @rmw64_fsub_seq_cst(ptr %p) nounwind { ; RV32-NEXT: mv a0, s2 ; RV32-NEXT: mv a1, s1 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call __adddf3@plt +; RV32-NEXT: call __adddf3 ; RV32-NEXT: mv a2, a0 ; RV32-NEXT: mv a3, a1 ; RV32-NEXT: sw s2, 8(sp) @@ -3954,7 +3954,7 @@ define double @rmw64_fsub_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw s1, 12(sp) ; RV32-NEXT: lw s2, 8(sp) ; RV32-NEXT: beqz a0, .LBB55_1 @@ -3983,14 +3983,14 @@ define double @rmw64_fsub_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 ; RV64-NO-ATOMIC-NEXT: mv a1, s1 -; RV64-NO-ATOMIC-NEXT: call __adddf3@plt +; RV64-NO-ATOMIC-NEXT: call __adddf3 ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sd s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB55_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -4017,11 +4017,11 @@ define double @rmw64_fsub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 ; RV64-ATOMIC-NEXT: mv a1, s1 -; RV64-ATOMIC-NEXT: call __adddf3@plt +; RV64-ATOMIC-NEXT: call __adddf3 ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB55_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -4046,11 +4046,11 @@ define double @rmw64_fsub_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: mv s2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV64-ATOMIC-TRAILING-NEXT: call __adddf3@plt +; RV64-ATOMIC-TRAILING-NEXT: call __adddf3 ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB55_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -4080,7 +4080,7 @@ define double @rmw64_fmin_seq_cst(ptr %p) nounwind { ; RV32-NEXT: mv a0, s2 ; RV32-NEXT: mv a1, s1 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call fmin@plt +; RV32-NEXT: call fmin ; RV32-NEXT: mv a2, a0 ; RV32-NEXT: mv a3, a1 ; RV32-NEXT: sw s2, 8(sp) @@ -4089,7 +4089,7 @@ define double @rmw64_fmin_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw s1, 12(sp) ; RV32-NEXT: lw s2, 8(sp) ; RV32-NEXT: beqz a0, .LBB56_1 @@ -4118,14 +4118,14 @@ define double @rmw64_fmin_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 ; RV64-NO-ATOMIC-NEXT: mv a1, s1 -; RV64-NO-ATOMIC-NEXT: call fmin@plt +; RV64-NO-ATOMIC-NEXT: call fmin ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sd s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB56_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -4152,11 +4152,11 @@ define double @rmw64_fmin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 ; RV64-ATOMIC-NEXT: mv a1, s1 -; RV64-ATOMIC-NEXT: call fmin@plt +; RV64-ATOMIC-NEXT: call fmin ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB56_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -4181,11 +4181,11 @@ define double @rmw64_fmin_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: mv s2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV64-ATOMIC-TRAILING-NEXT: call fmin@plt +; RV64-ATOMIC-TRAILING-NEXT: call fmin ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB56_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -4215,7 +4215,7 @@ define double @rmw64_fmax_seq_cst(ptr %p) nounwind { ; RV32-NEXT: mv a0, s2 ; RV32-NEXT: mv a1, s1 ; RV32-NEXT: li a2, 0 -; RV32-NEXT: call fmax@plt +; RV32-NEXT: call fmax ; RV32-NEXT: mv a2, a0 ; RV32-NEXT: mv a3, a1 ; RV32-NEXT: sw s2, 8(sp) @@ -4224,7 +4224,7 @@ define double @rmw64_fmax_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a0, s0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw s1, 12(sp) ; RV32-NEXT: lw s2, 8(sp) ; RV32-NEXT: beqz a0, .LBB57_1 @@ -4253,14 +4253,14 @@ define double @rmw64_fmax_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 ; RV64-NO-ATOMIC-NEXT: mv a1, s1 -; RV64-NO-ATOMIC-NEXT: call fmax@plt +; RV64-NO-ATOMIC-NEXT: call fmax ; RV64-NO-ATOMIC-NEXT: mv a2, a0 ; RV64-NO-ATOMIC-NEXT: sd s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld s2, 8(sp) ; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB57_1 ; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end @@ -4287,11 +4287,11 @@ define double @rmw64_fmax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 ; RV64-ATOMIC-NEXT: mv a1, s1 -; RV64-ATOMIC-NEXT: call fmax@plt +; RV64-ATOMIC-NEXT: call fmax ; RV64-ATOMIC-NEXT: mv a2, a0 ; RV64-ATOMIC-NEXT: mv a0, s0 ; RV64-ATOMIC-NEXT: mv a1, s2 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-NEXT: bne a0, s2, .LBB57_1 ; RV64-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -4316,11 +4316,11 @@ define double @rmw64_fmax_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-TRAILING-NEXT: mv s2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s1 -; RV64-ATOMIC-TRAILING-NEXT: call fmax@plt +; RV64-ATOMIC-TRAILING-NEXT: call fmax ; RV64-ATOMIC-TRAILING-NEXT: mv a2, a0 ; RV64-ATOMIC-TRAILING-NEXT: mv a0, s0 ; RV64-ATOMIC-TRAILING-NEXT: mv a1, s2 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-TRAILING-NEXT: bne a0, s2, .LBB57_1 ; RV64-ATOMIC-TRAILING-NEXT: # %bb.2: # %atomicrmw.end ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -4345,7 +4345,7 @@ define i64 @cmpxchg64_monotonic(ptr %p) nounwind { ; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a4, 0 ; RV32-NEXT: li a5, 0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a0, 0(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4361,7 +4361,7 @@ define i64 @cmpxchg64_monotonic(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a3, 0 ; RV64-NO-ATOMIC-NEXT: li a4, 0 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld a0, 0(sp) ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -4373,7 +4373,7 @@ define i64 @cmpxchg64_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a2, 1 ; RV64-ATOMIC-NEXT: li a1, 0 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -4384,7 +4384,7 @@ define i64 @cmpxchg64_monotonic(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV64-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -4405,7 +4405,7 @@ define i64 @cmpxchg64_seq_cst(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __atomic_compare_exchange_8@plt +; RV32-NEXT: call __atomic_compare_exchange_8 ; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a0, 0(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4421,7 +4421,7 @@ define i64 @cmpxchg64_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 -; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt +; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8 ; RV64-NO-ATOMIC-NEXT: ld a0, 0(sp) ; RV64-NO-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 16 @@ -4433,7 +4433,7 @@ define i64 @cmpxchg64_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: li a2, 1 ; RV64-ATOMIC-NEXT: li a1, 0 -; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-NEXT: ret @@ -4444,7 +4444,7 @@ define i64 @cmpxchg64_seq_cst(ptr %p) nounwind { ; RV64-ATOMIC-TRAILING-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-TRAILING-NEXT: li a2, 1 ; RV64-ATOMIC-TRAILING-NEXT: li a1, 0 -; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8@plt +; RV64-ATOMIC-TRAILING-NEXT: call __sync_val_compare_and_swap_8 ; RV64-ATOMIC-TRAILING-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV64-ATOMIC-TRAILING-NEXT: ret @@ -4463,7 +4463,7 @@ define i128 @load128(ptr %p) nounwind { ; RV32-NEXT: li a0, 16 ; RV32-NEXT: addi a2, sp, 8 ; RV32-NEXT: li a3, 5 -; RV32-NEXT: call __atomic_load@plt +; RV32-NEXT: call __atomic_load ; RV32-NEXT: lw a0, 20(sp) ; RV32-NEXT: lw a1, 16(sp) ; RV32-NEXT: lw a2, 12(sp) @@ -4482,7 +4482,7 @@ define i128 @load128(ptr %p) nounwind { ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: li a1, 5 -; RV64-NEXT: call __atomic_load_16@plt +; RV64-NEXT: call __atomic_load_16 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -4503,7 +4503,7 @@ define void @store128(ptr %p) nounwind { ; RV32-NEXT: li a0, 16 ; RV32-NEXT: addi a2, sp, 8 ; RV32-NEXT: li a3, 5 -; RV32-NEXT: call __atomic_store@plt +; RV32-NEXT: call __atomic_store ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: ret @@ -4515,7 +4515,7 @@ define void @store128(ptr %p) nounwind { ; RV64-NEXT: li a3, 5 ; RV64-NEXT: li a1, 0 ; RV64-NEXT: li a2, 0 -; RV64-NEXT: call __atomic_store_16@plt +; RV64-NEXT: call __atomic_store_16 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -4560,7 +4560,7 @@ define i128 @rmw128(ptr %p) nounwind { ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 ; RV32-NEXT: mv a1, s0 -; RV32-NEXT: call __atomic_compare_exchange@plt +; RV32-NEXT: call __atomic_compare_exchange ; RV32-NEXT: lw a1, 28(sp) ; RV32-NEXT: lw a2, 24(sp) ; RV32-NEXT: lw a3, 20(sp) @@ -4584,7 +4584,7 @@ define i128 @rmw128(ptr %p) nounwind { ; RV64-NEXT: li a1, 1 ; RV64-NEXT: li a3, 5 ; RV64-NEXT: li a2, 0 -; RV64-NEXT: call __atomic_fetch_add_16@plt +; RV64-NEXT: call __atomic_fetch_add_16 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -4613,7 +4613,7 @@ define i128 @cmpxchg128(ptr %p) nounwind { ; RV32-NEXT: addi a3, sp, 8 ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 -; RV32-NEXT: call __atomic_compare_exchange@plt +; RV32-NEXT: call __atomic_compare_exchange ; RV32-NEXT: lw a0, 36(sp) ; RV32-NEXT: lw a1, 32(sp) ; RV32-NEXT: lw a2, 28(sp) @@ -4638,7 +4638,7 @@ define i128 @cmpxchg128(ptr %p) nounwind { ; RV64-NEXT: li a4, 5 ; RV64-NEXT: li a5, 5 ; RV64-NEXT: li a3, 0 -; RV64-NEXT: call __atomic_compare_exchange_16@plt +; RV64-NEXT: call __atomic_compare_exchange_16 ; RV64-NEXT: ld a1, 8(sp) ; RV64-NEXT: ld a0, 0(sp) ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/fp128.ll b/llvm/test/CodeGen/RISCV/fp128.ll index 77a7914cdca6..611a70c0ad8b 100644 --- a/llvm/test/CodeGen/RISCV/fp128.ll +++ b/llvm/test/CodeGen/RISCV/fp128.ll @@ -33,7 +33,7 @@ define i32 @test_load_and_cmp() nounwind { ; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: sw a2, 24(sp) -; RV32I-NEXT: call __netf2@plt +; RV32I-NEXT: call __netf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 48 @@ -71,7 +71,7 @@ define i32 @test_add_and_fptosi() nounwind { ; RV32I-NEXT: addi a1, sp, 40 ; RV32I-NEXT: addi a2, sp, 24 ; RV32I-NEXT: sw a3, 40(sp) -; RV32I-NEXT: call __addtf3@plt +; RV32I-NEXT: call __addtf3 ; RV32I-NEXT: lw a1, 56(sp) ; RV32I-NEXT: lw a0, 60(sp) ; RV32I-NEXT: lw a2, 64(sp) @@ -81,7 +81,7 @@ define i32 @test_add_and_fptosi() nounwind { ; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: addi a0, sp, 8 ; RV32I-NEXT: sw a1, 8(sp) -; RV32I-NEXT: call __fixtfsi@plt +; RV32I-NEXT: call __fixtfsi ; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 80 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/fp16-promote.ll b/llvm/test/CodeGen/RISCV/fp16-promote.ll index 2a03746b1f7e..31842316606c 100644 --- a/llvm/test/CodeGen/RISCV/fp16-promote.ll +++ b/llvm/test/CodeGen/RISCV/fp16-promote.ll @@ -19,7 +19,7 @@ define float @test_fpextend_float(ptr %p) nounwind { ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: lhu a0, 0(a0) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret @@ -35,7 +35,7 @@ define double @test_fpextend_double(ptr %p) nounwind { ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: lhu a0, 0(a0) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fcvt.d.s fa0, fa0 ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 16 @@ -52,7 +52,7 @@ define void @test_fptrunc_float(float %f, ptr %p) nounwind { ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; CHECK-NEXT: mv s0, a0 -; CHECK-NEXT: call __truncsfhf2@plt +; CHECK-NEXT: call __truncsfhf2 ; CHECK-NEXT: fmv.x.w a0, fa0 ; CHECK-NEXT: sh a0, 0(s0) ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -71,7 +71,7 @@ define void @test_fptrunc_double(double %d, ptr %p) nounwind { ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; CHECK-NEXT: mv s0, a0 -; CHECK-NEXT: call __truncdfhf2@plt +; CHECK-NEXT: call __truncdfhf2 ; CHECK-NEXT: fmv.x.w a0, fa0 ; CHECK-NEXT: sh a0, 0(s0) ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -96,12 +96,12 @@ define void @test_fadd(ptr %p, ptr %q) nounwind { ; CHECK-NEXT: lhu a1, 0(a1) ; CHECK-NEXT: fmv.w.x fs0, a0 ; CHECK-NEXT: fmv.w.x fa0, a1 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs1, fa0 ; CHECK-NEXT: fmv.s fa0, fs0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fadd.s fa0, fa0, fs1 -; CHECK-NEXT: call __truncsfhf2@plt +; CHECK-NEXT: call __truncsfhf2 ; CHECK-NEXT: fmv.x.w a0, fa0 ; CHECK-NEXT: sh a0, 0(s0) ; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -130,12 +130,12 @@ define void @test_fmul(ptr %p, ptr %q) nounwind { ; CHECK-NEXT: lhu a1, 0(a1) ; CHECK-NEXT: fmv.w.x fs0, a0 ; CHECK-NEXT: fmv.w.x fa0, a1 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs1, fa0 ; CHECK-NEXT: fmv.s fa0, fs0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmul.s fa0, fa0, fs1 -; CHECK-NEXT: call __truncsfhf2@plt +; CHECK-NEXT: call __truncsfhf2 ; CHECK-NEXT: fmv.x.w a0, fa0 ; CHECK-NEXT: sh a0, 0(s0) ; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll index b091b0613c0f..3880ac9f4ec6 100644 --- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll +++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll @@ -17,7 +17,7 @@ define i32 @stest_f64i32(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfdi@plt +; RV32IF-NEXT: call __fixdfdi ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: addi a3, a2, -1 ; RV32IF-NEXT: beqz a1, .LBB0_2 @@ -56,7 +56,7 @@ define i32 @stest_f64i32(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfdi@plt +; RV64IF-NEXT: call __fixdfdi ; RV64IF-NEXT: lui a1, 524288 ; RV64IF-NEXT: addiw a2, a1, -1 ; RV64IF-NEXT: blt a0, a2, .LBB0_2 @@ -113,7 +113,7 @@ define i32 @utest_f64i32(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunsdfdi@plt +; RV32IF-NEXT: call __fixunsdfdi ; RV32IF-NEXT: sltiu a2, a0, -1 ; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: and a1, a1, a2 @@ -129,7 +129,7 @@ define i32 @utest_f64i32(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixunsdfdi@plt +; RV64IF-NEXT: call __fixunsdfdi ; RV64IF-NEXT: li a1, -1 ; RV64IF-NEXT: srli a1, a1, 32 ; RV64IF-NEXT: bltu a0, a1, .LBB1_2 @@ -174,7 +174,7 @@ define i32 @ustest_f64i32(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfdi@plt +; RV32IF-NEXT: call __fixdfdi ; RV32IF-NEXT: beqz a1, .LBB2_2 ; RV32IF-NEXT: # %bb.1: # %entry ; RV32IF-NEXT: slti a2, a1, 0 @@ -205,7 +205,7 @@ define i32 @ustest_f64i32(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfdi@plt +; RV64IF-NEXT: call __fixdfdi ; RV64IF-NEXT: li a1, -1 ; RV64IF-NEXT: srli a1, a1, 32 ; RV64IF-NEXT: blt a0, a1, .LBB2_2 @@ -355,8 +355,8 @@ define i32 @stest_f16i32(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt -; RV32-NEXT: call __fixsfdi@plt +; RV32-NEXT: call __extendhfsf2 +; RV32-NEXT: call __fixsfdi ; RV32-NEXT: lui a2, 524288 ; RV32-NEXT: addi a3, a2, -1 ; RV32-NEXT: beqz a1, .LBB6_2 @@ -395,7 +395,7 @@ define i32 @stest_f16i32(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: lui a1, 524288 ; RV64-NEXT: addiw a2, a1, -1 @@ -427,8 +427,8 @@ define i32 @utesth_f16i32(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt -; RV32-NEXT: call __fixunssfdi@plt +; RV32-NEXT: call __extendhfsf2 +; RV32-NEXT: call __fixunssfdi ; RV32-NEXT: sltiu a2, a0, -1 ; RV32-NEXT: seqz a1, a1 ; RV32-NEXT: and a1, a1, a2 @@ -444,7 +444,7 @@ define i32 @utesth_f16i32(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64-NEXT: li a1, -1 ; RV64-NEXT: srli a1, a1, 32 @@ -470,8 +470,8 @@ define i32 @ustest_f16i32(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt -; RV32-NEXT: call __fixsfdi@plt +; RV32-NEXT: call __extendhfsf2 +; RV32-NEXT: call __fixsfdi ; RV32-NEXT: beqz a1, .LBB8_2 ; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: slti a2, a1, 0 @@ -502,7 +502,7 @@ define i32 @ustest_f16i32(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: li a1, -1 ; RV64-NEXT: srli a1, a1, 32 @@ -535,7 +535,7 @@ define i16 @stest_f64i16(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfsi@plt +; RV32IF-NEXT: call __fixdfsi ; RV32IF-NEXT: lui a1, 8 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: blt a0, a1, .LBB9_2 @@ -557,7 +557,7 @@ define i16 @stest_f64i16(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfsi@plt +; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: lui a1, 8 ; RV64IF-NEXT: addiw a1, a1, -1 ; RV64IF-NEXT: blt a0, a1, .LBB9_2 @@ -627,7 +627,7 @@ define i16 @utest_f64i16(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunsdfsi@plt +; RV32IF-NEXT: call __fixunsdfsi ; RV32IF-NEXT: lui a1, 16 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: bltu a0, a1, .LBB10_2 @@ -644,7 +644,7 @@ define i16 @utest_f64i16(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixunsdfsi@plt +; RV64IF-NEXT: call __fixunsdfsi ; RV64IF-NEXT: lui a1, 16 ; RV64IF-NEXT: addiw a1, a1, -1 ; RV64IF-NEXT: bltu a0, a1, .LBB10_2 @@ -691,7 +691,7 @@ define i16 @ustest_f64i16(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfsi@plt +; RV32IF-NEXT: call __fixdfsi ; RV32IF-NEXT: lui a1, 16 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: blt a0, a1, .LBB11_2 @@ -711,7 +711,7 @@ define i16 @ustest_f64i16(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfsi@plt +; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: lui a1, 16 ; RV64IF-NEXT: addiw a1, a1, -1 ; RV64IF-NEXT: blt a0, a1, .LBB11_2 @@ -885,7 +885,7 @@ define i16 @stest_f16i16(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-NEXT: lui a1, 8 ; RV32-NEXT: addi a1, a1, -1 @@ -908,7 +908,7 @@ define i16 @stest_f16i16(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: lui a1, 8 ; RV64-NEXT: addiw a1, a1, -1 @@ -941,7 +941,7 @@ define i16 @utesth_f16i16(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32-NEXT: lui a1, 16 ; RV32-NEXT: addi a1, a1, -1 @@ -959,7 +959,7 @@ define i16 @utesth_f16i16(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64-NEXT: lui a1, 16 ; RV64-NEXT: addiw a1, a1, -1 @@ -985,7 +985,7 @@ define i16 @ustest_f16i16(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-NEXT: lui a1, 16 ; RV32-NEXT: addi a1, a1, -1 @@ -1006,7 +1006,7 @@ define i16 @ustest_f16i16(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: lui a1, 16 ; RV64-NEXT: addiw a1, a1, -1 @@ -1042,7 +1042,7 @@ define i64 @stest_f64i64(double %x) { ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: mv a1, a0 ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: call __fixdfti@plt +; RV32IF-NEXT: call __fixdfti ; RV32IF-NEXT: lw a0, 20(sp) ; RV32IF-NEXT: lw a2, 16(sp) ; RV32IF-NEXT: lw a1, 12(sp) @@ -1101,7 +1101,7 @@ define i64 @stest_f64i64(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfti@plt +; RV64IF-NEXT: call __fixdfti ; RV64IF-NEXT: li a2, -1 ; RV64IF-NEXT: srli a3, a2, 1 ; RV64IF-NEXT: beqz a1, .LBB18_2 @@ -1141,7 +1141,7 @@ define i64 @stest_f64i64(double %x) { ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call __fixdfti@plt +; RV32IFD-NEXT: call __fixdfti ; RV32IFD-NEXT: lw a0, 20(sp) ; RV32IFD-NEXT: lw a2, 16(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -1222,7 +1222,7 @@ define i64 @utest_f64i64(double %x) { ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: mv a1, a0 ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: call __fixunsdfti@plt +; RV32IF-NEXT: call __fixunsdfti ; RV32IF-NEXT: lw a0, 16(sp) ; RV32IF-NEXT: lw a1, 20(sp) ; RV32IF-NEXT: lw a2, 12(sp) @@ -1247,7 +1247,7 @@ define i64 @utest_f64i64(double %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixunsdfti@plt +; RV64-NEXT: call __fixunsdfti ; RV64-NEXT: snez a1, a1 ; RV64-NEXT: addi a1, a1, -1 ; RV64-NEXT: and a0, a1, a0 @@ -1262,7 +1262,7 @@ define i64 @utest_f64i64(double %x) { ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call __fixunsdfti@plt +; RV32IFD-NEXT: call __fixunsdfti ; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: lw a2, 12(sp) @@ -1298,7 +1298,7 @@ define i64 @ustest_f64i64(double %x) { ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: mv a1, a0 ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: call __fixdfti@plt +; RV32IF-NEXT: call __fixdfti ; RV32IF-NEXT: lw a1, 20(sp) ; RV32IF-NEXT: lw a0, 16(sp) ; RV32IF-NEXT: beqz a1, .LBB20_2 @@ -1349,7 +1349,7 @@ define i64 @ustest_f64i64(double %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixdfti@plt +; RV64-NEXT: call __fixdfti ; RV64-NEXT: slti a2, a1, 1 ; RV64-NEXT: blez a1, .LBB20_2 ; RV64-NEXT: # %bb.1: # %entry @@ -1377,7 +1377,7 @@ define i64 @ustest_f64i64(double %x) { ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call __fixdfti@plt +; RV32IFD-NEXT: call __fixdfti ; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: beqz a1, .LBB20_2 @@ -1439,7 +1439,7 @@ define i64 @stest_f32i64(float %x) { ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a0, 20(sp) ; RV32-NEXT: lw a2, 16(sp) ; RV32-NEXT: lw a1, 12(sp) @@ -1518,7 +1518,7 @@ define i64 @utest_f32i64(float %x) { ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixunssfti@plt +; RV32-NEXT: call __fixunssfti ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: lw a1, 20(sp) ; RV32-NEXT: lw a2, 12(sp) @@ -1543,7 +1543,7 @@ define i64 @utest_f32i64(float %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixunssfti@plt +; RV64-NEXT: call __fixunssfti ; RV64-NEXT: snez a1, a1 ; RV64-NEXT: addi a1, a1, -1 ; RV64-NEXT: and a0, a1, a0 @@ -1566,7 +1566,7 @@ define i64 @ustest_f32i64(float %x) { ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a1, 20(sp) ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: beqz a1, .LBB23_2 @@ -1617,7 +1617,7 @@ define i64 @ustest_f32i64(float %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixsfti@plt +; RV64-NEXT: call __fixsfti ; RV64-NEXT: slti a2, a1, 1 ; RV64-NEXT: blez a1, .LBB23_2 ; RV64-NEXT: # %bb.1: # %entry @@ -1654,9 +1654,9 @@ define i64 @stest_f16i64(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a0, 20(sp) ; RV32-NEXT: lw a2, 16(sp) ; RV32-NEXT: lw a1, 12(sp) @@ -1715,8 +1715,8 @@ define i64 @stest_f16i64(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt -; RV64-NEXT: call __fixsfti@plt +; RV64-NEXT: call __extendhfsf2 +; RV64-NEXT: call __fixsfti ; RV64-NEXT: li a2, -1 ; RV64-NEXT: srli a3, a2, 1 ; RV64-NEXT: beqz a1, .LBB24_2 @@ -1765,9 +1765,9 @@ define i64 @utesth_f16i64(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixunssfti@plt +; RV32-NEXT: call __fixunssfti ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: lw a1, 20(sp) ; RV32-NEXT: lw a2, 12(sp) @@ -1792,8 +1792,8 @@ define i64 @utesth_f16i64(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt -; RV64-NEXT: call __fixunssfti@plt +; RV64-NEXT: call __extendhfsf2 +; RV64-NEXT: call __fixunssfti ; RV64-NEXT: snez a1, a1 ; RV64-NEXT: addi a1, a1, -1 ; RV64-NEXT: and a0, a1, a0 @@ -1815,9 +1815,9 @@ define i64 @ustest_f16i64(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a1, 20(sp) ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: beqz a1, .LBB26_2 @@ -1868,8 +1868,8 @@ define i64 @ustest_f16i64(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt -; RV64-NEXT: call __fixsfti@plt +; RV64-NEXT: call __extendhfsf2 +; RV64-NEXT: call __fixsfti ; RV64-NEXT: slti a2, a1, 1 ; RV64-NEXT: blez a1, .LBB26_2 ; RV64-NEXT: # %bb.1: # %entry @@ -1911,7 +1911,7 @@ define i32 @stest_f64i32_mm(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfdi@plt +; RV32IF-NEXT: call __fixdfdi ; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: addi a3, a2, -1 ; RV32IF-NEXT: beqz a1, .LBB27_2 @@ -1950,7 +1950,7 @@ define i32 @stest_f64i32_mm(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfdi@plt +; RV64IF-NEXT: call __fixdfdi ; RV64IF-NEXT: lui a1, 524288 ; RV64IF-NEXT: addiw a2, a1, -1 ; RV64IF-NEXT: blt a0, a2, .LBB27_2 @@ -2005,7 +2005,7 @@ define i32 @utest_f64i32_mm(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunsdfdi@plt +; RV32IF-NEXT: call __fixunsdfdi ; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: or a0, a1, a0 @@ -2019,7 +2019,7 @@ define i32 @utest_f64i32_mm(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixunsdfdi@plt +; RV64IF-NEXT: call __fixunsdfdi ; RV64IF-NEXT: li a1, -1 ; RV64IF-NEXT: srli a1, a1, 32 ; RV64IF-NEXT: bltu a0, a1, .LBB28_2 @@ -2063,7 +2063,7 @@ define i32 @ustest_f64i32_mm(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfdi@plt +; RV32IF-NEXT: call __fixdfdi ; RV32IF-NEXT: bnez a1, .LBB29_2 ; RV32IF-NEXT: # %bb.1: # %entry ; RV32IF-NEXT: li a2, 1 @@ -2088,7 +2088,7 @@ define i32 @ustest_f64i32_mm(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfdi@plt +; RV64IF-NEXT: call __fixdfdi ; RV64IF-NEXT: li a1, -1 ; RV64IF-NEXT: srli a1, a1, 32 ; RV64IF-NEXT: blt a0, a1, .LBB29_2 @@ -2231,8 +2231,8 @@ define i32 @stest_f16i32_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt -; RV32-NEXT: call __fixsfdi@plt +; RV32-NEXT: call __extendhfsf2 +; RV32-NEXT: call __fixsfdi ; RV32-NEXT: lui a2, 524288 ; RV32-NEXT: addi a3, a2, -1 ; RV32-NEXT: beqz a1, .LBB33_2 @@ -2271,7 +2271,7 @@ define i32 @stest_f16i32_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: lui a1, 524288 ; RV64-NEXT: addiw a2, a1, -1 @@ -2301,8 +2301,8 @@ define i32 @utesth_f16i32_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt -; RV32-NEXT: call __fixunssfdi@plt +; RV32-NEXT: call __extendhfsf2 +; RV32-NEXT: call __fixunssfdi ; RV32-NEXT: seqz a1, a1 ; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: or a0, a1, a0 @@ -2316,7 +2316,7 @@ define i32 @utesth_f16i32_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64-NEXT: li a1, -1 ; RV64-NEXT: srli a1, a1, 32 @@ -2341,8 +2341,8 @@ define i32 @ustest_f16i32_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt -; RV32-NEXT: call __fixsfdi@plt +; RV32-NEXT: call __extendhfsf2 +; RV32-NEXT: call __fixsfdi ; RV32-NEXT: bnez a1, .LBB35_2 ; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: li a2, 1 @@ -2367,7 +2367,7 @@ define i32 @ustest_f16i32_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: li a1, -1 ; RV64-NEXT: srli a1, a1, 32 @@ -2398,7 +2398,7 @@ define i16 @stest_f64i16_mm(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfsi@plt +; RV32IF-NEXT: call __fixdfsi ; RV32IF-NEXT: lui a1, 8 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: blt a0, a1, .LBB36_2 @@ -2420,7 +2420,7 @@ define i16 @stest_f64i16_mm(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfsi@plt +; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: lui a1, 8 ; RV64IF-NEXT: addiw a1, a1, -1 ; RV64IF-NEXT: blt a0, a1, .LBB36_2 @@ -2488,7 +2488,7 @@ define i16 @utest_f64i16_mm(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixunsdfsi@plt +; RV32IF-NEXT: call __fixunsdfsi ; RV32IF-NEXT: lui a1, 16 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: bltu a0, a1, .LBB37_2 @@ -2505,7 +2505,7 @@ define i16 @utest_f64i16_mm(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixunsdfsi@plt +; RV64IF-NEXT: call __fixunsdfsi ; RV64IF-NEXT: lui a1, 16 ; RV64IF-NEXT: addiw a1, a1, -1 ; RV64IF-NEXT: bltu a0, a1, .LBB37_2 @@ -2551,7 +2551,7 @@ define i16 @ustest_f64i16_mm(double %x) { ; RV32IF-NEXT: .cfi_def_cfa_offset 16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 -; RV32IF-NEXT: call __fixdfsi@plt +; RV32IF-NEXT: call __fixdfsi ; RV32IF-NEXT: lui a1, 16 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: blt a0, a1, .LBB38_2 @@ -2571,7 +2571,7 @@ define i16 @ustest_f64i16_mm(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfsi@plt +; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: lui a1, 16 ; RV64IF-NEXT: addiw a1, a1, -1 ; RV64IF-NEXT: blt a0, a1, .LBB38_2 @@ -2738,7 +2738,7 @@ define i16 @stest_f16i16_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-NEXT: lui a1, 8 ; RV32-NEXT: addi a1, a1, -1 @@ -2761,7 +2761,7 @@ define i16 @stest_f16i16_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: lui a1, 8 ; RV64-NEXT: addiw a1, a1, -1 @@ -2792,7 +2792,7 @@ define i16 @utesth_f16i16_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32-NEXT: lui a1, 16 ; RV32-NEXT: addi a1, a1, -1 @@ -2810,7 +2810,7 @@ define i16 @utesth_f16i16_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64-NEXT: sext.w a0, a0 ; RV64-NEXT: lui a1, 16 @@ -2836,7 +2836,7 @@ define i16 @ustest_f16i16_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-NEXT: lui a1, 16 ; RV32-NEXT: addi a1, a1, -1 @@ -2857,7 +2857,7 @@ define i16 @ustest_f16i16_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt +; RV64-NEXT: call __extendhfsf2 ; RV64-NEXT: fcvt.l.s a0, fa0, rtz ; RV64-NEXT: lui a1, 16 ; RV64-NEXT: addiw a1, a1, -1 @@ -2891,7 +2891,7 @@ define i64 @stest_f64i64_mm(double %x) { ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: mv a1, a0 ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: call __fixdfti@plt +; RV32IF-NEXT: call __fixdfti ; RV32IF-NEXT: lw a0, 20(sp) ; RV32IF-NEXT: lw a2, 16(sp) ; RV32IF-NEXT: lw a1, 12(sp) @@ -2950,7 +2950,7 @@ define i64 @stest_f64i64_mm(double %x) { ; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: .cfi_offset ra, -8 -; RV64IF-NEXT: call __fixdfti@plt +; RV64IF-NEXT: call __fixdfti ; RV64IF-NEXT: li a2, -1 ; RV64IF-NEXT: srli a3, a2, 1 ; RV64IF-NEXT: beqz a1, .LBB45_2 @@ -2990,7 +2990,7 @@ define i64 @stest_f64i64_mm(double %x) { ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call __fixdfti@plt +; RV32IFD-NEXT: call __fixdfti ; RV32IFD-NEXT: lw a0, 20(sp) ; RV32IFD-NEXT: lw a2, 16(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -3069,7 +3069,7 @@ define i64 @utest_f64i64_mm(double %x) { ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: mv a1, a0 ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: call __fixunsdfti@plt +; RV32IF-NEXT: call __fixunsdfti ; RV32IF-NEXT: lw a0, 16(sp) ; RV32IF-NEXT: lw a1, 20(sp) ; RV32IF-NEXT: lw a2, 12(sp) @@ -3094,7 +3094,7 @@ define i64 @utest_f64i64_mm(double %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixunsdfti@plt +; RV64-NEXT: call __fixunsdfti ; RV64-NEXT: snez a1, a1 ; RV64-NEXT: addi a1, a1, -1 ; RV64-NEXT: and a0, a1, a0 @@ -3109,7 +3109,7 @@ define i64 @utest_f64i64_mm(double %x) { ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call __fixunsdfti@plt +; RV32IFD-NEXT: call __fixunsdfti ; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: lw a2, 12(sp) @@ -3144,7 +3144,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: mv a1, a0 ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: call __fixdfti@plt +; RV32IF-NEXT: call __fixdfti ; RV32IF-NEXT: lw a0, 8(sp) ; RV32IF-NEXT: lw a1, 12(sp) ; RV32IF-NEXT: lw a2, 20(sp) @@ -3179,7 +3179,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixdfti@plt +; RV64-NEXT: call __fixdfti ; RV64-NEXT: mv a2, a1 ; RV64-NEXT: blez a1, .LBB47_2 ; RV64-NEXT: # %bb.1: # %entry @@ -3202,7 +3202,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call __fixdfti@plt +; RV32IFD-NEXT: call __fixdfti ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a2, 20(sp) @@ -3246,7 +3246,7 @@ define i64 @stest_f32i64_mm(float %x) { ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a0, 20(sp) ; RV32-NEXT: lw a2, 16(sp) ; RV32-NEXT: lw a1, 12(sp) @@ -3323,7 +3323,7 @@ define i64 @utest_f32i64_mm(float %x) { ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixunssfti@plt +; RV32-NEXT: call __fixunssfti ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: lw a1, 20(sp) ; RV32-NEXT: lw a2, 12(sp) @@ -3348,7 +3348,7 @@ define i64 @utest_f32i64_mm(float %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixunssfti@plt +; RV64-NEXT: call __fixunssfti ; RV64-NEXT: snez a1, a1 ; RV64-NEXT: addi a1, a1, -1 ; RV64-NEXT: and a0, a1, a0 @@ -3370,7 +3370,7 @@ define i64 @ustest_f32i64_mm(float %x) { ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a0, 8(sp) ; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a2, 20(sp) @@ -3405,7 +3405,7 @@ define i64 @ustest_f32i64_mm(float %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __fixsfti@plt +; RV64-NEXT: call __fixsfti ; RV64-NEXT: mv a2, a1 ; RV64-NEXT: blez a1, .LBB50_2 ; RV64-NEXT: # %bb.1: # %entry @@ -3435,9 +3435,9 @@ define i64 @stest_f16i64_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a0, 20(sp) ; RV32-NEXT: lw a2, 16(sp) ; RV32-NEXT: lw a1, 12(sp) @@ -3496,8 +3496,8 @@ define i64 @stest_f16i64_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt -; RV64-NEXT: call __fixsfti@plt +; RV64-NEXT: call __extendhfsf2 +; RV64-NEXT: call __fixsfti ; RV64-NEXT: li a2, -1 ; RV64-NEXT: srli a3, a2, 1 ; RV64-NEXT: beqz a1, .LBB51_2 @@ -3544,9 +3544,9 @@ define i64 @utesth_f16i64_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixunssfti@plt +; RV32-NEXT: call __fixunssfti ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: lw a1, 20(sp) ; RV32-NEXT: lw a2, 12(sp) @@ -3571,8 +3571,8 @@ define i64 @utesth_f16i64_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt -; RV64-NEXT: call __fixunssfti@plt +; RV64-NEXT: call __extendhfsf2 +; RV64-NEXT: call __fixunssfti ; RV64-NEXT: snez a1, a1 ; RV64-NEXT: addi a1, a1, -1 ; RV64-NEXT: and a0, a1, a0 @@ -3593,9 +3593,9 @@ define i64 @ustest_f16i64_mm(half %x) { ; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call __extendhfsf2@plt +; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: call __fixsfti@plt +; RV32-NEXT: call __fixsfti ; RV32-NEXT: lw a0, 8(sp) ; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a2, 20(sp) @@ -3630,8 +3630,8 @@ define i64 @ustest_f16i64_mm(half %x) { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call __extendhfsf2@plt -; RV64-NEXT: call __fixsfti@plt +; RV64-NEXT: call __extendhfsf2 +; RV64-NEXT: call __fixsfti ; RV64-NEXT: mv a2, a1 ; RV64-NEXT: blez a1, .LBB53_2 ; RV64-NEXT: # %bb.1: # %entry diff --git a/llvm/test/CodeGen/RISCV/frame-info.ll b/llvm/test/CodeGen/RISCV/frame-info.ll index 95c4798c32ec..bc4f89e91774 100644 --- a/llvm/test/CodeGen/RISCV/frame-info.ll +++ b/llvm/test/CodeGen/RISCV/frame-info.ll @@ -64,7 +64,7 @@ define void @stack_alloc(i32 signext %size) { ; RV32-NEXT: andi a0, a0, -16 ; RV32-NEXT: sub a0, sp, a0 ; RV32-NEXT: mv sp, a0 -; RV32-NEXT: call callee_with_args@plt +; RV32-NEXT: call callee_with_args ; RV32-NEXT: addi sp, s0, -16 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -87,7 +87,7 @@ define void @stack_alloc(i32 signext %size) { ; RV64-NEXT: andi a0, a0, -16 ; RV64-NEXT: sub a0, sp, a0 ; RV64-NEXT: mv sp, a0 -; RV64-NEXT: call callee_with_args@plt +; RV64-NEXT: call callee_with_args ; RV64-NEXT: addi sp, s0, -16 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -108,7 +108,7 @@ define void @stack_alloc(i32 signext %size) { ; RV32-WITHFP-NEXT: andi a0, a0, -16 ; RV32-WITHFP-NEXT: sub a0, sp, a0 ; RV32-WITHFP-NEXT: mv sp, a0 -; RV32-WITHFP-NEXT: call callee_with_args@plt +; RV32-WITHFP-NEXT: call callee_with_args ; RV32-WITHFP-NEXT: addi sp, s0, -16 ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -131,7 +131,7 @@ define void @stack_alloc(i32 signext %size) { ; RV64-WITHFP-NEXT: andi a0, a0, -16 ; RV64-WITHFP-NEXT: sub a0, sp, a0 ; RV64-WITHFP-NEXT: mv sp, a0 -; RV64-WITHFP-NEXT: call callee_with_args@plt +; RV64-WITHFP-NEXT: call callee_with_args ; RV64-WITHFP-NEXT: addi sp, s0, -16 ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -149,13 +149,13 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-NEXT: andi a0, a0, 1 ; RV32-NEXT: beqz a0, .LBB2_2 ; RV32-NEXT: # %bb.1: # %blue_pill -; RV32-NEXT: tail callee1@plt +; RV32-NEXT: tail callee1 ; RV32-NEXT: .LBB2_2: # %red_pill ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call callee2@plt +; RV32-NEXT: call callee2 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -165,13 +165,13 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-NEXT: andi a0, a0, 1 ; RV64-NEXT: beqz a0, .LBB2_2 ; RV64-NEXT: # %bb.1: # %blue_pill -; RV64-NEXT: tail callee1@plt +; RV64-NEXT: tail callee1 ; RV64-NEXT: .LBB2_2: # %red_pill ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call callee2@plt +; RV64-NEXT: call callee2 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -181,7 +181,7 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-WITHFP-NEXT: andi a0, a0, 1 ; RV32-WITHFP-NEXT: beqz a0, .LBB2_2 ; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill -; RV32-WITHFP-NEXT: tail callee1@plt +; RV32-WITHFP-NEXT: tail callee1 ; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV32-WITHFP-NEXT: addi sp, sp, -16 ; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16 @@ -191,7 +191,7 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-WITHFP-NEXT: .cfi_offset s0, -8 ; RV32-WITHFP-NEXT: addi s0, sp, 16 ; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0 -; RV32-WITHFP-NEXT: call callee2@plt +; RV32-WITHFP-NEXT: call callee2 ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-WITHFP-NEXT: addi sp, sp, 16 @@ -202,7 +202,7 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-WITHFP-NEXT: andi a0, a0, 1 ; RV64-WITHFP-NEXT: beqz a0, .LBB2_2 ; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill -; RV64-WITHFP-NEXT: tail callee1@plt +; RV64-WITHFP-NEXT: tail callee1 ; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV64-WITHFP-NEXT: addi sp, sp, -16 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16 @@ -212,7 +212,7 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-WITHFP-NEXT: .cfi_offset s0, -16 ; RV64-WITHFP-NEXT: addi s0, sp, 16 ; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0 -; RV64-WITHFP-NEXT: call callee2@plt +; RV64-WITHFP-NEXT: call callee2 ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64-WITHFP-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/frame.ll b/llvm/test/CodeGen/RISCV/frame.ll index 183a0f47c68c..d50f1e55417a 100644 --- a/llvm/test/CodeGen/RISCV/frame.ll +++ b/llvm/test/CodeGen/RISCV/frame.ll @@ -17,7 +17,7 @@ define i32 @test() nounwind { ; RV32I-FPELIM-NEXT: sw zero, 12(sp) ; RV32I-FPELIM-NEXT: sw zero, 8(sp) ; RV32I-FPELIM-NEXT: addi a0, sp, 12 -; RV32I-FPELIM-NEXT: call test1@plt +; RV32I-FPELIM-NEXT: call test1 ; RV32I-FPELIM-NEXT: li a0, 0 ; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 32 @@ -35,7 +35,7 @@ define i32 @test() nounwind { ; RV32I-WITHFP-NEXT: sw zero, -28(s0) ; RV32I-WITHFP-NEXT: sw zero, -32(s0) ; RV32I-WITHFP-NEXT: addi a0, s0, -28 -; RV32I-WITHFP-NEXT: call test1@plt +; RV32I-WITHFP-NEXT: call test1 ; RV32I-WITHFP-NEXT: li a0, 0 ; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll b/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll index 23379c9430ac..478c8457997a 100644 --- a/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll +++ b/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll @@ -74,7 +74,7 @@ define ptr @test_frameaddress_3_alloca() nounwind { ; RV32I-NEXT: sw s0, 104(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi s0, sp, 112 ; RV32I-NEXT: addi a0, s0, -108 -; RV32I-NEXT: call notdead@plt +; RV32I-NEXT: call notdead ; RV32I-NEXT: lw a0, -8(s0) ; RV32I-NEXT: lw a0, -8(a0) ; RV32I-NEXT: lw a0, -8(a0) @@ -90,7 +90,7 @@ define ptr @test_frameaddress_3_alloca() nounwind { ; RV64I-NEXT: sd s0, 112(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi s0, sp, 128 ; RV64I-NEXT: addi a0, s0, -116 -; RV64I-NEXT: call notdead@plt +; RV64I-NEXT: call notdead ; RV64I-NEXT: ld a0, -16(s0) ; RV64I-NEXT: ld a0, -16(a0) ; RV64I-NEXT: ld a0, -16(a0) diff --git a/llvm/test/CodeGen/RISCV/ghccc-rv32.ll b/llvm/test/CodeGen/RISCV/ghccc-rv32.ll index bf1f41195c5d..0f9511125adb 100644 --- a/llvm/test/CodeGen/RISCV/ghccc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/ghccc-rv32.ll @@ -78,7 +78,7 @@ define ghccc void @foo() nounwind { ; CHECK-NEXT: lw s2, %lo(sp)(a0) ; CHECK-NEXT: lui a0, %hi(base) ; CHECK-NEXT: lw s1, %lo(base)(a0) -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar entry: %0 = load double, ptr @d6 %1 = load double, ptr @d5 diff --git a/llvm/test/CodeGen/RISCV/ghccc-rv64.ll b/llvm/test/CodeGen/RISCV/ghccc-rv64.ll index 9d2091df1f19..79afd4bc375d 100644 --- a/llvm/test/CodeGen/RISCV/ghccc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/ghccc-rv64.ll @@ -78,7 +78,7 @@ define ghccc void @foo() nounwind { ; CHECK-NEXT: ld s2, %lo(sp)(a0) ; CHECK-NEXT: lui a0, %hi(base) ; CHECK-NEXT: ld s1, %lo(base)(a0) -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar entry: %0 = load double, ptr @d6 %1 = load double, ptr @d5 diff --git a/llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll b/llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll index 32df34fe2c0f..6437beae0901 100644 --- a/llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll +++ b/llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll @@ -25,7 +25,7 @@ define ghccc void @caller_float() nounwind { ; CHECK-NEXT: lw s2, %lo(f2)(a0) ; CHECK-NEXT: lui a0, %hi(f1) ; CHECK-NEXT: lw s1, %lo(f1)(a0) -; CHECK-NEXT: tail callee_float@plt +; CHECK-NEXT: tail callee_float entry: %0 = load float, ptr @f6 %1 = load float, ptr @f5 @@ -61,7 +61,7 @@ define ghccc void @caller_double() nounwind { ; CHECK-NEXT: ld s2, %lo(d2)(a0) ; CHECK-NEXT: lui a0, %hi(d1) ; CHECK-NEXT: ld s1, %lo(d1)(a0) -; CHECK-NEXT: tail callee_double@plt +; CHECK-NEXT: tail callee_double entry: %0 = load double, ptr @d6 %1 = load double, ptr @d5 diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll index 98c732122951..f54adaa24b1b 100644 --- a/llvm/test/CodeGen/RISCV/half-arith.ll +++ b/llvm/test/CodeGen/RISCV/half-arith.ll @@ -47,14 +47,14 @@ define half @fadd_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -73,14 +73,14 @@ define half @fadd_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -136,14 +136,14 @@ define half @fsub_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __subsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __subsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -162,14 +162,14 @@ define half @fsub_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __subsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __subsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -225,14 +225,14 @@ define half @fmul_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __mulsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __mulsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -251,14 +251,14 @@ define half @fmul_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __mulsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __mulsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -314,14 +314,14 @@ define half @fdiv_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __divsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __divsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -340,14 +340,14 @@ define half @fdiv_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __divsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __divsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -400,9 +400,9 @@ define half @fsqrt_s(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call sqrtf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call sqrtf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -413,9 +413,9 @@ define half @fsqrt_s(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call sqrtf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call sqrtf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -577,21 +577,21 @@ define i32 @fneg_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: and a0, a0, s1 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s1 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: xor a0, s0, a0 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s1 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __eqsf2@plt +; RV32I-NEXT: call __eqsf2 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -608,21 +608,21 @@ define i32 @fneg_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: and a0, a0, s1 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s1 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a0, 524288 ; RV64I-NEXT: xor a0, s0, a0 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s1 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __eqsf2@plt +; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -699,19 +699,19 @@ define half @fsgnjn_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lui a1, 1048568 ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: slli s1, s1, 17 @@ -738,19 +738,19 @@ define half @fsgnjn_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: addiw s3, a0, -1 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: lui a1, 1048568 ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: slli s1, s1, 49 @@ -908,25 +908,25 @@ define half @fabs_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -945,25 +945,25 @@ define half @fabs_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: slli a0, a0, 33 ; RV64I-NEXT: srli a0, a0, 33 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1041,14 +1041,14 @@ define half @fmin_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call fminf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fminf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1067,14 +1067,14 @@ define half @fmin_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fminf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fminf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1132,14 +1132,14 @@ define half @fmax_s(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call fmaxf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaxf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1158,14 +1158,14 @@ define half @fmax_s(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fmaxf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaxf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1225,18 +1225,18 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s3, a1, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1258,18 +1258,18 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s3, a1, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1334,29 +1334,29 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: and a0, a2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1378,29 +1378,29 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: addiw s3, a0, -1 ; RV64I-NEXT: and a0, a2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1489,41 +1489,41 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui s3, 16 ; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: xor a0, a0, s4 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: xor a0, a0, s4 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1547,41 +1547,41 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui s3, 16 ; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: lui s4, 524288 ; RV64I-NEXT: xor a0, a0, s4 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: xor a0, a0, s4 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1691,41 +1691,41 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui s3, 16 ; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: xor a0, a0, s4 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: xor a0, a0, s4 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s2 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1749,41 +1749,41 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui s3, 16 ; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: lui s4, 524288 ; RV64I-NEXT: xor a0, a0, s4 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: xor a0, a0, s4 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s2 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1902,18 +1902,18 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s3, a1, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lui a1, 1048568 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -1937,18 +1937,18 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s3, a1, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: lui a1, 1048568 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload @@ -2033,18 +2033,18 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s3, a1, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lui a1, 1048568 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -2068,18 +2068,18 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s3, a1, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: lui a1, 1048568 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload @@ -2154,28 +2154,28 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s3, a1, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a2, s0 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -2197,28 +2197,28 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s3, a1, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -2304,29 +2304,29 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: and a0, a1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a2, s0 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -2348,29 +2348,29 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: addiw s3, a0, -1 ; RV64I-NEXT: and a0, a1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a2, s0 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -2453,23 +2453,23 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s3, a1, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __mulsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __mulsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -2491,23 +2491,23 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s3, a1, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __mulsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __mulsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -2582,29 +2582,29 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: and a0, a2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __mulsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __mulsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __subsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __subsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -2626,29 +2626,29 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: addiw s3, a0, -1 ; RV64I-NEXT: and a0, a2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __mulsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __mulsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __subsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __subsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -2738,46 +2738,46 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui s3, 16 ; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __mulsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __mulsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __subsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __subsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -2799,46 +2799,46 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui s3, 16 ; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __mulsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __mulsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __subsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __subsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -2956,36 +2956,36 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui s3, 16 ; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s2, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __mulsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __mulsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __subsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __subsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -3007,36 +3007,36 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui s3, 16 ; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s2, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __mulsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __mulsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __subsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __subsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll index f4d632449acd..6699ee947937 100644 --- a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll @@ -30,7 +30,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB0_2: # %if.else ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_false: ; RV64IZFH: # %bb.0: @@ -41,7 +41,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB0_2: # %if.else ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_false: ; RV32IZHINX: # %bb.0: @@ -52,7 +52,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB0_2: # %if.else ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_false: ; RV64IZHINX: # %bb.0: @@ -63,7 +63,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB0_2: # %if.else ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_false: ; RV32IZFHMIN: # %bb.0: @@ -74,7 +74,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB0_2: # %if.else ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_false: ; RV64IZFHMIN: # %bb.0: @@ -85,7 +85,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB0_2: # %if.else ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_false: ; RV32IZHINXMIN: # %bb.0: @@ -96,7 +96,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB0_2: # %if.else ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_false: ; RV64IZHINXMIN: # %bb.0: @@ -107,7 +107,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB0_2: # %if.else ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp false half %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -127,7 +127,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB1_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_oeq: ; RV64IZFH: # %bb.0: @@ -138,7 +138,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB1_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_oeq: ; RV32IZHINX: # %bb.0: @@ -149,7 +149,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB1_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_oeq: ; RV64IZHINX: # %bb.0: @@ -160,7 +160,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB1_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_oeq: ; RV32IZFHMIN: # %bb.0: @@ -173,7 +173,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB1_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_oeq: ; RV64IZFHMIN: # %bb.0: @@ -186,7 +186,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB1_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_oeq: ; RV32IZHINXMIN: # %bb.0: @@ -199,7 +199,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB1_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_oeq: ; RV64IZHINXMIN: # %bb.0: @@ -212,7 +212,7 @@ define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB1_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp oeq half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -235,7 +235,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB2_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_oeq_alt: ; RV64IZFH: # %bb.0: @@ -246,7 +246,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB2_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_oeq_alt: ; RV32IZHINX: # %bb.0: @@ -257,7 +257,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB2_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_oeq_alt: ; RV64IZHINX: # %bb.0: @@ -268,7 +268,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB2_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_oeq_alt: ; RV32IZFHMIN: # %bb.0: @@ -281,7 +281,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB2_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_oeq_alt: ; RV64IZFHMIN: # %bb.0: @@ -294,7 +294,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB2_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_oeq_alt: ; RV32IZHINXMIN: # %bb.0: @@ -307,7 +307,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB2_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_oeq_alt: ; RV64IZHINXMIN: # %bb.0: @@ -320,7 +320,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB2_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp oeq half %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -340,7 +340,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB3_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_ogt: ; RV64IZFH: # %bb.0: @@ -351,7 +351,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB3_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_ogt: ; RV32IZHINX: # %bb.0: @@ -362,7 +362,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB3_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_ogt: ; RV64IZHINX: # %bb.0: @@ -373,7 +373,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB3_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_ogt: ; RV32IZFHMIN: # %bb.0: @@ -386,7 +386,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB3_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_ogt: ; RV64IZFHMIN: # %bb.0: @@ -399,7 +399,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB3_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_ogt: ; RV32IZHINXMIN: # %bb.0: @@ -412,7 +412,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB3_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_ogt: ; RV64IZHINXMIN: # %bb.0: @@ -425,7 +425,7 @@ define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB3_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp ogt half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -445,7 +445,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB4_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_oge: ; RV64IZFH: # %bb.0: @@ -456,7 +456,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB4_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_oge: ; RV32IZHINX: # %bb.0: @@ -467,7 +467,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB4_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_oge: ; RV64IZHINX: # %bb.0: @@ -478,7 +478,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB4_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_oge: ; RV32IZFHMIN: # %bb.0: @@ -491,7 +491,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB4_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_oge: ; RV64IZFHMIN: # %bb.0: @@ -504,7 +504,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB4_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_oge: ; RV32IZHINXMIN: # %bb.0: @@ -517,7 +517,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB4_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_oge: ; RV64IZHINXMIN: # %bb.0: @@ -530,7 +530,7 @@ define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB4_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp oge half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -550,7 +550,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB5_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_olt: ; RV64IZFH: # %bb.0: @@ -561,7 +561,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB5_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_olt: ; RV32IZHINX: # %bb.0: @@ -572,7 +572,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB5_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_olt: ; RV64IZHINX: # %bb.0: @@ -583,7 +583,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB5_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_olt: ; RV32IZFHMIN: # %bb.0: @@ -596,7 +596,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB5_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_olt: ; RV64IZFHMIN: # %bb.0: @@ -609,7 +609,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB5_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_olt: ; RV32IZHINXMIN: # %bb.0: @@ -622,7 +622,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB5_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_olt: ; RV64IZHINXMIN: # %bb.0: @@ -635,7 +635,7 @@ define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB5_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp olt half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -655,7 +655,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB6_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_ole: ; RV64IZFH: # %bb.0: @@ -666,7 +666,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB6_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_ole: ; RV32IZHINX: # %bb.0: @@ -677,7 +677,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB6_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_ole: ; RV64IZHINX: # %bb.0: @@ -688,7 +688,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB6_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_ole: ; RV32IZFHMIN: # %bb.0: @@ -701,7 +701,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB6_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_ole: ; RV64IZFHMIN: # %bb.0: @@ -714,7 +714,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB6_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_ole: ; RV32IZHINXMIN: # %bb.0: @@ -727,7 +727,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB6_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_ole: ; RV64IZHINXMIN: # %bb.0: @@ -740,7 +740,7 @@ define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB6_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp ole half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -762,7 +762,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB7_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_one: ; RV64IZFH: # %bb.0: @@ -775,7 +775,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB7_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_one: ; RV32IZHINX: # %bb.0: @@ -788,7 +788,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB7_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_one: ; RV64IZHINX: # %bb.0: @@ -801,7 +801,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB7_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_one: ; RV32IZFHMIN: # %bb.0: @@ -816,7 +816,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB7_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_one: ; RV64IZFHMIN: # %bb.0: @@ -831,7 +831,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB7_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_one: ; RV32IZHINXMIN: # %bb.0: @@ -846,7 +846,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB7_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_one: ; RV64IZHINXMIN: # %bb.0: @@ -861,7 +861,7 @@ define void @br_fcmp_one(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB7_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp one half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -883,7 +883,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB8_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_ord: ; RV64IZFH: # %bb.0: @@ -896,7 +896,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB8_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_ord: ; RV32IZHINX: # %bb.0: @@ -909,7 +909,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB8_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_ord: ; RV64IZHINX: # %bb.0: @@ -922,7 +922,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB8_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_ord: ; RV32IZFHMIN: # %bb.0: @@ -937,7 +937,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB8_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_ord: ; RV64IZFHMIN: # %bb.0: @@ -952,7 +952,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB8_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_ord: ; RV32IZHINXMIN: # %bb.0: @@ -967,7 +967,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB8_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_ord: ; RV64IZHINXMIN: # %bb.0: @@ -982,7 +982,7 @@ define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB8_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp ord half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1004,7 +1004,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB9_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_ueq: ; RV64IZFH: # %bb.0: @@ -1017,7 +1017,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB9_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_ueq: ; RV32IZHINX: # %bb.0: @@ -1030,7 +1030,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB9_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_ueq: ; RV64IZHINX: # %bb.0: @@ -1043,7 +1043,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB9_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_ueq: ; RV32IZFHMIN: # %bb.0: @@ -1058,7 +1058,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB9_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_ueq: ; RV64IZFHMIN: # %bb.0: @@ -1073,7 +1073,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB9_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_ueq: ; RV32IZHINXMIN: # %bb.0: @@ -1088,7 +1088,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB9_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_ueq: ; RV64IZHINXMIN: # %bb.0: @@ -1103,7 +1103,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB9_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp ueq half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1123,7 +1123,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB10_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_ugt: ; RV64IZFH: # %bb.0: @@ -1134,7 +1134,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB10_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_ugt: ; RV32IZHINX: # %bb.0: @@ -1145,7 +1145,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB10_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_ugt: ; RV64IZHINX: # %bb.0: @@ -1156,7 +1156,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB10_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_ugt: ; RV32IZFHMIN: # %bb.0: @@ -1169,7 +1169,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB10_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_ugt: ; RV64IZFHMIN: # %bb.0: @@ -1182,7 +1182,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB10_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_ugt: ; RV32IZHINXMIN: # %bb.0: @@ -1195,7 +1195,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB10_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_ugt: ; RV64IZHINXMIN: # %bb.0: @@ -1208,7 +1208,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB10_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp ugt half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1228,7 +1228,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB11_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_uge: ; RV64IZFH: # %bb.0: @@ -1239,7 +1239,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB11_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_uge: ; RV32IZHINX: # %bb.0: @@ -1250,7 +1250,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB11_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_uge: ; RV64IZHINX: # %bb.0: @@ -1261,7 +1261,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB11_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_uge: ; RV32IZFHMIN: # %bb.0: @@ -1274,7 +1274,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB11_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_uge: ; RV64IZFHMIN: # %bb.0: @@ -1287,7 +1287,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB11_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_uge: ; RV32IZHINXMIN: # %bb.0: @@ -1300,7 +1300,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB11_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_uge: ; RV64IZHINXMIN: # %bb.0: @@ -1313,7 +1313,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB11_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp uge half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1333,7 +1333,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB12_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_ult: ; RV64IZFH: # %bb.0: @@ -1344,7 +1344,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB12_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_ult: ; RV32IZHINX: # %bb.0: @@ -1355,7 +1355,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB12_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_ult: ; RV64IZHINX: # %bb.0: @@ -1366,7 +1366,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB12_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_ult: ; RV32IZFHMIN: # %bb.0: @@ -1379,7 +1379,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB12_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_ult: ; RV64IZFHMIN: # %bb.0: @@ -1392,7 +1392,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB12_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_ult: ; RV32IZHINXMIN: # %bb.0: @@ -1405,7 +1405,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB12_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_ult: ; RV64IZHINXMIN: # %bb.0: @@ -1418,7 +1418,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB12_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp ult half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1438,7 +1438,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB13_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_ule: ; RV64IZFH: # %bb.0: @@ -1449,7 +1449,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB13_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_ule: ; RV32IZHINX: # %bb.0: @@ -1460,7 +1460,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB13_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_ule: ; RV64IZHINX: # %bb.0: @@ -1471,7 +1471,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB13_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_ule: ; RV32IZFHMIN: # %bb.0: @@ -1484,7 +1484,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB13_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_ule: ; RV64IZFHMIN: # %bb.0: @@ -1497,7 +1497,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB13_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_ule: ; RV32IZHINXMIN: # %bb.0: @@ -1510,7 +1510,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB13_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_ule: ; RV64IZHINXMIN: # %bb.0: @@ -1523,7 +1523,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB13_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp ule half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1543,7 +1543,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB14_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_une: ; RV64IZFH: # %bb.0: @@ -1554,7 +1554,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB14_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_une: ; RV32IZHINX: # %bb.0: @@ -1565,7 +1565,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB14_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_une: ; RV64IZHINX: # %bb.0: @@ -1576,7 +1576,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB14_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_une: ; RV32IZFHMIN: # %bb.0: @@ -1589,7 +1589,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB14_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_une: ; RV64IZFHMIN: # %bb.0: @@ -1602,7 +1602,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB14_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_une: ; RV32IZHINXMIN: # %bb.0: @@ -1615,7 +1615,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB14_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_une: ; RV64IZHINXMIN: # %bb.0: @@ -1628,7 +1628,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB14_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp une half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1650,7 +1650,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB15_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_uno: ; RV64IZFH: # %bb.0: @@ -1663,7 +1663,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB15_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_uno: ; RV32IZHINX: # %bb.0: @@ -1676,7 +1676,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB15_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_uno: ; RV64IZHINX: # %bb.0: @@ -1689,7 +1689,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB15_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_uno: ; RV32IZFHMIN: # %bb.0: @@ -1704,7 +1704,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB15_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_uno: ; RV64IZFHMIN: # %bb.0: @@ -1719,7 +1719,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB15_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_uno: ; RV32IZHINXMIN: # %bb.0: @@ -1734,7 +1734,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB15_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_uno: ; RV64IZHINXMIN: # %bb.0: @@ -1749,7 +1749,7 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB15_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp uno half %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -1769,7 +1769,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV32IZFH-NEXT: .LBB16_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call abort@plt +; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_true: ; RV64IZFH: # %bb.0: @@ -1780,7 +1780,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV64IZFH-NEXT: .LBB16_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call abort@plt +; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_true: ; RV32IZHINX: # %bb.0: @@ -1791,7 +1791,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: .LBB16_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call abort@plt +; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_true: ; RV64IZHINX: # %bb.0: @@ -1802,7 +1802,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: .LBB16_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call abort@plt +; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_true: ; RV32IZFHMIN: # %bb.0: @@ -1813,7 +1813,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: .LBB16_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: call abort@plt +; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_true: ; RV64IZFHMIN: # %bb.0: @@ -1824,7 +1824,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: .LBB16_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFHMIN-NEXT: call abort@plt +; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_true: ; RV32IZHINXMIN: # %bb.0: @@ -1835,7 +1835,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: .LBB16_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: call abort@plt +; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_true: ; RV64IZHINXMIN: # %bb.0: @@ -1846,7 +1846,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: .LBB16_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINXMIN-NEXT: call abort@plt +; RV64IZHINXMIN-NEXT: call abort %1 = fcmp true half %a, %b br i1 %1, label %if.then, label %if.else if.else: diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll index f6f85d3afeb0..f03a020762bb 100644 --- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll +++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll @@ -460,7 +460,7 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __fixhfdi@plt +; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -474,7 +474,7 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __fixhfdi@plt +; RV32IZHINX-NEXT: call __fixhfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -488,7 +488,7 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __fixhfdi@plt +; RV32IDZFH-NEXT: call __fixhfdi ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -502,7 +502,7 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __fixhfdi@plt +; RV32IZDINXZHINX-NEXT: call __fixhfdi ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -516,7 +516,7 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __fixhfdi@plt +; CHECK32-IZFHMIN-NEXT: call __fixhfdi ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -531,7 +531,7 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __fixhfdi@plt +; CHECK32-IZHINXMIN-NEXT: call __fixhfdi ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -546,7 +546,7 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixhfdi@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __fixhfdi ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -566,7 +566,7 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __fixunshfdi@plt +; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -580,7 +580,7 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __fixunshfdi@plt +; RV32IZHINX-NEXT: call __fixunshfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -594,7 +594,7 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __fixunshfdi@plt +; RV32IDZFH-NEXT: call __fixunshfdi ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -608,7 +608,7 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __fixunshfdi@plt +; RV32IZDINXZHINX-NEXT: call __fixunshfdi ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -622,7 +622,7 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __fixunshfdi@plt +; CHECK32-IZFHMIN-NEXT: call __fixunshfdi ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -637,7 +637,7 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __fixunshfdi@plt +; CHECK32-IZHINXMIN-NEXT: call __fixunshfdi ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -652,7 +652,7 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunshfdi@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunshfdi ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -1359,7 +1359,7 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __floatdihf@plt +; RV32IZFH-NEXT: call __floatdihf ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -1373,7 +1373,7 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __floatdihf@plt +; RV32IZHINX-NEXT: call __floatdihf ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -1387,7 +1387,7 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __floatdihf@plt +; RV32IDZFH-NEXT: call __floatdihf ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -1401,7 +1401,7 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __floatdihf@plt +; RV32IZDINXZHINX-NEXT: call __floatdihf ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -1415,7 +1415,7 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __floatdihf@plt +; CHECK32-IZFHMIN-NEXT: call __floatdihf ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -1430,7 +1430,7 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __floatdihf@plt +; CHECK32-IZHINXMIN-NEXT: call __floatdihf ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -1445,7 +1445,7 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __floatdihf@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __floatdihf ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -1465,7 +1465,7 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __floatundihf@plt +; RV32IZFH-NEXT: call __floatundihf ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -1479,7 +1479,7 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __floatundihf@plt +; RV32IZHINX-NEXT: call __floatundihf ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -1493,7 +1493,7 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __floatundihf@plt +; RV32IDZFH-NEXT: call __floatundihf ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -1507,7 +1507,7 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __floatundihf@plt +; RV32IZDINXZHINX-NEXT: call __floatundihf ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -1521,7 +1521,7 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __floatundihf@plt +; CHECK32-IZFHMIN-NEXT: call __floatundihf ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -1536,7 +1536,7 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __floatundihf@plt +; CHECK32-IZHINXMIN-NEXT: call __floatundihf ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -1551,7 +1551,7 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __floatundihf@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __floatundihf ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -1701,7 +1701,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __truncdfhf2@plt +; RV32IZFH-NEXT: call __truncdfhf2 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -1710,7 +1710,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV64IZFH: # %bb.0: ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call __truncdfhf2@plt +; RV64IZFH-NEXT: call __truncdfhf2 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret @@ -1719,7 +1719,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __truncdfhf2@plt +; RV32IZHINX-NEXT: call __truncdfhf2 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -1728,7 +1728,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV64IZHINX: # %bb.0: ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call __truncdfhf2@plt +; RV64IZHINX-NEXT: call __truncdfhf2 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 ; RV64IZHINX-NEXT: ret @@ -1763,7 +1763,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV32IFZFHMIN: # %bb.0: ; RV32IFZFHMIN-NEXT: addi sp, sp, -16 ; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: call __truncdfhf2@plt +; RV32IFZFHMIN-NEXT: call __truncdfhf2 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFZFHMIN-NEXT: ret @@ -1772,7 +1772,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV64IFZFHMIN: # %bb.0: ; RV64IFZFHMIN-NEXT: addi sp, sp, -16 ; RV64IFZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFZFHMIN-NEXT: call __truncdfhf2@plt +; RV64IFZFHMIN-NEXT: call __truncdfhf2 ; RV64IFZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFZFHMIN-NEXT: addi sp, sp, 16 ; RV64IFZFHMIN-NEXT: ret @@ -1781,7 +1781,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __truncdfhf2@plt +; CHECK32-IZHINXMIN-NEXT: call __truncdfhf2 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -1790,7 +1790,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; CHECK64-IZHINXMIN: # %bb.0: ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; CHECK64-IZHINXMIN-NEXT: call __truncdfhf2@plt +; CHECK64-IZHINXMIN-NEXT: call __truncdfhf2 ; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK64-IZHINXMIN-NEXT: ret @@ -1831,7 +1831,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call __extendsfdf2@plt +; RV32IZFH-NEXT: call __extendsfdf2 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -1841,7 +1841,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call __extendsfdf2@plt +; RV64IZFH-NEXT: call __extendsfdf2 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret @@ -1851,7 +1851,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call __extendsfdf2@plt +; RV32IZHINX-NEXT: call __extendsfdf2 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -1861,7 +1861,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call __extendsfdf2@plt +; RV64IZHINX-NEXT: call __extendsfdf2 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 ; RV64IZHINX-NEXT: ret @@ -1897,7 +1897,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV32IFZFHMIN-NEXT: addi sp, sp, -16 ; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IFZFHMIN-NEXT: call __extendsfdf2@plt +; RV32IFZFHMIN-NEXT: call __extendsfdf2 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFZFHMIN-NEXT: ret @@ -1907,7 +1907,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV64IFZFHMIN-NEXT: addi sp, sp, -16 ; RV64IFZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IFZFHMIN-NEXT: call __extendsfdf2@plt +; RV64IFZFHMIN-NEXT: call __extendsfdf2 ; RV64IFZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFZFHMIN-NEXT: addi sp, sp, 16 ; RV64IFZFHMIN-NEXT: ret @@ -1917,7 +1917,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZHINXMIN-NEXT: call __extendsfdf2@plt +; CHECK32-IZHINXMIN-NEXT: call __extendsfdf2 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -1927,7 +1927,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZHINXMIN-NEXT: call __extendsfdf2@plt +; CHECK64-IZHINXMIN-NEXT: call __extendsfdf2 ; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK64-IZHINXMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index 2d3f40e15fe4..daaceed3941c 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -91,8 +91,8 @@ define i16 @fcvt_si_h(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -103,8 +103,8 @@ define i16 @fcvt_si_h(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -113,7 +113,7 @@ define i16 @fcvt_si_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.w.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -124,7 +124,7 @@ define i16 @fcvt_si_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.l.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -135,7 +135,7 @@ define i16 @fcvt_si_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -145,7 +145,7 @@ define i16 @fcvt_si_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -316,13 +316,13 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 815104 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: bgez s2, .LBB1_2 ; RV32I-NEXT: # %bb.1: # %start @@ -331,7 +331,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV32I-NEXT: lui a0, 290816 ; RV32I-NEXT: addi a1, a0, -512 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB1_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: lui s1, 8 @@ -339,7 +339,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV32I-NEXT: .LBB1_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -359,13 +359,13 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 815104 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: bgez s2, .LBB1_2 ; RV64I-NEXT: # %bb.1: # %start @@ -374,7 +374,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV64I-NEXT: lui a0, 290816 ; RV64I-NEXT: addiw a1, a0, -512 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB1_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: lui s1, 8 @@ -382,7 +382,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV64I-NEXT: .LBB1_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -397,7 +397,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: feq.s a0, fa5, fa5 ; RV32ID-ILP32-NEXT: neg a0, a0 @@ -417,7 +417,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: feq.s a0, fa5, fa5 ; RV64ID-LP64-NEXT: lui a1, %hi(.LCPI1_0) @@ -437,7 +437,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: feq.s a0, fa0, fa0 ; RV32ID-NEXT: neg a0, a0 ; RV32ID-NEXT: lui a1, %hi(.LCPI1_0) @@ -456,7 +456,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: feq.s a0, fa0, fa0 ; RV64ID-NEXT: lui a1, %hi(.LCPI1_0) ; RV64ID-NEXT: flw fa5, %lo(.LCPI1_0)(a1) @@ -609,8 +609,8 @@ define i16 @fcvt_ui_h(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -621,8 +621,8 @@ define i16 @fcvt_ui_h(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -631,7 +631,7 @@ define i16 @fcvt_ui_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.wu.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -642,7 +642,7 @@ define i16 @fcvt_ui_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.lu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -653,7 +653,7 @@ define i16 @fcvt_ui_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -663,7 +663,7 @@ define i16 @fcvt_ui_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -804,18 +804,18 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV32I-NEXT: lui s0, 16 ; RV32I-NEXT: addi s0, s0, -1 ; RV32I-NEXT: and a0, a0, s0 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a0, 292864 ; RV32I-NEXT: addi a1, a0, -256 ; RV32I-NEXT: mv a0, s3 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: bgtz a0, .LBB3_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: slti a0, s2, 0 @@ -842,18 +842,18 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV64I-NEXT: lui s0, 16 ; RV64I-NEXT: addiw s0, s0, -1 ; RV64I-NEXT: and a0, a0, s0 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s3, a0 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: lui a0, 292864 ; RV64I-NEXT: addiw a1, a0, -256 ; RV64I-NEXT: mv a0, s3 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: bgtz a0, .LBB3_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: slti a0, s2, 0 @@ -873,7 +873,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: lui a1, %hi(.LCPI3_0) ; RV32ID-ILP32-NEXT: flw fa5, %lo(.LCPI3_0)(a1) ; RV32ID-ILP32-NEXT: fmv.w.x fa4, a0 @@ -889,7 +889,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: lui a1, %hi(.LCPI3_0) ; RV64ID-LP64-NEXT: flw fa5, %lo(.LCPI3_0)(a1) ; RV64ID-LP64-NEXT: fmv.w.x fa4, a0 @@ -905,7 +905,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: lui a0, %hi(.LCPI3_0) ; RV32ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0) ; RV32ID-NEXT: fmv.w.x fa4, zero @@ -920,7 +920,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: lui a0, %hi(.LCPI3_0) ; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0) ; RV64ID-NEXT: fmv.w.x fa4, zero @@ -1030,8 +1030,8 @@ define i32 @fcvt_w_h(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1042,8 +1042,8 @@ define i32 @fcvt_w_h(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1052,7 +1052,7 @@ define i32 @fcvt_w_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.w.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1063,7 +1063,7 @@ define i32 @fcvt_w_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.l.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1074,7 +1074,7 @@ define i32 @fcvt_w_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -1084,7 +1084,7 @@ define i32 @fcvt_w_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -1185,13 +1185,13 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 847872 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui s3, 524288 ; RV32I-NEXT: bgez s2, .LBB5_2 @@ -1201,14 +1201,14 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV32I-NEXT: lui a1, 323584 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB5_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: addi s1, s3, -1 ; RV32I-NEXT: .LBB5_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -1230,13 +1230,13 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 847872 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui s3, 524288 ; RV64I-NEXT: bgez s2, .LBB5_2 @@ -1246,14 +1246,14 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV64I-NEXT: lui a1, 323584 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB5_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: addiw s1, s3, -1 ; RV64I-NEXT: .LBB5_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -1269,7 +1269,7 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.w.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: feq.s a1, fa5, fa5 @@ -1284,7 +1284,7 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.w.s a0, fa5, rtz ; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5 @@ -1299,7 +1299,7 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV32ID-NEXT: feq.s a1, fa0, fa0 ; RV32ID-NEXT: seqz a1, a1 @@ -1313,7 +1313,7 @@ define i32 @fcvt_w_h_sat(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV64ID-NEXT: feq.s a1, fa0, fa0 ; RV64ID-NEXT: seqz a1, a1 @@ -1420,8 +1420,8 @@ define i32 @fcvt_wu_h(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1432,8 +1432,8 @@ define i32 @fcvt_wu_h(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1442,7 +1442,7 @@ define i32 @fcvt_wu_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.wu.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1453,7 +1453,7 @@ define i32 @fcvt_wu_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.lu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1464,7 +1464,7 @@ define i32 @fcvt_wu_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -1474,7 +1474,7 @@ define i32 @fcvt_wu_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -1563,8 +1563,8 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: seqz a1, a0 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1577,8 +1577,8 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: seqz a1, a0 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1589,7 +1589,7 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.wu.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: seqz a1, a0 @@ -1602,7 +1602,7 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.lu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: seqz a1, a0 @@ -1615,7 +1615,7 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32ID-NEXT: seqz a1, a0 ; RV32ID-NEXT: add a0, a0, a1 @@ -1627,7 +1627,7 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64ID-NEXT: seqz a1, a0 ; RV64ID-NEXT: add a0, a0, a1 @@ -1778,20 +1778,20 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 325632 ; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s1, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: and a0, s2, a0 ; RV32I-NEXT: or a0, s1, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1810,18 +1810,18 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a1, 325632 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB8_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, -1 @@ -1843,7 +1843,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.wu.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: feq.s a1, fa5, fa5 @@ -1858,7 +1858,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.wu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5 @@ -1875,7 +1875,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32ID-NEXT: feq.s a1, fa0, fa0 ; RV32ID-NEXT: seqz a1, a1 @@ -1889,7 +1889,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV64ID-NEXT: feq.s a1, fa0, fa0 ; RV64ID-NEXT: seqz a1, a1 @@ -1977,7 +1977,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __fixhfdi@plt +; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -1991,7 +1991,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __fixhfdi@plt +; RV32IDZFH-NEXT: call __fixhfdi ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -2005,7 +2005,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __fixhfdi@plt +; RV32IZHINX-NEXT: call __fixhfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -2019,7 +2019,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __fixhfdi@plt +; RV32IZDINXZHINX-NEXT: call __fixhfdi ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -2035,8 +2035,8 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfdi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2047,8 +2047,8 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2057,8 +2057,8 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt -; RV32ID-ILP32-NEXT: call __fixsfdi@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 +; RV32ID-ILP32-NEXT: call __fixsfdi ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-ILP32-NEXT: addi sp, sp, 16 ; RV32ID-ILP32-NEXT: ret @@ -2067,7 +2067,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.l.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -2078,8 +2078,8 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt -; RV32ID-NEXT: call __fixsfdi@plt +; RV32ID-NEXT: call __extendhfsf2 +; RV32ID-NEXT: call __fixsfdi ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: ret @@ -2088,7 +2088,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -2098,7 +2098,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __fixhfdi@plt +; CHECK32-IZFHMIN-NEXT: call __fixhfdi ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -2113,7 +2113,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __fixhfdi@plt +; CHECK32-IZHINXMIN-NEXT: call __fixhfdi ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -2128,7 +2128,7 @@ define i64 @fcvt_l_h(half %a) nounwind { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixhfdi@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __fixhfdi ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -2154,7 +2154,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixsfdi@plt +; RV32IZFH-NEXT: call __fixsfdi ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB10_2 @@ -2202,7 +2202,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IDZFH-NEXT: fmv.w.x fa5, a0 ; RV32IDZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0 -; RV32IDZFH-NEXT: call __fixsfdi@plt +; RV32IDZFH-NEXT: call __fixsfdi ; RV32IDZFH-NEXT: lui a4, 524288 ; RV32IDZFH-NEXT: lui a2, 524288 ; RV32IDZFH-NEXT: beqz s0, .LBB10_2 @@ -2257,7 +2257,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IZHINX-NEXT: fle.s s3, a0, s0 ; RV32IZHINX-NEXT: neg s4, s3 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixsfdi@plt +; RV32IZHINX-NEXT: call __fixsfdi ; RV32IZHINX-NEXT: and a0, s4, a0 ; RV32IZHINX-NEXT: or a0, s2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 @@ -2310,7 +2310,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IZDINXZHINX-NEXT: fle.s s3, a0, s0 ; RV32IZDINXZHINX-NEXT: neg s4, s3 ; RV32IZDINXZHINX-NEXT: mv a0, s0 -; RV32IZDINXZHINX-NEXT: call __fixsfdi@plt +; RV32IZDINXZHINX-NEXT: call __fixsfdi ; RV32IZDINXZHINX-NEXT: and a0, s4, a0 ; RV32IZDINXZHINX-NEXT: or a0, s2, a0 ; RV32IZDINXZHINX-NEXT: feq.s a2, s0, s0 @@ -2355,13 +2355,13 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a1, 913408 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __fixsfdi@plt +; RV32I-NEXT: call __fixsfdi ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: lui s5, 524288 @@ -2372,7 +2372,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32I-NEXT: lui a1, 389120 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: blez a0, .LBB10_4 ; RV32I-NEXT: # %bb.3: # %start @@ -2380,7 +2380,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32I-NEXT: .LBB10_4: # %start ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a1, a0, s3 @@ -2411,13 +2411,13 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 913408 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li s3, -1 ; RV64I-NEXT: bgez s2, .LBB10_2 @@ -2427,14 +2427,14 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV64I-NEXT: lui a1, 389120 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB10_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: srli s1, s3, 1 ; RV64I-NEXT: .LBB10_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -2451,13 +2451,13 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa4, a0 ; RV32ID-ILP32-NEXT: lui a1, 913408 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a1 ; RV32ID-ILP32-NEXT: fsw fa4, 4(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: fle.s s0, fa5, fa4 -; RV32ID-ILP32-NEXT: call __fixsfdi@plt +; RV32ID-ILP32-NEXT: call __fixsfdi ; RV32ID-ILP32-NEXT: lui a4, 524288 ; RV32ID-ILP32-NEXT: lui a2, 524288 ; RV32ID-ILP32-NEXT: beqz s0, .LBB10_2 @@ -2490,7 +2490,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.l.s a0, fa5, rtz ; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5 @@ -2507,12 +2507,12 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fmv.s fs0, fa0 ; RV32ID-NEXT: lui a0, 913408 ; RV32ID-NEXT: fmv.w.x fa5, a0 ; RV32ID-NEXT: fle.s s0, fa5, fa0 -; RV32ID-NEXT: call __fixsfdi@plt +; RV32ID-NEXT: call __fixsfdi ; RV32ID-NEXT: lui a4, 524288 ; RV32ID-NEXT: lui a2, 524288 ; RV32ID-NEXT: beqz s0, .LBB10_2 @@ -2544,7 +2544,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz ; RV64ID-NEXT: feq.s a1, fa0, fa0 ; RV64ID-NEXT: seqz a1, a1 @@ -2565,7 +2565,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IFZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IFZFHMIN-NEXT: call __fixsfdi@plt +; RV32IFZFHMIN-NEXT: call __fixsfdi ; RV32IFZFHMIN-NEXT: lui a4, 524288 ; RV32IFZFHMIN-NEXT: lui a2, 524288 ; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_2 @@ -2614,7 +2614,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IDZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IDZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IDZFHMIN-NEXT: call __fixsfdi@plt +; RV32IDZFHMIN-NEXT: call __fixsfdi ; RV32IDZFHMIN-NEXT: lui a4, 524288 ; RV32IDZFHMIN-NEXT: lui a2, 524288 ; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_2 @@ -2660,7 +2660,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; CHECK32-IZHINXMIN-NEXT: fle.s s3, a0, s0 ; CHECK32-IZHINXMIN-NEXT: neg s4, s3 ; CHECK32-IZHINXMIN-NEXT: mv a0, s0 -; CHECK32-IZHINXMIN-NEXT: call __fixsfdi@plt +; CHECK32-IZHINXMIN-NEXT: call __fixsfdi ; CHECK32-IZHINXMIN-NEXT: and a0, s4, a0 ; CHECK32-IZHINXMIN-NEXT: or a0, s2, a0 ; CHECK32-IZHINXMIN-NEXT: feq.s a2, s0, s0 @@ -2714,7 +2714,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; CHECK32-IZDINXZHINXMIN-NEXT: fle.s s3, a0, s0 ; CHECK32-IZDINXZHINXMIN-NEXT: neg s4, s3 ; CHECK32-IZDINXZHINXMIN-NEXT: mv a0, s0 -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixsfdi@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __fixsfdi ; CHECK32-IZDINXZHINXMIN-NEXT: and a0, s4, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: or a0, s2, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: feq.s a2, s0, s0 @@ -2760,7 +2760,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __fixunshfdi@plt +; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -2774,7 +2774,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __fixunshfdi@plt +; RV32IDZFH-NEXT: call __fixunshfdi ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -2788,7 +2788,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __fixunshfdi@plt +; RV32IZHINX-NEXT: call __fixunshfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -2802,7 +2802,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __fixunshfdi@plt +; RV32IZDINXZHINX-NEXT: call __fixunshfdi ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -2818,8 +2818,8 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixunssfdi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixunssfdi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2830,8 +2830,8 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2840,8 +2840,8 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt -; RV32ID-ILP32-NEXT: call __fixunssfdi@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 +; RV32ID-ILP32-NEXT: call __fixunssfdi ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-ILP32-NEXT: addi sp, sp, 16 ; RV32ID-ILP32-NEXT: ret @@ -2850,7 +2850,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.lu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -2861,8 +2861,8 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt -; RV32ID-NEXT: call __fixunssfdi@plt +; RV32ID-NEXT: call __extendhfsf2 +; RV32ID-NEXT: call __fixunssfdi ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: ret @@ -2871,7 +2871,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -2881,7 +2881,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __fixunshfdi@plt +; CHECK32-IZFHMIN-NEXT: call __fixunshfdi ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -2896,7 +2896,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __fixunshfdi@plt +; CHECK32-IZHINXMIN-NEXT: call __fixunshfdi ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -2911,7 +2911,7 @@ define i64 @fcvt_lu_h(half %a) nounwind { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunshfdi@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunshfdi ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -2940,7 +2940,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, zero ; RV32IZFH-NEXT: fle.s a0, fa5, fa0 ; RV32IZFH-NEXT: neg s1, a0 -; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: call __fixunssfdi ; RV32IZFH-NEXT: and a0, s1, a0 ; RV32IZFH-NEXT: or a0, s0, a0 ; RV32IZFH-NEXT: and a1, s1, a1 @@ -2974,7 +2974,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32IDZFH-NEXT: fmv.w.x fa5, zero ; RV32IDZFH-NEXT: fle.s a0, fa5, fa0 ; RV32IDZFH-NEXT: neg s1, a0 -; RV32IDZFH-NEXT: call __fixunssfdi@plt +; RV32IDZFH-NEXT: call __fixunssfdi ; RV32IDZFH-NEXT: and a0, s1, a0 ; RV32IDZFH-NEXT: or a0, s0, a0 ; RV32IDZFH-NEXT: and a1, s1, a1 @@ -3007,7 +3007,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32IZHINX-NEXT: neg s0, a1 ; RV32IZHINX-NEXT: fle.s a1, zero, a0 ; RV32IZHINX-NEXT: neg s1, a1 -; RV32IZHINX-NEXT: call __fixunssfdi@plt +; RV32IZHINX-NEXT: call __fixunssfdi ; RV32IZHINX-NEXT: and a0, s1, a0 ; RV32IZHINX-NEXT: or a0, s0, a0 ; RV32IZHINX-NEXT: and a1, s1, a1 @@ -3040,7 +3040,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32IZDINXZHINX-NEXT: neg s0, a1 ; RV32IZDINXZHINX-NEXT: fle.s a1, zero, a0 ; RV32IZDINXZHINX-NEXT: neg s1, a1 -; RV32IZDINXZHINX-NEXT: call __fixunssfdi@plt +; RV32IZDINXZHINX-NEXT: call __fixunssfdi ; RV32IZDINXZHINX-NEXT: and a0, s1, a0 ; RV32IZDINXZHINX-NEXT: or a0, s0, a0 ; RV32IZDINXZHINX-NEXT: and a1, s1, a1 @@ -3067,20 +3067,20 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 391168 ; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s1, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixunssfdi@plt +; RV32I-NEXT: call __fixunssfdi ; RV32I-NEXT: and a0, s2, a0 ; RV32I-NEXT: or a0, s1, a0 ; RV32I-NEXT: and a1, s2, a1 @@ -3101,20 +3101,20 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 391168 ; RV64I-NEXT: addiw a1, a1, -1 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: neg s1, a0 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: addi s2, a0, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: and a0, s2, a0 ; RV64I-NEXT: or a0, s1, a0 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -3130,7 +3130,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: lui a1, %hi(.LCPI12_0) ; RV32ID-ILP32-NEXT: flw fa5, %lo(.LCPI12_0)(a1) ; RV32ID-ILP32-NEXT: fmv.w.x fa4, a0 @@ -3139,7 +3139,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32ID-ILP32-NEXT: fmv.w.x fa5, zero ; RV32ID-ILP32-NEXT: fle.s a1, fa5, fa4 ; RV32ID-ILP32-NEXT: neg s1, a1 -; RV32ID-ILP32-NEXT: call __fixunssfdi@plt +; RV32ID-ILP32-NEXT: call __fixunssfdi ; RV32ID-ILP32-NEXT: and a0, s1, a0 ; RV32ID-ILP32-NEXT: or a0, s0, a0 ; RV32ID-ILP32-NEXT: and a1, s1, a1 @@ -3154,7 +3154,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.lu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5 @@ -3171,7 +3171,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: lui a0, %hi(.LCPI12_0) ; RV32ID-NEXT: flw fa5, %lo(.LCPI12_0)(a0) ; RV32ID-NEXT: flt.s a0, fa5, fa0 @@ -3179,7 +3179,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32ID-NEXT: fmv.w.x fa5, zero ; RV32ID-NEXT: fle.s a0, fa5, fa0 ; RV32ID-NEXT: neg s1, a0 -; RV32ID-NEXT: call __fixunssfdi@plt +; RV32ID-NEXT: call __fixunssfdi ; RV32ID-NEXT: and a0, s1, a0 ; RV32ID-NEXT: or a0, s0, a0 ; RV32ID-NEXT: and a1, s1, a1 @@ -3194,7 +3194,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64ID-NEXT: feq.s a1, fa0, fa0 ; RV64ID-NEXT: seqz a1, a1 @@ -3218,7 +3218,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; CHECK32-IZFHMIN-NEXT: fmv.w.x fa5, zero ; CHECK32-IZFHMIN-NEXT: fle.s a0, fa5, fa0 ; CHECK32-IZFHMIN-NEXT: neg s1, a0 -; CHECK32-IZFHMIN-NEXT: call __fixunssfdi@plt +; CHECK32-IZFHMIN-NEXT: call __fixunssfdi ; CHECK32-IZFHMIN-NEXT: and a0, s1, a0 ; CHECK32-IZFHMIN-NEXT: or a0, s0, a0 ; CHECK32-IZFHMIN-NEXT: and a1, s1, a1 @@ -3252,7 +3252,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; CHECK32-IZHINXMIN-NEXT: neg s0, a1 ; CHECK32-IZHINXMIN-NEXT: fle.s a1, zero, a0 ; CHECK32-IZHINXMIN-NEXT: neg s1, a1 -; CHECK32-IZHINXMIN-NEXT: call __fixunssfdi@plt +; CHECK32-IZHINXMIN-NEXT: call __fixunssfdi ; CHECK32-IZHINXMIN-NEXT: and a0, s1, a0 ; CHECK32-IZHINXMIN-NEXT: or a0, s0, a0 ; CHECK32-IZHINXMIN-NEXT: and a1, s1, a1 @@ -3286,7 +3286,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; CHECK32-IZDINXZHINXMIN-NEXT: neg s0, a1 ; CHECK32-IZDINXZHINXMIN-NEXT: fle.s a1, zero, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: neg s1, a1 -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunssfdi@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunssfdi ; CHECK32-IZDINXZHINXMIN-NEXT: and a0, s1, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: or a0, s0, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: and a1, s1, a1 @@ -3375,8 +3375,8 @@ define half @fcvt_h_si(i16 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: call __floatsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3387,8 +3387,8 @@ define half @fcvt_h_si(i16 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: call __floatsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3401,7 +3401,7 @@ define half @fcvt_h_si(i16 %a) nounwind { ; RV32ID-ILP32-NEXT: srai a0, a0, 16 ; RV32ID-ILP32-NEXT: fcvt.s.w fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3416,7 +3416,7 @@ define half @fcvt_h_si(i16 %a) nounwind { ; RV64ID-LP64-NEXT: srai a0, a0, 48 ; RV64ID-LP64-NEXT: fcvt.s.w fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -3430,7 +3430,7 @@ define half @fcvt_h_si(i16 %a) nounwind { ; RV32ID-NEXT: slli a0, a0, 16 ; RV32ID-NEXT: srai a0, a0, 16 ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -3446,7 +3446,7 @@ define half @fcvt_h_si(i16 %a) nounwind { ; RV64ID-NEXT: slli a0, a0, 48 ; RV64ID-NEXT: srai a0, a0, 48 ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -3536,8 +3536,8 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3546,8 +3546,8 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3558,7 +3558,7 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind { ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: fcvt.s.w fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3571,7 +3571,7 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind { ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-LP64-NEXT: fcvt.s.w fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -3583,7 +3583,7 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -3597,7 +3597,7 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -3708,8 +3708,8 @@ define half @fcvt_h_ui(i16 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __floatunsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatunsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3720,8 +3720,8 @@ define half @fcvt_h_ui(i16 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __floatunsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatunsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3734,7 +3734,7 @@ define half @fcvt_h_ui(i16 %a) nounwind { ; RV32ID-ILP32-NEXT: srli a0, a0, 16 ; RV32ID-ILP32-NEXT: fcvt.s.wu fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3749,7 +3749,7 @@ define half @fcvt_h_ui(i16 %a) nounwind { ; RV64ID-LP64-NEXT: srli a0, a0, 48 ; RV64ID-LP64-NEXT: fcvt.s.wu fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -3763,7 +3763,7 @@ define half @fcvt_h_ui(i16 %a) nounwind { ; RV32ID-NEXT: slli a0, a0, 16 ; RV32ID-NEXT: srli a0, a0, 16 ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -3779,7 +3779,7 @@ define half @fcvt_h_ui(i16 %a) nounwind { ; RV64ID-NEXT: slli a0, a0, 48 ; RV64ID-NEXT: srli a0, a0, 48 ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -3869,8 +3869,8 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatunsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -3879,8 +3879,8 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatunsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatunsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3891,7 +3891,7 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind { ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: fcvt.s.wu fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3904,7 +3904,7 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind { ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-LP64-NEXT: fcvt.s.wu fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -3916,7 +3916,7 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -3930,7 +3930,7 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -4008,8 +4008,8 @@ define half @fcvt_h_w(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4019,8 +4019,8 @@ define half @fcvt_h_w(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4031,7 +4031,7 @@ define half @fcvt_h_w(i32 %a) nounwind { ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: fcvt.s.w fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4044,7 +4044,7 @@ define half @fcvt_h_w(i32 %a) nounwind { ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-LP64-NEXT: fcvt.s.w fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -4056,7 +4056,7 @@ define half @fcvt_h_w(i32 %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -4070,7 +4070,7 @@ define half @fcvt_h_w(i32 %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -4157,8 +4157,8 @@ define half @fcvt_h_w_load(ptr %p) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4168,8 +4168,8 @@ define half @fcvt_h_w_load(ptr %p) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4181,7 +4181,7 @@ define half @fcvt_h_w_load(ptr %p) nounwind { ; RV32ID-ILP32-NEXT: lw a0, 0(a0) ; RV32ID-ILP32-NEXT: fcvt.s.w fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4195,7 +4195,7 @@ define half @fcvt_h_w_load(ptr %p) nounwind { ; RV64ID-LP64-NEXT: lw a0, 0(a0) ; RV64ID-LP64-NEXT: fcvt.s.w fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -4208,7 +4208,7 @@ define half @fcvt_h_w_load(ptr %p) nounwind { ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: lw a0, 0(a0) ; RV32ID-NEXT: fcvt.s.w fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -4223,7 +4223,7 @@ define half @fcvt_h_w_load(ptr %p) nounwind { ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: lw a0, 0(a0) ; RV64ID-NEXT: fcvt.s.w fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -4308,8 +4308,8 @@ define half @fcvt_h_wu(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatunsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatunsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4319,8 +4319,8 @@ define half @fcvt_h_wu(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: call __floatunsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatunsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4331,7 +4331,7 @@ define half @fcvt_h_wu(i32 %a) nounwind { ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-ILP32-NEXT: fcvt.s.wu fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4344,7 +4344,7 @@ define half @fcvt_h_wu(i32 %a) nounwind { ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-LP64-NEXT: fcvt.s.wu fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -4356,7 +4356,7 @@ define half @fcvt_h_wu(i32 %a) nounwind { ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -4370,7 +4370,7 @@ define half @fcvt_h_wu(i32 %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -4478,8 +4478,8 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, 0(a0) -; RV32I-NEXT: call __floatunsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatunsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4489,8 +4489,8 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: call __floatunsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatunsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4502,7 +4502,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV32ID-ILP32-NEXT: lw a0, 0(a0) ; RV32ID-ILP32-NEXT: fcvt.s.wu fa5, a0 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4516,7 +4516,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV64ID-LP64-NEXT: lwu a0, 0(a0) ; RV64ID-LP64-NEXT: fcvt.s.wu fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -4529,7 +4529,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: lw a0, 0(a0) ; RV32ID-NEXT: fcvt.s.wu fa0, a0 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -4544,7 +4544,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: lwu a0, 0(a0) ; RV64ID-NEXT: fcvt.s.wu fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -4604,7 +4604,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __floatdihf@plt +; RV32IZFH-NEXT: call __floatdihf ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -4618,7 +4618,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __floatdihf@plt +; RV32IDZFH-NEXT: call __floatdihf ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -4632,7 +4632,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __floatdihf@plt +; RV32IZHINX-NEXT: call __floatdihf ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -4646,7 +4646,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __floatdihf@plt +; RV32IZDINXZHINX-NEXT: call __floatdihf ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -4660,8 +4660,8 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatdisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatdisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4670,8 +4670,8 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatdisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatdisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4680,8 +4680,8 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __floatdisf@plt -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __floatdisf +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4694,7 +4694,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-LP64-NEXT: fcvt.s.l fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -4705,8 +4705,8 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __floatdisf@plt -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __floatdisf +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -4720,7 +4720,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.l fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -4733,7 +4733,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __floatdihf@plt +; CHECK32-IZFHMIN-NEXT: call __floatdihf ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -4748,7 +4748,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __floatdihf@plt +; CHECK32-IZHINXMIN-NEXT: call __floatdihf ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -4763,7 +4763,7 @@ define half @fcvt_h_l(i64 %a) nounwind { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __floatdihf@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __floatdihf ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -4782,7 +4782,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __floatundihf@plt +; RV32IZFH-NEXT: call __floatundihf ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -4796,7 +4796,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __floatundihf@plt +; RV32IDZFH-NEXT: call __floatundihf ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret @@ -4810,7 +4810,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __floatundihf@plt +; RV32IZHINX-NEXT: call __floatundihf ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -4824,7 +4824,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV32IZDINXZHINX: # %bb.0: ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __floatundihf@plt +; RV32IZDINXZHINX-NEXT: call __floatundihf ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -4838,8 +4838,8 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __floatundisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatundisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4848,8 +4848,8 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __floatundisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatundisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -4858,8 +4858,8 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __floatundisf@plt -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __floatundisf +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4872,7 +4872,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-LP64-NEXT: fcvt.s.lu fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -4883,8 +4883,8 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __floatundisf@plt -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __floatundisf +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -4898,7 +4898,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ID-NEXT: fcvt.s.lu fa0, a0 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -4911,7 +4911,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; CHECK32-IZFHMIN: # %bb.0: ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZFHMIN-NEXT: call __floatundihf@plt +; CHECK32-IZFHMIN-NEXT: call __floatundihf ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZFHMIN-NEXT: ret @@ -4926,7 +4926,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __floatundihf@plt +; CHECK32-IZHINXMIN-NEXT: call __floatundihf ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -4941,7 +4941,7 @@ define half @fcvt_h_lu(i64 %a) nounwind { ; CHECK32-IZDINXZHINXMIN: # %bb.0: ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __floatundihf@plt +; CHECK32-IZDINXZHINXMIN-NEXT: call __floatundihf ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZDINXZHINXMIN-NEXT: ret @@ -4985,7 +4985,7 @@ define half @fcvt_h_s(float %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -4994,7 +4994,7 @@ define half @fcvt_h_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -5003,7 +5003,7 @@ define half @fcvt_h_s(float %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -5014,7 +5014,7 @@ define half @fcvt_h_s(float %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -5025,7 +5025,7 @@ define half @fcvt_h_s(float %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -5038,7 +5038,7 @@ define half @fcvt_h_s(float %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -5110,7 +5110,7 @@ define float @fcvt_s_h(half %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -5119,7 +5119,7 @@ define float @fcvt_s_h(half %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -5128,7 +5128,7 @@ define float @fcvt_s_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-ILP32-NEXT: addi sp, sp, 16 ; RV32ID-ILP32-NEXT: ret @@ -5137,7 +5137,7 @@ define float @fcvt_s_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-LP64-NEXT: addi sp, sp, 16 ; RV64ID-LP64-NEXT: ret @@ -5146,7 +5146,7 @@ define float @fcvt_s_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: ret @@ -5155,7 +5155,7 @@ define float @fcvt_s_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 ; RV64ID-NEXT: ret @@ -5198,7 +5198,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __truncdfhf2@plt +; RV32IZFH-NEXT: call __truncdfhf2 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -5207,7 +5207,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV64IZFH: # %bb.0: ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call __truncdfhf2@plt +; RV64IZFH-NEXT: call __truncdfhf2 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret @@ -5226,7 +5226,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV32IZHINX: # %bb.0: ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __truncdfhf2@plt +; RV32IZHINX-NEXT: call __truncdfhf2 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -5235,7 +5235,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV64IZHINX: # %bb.0: ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call __truncdfhf2@plt +; RV64IZHINX-NEXT: call __truncdfhf2 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 ; RV64IZHINX-NEXT: ret @@ -5260,7 +5260,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __truncdfhf2@plt +; RV32I-NEXT: call __truncdfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -5269,7 +5269,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __truncdfhf2@plt +; RV64I-NEXT: call __truncdfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -5278,7 +5278,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __truncdfhf2@plt +; RV32ID-ILP32-NEXT: call __truncdfhf2 ; RV32ID-ILP32-NEXT: lui a1, 1048560 ; RV32ID-ILP32-NEXT: or a0, a0, a1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -5289,7 +5289,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __truncdfhf2@plt +; RV64ID-LP64-NEXT: call __truncdfhf2 ; RV64ID-LP64-NEXT: lui a1, 1048560 ; RV64ID-LP64-NEXT: or a0, a0, a1 ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -5300,7 +5300,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __truncdfhf2@plt +; RV32ID-NEXT: call __truncdfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: lui a1, 1048560 ; RV32ID-NEXT: or a0, a0, a1 @@ -5313,7 +5313,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __truncdfhf2@plt +; RV64ID-NEXT: call __truncdfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: lui a1, 1048560 ; RV64ID-NEXT: or a0, a0, a1 @@ -5326,7 +5326,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV32IFZFHMIN: # %bb.0: ; RV32IFZFHMIN-NEXT: addi sp, sp, -16 ; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: call __truncdfhf2@plt +; RV32IFZFHMIN-NEXT: call __truncdfhf2 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFZFHMIN-NEXT: ret @@ -5335,7 +5335,7 @@ define half @fcvt_h_d(double %a) nounwind { ; RV64IFZFHMIN: # %bb.0: ; RV64IFZFHMIN-NEXT: addi sp, sp, -16 ; RV64IFZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFZFHMIN-NEXT: call __truncdfhf2@plt +; RV64IFZFHMIN-NEXT: call __truncdfhf2 ; RV64IFZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFZFHMIN-NEXT: addi sp, sp, 16 ; RV64IFZFHMIN-NEXT: ret @@ -5354,7 +5354,7 @@ define half @fcvt_h_d(double %a) nounwind { ; CHECK32-IZHINXMIN: # %bb.0: ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __truncdfhf2@plt +; CHECK32-IZHINXMIN-NEXT: call __truncdfhf2 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -5363,7 +5363,7 @@ define half @fcvt_h_d(double %a) nounwind { ; CHECK64-IZHINXMIN: # %bb.0: ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; CHECK64-IZHINXMIN-NEXT: call __truncdfhf2@plt +; CHECK64-IZHINXMIN-NEXT: call __truncdfhf2 ; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK64-IZHINXMIN-NEXT: ret @@ -5393,7 +5393,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call __extendsfdf2@plt +; RV32IZFH-NEXT: call __extendsfdf2 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -5403,7 +5403,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call __extendsfdf2@plt +; RV64IZFH-NEXT: call __extendsfdf2 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret @@ -5423,7 +5423,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call __extendsfdf2@plt +; RV32IZHINX-NEXT: call __extendsfdf2 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -5433,7 +5433,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call __extendsfdf2@plt +; RV64IZHINX-NEXT: call __extendsfdf2 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 ; RV64IZHINX-NEXT: ret @@ -5458,8 +5458,8 @@ define double @fcvt_d_h(half %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __extendsfdf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __extendsfdf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -5468,8 +5468,8 @@ define double @fcvt_d_h(half %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __extendsfdf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __extendsfdf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -5478,7 +5478,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.d.s fa5, fa5 ; RV32ID-ILP32-NEXT: fsd fa5, 0(sp) @@ -5492,7 +5492,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.d.s fa5, fa5 ; RV64ID-LP64-NEXT: fmv.x.d a0, fa5 @@ -5504,7 +5504,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.d.s fa0, fa0 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -5514,7 +5514,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.d.s fa0, fa0 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -5525,7 +5525,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV32IFZFHMIN-NEXT: addi sp, sp, -16 ; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IFZFHMIN-NEXT: call __extendsfdf2@plt +; RV32IFZFHMIN-NEXT: call __extendsfdf2 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFZFHMIN-NEXT: ret @@ -5535,7 +5535,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV64IFZFHMIN-NEXT: addi sp, sp, -16 ; RV64IFZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IFZFHMIN-NEXT: call __extendsfdf2@plt +; RV64IFZFHMIN-NEXT: call __extendsfdf2 ; RV64IFZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFZFHMIN-NEXT: addi sp, sp, 16 ; RV64IFZFHMIN-NEXT: ret @@ -5555,7 +5555,7 @@ define double @fcvt_d_h(half %a) nounwind { ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZHINXMIN-NEXT: call __extendsfdf2@plt +; CHECK32-IZHINXMIN-NEXT: call __extendsfdf2 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK32-IZHINXMIN-NEXT: ret @@ -5565,7 +5565,7 @@ define double @fcvt_d_h(half %a) nounwind { ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16 ; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZHINXMIN-NEXT: call __extendsfdf2@plt +; CHECK64-IZHINXMIN-NEXT: call __extendsfdf2 ; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK64-IZHINXMIN-NEXT: ret @@ -5826,8 +5826,8 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -5845,8 +5845,8 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: sh a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -5865,7 +5865,7 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32ID-ILP32-NEXT: addi s1, a0, 1 ; RV32ID-ILP32-NEXT: fcvt.s.w fa5, s1 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: sh a0, 0(s0) ; RV32ID-ILP32-NEXT: mv a0, s1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -5884,7 +5884,7 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64ID-LP64-NEXT: addiw s1, a0, 1 ; RV64ID-LP64-NEXT: fcvt.s.w fa5, s1 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: sh a0, 0(s0) ; RV64ID-LP64-NEXT: mv a0, s1 ; RV64ID-LP64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -5902,7 +5902,7 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32ID-NEXT: mv s0, a1 ; RV32ID-NEXT: addi s1, a0, 1 ; RV32ID-NEXT: fcvt.s.w fa0, s1 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: sh a0, 0(s0) ; RV32ID-NEXT: mv a0, s1 @@ -5921,7 +5921,7 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64ID-NEXT: mv s0, a1 ; RV64ID-NEXT: addiw s1, a0, 1 ; RV64ID-NEXT: fcvt.s.w fa0, s1 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: sh a0, 0(s0) ; RV64ID-NEXT: mv a0, s1 @@ -6051,8 +6051,8 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: addi s1, a0, 1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __floatunsisf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __floatunsisf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -6070,8 +6070,8 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: addiw s1, a0, 1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __floatunsisf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __floatunsisf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: sh a0, 0(s0) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -6090,7 +6090,7 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32ID-ILP32-NEXT: addi s1, a0, 1 ; RV32ID-ILP32-NEXT: fcvt.s.wu fa5, s1 ; RV32ID-ILP32-NEXT: fmv.x.w a0, fa5 -; RV32ID-ILP32-NEXT: call __truncsfhf2@plt +; RV32ID-ILP32-NEXT: call __truncsfhf2 ; RV32ID-ILP32-NEXT: sh a0, 0(s0) ; RV32ID-ILP32-NEXT: mv a0, s1 ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -6109,7 +6109,7 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64ID-LP64-NEXT: addiw s1, a0, 1 ; RV64ID-LP64-NEXT: fcvt.s.wu fa5, s1 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 -; RV64ID-LP64-NEXT: call __truncsfhf2@plt +; RV64ID-LP64-NEXT: call __truncsfhf2 ; RV64ID-LP64-NEXT: sh a0, 0(s0) ; RV64ID-LP64-NEXT: mv a0, s1 ; RV64ID-LP64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -6127,7 +6127,7 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV32ID-NEXT: mv s0, a1 ; RV32ID-NEXT: addi s1, a0, 1 ; RV32ID-NEXT: fcvt.s.wu fa0, s1 -; RV32ID-NEXT: call __truncsfhf2@plt +; RV32ID-NEXT: call __truncsfhf2 ; RV32ID-NEXT: fmv.x.w a0, fa0 ; RV32ID-NEXT: sh a0, 0(s0) ; RV32ID-NEXT: mv a0, s1 @@ -6146,7 +6146,7 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { ; RV64ID-NEXT: mv s0, a1 ; RV64ID-NEXT: addiw s1, a0, 1 ; RV64ID-NEXT: fcvt.s.wu fa0, s1 -; RV64ID-NEXT: call __truncsfhf2@plt +; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 ; RV64ID-NEXT: sh a0, 0(s0) ; RV64ID-NEXT: mv a0, s1 @@ -6262,8 +6262,8 @@ define signext i16 @fcvt_w_s_i16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -6274,8 +6274,8 @@ define signext i16 @fcvt_w_s_i16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -6284,7 +6284,7 @@ define signext i16 @fcvt_w_s_i16(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.w.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -6295,7 +6295,7 @@ define signext i16 @fcvt_w_s_i16(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.l.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -6306,7 +6306,7 @@ define signext i16 @fcvt_w_s_i16(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -6316,7 +6316,7 @@ define signext i16 @fcvt_w_s_i16(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -6487,13 +6487,13 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 815104 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: bgez s2, .LBB32_2 ; RV32I-NEXT: # %bb.1: # %start @@ -6502,7 +6502,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV32I-NEXT: lui a0, 290816 ; RV32I-NEXT: addi a1, a0, -512 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB32_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: lui s1, 8 @@ -6510,7 +6510,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV32I-NEXT: .LBB32_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -6532,13 +6532,13 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 815104 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: bgez s2, .LBB32_2 ; RV64I-NEXT: # %bb.1: # %start @@ -6547,7 +6547,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV64I-NEXT: lui a0, 290816 ; RV64I-NEXT: addiw a1, a0, -512 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB32_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: lui s1, 8 @@ -6555,7 +6555,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV64I-NEXT: .LBB32_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -6572,7 +6572,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: feq.s a0, fa5, fa5 ; RV32ID-ILP32-NEXT: neg a0, a0 @@ -6592,7 +6592,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: feq.s a0, fa5, fa5 ; RV64ID-LP64-NEXT: lui a1, %hi(.LCPI32_0) @@ -6612,7 +6612,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: feq.s a0, fa0, fa0 ; RV32ID-NEXT: neg a0, a0 ; RV32ID-NEXT: lui a1, %hi(.LCPI32_0) @@ -6631,7 +6631,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: feq.s a0, fa0, fa0 ; RV64ID-NEXT: lui a1, %hi(.LCPI32_0) ; RV64ID-NEXT: flw fa5, %lo(.LCPI32_0)(a1) @@ -6783,8 +6783,8 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -6795,8 +6795,8 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -6805,7 +6805,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.wu.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -6816,7 +6816,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.lu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -6827,7 +6827,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -6837,7 +6837,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -6978,18 +6978,18 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV32I-NEXT: lui s3, 16 ; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, 292864 ; RV32I-NEXT: addi a1, a0, -256 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB34_2 ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: mv a0, s3 @@ -7019,18 +7019,18 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV64I-NEXT: lui s3, 16 ; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 292864 ; RV64I-NEXT: addiw a1, a0, -256 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB34_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: mv a0, s3 @@ -7053,7 +7053,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: lui a1, %hi(.LCPI34_0) ; RV32ID-ILP32-NEXT: flw fa5, %lo(.LCPI34_0)(a1) ; RV32ID-ILP32-NEXT: fmv.w.x fa4, a0 @@ -7069,7 +7069,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: lui a1, %hi(.LCPI34_0) ; RV64ID-LP64-NEXT: flw fa5, %lo(.LCPI34_0)(a1) ; RV64ID-LP64-NEXT: fmv.w.x fa4, a0 @@ -7085,7 +7085,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: lui a0, %hi(.LCPI34_0) ; RV32ID-NEXT: flw fa5, %lo(.LCPI34_0)(a0) ; RV32ID-NEXT: fmv.w.x fa4, zero @@ -7100,7 +7100,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: lui a0, %hi(.LCPI34_0) ; RV64ID-NEXT: flw fa5, %lo(.LCPI34_0)(a0) ; RV64ID-NEXT: fmv.w.x fa4, zero @@ -7224,8 +7224,8 @@ define signext i8 @fcvt_w_s_i8(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7236,8 +7236,8 @@ define signext i8 @fcvt_w_s_i8(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7246,7 +7246,7 @@ define signext i8 @fcvt_w_s_i8(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.w.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -7257,7 +7257,7 @@ define signext i8 @fcvt_w_s_i8(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.l.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -7268,7 +7268,7 @@ define signext i8 @fcvt_w_s_i8(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -7278,7 +7278,7 @@ define signext i8 @fcvt_w_s_i8(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.l.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -7445,13 +7445,13 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 798720 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: bgez s2, .LBB36_2 ; RV32I-NEXT: # %bb.1: # %start @@ -7459,14 +7459,14 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV32I-NEXT: .LBB36_2: # %start ; RV32I-NEXT: lui a1, 274400 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB36_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: li s1, 127 ; RV32I-NEXT: .LBB36_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -7488,13 +7488,13 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 798720 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: bgez s2, .LBB36_2 ; RV64I-NEXT: # %bb.1: # %start @@ -7502,14 +7502,14 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV64I-NEXT: .LBB36_2: # %start ; RV64I-NEXT: lui a1, 274400 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB36_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: li s1, 127 ; RV64I-NEXT: .LBB36_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -7526,7 +7526,7 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: feq.s a0, fa5, fa5 ; RV32ID-ILP32-NEXT: neg a0, a0 @@ -7546,7 +7546,7 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: feq.s a0, fa5, fa5 ; RV64ID-LP64-NEXT: neg a0, a0 @@ -7566,7 +7566,7 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: feq.s a0, fa0, fa0 ; RV32ID-NEXT: neg a0, a0 ; RV32ID-NEXT: lui a1, 798720 @@ -7585,7 +7585,7 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: feq.s a0, fa0, fa0 ; RV64ID-NEXT: neg a0, a0 ; RV64ID-NEXT: lui a1, 798720 @@ -7734,8 +7734,8 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -7746,8 +7746,8 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -7756,7 +7756,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.wu.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -7767,7 +7767,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.lu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -7778,7 +7778,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind { ; RV32ID: # %bb.0: ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: addi sp, sp, 16 @@ -7788,7 +7788,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64ID-NEXT: addi sp, sp, 16 @@ -7923,17 +7923,17 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a1, 276464 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB38_2 ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: li a0, 255 @@ -7960,17 +7960,17 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a1, 276464 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB38_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, 255 @@ -7992,7 +7992,7 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fmv.w.x fa4, zero ; RV32ID-ILP32-NEXT: fmax.s fa5, fa5, fa4 @@ -8008,7 +8008,7 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fmv.w.x fa4, zero ; RV64ID-LP64-NEXT: fmax.s fa5, fa5, fa4 @@ -8024,7 +8024,7 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fmv.w.x fa5, zero ; RV32ID-NEXT: fmax.s fa5, fa0, fa5 ; RV32ID-NEXT: lui a0, 276464 @@ -8039,7 +8039,7 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fmv.w.x fa5, zero ; RV64ID-NEXT: fmax.s fa5, fa0, fa5 ; RV64ID-NEXT: lui a0, 276464 @@ -8203,20 +8203,20 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 325632 ; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s1, a0 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixunssfsi@plt +; RV32I-NEXT: call __fixunssfsi ; RV32I-NEXT: and a0, s2, a0 ; RV32I-NEXT: or a0, s1, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -8235,18 +8235,18 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __fixunssfdi@plt +; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a1, 325632 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB39_2 ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li a0, -1 @@ -8270,7 +8270,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.wu.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: feq.s a1, fa5, fa5 @@ -8285,7 +8285,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.wu.s a0, fa5, rtz ; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5 @@ -8302,7 +8302,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV32ID-NEXT: feq.s a1, fa0, fa0 ; RV32ID-NEXT: seqz a1, a1 @@ -8316,7 +8316,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.wu.s a0, fa0, rtz ; RV64ID-NEXT: feq.s a1, fa0, fa0 ; RV64ID-NEXT: seqz a1, a1 @@ -8454,13 +8454,13 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 847872 -; RV32I-NEXT: call __gesf2@plt +; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __fixsfsi@plt +; RV32I-NEXT: call __fixsfsi ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui s3, 524288 ; RV32I-NEXT: bgez s2, .LBB40_2 @@ -8470,14 +8470,14 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV32I-NEXT: lui a1, 323584 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2@plt +; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: blez a0, .LBB40_4 ; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: addi s1, s3, -1 ; RV32I-NEXT: .LBB40_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __unordsf2@plt +; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, s1 @@ -8499,13 +8499,13 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lui a1, 847872 -; RV64I-NEXT: call __gesf2@plt +; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __fixsfdi@plt +; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui s3, 524288 ; RV64I-NEXT: bgez s2, .LBB40_2 @@ -8515,14 +8515,14 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV64I-NEXT: lui a1, 323584 ; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __gtsf2@plt +; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: blez a0, .LBB40_4 ; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: addi s1, s3, -1 ; RV64I-NEXT: .LBB40_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __unordsf2@plt +; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, s1 @@ -8539,7 +8539,7 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV32ID-ILP32: # %bb.0: # %start ; RV32ID-ILP32-NEXT: addi sp, sp, -16 ; RV32ID-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-ILP32-NEXT: call __extendhfsf2@plt +; RV32ID-ILP32-NEXT: call __extendhfsf2 ; RV32ID-ILP32-NEXT: fmv.w.x fa5, a0 ; RV32ID-ILP32-NEXT: fcvt.w.s a0, fa5, rtz ; RV32ID-ILP32-NEXT: feq.s a1, fa5, fa5 @@ -8554,7 +8554,7 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV64ID-LP64: # %bb.0: # %start ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: call __extendhfsf2@plt +; RV64ID-LP64-NEXT: call __extendhfsf2 ; RV64ID-LP64-NEXT: fmv.w.x fa5, a0 ; RV64ID-LP64-NEXT: fcvt.w.s a0, fa5, rtz ; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5 @@ -8569,7 +8569,7 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV32ID: # %bb.0: # %start ; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: call __extendhfsf2@plt +; RV32ID-NEXT: call __extendhfsf2 ; RV32ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV32ID-NEXT: feq.s a1, fa0, fa0 ; RV32ID-NEXT: seqz a1, a1 @@ -8583,7 +8583,7 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind { ; RV64ID: # %bb.0: # %start ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: call __extendhfsf2@plt +; RV64ID-NEXT: call __extendhfsf2 ; RV64ID-NEXT: fcvt.w.s a0, fa0, rtz ; RV64ID-NEXT: feq.s a1, fa0, fa0 ; RV64ID-NEXT: seqz a1, a1 diff --git a/llvm/test/CodeGen/RISCV/half-frem.ll b/llvm/test/CodeGen/RISCV/half-frem.ll index 73d1760c8596..a262094190e1 100644 --- a/llvm/test/CodeGen/RISCV/half-frem.ll +++ b/llvm/test/CodeGen/RISCV/half-frem.ll @@ -31,7 +31,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa1, fa1 -; RV32IZFH-NEXT: call fmodf@plt +; RV32IZFH-NEXT: call fmodf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -43,7 +43,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa1, fa1 -; RV64IZFH-NEXT: call fmodf@plt +; RV64IZFH-NEXT: call fmodf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -55,7 +55,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 ; RV32IZHINX-NEXT: fcvt.s.h a1, a1 -; RV32IZHINX-NEXT: call fmodf@plt +; RV32IZHINX-NEXT: call fmodf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -67,7 +67,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 ; RV64IZHINX-NEXT: fcvt.s.h a1, a1 -; RV64IZHINX-NEXT: call fmodf@plt +; RV64IZHINX-NEXT: call fmodf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -79,7 +79,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFHMIN-NEXT: fcvt.s.h fa1, fa1 -; RV32IZFHMIN-NEXT: call fmodf@plt +; RV32IZFHMIN-NEXT: call fmodf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -91,7 +91,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa1, fa1 -; RV64IZFHMIN-NEXT: call fmodf@plt +; RV64IZFHMIN-NEXT: call fmodf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -103,7 +103,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV32IZHINXMIN-NEXT: call fmodf@plt +; RV32IZHINXMIN-NEXT: call fmodf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -115,7 +115,7 @@ define half @frem_f16(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV64IZHINXMIN-NEXT: call fmodf@plt +; RV64IZHINXMIN-NEXT: call fmodf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll index 2d4b7538c34d..c493a9b2cb1d 100644 --- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll @@ -75,9 +75,9 @@ define half @sqrt_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call sqrtf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call sqrtf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -88,9 +88,9 @@ define half @sqrt_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call sqrtf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call sqrtf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -120,7 +120,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call __powisf2@plt +; RV32IZFH-NEXT: call __powisf2 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -132,7 +132,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV64IZFH-NEXT: sext.w a0, a0 -; RV64IZFH-NEXT: call __powisf2@plt +; RV64IZFH-NEXT: call __powisf2 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -143,7 +143,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call __powisf2@plt +; RV32IZHINX-NEXT: call __powisf2 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -155,7 +155,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: sext.w a1, a1 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call __powisf2@plt +; RV64IZHINX-NEXT: call __powisf2 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -169,10 +169,10 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __powisf2@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __powisf2 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -186,10 +186,10 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: sext.w a1, s0 -; RV64I-NEXT: call __powisf2@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __powisf2 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -200,7 +200,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call __powisf2@plt +; RV32IZFHMIN-NEXT: call __powisf2 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -212,7 +212,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 ; RV64IZFHMIN-NEXT: sext.w a0, a0 -; RV64IZFHMIN-NEXT: call __powisf2@plt +; RV64IZFHMIN-NEXT: call __powisf2 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -223,7 +223,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call __powisf2@plt +; RV32IZHINXMIN-NEXT: call __powisf2 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -235,7 +235,7 @@ define half @powi_f16(half %a, i32 %b) nounwind { ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: sext.w a1, a1 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call __powisf2@plt +; RV64IZHINXMIN-NEXT: call __powisf2 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -252,7 +252,7 @@ define half @sin_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call sinf@plt +; RV32IZFH-NEXT: call sinf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -263,7 +263,7 @@ define half @sin_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call sinf@plt +; RV64IZFH-NEXT: call sinf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -274,7 +274,7 @@ define half @sin_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call sinf@plt +; RV32IZHINX-NEXT: call sinf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -285,7 +285,7 @@ define half @sin_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call sinf@plt +; RV64IZHINX-NEXT: call sinf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -297,9 +297,9 @@ define half @sin_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call sinf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call sinf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -310,9 +310,9 @@ define half @sin_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call sinf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call sinf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -322,7 +322,7 @@ define half @sin_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call sinf@plt +; RV32IZFHMIN-NEXT: call sinf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -333,7 +333,7 @@ define half @sin_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call sinf@plt +; RV64IZFHMIN-NEXT: call sinf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -344,7 +344,7 @@ define half @sin_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call sinf@plt +; RV32IZHINXMIN-NEXT: call sinf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -355,7 +355,7 @@ define half @sin_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call sinf@plt +; RV64IZHINXMIN-NEXT: call sinf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -372,7 +372,7 @@ define half @cos_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call cosf@plt +; RV32IZFH-NEXT: call cosf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -383,7 +383,7 @@ define half @cos_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call cosf@plt +; RV64IZFH-NEXT: call cosf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -394,7 +394,7 @@ define half @cos_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call cosf@plt +; RV32IZHINX-NEXT: call cosf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -405,7 +405,7 @@ define half @cos_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call cosf@plt +; RV64IZHINX-NEXT: call cosf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -417,9 +417,9 @@ define half @cos_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call cosf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call cosf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -430,9 +430,9 @@ define half @cos_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call cosf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call cosf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -442,7 +442,7 @@ define half @cos_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call cosf@plt +; RV32IZFHMIN-NEXT: call cosf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -453,7 +453,7 @@ define half @cos_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call cosf@plt +; RV64IZFHMIN-NEXT: call cosf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -464,7 +464,7 @@ define half @cos_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call cosf@plt +; RV32IZHINXMIN-NEXT: call cosf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -475,7 +475,7 @@ define half @cos_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call cosf@plt +; RV64IZHINXMIN-NEXT: call cosf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -494,10 +494,10 @@ define half @sincos_f16(half %a) nounwind { ; RV32IFZFH-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill ; RV32IFZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IFZFH-NEXT: fmv.s fa0, fs0 -; RV32IFZFH-NEXT: call sinf@plt +; RV32IFZFH-NEXT: call sinf ; RV32IFZFH-NEXT: fcvt.h.s fs1, fa0 ; RV32IFZFH-NEXT: fmv.s fa0, fs0 -; RV32IFZFH-NEXT: call cosf@plt +; RV32IFZFH-NEXT: call cosf ; RV32IFZFH-NEXT: fcvt.h.s fa5, fa0 ; RV32IFZFH-NEXT: fadd.h fa0, fs1, fa5 ; RV32IFZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -514,10 +514,10 @@ define half @sincos_f16(half %a) nounwind { ; RV64IFZFH-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill ; RV64IFZFH-NEXT: fcvt.s.h fs0, fa0 ; RV64IFZFH-NEXT: fmv.s fa0, fs0 -; RV64IFZFH-NEXT: call sinf@plt +; RV64IFZFH-NEXT: call sinf ; RV64IFZFH-NEXT: fcvt.h.s fs1, fa0 ; RV64IFZFH-NEXT: fmv.s fa0, fs0 -; RV64IFZFH-NEXT: call cosf@plt +; RV64IFZFH-NEXT: call cosf ; RV64IFZFH-NEXT: fcvt.h.s fa5, fa0 ; RV64IFZFH-NEXT: fadd.h fa0, fs1, fa5 ; RV64IFZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -534,10 +534,10 @@ define half @sincos_f16(half %a) nounwind { ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call sinf@plt +; RV32IZHINX-NEXT: call sinf ; RV32IZHINX-NEXT: fcvt.h.s s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call cosf@plt +; RV32IZHINX-NEXT: call cosf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: fadd.h a0, s1, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -554,10 +554,10 @@ define half @sincos_f16(half %a) nounwind { ; RV64IZHINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h s0, a0 ; RV64IZHINX-NEXT: mv a0, s0 -; RV64IZHINX-NEXT: call sinf@plt +; RV64IZHINX-NEXT: call sinf ; RV64IZHINX-NEXT: fcvt.h.s s1, a0 ; RV64IZHINX-NEXT: mv a0, s0 -; RV64IZHINX-NEXT: call cosf@plt +; RV64IZHINX-NEXT: call cosf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: fadd.h a0, s1, a0 ; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -574,10 +574,10 @@ define half @sincos_f16(half %a) nounwind { ; RV32IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0 -; RV32IDZFH-NEXT: call sinf@plt +; RV32IDZFH-NEXT: call sinf ; RV32IDZFH-NEXT: fcvt.h.s fs1, fa0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0 -; RV32IDZFH-NEXT: call cosf@plt +; RV32IDZFH-NEXT: call cosf ; RV32IDZFH-NEXT: fcvt.h.s fa5, fa0 ; RV32IDZFH-NEXT: fadd.h fa0, fs1, fa5 ; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -594,10 +594,10 @@ define half @sincos_f16(half %a) nounwind { ; RV64IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV64IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV64IDZFH-NEXT: fmv.s fa0, fs0 -; RV64IDZFH-NEXT: call sinf@plt +; RV64IDZFH-NEXT: call sinf ; RV64IDZFH-NEXT: fcvt.h.s fs1, fa0 ; RV64IDZFH-NEXT: fmv.s fa0, fs0 -; RV64IDZFH-NEXT: call cosf@plt +; RV64IDZFH-NEXT: call cosf ; RV64IDZFH-NEXT: fcvt.h.s fa5, fa0 ; RV64IDZFH-NEXT: fadd.h fa0, fs1, fa5 ; RV64IDZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -616,24 +616,24 @@ define half @sincos_f16(half %a) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: call sinf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call sinf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call cosf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call cosf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s1, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -651,24 +651,24 @@ define half @sincos_f16(half %a) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: call sinf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call sinf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call cosf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call cosf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s1, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -684,10 +684,10 @@ define half @sincos_f16(half %a) nounwind { ; RV32IFZFHMIN-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill ; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IFZFHMIN-NEXT: call sinf@plt +; RV32IFZFHMIN-NEXT: call sinf ; RV32IFZFHMIN-NEXT: fcvt.h.s fs1, fa0 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IFZFHMIN-NEXT: call cosf@plt +; RV32IFZFHMIN-NEXT: call cosf ; RV32IFZFHMIN-NEXT: fcvt.h.s fa5, fa0 ; RV32IFZFHMIN-NEXT: fcvt.s.h fa5, fa5 ; RV32IFZFHMIN-NEXT: fcvt.s.h fa4, fs1 @@ -707,10 +707,10 @@ define half @sincos_f16(half %a) nounwind { ; RV64IFZFHMIN-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill ; RV64IFZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV64IFZFHMIN-NEXT: fmv.s fa0, fs0 -; RV64IFZFHMIN-NEXT: call sinf@plt +; RV64IFZFHMIN-NEXT: call sinf ; RV64IFZFHMIN-NEXT: fcvt.h.s fs1, fa0 ; RV64IFZFHMIN-NEXT: fmv.s fa0, fs0 -; RV64IFZFHMIN-NEXT: call cosf@plt +; RV64IFZFHMIN-NEXT: call cosf ; RV64IFZFHMIN-NEXT: fcvt.h.s fa5, fa0 ; RV64IFZFHMIN-NEXT: fcvt.s.h fa5, fa5 ; RV64IFZFHMIN-NEXT: fcvt.s.h fa4, fs1 @@ -730,10 +730,10 @@ define half @sincos_f16(half %a) nounwind { ; RV32IDZFHMIN-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IDZFHMIN-NEXT: call sinf@plt +; RV32IDZFHMIN-NEXT: call sinf ; RV32IDZFHMIN-NEXT: fcvt.h.s fs1, fa0 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IDZFHMIN-NEXT: call cosf@plt +; RV32IDZFHMIN-NEXT: call cosf ; RV32IDZFHMIN-NEXT: fcvt.h.s fa5, fa0 ; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa5 ; RV32IDZFHMIN-NEXT: fcvt.s.h fa4, fs1 @@ -753,10 +753,10 @@ define half @sincos_f16(half %a) nounwind { ; RV64IDZFHMIN-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV64IDZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV64IDZFHMIN-NEXT: fmv.s fa0, fs0 -; RV64IDZFHMIN-NEXT: call sinf@plt +; RV64IDZFHMIN-NEXT: call sinf ; RV64IDZFHMIN-NEXT: fcvt.h.s fs1, fa0 ; RV64IDZFHMIN-NEXT: fmv.s fa0, fs0 -; RV64IDZFHMIN-NEXT: call cosf@plt +; RV64IDZFHMIN-NEXT: call cosf ; RV64IDZFHMIN-NEXT: fcvt.h.s fa5, fa0 ; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa5 ; RV64IDZFHMIN-NEXT: fcvt.s.h fa4, fs1 @@ -776,10 +776,10 @@ define half @sincos_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call sinf@plt +; RV32IZHINXMIN-NEXT: call sinf ; RV32IZHINXMIN-NEXT: fcvt.h.s s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call cosf@plt +; RV32IZHINXMIN-NEXT: call cosf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, s1 @@ -799,10 +799,10 @@ define half @sincos_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h s0, a0 ; RV64IZHINXMIN-NEXT: mv a0, s0 -; RV64IZHINXMIN-NEXT: call sinf@plt +; RV64IZHINXMIN-NEXT: call sinf ; RV64IZHINXMIN-NEXT: fcvt.h.s s1, a0 ; RV64IZHINXMIN-NEXT: mv a0, s0 -; RV64IZHINXMIN-NEXT: call cosf@plt +; RV64IZHINXMIN-NEXT: call cosf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, s1 @@ -828,7 +828,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa1, fa1 -; RV32IZFH-NEXT: call powf@plt +; RV32IZFH-NEXT: call powf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -840,7 +840,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa1, fa1 -; RV64IZFH-NEXT: call powf@plt +; RV64IZFH-NEXT: call powf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -852,7 +852,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 ; RV32IZHINX-NEXT: fcvt.s.h a1, a1 -; RV32IZHINX-NEXT: call powf@plt +; RV32IZHINX-NEXT: call powf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -864,7 +864,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 ; RV64IZHINX-NEXT: fcvt.s.h a1, a1 -; RV64IZHINX-NEXT: call powf@plt +; RV64IZHINX-NEXT: call powf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -881,14 +881,14 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call powf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call powf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -907,14 +907,14 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call powf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call powf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -928,7 +928,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFHMIN-NEXT: fcvt.s.h fa1, fa1 -; RV32IZFHMIN-NEXT: call powf@plt +; RV32IZFHMIN-NEXT: call powf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -940,7 +940,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa1, fa1 -; RV64IZFHMIN-NEXT: call powf@plt +; RV64IZFHMIN-NEXT: call powf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -952,7 +952,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV32IZHINXMIN-NEXT: call powf@plt +; RV32IZHINXMIN-NEXT: call powf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -964,7 +964,7 @@ define half @pow_f16(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV64IZHINXMIN-NEXT: call powf@plt +; RV64IZHINXMIN-NEXT: call powf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -981,7 +981,7 @@ define half @exp_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call expf@plt +; RV32IZFH-NEXT: call expf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -992,7 +992,7 @@ define half @exp_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call expf@plt +; RV64IZFH-NEXT: call expf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -1003,7 +1003,7 @@ define half @exp_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call expf@plt +; RV32IZHINX-NEXT: call expf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -1014,7 +1014,7 @@ define half @exp_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call expf@plt +; RV64IZHINX-NEXT: call expf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -1026,9 +1026,9 @@ define half @exp_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call expf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call expf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1039,9 +1039,9 @@ define half @exp_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call expf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call expf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1051,7 +1051,7 @@ define half @exp_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call expf@plt +; RV32IZFHMIN-NEXT: call expf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -1062,7 +1062,7 @@ define half @exp_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call expf@plt +; RV64IZFHMIN-NEXT: call expf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -1073,7 +1073,7 @@ define half @exp_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call expf@plt +; RV32IZHINXMIN-NEXT: call expf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1084,7 +1084,7 @@ define half @exp_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call expf@plt +; RV64IZHINXMIN-NEXT: call expf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1101,7 +1101,7 @@ define half @exp2_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call exp2f@plt +; RV32IZFH-NEXT: call exp2f ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -1112,7 +1112,7 @@ define half @exp2_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call exp2f@plt +; RV64IZFH-NEXT: call exp2f ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -1123,7 +1123,7 @@ define half @exp2_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call exp2f@plt +; RV32IZHINX-NEXT: call exp2f ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -1134,7 +1134,7 @@ define half @exp2_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call exp2f@plt +; RV64IZHINX-NEXT: call exp2f ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -1146,9 +1146,9 @@ define half @exp2_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call exp2f@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call exp2f +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1159,9 +1159,9 @@ define half @exp2_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call exp2f@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call exp2f +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1171,7 +1171,7 @@ define half @exp2_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call exp2f@plt +; RV32IZFHMIN-NEXT: call exp2f ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -1182,7 +1182,7 @@ define half @exp2_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call exp2f@plt +; RV64IZFHMIN-NEXT: call exp2f ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -1193,7 +1193,7 @@ define half @exp2_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call exp2f@plt +; RV32IZHINXMIN-NEXT: call exp2f ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1204,7 +1204,7 @@ define half @exp2_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call exp2f@plt +; RV64IZHINXMIN-NEXT: call exp2f ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1221,7 +1221,7 @@ define half @log_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call logf@plt +; RV32IZFH-NEXT: call logf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -1232,7 +1232,7 @@ define half @log_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call logf@plt +; RV64IZFH-NEXT: call logf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -1243,7 +1243,7 @@ define half @log_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call logf@plt +; RV32IZHINX-NEXT: call logf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -1254,7 +1254,7 @@ define half @log_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call logf@plt +; RV64IZHINX-NEXT: call logf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -1266,9 +1266,9 @@ define half @log_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call logf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call logf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1279,9 +1279,9 @@ define half @log_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call logf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call logf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1291,7 +1291,7 @@ define half @log_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call logf@plt +; RV32IZFHMIN-NEXT: call logf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -1302,7 +1302,7 @@ define half @log_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call logf@plt +; RV64IZFHMIN-NEXT: call logf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -1313,7 +1313,7 @@ define half @log_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call logf@plt +; RV32IZHINXMIN-NEXT: call logf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1324,7 +1324,7 @@ define half @log_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call logf@plt +; RV64IZHINXMIN-NEXT: call logf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1341,7 +1341,7 @@ define half @log10_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call log10f@plt +; RV32IZFH-NEXT: call log10f ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -1352,7 +1352,7 @@ define half @log10_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call log10f@plt +; RV64IZFH-NEXT: call log10f ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -1363,7 +1363,7 @@ define half @log10_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call log10f@plt +; RV32IZHINX-NEXT: call log10f ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -1374,7 +1374,7 @@ define half @log10_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call log10f@plt +; RV64IZHINX-NEXT: call log10f ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -1386,9 +1386,9 @@ define half @log10_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call log10f@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call log10f +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1399,9 +1399,9 @@ define half @log10_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call log10f@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call log10f +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1411,7 +1411,7 @@ define half @log10_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call log10f@plt +; RV32IZFHMIN-NEXT: call log10f ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -1422,7 +1422,7 @@ define half @log10_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call log10f@plt +; RV64IZFHMIN-NEXT: call log10f ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -1433,7 +1433,7 @@ define half @log10_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call log10f@plt +; RV32IZHINXMIN-NEXT: call log10f ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1444,7 +1444,7 @@ define half @log10_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call log10f@plt +; RV64IZHINXMIN-NEXT: call log10f ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1461,7 +1461,7 @@ define half @log2_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call log2f@plt +; RV32IZFH-NEXT: call log2f ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -1472,7 +1472,7 @@ define half @log2_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call log2f@plt +; RV64IZFH-NEXT: call log2f ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -1483,7 +1483,7 @@ define half @log2_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call log2f@plt +; RV32IZHINX-NEXT: call log2f ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -1494,7 +1494,7 @@ define half @log2_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call log2f@plt +; RV64IZHINX-NEXT: call log2f ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -1506,9 +1506,9 @@ define half @log2_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call log2f@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call log2f +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1519,9 +1519,9 @@ define half @log2_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call log2f@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call log2f +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1531,7 +1531,7 @@ define half @log2_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call log2f@plt +; RV32IZFHMIN-NEXT: call log2f ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -1542,7 +1542,7 @@ define half @log2_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call log2f@plt +; RV64IZFHMIN-NEXT: call log2f ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -1553,7 +1553,7 @@ define half @log2_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call log2f@plt +; RV32IZHINXMIN-NEXT: call log2f ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1564,7 +1564,7 @@ define half @log2_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call log2f@plt +; RV64IZHINXMIN-NEXT: call log2f ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -1599,18 +1599,18 @@ define half @fma_f16(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s3, a1, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call fmaf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1632,18 +1632,18 @@ define half @fma_f16(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s3, a1, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call fmaf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1699,23 +1699,23 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s3, a1, -1 ; RV32I-NEXT: and a0, a0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __mulsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __mulsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: and a0, s1, s3 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1737,23 +1737,23 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s3, a1, -1 ; RV64I-NEXT: and a0, a0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __mulsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __mulsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: and a0, s1, s3 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1867,14 +1867,14 @@ define half @minnum_f16(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call fminf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fminf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1893,14 +1893,14 @@ define half @minnum_f16(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fminf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fminf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1951,14 +1951,14 @@ define half @maxnum_f16(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call fmaxf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call fmaxf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1977,14 +1977,14 @@ define half @maxnum_f16(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call fmaxf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call fmaxf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2159,9 +2159,9 @@ define half @floor_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call floorf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call floorf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2172,9 +2172,9 @@ define half @floor_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call floorf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call floorf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2250,9 +2250,9 @@ define half @ceil_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call ceilf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call ceilf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2263,9 +2263,9 @@ define half @ceil_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call ceilf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call ceilf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2341,9 +2341,9 @@ define half @trunc_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call truncf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call truncf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2354,9 +2354,9 @@ define half @trunc_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call truncf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call truncf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2432,9 +2432,9 @@ define half @rint_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call rintf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call rintf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2445,9 +2445,9 @@ define half @rint_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call rintf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call rintf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2494,7 +2494,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call nearbyintf@plt +; RV32IZFH-NEXT: call nearbyintf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -2505,7 +2505,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call nearbyintf@plt +; RV64IZFH-NEXT: call nearbyintf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -2516,7 +2516,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call nearbyintf@plt +; RV32IZHINX-NEXT: call nearbyintf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -2527,7 +2527,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call nearbyintf@plt +; RV64IZHINX-NEXT: call nearbyintf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -2539,9 +2539,9 @@ define half @nearbyint_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call nearbyintf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call nearbyintf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2552,9 +2552,9 @@ define half @nearbyint_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call nearbyintf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call nearbyintf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2564,7 +2564,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call nearbyintf@plt +; RV32IZFHMIN-NEXT: call nearbyintf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -2575,7 +2575,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call nearbyintf@plt +; RV64IZFHMIN-NEXT: call nearbyintf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -2586,7 +2586,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: call nearbyintf@plt +; RV32IZHINXMIN-NEXT: call nearbyintf ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 @@ -2597,7 +2597,7 @@ define half @nearbyint_f16(half %a) nounwind { ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: call nearbyintf@plt +; RV64IZHINXMIN-NEXT: call nearbyintf ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 @@ -2643,9 +2643,9 @@ define half @round_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call roundf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call roundf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2656,9 +2656,9 @@ define half @round_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call roundf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call roundf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -2734,9 +2734,9 @@ define half @roundeven_f16(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt -; RV32I-NEXT: call roundevenf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __extendhfsf2 +; RV32I-NEXT: call roundevenf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -2747,9 +2747,9 @@ define half @roundeven_f16(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: call roundevenf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __extendhfsf2 +; RV64I-NEXT: call roundevenf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/half-mem.ll b/llvm/test/CodeGen/RISCV/half-mem.ll index bb25d2a7443d..5b6a94a83f94 100644 --- a/llvm/test/CodeGen/RISCV/half-mem.ll +++ b/llvm/test/CodeGen/RISCV/half-mem.ll @@ -264,7 +264,7 @@ define half @flh_stack(half %a) nounwind { ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fmv.h fs0, fa0 ; RV32IZFH-NEXT: addi a0, sp, 4 -; RV32IZFH-NEXT: call notdead@plt +; RV32IZFH-NEXT: call notdead ; RV32IZFH-NEXT: flh fa5, 4(sp) ; RV32IZFH-NEXT: fadd.h fa0, fa5, fs0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -279,7 +279,7 @@ define half @flh_stack(half %a) nounwind { ; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IZFH-NEXT: fmv.h fs0, fa0 ; RV64IZFH-NEXT: mv a0, sp -; RV64IZFH-NEXT: call notdead@plt +; RV64IZFH-NEXT: call notdead ; RV64IZFH-NEXT: flh fa5, 0(sp) ; RV64IZFH-NEXT: fadd.h fa0, fa5, fs0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -294,7 +294,7 @@ define half @flh_stack(half %a) nounwind { ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: mv s0, a0 ; RV32IZHINX-NEXT: addi a0, sp, 4 -; RV32IZHINX-NEXT: call notdead@plt +; RV32IZHINX-NEXT: call notdead ; RV32IZHINX-NEXT: lh a0, 4(sp) ; RV32IZHINX-NEXT: fadd.h a0, a0, s0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -309,7 +309,7 @@ define half @flh_stack(half %a) nounwind { ; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: mv s0, a0 ; RV64IZHINX-NEXT: addi a0, sp, 12 -; RV64IZHINX-NEXT: call notdead@plt +; RV64IZHINX-NEXT: call notdead ; RV64IZHINX-NEXT: lh a0, 12(sp) ; RV64IZHINX-NEXT: fadd.h a0, a0, s0 ; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -324,7 +324,7 @@ define half @flh_stack(half %a) nounwind { ; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fmv.s fs0, fa0 ; RV32IZFHMIN-NEXT: addi a0, sp, 4 -; RV32IZFHMIN-NEXT: call notdead@plt +; RV32IZFHMIN-NEXT: call notdead ; RV32IZFHMIN-NEXT: flh fa5, 4(sp) ; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fs0 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 @@ -342,7 +342,7 @@ define half @flh_stack(half %a) nounwind { ; RV64IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IZFHMIN-NEXT: fmv.s fs0, fa0 ; RV64IZFHMIN-NEXT: mv a0, sp -; RV64IZFHMIN-NEXT: call notdead@plt +; RV64IZFHMIN-NEXT: call notdead ; RV64IZFHMIN-NEXT: flh fa5, 0(sp) ; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fs0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 @@ -360,7 +360,7 @@ define half @flh_stack(half %a) nounwind { ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: mv s0, a0 ; RV32IZHINXMIN-NEXT: addi a0, sp, 4 -; RV32IZHINXMIN-NEXT: call notdead@plt +; RV32IZHINXMIN-NEXT: call notdead ; RV32IZHINXMIN-NEXT: lh a0, 4(sp) ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, s0 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 @@ -378,7 +378,7 @@ define half @flh_stack(half %a) nounwind { ; RV64IZHINXMIN-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: mv s0, a0 ; RV64IZHINXMIN-NEXT: addi a0, sp, 12 -; RV64IZHINXMIN-NEXT: call notdead@plt +; RV64IZHINXMIN-NEXT: call notdead ; RV64IZHINXMIN-NEXT: lh a0, 12(sp) ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, s0 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 @@ -403,7 +403,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV32IZFH-NEXT: fadd.h fa5, fa0, fa1 ; RV32IZFH-NEXT: fsh fa5, 8(sp) ; RV32IZFH-NEXT: addi a0, sp, 8 -; RV32IZFH-NEXT: call notdead@plt +; RV32IZFH-NEXT: call notdead ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -415,7 +415,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV64IZFH-NEXT: fadd.h fa5, fa0, fa1 ; RV64IZFH-NEXT: fsh fa5, 4(sp) ; RV64IZFH-NEXT: addi a0, sp, 4 -; RV64IZFH-NEXT: call notdead@plt +; RV64IZFH-NEXT: call notdead ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret @@ -427,7 +427,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV32IZHINX-NEXT: fadd.h a0, a0, a1 ; RV32IZHINX-NEXT: sh a0, 8(sp) ; RV32IZHINX-NEXT: addi a0, sp, 8 -; RV32IZHINX-NEXT: call notdead@plt +; RV32IZHINX-NEXT: call notdead ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -439,7 +439,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV64IZHINX-NEXT: fadd.h a0, a0, a1 ; RV64IZHINX-NEXT: sh a0, 4(sp) ; RV64IZHINX-NEXT: addi a0, sp, 4 -; RV64IZHINX-NEXT: call notdead@plt +; RV64IZHINX-NEXT: call notdead ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 ; RV64IZHINX-NEXT: ret @@ -454,7 +454,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fsh fa5, 8(sp) ; RV32IZFHMIN-NEXT: addi a0, sp, 8 -; RV32IZFHMIN-NEXT: call notdead@plt +; RV32IZFHMIN-NEXT: call notdead ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -469,7 +469,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV64IZFHMIN-NEXT: fsh fa5, 4(sp) ; RV64IZFHMIN-NEXT: addi a0, sp, 4 -; RV64IZFHMIN-NEXT: call notdead@plt +; RV64IZFHMIN-NEXT: call notdead ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 ; RV64IZFHMIN-NEXT: ret @@ -484,7 +484,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: sh a0, 8(sp) ; RV32IZHINXMIN-NEXT: addi a0, sp, 8 -; RV32IZHINXMIN-NEXT: call notdead@plt +; RV32IZHINXMIN-NEXT: call notdead ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -499,7 +499,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-NEXT: sh a0, 4(sp) ; RV64IZHINXMIN-NEXT: addi a0, sp, 4 -; RV64IZHINXMIN-NEXT: call notdead@plt +; RV64IZHINXMIN-NEXT: call notdead ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-NEXT: addi sp, sp, 16 ; RV64IZHINXMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll index 962ed8393b72..3f385909b0b5 100644 --- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll @@ -114,7 +114,7 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixsfdi@plt +; RV32IZFH-NEXT: call __fixsfdi ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB1_4 @@ -173,7 +173,7 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s s1, a0, s0 ; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixsfdi@plt +; RV32IZHINX-NEXT: call __fixsfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 @@ -243,7 +243,7 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixsfdi@plt +; RV32IZFHMIN-NEXT: call __fixsfdi ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4 @@ -316,7 +316,7 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 ; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixsfdi@plt +; RV32IZHINXMIN-NEXT: call __fixsfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 @@ -529,7 +529,7 @@ define i64 @test_floor_ui64(half %x) nounwind { ; RV32IZFH-NEXT: fle.s a0, fa5, fs0 ; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: call __fixunssfdi ; RV32IZFH-NEXT: lui a2, %hi(.LCPI3_1) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI3_1)(a2) ; RV32IZFH-NEXT: and a0, s0, a0 @@ -573,7 +573,7 @@ define i64 @test_floor_ui64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s a0, zero, s0 ; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixunssfdi@plt +; RV32IZHINX-NEXT: call __fixunssfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI3_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI3_1)(a2) ; RV32IZHINX-NEXT: and a0, s1, a0 @@ -630,7 +630,7 @@ define i64 @test_floor_ui64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 ; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: call __fixunssfdi ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a2) ; RV32IZFHMIN-NEXT: and a0, s0, a0 @@ -688,7 +688,7 @@ define i64 @test_floor_ui64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 ; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunssfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI3_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s1, a0 @@ -826,7 +826,7 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixsfdi@plt +; RV32IZFH-NEXT: call __fixsfdi ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB5_4 @@ -885,7 +885,7 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s s1, a0, s0 ; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixsfdi@plt +; RV32IZHINX-NEXT: call __fixsfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI5_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI5_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 @@ -955,7 +955,7 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixsfdi@plt +; RV32IZFHMIN-NEXT: call __fixsfdi ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4 @@ -1028,7 +1028,7 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 ; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixsfdi@plt +; RV32IZHINXMIN-NEXT: call __fixsfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 @@ -1241,7 +1241,7 @@ define i64 @test_ceil_ui64(half %x) nounwind { ; RV32IZFH-NEXT: fle.s a0, fa5, fs0 ; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: call __fixunssfdi ; RV32IZFH-NEXT: lui a2, %hi(.LCPI7_1) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI7_1)(a2) ; RV32IZFH-NEXT: and a0, s0, a0 @@ -1285,7 +1285,7 @@ define i64 @test_ceil_ui64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s a0, zero, s0 ; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixunssfdi@plt +; RV32IZHINX-NEXT: call __fixunssfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI7_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI7_1)(a2) ; RV32IZHINX-NEXT: and a0, s1, a0 @@ -1342,7 +1342,7 @@ define i64 @test_ceil_ui64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 ; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: call __fixunssfdi ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI7_0)(a2) ; RV32IZFHMIN-NEXT: and a0, s0, a0 @@ -1400,7 +1400,7 @@ define i64 @test_ceil_ui64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 ; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunssfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI7_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s1, a0 @@ -1538,7 +1538,7 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixsfdi@plt +; RV32IZFH-NEXT: call __fixsfdi ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB9_4 @@ -1597,7 +1597,7 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s s1, a0, s0 ; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixsfdi@plt +; RV32IZHINX-NEXT: call __fixsfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI9_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI9_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 @@ -1667,7 +1667,7 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixsfdi@plt +; RV32IZFHMIN-NEXT: call __fixsfdi ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4 @@ -1740,7 +1740,7 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 ; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixsfdi@plt +; RV32IZHINXMIN-NEXT: call __fixsfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 @@ -1953,7 +1953,7 @@ define i64 @test_trunc_ui64(half %x) nounwind { ; RV32IZFH-NEXT: fle.s a0, fa5, fs0 ; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: call __fixunssfdi ; RV32IZFH-NEXT: lui a2, %hi(.LCPI11_1) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI11_1)(a2) ; RV32IZFH-NEXT: and a0, s0, a0 @@ -1997,7 +1997,7 @@ define i64 @test_trunc_ui64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s a0, zero, s0 ; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixunssfdi@plt +; RV32IZHINX-NEXT: call __fixunssfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI11_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI11_1)(a2) ; RV32IZHINX-NEXT: and a0, s1, a0 @@ -2054,7 +2054,7 @@ define i64 @test_trunc_ui64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 ; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: call __fixunssfdi ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI11_0)(a2) ; RV32IZFHMIN-NEXT: and a0, s0, a0 @@ -2112,7 +2112,7 @@ define i64 @test_trunc_ui64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 ; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunssfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI11_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s1, a0 @@ -2250,7 +2250,7 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixsfdi@plt +; RV32IZFH-NEXT: call __fixsfdi ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB13_4 @@ -2309,7 +2309,7 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s s1, a0, s0 ; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixsfdi@plt +; RV32IZHINX-NEXT: call __fixsfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI13_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI13_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 @@ -2379,7 +2379,7 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixsfdi@plt +; RV32IZFHMIN-NEXT: call __fixsfdi ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4 @@ -2452,7 +2452,7 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 ; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixsfdi@plt +; RV32IZHINXMIN-NEXT: call __fixsfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 @@ -2665,7 +2665,7 @@ define i64 @test_round_ui64(half %x) nounwind { ; RV32IZFH-NEXT: fle.s a0, fa5, fs0 ; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: call __fixunssfdi ; RV32IZFH-NEXT: lui a2, %hi(.LCPI15_1) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI15_1)(a2) ; RV32IZFH-NEXT: and a0, s0, a0 @@ -2709,7 +2709,7 @@ define i64 @test_round_ui64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s a0, zero, s0 ; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixunssfdi@plt +; RV32IZHINX-NEXT: call __fixunssfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI15_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI15_1)(a2) ; RV32IZHINX-NEXT: and a0, s1, a0 @@ -2766,7 +2766,7 @@ define i64 @test_round_ui64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 ; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: call __fixunssfdi ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI15_0)(a2) ; RV32IZFHMIN-NEXT: and a0, s0, a0 @@ -2824,7 +2824,7 @@ define i64 @test_round_ui64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 ; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunssfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI15_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s1, a0 @@ -2962,7 +2962,7 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixsfdi@plt +; RV32IZFH-NEXT: call __fixsfdi ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB17_4 @@ -3021,7 +3021,7 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s s1, a0, s0 ; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixsfdi@plt +; RV32IZHINX-NEXT: call __fixsfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI17_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI17_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 @@ -3091,7 +3091,7 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixsfdi@plt +; RV32IZFHMIN-NEXT: call __fixsfdi ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4 @@ -3164,7 +3164,7 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 ; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixsfdi@plt +; RV32IZHINXMIN-NEXT: call __fixsfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 @@ -3377,7 +3377,7 @@ define i64 @test_roundeven_ui64(half %x) nounwind { ; RV32IZFH-NEXT: fle.s a0, fa5, fs0 ; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: call __fixunssfdi ; RV32IZFH-NEXT: lui a2, %hi(.LCPI19_1) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI19_1)(a2) ; RV32IZFH-NEXT: and a0, s0, a0 @@ -3421,7 +3421,7 @@ define i64 @test_roundeven_ui64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s a0, zero, s0 ; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixunssfdi@plt +; RV32IZHINX-NEXT: call __fixunssfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI19_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI19_1)(a2) ; RV32IZHINX-NEXT: and a0, s1, a0 @@ -3478,7 +3478,7 @@ define i64 @test_roundeven_ui64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 ; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: call __fixunssfdi ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI19_0)(a2) ; RV32IZFHMIN-NEXT: and a0, s0, a0 @@ -3536,7 +3536,7 @@ define i64 @test_roundeven_ui64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 ; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunssfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI19_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s1, a0 @@ -3674,7 +3674,7 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixsfdi@plt +; RV32IZFH-NEXT: call __fixsfdi ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB21_4 @@ -3733,7 +3733,7 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s s1, a0, s0 ; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixsfdi@plt +; RV32IZHINX-NEXT: call __fixsfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI21_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI21_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 @@ -3803,7 +3803,7 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixsfdi@plt +; RV32IZFHMIN-NEXT: call __fixsfdi ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB21_4 @@ -3876,7 +3876,7 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 ; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixsfdi@plt +; RV32IZHINXMIN-NEXT: call __fixsfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 @@ -4089,7 +4089,7 @@ define i64 @test_rint_ui64(half %x) nounwind { ; RV32IZFH-NEXT: fle.s a0, fa5, fs0 ; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 -; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: call __fixunssfdi ; RV32IZFH-NEXT: lui a2, %hi(.LCPI23_1) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI23_1)(a2) ; RV32IZFH-NEXT: and a0, s0, a0 @@ -4133,7 +4133,7 @@ define i64 @test_rint_ui64(half %x) nounwind { ; RV32IZHINX-NEXT: fle.s a0, zero, s0 ; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 -; RV32IZHINX-NEXT: call __fixunssfdi@plt +; RV32IZHINX-NEXT: call __fixunssfdi ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI23_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI23_1)(a2) ; RV32IZHINX-NEXT: and a0, s1, a0 @@ -4190,7 +4190,7 @@ define i64 @test_rint_ui64(half %x) nounwind { ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 ; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 -; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: call __fixunssfdi ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI23_0) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI23_0)(a2) ; RV32IZFHMIN-NEXT: and a0, s0, a0 @@ -4248,7 +4248,7 @@ define i64 @test_rint_ui64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 ; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 -; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunssfdi ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI23_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s1, a0 diff --git a/llvm/test/CodeGen/RISCV/half-round-conv.ll b/llvm/test/CodeGen/RISCV/half-round-conv.ll index 84ba49684fc6..173164db5b78 100644 --- a/llvm/test/CodeGen/RISCV/half-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/half-round-conv.ll @@ -323,7 +323,7 @@ define i64 @test_floor_si64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixhfdi@plt +; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -349,7 +349,7 @@ define i64 @test_floor_si64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixhfdi@plt +; RV32IZHINX-NEXT: call __fixhfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -387,7 +387,7 @@ define i64 @test_floor_si64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixhfdi@plt +; RV32IZFHMIN-NEXT: call __fixhfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -427,7 +427,7 @@ define i64 @test_floor_si64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixhfdi@plt +; RV32IZHINXMIN-NEXT: call __fixhfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -760,7 +760,7 @@ define i64 @test_floor_ui64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixunshfdi@plt +; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -786,7 +786,7 @@ define i64 @test_floor_ui64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixunshfdi@plt +; RV32IZHINX-NEXT: call __fixunshfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -824,7 +824,7 @@ define i64 @test_floor_ui64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixunshfdi@plt +; RV32IZFHMIN-NEXT: call __fixunshfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -864,7 +864,7 @@ define i64 @test_floor_ui64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixunshfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunshfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -1197,7 +1197,7 @@ define i64 @test_ceil_si64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixhfdi@plt +; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -1223,7 +1223,7 @@ define i64 @test_ceil_si64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixhfdi@plt +; RV32IZHINX-NEXT: call __fixhfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -1261,7 +1261,7 @@ define i64 @test_ceil_si64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixhfdi@plt +; RV32IZFHMIN-NEXT: call __fixhfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -1301,7 +1301,7 @@ define i64 @test_ceil_si64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixhfdi@plt +; RV32IZHINXMIN-NEXT: call __fixhfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -1634,7 +1634,7 @@ define i64 @test_ceil_ui64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixunshfdi@plt +; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -1660,7 +1660,7 @@ define i64 @test_ceil_ui64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixunshfdi@plt +; RV32IZHINX-NEXT: call __fixunshfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -1698,7 +1698,7 @@ define i64 @test_ceil_ui64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixunshfdi@plt +; RV32IZFHMIN-NEXT: call __fixunshfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -1738,7 +1738,7 @@ define i64 @test_ceil_ui64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixunshfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunshfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -2071,7 +2071,7 @@ define i64 @test_trunc_si64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixhfdi@plt +; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -2097,7 +2097,7 @@ define i64 @test_trunc_si64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixhfdi@plt +; RV32IZHINX-NEXT: call __fixhfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -2135,7 +2135,7 @@ define i64 @test_trunc_si64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixhfdi@plt +; RV32IZFHMIN-NEXT: call __fixhfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -2175,7 +2175,7 @@ define i64 @test_trunc_si64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixhfdi@plt +; RV32IZHINXMIN-NEXT: call __fixhfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -2508,7 +2508,7 @@ define i64 @test_trunc_ui64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixunshfdi@plt +; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -2534,7 +2534,7 @@ define i64 @test_trunc_ui64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixunshfdi@plt +; RV32IZHINX-NEXT: call __fixunshfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -2572,7 +2572,7 @@ define i64 @test_trunc_ui64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixunshfdi@plt +; RV32IZFHMIN-NEXT: call __fixunshfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -2612,7 +2612,7 @@ define i64 @test_trunc_ui64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixunshfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunshfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -2945,7 +2945,7 @@ define i64 @test_round_si64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixhfdi@plt +; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -2971,7 +2971,7 @@ define i64 @test_round_si64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixhfdi@plt +; RV32IZHINX-NEXT: call __fixhfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -3009,7 +3009,7 @@ define i64 @test_round_si64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixhfdi@plt +; RV32IZFHMIN-NEXT: call __fixhfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -3049,7 +3049,7 @@ define i64 @test_round_si64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixhfdi@plt +; RV32IZHINXMIN-NEXT: call __fixhfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -3382,7 +3382,7 @@ define i64 @test_round_ui64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixunshfdi@plt +; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -3408,7 +3408,7 @@ define i64 @test_round_ui64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixunshfdi@plt +; RV32IZHINX-NEXT: call __fixunshfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -3446,7 +3446,7 @@ define i64 @test_round_ui64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixunshfdi@plt +; RV32IZFHMIN-NEXT: call __fixunshfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -3486,7 +3486,7 @@ define i64 @test_round_ui64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixunshfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunshfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -3819,7 +3819,7 @@ define i64 @test_roundeven_si64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixhfdi@plt +; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -3845,7 +3845,7 @@ define i64 @test_roundeven_si64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixhfdi@plt +; RV32IZHINX-NEXT: call __fixhfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -3883,7 +3883,7 @@ define i64 @test_roundeven_si64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixhfdi@plt +; RV32IZFHMIN-NEXT: call __fixhfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -3923,7 +3923,7 @@ define i64 @test_roundeven_si64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixhfdi@plt +; RV32IZHINXMIN-NEXT: call __fixhfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret @@ -4256,7 +4256,7 @@ define i64 @test_roundeven_ui64(half %x) { ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: .cfi_offset ra, -4 -; RV32IZFH-NEXT: call __fixunshfdi@plt +; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -4282,7 +4282,7 @@ define i64 @test_roundeven_ui64(half %x) { ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: .cfi_offset ra, -4 -; RV32IZHINX-NEXT: call __fixunshfdi@plt +; RV32IZHINX-NEXT: call __fixunshfdi ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -4320,7 +4320,7 @@ define i64 @test_roundeven_ui64(half %x) { ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; RV32IZFHMIN-NEXT: call __fixunshfdi@plt +; RV32IZFHMIN-NEXT: call __fixunshfdi ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -4360,7 +4360,7 @@ define i64 @test_roundeven_ui64(half %x) { ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; RV32IZHINXMIN-NEXT: call __fixunshfdi@plt +; RV32IZHINXMIN-NEXT: call __fixunshfdi ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll index 55c30046366d..5f9866f08c82 100644 --- a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll +++ b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll @@ -149,7 +149,7 @@ define dso_local i32 @load_half() nounwind { ; RV32-NEXT: .LBB8_2: # %if.then ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-NEXT: call abort@plt +; RV32-NEXT: call abort ; ; RV64-LABEL: load_half: ; RV64: # %bb.0: # %entry @@ -163,7 +163,7 @@ define dso_local i32 @load_half() nounwind { ; RV64-NEXT: .LBB8_2: # %if.then ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-NEXT: call abort@plt +; RV64-NEXT: call abort entry: %0 = load i16, ptr getelementptr inbounds ([6 x i16], ptr @foo, i32 0, i32 4), align 2 %cmp = icmp eq i16 %0, 140 diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll index 0ead223d87ca..0c9528f291c8 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll @@ -18,14 +18,14 @@ define dso_local void @handler() nounwind { ; CHECK-RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; CHECK-RV32-NEXT: lui a0, 2 ; CHECK-RV32-NEXT: addi a0, a0, 4 -; CHECK-RV32-NEXT: call read@plt +; CHECK-RV32-NEXT: call read ; CHECK-RV32-NEXT: mv s0, a0 -; CHECK-RV32-NEXT: call callee@plt +; CHECK-RV32-NEXT: call callee ; CHECK-RV32-NEXT: mv a0, s0 ; CHECK-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; CHECK-RV32-NEXT: addi sp, sp, 16 -; CHECK-RV32-NEXT: tail write@plt +; CHECK-RV32-NEXT: tail write ; ; CHECK-RV32-F-LABEL: handler: ; CHECK-RV32-F: # %bb.0: # %entry @@ -34,14 +34,14 @@ define dso_local void @handler() nounwind { ; CHECK-RV32-F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: lui a0, 2 ; CHECK-RV32-F-NEXT: addi a0, a0, 4 -; CHECK-RV32-F-NEXT: call read@plt +; CHECK-RV32-F-NEXT: call read ; CHECK-RV32-F-NEXT: mv s0, a0 -; CHECK-RV32-F-NEXT: call callee@plt +; CHECK-RV32-F-NEXT: call callee ; CHECK-RV32-F-NEXT: mv a0, s0 ; CHECK-RV32-F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: addi sp, sp, 16 -; CHECK-RV32-F-NEXT: tail write@plt +; CHECK-RV32-F-NEXT: tail write ; ; CHECK-RV32-FD-LABEL: handler: ; CHECK-RV32-FD: # %bb.0: # %entry @@ -50,14 +50,14 @@ define dso_local void @handler() nounwind { ; CHECK-RV32-FD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; CHECK-RV32-FD-NEXT: lui a0, 2 ; CHECK-RV32-FD-NEXT: addi a0, a0, 4 -; CHECK-RV32-FD-NEXT: call read@plt +; CHECK-RV32-FD-NEXT: call read ; CHECK-RV32-FD-NEXT: mv s0, a0 -; CHECK-RV32-FD-NEXT: call callee@plt +; CHECK-RV32-FD-NEXT: call callee ; CHECK-RV32-FD-NEXT: mv a0, s0 ; CHECK-RV32-FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-RV32-FD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; CHECK-RV32-FD-NEXT: addi sp, sp, 16 -; CHECK-RV32-FD-NEXT: tail write@plt +; CHECK-RV32-FD-NEXT: tail write entry: %call = tail call i32 @read(i32 8196) tail call void @callee() diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll index 7d80c34eabcb..263743d39a8e 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll @@ -185,7 +185,7 @@ define void @foo_float() nounwind #0 { ; CHECK-RV32-NEXT: lw a0, %lo(e)(a0) ; CHECK-RV32-NEXT: lui a1, %hi(f) ; CHECK-RV32-NEXT: lw a1, %lo(f)(a1) -; CHECK-RV32-NEXT: call __addsf3@plt +; CHECK-RV32-NEXT: call __addsf3 ; CHECK-RV32-NEXT: lui a1, %hi(d) ; CHECK-RV32-NEXT: sw a0, %lo(d)(a1) ; CHECK-RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload @@ -280,7 +280,7 @@ define void @foo_fp_float() nounwind #1 { ; CHECK-RV32-NEXT: lw a0, %lo(e)(a0) ; CHECK-RV32-NEXT: lui a1, %hi(f) ; CHECK-RV32-NEXT: lw a1, %lo(f)(a1) -; CHECK-RV32-NEXT: call __addsf3@plt +; CHECK-RV32-NEXT: call __addsf3 ; CHECK-RV32-NEXT: lui a1, %hi(d) ; CHECK-RV32-NEXT: sw a0, %lo(d)(a1) ; CHECK-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload @@ -387,7 +387,7 @@ define void @foo_double() nounwind #0 { ; CHECK-RV32-NEXT: lui a3, %hi(i) ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3) -; CHECK-RV32-NEXT: call __adddf3@plt +; CHECK-RV32-NEXT: call __adddf3 ; CHECK-RV32-NEXT: lui a2, %hi(g) ; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32-NEXT: sw a0, %lo(g)(a2) @@ -467,7 +467,7 @@ define void @foo_double() nounwind #0 { ; CHECK-RV32IF-NEXT: lui a3, %hi(i) ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3) -; CHECK-RV32IF-NEXT: call __adddf3@plt +; CHECK-RV32IF-NEXT: call __adddf3 ; CHECK-RV32IF-NEXT: lui a2, %hi(g) ; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) @@ -578,7 +578,7 @@ define void @foo_fp_double() nounwind #1 { ; CHECK-RV32-NEXT: lui a3, %hi(i) ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3) -; CHECK-RV32-NEXT: call __adddf3@plt +; CHECK-RV32-NEXT: call __adddf3 ; CHECK-RV32-NEXT: lui a2, %hi(g) ; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32-NEXT: sw a0, %lo(g)(a2) @@ -661,7 +661,7 @@ define void @foo_fp_double() nounwind #1 { ; CHECK-RV32IF-NEXT: lui a3, %hi(i) ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3) -; CHECK-RV32IF-NEXT: call __adddf3@plt +; CHECK-RV32IF-NEXT: call __adddf3 ; CHECK-RV32IF-NEXT: lui a2, %hi(g) ; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr.ll b/llvm/test/CodeGen/RISCV/interrupt-attr.ll index 5b269014b8f8..5887968042cb 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr.ll @@ -63,7 +63,7 @@ define void @foo_with_call() #1 { ; CHECK-RV32-NEXT: sw t4, 8(sp) # 4-byte Folded Spill ; CHECK-RV32-NEXT: sw t5, 4(sp) # 4-byte Folded Spill ; CHECK-RV32-NEXT: sw t6, 0(sp) # 4-byte Folded Spill -; CHECK-RV32-NEXT: call otherfoo@plt +; CHECK-RV32-NEXT: call otherfoo ; CHECK-RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; CHECK-RV32-NEXT: lw t0, 56(sp) # 4-byte Folded Reload ; CHECK-RV32-NEXT: lw t1, 52(sp) # 4-byte Folded Reload @@ -134,7 +134,7 @@ define void @foo_with_call() #1 { ; CHECK-RV32-F-NEXT: fsw ft9, 8(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft10, 4(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft11, 0(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: call otherfoo@plt +; CHECK-RV32-F-NEXT: call otherfoo ; CHECK-RV32-F-NEXT: lw ra, 188(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: lw t0, 184(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: lw t1, 180(sp) # 4-byte Folded Reload @@ -237,7 +237,7 @@ define void @foo_with_call() #1 { ; CHECK-RV32-FD-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: call otherfoo@plt +; CHECK-RV32-FD-NEXT: call otherfoo ; CHECK-RV32-FD-NEXT: lw ra, 316(sp) # 4-byte Folded Reload ; CHECK-RV32-FD-NEXT: lw t0, 312(sp) # 4-byte Folded Reload ; CHECK-RV32-FD-NEXT: lw t1, 308(sp) # 4-byte Folded Reload @@ -308,7 +308,7 @@ define void @foo_with_call() #1 { ; CHECK-RV64-NEXT: sd t4, 16(sp) # 8-byte Folded Spill ; CHECK-RV64-NEXT: sd t5, 8(sp) # 8-byte Folded Spill ; CHECK-RV64-NEXT: sd t6, 0(sp) # 8-byte Folded Spill -; CHECK-RV64-NEXT: call otherfoo@plt +; CHECK-RV64-NEXT: call otherfoo ; CHECK-RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: ld t0, 112(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: ld t1, 104(sp) # 8-byte Folded Reload @@ -379,7 +379,7 @@ define void @foo_with_call() #1 { ; CHECK-RV64-F-NEXT: fsw ft9, 8(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft10, 4(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft11, 0(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: call otherfoo@plt +; CHECK-RV64-F-NEXT: call otherfoo ; CHECK-RV64-F-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; CHECK-RV64-F-NEXT: ld t0, 240(sp) # 8-byte Folded Reload ; CHECK-RV64-F-NEXT: ld t1, 232(sp) # 8-byte Folded Reload @@ -482,7 +482,7 @@ define void @foo_with_call() #1 { ; CHECK-RV64-FD-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: call otherfoo@plt +; CHECK-RV64-FD-NEXT: call otherfoo ; CHECK-RV64-FD-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: ld t0, 368(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: ld t1, 360(sp) # 8-byte Folded Reload @@ -563,7 +563,7 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV32-NEXT: sw t5, 16(sp) # 4-byte Folded Spill ; CHECK-RV32-NEXT: sw t6, 12(sp) # 4-byte Folded Spill ; CHECK-RV32-NEXT: addi s0, sp, 80 -; CHECK-RV32-NEXT: call otherfoo@plt +; CHECK-RV32-NEXT: call otherfoo ; CHECK-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload ; CHECK-RV32-NEXT: lw t0, 72(sp) # 4-byte Folded Reload ; CHECK-RV32-NEXT: lw t1, 68(sp) # 4-byte Folded Reload @@ -637,7 +637,7 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV32-F-NEXT: fsw ft10, 16(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft11, 12(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: addi s0, sp, 208 -; CHECK-RV32-F-NEXT: call otherfoo@plt +; CHECK-RV32-F-NEXT: call otherfoo ; CHECK-RV32-F-NEXT: lw ra, 204(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: lw t0, 200(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: lw t1, 196(sp) # 4-byte Folded Reload @@ -743,7 +743,7 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV32-FD-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: addi s0, sp, 336 -; CHECK-RV32-FD-NEXT: call otherfoo@plt +; CHECK-RV32-FD-NEXT: call otherfoo ; CHECK-RV32-FD-NEXT: lw ra, 332(sp) # 4-byte Folded Reload ; CHECK-RV32-FD-NEXT: lw t0, 328(sp) # 4-byte Folded Reload ; CHECK-RV32-FD-NEXT: lw t1, 324(sp) # 4-byte Folded Reload @@ -817,7 +817,7 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV64-NEXT: sd t5, 16(sp) # 8-byte Folded Spill ; CHECK-RV64-NEXT: sd t6, 8(sp) # 8-byte Folded Spill ; CHECK-RV64-NEXT: addi s0, sp, 144 -; CHECK-RV64-NEXT: call otherfoo@plt +; CHECK-RV64-NEXT: call otherfoo ; CHECK-RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: ld t0, 128(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: ld t1, 120(sp) # 8-byte Folded Reload @@ -891,7 +891,7 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV64-F-NEXT: fsw ft10, 12(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft11, 8(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: addi s0, sp, 272 -; CHECK-RV64-F-NEXT: call otherfoo@plt +; CHECK-RV64-F-NEXT: call otherfoo ; CHECK-RV64-F-NEXT: ld ra, 264(sp) # 8-byte Folded Reload ; CHECK-RV64-F-NEXT: ld t0, 256(sp) # 8-byte Folded Reload ; CHECK-RV64-F-NEXT: ld t1, 248(sp) # 8-byte Folded Reload @@ -997,7 +997,7 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV64-FD-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: addi s0, sp, 400 -; CHECK-RV64-FD-NEXT: call otherfoo@plt +; CHECK-RV64-FD-NEXT: call otherfoo ; CHECK-RV64-FD-NEXT: ld ra, 392(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: ld t0, 384(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: ld t1, 376(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll index 60f72c41e836..bafa92e06834 100644 --- a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll +++ b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll @@ -74,7 +74,7 @@ define i64 @ctz_nxv8i1_no_range( %a) { ; RV32-NEXT: li a2, 8 ; RV32-NEXT: li a1, 0 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __muldi3@plt +; RV32-NEXT: call __muldi3 ; RV32-NEXT: sw a1, 20(sp) ; RV32-NEXT: sw a0, 16(sp) ; RV32-NEXT: addi a2, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll index 043d48918e3b..541fb3774257 100644 --- a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll +++ b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll @@ -28,7 +28,7 @@ define zeroext i8 @udiv8(i8 zeroext %a, i8 zeroext %b) nounwind { ; RV32-ALL: # %bb.0: ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ALL-NEXT: call __udivsi3@plt +; RV32-ALL-NEXT: call __udivsi3 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -37,7 +37,7 @@ define zeroext i8 @udiv8(i8 zeroext %a, i8 zeroext %b) nounwind { ; RV64-ALL: # %bb.0: ; RV64-ALL-NEXT: addi sp, sp, -16 ; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-ALL-NEXT: call __udivdi3@plt +; RV64-ALL-NEXT: call __udivdi3 ; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ALL-NEXT: addi sp, sp, 16 ; RV64-ALL-NEXT: ret @@ -50,7 +50,7 @@ define signext i16 @sdiv16(i16 signext %a, i16 signext %b) nounwind { ; RV32-ALL: # %bb.0: ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ALL-NEXT: call __divsi3@plt +; RV32-ALL-NEXT: call __divsi3 ; RV32-ALL-NEXT: slli a0, a0, 16 ; RV32-ALL-NEXT: srai a0, a0, 16 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -61,7 +61,7 @@ define signext i16 @sdiv16(i16 signext %a, i16 signext %b) nounwind { ; RV64-ALL: # %bb.0: ; RV64-ALL-NEXT: addi sp, sp, -16 ; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-ALL-NEXT: call __divdi3@plt +; RV64-ALL-NEXT: call __divdi3 ; RV64-ALL-NEXT: slli a0, a0, 48 ; RV64-ALL-NEXT: srai a0, a0, 48 ; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -76,7 +76,7 @@ define signext i32 @mul32(i32 %a, i32 %b) nounwind { ; RV32-ALL: # %bb.0: ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ALL-NEXT: call __mulsi3@plt +; RV32-ALL-NEXT: call __mulsi3 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -85,7 +85,7 @@ define signext i32 @mul32(i32 %a, i32 %b) nounwind { ; RV64-ALL: # %bb.0: ; RV64-ALL-NEXT: addi sp, sp, -16 ; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-ALL-NEXT: call __muldi3@plt +; RV64-ALL-NEXT: call __muldi3 ; RV64-ALL-NEXT: sext.w a0, a0 ; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ALL-NEXT: addi sp, sp, 16 @@ -99,14 +99,14 @@ define i64 @mul64(i64 %a, i64 %b) nounwind { ; RV32-ALL: # %bb.0: ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ALL-NEXT: call __muldi3@plt +; RV32-ALL-NEXT: call __muldi3 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret ; ; RV64-ALL-LABEL: mul64: ; RV64-ALL: # %bb.0: -; RV64-ALL-NEXT: tail __muldi3@plt +; RV64-ALL-NEXT: tail __muldi3 %1 = mul i64 %a, %b ret i64 %1 } @@ -120,9 +120,9 @@ define half @sin_f16(half %a) nounwind { ; RV32IFD-ILP32D: # %bb.0: ; RV32IFD-ILP32D-NEXT: addi sp, sp, -16 ; RV32IFD-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-ILP32D-NEXT: call __extendhfsf2@plt -; RV32IFD-ILP32D-NEXT: call sinf@plt -; RV32IFD-ILP32D-NEXT: call __truncsfhf2@plt +; RV32IFD-ILP32D-NEXT: call __extendhfsf2 +; RV32IFD-ILP32D-NEXT: call sinf +; RV32IFD-ILP32D-NEXT: call __truncsfhf2 ; RV32IFD-ILP32D-NEXT: fmv.x.w a0, fa0 ; RV32IFD-ILP32D-NEXT: lui a1, 1048560 ; RV32IFD-ILP32D-NEXT: or a0, a0, a1 @@ -135,9 +135,9 @@ define half @sin_f16(half %a) nounwind { ; RV32IF-ILP32F: # %bb.0: ; RV32IF-ILP32F-NEXT: addi sp, sp, -16 ; RV32IF-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-ILP32F-NEXT: call __extendhfsf2@plt -; RV32IF-ILP32F-NEXT: call sinf@plt -; RV32IF-ILP32F-NEXT: call __truncsfhf2@plt +; RV32IF-ILP32F-NEXT: call __extendhfsf2 +; RV32IF-ILP32F-NEXT: call sinf +; RV32IF-ILP32F-NEXT: call __truncsfhf2 ; RV32IF-ILP32F-NEXT: fmv.x.w a0, fa0 ; RV32IF-ILP32F-NEXT: lui a1, 1048560 ; RV32IF-ILP32F-NEXT: or a0, a0, a1 @@ -150,9 +150,9 @@ define half @sin_f16(half %a) nounwind { ; RV32IFD-ILP32: # %bb.0: ; RV32IFD-ILP32-NEXT: addi sp, sp, -16 ; RV32IFD-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-ILP32-NEXT: call __extendhfsf2@plt -; RV32IFD-ILP32-NEXT: call sinf@plt -; RV32IFD-ILP32-NEXT: call __truncsfhf2@plt +; RV32IFD-ILP32-NEXT: call __extendhfsf2 +; RV32IFD-ILP32-NEXT: call sinf +; RV32IFD-ILP32-NEXT: call __truncsfhf2 ; RV32IFD-ILP32-NEXT: lui a1, 1048560 ; RV32IFD-ILP32-NEXT: or a0, a0, a1 ; RV32IFD-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -165,9 +165,9 @@ define half @sin_f16(half %a) nounwind { ; RV32I-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-ILP32-NEXT: slli a0, a0, 16 ; RV32I-ILP32-NEXT: srli a0, a0, 16 -; RV32I-ILP32-NEXT: call __extendhfsf2@plt -; RV32I-ILP32-NEXT: call sinf@plt -; RV32I-ILP32-NEXT: call __truncsfhf2@plt +; RV32I-ILP32-NEXT: call __extendhfsf2 +; RV32I-ILP32-NEXT: call sinf +; RV32I-ILP32-NEXT: call __truncsfhf2 ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -176,9 +176,9 @@ define half @sin_f16(half %a) nounwind { ; RV64IFD-LP64D: # %bb.0: ; RV64IFD-LP64D-NEXT: addi sp, sp, -16 ; RV64IFD-LP64D-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-LP64D-NEXT: call __extendhfsf2@plt -; RV64IFD-LP64D-NEXT: call sinf@plt -; RV64IFD-LP64D-NEXT: call __truncsfhf2@plt +; RV64IFD-LP64D-NEXT: call __extendhfsf2 +; RV64IFD-LP64D-NEXT: call sinf +; RV64IFD-LP64D-NEXT: call __truncsfhf2 ; RV64IFD-LP64D-NEXT: fmv.x.w a0, fa0 ; RV64IFD-LP64D-NEXT: lui a1, 1048560 ; RV64IFD-LP64D-NEXT: or a0, a0, a1 @@ -191,9 +191,9 @@ define half @sin_f16(half %a) nounwind { ; RV64IF-LP64F: # %bb.0: ; RV64IF-LP64F-NEXT: addi sp, sp, -16 ; RV64IF-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-LP64F-NEXT: call __extendhfsf2@plt -; RV64IF-LP64F-NEXT: call sinf@plt -; RV64IF-LP64F-NEXT: call __truncsfhf2@plt +; RV64IF-LP64F-NEXT: call __extendhfsf2 +; RV64IF-LP64F-NEXT: call sinf +; RV64IF-LP64F-NEXT: call __truncsfhf2 ; RV64IF-LP64F-NEXT: fmv.x.w a0, fa0 ; RV64IF-LP64F-NEXT: lui a1, 1048560 ; RV64IF-LP64F-NEXT: or a0, a0, a1 @@ -206,9 +206,9 @@ define half @sin_f16(half %a) nounwind { ; RV64IFD-LP64: # %bb.0: ; RV64IFD-LP64-NEXT: addi sp, sp, -16 ; RV64IFD-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-LP64-NEXT: call __extendhfsf2@plt -; RV64IFD-LP64-NEXT: call sinf@plt -; RV64IFD-LP64-NEXT: call __truncsfhf2@plt +; RV64IFD-LP64-NEXT: call __extendhfsf2 +; RV64IFD-LP64-NEXT: call sinf +; RV64IFD-LP64-NEXT: call __truncsfhf2 ; RV64IFD-LP64-NEXT: lui a1, 1048560 ; RV64IFD-LP64-NEXT: or a0, a0, a1 ; RV64IFD-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -221,9 +221,9 @@ define half @sin_f16(half %a) nounwind { ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-LP64-NEXT: slli a0, a0, 48 ; RV64I-LP64-NEXT: srli a0, a0, 48 -; RV64I-LP64-NEXT: call __extendhfsf2@plt -; RV64I-LP64-NEXT: call sinf@plt -; RV64I-LP64-NEXT: call __truncsfhf2@plt +; RV64I-LP64-NEXT: call __extendhfsf2 +; RV64I-LP64-NEXT: call sinf +; RV64I-LP64-NEXT: call __truncsfhf2 ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -238,17 +238,17 @@ declare float @llvm.sin.f32(float) define float @sin_f32(float %a) nounwind { ; F-ABI-ALL-LABEL: sin_f32: ; F-ABI-ALL: # %bb.0: -; F-ABI-ALL-NEXT: tail sinf@plt +; F-ABI-ALL-NEXT: tail sinf ; ; RV32IFD-ILP32-LABEL: sin_f32: ; RV32IFD-ILP32: # %bb.0: -; RV32IFD-ILP32-NEXT: tail sinf@plt +; RV32IFD-ILP32-NEXT: tail sinf ; ; RV32I-ILP32-LABEL: sin_f32: ; RV32I-ILP32: # %bb.0: ; RV32I-ILP32-NEXT: addi sp, sp, -16 ; RV32I-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-ILP32-NEXT: call sinf@plt +; RV32I-ILP32-NEXT: call sinf ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -257,7 +257,7 @@ define float @sin_f32(float %a) nounwind { ; RV64-LP64-ALL: # %bb.0: ; RV64-LP64-ALL-NEXT: addi sp, sp, -16 ; RV64-LP64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-LP64-ALL-NEXT: call sinf@plt +; RV64-LP64-ALL-NEXT: call sinf ; RV64-LP64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64-ALL-NEXT: addi sp, sp, 16 ; RV64-LP64-ALL-NEXT: ret @@ -270,21 +270,21 @@ declare float @llvm.powi.f32.i32(float, i32) define float @powi_f32(float %a, i32 %b) nounwind { ; RV32IFD-ILP32D-LABEL: powi_f32: ; RV32IFD-ILP32D: # %bb.0: -; RV32IFD-ILP32D-NEXT: tail __powisf2@plt +; RV32IFD-ILP32D-NEXT: tail __powisf2 ; ; RV32IF-ILP32F-LABEL: powi_f32: ; RV32IF-ILP32F: # %bb.0: -; RV32IF-ILP32F-NEXT: tail __powisf2@plt +; RV32IF-ILP32F-NEXT: tail __powisf2 ; ; RV32IFD-ILP32-LABEL: powi_f32: ; RV32IFD-ILP32: # %bb.0: -; RV32IFD-ILP32-NEXT: tail __powisf2@plt +; RV32IFD-ILP32-NEXT: tail __powisf2 ; ; RV32I-ILP32-LABEL: powi_f32: ; RV32I-ILP32: # %bb.0: ; RV32I-ILP32-NEXT: addi sp, sp, -16 ; RV32I-ILP32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-ILP32-NEXT: call __powisf2@plt +; RV32I-ILP32-NEXT: call __powisf2 ; RV32I-ILP32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-ILP32-NEXT: addi sp, sp, 16 ; RV32I-ILP32-NEXT: ret @@ -294,7 +294,7 @@ define float @powi_f32(float %a, i32 %b) nounwind { ; RV64IFD-LP64D-NEXT: addi sp, sp, -16 ; RV64IFD-LP64D-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-LP64D-NEXT: sext.w a0, a0 -; RV64IFD-LP64D-NEXT: call __powisf2@plt +; RV64IFD-LP64D-NEXT: call __powisf2 ; RV64IFD-LP64D-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-LP64D-NEXT: addi sp, sp, 16 ; RV64IFD-LP64D-NEXT: ret @@ -304,7 +304,7 @@ define float @powi_f32(float %a, i32 %b) nounwind { ; RV64IF-LP64F-NEXT: addi sp, sp, -16 ; RV64IF-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-LP64F-NEXT: sext.w a0, a0 -; RV64IF-LP64F-NEXT: call __powisf2@plt +; RV64IF-LP64F-NEXT: call __powisf2 ; RV64IF-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-LP64F-NEXT: addi sp, sp, 16 ; RV64IF-LP64F-NEXT: ret @@ -314,7 +314,7 @@ define float @powi_f32(float %a, i32 %b) nounwind { ; RV64-LP64-ALL-NEXT: addi sp, sp, -16 ; RV64-LP64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-LP64-ALL-NEXT: sext.w a1, a1 -; RV64-LP64-ALL-NEXT: call __powisf2@plt +; RV64-LP64-ALL-NEXT: call __powisf2 ; RV64-LP64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64-ALL-NEXT: addi sp, sp, 16 ; RV64-LP64-ALL-NEXT: ret @@ -329,7 +329,7 @@ define i64 @llround_f32(float %a) nounwind { ; RV32-ALL: # %bb.0: ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ALL-NEXT: call llroundf@plt +; RV32-ALL-NEXT: call llroundf ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -354,7 +354,7 @@ define i64 @llround_f32(float %a) nounwind { ; RV64I-LP64: # %bb.0: ; RV64I-LP64-NEXT: addi sp, sp, -16 ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-LP64-NEXT: call llroundf@plt +; RV64I-LP64-NEXT: call llroundf ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -369,13 +369,13 @@ declare double @llvm.sin.f64(double) define double @sin_f64(double %a) nounwind { ; D-ABI-ALL-LABEL: sin_f64: ; D-ABI-ALL: # %bb.0: -; D-ABI-ALL-NEXT: tail sin@plt +; D-ABI-ALL-NEXT: tail sin ; ; RV32IF-ILP32F-LABEL: sin_f64: ; RV32IF-ILP32F: # %bb.0: ; RV32IF-ILP32F-NEXT: addi sp, sp, -16 ; RV32IF-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-ILP32F-NEXT: call sin@plt +; RV32IF-ILP32F-NEXT: call sin ; RV32IF-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-ILP32F-NEXT: addi sp, sp, 16 ; RV32IF-ILP32F-NEXT: ret @@ -384,7 +384,7 @@ define double @sin_f64(double %a) nounwind { ; RV32-ILP32-ALL: # %bb.0: ; RV32-ILP32-ALL-NEXT: addi sp, sp, -16 ; RV32-ILP32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ILP32-ALL-NEXT: call sin@plt +; RV32-ILP32-ALL-NEXT: call sin ; RV32-ILP32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32-ALL-NEXT: addi sp, sp, 16 ; RV32-ILP32-ALL-NEXT: ret @@ -393,20 +393,20 @@ define double @sin_f64(double %a) nounwind { ; RV64IF-LP64F: # %bb.0: ; RV64IF-LP64F-NEXT: addi sp, sp, -16 ; RV64IF-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-LP64F-NEXT: call sin@plt +; RV64IF-LP64F-NEXT: call sin ; RV64IF-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-LP64F-NEXT: addi sp, sp, 16 ; RV64IF-LP64F-NEXT: ret ; ; RV64IFD-LP64-LABEL: sin_f64: ; RV64IFD-LP64: # %bb.0: -; RV64IFD-LP64-NEXT: tail sin@plt +; RV64IFD-LP64-NEXT: tail sin ; ; RV64I-LP64-LABEL: sin_f64: ; RV64I-LP64: # %bb.0: ; RV64I-LP64-NEXT: addi sp, sp, -16 ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-LP64-NEXT: call sin@plt +; RV64I-LP64-NEXT: call sin ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -419,13 +419,13 @@ declare double @llvm.powi.f64.i32(double, i32) define double @powi_f64(double %a, i32 %b) nounwind { ; RV32IFD-ILP32D-LABEL: powi_f64: ; RV32IFD-ILP32D: # %bb.0: -; RV32IFD-ILP32D-NEXT: tail __powidf2@plt +; RV32IFD-ILP32D-NEXT: tail __powidf2 ; ; RV32IF-ILP32F-LABEL: powi_f64: ; RV32IF-ILP32F: # %bb.0: ; RV32IF-ILP32F-NEXT: addi sp, sp, -16 ; RV32IF-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-ILP32F-NEXT: call __powidf2@plt +; RV32IF-ILP32F-NEXT: call __powidf2 ; RV32IF-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-ILP32F-NEXT: addi sp, sp, 16 ; RV32IF-ILP32F-NEXT: ret @@ -434,7 +434,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV32-ILP32-ALL: # %bb.0: ; RV32-ILP32-ALL-NEXT: addi sp, sp, -16 ; RV32-ILP32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ILP32-ALL-NEXT: call __powidf2@plt +; RV32-ILP32-ALL-NEXT: call __powidf2 ; RV32-ILP32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ILP32-ALL-NEXT: addi sp, sp, 16 ; RV32-ILP32-ALL-NEXT: ret @@ -444,7 +444,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV64IFD-LP64D-NEXT: addi sp, sp, -16 ; RV64IFD-LP64D-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-LP64D-NEXT: sext.w a0, a0 -; RV64IFD-LP64D-NEXT: call __powidf2@plt +; RV64IFD-LP64D-NEXT: call __powidf2 ; RV64IFD-LP64D-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-LP64D-NEXT: addi sp, sp, 16 ; RV64IFD-LP64D-NEXT: ret @@ -454,7 +454,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV64IF-LP64F-NEXT: addi sp, sp, -16 ; RV64IF-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-LP64F-NEXT: sext.w a1, a1 -; RV64IF-LP64F-NEXT: call __powidf2@plt +; RV64IF-LP64F-NEXT: call __powidf2 ; RV64IF-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-LP64F-NEXT: addi sp, sp, 16 ; RV64IF-LP64F-NEXT: ret @@ -464,7 +464,7 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; RV64-LP64-ALL-NEXT: addi sp, sp, -16 ; RV64-LP64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-LP64-ALL-NEXT: sext.w a1, a1 -; RV64-LP64-ALL-NEXT: call __powidf2@plt +; RV64-LP64-ALL-NEXT: call __powidf2 ; RV64-LP64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-LP64-ALL-NEXT: addi sp, sp, 16 ; RV64-LP64-ALL-NEXT: ret @@ -479,7 +479,7 @@ define i64 @llround_f64(double %a) nounwind { ; RV32-ALL: # %bb.0: ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-ALL-NEXT: call llround@plt +; RV32-ALL-NEXT: call llround ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -493,7 +493,7 @@ define i64 @llround_f64(double %a) nounwind { ; RV64IF-LP64F: # %bb.0: ; RV64IF-LP64F-NEXT: addi sp, sp, -16 ; RV64IF-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-LP64F-NEXT: call llround@plt +; RV64IF-LP64F-NEXT: call llround ; RV64IF-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-LP64F-NEXT: addi sp, sp, 16 ; RV64IF-LP64F-NEXT: ret @@ -508,7 +508,7 @@ define i64 @llround_f64(double %a) nounwind { ; RV64I-LP64: # %bb.0: ; RV64I-LP64-NEXT: addi sp, sp, -16 ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-LP64-NEXT: call llround@plt +; RV64I-LP64-NEXT: call llround ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 ; RV64I-LP64-NEXT: ret @@ -524,7 +524,7 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ALL-NEXT: li a1, 0 -; RV32-ALL-NEXT: call __atomic_load_1@plt +; RV32-ALL-NEXT: call __atomic_load_1 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -534,7 +534,7 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV64-ALL-NEXT: addi sp, sp, -16 ; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ALL-NEXT: li a1, 0 -; RV64-ALL-NEXT: call __atomic_load_1@plt +; RV64-ALL-NEXT: call __atomic_load_1 ; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ALL-NEXT: addi sp, sp, 16 ; RV64-ALL-NEXT: ret @@ -548,7 +548,7 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ALL-NEXT: li a2, 3 -; RV32-ALL-NEXT: call __atomic_fetch_add_2@plt +; RV32-ALL-NEXT: call __atomic_fetch_add_2 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -558,7 +558,7 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV64-ALL-NEXT: addi sp, sp, -16 ; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ALL-NEXT: li a2, 3 -; RV64-ALL-NEXT: call __atomic_fetch_add_2@plt +; RV64-ALL-NEXT: call __atomic_fetch_add_2 ; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ALL-NEXT: addi sp, sp, 16 ; RV64-ALL-NEXT: ret @@ -572,7 +572,7 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ALL-NEXT: li a2, 4 -; RV32-ALL-NEXT: call __atomic_fetch_xor_4@plt +; RV32-ALL-NEXT: call __atomic_fetch_xor_4 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -582,7 +582,7 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64-ALL-NEXT: addi sp, sp, -16 ; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ALL-NEXT: li a2, 4 -; RV64-ALL-NEXT: call __atomic_fetch_xor_4@plt +; RV64-ALL-NEXT: call __atomic_fetch_xor_4 ; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ALL-NEXT: addi sp, sp, 16 ; RV64-ALL-NEXT: ret @@ -596,7 +596,7 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32-ALL-NEXT: addi sp, sp, -16 ; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ALL-NEXT: li a3, 5 -; RV32-ALL-NEXT: call __atomic_fetch_nand_8@plt +; RV32-ALL-NEXT: call __atomic_fetch_nand_8 ; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-ALL-NEXT: addi sp, sp, 16 ; RV32-ALL-NEXT: ret @@ -606,7 +606,7 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64-ALL-NEXT: addi sp, sp, -16 ; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ALL-NEXT: li a2, 5 -; RV64-ALL-NEXT: call __atomic_fetch_nand_8@plt +; RV64-ALL-NEXT: call __atomic_fetch_nand_8 ; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-ALL-NEXT: addi sp, sp, 16 ; RV64-ALL-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/llvm.exp10.ll b/llvm/test/CodeGen/RISCV/llvm.exp10.ll index bfac15e009f0..6fde86733b07 100644 --- a/llvm/test/CodeGen/RISCV/llvm.exp10.ll +++ b/llvm/test/CodeGen/RISCV/llvm.exp10.ll @@ -29,9 +29,9 @@ define half @exp10_f16(half %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a0, fa0 ; RV32IFD-NEXT: lui a1, 1048560 ; RV32IFD-NEXT: or a0, a0, a1 @@ -46,9 +46,9 @@ define half @exp10_f16(half %x) { ; RV64IFD-NEXT: .cfi_def_cfa_offset 16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: .cfi_offset ra, -8 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: lui a1, 1048560 ; RV64IFD-NEXT: or a0, a0, a1 @@ -68,9 +68,9 @@ define <1 x half> @exp10_v1f16(<1 x half> %x) { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 ; RV32IFD-NEXT: fmv.w.x fa0, a0 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a0, fa0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 @@ -83,9 +83,9 @@ define <1 x half> @exp10_v1f16(<1 x half> %x) { ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: .cfi_offset ra, -8 ; RV64IFD-NEXT: fmv.w.x fa0, a0 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 @@ -107,14 +107,14 @@ define <2 x half> @exp10_v2f16(<2 x half> %x) { ; RV32IFD-NEXT: .cfi_offset fs0, -16 ; RV32IFD-NEXT: fmv.w.x fs0, a1 ; RV32IFD-NEXT: fmv.w.x fa0, a0 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w s0, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a1, fa0 ; RV32IFD-NEXT: mv a0, s0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -135,14 +135,14 @@ define <2 x half> @exp10_v2f16(<2 x half> %x) { ; RV64IFD-NEXT: .cfi_offset s1, -24 ; RV64IFD-NEXT: mv s0, a1 ; RV64IFD-NEXT: fmv.w.x fa0, a0 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w s1, fa0 ; RV64IFD-NEXT: fmv.w.x fa0, s0 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a1, fa0 ; RV64IFD-NEXT: mv a0, s1 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -178,24 +178,24 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) { ; RV32IFD-NEXT: fmv.w.x fs0, a2 ; RV32IFD-NEXT: fmv.w.x fs1, a3 ; RV32IFD-NEXT: fmv.w.x fa0, a1 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.s fs2, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs1 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.x.w a0, fs2 ; RV32IFD-NEXT: slli s1, a0, 16 -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a0, fa0 ; RV32IFD-NEXT: slli a0, a0, 16 ; RV32IFD-NEXT: srli a0, a0, 16 ; RV32IFD-NEXT: or s1, a0, s1 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a0, fa0 ; RV32IFD-NEXT: sh a0, 4(s0) ; RV32IFD-NEXT: sw s1, 0(s0) @@ -227,24 +227,24 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) { ; RV64IFD-NEXT: lhu a1, 8(a1) ; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: fmv.w.x fa0, a1 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.s fs0, fa0 ; RV64IFD-NEXT: fmv.w.x fa0, s2 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.x.w a0, fs0 ; RV64IFD-NEXT: slli s2, a0, 16 -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: slli a0, a0, 48 ; RV64IFD-NEXT: srli a0, a0, 48 ; RV64IFD-NEXT: or s2, a0, s2 ; RV64IFD-NEXT: fmv.w.x fa0, s1 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: sh a0, 4(s0) ; RV64IFD-NEXT: sw s2, 0(s0) @@ -291,27 +291,27 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) { ; RV32IFD-NEXT: fmv.w.x fs1, a2 ; RV32IFD-NEXT: fmv.w.x fs2, a3 ; RV32IFD-NEXT: fmv.w.x fa0, a1 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.s fs3, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs2 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.s fs2, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs1 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.s fs1, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call __extendhfsf2@plt -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call __extendhfsf2 +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.x.w s1, fs1 ; RV32IFD-NEXT: fmv.x.w s2, fs2 ; RV32IFD-NEXT: fmv.x.w s3, fs3 -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a0, fa0 ; RV32IFD-NEXT: sh a0, 6(s0) ; RV32IFD-NEXT: sh s3, 4(s0) @@ -355,27 +355,27 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) { ; RV64IFD-NEXT: lhu a1, 16(a1) ; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: fmv.w.x fa0, a1 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.s fs0, fa0 ; RV64IFD-NEXT: fmv.w.x fa0, s3 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.s fs1, fa0 ; RV64IFD-NEXT: fmv.w.x fa0, s2 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.s fs2, fa0 ; RV64IFD-NEXT: fmv.w.x fa0, s1 -; RV64IFD-NEXT: call __extendhfsf2@plt -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call __extendhfsf2 +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.x.w s1, fs2 ; RV64IFD-NEXT: fmv.x.w s2, fs1 ; RV64IFD-NEXT: fmv.x.w s3, fs0 -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: sh a0, 6(s0) ; RV64IFD-NEXT: sh s3, 4(s0) @@ -398,7 +398,7 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) { define float @exp10_f32(float %x) { ; CHECK-LABEL: exp10_f32: ; CHECK: # %bb.0: -; CHECK-NEXT: tail exp10f@plt +; CHECK-NEXT: tail exp10f %r = call float @llvm.exp10.f32(float %x) ret float %r } @@ -410,7 +410,7 @@ define <1 x float> @exp10_v1f32(<1 x float> %x) { ; RV32IFD-NEXT: .cfi_def_cfa_offset 16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: .cfi_offset ra, -4 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -421,7 +421,7 @@ define <1 x float> @exp10_v1f32(<1 x float> %x) { ; RV64IFD-NEXT: .cfi_def_cfa_offset 16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: .cfi_offset ra, -8 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -441,10 +441,10 @@ define <2 x float> @exp10_v2f32(<2 x float> %x) { ; RV32IFD-NEXT: .cfi_offset fs0, -16 ; RV32IFD-NEXT: .cfi_offset fs1, -24 ; RV32IFD-NEXT: fmv.s fs0, fa1 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.s fs1, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.s fa1, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs1 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -464,10 +464,10 @@ define <2 x float> @exp10_v2f32(<2 x float> %x) { ; RV64IFD-NEXT: .cfi_offset fs0, -16 ; RV64IFD-NEXT: .cfi_offset fs1, -24 ; RV64IFD-NEXT: fmv.s fs0, fa1 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.s fs1, fa0 ; RV64IFD-NEXT: fmv.s fa0, fs0 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.s fa1, fa0 ; RV64IFD-NEXT: fmv.s fa0, fs1 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -497,13 +497,13 @@ define <3 x float> @exp10_v3f32(<3 x float> %x) { ; RV32IFD-NEXT: fmv.s fs0, fa2 ; RV32IFD-NEXT: fmv.s fs1, fa1 ; RV32IFD-NEXT: mv s0, a0 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.s fs2, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs1 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.s fs1, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fsw fa0, 8(s0) ; RV32IFD-NEXT: fsw fs1, 4(s0) ; RV32IFD-NEXT: fsw fs2, 0(s0) @@ -533,17 +533,17 @@ define <3 x float> @exp10_v3f32(<3 x float> %x) { ; RV64IFD-NEXT: fmv.s fs1, fa0 ; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: fmv.s fa0, fa1 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: slli s1, a0, 32 ; RV64IFD-NEXT: fmv.s fa0, fs1 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: slli a0, a0, 32 ; RV64IFD-NEXT: srli a0, a0, 32 ; RV64IFD-NEXT: or s1, a0, s1 ; RV64IFD-NEXT: fmv.s fa0, fs0 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fsw fa0, 8(s0) ; RV64IFD-NEXT: sd s1, 0(s0) ; RV64IFD-NEXT: ld ra, 40(sp) # 8-byte Folded Reload @@ -578,16 +578,16 @@ define <4 x float> @exp10_v4f32(<4 x float> %x) { ; RV32IFD-NEXT: fmv.s fs1, fa2 ; RV32IFD-NEXT: fmv.s fs2, fa1 ; RV32IFD-NEXT: mv s0, a0 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.s fs3, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs2 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.s fs2, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs1 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fmv.s fs1, fa0 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call exp10f@plt +; RV32IFD-NEXT: call exp10f ; RV32IFD-NEXT: fsw fa0, 12(s0) ; RV32IFD-NEXT: fsw fs1, 8(s0) ; RV32IFD-NEXT: fsw fs2, 4(s0) @@ -621,16 +621,16 @@ define <4 x float> @exp10_v4f32(<4 x float> %x) { ; RV64IFD-NEXT: fmv.s fs1, fa2 ; RV64IFD-NEXT: fmv.s fs2, fa1 ; RV64IFD-NEXT: mv s0, a0 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.s fs3, fa0 ; RV64IFD-NEXT: fmv.s fa0, fs2 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.s fs2, fa0 ; RV64IFD-NEXT: fmv.s fa0, fs1 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fmv.s fs1, fa0 ; RV64IFD-NEXT: fmv.s fa0, fs0 -; RV64IFD-NEXT: call exp10f@plt +; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: fsw fa0, 12(s0) ; RV64IFD-NEXT: fsw fs1, 8(s0) ; RV64IFD-NEXT: fsw fs2, 4(s0) @@ -650,7 +650,7 @@ define <4 x float> @exp10_v4f32(<4 x float> %x) { define double @exp10_f64(double %x) { ; CHECK-LABEL: exp10_f64: ; CHECK: # %bb.0: -; CHECK-NEXT: tail exp10@plt +; CHECK-NEXT: tail exp10 %r = call double @llvm.exp10.f64(double %x) ret double %r } @@ -673,10 +673,10 @@ define <2 x double> @exp10_v2f64(<2 x double> %x) { ; RV32IFD-NEXT: .cfi_offset fs0, -16 ; RV32IFD-NEXT: .cfi_offset fs1, -24 ; RV32IFD-NEXT: fmv.d fs0, fa1 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs0 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fmv.d fa1, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs1 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -696,10 +696,10 @@ define <2 x double> @exp10_v2f64(<2 x double> %x) { ; RV64IFD-NEXT: .cfi_offset fs0, -16 ; RV64IFD-NEXT: .cfi_offset fs1, -24 ; RV64IFD-NEXT: fmv.d fs0, fa1 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs0 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fmv.d fa1, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs1 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -729,13 +729,13 @@ define <3 x double> @exp10_v3f64(<3 x double> %x) { ; RV32IFD-NEXT: fmv.d fs0, fa2 ; RV32IFD-NEXT: fmv.d fs1, fa1 ; RV32IFD-NEXT: mv s0, a0 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fmv.d fs2, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs1 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs0 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fsd fa0, 16(s0) ; RV32IFD-NEXT: fsd fs1, 8(s0) ; RV32IFD-NEXT: fsd fs2, 0(s0) @@ -764,13 +764,13 @@ define <3 x double> @exp10_v3f64(<3 x double> %x) { ; RV64IFD-NEXT: fmv.d fs0, fa2 ; RV64IFD-NEXT: fmv.d fs1, fa1 ; RV64IFD-NEXT: mv s0, a0 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs1 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs0 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fsd fa0, 16(s0) ; RV64IFD-NEXT: fsd fs1, 8(s0) ; RV64IFD-NEXT: fsd fs2, 0(s0) @@ -806,16 +806,16 @@ define <4 x double> @exp10_v4f64(<4 x double> %x) { ; RV32IFD-NEXT: fmv.d fs1, fa2 ; RV32IFD-NEXT: fmv.d fs2, fa1 ; RV32IFD-NEXT: mv s0, a0 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fmv.d fs3, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs2 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fmv.d fs2, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs1 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: fmv.d fa0, fs0 -; RV32IFD-NEXT: call exp10@plt +; RV32IFD-NEXT: call exp10 ; RV32IFD-NEXT: fsd fa0, 24(s0) ; RV32IFD-NEXT: fsd fs1, 16(s0) ; RV32IFD-NEXT: fsd fs2, 8(s0) @@ -849,16 +849,16 @@ define <4 x double> @exp10_v4f64(<4 x double> %x) { ; RV64IFD-NEXT: fmv.d fs1, fa2 ; RV64IFD-NEXT: fmv.d fs2, fa1 ; RV64IFD-NEXT: mv s0, a0 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fmv.d fs3, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs2 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs1 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fa0, fs0 -; RV64IFD-NEXT: call exp10@plt +; RV64IFD-NEXT: call exp10 ; RV64IFD-NEXT: fsd fa0, 24(s0) ; RV64IFD-NEXT: fsd fs1, 16(s0) ; RV64IFD-NEXT: fsd fs2, 8(s0) diff --git a/llvm/test/CodeGen/RISCV/llvm.frexp.ll b/llvm/test/CodeGen/RISCV/llvm.frexp.ll index 94b9444dfaf8..30f9dd1e5165 100644 --- a/llvm/test/CodeGen/RISCV/llvm.frexp.ll +++ b/llvm/test/CodeGen/RISCV/llvm.frexp.ll @@ -23,10 +23,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __extendhfsf2@plt +; RV32IFD-NEXT: call __extendhfsf2 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call frexpf +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a1, fa0 ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lui a2, 1048560 @@ -40,10 +40,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) nounwind { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call __extendhfsf2@plt +; RV64IFD-NEXT: call __extendhfsf2 ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call frexpf +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a1, fa0 ; RV64IFD-NEXT: ld a0, 0(sp) ; RV64IFD-NEXT: lui a2, 1048560 @@ -57,10 +57,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __extendhfsf2@plt +; RV32IZFINXZDINX-NEXT: call __extendhfsf2 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexpf@plt -; RV32IZFINXZDINX-NEXT: call __truncsfhf2@plt +; RV32IZFINXZDINX-NEXT: call frexpf +; RV32IZFINXZDINX-NEXT: call __truncsfhf2 ; RV32IZFINXZDINX-NEXT: lw a1, 8(sp) ; RV32IZFINXZDINX-NEXT: lui a2, 1048560 ; RV32IZFINXZDINX-NEXT: or a0, a0, a2 @@ -72,10 +72,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) nounwind { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call __extendhfsf2@plt +; RV64IZFINXZDINX-NEXT: call __extendhfsf2 ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexpf@plt -; RV64IZFINXZDINX-NEXT: call __truncsfhf2@plt +; RV64IZFINXZDINX-NEXT: call frexpf +; RV64IZFINXZDINX-NEXT: call __truncsfhf2 ; RV64IZFINXZDINX-NEXT: ld a1, 0(sp) ; RV64IZFINXZDINX-NEXT: lui a2, 1048560 ; RV64IZFINXZDINX-NEXT: or a0, a0, a2 @@ -89,10 +89,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: call frexpf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call frexpf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw a1, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -104,10 +104,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexpf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call frexpf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: lw a1, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -121,10 +121,10 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __extendhfsf2@plt +; RV32IFD-NEXT: call __extendhfsf2 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt -; RV32IFD-NEXT: call __truncsfhf2@plt +; RV32IFD-NEXT: call frexpf +; RV32IFD-NEXT: call __truncsfhf2 ; RV32IFD-NEXT: fmv.x.w a0, fa0 ; RV32IFD-NEXT: lui a1, 1048560 ; RV32IFD-NEXT: or a0, a0, a1 @@ -137,10 +137,10 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call __extendhfsf2@plt +; RV64IFD-NEXT: call __extendhfsf2 ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt -; RV64IFD-NEXT: call __truncsfhf2@plt +; RV64IFD-NEXT: call frexpf +; RV64IFD-NEXT: call __truncsfhf2 ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: lui a1, 1048560 ; RV64IFD-NEXT: or a0, a0, a1 @@ -153,10 +153,10 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __extendhfsf2@plt +; RV32IZFINXZDINX-NEXT: call __extendhfsf2 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexpf@plt -; RV32IZFINXZDINX-NEXT: call __truncsfhf2@plt +; RV32IZFINXZDINX-NEXT: call frexpf +; RV32IZFINXZDINX-NEXT: call __truncsfhf2 ; RV32IZFINXZDINX-NEXT: lui a1, 1048560 ; RV32IZFINXZDINX-NEXT: or a0, a0, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -167,10 +167,10 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call __extendhfsf2@plt +; RV64IZFINXZDINX-NEXT: call __extendhfsf2 ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexpf@plt -; RV64IZFINXZDINX-NEXT: call __truncsfhf2@plt +; RV64IZFINXZDINX-NEXT: call frexpf +; RV64IZFINXZDINX-NEXT: call __truncsfhf2 ; RV64IZFINXZDINX-NEXT: lui a1, 1048560 ; RV64IZFINXZDINX-NEXT: or a0, a0, a1 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -183,10 +183,10 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: call frexpf@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call frexpf +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -197,10 +197,10 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexpf@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call frexpf +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -214,9 +214,9 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: call __extendhfsf2@plt +; RV32IFD-NEXT: call __extendhfsf2 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 @@ -226,9 +226,9 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind { ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IFD-NEXT: call __extendhfsf2@plt +; RV64IFD-NEXT: call __extendhfsf2 ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: ld a0, 0(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 @@ -238,9 +238,9 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind { ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: call __extendhfsf2@plt +; RV32IZFINXZDINX-NEXT: call __extendhfsf2 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -250,9 +250,9 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind { ; RV64IZFINXZDINX: # %bb.0: ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFINXZDINX-NEXT: call __extendhfsf2@plt +; RV64IZFINXZDINX-NEXT: call __extendhfsf2 ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: ld a0, 0(sp) ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -264,9 +264,9 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -278,9 +278,9 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -314,7 +314,7 @@ define { float, i32 } @test_frexp_f32_i32(float %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 @@ -325,7 +325,7 @@ define { float, i32 } @test_frexp_f32_i32(float %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: ld a0, 0(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 @@ -336,7 +336,7 @@ define { float, i32 } @test_frexp_f32_i32(float %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: lw a1, 8(sp) ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -347,7 +347,7 @@ define { float, i32 } @test_frexp_f32_i32(float %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: ld a1, 0(sp) ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -358,7 +358,7 @@ define { float, i32 } @test_frexp_f32_i32(float %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: lw a1, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -369,7 +369,7 @@ define { float, i32 } @test_frexp_f32_i32(float %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: lw a1, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -384,7 +384,7 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -394,7 +394,7 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -404,7 +404,7 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -414,7 +414,7 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -424,7 +424,7 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -434,7 +434,7 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -449,7 +449,7 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 @@ -460,7 +460,7 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: ld a0, 0(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 @@ -471,7 +471,7 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -482,7 +482,7 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: ld a0, 0(sp) ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -493,7 +493,7 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -504,7 +504,7 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -547,19 +547,19 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV32IFD-NEXT: fmv.s fs2, fa1 ; RV32IFD-NEXT: mv s0, a0 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: fmv.s fs3, fa0 ; RV32IFD-NEXT: addi a0, sp, 12 ; RV32IFD-NEXT: fmv.s fa0, fs2 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: fmv.s fs2, fa0 ; RV32IFD-NEXT: addi a0, sp, 16 ; RV32IFD-NEXT: fmv.s fa0, fs1 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: fmv.s fs1, fa0 ; RV32IFD-NEXT: addi a0, sp, 20 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: lw a0, 20(sp) ; RV32IFD-NEXT: lw a1, 16(sp) ; RV32IFD-NEXT: lw a2, 12(sp) @@ -595,19 +595,19 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV64IFD-NEXT: fmv.s fs2, fa1 ; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: fmv.s fs3, fa0 ; RV64IFD-NEXT: addi a0, sp, 8 ; RV64IFD-NEXT: fmv.s fa0, fs2 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: fmv.s fs2, fa0 ; RV64IFD-NEXT: addi a0, sp, 16 ; RV64IFD-NEXT: fmv.s fa0, fs1 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: fmv.s fs1, fa0 ; RV64IFD-NEXT: addi a0, sp, 24 ; RV64IFD-NEXT: fmv.s fa0, fs0 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: ld a0, 24(sp) ; RV64IFD-NEXT: ld a1, 16(sp) ; RV64IFD-NEXT: ld a2, 8(sp) @@ -645,19 +645,19 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV32IZFINXZDINX-NEXT: mv s3, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 ; RV32IZFINXZDINX-NEXT: mv a0, a2 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: mv s4, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 12 ; RV32IZFINXZDINX-NEXT: mv a0, s2 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: mv s2, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 16 ; RV32IZFINXZDINX-NEXT: mv a0, s1 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: mv s1, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 20 ; RV32IZFINXZDINX-NEXT: mv a0, s0 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: lw a1, 20(sp) ; RV32IZFINXZDINX-NEXT: lw a2, 16(sp) ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp) @@ -695,19 +695,19 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV64IZFINXZDINX-NEXT: mv s3, a0 ; RV64IZFINXZDINX-NEXT: mv a1, sp ; RV64IZFINXZDINX-NEXT: mv a0, a2 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: mv s4, a0 ; RV64IZFINXZDINX-NEXT: addi a1, sp, 8 ; RV64IZFINXZDINX-NEXT: mv a0, s2 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: mv s2, a0 ; RV64IZFINXZDINX-NEXT: addi a1, sp, 16 ; RV64IZFINXZDINX-NEXT: mv a0, s1 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: mv s1, a0 ; RV64IZFINXZDINX-NEXT: addi a1, sp, 24 ; RV64IZFINXZDINX-NEXT: mv a0, s0 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: ld a1, 24(sp) ; RV64IZFINXZDINX-NEXT: ld a2, 16(sp) ; RV64IZFINXZDINX-NEXT: ld a3, 8(sp) @@ -745,19 +745,19 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: addi a1, sp, 12 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: addi a1, sp, 16 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a1, sp, 20 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: lw a1, 8(sp) ; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 16(sp) @@ -795,19 +795,19 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: addi a1, sp, 8 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: lw a1, 0(sp) ; RV64I-NEXT: lw a2, 4(sp) ; RV64I-NEXT: lw a3, 8(sp) @@ -847,19 +847,19 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV32IFD-NEXT: fmv.s fs2, fa1 ; RV32IFD-NEXT: mv s0, a0 ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: fmv.s fs3, fa0 ; RV32IFD-NEXT: addi a0, sp, 12 ; RV32IFD-NEXT: fmv.s fa0, fs2 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: fmv.s fs2, fa0 ; RV32IFD-NEXT: addi a0, sp, 16 ; RV32IFD-NEXT: fmv.s fa0, fs1 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: fmv.s fs1, fa0 ; RV32IFD-NEXT: addi a0, sp, 20 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: fsw fa0, 12(s0) ; RV32IFD-NEXT: fsw fs1, 8(s0) ; RV32IFD-NEXT: fsw fs2, 4(s0) @@ -887,19 +887,19 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV64IFD-NEXT: fmv.s fs2, fa1 ; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: fmv.s fs3, fa0 ; RV64IFD-NEXT: addi a0, sp, 8 ; RV64IFD-NEXT: fmv.s fa0, fs2 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: fmv.s fs2, fa0 ; RV64IFD-NEXT: addi a0, sp, 16 ; RV64IFD-NEXT: fmv.s fa0, fs1 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: fmv.s fs1, fa0 ; RV64IFD-NEXT: addi a0, sp, 24 ; RV64IFD-NEXT: fmv.s fa0, fs0 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: fsw fa0, 12(s0) ; RV64IFD-NEXT: fsw fs1, 8(s0) ; RV64IFD-NEXT: fsw fs2, 4(s0) @@ -929,19 +929,19 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV32IZFINXZDINX-NEXT: mv s3, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 ; RV32IZFINXZDINX-NEXT: mv a0, a2 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: mv s4, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 12 ; RV32IZFINXZDINX-NEXT: mv a0, s2 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: mv s2, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 16 ; RV32IZFINXZDINX-NEXT: mv a0, s1 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: mv s1, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 20 ; RV32IZFINXZDINX-NEXT: mv a0, s0 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: sw a0, 12(s3) ; RV32IZFINXZDINX-NEXT: sw s1, 8(s3) ; RV32IZFINXZDINX-NEXT: sw s2, 4(s3) @@ -971,19 +971,19 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV64IZFINXZDINX-NEXT: mv s3, a0 ; RV64IZFINXZDINX-NEXT: mv a1, sp ; RV64IZFINXZDINX-NEXT: mv a0, a2 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: mv s4, a0 ; RV64IZFINXZDINX-NEXT: addi a1, sp, 8 ; RV64IZFINXZDINX-NEXT: mv a0, s2 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: mv s2, a0 ; RV64IZFINXZDINX-NEXT: addi a1, sp, 16 ; RV64IZFINXZDINX-NEXT: mv a0, s1 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: mv s1, a0 ; RV64IZFINXZDINX-NEXT: addi a1, sp, 24 ; RV64IZFINXZDINX-NEXT: mv a0, s0 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: sw a0, 12(s3) ; RV64IZFINXZDINX-NEXT: sw s1, 8(s3) ; RV64IZFINXZDINX-NEXT: sw s2, 4(s3) @@ -1013,19 +1013,19 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: addi a1, sp, 12 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: addi a1, sp, 16 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a1, sp, 20 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: sw a0, 12(s3) ; RV32I-NEXT: sw s1, 8(s3) ; RV32I-NEXT: sw s2, 4(s3) @@ -1055,19 +1055,19 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: addi a1, sp, 8 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: sw a0, 12(s3) ; RV64I-NEXT: sw s1, 8(s3) ; RV64I-NEXT: sw s2, 4(s3) @@ -1099,16 +1099,16 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV32IFD-NEXT: fmv.s fs2, fa1 ; RV32IFD-NEXT: mv s0, a0 ; RV32IFD-NEXT: mv a0, sp -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: addi a0, sp, 4 ; RV32IFD-NEXT: fmv.s fa0, fs2 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: addi a0, sp, 8 ; RV32IFD-NEXT: fmv.s fa0, fs1 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: addi a0, sp, 12 ; RV32IFD-NEXT: fmv.s fa0, fs0 -; RV32IFD-NEXT: call frexpf@plt +; RV32IFD-NEXT: call frexpf ; RV32IFD-NEXT: lw a0, 12(sp) ; RV32IFD-NEXT: lw a1, 8(sp) ; RV32IFD-NEXT: lw a2, 4(sp) @@ -1138,16 +1138,16 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV64IFD-NEXT: fmv.s fs2, fa1 ; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: addi a0, sp, 8 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: addi a0, sp, 16 ; RV64IFD-NEXT: fmv.s fa0, fs2 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: addi a0, sp, 24 ; RV64IFD-NEXT: fmv.s fa0, fs1 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: addi a0, sp, 32 ; RV64IFD-NEXT: fmv.s fa0, fs0 -; RV64IFD-NEXT: call frexpf@plt +; RV64IFD-NEXT: call frexpf ; RV64IFD-NEXT: ld a0, 32(sp) ; RV64IFD-NEXT: ld a1, 24(sp) ; RV64IFD-NEXT: ld a2, 16(sp) @@ -1179,16 +1179,16 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV32IZFINXZDINX-NEXT: mv s3, a0 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 12 ; RV32IZFINXZDINX-NEXT: mv a0, a2 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: addi a1, sp, 16 ; RV32IZFINXZDINX-NEXT: mv a0, s2 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: addi a1, sp, 20 ; RV32IZFINXZDINX-NEXT: mv a0, s1 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: addi a1, sp, 24 ; RV32IZFINXZDINX-NEXT: mv a0, s0 -; RV32IZFINXZDINX-NEXT: call frexpf@plt +; RV32IZFINXZDINX-NEXT: call frexpf ; RV32IZFINXZDINX-NEXT: lw a0, 24(sp) ; RV32IZFINXZDINX-NEXT: lw a1, 20(sp) ; RV32IZFINXZDINX-NEXT: lw a2, 16(sp) @@ -1220,16 +1220,16 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV64IZFINXZDINX-NEXT: mv s3, a0 ; RV64IZFINXZDINX-NEXT: addi a1, sp, 8 ; RV64IZFINXZDINX-NEXT: mv a0, a2 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: addi a1, sp, 16 ; RV64IZFINXZDINX-NEXT: mv a0, s2 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: addi a1, sp, 24 ; RV64IZFINXZDINX-NEXT: mv a0, s1 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: addi a1, sp, 32 ; RV64IZFINXZDINX-NEXT: mv a0, s0 -; RV64IZFINXZDINX-NEXT: call frexpf@plt +; RV64IZFINXZDINX-NEXT: call frexpf ; RV64IZFINXZDINX-NEXT: ld a0, 32(sp) ; RV64IZFINXZDINX-NEXT: ld a1, 24(sp) ; RV64IZFINXZDINX-NEXT: ld a2, 16(sp) @@ -1261,16 +1261,16 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: addi a1, sp, 12 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: addi a1, sp, 16 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: addi a1, sp, 20 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: addi a1, sp, 24 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call frexpf@plt +; RV32I-NEXT: call frexpf ; RV32I-NEXT: lw a0, 24(sp) ; RV32I-NEXT: lw a1, 20(sp) ; RV32I-NEXT: lw a2, 16(sp) @@ -1302,16 +1302,16 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: addi a1, sp, 8 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: addi a1, sp, 16 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: addi a1, sp, 20 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call frexpf@plt +; RV64I-NEXT: call frexpf ; RV64I-NEXT: lw a0, 20(sp) ; RV64I-NEXT: lw a1, 16(sp) ; RV64I-NEXT: lw a2, 12(sp) @@ -1338,7 +1338,7 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexp@plt +; RV32IFD-NEXT: call frexp ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 @@ -1349,7 +1349,7 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexp@plt +; RV64IFD-NEXT: call frexp ; RV64IFD-NEXT: ld a0, 0(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 @@ -1360,7 +1360,7 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: addi a2, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexp@plt +; RV32IZFINXZDINX-NEXT: call frexp ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp) ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -1371,7 +1371,7 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexp@plt +; RV64IZFINXZDINX-NEXT: call frexp ; RV64IZFINXZDINX-NEXT: ld a1, 0(sp) ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -1387,7 +1387,7 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind { ; RV32I-NEXT: addi a2, sp, 4 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a1, a3 -; RV32I-NEXT: call frexp@plt +; RV32I-NEXT: call frexp ; RV32I-NEXT: lw a2, 4(sp) ; RV32I-NEXT: sw a1, 4(s0) ; RV32I-NEXT: sw a0, 0(s0) @@ -1402,7 +1402,7 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexp@plt +; RV64I-NEXT: call frexp ; RV64I-NEXT: lw a1, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1417,7 +1417,7 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexp@plt +; RV32IFD-NEXT: call frexp ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -1427,7 +1427,7 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexp@plt +; RV64IFD-NEXT: call frexp ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1437,7 +1437,7 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: addi a2, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexp@plt +; RV32IZFINXZDINX-NEXT: call frexp ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret @@ -1447,7 +1447,7 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexp@plt +; RV64IZFINXZDINX-NEXT: call frexp ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1457,7 +1457,7 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi a2, sp, 8 -; RV32I-NEXT: call frexp@plt +; RV32I-NEXT: call frexp ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1467,7 +1467,7 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexp@plt +; RV64I-NEXT: call frexp ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1482,7 +1482,7 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: call frexp@plt +; RV32IFD-NEXT: call frexp ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 @@ -1493,7 +1493,7 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: mv a0, sp -; RV64IFD-NEXT: call frexp@plt +; RV64IFD-NEXT: call frexp ; RV64IFD-NEXT: ld a0, 0(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 @@ -1504,7 +1504,7 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: addi a2, sp, 8 -; RV32IZFINXZDINX-NEXT: call frexp@plt +; RV32IZFINXZDINX-NEXT: call frexp ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -1515,7 +1515,7 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: mv a1, sp -; RV64IZFINXZDINX-NEXT: call frexp@plt +; RV64IZFINXZDINX-NEXT: call frexp ; RV64IZFINXZDINX-NEXT: ld a0, 0(sp) ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -1526,7 +1526,7 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi a2, sp, 8 -; RV32I-NEXT: call frexp@plt +; RV32I-NEXT: call frexp ; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1537,7 +1537,7 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a1, sp, 4 -; RV64I-NEXT: call frexp@plt +; RV64I-NEXT: call frexp ; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1583,7 +1583,7 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV32IFD-NEXT: mv a1, sp ; RV32IFD-NEXT: addi a2, sp, 36 ; RV32IFD-NEXT: sw a3, 0(sp) -; RV32IFD-NEXT: call frexpl@plt +; RV32IFD-NEXT: call frexpl ; RV32IFD-NEXT: lw a0, 36(sp) ; RV32IFD-NEXT: lw a1, 28(sp) ; RV32IFD-NEXT: lw a2, 24(sp) @@ -1609,7 +1609,7 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV64IFD-NEXT: addi a2, sp, 12 ; RV64IFD-NEXT: mv a0, a1 ; RV64IFD-NEXT: mv a1, a3 -; RV64IFD-NEXT: call frexpl@plt +; RV64IFD-NEXT: call frexpl ; RV64IFD-NEXT: lw a2, 12(sp) ; RV64IFD-NEXT: sd a1, 8(s0) ; RV64IFD-NEXT: sd a0, 0(s0) @@ -1636,7 +1636,7 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV32IZFINXZDINX-NEXT: mv a1, sp ; RV32IZFINXZDINX-NEXT: addi a2, sp, 36 ; RV32IZFINXZDINX-NEXT: sw a3, 0(sp) -; RV32IZFINXZDINX-NEXT: call frexpl@plt +; RV32IZFINXZDINX-NEXT: call frexpl ; RV32IZFINXZDINX-NEXT: lw a0, 36(sp) ; RV32IZFINXZDINX-NEXT: lw a1, 28(sp) ; RV32IZFINXZDINX-NEXT: lw a2, 24(sp) @@ -1662,7 +1662,7 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi a2, sp, 12 ; RV64IZFINXZDINX-NEXT: mv a0, a1 ; RV64IZFINXZDINX-NEXT: mv a1, a3 -; RV64IZFINXZDINX-NEXT: call frexpl@plt +; RV64IZFINXZDINX-NEXT: call frexpl ; RV64IZFINXZDINX-NEXT: lw a2, 12(sp) ; RV64IZFINXZDINX-NEXT: sd a1, 8(s0) ; RV64IZFINXZDINX-NEXT: sd a0, 0(s0) @@ -1689,7 +1689,7 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: addi a2, sp, 36 ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: call frexpl@plt +; RV32I-NEXT: call frexpl ; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a1, 28(sp) ; RV32I-NEXT: lw a2, 24(sp) @@ -1715,7 +1715,7 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV64I-NEXT: addi a2, sp, 12 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a1, a3 -; RV64I-NEXT: call frexpl@plt +; RV64I-NEXT: call frexpl ; RV64I-NEXT: lw a2, 12(sp) ; RV64I-NEXT: sd a1, 8(s0) ; RV64I-NEXT: sd a0, 0(s0) @@ -1746,7 +1746,7 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV32IFD-NEXT: mv a1, sp ; RV32IFD-NEXT: addi a2, sp, 36 ; RV32IFD-NEXT: sw a3, 0(sp) -; RV32IFD-NEXT: call frexpl@plt +; RV32IFD-NEXT: call frexpl ; RV32IFD-NEXT: lw a0, 28(sp) ; RV32IFD-NEXT: lw a1, 24(sp) ; RV32IFD-NEXT: lw a2, 20(sp) @@ -1765,7 +1765,7 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: addi a2, sp, 4 -; RV64IFD-NEXT: call frexpl@plt +; RV64IFD-NEXT: call frexpl ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret @@ -1787,7 +1787,7 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV32IZFINXZDINX-NEXT: mv a1, sp ; RV32IZFINXZDINX-NEXT: addi a2, sp, 36 ; RV32IZFINXZDINX-NEXT: sw a3, 0(sp) -; RV32IZFINXZDINX-NEXT: call frexpl@plt +; RV32IZFINXZDINX-NEXT: call frexpl ; RV32IZFINXZDINX-NEXT: lw a0, 28(sp) ; RV32IZFINXZDINX-NEXT: lw a1, 24(sp) ; RV32IZFINXZDINX-NEXT: lw a2, 20(sp) @@ -1806,7 +1806,7 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: addi a2, sp, 4 -; RV64IZFINXZDINX-NEXT: call frexpl@plt +; RV64IZFINXZDINX-NEXT: call frexpl ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV64IZFINXZDINX-NEXT: ret @@ -1828,7 +1828,7 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: addi a2, sp, 36 ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: call frexpl@plt +; RV32I-NEXT: call frexpl ; RV32I-NEXT: lw a0, 28(sp) ; RV32I-NEXT: lw a1, 24(sp) ; RV32I-NEXT: lw a2, 20(sp) @@ -1847,7 +1847,7 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a2, sp, 4 -; RV64I-NEXT: call frexpl@plt +; RV64I-NEXT: call frexpl ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1872,7 +1872,7 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV32IFD-NEXT: addi a1, sp, 8 ; RV32IFD-NEXT: addi a2, sp, 40 ; RV32IFD-NEXT: sw a3, 8(sp) -; RV32IFD-NEXT: call frexpl@plt +; RV32IFD-NEXT: call frexpl ; RV32IFD-NEXT: lw a0, 40(sp) ; RV32IFD-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 48 @@ -1883,7 +1883,7 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: addi a2, sp, 4 -; RV64IFD-NEXT: call frexpl@plt +; RV64IFD-NEXT: call frexpl ; RV64IFD-NEXT: lw a0, 4(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 @@ -1904,7 +1904,7 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 ; RV32IZFINXZDINX-NEXT: addi a2, sp, 40 ; RV32IZFINXZDINX-NEXT: sw a3, 8(sp) -; RV32IZFINXZDINX-NEXT: call frexpl@plt +; RV32IZFINXZDINX-NEXT: call frexpl ; RV32IZFINXZDINX-NEXT: lw a0, 40(sp) ; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 48 @@ -1915,7 +1915,7 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: addi a2, sp, 4 -; RV64IZFINXZDINX-NEXT: call frexpl@plt +; RV64IZFINXZDINX-NEXT: call frexpl ; RV64IZFINXZDINX-NEXT: lw a0, 4(sp) ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -1936,7 +1936,7 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a2, sp, 40 ; RV32I-NEXT: sw a3, 8(sp) -; RV32I-NEXT: call frexpl@plt +; RV32I-NEXT: call frexpl ; RV32I-NEXT: lw a0, 40(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 48 @@ -1947,7 +1947,7 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addi a2, sp, 4 -; RV64I-NEXT: call frexpl@plt +; RV64I-NEXT: call frexpl ; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll b/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll index 45c582a61330..a1a6fa1f62a5 100644 --- a/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll +++ b/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll @@ -147,47 +147,47 @@ declare void @exit(i32 signext) noreturn ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call t0, OUTLINED_FUNCTION_0 -; RV64I-NEXT: call nge@plt +; RV64I-NEXT: call nge ; RV64I-NEXT: bnez a0, .LBB4_9 ; RV64I-NEXT: # %bb.1: # %if.end ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call nge@plt +; RV64I-NEXT: call nge ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: bne a0, a1, .LBB4_9 ; RV64I-NEXT: # %bb.2: # %if.end4 ; RV64I-NEXT: call t0, OUTLINED_FUNCTION_0 -; RV64I-NEXT: call ngt@plt +; RV64I-NEXT: call ngt ; RV64I-NEXT: bnez a0, .LBB4_9 ; RV64I-NEXT: # %bb.3: # %if.end8 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call ngt@plt +; RV64I-NEXT: call ngt ; RV64I-NEXT: li s1, -1 ; RV64I-NEXT: bne a0, s1, .LBB4_9 ; RV64I-NEXT: # %bb.4: # %if.end12 ; RV64I-NEXT: call t0, OUTLINED_FUNCTION_0 -; RV64I-NEXT: call nle@plt +; RV64I-NEXT: call nle ; RV64I-NEXT: bne a0, s1, .LBB4_9 ; RV64I-NEXT: # %bb.5: # %if.end16 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call nle@plt +; RV64I-NEXT: call nle ; RV64I-NEXT: bnez a0, .LBB4_9 ; RV64I-NEXT: # %bb.6: # %if.end20 ; RV64I-NEXT: call t0, OUTLINED_FUNCTION_0 -; RV64I-NEXT: call nlt@plt +; RV64I-NEXT: call nlt ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: bne a0, a1, .LBB4_9 ; RV64I-NEXT: # %bb.7: # %if.end24 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call nlt@plt +; RV64I-NEXT: call nlt ; RV64I-NEXT: bnez a0, .LBB4_9 ; RV64I-NEXT: # %bb.8: # %if.end28 -; RV64I-NEXT: call exit@plt +; RV64I-NEXT: call exit ; RV64I-NEXT: .LBB4_9: # %if.then -; RV64I-NEXT: call abort@plt +; RV64I-NEXT: call abort ; ; RV64I-LABEL: OUTLINED_FUNCTION_0: ; RV64I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll b/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll index 21254b630203..2de29fe2fa68 100644 --- a/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll +++ b/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll @@ -15,12 +15,12 @@ define i32 @func1(i32 %x) #0 { ; CHECK-NEXT: mul a0, a0, a0 ; CHECK-NEXT: addi s0, a0, 1 ; CHECK-NEXT: li a0, 4 -; CHECK-NEXT: call __cxa_allocate_exception@plt +; CHECK-NEXT: call __cxa_allocate_exception ; CHECK-NEXT: sw s0, 0(a0) ; CHECK-NEXT: lui a1, %hi(_ZTIi) ; CHECK-NEXT: addi a1, a1, %lo(_ZTIi) ; CHECK-NEXT: li a2, 0 -; CHECK-NEXT: call __cxa_throw@plt +; CHECK-NEXT: call __cxa_throw entry: %mul = mul i32 %x, %x %add = add i32 %mul, 1 @@ -42,12 +42,12 @@ define i32 @func2(i32 %x) #0 { ; CHECK-NEXT: mul a0, a0, a0 ; CHECK-NEXT: addi s0, a0, 1 ; CHECK-NEXT: li a0, 4 -; CHECK-NEXT: call __cxa_allocate_exception@plt +; CHECK-NEXT: call __cxa_allocate_exception ; CHECK-NEXT: sw s0, 0(a0) ; CHECK-NEXT: lui a1, %hi(_ZTIi) ; CHECK-NEXT: addi a1, a1, %lo(_ZTIi) ; CHECK-NEXT: li a2, 0 -; CHECK-NEXT: call __cxa_throw@plt +; CHECK-NEXT: call __cxa_throw entry: %mul = mul i32 %x, %x %add = add i32 %mul, 1 diff --git a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll index 17167e7f51b4..27297c978718 100644 --- a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll +++ b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll @@ -156,7 +156,7 @@ define void @test_la_tls_gd(i32 signext %n) nounwind { ; RV32I-NEXT: .LBB3_1: # %loop ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __tls_get_addr@plt +; RV32I-NEXT: call __tls_get_addr ; RV32I-NEXT: lw zero, 0(a0) ; RV32I-NEXT: addi s2, s2, 1 ; RV32I-NEXT: blt s2, s0, .LBB3_1 @@ -183,7 +183,7 @@ define void @test_la_tls_gd(i32 signext %n) nounwind { ; RV64I-NEXT: .LBB3_1: # %loop ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __tls_get_addr@plt +; RV64I-NEXT: call __tls_get_addr ; RV64I-NEXT: lw zero, 0(a0) ; RV64I-NEXT: addiw s2, s2, 1 ; RV64I-NEXT: blt s2, s0, .LBB3_1 diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll index 498e6cf23ba3..b45365e7a8b6 100644 --- a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll +++ b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll @@ -14,21 +14,21 @@ define void @foo(i32 signext %0, i32 signext %1) { ; NOFUSION-NEXT: lui a0, %hi(.L.str) ; NOFUSION-NEXT: fcvt.s.w fa0, a1 ; NOFUSION-NEXT: addi a0, a0, %lo(.L.str) -; NOFUSION-NEXT: tail bar@plt +; NOFUSION-NEXT: tail bar ; ; FUSION-LABEL: foo: ; FUSION: # %bb.0: ; FUSION-NEXT: fcvt.s.w fa0, a1 ; FUSION-NEXT: lui a0, %hi(.L.str) ; FUSION-NEXT: addi a0, a0, %lo(.L.str) -; FUSION-NEXT: tail bar@plt +; FUSION-NEXT: tail bar ; ; FUSION-POSTRA-LABEL: foo: ; FUSION-POSTRA: # %bb.0: ; FUSION-POSTRA-NEXT: fcvt.s.w fa0, a1 ; FUSION-POSTRA-NEXT: lui a0, %hi(.L.str) ; FUSION-POSTRA-NEXT: addi a0, a0, %lo(.L.str) -; FUSION-POSTRA-NEXT: tail bar@plt +; FUSION-POSTRA-NEXT: tail bar %3 = sitofp i32 %1 to float tail call void @bar(ptr @.str, float %3) ret void diff --git a/llvm/test/CodeGen/RISCV/mem.ll b/llvm/test/CodeGen/RISCV/mem.ll index 7c98d4ae1b3f..a9cb80cb6634 100644 --- a/llvm/test/CodeGen/RISCV/mem.ll +++ b/llvm/test/CodeGen/RISCV/mem.ll @@ -324,7 +324,7 @@ define void @addi_fold_crash(i32 %arg) nounwind { ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: sb zero, 0(a0) ; RV32I-NEXT: mv a0, a1 -; RV32I-NEXT: call snork@plt +; RV32I-NEXT: call snork ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/mem64.ll b/llvm/test/CodeGen/RISCV/mem64.ll index 09b04535498c..248964146325 100644 --- a/llvm/test/CodeGen/RISCV/mem64.ll +++ b/llvm/test/CodeGen/RISCV/mem64.ll @@ -363,7 +363,7 @@ define void @addi_fold_crash(i64 %arg) nounwind { ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: sb zero, 0(a0) ; RV64I-NEXT: mv a0, a1 -; RV64I-NEXT: call snork@plt +; RV64I-NEXT: call snork ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/memcpy.ll b/llvm/test/CodeGen/RISCV/memcpy.ll index 26ad87250919..12ec0881b20d 100644 --- a/llvm/test/CodeGen/RISCV/memcpy.ll +++ b/llvm/test/CodeGen/RISCV/memcpy.ll @@ -91,14 +91,14 @@ define void @t1(ptr nocapture %C) nounwind { ; RV32-NEXT: lui a1, %hi(.L.str1) ; RV32-NEXT: addi a1, a1, %lo(.L.str1) ; RV32-NEXT: li a2, 31 -; RV32-NEXT: tail memcpy@plt +; RV32-NEXT: tail memcpy ; ; RV64-LABEL: t1: ; RV64: # %bb.0: # %entry ; RV64-NEXT: lui a1, %hi(.L.str1) ; RV64-NEXT: addi a1, a1, %lo(.L.str1) ; RV64-NEXT: li a2, 31 -; RV64-NEXT: tail memcpy@plt +; RV64-NEXT: tail memcpy ; ; RV32-FAST-LABEL: t1: ; RV32-FAST: # %bb.0: # %entry @@ -152,14 +152,14 @@ define void @t2(ptr nocapture %C) nounwind { ; RV32-BOTH-NEXT: lui a1, %hi(.L.str2) ; RV32-BOTH-NEXT: addi a1, a1, %lo(.L.str2) ; RV32-BOTH-NEXT: li a2, 36 -; RV32-BOTH-NEXT: tail memcpy@plt +; RV32-BOTH-NEXT: tail memcpy ; ; RV64-LABEL: t2: ; RV64: # %bb.0: # %entry ; RV64-NEXT: lui a1, %hi(.L.str2) ; RV64-NEXT: addi a1, a1, %lo(.L.str2) ; RV64-NEXT: li a2, 36 -; RV64-NEXT: tail memcpy@plt +; RV64-NEXT: tail memcpy ; ; RV64-FAST-LABEL: t2: ; RV64-FAST: # %bb.0: # %entry @@ -188,14 +188,14 @@ define void @t3(ptr nocapture %C) nounwind { ; RV32-NEXT: lui a1, %hi(.L.str3) ; RV32-NEXT: addi a1, a1, %lo(.L.str3) ; RV32-NEXT: li a2, 24 -; RV32-NEXT: tail memcpy@plt +; RV32-NEXT: tail memcpy ; ; RV64-LABEL: t3: ; RV64: # %bb.0: # %entry ; RV64-NEXT: lui a1, %hi(.L.str3) ; RV64-NEXT: addi a1, a1, %lo(.L.str3) ; RV64-NEXT: li a2, 24 -; RV64-NEXT: tail memcpy@plt +; RV64-NEXT: tail memcpy ; ; RV32-FAST-LABEL: t3: ; RV32-FAST: # %bb.0: # %entry @@ -241,14 +241,14 @@ define void @t4(ptr nocapture %C) nounwind { ; RV32-NEXT: lui a1, %hi(.L.str4) ; RV32-NEXT: addi a1, a1, %lo(.L.str4) ; RV32-NEXT: li a2, 18 -; RV32-NEXT: tail memcpy@plt +; RV32-NEXT: tail memcpy ; ; RV64-LABEL: t4: ; RV64: # %bb.0: # %entry ; RV64-NEXT: lui a1, %hi(.L.str4) ; RV64-NEXT: addi a1, a1, %lo(.L.str4) ; RV64-NEXT: li a2, 18 -; RV64-NEXT: tail memcpy@plt +; RV64-NEXT: tail memcpy ; ; RV32-FAST-LABEL: t4: ; RV32-FAST: # %bb.0: # %entry @@ -353,7 +353,7 @@ define void @t6() nounwind { ; RV32-NEXT: lui a1, %hi(.L.str6) ; RV32-NEXT: addi a1, a1, %lo(.L.str6) ; RV32-NEXT: li a2, 14 -; RV32-NEXT: call memcpy@plt +; RV32-NEXT: call memcpy ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -367,7 +367,7 @@ define void @t6() nounwind { ; RV64-NEXT: lui a1, %hi(.L.str6) ; RV64-NEXT: addi a1, a1, %lo(.L.str6) ; RV64-NEXT: li a2, 14 -; RV64-NEXT: call memcpy@plt +; RV64-NEXT: call memcpy ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll b/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll index b7c0a9f29273..45db5078f150 100644 --- a/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll +++ b/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll @@ -34,7 +34,7 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a6, 0 ; CHECK-NEXT: li a7, 0 -; CHECK-NEXT: call _Z3fooiiiiiiiiiiPi@plt +; CHECK-NEXT: call _Z3fooiiiiiiiiiiPi ; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: # %bb.1: # %try.cont.unreachable @@ -44,9 +44,9 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: li a2, 1 ; CHECK-NEXT: bne a1, a2, .LBB0_4 ; CHECK-NEXT: # %bb.3: # %catch -; CHECK-NEXT: call __cxa_begin_catch@plt +; CHECK-NEXT: call __cxa_begin_catch ; CHECK-NEXT: lw s1, 0(a0) -; CHECK-NEXT: call __cxa_end_catch@plt +; CHECK-NEXT: call __cxa_end_catch ; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: addi sp, s0, -32 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -55,7 +55,7 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB0_4: # %ehcleanup -; CHECK-NEXT: call _Unwind_Resume@plt +; CHECK-NEXT: call _Unwind_Resume entry: invoke void @_Z3fooiiiiiiiiiiPi(i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 poison, i32 poison, i32 poison) to label %try.cont.unreachable unwind label %lpad diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll index f2b7e8d26328..af341dbaadea 100644 --- a/llvm/test/CodeGen/RISCV/mul.ll +++ b/llvm/test/CodeGen/RISCV/mul.ll @@ -14,7 +14,7 @@ define signext i32 @square(i32 %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -29,7 +29,7 @@ define signext i32 @square(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -48,7 +48,7 @@ define signext i32 @mul(i32 %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -62,7 +62,7 @@ define signext i32 @mul(i32 %a, i32 %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -133,7 +133,7 @@ define i64 @mul64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -150,7 +150,7 @@ define i64 @mul64(i64 %a, i64 %b) nounwind { ; ; RV64I-LABEL: mul64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __muldi3@plt +; RV64I-NEXT: tail __muldi3 ; ; RV64IM-LABEL: mul64: ; RV64IM: # %bb.0: @@ -208,7 +208,7 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a3, a2, 31 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -225,7 +225,7 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -343,7 +343,7 @@ define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind { ; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -358,7 +358,7 @@ define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -385,7 +385,7 @@ define i32 @mulhsu(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: srai a3, a1, 31 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -403,7 +403,7 @@ define i32 @mulhsu(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -751,7 +751,7 @@ define i32 @muli32_p384(i32 %a) nounwind { ; RV32I-LABEL: muli32_p384: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 384 -; RV32I-NEXT: tail __mulsi3@plt +; RV32I-NEXT: tail __mulsi3 ; ; RV32IM-LABEL: muli32_p384: ; RV32IM: # %bb.0: @@ -764,7 +764,7 @@ define i32 @muli32_p384(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, 384 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -782,7 +782,7 @@ define i32 @muli32_p12288(i32 %a) nounwind { ; RV32I-LABEL: muli32_p12288: ; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, 3 -; RV32I-NEXT: tail __mulsi3@plt +; RV32I-NEXT: tail __mulsi3 ; ; RV32IM-LABEL: muli32_p12288: ; RV32IM: # %bb.0: @@ -795,7 +795,7 @@ define i32 @muli32_p12288(i32 %a) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lui a1, 3 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -910,7 +910,7 @@ define i32 @muli32_m4352(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, -17 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: tail __mulsi3@plt +; RV32I-NEXT: tail __mulsi3 ; ; RV32IM-LABEL: muli32_m4352: ; RV32IM: # %bb.0: @@ -925,7 +925,7 @@ define i32 @muli32_m4352(i32 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: li a1, -17 ; RV64I-NEXT: slli a1, a1, 8 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1036,7 +1036,7 @@ define i64 @muli64_m4352(i64 %a) nounwind { ; RV32I-NEXT: li a2, -17 ; RV32I-NEXT: slli a2, a2, 8 ; RV32I-NEXT: li a3, -1 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1056,7 +1056,7 @@ define i64 @muli64_m4352(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, -17 ; RV64I-NEXT: slli a1, a1, 8 -; RV64I-NEXT: tail __muldi3@plt +; RV64I-NEXT: tail __muldi3 ; ; RV64IM-LABEL: muli64_m4352: ; RV64IM: # %bb.0: @@ -1395,13 +1395,13 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: srai s4, a3, 31 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: add s5, a0, s5 ; RV32I-NEXT: sltu a0, s5, a0 ; RV32I-NEXT: add s7, a1, a0 @@ -1409,7 +1409,7 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: add s5, a0, s5 ; RV32I-NEXT: sltu a0, s5, a0 ; RV32I-NEXT: add a0, a1, a0 @@ -1418,7 +1418,7 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s6, a1 ; RV32I-NEXT: add s9, a0, s8 @@ -1426,14 +1426,14 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 -; RV32I-NEXT: call __muldi3@plt +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: add s2, a0, s2 ; RV32I-NEXT: add a2, s9, s2 ; RV32I-NEXT: sltu a3, a2, s9 @@ -1502,7 +1502,7 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind { ; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: srai a3, a1, 63 ; RV64I-NEXT: li a1, 0 -; RV64I-NEXT: call __multi3@plt +; RV64I-NEXT: call __multi3 ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/nest-register.ll b/llvm/test/CodeGen/RISCV/nest-register.ll index 97704ebae4cb..e222beee4578 100644 --- a/llvm/test/CodeGen/RISCV/nest-register.ll +++ b/llvm/test/CodeGen/RISCV/nest-register.ll @@ -17,7 +17,6 @@ define ptr @nest_receiver(ptr nest %arg) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a0, t2 ; RV64I-NEXT: ret -; ret ptr %arg } @@ -27,7 +26,7 @@ define ptr @nest_caller(ptr %arg) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv t2, a0 -; RV32I-NEXT: call nest_receiver@plt +; RV32I-NEXT: call nest_receiver ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -37,11 +36,10 @@ define ptr @nest_caller(ptr %arg) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv t2, a0 -; RV64I-NEXT: call nest_receiver@plt +; RV64I-NEXT: call nest_receiver ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret -; %result = call ptr @nest_receiver(ptr nest %arg) ret ptr %result } diff --git a/llvm/test/CodeGen/RISCV/nomerge.ll b/llvm/test/CodeGen/RISCV/nomerge.ll index f4e50b6697ae..8e77adfc16e2 100644 --- a/llvm/test/CodeGen/RISCV/nomerge.ll +++ b/llvm/test/CodeGen/RISCV/nomerge.ll @@ -13,14 +13,14 @@ define void @foo(i32 %i) nounwind { ; CHECK-NEXT: li a1, 5 ; CHECK-NEXT: bne a0, a1, .LBB0_4 ; CHECK-NEXT: # %bb.2: # %if.then -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: j .LBB0_4 ; CHECK-NEXT: .LBB0_3: # %if.then2 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: .LBB0_4: # %if.end3 ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 16 -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar entry: switch i32 %i, label %if.end3 [ i32 5, label %if.then @@ -46,9 +46,9 @@ define void @foo_tail(i1 %i) nounwind { ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: beqz a0, .LBB1_2 ; CHECK-NEXT: # %bb.1: # %if.then -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar ; CHECK-NEXT: .LBB1_2: # %if.else -; CHECK-NEXT: tail bar@plt +; CHECK-NEXT: tail bar entry: br i1 %i, label %if.then, label %if.else diff --git a/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir b/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir index ca80abc54601..19ad7b16e386 100644 --- a/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir +++ b/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir @@ -40,7 +40,7 @@ ; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: sd a0, -8(a1) ; CHECK-NEXT: ld a1, 0(sp) - ; CHECK-NEXT: call foo@plt + ; CHECK-NEXT: call foo ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: sub sp, s0, a0 ; CHECK-NEXT: addiw a0, a0, -2032 @@ -80,3 +80,5 @@ body: | PseudoRET ... +## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +# DEBUG: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll index 7c3294fa81dc..4bb65f376218 100644 --- a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll @@ -451,7 +451,7 @@ define i64 @uaddo6_xor_multi_use(i64 %a, i64 %b) { ; RV32-NEXT: .LBB10_4: ; RV32-NEXT: neg s1, a2 ; RV32-NEXT: and s1, s1, a3 -; RV32-NEXT: call use@plt +; RV32-NEXT: call use ; RV32-NEXT: mv a0, s0 ; RV32-NEXT: mv a1, s1 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -474,7 +474,7 @@ define i64 @uaddo6_xor_multi_use(i64 %a, i64 %b) { ; RV64-NEXT: # %bb.1: ; RV64-NEXT: li s0, 42 ; RV64-NEXT: .LBB10_2: -; RV64-NEXT: call use@plt +; RV64-NEXT: call use ; RV64-NEXT: mv a0, s0 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -1091,7 +1091,7 @@ define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) { ; RV32-NEXT: sltu s6, s4, s1 ; RV32-NEXT: .LBB32_4: # %t ; RV32-NEXT: mv a0, s6 -; RV32-NEXT: call call@plt +; RV32-NEXT: call call ; RV32-NEXT: beqz s6, .LBB32_8 ; RV32-NEXT: # %bb.5: # %end ; RV32-NEXT: sltu a1, s4, s1 @@ -1145,7 +1145,7 @@ define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) { ; RV64-NEXT: mv s3, a0 ; RV64-NEXT: sltu s4, a0, a1 ; RV64-NEXT: mv a0, s4 -; RV64-NEXT: call call@plt +; RV64-NEXT: call call ; RV64-NEXT: bgeu s3, s2, .LBB32_3 ; RV64-NEXT: # %bb.2: # %end ; RV64-NEXT: sub a0, s3, s2 diff --git a/llvm/test/CodeGen/RISCV/pr51206.ll b/llvm/test/CodeGen/RISCV/pr51206.ll index b83903e7c55c..f54031af0de5 100644 --- a/llvm/test/CodeGen/RISCV/pr51206.ll +++ b/llvm/test/CodeGen/RISCV/pr51206.ll @@ -31,7 +31,7 @@ define signext i32 @wobble() nounwind { ; CHECK-NEXT: # %bb.1: # %bb10 ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; CHECK-NEXT: call quux@plt +; CHECK-NEXT: call quux ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: .LBB0_2: # %bb12 diff --git a/llvm/test/CodeGen/RISCV/pr63816.ll b/llvm/test/CodeGen/RISCV/pr63816.ll index 6eaec08abb90..2e33a0e99499 100644 --- a/llvm/test/CodeGen/RISCV/pr63816.ll +++ b/llvm/test/CodeGen/RISCV/pr63816.ll @@ -19,31 +19,31 @@ define void @test(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: lhu a0, 12(a0) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs0, fa0 ; CHECK-NEXT: lhu a0, 10(s1) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs1, fa0 ; CHECK-NEXT: lhu a0, 8(s1) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs2, fa0 ; CHECK-NEXT: lhu a0, 6(s1) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs3, fa0 ; CHECK-NEXT: lhu a0, 4(s1) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs4, fa0 ; CHECK-NEXT: lhu a0, 2(s1) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fmv.s fs5, fa0 ; CHECK-NEXT: lhu a0, 0(s1) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fcvt.d.s fs6, fa0 ; CHECK-NEXT: fcvt.d.s fs5, fs5 ; CHECK-NEXT: fcvt.d.s fs4, fs4 @@ -53,7 +53,7 @@ define void @test(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: fcvt.d.s fs1, fs1 ; CHECK-NEXT: fmv.w.x fa0, a0 ; CHECK-NEXT: fcvt.d.s fs0, fs0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fcvt.d.s fa5, fa0 ; CHECK-NEXT: fsd fa5, 56(s0) ; CHECK-NEXT: fsd fs0, 48(s0) diff --git a/llvm/test/CodeGen/RISCV/push-pop-popret.ll b/llvm/test/CodeGen/RISCV/push-pop-popret.ll index 9ff4235746ca..945e7b46f8c9 100644 --- a/llvm/test/CodeGen/RISCV/push-pop-popret.ll +++ b/llvm/test/CodeGen/RISCV/push-pop-popret.ll @@ -24,7 +24,7 @@ define i32 @foo() { ; RV32IZCMP-NEXT: .cfi_def_cfa_offset 528 ; RV32IZCMP-NEXT: .cfi_offset ra, -4 ; RV32IZCMP-NEXT: mv a0, sp -; RV32IZCMP-NEXT: call test@plt +; RV32IZCMP-NEXT: call test ; RV32IZCMP-NEXT: addi sp, sp, 464 ; RV32IZCMP-NEXT: cm.popretz {ra}, 64 ; @@ -35,7 +35,7 @@ define i32 @foo() { ; RV64IZCMP-NEXT: .cfi_def_cfa_offset 528 ; RV64IZCMP-NEXT: .cfi_offset ra, -8 ; RV64IZCMP-NEXT: mv a0, sp -; RV64IZCMP-NEXT: call test@plt +; RV64IZCMP-NEXT: call test ; RV64IZCMP-NEXT: addi sp, sp, 464 ; RV64IZCMP-NEXT: cm.popretz {ra}, 64 ; @@ -46,7 +46,7 @@ define i32 @foo() { ; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 528 ; RV32IZCMP-SR-NEXT: .cfi_offset ra, -4 ; RV32IZCMP-SR-NEXT: mv a0, sp -; RV32IZCMP-SR-NEXT: call test@plt +; RV32IZCMP-SR-NEXT: call test ; RV32IZCMP-SR-NEXT: addi sp, sp, 464 ; RV32IZCMP-SR-NEXT: cm.popretz {ra}, 64 ; @@ -57,7 +57,7 @@ define i32 @foo() { ; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 528 ; RV64IZCMP-SR-NEXT: .cfi_offset ra, -8 ; RV64IZCMP-SR-NEXT: mv a0, sp -; RV64IZCMP-SR-NEXT: call test@plt +; RV64IZCMP-SR-NEXT: call test ; RV64IZCMP-SR-NEXT: addi sp, sp, 464 ; RV64IZCMP-SR-NEXT: cm.popretz {ra}, 64 ; @@ -68,7 +68,7 @@ define i32 @foo() { ; RV32I-NEXT: sw ra, 524(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: addi a0, sp, 12 -; RV32I-NEXT: call test@plt +; RV32I-NEXT: call test ; RV32I-NEXT: li a0, 0 ; RV32I-NEXT: lw ra, 524(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 528 @@ -81,7 +81,7 @@ define i32 @foo() { ; RV64I-NEXT: sd ra, 520(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: addi a0, sp, 8 -; RV64I-NEXT: call test@plt +; RV64I-NEXT: call test ; RV64I-NEXT: li a0, 0 ; RV64I-NEXT: ld ra, 520(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 528 @@ -105,7 +105,7 @@ define i32 @pushpopret0(i32 signext %size){ ; RV32IZCMP-NEXT: andi a0, a0, -16 ; RV32IZCMP-NEXT: sub a0, sp, a0 ; RV32IZCMP-NEXT: mv sp, a0 -; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: call callee_void ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: cm.popretz {ra, s0}, 16 ; @@ -123,7 +123,7 @@ define i32 @pushpopret0(i32 signext %size){ ; RV64IZCMP-NEXT: andi a0, a0, -16 ; RV64IZCMP-NEXT: sub a0, sp, a0 ; RV64IZCMP-NEXT: mv sp, a0 -; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: call callee_void ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: cm.popretz {ra, s0}, 16 ; @@ -139,7 +139,7 @@ define i32 @pushpopret0(i32 signext %size){ ; RV32IZCMP-SR-NEXT: andi a0, a0, -16 ; RV32IZCMP-SR-NEXT: sub a0, sp, a0 ; RV32IZCMP-SR-NEXT: mv sp, a0 -; RV32IZCMP-SR-NEXT: call callee_void@plt +; RV32IZCMP-SR-NEXT: call callee_void ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: cm.popretz {ra, s0}, 16 ; @@ -157,7 +157,7 @@ define i32 @pushpopret0(i32 signext %size){ ; RV64IZCMP-SR-NEXT: andi a0, a0, -16 ; RV64IZCMP-SR-NEXT: sub a0, sp, a0 ; RV64IZCMP-SR-NEXT: mv sp, a0 -; RV64IZCMP-SR-NEXT: call callee_void@plt +; RV64IZCMP-SR-NEXT: call callee_void ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: cm.popretz {ra, s0}, 16 ; @@ -175,7 +175,7 @@ define i32 @pushpopret0(i32 signext %size){ ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: call callee_void ; RV32I-NEXT: li a0, 0 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -199,7 +199,7 @@ define i32 @pushpopret0(i32 signext %size){ ; RV64I-NEXT: andi a0, a0, -16 ; RV64I-NEXT: sub a0, sp, a0 ; RV64I-NEXT: mv sp, a0 -; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: call callee_void ; RV64I-NEXT: li a0, 0 ; RV64I-NEXT: addi sp, s0, -16 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -225,7 +225,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV32IZCMP-NEXT: andi a0, a0, -16 ; RV32IZCMP-NEXT: sub a0, sp, a0 ; RV32IZCMP-NEXT: mv sp, a0 -; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: call callee_void ; RV32IZCMP-NEXT: li a0, 1 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: cm.popret {ra, s0}, 16 @@ -244,7 +244,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV64IZCMP-NEXT: andi a0, a0, -16 ; RV64IZCMP-NEXT: sub a0, sp, a0 ; RV64IZCMP-NEXT: mv sp, a0 -; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: call callee_void ; RV64IZCMP-NEXT: li a0, 1 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: cm.popret {ra, s0}, 16 @@ -261,7 +261,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV32IZCMP-SR-NEXT: andi a0, a0, -16 ; RV32IZCMP-SR-NEXT: sub a0, sp, a0 ; RV32IZCMP-SR-NEXT: mv sp, a0 -; RV32IZCMP-SR-NEXT: call callee_void@plt +; RV32IZCMP-SR-NEXT: call callee_void ; RV32IZCMP-SR-NEXT: li a0, 1 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 @@ -280,7 +280,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV64IZCMP-SR-NEXT: andi a0, a0, -16 ; RV64IZCMP-SR-NEXT: sub a0, sp, a0 ; RV64IZCMP-SR-NEXT: mv sp, a0 -; RV64IZCMP-SR-NEXT: call callee_void@plt +; RV64IZCMP-SR-NEXT: call callee_void ; RV64IZCMP-SR-NEXT: li a0, 1 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 @@ -299,7 +299,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: call callee_void ; RV32I-NEXT: li a0, 1 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -323,7 +323,7 @@ define i32 @pushpopret1(i32 signext %size) { ; RV64I-NEXT: andi a0, a0, -16 ; RV64I-NEXT: sub a0, sp, a0 ; RV64I-NEXT: mv sp, a0 -; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: call callee_void ; RV64I-NEXT: li a0, 1 ; RV64I-NEXT: addi sp, s0, -16 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -349,7 +349,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV32IZCMP-NEXT: andi a0, a0, -16 ; RV32IZCMP-NEXT: sub a0, sp, a0 ; RV32IZCMP-NEXT: mv sp, a0 -; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: call callee_void ; RV32IZCMP-NEXT: li a0, -1 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: cm.popret {ra, s0}, 16 @@ -368,7 +368,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV64IZCMP-NEXT: andi a0, a0, -16 ; RV64IZCMP-NEXT: sub a0, sp, a0 ; RV64IZCMP-NEXT: mv sp, a0 -; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: call callee_void ; RV64IZCMP-NEXT: li a0, -1 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: cm.popret {ra, s0}, 16 @@ -385,7 +385,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV32IZCMP-SR-NEXT: andi a0, a0, -16 ; RV32IZCMP-SR-NEXT: sub a0, sp, a0 ; RV32IZCMP-SR-NEXT: mv sp, a0 -; RV32IZCMP-SR-NEXT: call callee_void@plt +; RV32IZCMP-SR-NEXT: call callee_void ; RV32IZCMP-SR-NEXT: li a0, -1 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 @@ -404,7 +404,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV64IZCMP-SR-NEXT: andi a0, a0, -16 ; RV64IZCMP-SR-NEXT: sub a0, sp, a0 ; RV64IZCMP-SR-NEXT: mv sp, a0 -; RV64IZCMP-SR-NEXT: call callee_void@plt +; RV64IZCMP-SR-NEXT: call callee_void ; RV64IZCMP-SR-NEXT: li a0, -1 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 @@ -423,7 +423,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: call callee_void ; RV32I-NEXT: li a0, -1 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -447,7 +447,7 @@ define i32 @pushpopretneg1(i32 signext %size) { ; RV64I-NEXT: andi a0, a0, -16 ; RV64I-NEXT: sub a0, sp, a0 ; RV64I-NEXT: mv sp, a0 -; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: call callee_void ; RV64I-NEXT: li a0, -1 ; RV64I-NEXT: addi sp, s0, -16 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -473,7 +473,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV32IZCMP-NEXT: andi a0, a0, -16 ; RV32IZCMP-NEXT: sub a0, sp, a0 ; RV32IZCMP-NEXT: mv sp, a0 -; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: call callee_void ; RV32IZCMP-NEXT: li a0, 2 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: cm.popret {ra, s0}, 16 @@ -492,7 +492,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV64IZCMP-NEXT: andi a0, a0, -16 ; RV64IZCMP-NEXT: sub a0, sp, a0 ; RV64IZCMP-NEXT: mv sp, a0 -; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: call callee_void ; RV64IZCMP-NEXT: li a0, 2 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: cm.popret {ra, s0}, 16 @@ -509,7 +509,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV32IZCMP-SR-NEXT: andi a0, a0, -16 ; RV32IZCMP-SR-NEXT: sub a0, sp, a0 ; RV32IZCMP-SR-NEXT: mv sp, a0 -; RV32IZCMP-SR-NEXT: call callee_void@plt +; RV32IZCMP-SR-NEXT: call callee_void ; RV32IZCMP-SR-NEXT: li a0, 2 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 @@ -528,7 +528,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV64IZCMP-SR-NEXT: andi a0, a0, -16 ; RV64IZCMP-SR-NEXT: sub a0, sp, a0 ; RV64IZCMP-SR-NEXT: mv sp, a0 -; RV64IZCMP-SR-NEXT: call callee_void@plt +; RV64IZCMP-SR-NEXT: call callee_void ; RV64IZCMP-SR-NEXT: li a0, 2 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: cm.popret {ra, s0}, 16 @@ -547,7 +547,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: call callee_void ; RV32I-NEXT: li a0, 2 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -571,7 +571,7 @@ define i32 @pushpopret2(i32 signext %size) { ; RV64I-NEXT: andi a0, a0, -16 ; RV64I-NEXT: sub a0, sp, a0 ; RV64I-NEXT: mv sp, a0 -; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: call callee_void ; RV64I-NEXT: li a0, 2 ; RV64I-NEXT: addi sp, s0, -16 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -599,7 +599,7 @@ define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 { ; RV32IZCMP-NEXT: mv sp, a0 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-NEXT: tail callee@plt +; RV32IZCMP-NEXT: tail callee ; ; RV64IZCMP-LABEL: tailcall: ; RV64IZCMP: # %bb.0: # %entry @@ -617,7 +617,7 @@ define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 { ; RV64IZCMP-NEXT: mv sp, a0 ; RV64IZCMP-NEXT: addi sp, s0, -16 ; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-NEXT: tail callee@plt +; RV64IZCMP-NEXT: tail callee ; ; RV32IZCMP-SR-LABEL: tailcall: ; RV32IZCMP-SR: # %bb.0: # %entry @@ -633,7 +633,7 @@ define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 { ; RV32IZCMP-SR-NEXT: mv sp, a0 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV32IZCMP-SR-NEXT: tail callee@plt +; RV32IZCMP-SR-NEXT: tail callee ; ; RV64IZCMP-SR-LABEL: tailcall: ; RV64IZCMP-SR: # %bb.0: # %entry @@ -651,7 +651,7 @@ define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 { ; RV64IZCMP-SR-NEXT: mv sp, a0 ; RV64IZCMP-SR-NEXT: addi sp, s0, -16 ; RV64IZCMP-SR-NEXT: cm.pop {ra, s0}, 16 -; RV64IZCMP-SR-NEXT: tail callee@plt +; RV64IZCMP-SR-NEXT: tail callee ; ; RV32I-LABEL: tailcall: ; RV32I: # %bb.0: # %entry @@ -671,7 +671,7 @@ define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 { ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: tail callee@plt +; RV32I-NEXT: tail callee ; ; RV64I-LABEL: tailcall: ; RV64I: # %bb.0: # %entry @@ -693,7 +693,7 @@ define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 { ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: tail callee@plt +; RV64I-NEXT: tail callee entry: %0 = alloca i8, i32 %size, align 16 %1 = tail call i32 @callee(i8* nonnull %0) @@ -730,7 +730,7 @@ define i32 @nocompress(i32 signext %size) { ; RV32IZCMP-NEXT: addi s7, s1, %lo(var) ; RV32IZCMP-NEXT: lw s8, 16(s7) ; RV32IZCMP-NEXT: mv a0, s2 -; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: call callee_void ; RV32IZCMP-NEXT: sw s8, 16(s7) ; RV32IZCMP-NEXT: sw s6, %lo(var+12)(s1) ; RV32IZCMP-NEXT: sw s5, %lo(var+8)(s1) @@ -739,7 +739,7 @@ define i32 @nocompress(i32 signext %size) { ; RV32IZCMP-NEXT: mv a0, s2 ; RV32IZCMP-NEXT: addi sp, s0, -48 ; RV32IZCMP-NEXT: cm.pop {ra, s0-s8}, 48 -; RV32IZCMP-NEXT: tail callee@plt +; RV32IZCMP-NEXT: tail callee ; ; RV64IZCMP-LABEL: nocompress: ; RV64IZCMP: # %bb.0: # %entry @@ -771,7 +771,7 @@ define i32 @nocompress(i32 signext %size) { ; RV64IZCMP-NEXT: addi s7, s1, %lo(var) ; RV64IZCMP-NEXT: lw s8, 16(s7) ; RV64IZCMP-NEXT: mv a0, s2 -; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: call callee_void ; RV64IZCMP-NEXT: sw s8, 16(s7) ; RV64IZCMP-NEXT: sw s6, %lo(var+12)(s1) ; RV64IZCMP-NEXT: sw s5, %lo(var+8)(s1) @@ -780,7 +780,7 @@ define i32 @nocompress(i32 signext %size) { ; RV64IZCMP-NEXT: mv a0, s2 ; RV64IZCMP-NEXT: addi sp, s0, -80 ; RV64IZCMP-NEXT: cm.pop {ra, s0-s8}, 80 -; RV64IZCMP-NEXT: tail callee@plt +; RV64IZCMP-NEXT: tail callee ; ; RV32IZCMP-SR-LABEL: nocompress: ; RV32IZCMP-SR: # %bb.0: # %entry @@ -810,7 +810,7 @@ define i32 @nocompress(i32 signext %size) { ; RV32IZCMP-SR-NEXT: addi s7, s1, %lo(var) ; RV32IZCMP-SR-NEXT: lw s8, 16(s7) ; RV32IZCMP-SR-NEXT: mv a0, s2 -; RV32IZCMP-SR-NEXT: call callee_void@plt +; RV32IZCMP-SR-NEXT: call callee_void ; RV32IZCMP-SR-NEXT: sw s8, 16(s7) ; RV32IZCMP-SR-NEXT: sw s6, %lo(var+12)(s1) ; RV32IZCMP-SR-NEXT: sw s5, %lo(var+8)(s1) @@ -819,7 +819,7 @@ define i32 @nocompress(i32 signext %size) { ; RV32IZCMP-SR-NEXT: mv a0, s2 ; RV32IZCMP-SR-NEXT: addi sp, s0, -48 ; RV32IZCMP-SR-NEXT: cm.pop {ra, s0-s8}, 48 -; RV32IZCMP-SR-NEXT: tail callee@plt +; RV32IZCMP-SR-NEXT: tail callee ; ; RV64IZCMP-SR-LABEL: nocompress: ; RV64IZCMP-SR: # %bb.0: # %entry @@ -851,7 +851,7 @@ define i32 @nocompress(i32 signext %size) { ; RV64IZCMP-SR-NEXT: addi s7, s1, %lo(var) ; RV64IZCMP-SR-NEXT: lw s8, 16(s7) ; RV64IZCMP-SR-NEXT: mv a0, s2 -; RV64IZCMP-SR-NEXT: call callee_void@plt +; RV64IZCMP-SR-NEXT: call callee_void ; RV64IZCMP-SR-NEXT: sw s8, 16(s7) ; RV64IZCMP-SR-NEXT: sw s6, %lo(var+12)(s1) ; RV64IZCMP-SR-NEXT: sw s5, %lo(var+8)(s1) @@ -860,7 +860,7 @@ define i32 @nocompress(i32 signext %size) { ; RV64IZCMP-SR-NEXT: mv a0, s2 ; RV64IZCMP-SR-NEXT: addi sp, s0, -80 ; RV64IZCMP-SR-NEXT: cm.pop {ra, s0-s8}, 80 -; RV64IZCMP-SR-NEXT: tail callee@plt +; RV64IZCMP-SR-NEXT: tail callee ; ; RV32I-LABEL: nocompress: ; RV32I: # %bb.0: # %entry @@ -900,7 +900,7 @@ define i32 @nocompress(i32 signext %size) { ; RV32I-NEXT: addi s7, s2, %lo(var) ; RV32I-NEXT: lw s8, 16(s7) ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: call callee_void ; RV32I-NEXT: sw s8, 16(s7) ; RV32I-NEXT: sw s6, %lo(var+12)(s2) ; RV32I-NEXT: sw s5, %lo(var+8)(s2) @@ -919,7 +919,7 @@ define i32 @nocompress(i32 signext %size) { ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 48 -; RV32I-NEXT: tail callee@plt +; RV32I-NEXT: tail callee ; ; RV64I-LABEL: nocompress: ; RV64I: # %bb.0: # %entry @@ -961,7 +961,7 @@ define i32 @nocompress(i32 signext %size) { ; RV64I-NEXT: addi s7, s2, %lo(var) ; RV64I-NEXT: lw s8, 16(s7) ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: call callee_void ; RV64I-NEXT: sw s8, 16(s7) ; RV64I-NEXT: sw s6, %lo(var+12)(s2) ; RV64I-NEXT: sw s5, %lo(var+8)(s2) @@ -980,7 +980,7 @@ define i32 @nocompress(i32 signext %size) { ; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s8, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 80 -; RV64I-NEXT: tail callee@plt +; RV64I-NEXT: tail callee entry: %0 = alloca i8, i32 %size, align 16 %val = load [5 x i32], [5 x i32]* @var @@ -1405,7 +1405,7 @@ define void @alloca(i32 %n) nounwind { ; RV32IZCMP-NEXT: andi a0, a0, -16 ; RV32IZCMP-NEXT: sub a0, sp, a0 ; RV32IZCMP-NEXT: mv sp, a0 -; RV32IZCMP-NEXT: call notdead@plt +; RV32IZCMP-NEXT: call notdead ; RV32IZCMP-NEXT: mv sp, s1 ; RV32IZCMP-NEXT: addi sp, s0, -16 ; RV32IZCMP-NEXT: cm.popret {ra, s0-s1}, 16 @@ -1421,7 +1421,7 @@ define void @alloca(i32 %n) nounwind { ; RV64IZCMP-NEXT: andi a0, a0, -16 ; RV64IZCMP-NEXT: sub a0, sp, a0 ; RV64IZCMP-NEXT: mv sp, a0 -; RV64IZCMP-NEXT: call notdead@plt +; RV64IZCMP-NEXT: call notdead ; RV64IZCMP-NEXT: mv sp, s1 ; RV64IZCMP-NEXT: addi sp, s0, -32 ; RV64IZCMP-NEXT: cm.popret {ra, s0-s1}, 32 @@ -1435,7 +1435,7 @@ define void @alloca(i32 %n) nounwind { ; RV32IZCMP-SR-NEXT: andi a0, a0, -16 ; RV32IZCMP-SR-NEXT: sub a0, sp, a0 ; RV32IZCMP-SR-NEXT: mv sp, a0 -; RV32IZCMP-SR-NEXT: call notdead@plt +; RV32IZCMP-SR-NEXT: call notdead ; RV32IZCMP-SR-NEXT: mv sp, s1 ; RV32IZCMP-SR-NEXT: addi sp, s0, -16 ; RV32IZCMP-SR-NEXT: cm.popret {ra, s0-s1}, 16 @@ -1451,7 +1451,7 @@ define void @alloca(i32 %n) nounwind { ; RV64IZCMP-SR-NEXT: andi a0, a0, -16 ; RV64IZCMP-SR-NEXT: sub a0, sp, a0 ; RV64IZCMP-SR-NEXT: mv sp, a0 -; RV64IZCMP-SR-NEXT: call notdead@plt +; RV64IZCMP-SR-NEXT: call notdead ; RV64IZCMP-SR-NEXT: mv sp, s1 ; RV64IZCMP-SR-NEXT: addi sp, s0, -32 ; RV64IZCMP-SR-NEXT: cm.popret {ra, s0-s1}, 32 @@ -1468,7 +1468,7 @@ define void @alloca(i32 %n) nounwind { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: call notdead@plt +; RV32I-NEXT: call notdead ; RV32I-NEXT: mv sp, s1 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1491,7 +1491,7 @@ define void @alloca(i32 %n) nounwind { ; RV64I-NEXT: andi a0, a0, -16 ; RV64I-NEXT: sub a0, sp, a0 ; RV64I-NEXT: mv sp, a0 -; RV64I-NEXT: call notdead@plt +; RV64I-NEXT: call notdead ; RV64I-NEXT: mv sp, s1 ; RV64I-NEXT: addi sp, s0, -32 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -1529,7 +1529,7 @@ define void @foo_with_irq() nounwind "interrupt"="user" { ; RV32IZCMP-NEXT: sw t4, 12(sp) # 4-byte Folded Spill ; RV32IZCMP-NEXT: sw t5, 8(sp) # 4-byte Folded Spill ; RV32IZCMP-NEXT: sw t6, 4(sp) # 4-byte Folded Spill -; RV32IZCMP-NEXT: call foo_test_irq@plt +; RV32IZCMP-NEXT: call foo_test_irq ; RV32IZCMP-NEXT: lw t0, 60(sp) # 4-byte Folded Reload ; RV32IZCMP-NEXT: lw t1, 56(sp) # 4-byte Folded Reload ; RV32IZCMP-NEXT: lw t2, 52(sp) # 4-byte Folded Reload @@ -1568,7 +1568,7 @@ define void @foo_with_irq() nounwind "interrupt"="user" { ; RV64IZCMP-NEXT: sd t4, 24(sp) # 8-byte Folded Spill ; RV64IZCMP-NEXT: sd t5, 16(sp) # 8-byte Folded Spill ; RV64IZCMP-NEXT: sd t6, 8(sp) # 8-byte Folded Spill -; RV64IZCMP-NEXT: call foo_test_irq@plt +; RV64IZCMP-NEXT: call foo_test_irq ; RV64IZCMP-NEXT: ld t0, 120(sp) # 8-byte Folded Reload ; RV64IZCMP-NEXT: ld t1, 112(sp) # 8-byte Folded Reload ; RV64IZCMP-NEXT: ld t2, 104(sp) # 8-byte Folded Reload @@ -1607,7 +1607,7 @@ define void @foo_with_irq() nounwind "interrupt"="user" { ; RV32IZCMP-SR-NEXT: sw t4, 12(sp) # 4-byte Folded Spill ; RV32IZCMP-SR-NEXT: sw t5, 8(sp) # 4-byte Folded Spill ; RV32IZCMP-SR-NEXT: sw t6, 4(sp) # 4-byte Folded Spill -; RV32IZCMP-SR-NEXT: call foo_test_irq@plt +; RV32IZCMP-SR-NEXT: call foo_test_irq ; RV32IZCMP-SR-NEXT: lw t0, 60(sp) # 4-byte Folded Reload ; RV32IZCMP-SR-NEXT: lw t1, 56(sp) # 4-byte Folded Reload ; RV32IZCMP-SR-NEXT: lw t2, 52(sp) # 4-byte Folded Reload @@ -1646,7 +1646,7 @@ define void @foo_with_irq() nounwind "interrupt"="user" { ; RV64IZCMP-SR-NEXT: sd t4, 24(sp) # 8-byte Folded Spill ; RV64IZCMP-SR-NEXT: sd t5, 16(sp) # 8-byte Folded Spill ; RV64IZCMP-SR-NEXT: sd t6, 8(sp) # 8-byte Folded Spill -; RV64IZCMP-SR-NEXT: call foo_test_irq@plt +; RV64IZCMP-SR-NEXT: call foo_test_irq ; RV64IZCMP-SR-NEXT: ld t0, 120(sp) # 8-byte Folded Reload ; RV64IZCMP-SR-NEXT: ld t1, 112(sp) # 8-byte Folded Reload ; RV64IZCMP-SR-NEXT: ld t2, 104(sp) # 8-byte Folded Reload @@ -1685,7 +1685,7 @@ define void @foo_with_irq() nounwind "interrupt"="user" { ; RV32I-NEXT: sw t4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw t5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw t6, 0(sp) # 4-byte Folded Spill -; RV32I-NEXT: call foo_test_irq@plt +; RV32I-NEXT: call foo_test_irq ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw t0, 56(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw t1, 52(sp) # 4-byte Folded Reload @@ -1724,7 +1724,7 @@ define void @foo_with_irq() nounwind "interrupt"="user" { ; RV64I-NEXT: sd t4, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd t5, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd t6, 0(sp) # 8-byte Folded Spill -; RV64I-NEXT: call foo_test_irq@plt +; RV64I-NEXT: call foo_test_irq ; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld t0, 112(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld t1, 104(sp) # 8-byte Folded Reload @@ -1751,32 +1751,32 @@ define void @foo_no_irq() nounwind{ ; RV32IZCMP-LABEL: foo_no_irq: ; RV32IZCMP: # %bb.0: ; RV32IZCMP-NEXT: cm.push {ra}, -16 -; RV32IZCMP-NEXT: call foo_test_irq@plt +; RV32IZCMP-NEXT: call foo_test_irq ; RV32IZCMP-NEXT: cm.popret {ra}, 16 ; ; RV64IZCMP-LABEL: foo_no_irq: ; RV64IZCMP: # %bb.0: ; RV64IZCMP-NEXT: cm.push {ra}, -16 -; RV64IZCMP-NEXT: call foo_test_irq@plt +; RV64IZCMP-NEXT: call foo_test_irq ; RV64IZCMP-NEXT: cm.popret {ra}, 16 ; ; RV32IZCMP-SR-LABEL: foo_no_irq: ; RV32IZCMP-SR: # %bb.0: ; RV32IZCMP-SR-NEXT: cm.push {ra}, -16 -; RV32IZCMP-SR-NEXT: call foo_test_irq@plt +; RV32IZCMP-SR-NEXT: call foo_test_irq ; RV32IZCMP-SR-NEXT: cm.popret {ra}, 16 ; ; RV64IZCMP-SR-LABEL: foo_no_irq: ; RV64IZCMP-SR: # %bb.0: ; RV64IZCMP-SR-NEXT: cm.push {ra}, -16 -; RV64IZCMP-SR-NEXT: call foo_test_irq@plt +; RV64IZCMP-SR-NEXT: call foo_test_irq ; RV64IZCMP-SR-NEXT: cm.popret {ra}, 16 ; ; RV32I-LABEL: foo_no_irq: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call foo_test_irq@plt +; RV32I-NEXT: call foo_test_irq ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1785,7 +1785,7 @@ define void @foo_no_irq() nounwind{ ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call foo_test_irq@plt +; RV64I-NEXT: call foo_test_irq ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -3115,7 +3115,7 @@ define i32 @use_fp(i32 %x) { ; RV32IZCMP-NEXT: mv s1, a0 ; RV32IZCMP-NEXT: addi a1, s0, -20 ; RV32IZCMP-NEXT: mv a0, s0 -; RV32IZCMP-NEXT: call bar@plt +; RV32IZCMP-NEXT: call bar ; RV32IZCMP-NEXT: mv a0, s1 ; RV32IZCMP-NEXT: cm.popret {ra, s0-s1}, 32 ; @@ -3131,7 +3131,7 @@ define i32 @use_fp(i32 %x) { ; RV64IZCMP-NEXT: mv s1, a0 ; RV64IZCMP-NEXT: addi a1, s0, -36 ; RV64IZCMP-NEXT: mv a0, s0 -; RV64IZCMP-NEXT: call bar@plt +; RV64IZCMP-NEXT: call bar ; RV64IZCMP-NEXT: mv a0, s1 ; RV64IZCMP-NEXT: cm.popret {ra, s0-s1}, 48 ; @@ -3147,7 +3147,7 @@ define i32 @use_fp(i32 %x) { ; RV32IZCMP-SR-NEXT: mv s1, a0 ; RV32IZCMP-SR-NEXT: addi a1, s0, -20 ; RV32IZCMP-SR-NEXT: mv a0, s0 -; RV32IZCMP-SR-NEXT: call bar@plt +; RV32IZCMP-SR-NEXT: call bar ; RV32IZCMP-SR-NEXT: mv a0, s1 ; RV32IZCMP-SR-NEXT: cm.popret {ra, s0-s1}, 32 ; @@ -3163,7 +3163,7 @@ define i32 @use_fp(i32 %x) { ; RV64IZCMP-SR-NEXT: mv s1, a0 ; RV64IZCMP-SR-NEXT: addi a1, s0, -36 ; RV64IZCMP-SR-NEXT: mv a0, s0 -; RV64IZCMP-SR-NEXT: call bar@plt +; RV64IZCMP-SR-NEXT: call bar ; RV64IZCMP-SR-NEXT: mv a0, s1 ; RV64IZCMP-SR-NEXT: cm.popret {ra, s0-s1}, 48 ; @@ -3182,7 +3182,7 @@ define i32 @use_fp(i32 %x) { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a1, s0, -16 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call bar@plt +; RV32I-NEXT: call bar ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -3205,7 +3205,7 @@ define i32 @use_fp(i32 %x) { ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: addi a1, s0, -28 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call bar@plt +; RV64I-NEXT: call bar ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll index bb65f408c77a..351408a7f085 100644 --- a/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll +++ b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll @@ -21,15 +21,15 @@ define signext i32 @test() nounwind { ; RV64I-NEXT: beqz s0, .LBB0_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call test1@plt +; RV64I-NEXT: call test1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call test2@plt +; RV64I-NEXT: call test2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call test3@plt +; RV64I-NEXT: call test3 ; RV64I-NEXT: j .LBB0_3 ; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: li a0, 0 -; RV64I-NEXT: call test2@plt +; RV64I-NEXT: call test2 ; RV64I-NEXT: .LBB0_3: ; RV64I-NEXT: li a0, 0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -68,7 +68,7 @@ define signext i32 @test_loop() nounwind { ; RV64I-NEXT: j .LBB1_2 ; RV64I-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call test2@plt +; RV64I-NEXT: call test2 ; RV64I-NEXT: addiw s1, s1, 1 ; RV64I-NEXT: beqz s1, .LBB1_4 ; RV64I-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1 @@ -76,11 +76,11 @@ define signext i32 @test_loop() nounwind { ; RV64I-NEXT: beqz s0, .LBB1_1 ; RV64I-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call test1@plt +; RV64I-NEXT: call test1 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call test2@plt +; RV64I-NEXT: call test2 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call test3@plt +; RV64I-NEXT: call test3 ; RV64I-NEXT: addiw s1, s1, 1 ; RV64I-NEXT: bnez s1, .LBB1_2 ; RV64I-NEXT: .LBB1_4: diff --git a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll index f017d8dff2bd..804bc053728d 100644 --- a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll +++ b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll @@ -42,7 +42,7 @@ define void @last_chance_recoloring_failure() { ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill -; CHECK-NEXT: call func@plt +; CHECK-NEXT: call func ; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vrgather.vv v16, v8, v12, v0.t @@ -108,7 +108,7 @@ define void @last_chance_recoloring_failure() { ; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t ; SUBREGLIVENESS-NEXT: addi a0, sp, 16 ; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill -; SUBREGLIVENESS-NEXT: call func@plt +; SUBREGLIVENESS-NEXT: call func ; SUBREGLIVENESS-NEXT: li a0, 32 ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; SUBREGLIVENESS-NEXT: vrgather.vv v16, v8, v12, v0.t diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll index feece1f54ffc..5b27c4129df6 100644 --- a/llvm/test/CodeGen/RISCV/rem.ll +++ b/llvm/test/CodeGen/RISCV/rem.ll @@ -11,7 +11,7 @@ define i32 @urem(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: urem: ; RV32I: # %bb.0: -; RV32I-NEXT: tail __umodsi3@plt +; RV32I-NEXT: tail __umodsi3 ; ; RV32IM-LABEL: urem: ; RV32IM: # %bb.0: @@ -26,7 +26,7 @@ define i32 @urem(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -44,7 +44,7 @@ define i32 @urem_constant_lhs(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: li a0, 10 -; RV32I-NEXT: tail __umodsi3@plt +; RV32I-NEXT: tail __umodsi3 ; ; RV32IM-LABEL: urem_constant_lhs: ; RV32IM: # %bb.0: @@ -59,7 +59,7 @@ define i32 @urem_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a1, a0, 32 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -76,7 +76,7 @@ define i32 @urem_constant_lhs(i32 %a) nounwind { define i32 @srem(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: srem: ; RV32I: # %bb.0: -; RV32I-NEXT: tail __modsi3@plt +; RV32I-NEXT: tail __modsi3 ; ; RV32IM-LABEL: srem: ; RV32IM: # %bb.0: @@ -89,7 +89,7 @@ define i32 @srem(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -191,7 +191,7 @@ define i32 @srem_constant_lhs(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: li a0, -10 -; RV32I-NEXT: tail __modsi3@plt +; RV32I-NEXT: tail __modsi3 ; ; RV32IM-LABEL: srem_constant_lhs: ; RV32IM: # %bb.0: @@ -205,7 +205,7 @@ define i32 @srem_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -224,7 +224,7 @@ define i64 @urem64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __umoddi3@plt +; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -233,14 +233,14 @@ define i64 @urem64(i64 %a, i64 %b) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IM-NEXT: call __umoddi3@plt +; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret ; ; RV64I-LABEL: urem64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __umoddi3@plt +; RV64I-NEXT: tail __umoddi3 ; ; RV64IM-LABEL: urem64: ; RV64IM: # %bb.0: @@ -259,7 +259,7 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind { ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: li a0, 10 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: call __umoddi3@plt +; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -272,7 +272,7 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind { ; RV32IM-NEXT: mv a2, a0 ; RV32IM-NEXT: li a0, 10 ; RV32IM-NEXT: li a1, 0 -; RV32IM-NEXT: call __umoddi3@plt +; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -281,7 +281,7 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: tail __umoddi3@plt +; RV64I-NEXT: tail __umoddi3 ; ; RV64IM-LABEL: urem64_constant_lhs: ; RV64IM: # %bb.0: @@ -297,7 +297,7 @@ define i64 @srem64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __moddi3@plt +; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -306,14 +306,14 @@ define i64 @srem64(i64 %a, i64 %b) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IM-NEXT: call __moddi3@plt +; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret ; ; RV64I-LABEL: srem64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __moddi3@plt +; RV64I-NEXT: tail __moddi3 ; ; RV64IM-LABEL: srem64: ; RV64IM: # %bb.0: @@ -332,7 +332,7 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind { ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: li a0, -10 ; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: call __moddi3@plt +; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -345,7 +345,7 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind { ; RV32IM-NEXT: mv a2, a0 ; RV32IM-NEXT: li a0, -10 ; RV32IM-NEXT: li a1, -1 -; RV32IM-NEXT: call __moddi3@plt +; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -354,7 +354,7 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: tail __moddi3@plt +; RV64I-NEXT: tail __moddi3 ; ; RV64IM-LABEL: srem64_constant_lhs: ; RV64IM: # %bb.0: @@ -372,7 +372,7 @@ define i8 @urem8(i8 %a, i8 %b) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a1, a1, 255 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -390,7 +390,7 @@ define i8 @urem8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: andi a1, a1, 255 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -412,7 +412,7 @@ define i8 @urem8_constant_lhs(i8 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: li a0, 10 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -430,7 +430,7 @@ define i8 @urem8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -455,7 +455,7 @@ define i8 @srem8(i8 %a, i8 %b) nounwind { ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: srai a1, a1, 24 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -477,7 +477,7 @@ define i8 @srem8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: srai a1, a1, 56 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -502,7 +502,7 @@ define i8 @srem8_constant_lhs(i8 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a1, a0, 24 ; RV32I-NEXT: li a0, -10 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -522,7 +522,7 @@ define i8 @srem8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a1, a0, 56 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -548,7 +548,7 @@ define i16 @urem16(i16 %a, i16 %b) nounwind { ; RV32I-NEXT: addi a2, a2, -1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -570,7 +570,7 @@ define i16 @urem16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: addiw a2, a2, -1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -595,7 +595,7 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: li a0, 10 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -615,7 +615,7 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -640,7 +640,7 @@ define i16 @srem16(i16 %a, i16 %b) nounwind { ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: srai a1, a1, 16 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -662,7 +662,7 @@ define i16 @srem16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: srai a1, a1, 48 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -687,7 +687,7 @@ define i16 @srem16_constant_lhs(i16 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a1, a0, 16 ; RV32I-NEXT: li a0, -10 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -707,7 +707,7 @@ define i16 @srem16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a1, a0, 48 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/remat.ll b/llvm/test/CodeGen/RISCV/remat.ll index e1c825fc8f26..92ae85f560cd 100644 --- a/llvm/test/CodeGen/RISCV/remat.ll +++ b/llvm/test/CodeGen/RISCV/remat.ll @@ -70,7 +70,7 @@ define i32 @test() nounwind { ; RV32I-NEXT: lw a3, %lo(d)(s5) ; RV32I-NEXT: lw a4, %lo(e)(s6) ; RV32I-NEXT: li a5, 32 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: .LBB0_5: # %if.end ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: lw a0, %lo(k)(s2) @@ -83,7 +83,7 @@ define i32 @test() nounwind { ; RV32I-NEXT: lw a3, %lo(e)(s6) ; RV32I-NEXT: lw a4, %lo(f)(s7) ; RV32I-NEXT: li a5, 64 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: .LBB0_7: # %if.end5 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: lw a0, %lo(j)(s3) @@ -96,7 +96,7 @@ define i32 @test() nounwind { ; RV32I-NEXT: lw a3, %lo(f)(s7) ; RV32I-NEXT: lw a4, %lo(g)(s8) ; RV32I-NEXT: li a5, 32 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: .LBB0_9: # %if.end9 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: lw a0, %lo(i)(s4) @@ -109,7 +109,7 @@ define i32 @test() nounwind { ; RV32I-NEXT: lw a3, %lo(g)(s8) ; RV32I-NEXT: lw a4, %lo(h)(s9) ; RV32I-NEXT: li a5, 32 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: j .LBB0_2 ; RV32I-NEXT: .LBB0_11: # %for.end ; RV32I-NEXT: li a0, 1 diff --git a/llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll b/llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll index e03696419467..cd7bce868eae 100644 --- a/llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll +++ b/llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll @@ -18,9 +18,9 @@ define float @float_test(float %a, float %b) nounwind { ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: mv s0, a1 -; RV32IF-NEXT: call __addsf3@plt +; RV32IF-NEXT: call __addsf3 ; RV32IF-NEXT: mv a1, s0 -; RV32IF-NEXT: call __divsf3@plt +; RV32IF-NEXT: call __divsf3 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 @@ -32,9 +32,9 @@ define float @float_test(float %a, float %b) nounwind { ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64IF-NEXT: mv s0, a1 -; RV64IF-NEXT: call __addsf3@plt +; RV64IF-NEXT: call __addsf3 ; RV64IF-NEXT: mv a1, s0 -; RV64IF-NEXT: call __divsf3@plt +; RV64IF-NEXT: call __divsf3 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 @@ -53,10 +53,10 @@ define double @double_test(double %a, double %b) nounwind { ; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: mv s0, a3 ; RV32IF-NEXT: mv s1, a2 -; RV32IF-NEXT: call __adddf3@plt +; RV32IF-NEXT: call __adddf3 ; RV32IF-NEXT: mv a2, s1 ; RV32IF-NEXT: mv a3, s0 -; RV32IF-NEXT: call __divdf3@plt +; RV32IF-NEXT: call __divdf3 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -69,9 +69,9 @@ define double @double_test(double %a, double %b) nounwind { ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64IF-NEXT: mv s0, a1 -; RV64IF-NEXT: call __adddf3@plt +; RV64IF-NEXT: call __adddf3 ; RV64IF-NEXT: mv a1, s0 -; RV64IF-NEXT: call __divdf3@plt +; RV64IF-NEXT: call __divdf3 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll b/llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll index 0269bbe9ee33..99b111b10f66 100644 --- a/llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll +++ b/llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll @@ -21,20 +21,20 @@ define half @half_test(half %a, half %b) nounwind { ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: and a0, s0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __addsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __addsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: and a0, a0, s2 -; RV32I-NEXT: call __extendhfsf2@plt +; RV32I-NEXT: call __extendhfsf2 ; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __divsf3@plt -; RV32I-NEXT: call __truncsfhf2@plt +; RV32I-NEXT: call __divsf3 +; RV32I-NEXT: call __truncsfhf2 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -53,20 +53,20 @@ define half @half_test(half %a, half %b) nounwind { ; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: and a0, s0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __addsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __addsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: and a0, a0, s2 -; RV64I-NEXT: call __extendhfsf2@plt +; RV64I-NEXT: call __extendhfsf2 ; RV64I-NEXT: mv a1, s0 -; RV64I-NEXT: call __divsf3@plt -; RV64I-NEXT: call __truncsfhf2@plt +; RV64I-NEXT: call __divsf3 +; RV64I-NEXT: call __truncsfhf2 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll index 321d9c612336..3731b9719445 100644 --- a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll @@ -42,7 +42,7 @@ define i32 @ctlz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -105,7 +105,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s3, a1, 257 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: or a0, s2, a0 @@ -129,7 +129,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s0, .LBB1_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 @@ -179,7 +179,7 @@ define i32 @cttz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI2_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0) @@ -229,14 +229,14 @@ define i64 @cttz_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi s3, a1, 1329 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, %hi(.LCPI3_0) ; RV32I-NEXT: addi s4, a0, %lo(.LCPI3_0) ; RV32I-NEXT: neg a0, s2 ; RV32I-NEXT: and a0, s2, a0 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s2, .LBB3_3 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: li a0, 32 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll index 5f9ca503bcb0..36c107061795 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll @@ -42,7 +42,7 @@ define i32 @ctlz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -105,7 +105,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s3, a1, 257 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: or a0, s2, a0 @@ -129,7 +129,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s0, .LBB1_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 @@ -179,7 +179,7 @@ define i32 @cttz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi a1, a1, 1329 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: lui a1, %hi(.LCPI2_0) ; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0) @@ -219,14 +219,14 @@ define i64 @cttz_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 30667 ; RV32I-NEXT: addi s3, a1, 1329 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, %hi(.LCPI3_0) ; RV32I-NEXT: addi s4, a0, %lo(.LCPI3_0) ; RV32I-NEXT: neg a0, s2 ; RV32I-NEXT: and a0, s2, a0 ; RV32I-NEXT: mv a1, s3 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s2, .LBB3_3 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: li a0, 32 @@ -295,7 +295,7 @@ define i32 @ctpop_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -418,7 +418,7 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli s2, a0, 24 ; RV32I-NEXT: srli a0, s0, 1 ; RV32I-NEXT: and a0, a0, s3 @@ -431,7 +431,7 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s5 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a1, a0, 24 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -586,7 +586,7 @@ define i64 @ctpop_i64(i64 %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli s5, a0, 24 ; RV32I-NEXT: srli a0, s0, 1 ; RV32I-NEXT: and a0, a0, s2 @@ -599,7 +599,7 @@ define i64 @ctpop_i64(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: add a0, a0, s5 ; RV32I-NEXT: li a1, 0 @@ -773,7 +773,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli s8, a0, 24 ; RV32I-NEXT: srli a0, s6, 1 ; RV32I-NEXT: and a0, a0, s3 @@ -786,7 +786,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s7 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: add s8, a0, s8 ; RV32I-NEXT: srli a0, s5, 1 @@ -800,7 +800,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s7 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli s5, a0, 24 ; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: and a0, a0, s3 @@ -813,7 +813,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s7 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __mulsi3@plt +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: add a0, a0, s5 ; RV32I-NEXT: sw zero, 12(s0) diff --git a/llvm/test/CodeGen/RISCV/rv64-large-stack.ll b/llvm/test/CodeGen/RISCV/rv64-large-stack.ll index 535550e83eeb..8bd99c0b639a 100644 --- a/llvm/test/CodeGen/RISCV/rv64-large-stack.ll +++ b/llvm/test/CodeGen/RISCV/rv64-large-stack.ll @@ -14,7 +14,7 @@ define void @foo() nounwind { ; CHECK-NEXT: addi a0, a0, -2000 ; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: call baz@plt +; CHECK-NEXT: call baz ; CHECK-NEXT: lui a0, 390625 ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -2000 diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll index 1ae2c1cfad68..17d9e9cefe11 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll @@ -13,7 +13,7 @@ define i32 @udiv(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -34,7 +34,7 @@ define i32 @udiv_constant(i32 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -74,7 +74,7 @@ define i32 @udiv_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a1, a0, 32 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -91,7 +91,7 @@ define i32 @udiv_constant_lhs(i32 %a) nounwind { define i64 @udiv64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: udiv64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __udivdi3@plt +; RV64I-NEXT: tail __udivdi3 ; ; RV64IM-LABEL: udiv64: ; RV64IM: # %bb.0: @@ -105,7 +105,7 @@ define i64 @udiv64_constant(i64 %a) nounwind { ; RV64I-LABEL: udiv64_constant: ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: tail __udivdi3@plt +; RV64I-NEXT: tail __udivdi3 ; ; RV64IM-LABEL: udiv64_constant: ; RV64IM: # %bb.0: @@ -125,7 +125,7 @@ define i64 @udiv64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: tail __udivdi3@plt +; RV64I-NEXT: tail __udivdi3 ; ; RV64IM-LABEL: udiv64_constant_lhs: ; RV64IM: # %bb.0: @@ -143,7 +143,7 @@ define i8 @udiv8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: andi a1, a1, 255 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -165,7 +165,7 @@ define i8 @udiv8_constant(i8 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -204,7 +204,7 @@ define i8 @udiv8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -228,7 +228,7 @@ define i16 @udiv16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: addiw a2, a2, -1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -253,7 +253,7 @@ define i16 @udiv16_constant(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -294,7 +294,7 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -317,7 +317,7 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -337,7 +337,7 @@ define i32 @sdiv_constant(i32 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -403,7 +403,7 @@ define i32 @sdiv_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -420,7 +420,7 @@ define i32 @sdiv_constant_lhs(i32 %a) nounwind { define i64 @sdiv64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: sdiv64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64: ; RV64IM: # %bb.0: @@ -434,7 +434,7 @@ define i64 @sdiv64_constant(i64 %a) nounwind { ; RV64I-LABEL: sdiv64_constant: ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64_constant: ; RV64IM: # %bb.0: @@ -454,7 +454,7 @@ define i64 @sdiv64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64_constant_lhs: ; RV64IM: # %bb.0: @@ -473,7 +473,7 @@ define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: tail __divdi3@plt +; RV64I-NEXT: tail __divdi3 ; ; RV64IM-LABEL: sdiv64_sext_operands: ; RV64IM: # %bb.0: @@ -496,7 +496,7 @@ define i8 @sdiv8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: sraiw a1, a1, 24 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: sraiw a0, a0, 24 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -521,7 +521,7 @@ define i8 @sdiv8_constant(i8 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: sraiw a0, a0, 24 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -575,7 +575,7 @@ define i8 @sdiv8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: sraiw a1, a0, 24 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -600,7 +600,7 @@ define i16 @sdiv16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: sraiw a1, a1, 16 ; RV64I-NEXT: slli a0, a0, 16 ; RV64I-NEXT: sraiw a0, a0, 16 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -625,7 +625,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 16 ; RV64I-NEXT: sraiw a0, a0, 16 ; RV64I-NEXT: li a1, 5 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -679,7 +679,7 @@ define i16 @sdiv16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 16 ; RV64I-NEXT: sraiw a1, a0, 16 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll index 76ab0e7d5810..de4c21f32468 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll @@ -325,7 +325,7 @@ define void @addi_fold_crash(i64 %arg) nounwind { ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: sb zero, 0(a0) ; RV64I-NEXT: mv a0, a1 -; RV64I-NEXT: call snork@plt +; RV64I-NEXT: call snork ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll index 11adbbdd245f..9d7b77de03ee 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll @@ -13,7 +13,7 @@ define i32 @urem(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -34,7 +34,7 @@ define i32 @urem_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a1, a0, 32 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -55,7 +55,7 @@ define i32 @srem(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a1, a1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -121,7 +121,7 @@ define i32 @srem_constant_lhs(i32 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -138,7 +138,7 @@ define i32 @srem_constant_lhs(i32 %a) nounwind { define i64 @urem64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: urem64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __umoddi3@plt +; RV64I-NEXT: tail __umoddi3 ; ; RV64IM-LABEL: urem64: ; RV64IM: # %bb.0: @@ -153,7 +153,7 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: tail __umoddi3@plt +; RV64I-NEXT: tail __umoddi3 ; ; RV64IM-LABEL: urem64_constant_lhs: ; RV64IM: # %bb.0: @@ -167,7 +167,7 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind { define i64 @srem64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: srem64: ; RV64I: # %bb.0: -; RV64I-NEXT: tail __moddi3@plt +; RV64I-NEXT: tail __moddi3 ; ; RV64IM-LABEL: srem64: ; RV64IM: # %bb.0: @@ -182,7 +182,7 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: tail __moddi3@plt +; RV64I-NEXT: tail __moddi3 ; ; RV64IM-LABEL: srem64_constant_lhs: ; RV64IM: # %bb.0: @@ -200,7 +200,7 @@ define i8 @urem8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: andi a1, a1, 255 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -222,7 +222,7 @@ define i8 @urem8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -247,7 +247,7 @@ define i8 @srem8(i8 %a, i8 %b) nounwind { ; RV64I-NEXT: sraiw a1, a1, 24 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: sraiw a0, a0, 24 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -272,7 +272,7 @@ define i8 @srem8_constant_lhs(i8 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: sraiw a1, a0, 24 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -298,7 +298,7 @@ define i16 @urem16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: addiw a2, a2, -1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -323,7 +323,7 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: li a0, 10 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -348,7 +348,7 @@ define i16 @srem16(i16 %a, i16 %b) nounwind { ; RV64I-NEXT: sraiw a1, a1, 16 ; RV64I-NEXT: slli a0, a0, 16 ; RV64I-NEXT: sraiw a0, a0, 16 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -373,7 +373,7 @@ define i16 @srem16_constant_lhs(i16 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 16 ; RV64I-NEXT: sraiw a1, a0, 16 ; RV64I-NEXT: li a0, -10 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll index 3e2e6ac75af8..4ec7f2660b2a 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll @@ -42,7 +42,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -97,7 +97,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -162,7 +162,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a1, a0, 24 ; RV64I-NEXT: .LBB2_2: # %cond.end ; RV64I-NEXT: subw a0, s0, a1 @@ -223,7 +223,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: xori a0, a0, 31 ; RV64I-NEXT: snez a1, s0 @@ -290,7 +290,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -358,7 +358,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -388,7 +388,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI6_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0) @@ -411,7 +411,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64XTHEADBB-NEXT: and a0, a0, a1 ; RV64XTHEADBB-NEXT: lui a1, 30667 ; RV64XTHEADBB-NEXT: addiw a1, a1, 1329 -; RV64XTHEADBB-NEXT: call __muldi3@plt +; RV64XTHEADBB-NEXT: call __muldi3 ; RV64XTHEADBB-NEXT: srliw a0, a0, 27 ; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI6_0) ; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI6_0) @@ -440,7 +440,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI7_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0) @@ -458,7 +458,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64XTHEADBB-NEXT: and a0, a0, a1 ; RV64XTHEADBB-NEXT: lui a1, 30667 ; RV64XTHEADBB-NEXT: addiw a1, a1, 1329 -; RV64XTHEADBB-NEXT: call __muldi3@plt +; RV64XTHEADBB-NEXT: call __muldi3 ; RV64XTHEADBB-NEXT: srliw a0, a0, 27 ; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI7_0) ; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI7_0) @@ -482,7 +482,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI8_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0) @@ -506,7 +506,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64XTHEADBB-NEXT: and a0, s0, a0 ; RV64XTHEADBB-NEXT: lui a1, 30667 ; RV64XTHEADBB-NEXT: addiw a1, a1, 1329 -; RV64XTHEADBB-NEXT: call __muldi3@plt +; RV64XTHEADBB-NEXT: call __muldi3 ; RV64XTHEADBB-NEXT: srliw a0, a0, 27 ; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI8_0) ; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI8_0) @@ -536,7 +536,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI9_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0) @@ -563,7 +563,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64XTHEADBB-NEXT: and a0, s0, a0 ; RV64XTHEADBB-NEXT: lui a1, 30667 ; RV64XTHEADBB-NEXT: addiw a1, a1, 1329 -; RV64XTHEADBB-NEXT: call __muldi3@plt +; RV64XTHEADBB-NEXT: call __muldi3 ; RV64XTHEADBB-NEXT: srliw a0, a0, 27 ; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI9_0) ; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI9_0) @@ -599,7 +599,7 @@ define i64 @cttz_i64(i64 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, %hi(.LCPI10_0) ; RV64I-NEXT: ld a1, %lo(.LCPI10_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI10_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_1) diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll index 1170a3011b9b..9b3f206be4a0 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll @@ -42,7 +42,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -95,7 +95,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -158,7 +158,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a1, a0, 24 ; RV64I-NEXT: .LBB2_2: # %cond.end ; RV64I-NEXT: subw a0, s0, a1 @@ -216,7 +216,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: xori a0, a0, 31 ; RV64I-NEXT: snez a1, s0 @@ -281,7 +281,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -348,7 +348,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -378,7 +378,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI6_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0) @@ -408,7 +408,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI7_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0) @@ -437,7 +437,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI8_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0) @@ -475,7 +475,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI9_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0) @@ -521,7 +521,7 @@ define i64 @cttz_i64(i64 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, %hi(.LCPI10_0) ; RV64I-NEXT: ld a1, %lo(.LCPI10_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI10_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_1) @@ -567,7 +567,7 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -605,7 +605,7 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -654,7 +654,7 @@ define i64 @ctpop_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll index af1eb318cb46..2db8e2c9b3d1 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll @@ -374,7 +374,7 @@ define void @bext_i32_trunc(i32 signext %0, i32 signext %1) { ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB19_2: -; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: tail bar ; ; RV64ZBS-LABEL: bext_i32_trunc: ; RV64ZBS: # %bb.0: @@ -383,7 +383,7 @@ define void @bext_i32_trunc(i32 signext %0, i32 signext %1) { ; RV64ZBS-NEXT: # %bb.1: ; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: .LBB19_2: -; RV64ZBS-NEXT: tail bar@plt +; RV64ZBS-NEXT: tail bar %3 = shl i32 1, %1 %4 = and i32 %3, %0 %5 = icmp eq i32 %4, 0 diff --git a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll index 690828c77943..16f4119ef20b 100644 --- a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll @@ -15,11 +15,11 @@ define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind { ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: srli s0, a0, 32 ; CHECK-NEXT: srli s1, a1, 32 -; CHECK-NEXT: call __addsf3@plt +; CHECK-NEXT: call __addsf3 ; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a1, s1 -; CHECK-NEXT: call __addsf3@plt +; CHECK-NEXT: call __addsf3 ; CHECK-NEXT: slli a0, a0, 32 ; CHECK-NEXT: slli s2, s2, 32 ; CHECK-NEXT: srli a1, s2, 32 diff --git a/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll index 25278caee64d..6fdf2a3a939c 100644 --- a/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll @@ -15,7 +15,7 @@ define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp { ; RV64I: # %bb.0: # %entry ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunsdfsi@plt +; RV64I-NEXT: call __fixunsdfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -24,7 +24,7 @@ define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp { ; RV64IF: # %bb.0: # %entry ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call __fixunsdfsi@plt +; RV64IF-NEXT: call __fixunsdfsi ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret @@ -38,7 +38,7 @@ define i32 @strict_fp64_to_si32(double %a) nounwind strictfp { ; RV64I: # %bb.0: # %entry ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixdfsi@plt +; RV64I-NEXT: call __fixdfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -47,7 +47,7 @@ define i32 @strict_fp64_to_si32(double %a) nounwind strictfp { ; RV64IF: # %bb.0: # %entry ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call __fixdfsi@plt +; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll index b7e112bbb7b5..b645b621c75c 100644 --- a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll @@ -13,7 +13,7 @@ define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp { ; RV64I: # %bb.0: # %entry ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixunssfsi@plt +; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -27,7 +27,7 @@ define i32 @strict_fp32_to_si32(float %a) nounwind strictfp { ; RV64I: # %bb.0: # %entry ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __fixsfsi@plt +; RV64I-NEXT: call __fixsfsi ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll index c8cd710fe9ae..1f62ea9f5681 100644 --- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll @@ -42,7 +42,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -97,7 +97,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -162,7 +162,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a1, a0, 24 ; RV64I-NEXT: .LBB2_2: # %cond.end ; RV64I-NEXT: sub a0, s0, a1 @@ -222,7 +222,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: xori a0, a0, 31 ; RV64I-NEXT: snez a1, s0 @@ -289,7 +289,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -358,7 +358,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -388,7 +388,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI6_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0) @@ -428,7 +428,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI7_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0) @@ -462,7 +462,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI8_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0) @@ -505,7 +505,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI9_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0) @@ -552,7 +552,7 @@ define i64 @cttz_i64(i64 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, %hi(.LCPI10_0) ; RV64I-NEXT: ld a1, %lo(.LCPI10_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI10_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_1) diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll index 8123721ed316..2269d8d04c9c 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll @@ -42,7 +42,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -95,7 +95,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -158,7 +158,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a1, a0, 24 ; RV64I-NEXT: .LBB2_2: # %cond.end ; RV64I-NEXT: sub a0, s0, a1 @@ -216,7 +216,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: xori a0, a0, 31 ; RV64I-NEXT: snez a1, s0 @@ -281,7 +281,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -348,7 +348,7 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -378,7 +378,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI6_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0) @@ -408,7 +408,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI7_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0) @@ -437,7 +437,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI8_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0) @@ -475,7 +475,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, s0, a0 ; RV64I-NEXT: lui a1, 30667 ; RV64I-NEXT: addiw a1, a1, 1329 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 27 ; RV64I-NEXT: lui a1, %hi(.LCPI9_0) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0) @@ -518,7 +518,7 @@ define i64 @cttz_i64(i64 %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, %hi(.LCPI10_0) ; RV64I-NEXT: ld a1, %lo(.LCPI10_0)(a1) -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: lui a1, %hi(.LCPI10_1) ; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_1) @@ -564,7 +564,7 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -678,7 +678,7 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind { ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -727,7 +727,7 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind { ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw s1, a1, 257 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw s2, a0, 24 ; RV64I-NEXT: srli a0, s0, 1 ; RV64I-NEXT: and a0, a0, s3 @@ -740,7 +740,7 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind { ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: and a0, a0, s5 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a1, a0, 24 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload @@ -903,7 +903,7 @@ define i64 @ctpop_i64(i64 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: slli a2, a1, 32 ; RV64I-NEXT: add a1, a1, a2 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1034,7 +1034,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV64I-NEXT: slli a1, s1, 32 ; RV64I-NEXT: add s1, s1, a1 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli s2, a0, 56 ; RV64I-NEXT: srli a0, s0, 1 ; RV64I-NEXT: and a0, a0, s3 @@ -1047,7 +1047,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: and a0, a0, s5 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call __muldi3@plt +; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srli a1, a0, 56 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll index 016b0924eaf1..d370b1877470 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll @@ -376,7 +376,7 @@ define void @bext_i32_trunc(i32 signext %0, i32 signext %1) { ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB19_2: -; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: tail bar ; ; RV64ZBS-LABEL: bext_i32_trunc: ; RV64ZBS: # %bb.0: @@ -385,7 +385,7 @@ define void @bext_i32_trunc(i32 signext %0, i32 signext %1) { ; RV64ZBS-NEXT: # %bb.1: ; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: .LBB19_2: -; RV64ZBS-NEXT: tail bar@plt +; RV64ZBS-NEXT: tail bar %3 = shl i32 1, %1 %4 = and i32 %3, %0 %5 = icmp eq i32 %4, 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll index 94218455a984..661b79141fee 100644 --- a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll @@ -313,7 +313,7 @@ define fastcc @ret_nxv32i32_call_nxv32i32_nxv32i32_i32( @ret_nxv32i32_call_nxv32i32_nxv32i32_i32( @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_ ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 128 ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: call ext3@plt +; RV32-NEXT: call ext3 ; RV32-NEXT: addi sp, s0, -144 ; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload @@ -487,7 +487,7 @@ define fastcc @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_ ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 128 ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: call ext3@plt +; RV64-NEXT: call ext3 ; RV64-NEXT: addi sp, s0, -144 ; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 128(sp) # 8-byte Folded Reload @@ -562,7 +562,7 @@ define fastcc @pass_vector_arg_indirect_stack( @pass_vector_arg_indirect_stack( @caller_scalable_vector_split_indirect( @caller_scalable_vector_split_indirect( @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX8-NEXT: li a1, 2 ; LMULMAX8-NEXT: vmv8r.v v8, v16 ; LMULMAX8-NEXT: vmv8r.v v16, v24 -; LMULMAX8-NEXT: call ext2@plt +; LMULMAX8-NEXT: call ext2 ; LMULMAX8-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: addi sp, sp, 16 ; LMULMAX8-NEXT: ret @@ -272,7 +272,7 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX4-NEXT: vmv4r.v v12, v20 ; LMULMAX4-NEXT: vmv4r.v v16, v28 ; LMULMAX4-NEXT: vmv4r.v v20, v24 -; LMULMAX4-NEXT: call ext2@plt +; LMULMAX4-NEXT: call ext2 ; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 16 ; LMULMAX4-NEXT: ret @@ -300,7 +300,7 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x ; LMULMAX8-NEXT: li a2, 42 ; LMULMAX8-NEXT: vse32.v v8, (a3) ; LMULMAX8-NEXT: vmv.v.v v8, v24 -; LMULMAX8-NEXT: call ext3@plt +; LMULMAX8-NEXT: call ext3 ; LMULMAX8-NEXT: addi sp, s0, -256 ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -330,7 +330,7 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x ; LMULMAX4-NEXT: vse32.v v8, (a1) ; LMULMAX4-NEXT: vmv.v.v v8, v24 ; LMULMAX4-NEXT: vmv.v.v v12, v28 -; LMULMAX4-NEXT: call ext3@plt +; LMULMAX4-NEXT: call ext3 ; LMULMAX4-NEXT: addi sp, s0, -256 ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -394,7 +394,7 @@ define fastcc <32 x i32> @pass_vector_arg_indirect_stack(<32 x i32> %x, <32 x i3 ; LMULMAX8-NEXT: vse32.v v8, (a0) ; LMULMAX8-NEXT: li a0, 0 ; LMULMAX8-NEXT: vmv.v.i v16, 0 -; LMULMAX8-NEXT: call vector_arg_indirect_stack@plt +; LMULMAX8-NEXT: call vector_arg_indirect_stack ; LMULMAX8-NEXT: addi sp, s0, -256 ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -431,7 +431,7 @@ define fastcc <32 x i32> @pass_vector_arg_indirect_stack(<32 x i32> %x, <32 x i3 ; LMULMAX4-NEXT: vmv.v.i v12, 0 ; LMULMAX4-NEXT: vmv.v.i v16, 0 ; LMULMAX4-NEXT: vmv.v.i v20, 0 -; LMULMAX4-NEXT: call vector_arg_indirect_stack@plt +; LMULMAX4-NEXT: call vector_arg_indirect_stack ; LMULMAX4-NEXT: addi sp, s0, -256 ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -501,7 +501,7 @@ define fastcc <32 x i32> @pass_vector_arg_direct_stack(<32 x i32> %x, <32 x i32> ; LMULMAX8-NEXT: sd a0, 0(sp) ; LMULMAX8-NEXT: li a0, 0 ; LMULMAX8-NEXT: vmv.v.i v16, 0 -; LMULMAX8-NEXT: call vector_arg_direct_stack@plt +; LMULMAX8-NEXT: call vector_arg_direct_stack ; LMULMAX8-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: addi sp, sp, 160 ; LMULMAX8-NEXT: ret @@ -538,7 +538,7 @@ define fastcc <32 x i32> @pass_vector_arg_direct_stack(<32 x i32> %x, <32 x i32> ; LMULMAX4-NEXT: vmv.v.i v12, 0 ; LMULMAX4-NEXT: vmv.v.i v16, 0 ; LMULMAX4-NEXT: vmv.v.i v20, 0 -; LMULMAX4-NEXT: call vector_arg_direct_stack@plt +; LMULMAX4-NEXT: call vector_arg_direct_stack ; LMULMAX4-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 160 ; LMULMAX4-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll index 775fd4984b89..8e3a432b8ac8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll @@ -693,7 +693,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX8-NEXT: li a1, 2 ; LMULMAX8-NEXT: vmv8r.v v8, v16 ; LMULMAX8-NEXT: vmv8r.v v16, v24 -; LMULMAX8-NEXT: call ext2@plt +; LMULMAX8-NEXT: call ext2 ; LMULMAX8-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: addi sp, sp, 16 ; LMULMAX8-NEXT: ret @@ -711,7 +711,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX4-NEXT: vmv4r.v v12, v20 ; LMULMAX4-NEXT: vmv4r.v v16, v28 ; LMULMAX4-NEXT: vmv4r.v v20, v24 -; LMULMAX4-NEXT: call ext2@plt +; LMULMAX4-NEXT: call ext2 ; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 16 ; LMULMAX4-NEXT: ret @@ -735,7 +735,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX2-NEXT: vmv2r.v v18, v28 ; LMULMAX2-NEXT: vmv2r.v v20, v26 ; LMULMAX2-NEXT: vmv2r.v v22, v24 -; LMULMAX2-NEXT: call ext2@plt +; LMULMAX2-NEXT: call ext2 ; LMULMAX2-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: addi sp, sp, 16 ; LMULMAX2-NEXT: ret @@ -771,7 +771,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX1-NEXT: vmv1r.v v21, v26 ; LMULMAX1-NEXT: vmv1r.v v22, v25 ; LMULMAX1-NEXT: vmv1r.v v23, v24 -; LMULMAX1-NEXT: call ext2@plt +; LMULMAX1-NEXT: call ext2 ; LMULMAX1-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: addi sp, sp, 16 ; LMULMAX1-NEXT: ret @@ -799,7 +799,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX8-NEXT: li a2, 42 ; LMULMAX8-NEXT: vse32.v v8, (a3) ; LMULMAX8-NEXT: vmv.v.v v8, v24 -; LMULMAX8-NEXT: call ext3@plt +; LMULMAX8-NEXT: call ext3 ; LMULMAX8-NEXT: addi sp, s0, -256 ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -829,7 +829,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX4-NEXT: vse32.v v8, (a1) ; LMULMAX4-NEXT: vmv.v.v v8, v24 ; LMULMAX4-NEXT: vmv.v.v v12, v28 -; LMULMAX4-NEXT: call ext3@plt +; LMULMAX4-NEXT: call ext3 ; LMULMAX4-NEXT: addi sp, s0, -256 ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -869,7 +869,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX2-NEXT: vmv.v.v v10, v26 ; LMULMAX2-NEXT: vmv.v.v v12, v28 ; LMULMAX2-NEXT: vmv.v.v v14, v30 -; LMULMAX2-NEXT: call ext3@plt +; LMULMAX2-NEXT: call ext3 ; LMULMAX2-NEXT: addi sp, s0, -256 ; LMULMAX2-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -936,7 +936,7 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX1-NEXT: vmv.v.v v13, v29 ; LMULMAX1-NEXT: vmv.v.v v14, v30 ; LMULMAX1-NEXT: vmv.v.v v15, v31 -; LMULMAX1-NEXT: call ext3@plt +; LMULMAX1-NEXT: call ext3 ; LMULMAX1-NEXT: addi sp, sp, 16 ; LMULMAX1-NEXT: addi sp, s0, -256 ; LMULMAX1-NEXT: ld ra, 248(sp) # 8-byte Folded Reload @@ -1043,7 +1043,7 @@ define <32 x i32> @call_split_vector_args(ptr %pa, ptr %pb) { ; LMULMAX8-NEXT: vmv1r.v v10, v8 ; LMULMAX8-NEXT: vmv1r.v v11, v8 ; LMULMAX8-NEXT: vmv1r.v v12, v8 -; LMULMAX8-NEXT: call split_vector_args@plt +; LMULMAX8-NEXT: call split_vector_args ; LMULMAX8-NEXT: addi sp, s0, -256 ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -1076,7 +1076,7 @@ define <32 x i32> @call_split_vector_args(ptr %pa, ptr %pb) { ; LMULMAX4-NEXT: vmv1r.v v10, v8 ; LMULMAX4-NEXT: vmv1r.v v11, v8 ; LMULMAX4-NEXT: vmv1r.v v12, v8 -; LMULMAX4-NEXT: call split_vector_args@plt +; LMULMAX4-NEXT: call split_vector_args ; LMULMAX4-NEXT: addi sp, s0, -256 ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -1116,7 +1116,7 @@ define <32 x i32> @call_split_vector_args(ptr %pa, ptr %pb) { ; LMULMAX2-NEXT: vmv1r.v v11, v8 ; LMULMAX2-NEXT: vmv1r.v v12, v8 ; LMULMAX2-NEXT: vmv.v.v v22, v14 -; LMULMAX2-NEXT: call split_vector_args@plt +; LMULMAX2-NEXT: call split_vector_args ; LMULMAX2-NEXT: addi sp, s0, -128 ; LMULMAX2-NEXT: ld ra, 120(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: ld s0, 112(sp) # 8-byte Folded Reload @@ -1170,7 +1170,7 @@ define <32 x i32> @call_split_vector_args(ptr %pa, ptr %pb) { ; LMULMAX1-NEXT: vmv.v.v v21, v13 ; LMULMAX1-NEXT: vmv.v.v v22, v14 ; LMULMAX1-NEXT: vmv.v.v v23, v15 -; LMULMAX1-NEXT: call split_vector_args@plt +; LMULMAX1-NEXT: call split_vector_args ; LMULMAX1-NEXT: addi sp, s0, -128 ; LMULMAX1-NEXT: ld ra, 120(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: ld s0, 112(sp) # 8-byte Folded Reload @@ -1273,7 +1273,7 @@ define <32 x i32> @pass_vector_arg_via_stack(<32 x i32> %x, <32 x i32> %y, <32 x ; LMULMAX8-NEXT: sd a0, 128(sp) ; LMULMAX8-NEXT: li a0, 0 ; LMULMAX8-NEXT: vmv.v.i v16, 0 -; LMULMAX8-NEXT: call vector_arg_via_stack@plt +; LMULMAX8-NEXT: call vector_arg_via_stack ; LMULMAX8-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: addi sp, sp, 144 ; LMULMAX8-NEXT: ret @@ -1302,7 +1302,7 @@ define <32 x i32> @pass_vector_arg_via_stack(<32 x i32> %x, <32 x i32> %y, <32 x ; LMULMAX4-NEXT: vmv.v.i v12, 0 ; LMULMAX4-NEXT: vmv.v.i v16, 0 ; LMULMAX4-NEXT: vmv.v.i v20, 0 -; LMULMAX4-NEXT: call vector_arg_via_stack@plt +; LMULMAX4-NEXT: call vector_arg_via_stack ; LMULMAX4-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 144 ; LMULMAX4-NEXT: ret @@ -1339,7 +1339,7 @@ define <32 x i32> @pass_vector_arg_via_stack(<32 x i32> %x, <32 x i32> %y, <32 x ; LMULMAX2-NEXT: vmv.v.i v18, 0 ; LMULMAX2-NEXT: vmv.v.i v20, 0 ; LMULMAX2-NEXT: vmv.v.i v22, 0 -; LMULMAX2-NEXT: call vector_arg_via_stack@plt +; LMULMAX2-NEXT: call vector_arg_via_stack ; LMULMAX2-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: addi sp, sp, 144 ; LMULMAX2-NEXT: ret @@ -1392,7 +1392,7 @@ define <32 x i32> @pass_vector_arg_via_stack(<32 x i32> %x, <32 x i32> %y, <32 x ; LMULMAX1-NEXT: vmv.v.i v21, 0 ; LMULMAX1-NEXT: vmv.v.i v22, 0 ; LMULMAX1-NEXT: vmv.v.i v23, 0 -; LMULMAX1-NEXT: call vector_arg_via_stack@plt +; LMULMAX1-NEXT: call vector_arg_via_stack ; LMULMAX1-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: addi sp, sp, 144 ; LMULMAX1-NEXT: ret @@ -1447,7 +1447,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX8-NEXT: li a3, 0 ; LMULMAX8-NEXT: li a4, 0 ; LMULMAX8-NEXT: vmv8r.v v16, v8 -; LMULMAX8-NEXT: call vector_mask_arg_via_stack@plt +; LMULMAX8-NEXT: call vector_mask_arg_via_stack ; LMULMAX8-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: addi sp, sp, 160 ; LMULMAX8-NEXT: ret @@ -1487,7 +1487,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX4-NEXT: vmv4r.v v12, v8 ; LMULMAX4-NEXT: vmv4r.v v16, v8 ; LMULMAX4-NEXT: vmv4r.v v20, v8 -; LMULMAX4-NEXT: call vector_mask_arg_via_stack@plt +; LMULMAX4-NEXT: call vector_mask_arg_via_stack ; LMULMAX4-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 160 ; LMULMAX4-NEXT: ret @@ -1535,7 +1535,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX2-NEXT: vmv2r.v v18, v8 ; LMULMAX2-NEXT: vmv2r.v v20, v8 ; LMULMAX2-NEXT: vmv2r.v v22, v8 -; LMULMAX2-NEXT: call vector_mask_arg_via_stack@plt +; LMULMAX2-NEXT: call vector_mask_arg_via_stack ; LMULMAX2-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: addi sp, sp, 160 ; LMULMAX2-NEXT: ret @@ -1599,7 +1599,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX1-NEXT: vmv1r.v v21, v8 ; LMULMAX1-NEXT: vmv1r.v v22, v8 ; LMULMAX1-NEXT: vmv1r.v v23, v8 -; LMULMAX1-NEXT: call vector_mask_arg_via_stack@plt +; LMULMAX1-NEXT: call vector_mask_arg_via_stack ; LMULMAX1-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: addi sp, sp, 160 ; LMULMAX1-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir index c261019e2e12..0403ceda8f11 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir @@ -18,7 +18,7 @@ ; CHECK-NEXT: addi a1, sp, 24 ; CHECK-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: ld a1, 0(sp) - ; CHECK-NEXT: call fixedlen_vector_spillslot@plt + ; CHECK-NEXT: call fixedlen_vector_spillslot ; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 48 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll index 06d1ada300a1..e969da6fd45b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll @@ -616,7 +616,7 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind { ; RV32NOM-NEXT: mv s2, a0 ; RV32NOM-NEXT: andi a0, a1, 31 ; RV32NOM-NEXT: li a1, 4 -; RV32NOM-NEXT: call __mulsi3@plt +; RV32NOM-NEXT: call __mulsi3 ; RV32NOM-NEXT: li a1, 32 ; RV32NOM-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32NOM-NEXT: vle32.v v8, (s2) @@ -666,7 +666,7 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind { ; RV64NOM-NEXT: mv s2, a0 ; RV64NOM-NEXT: andi a0, a1, 31 ; RV64NOM-NEXT: li a1, 4 -; RV64NOM-NEXT: call __muldi3@plt +; RV64NOM-NEXT: call __muldi3 ; RV64NOM-NEXT: li a1, 32 ; RV64NOM-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV64NOM-NEXT: vle32.v v8, (s2) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll index 7c5047bbdf63..d55683e653d2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll @@ -13,7 +13,7 @@ define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) { ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a1 @@ -49,7 +49,7 @@ define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) { ; RV32-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a1 @@ -62,7 +62,7 @@ define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: add a2, sp, a2 @@ -112,7 +112,7 @@ define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x) { ; RV32-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a1 @@ -126,7 +126,7 @@ define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -142,7 +142,7 @@ define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 2 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -158,7 +158,7 @@ define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 3 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -218,7 +218,7 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) { ; RV32-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a1 @@ -232,7 +232,7 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -248,7 +248,7 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 2 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -264,7 +264,7 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 3 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -325,7 +325,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 68(sp) ; RV32-NEXT: sw a0, 64(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -333,7 +333,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 7 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 124(sp) ; RV32-NEXT: sw a0, 120(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -341,7 +341,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 6 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 116(sp) ; RV32-NEXT: sw a0, 112(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -349,7 +349,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 5 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 108(sp) ; RV32-NEXT: sw a0, 104(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -357,7 +357,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 4 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 100(sp) ; RV32-NEXT: sw a0, 96(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma @@ -365,7 +365,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 3 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 92(sp) ; RV32-NEXT: sw a0, 88(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma @@ -373,7 +373,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 2 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 84(sp) ; RV32-NEXT: sw a0, 80(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma @@ -381,7 +381,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 76(sp) ; RV32-NEXT: sw a0, 72(sp) ; RV32-NEXT: addi a0, sp, 64 @@ -471,42 +471,42 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: flw fa0, 124(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 252(sp) ; RV32-NEXT: sw a0, 248(sp) ; RV32-NEXT: flw fa0, 120(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 244(sp) ; RV32-NEXT: sw a0, 240(sp) ; RV32-NEXT: flw fa0, 116(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 236(sp) ; RV32-NEXT: sw a0, 232(sp) ; RV32-NEXT: flw fa0, 112(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 228(sp) ; RV32-NEXT: sw a0, 224(sp) ; RV32-NEXT: flw fa0, 108(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 220(sp) ; RV32-NEXT: sw a0, 216(sp) ; RV32-NEXT: flw fa0, 104(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 212(sp) ; RV32-NEXT: sw a0, 208(sp) ; RV32-NEXT: flw fa0, 100(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 204(sp) ; RV32-NEXT: sw a0, 200(sp) ; RV32-NEXT: flw fa0, 96(sp) -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 196(sp) ; RV32-NEXT: sw a0, 192(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32-NEXT: addi a0, sp, 384 ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 132(sp) ; RV32-NEXT: sw a0, 128(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma @@ -514,7 +514,7 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 3 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 156(sp) ; RV32-NEXT: sw a0, 152(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma @@ -522,7 +522,7 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 2 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 148(sp) ; RV32-NEXT: sw a0, 144(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma @@ -530,7 +530,7 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 140(sp) ; RV32-NEXT: sw a0, 136(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -538,7 +538,7 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 7 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 188(sp) ; RV32-NEXT: sw a0, 184(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -546,7 +546,7 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 6 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 180(sp) ; RV32-NEXT: sw a0, 176(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -554,7 +554,7 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 5 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 172(sp) ; RV32-NEXT: sw a0, 168(sp) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma @@ -562,7 +562,7 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 4 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrintf@plt +; RV32-NEXT: call llrintf ; RV32-NEXT: sw a1, 164(sp) ; RV32-NEXT: sw a0, 160(sp) ; RV32-NEXT: li a0, 32 @@ -668,7 +668,7 @@ define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) { ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a1 @@ -703,7 +703,7 @@ define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) { ; RV32-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a1 @@ -716,7 +716,7 @@ define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) { ; RV32-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: add a2, sp, a2 @@ -766,7 +766,7 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) { ; RV32-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a1 @@ -780,7 +780,7 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -796,7 +796,7 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 2 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -812,7 +812,7 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) { ; RV32-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 3 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -875,26 +875,26 @@ define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) { ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: fld fa0, 120(sp) -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 188(sp) ; RV32-NEXT: sw a0, 184(sp) ; RV32-NEXT: fld fa0, 112(sp) -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 180(sp) ; RV32-NEXT: sw a0, 176(sp) ; RV32-NEXT: fld fa0, 104(sp) -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 172(sp) ; RV32-NEXT: sw a0, 168(sp) ; RV32-NEXT: fld fa0, 96(sp) -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 164(sp) ; RV32-NEXT: sw a0, 160(sp) ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: addi a0, sp, 256 ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 132(sp) ; RV32-NEXT: sw a0, 128(sp) ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma @@ -902,7 +902,7 @@ define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 140(sp) ; RV32-NEXT: sw a0, 136(sp) ; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma @@ -910,7 +910,7 @@ define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 3 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 156(sp) ; RV32-NEXT: sw a0, 152(sp) ; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma @@ -918,7 +918,7 @@ define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) { ; RV32-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vslidedown.vi v8, v8, 2 ; RV32-NEXT: vfmv.f.s fa0, v8 -; RV32-NEXT: call llrint@plt +; RV32-NEXT: call llrint ; RV32-NEXT: sw a1, 148(sp) ; RV32-NEXT: sw a0, 144(sp) ; RV32-NEXT: addi a0, sp, 128 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll index 4e576f12e107..34339a6f613f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll @@ -1429,7 +1429,7 @@ define i8 @vpreduce_mul_v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 zeroext %evl) ; RV32-NEXT: vmerge.vvm v8, v9, v8, v0 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: mv a1, a2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -1450,7 +1450,7 @@ define i8 @vpreduce_mul_v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 zeroext %evl) ; RV64-NEXT: vmerge.vvm v8, v9, v8, v0 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: mv a1, a2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -1479,7 +1479,7 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3 ; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: mv a1, a2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a0, a0, 24 ; RV32-NEXT: srai a0, a0, 24 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1504,7 +1504,7 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3 ; RV64-NEXT: vmul.vv v8, v8, v9 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: mv a1, a2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a0, a0, 56 ; RV64-NEXT: srai a0, a0, 56 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1537,7 +1537,7 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3 ; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: mv a1, a2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a0, a0, 24 ; RV32-NEXT: srai a0, a0, 24 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1564,7 +1564,7 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3 ; RV64-NEXT: vmul.vv v8, v8, v9 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: mv a1, a2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a0, a0, 56 ; RV64-NEXT: srai a0, a0, 56 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1599,7 +1599,7 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3 ; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: mv a1, a2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a0, a0, 24 ; RV32-NEXT: srai a0, a0, 24 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1628,7 +1628,7 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3 ; RV64-NEXT: vmul.vv v8, v8, v9 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: mv a1, a2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a0, a0, 56 ; RV64-NEXT: srai a0, a0, 56 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1665,7 +1665,7 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m, ; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: mv a1, a2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a0, a0, 24 ; RV32-NEXT: srai a0, a0, 24 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1696,7 +1696,7 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m, ; RV64-NEXT: vmul.vv v8, v8, v9 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: mv a1, a2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a0, a0, 56 ; RV64-NEXT: srai a0, a0, 56 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1736,7 +1736,7 @@ define signext i8 @vpreduce_mul_v32i8(i8 signext %s, <32 x i8> %v, <32 x i1> %m, ; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: mv a1, a2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a0, a0, 24 ; RV32-NEXT: srai a0, a0, 24 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1770,7 +1770,7 @@ define signext i8 @vpreduce_mul_v32i8(i8 signext %s, <32 x i8> %v, <32 x i1> %m, ; RV64-NEXT: vmul.vv v8, v8, v10 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: mv a1, a2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a0, a0, 56 ; RV64-NEXT: srai a0, a0, 56 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -1820,7 +1820,7 @@ define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m, ; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: mv a1, a2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a0, a0, 24 ; RV32-NEXT: srai a0, a0, 24 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1864,7 +1864,7 @@ define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m, ; RV64-NEXT: vmul.vv v8, v8, v12 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: mv a1, a2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a0, a0, 56 ; RV64-NEXT: srai a0, a0, 56 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll index f1a82b9e427e..783738f918d0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll @@ -352,17 +352,17 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 16(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs2, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: lui a1, 524288 ; CHECK-NOV-NEXT: addiw a4, a1, -1 @@ -446,14 +446,14 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -466,7 +466,7 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -482,7 +482,7 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -540,17 +540,17 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 8(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.lu.s s1, fs2, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-NOV-NEXT: li a1, -1 ; CHECK-NOV-NEXT: srli a1, a1, 32 @@ -614,14 +614,14 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -634,7 +634,7 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -650,7 +650,7 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -706,17 +706,17 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 8(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs2, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: li a2, -1 ; CHECK-NOV-NEXT: srli a2, a2, 32 @@ -792,14 +792,14 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -812,7 +812,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -828,7 +828,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1236,29 +1236,29 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 48(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs6, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s7 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs5, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s6 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs4, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s5 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs3, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s4 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs6, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: lui a7, 8 ; CHECK-NOV-NEXT: addiw a7, a7, -1 @@ -1416,14 +1416,14 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: lhu s6, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s6 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1432,7 +1432,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s5 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1441,7 +1441,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s4 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1450,7 +1450,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s3 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 5, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1459,7 +1459,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 4 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 6, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1468,7 +1468,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 5 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 7, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1477,7 +1477,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 6 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1556,29 +1556,29 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 8(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs6, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s7 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs5, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s6 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs4, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s5 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs3, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s4 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.lu.s s1, fs6, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-NOV-NEXT: lui a1, 16 ; CHECK-NOV-NEXT: addiw a1, a1, -1 @@ -1694,14 +1694,14 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: lhu s6, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s6 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1710,7 +1710,7 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s5 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1719,7 +1719,7 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s4 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1728,7 +1728,7 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s3 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 5, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1737,7 +1737,7 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 4 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 6, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1746,7 +1746,7 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 5 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 7, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1755,7 +1755,7 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 6 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -1832,29 +1832,29 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 8(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs6, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s7 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs5, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s6 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs4, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s5 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs3, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s4 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs6, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: lui a3, 16 ; CHECK-NOV-NEXT: addiw a3, a3, -1 @@ -1994,14 +1994,14 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: lhu s6, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s6 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -2010,7 +2010,7 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s5 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -2019,7 +2019,7 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s4 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -2028,7 +2028,7 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s3 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 5, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -2037,7 +2037,7 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 4 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 6, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -2046,7 +2046,7 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 5 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 7, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -2055,7 +2055,7 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 6 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -2107,11 +2107,11 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.d fs0, fa1 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv a2, a0 ; CHECK-NOV-NEXT: li a0, -1 ; CHECK-NOV-NEXT: srli a3, a0, 1 @@ -2192,14 +2192,14 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB18_3 @@ -2287,11 +2287,11 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.d fs0, fa1 -; CHECK-NOV-NEXT: call __fixunsdfti@plt +; CHECK-NOV-NEXT: call __fixunsdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 -; CHECK-NOV-NEXT: call __fixunsdfti@plt +; CHECK-NOV-NEXT: call __fixunsdfti ; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: snez a2, s1 ; CHECK-NOV-NEXT: addi a2, a2, -1 @@ -2325,14 +2325,14 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixunsdfti@plt +; CHECK-V-NEXT: call __fixunsdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixunsdfti@plt +; CHECK-V-NEXT: call __fixunsdfti ; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 @@ -2373,11 +2373,11 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.d fs0, fa1 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv a2, s1 ; CHECK-NOV-NEXT: blez s1, .LBB20_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -2437,14 +2437,14 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv a2, s1 ; CHECK-V-NEXT: blez s1, .LBB20_2 ; CHECK-V-NEXT: # %bb.1: # %entry @@ -2514,11 +2514,11 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.s fs0, fa1 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, a0 ; CHECK-NOV-NEXT: li a0, -1 ; CHECK-NOV-NEXT: srli a3, a0, 1 @@ -2599,14 +2599,14 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB21_3 @@ -2694,11 +2694,11 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.s fs0, fa1 -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: snez a2, s1 ; CHECK-NOV-NEXT: addi a2, a2, -1 @@ -2732,14 +2732,14 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 @@ -2780,11 +2780,11 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.s fs0, fa1 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, s1 ; CHECK-NOV-NEXT: blez s1, .LBB23_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -2844,14 +2844,14 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv a2, s1 ; CHECK-V-NEXT: blez s1, .LBB23_2 ; CHECK-V-NEXT: # %bb.1: # %entry @@ -2922,13 +2922,13 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s2, -32 ; CHECK-NOV-NEXT: mv s2, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, a0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, a0 ; CHECK-NOV-NEXT: li a0, -1 ; CHECK-NOV-NEXT: srli a3, a0, 1 @@ -3004,13 +3004,13 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: mv s2, a1 ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB24_3 @@ -3097,13 +3097,13 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s2, -32 ; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, a0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s1, a0 ; CHECK-NOV-NEXT: mv s2, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, s0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: snez a2, s2 ; CHECK-NOV-NEXT: addi a2, a2, -1 @@ -3132,13 +3132,13 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s2, a1 ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a2, s2 ; CHECK-V-NEXT: addi a2, a2, -1 @@ -3178,13 +3178,13 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s2, -32 ; CHECK-NOV-NEXT: mv s2, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, a0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, s1 ; CHECK-NOV-NEXT: blez s1, .LBB26_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -3239,13 +3239,13 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: mv s2, a1 ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv a2, s1 ; CHECK-V-NEXT: blez s1, .LBB26_2 ; CHECK-V-NEXT: # %bb.1: # %entry @@ -3639,17 +3639,17 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 16(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs2, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: lui a1, 524288 ; CHECK-NOV-NEXT: addiw a4, a1, -1 @@ -3733,14 +3733,14 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -3753,7 +3753,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -3769,7 +3769,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -3825,17 +3825,17 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 8(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.lu.s s1, fs2, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-NOV-NEXT: li a1, -1 ; CHECK-NOV-NEXT: srli a1, a1, 32 @@ -3899,14 +3899,14 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -3919,7 +3919,7 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -3935,7 +3935,7 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -3990,17 +3990,17 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 16(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs2, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: li a2, -1 ; CHECK-NOV-NEXT: srli a2, a2, 32 @@ -4076,14 +4076,14 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4096,7 +4096,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4112,7 +4112,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) { ; CHECK-V-NEXT: addi a0, a0, 16 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4508,29 +4508,29 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 48(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs6, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s7 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs5, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s6 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs4, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s5 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs3, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s4 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs6, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: lui a7, 8 ; CHECK-NOV-NEXT: addiw a7, a7, -1 @@ -4688,14 +4688,14 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: lhu s6, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s6 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4704,7 +4704,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s5 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4713,7 +4713,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s4 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4722,7 +4722,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s3 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 5, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4731,7 +4731,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 4 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 6, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4740,7 +4740,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 5 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 7, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4749,7 +4749,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 6 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4826,31 +4826,31 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 8(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs5, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s7 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs6, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s6 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs4, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s5 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs3, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s4 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fcvt.lu.s s2, fs6, rtz ; CHECK-NOV-NEXT: fcvt.lu.s a0, fs5, rtz ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: sext.w s1, a0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-NOV-NEXT: sext.w a0, a0 ; CHECK-NOV-NEXT: lui a1, 16 @@ -4962,14 +4962,14 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: lhu s6, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s6 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4978,7 +4978,7 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s5 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4987,7 +4987,7 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s4 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -4996,7 +4996,7 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s3 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 5, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5005,7 +5005,7 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 4 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 6, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5014,7 +5014,7 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 5 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 7, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5023,7 +5023,7 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 6 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5099,29 +5099,29 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-NOV-NEXT: lhu a1, 48(a1) ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs6, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s7 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs5, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s6 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs4, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s5 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs3, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s4 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs2, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s3 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs1, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.w.x fa0, s1 ; CHECK-NOV-NEXT: fcvt.l.s s1, fs6, rtz -; CHECK-NOV-NEXT: call __extendhfsf2@plt +; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-NOV-NEXT: lui a3, 16 ; CHECK-NOV-NEXT: addiw a3, a3, -1 @@ -5261,14 +5261,14 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: lhu s6, 0(a0) ; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s6 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5277,7 +5277,7 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s5 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 3, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5286,7 +5286,7 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s4 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5295,7 +5295,7 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s3 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 5, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5304,7 +5304,7 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 4 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 6, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5313,7 +5313,7 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 5 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s1 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 7, e32, m2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5322,7 +5322,7 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { ; CHECK-V-NEXT: vslideup.vi v10, v8, 6 ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt +; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -5372,11 +5372,11 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.d fs0, fa1 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv a2, a0 ; CHECK-NOV-NEXT: li a0, -1 ; CHECK-NOV-NEXT: srli a3, a0, 1 @@ -5460,14 +5460,14 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB45_2 @@ -5557,11 +5557,11 @@ define <2 x i64> @utest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.d fs0, fa0 ; CHECK-NOV-NEXT: fmv.d fa0, fa1 -; CHECK-NOV-NEXT: call __fixunsdfti@plt +; CHECK-NOV-NEXT: call __fixunsdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 -; CHECK-NOV-NEXT: call __fixunsdfti@plt +; CHECK-NOV-NEXT: call __fixunsdfti ; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: and a0, a1, a0 @@ -5593,7 +5593,7 @@ define <2 x i64> @utest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixunsdfti@plt +; CHECK-V-NEXT: call __fixunsdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma @@ -5601,7 +5601,7 @@ define <2 x i64> @utest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixunsdfti@plt +; CHECK-V-NEXT: call __fixunsdfti ; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a0, a1, a0 @@ -5641,11 +5641,11 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.d fs0, fa1 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 -; CHECK-NOV-NEXT: call __fixdfti@plt +; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB47_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -5694,14 +5694,14 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixdfti@plt +; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB47_2 ; CHECK-V-NEXT: # %bb.1: # %entry @@ -5758,11 +5758,11 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.s fs0, fa1 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, a0 ; CHECK-NOV-NEXT: li a0, -1 ; CHECK-NOV-NEXT: srli a3, a0, 1 @@ -5846,14 +5846,14 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB48_2 @@ -5943,11 +5943,11 @@ define <2 x i64> @utest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fmv.s fa0, fa1 -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: and a0, a1, a0 @@ -5979,7 +5979,7 @@ define <2 x i64> @utest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma @@ -5987,7 +5987,7 @@ define <2 x i64> @utest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a0, a1, a0 @@ -6027,11 +6027,11 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 ; CHECK-NOV-NEXT: fmv.s fs0, fa1 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB50_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -6080,14 +6080,14 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v9 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB50_2 ; CHECK-V-NEXT: # %bb.1: # %entry @@ -6145,13 +6145,13 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s2, -32 ; CHECK-NOV-NEXT: mv s2, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, a0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, a0 ; CHECK-NOV-NEXT: li a0, -1 ; CHECK-NOV-NEXT: srli a3, a0, 1 @@ -6230,13 +6230,13 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: mv s2, a1 ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB51_2 @@ -6324,13 +6324,13 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s2, -32 ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: fmv.w.x fa0, a1 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s1, a0 ; CHECK-NOV-NEXT: mv s2, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, s0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixunssfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: and a0, a1, a0 @@ -6358,13 +6358,13 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: fmv.w.x fa0, a1 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s2, a1 ; CHECK-V-NEXT: fmv.w.x fa0, s0 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixunssfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a0, a1, a0 @@ -6403,13 +6403,13 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s2, -32 ; CHECK-NOV-NEXT: mv s2, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, a0 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 -; CHECK-NOV-NEXT: call __extendhfsf2@plt -; CHECK-NOV-NEXT: call __fixsfti@plt +; CHECK-NOV-NEXT: call __extendhfsf2 +; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB53_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -6453,13 +6453,13 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: mv s2, a1 ; CHECK-V-NEXT: fmv.w.x fa0, a0 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: fmv.w.x fa0, s2 -; CHECK-V-NEXT: call __extendhfsf2@plt -; CHECK-V-NEXT: call __fixsfti@plt +; CHECK-V-NEXT: call __extendhfsf2 +; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB53_2 ; CHECK-V-NEXT: # %bb.1: # %entry diff --git a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir index de44fbc04e3a..bf78329c261f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir +++ b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir @@ -32,7 +32,7 @@ ; CHECK-NEXT: addi a0, a0, 241 ; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: ld a0, 8(sp) - ; CHECK-NEXT: call spillslot@plt + ; CHECK-NEXT: call spillslot ; CHECK-NEXT: addi sp, s0, -2048 ; CHECK-NEXT: addi sp, sp, -256 ; CHECK-NEXT: addi sp, sp, 272 diff --git a/llvm/test/CodeGen/RISCV/rvv/localvar.ll b/llvm/test/CodeGen/RISCV/rvv/localvar.ll index 8c9a749d5ea1..1ee88f897b6e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/localvar.ll +++ b/llvm/test/CodeGen/RISCV/rvv/localvar.ll @@ -215,7 +215,7 @@ define void @local_var_m2_with_varsize_object(i64 %n) { ; RV64IV-NEXT: slli s1, s1, 1 ; RV64IV-NEXT: sub s1, s0, s1 ; RV64IV-NEXT: addi s1, s1, -32 -; RV64IV-NEXT: call notdead@plt +; RV64IV-NEXT: call notdead ; RV64IV-NEXT: vl2r.v v8, (s1) ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 2 @@ -270,7 +270,7 @@ define void @local_var_m2_with_bp(i64 %n) { ; RV64IV-NEXT: slli s2, s2, 1 ; RV64IV-NEXT: add s2, s1, s2 ; RV64IV-NEXT: addi s2, s2, 224 -; RV64IV-NEXT: call notdead2@plt +; RV64IV-NEXT: call notdead2 ; RV64IV-NEXT: lw zero, 124(s1) ; RV64IV-NEXT: vl2r.v v8, (s2) ; RV64IV-NEXT: addi a0, s1, 224 diff --git a/llvm/test/CodeGen/RISCV/rvv/memory-args.ll b/llvm/test/CodeGen/RISCV/rvv/memory-args.ll index 5cd9c374ed41..bdfec92d2305 100644 --- a/llvm/test/CodeGen/RISCV/rvv/memory-args.ll +++ b/llvm/test/CodeGen/RISCV/rvv/memory-args.ll @@ -58,7 +58,7 @@ define @caller() { ; RV64IV-NEXT: addi a1, sp, 64 ; RV64IV-NEXT: addi a0, sp, 64 ; RV64IV-NEXT: vs8r.v v24, (a1) -; RV64IV-NEXT: call callee@plt +; RV64IV-NEXT: call callee ; RV64IV-NEXT: addi sp, s0, -80 ; RV64IV-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 64(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll b/llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll index 705ec2df126b..47b88ba71d55 100644 --- a/llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll +++ b/llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll @@ -38,7 +38,7 @@ define signext i32 @foo(i32 signext %aa) #0 { ; CHECK-NEXT: addi a1, s1, 48 ; CHECK-NEXT: sd t1, 0(sp) ; CHECK-NEXT: mv a0, t0 -; CHECK-NEXT: call gfunc@plt +; CHECK-NEXT: call gfunc ; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: addi sp, s0, -96 diff --git a/llvm/test/CodeGen/RISCV/rvv/pr63596.ll b/llvm/test/CodeGen/RISCV/rvv/pr63596.ll index 65dca0daed8c..c27488b18a01 100644 --- a/llvm/test/CodeGen/RISCV/rvv/pr63596.ll +++ b/llvm/test/CodeGen/RISCV/rvv/pr63596.ll @@ -14,16 +14,16 @@ define <4 x float> @foo(ptr %0) nounwind { ; CHECK-NEXT: lhu s2, 0(a0) ; CHECK-NEXT: lhu a0, 2(a0) ; CHECK-NEXT: fmv.w.x fa0, a0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fsw fa0, 8(sp) ; CHECK-NEXT: fmv.w.x fa0, s2 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fsw fa0, 0(sp) ; CHECK-NEXT: fmv.w.x fa0, s1 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fsw fa0, 12(sp) ; CHECK-NEXT: fmv.w.x fa0, s0 -; CHECK-NEXT: call __extendhfsf2@plt +; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: fsw fa0, 4(sp) ; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll b/llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll index 978d1c8fb7b0..600ac594380b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll @@ -38,7 +38,7 @@ define void @foo(ptr nocapture noundef %p1) { ; CHECK-NEXT: li a6, 7 ; CHECK-NEXT: li a7, 8 ; CHECK-NEXT: sd t0, 0(sp) -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (s2) diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll index c44f5ebcde48..129fbcfb8832 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll @@ -28,7 +28,7 @@ define @foo( %a, @foo( %a, @foo( %a, @foo( %a, @foo( %a, @foo(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, ; CHECK-NEXT: sd t0, 8(sp) ; CHECK-NEXT: sd t1, 0(sp) ; CHECK-NEXT: vmv8r.v v16, v8 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, s0, -96 ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir index 686401da41a4..b8a922a9fb1a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir @@ -24,7 +24,7 @@ ; RV32-NEXT: addi a0, sp, 32 ; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a2, sp, 8 - ; RV32-NEXT: call extern@plt + ; RV32-NEXT: call extern ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 1 ; RV32-NEXT: add sp, sp, a0 @@ -42,7 +42,7 @@ ; RV64-NEXT: addi a0, sp, 32 ; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: addi a2, sp, 8 - ; RV64-NEXT: call extern@plt + ; RV64-NEXT: call extern ; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: add sp, sp, a0 @@ -67,7 +67,7 @@ ; RV32-NEXT: addi a0, sp, 32 ; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a2, sp, 8 - ; RV32-NEXT: call extern@plt + ; RV32-NEXT: call extern ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 1 ; RV32-NEXT: add sp, sp, a0 @@ -85,7 +85,7 @@ ; RV64-NEXT: addi a0, sp, 32 ; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: addi a2, sp, 8 - ; RV64-NEXT: call extern@plt + ; RV64-NEXT: call extern ; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: add sp, sp, a0 @@ -113,7 +113,7 @@ ; RV32-NEXT: addi a0, sp, 32 ; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a2, sp, 8 - ; RV32-NEXT: call extern@plt + ; RV32-NEXT: call extern ; RV32-NEXT: addi sp, s0, -48 ; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 40(sp) # 4-byte Folded Reload @@ -133,7 +133,7 @@ ; RV64-NEXT: addi a0, sp, 64 ; RV64-NEXT: addi a1, sp, 40 ; RV64-NEXT: addi a2, sp, 32 - ; RV64-NEXT: call extern@plt + ; RV64-NEXT: call extern ; RV64-NEXT: addi sp, s0, -80 ; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll b/llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll index 76773bb38313..7aaafe9874fb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll +++ b/llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll @@ -19,7 +19,7 @@ define ptr @scalar_stack_align16() nounwind { ; RV32-NEXT: slli a0, a0, 1 ; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: addi a0, sp, 32 -; RV32-NEXT: call extern@plt +; RV32-NEXT: call extern ; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: slli a1, a1, 1 @@ -36,7 +36,7 @@ define ptr @scalar_stack_align16() nounwind { ; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: sub sp, sp, a0 ; RV64-NEXT: addi a0, sp, 32 -; RV64-NEXT: call extern@plt +; RV64-NEXT: call extern ; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: slli a1, a1, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll index 73f651225da6..07fcec13146c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll @@ -343,7 +343,7 @@ define @test8(i64 %avl, i8 zeroext %cond, @test9(i64 %avl, i8 zeroext %cond, @test3( %0, %1, @test3( %0, %1, This Inner Loop Header: Depth=1 ; CHECK-NEXT: mv a0, s1 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: sllw s1, s1, s0 ; CHECK-NEXT: bnez a0, .LBB0_1 ; CHECK-NEXT: # %bb.2: # %bb7 @@ -39,7 +39,7 @@ define void @test1(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB0_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, s1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: sllw s1, s1, s0 ; NOREMOVAL-NEXT: bnez a0, .LBB0_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -186,7 +186,7 @@ define void @test5(i32 signext %arg, i32 signext %arg1) nounwind { ; RV64I-NEXT: addi s3, a1, 257 ; RV64I-NEXT: .LBB4_1: # %bb2 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: call bar@plt +; RV64I-NEXT: call bar ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: and a0, a0, s0 @@ -217,7 +217,7 @@ define void @test5(i32 signext %arg, i32 signext %arg1) nounwind { ; RV64ZBB-NEXT: sraw a0, a0, a1 ; RV64ZBB-NEXT: .LBB4_1: # %bb2 ; RV64ZBB-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64ZBB-NEXT: call bar@plt +; RV64ZBB-NEXT: call bar ; RV64ZBB-NEXT: mv a1, a0 ; RV64ZBB-NEXT: cpopw a0, a0 ; RV64ZBB-NEXT: bnez a1, .LBB4_1 @@ -234,7 +234,7 @@ define void @test5(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB4_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, a1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: cpopw a1, a0 ; NOREMOVAL-NEXT: bnez a0, .LBB4_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -268,7 +268,7 @@ define void @test6(i32 signext %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: fmv.w.x fs0, zero ; CHECK-NEXT: .LBB5_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: call baz@plt +; CHECK-NEXT: call baz ; CHECK-NEXT: feq.s a1, fa0, fs0 ; CHECK-NEXT: fcvt.w.s a0, fa0, rtz ; CHECK-NEXT: beqz a1, .LBB5_1 @@ -288,7 +288,7 @@ define void @test6(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB5_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, a0 -; NOREMOVAL-NEXT: call baz@plt +; NOREMOVAL-NEXT: call baz ; NOREMOVAL-NEXT: feq.s a1, fa0, fs0 ; NOREMOVAL-NEXT: fcvt.w.s a0, fa0, rtz ; NOREMOVAL-NEXT: beqz a1, .LBB5_1 @@ -341,7 +341,7 @@ define void @test7(i32 signext %arg, i32 signext %arg1) nounwind { ; RV64I-NEXT: add s3, s3, a1 ; RV64I-NEXT: .LBB6_1: # %bb2 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: call foo@plt +; RV64I-NEXT: call foo ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a1, a1, s0 ; RV64I-NEXT: sub a0, a0, a1 @@ -371,7 +371,7 @@ define void @test7(i32 signext %arg, i32 signext %arg1) nounwind { ; RV64ZBB-NEXT: sraw a0, a0, a1 ; RV64ZBB-NEXT: .LBB6_1: # %bb2 ; RV64ZBB-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64ZBB-NEXT: call foo@plt +; RV64ZBB-NEXT: call foo ; RV64ZBB-NEXT: cpop a0, a0 ; RV64ZBB-NEXT: bnez a0, .LBB6_1 ; RV64ZBB-NEXT: # %bb.2: # %bb7 @@ -387,7 +387,7 @@ define void @test7(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB6_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, a0 -; NOREMOVAL-NEXT: call foo@plt +; NOREMOVAL-NEXT: call foo ; NOREMOVAL-NEXT: cpop a0, a0 ; NOREMOVAL-NEXT: bnez a0, .LBB6_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -420,7 +420,7 @@ define void @test8(i32 signext %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: sraw a0, a0, a1 ; CHECK-NEXT: .LBB7_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: call foo@plt +; CHECK-NEXT: call foo ; CHECK-NEXT: ori a0, a0, -256 ; CHECK-NEXT: bnez a0, .LBB7_1 ; CHECK-NEXT: # %bb.2: # %bb7 @@ -436,7 +436,7 @@ define void @test8(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB7_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, a0 -; NOREMOVAL-NEXT: call foo@plt +; NOREMOVAL-NEXT: call foo ; NOREMOVAL-NEXT: ori a0, a0, -256 ; NOREMOVAL-NEXT: bnez a0, .LBB7_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -471,7 +471,7 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: li s0, 254 ; CHECK-NEXT: .LBB8_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: mv a1, a0 ; CHECK-NEXT: slti a0, a0, 255 ; CHECK-NEXT: blt s0, a1, .LBB8_1 @@ -491,7 +491,7 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB8_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, a1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: slti a1, a0, 255 ; NOREMOVAL-NEXT: blt s0, a0, .LBB8_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -525,7 +525,7 @@ define void @test10(i32 signext %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: fmv.w.x fs0, zero ; CHECK-NEXT: .LBB9_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: call baz@plt +; CHECK-NEXT: call baz ; CHECK-NEXT: feq.s a1, fa0, fs0 ; CHECK-NEXT: fmv.x.w a0, fa0 ; CHECK-NEXT: beqz a1, .LBB9_1 @@ -545,7 +545,7 @@ define void @test10(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB9_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, a0 -; NOREMOVAL-NEXT: call baz@plt +; NOREMOVAL-NEXT: call baz ; NOREMOVAL-NEXT: feq.s a1, fa0, fs0 ; NOREMOVAL-NEXT: fmv.x.w a0, fa0 ; NOREMOVAL-NEXT: beqz a1, .LBB9_1 @@ -1152,12 +1152,12 @@ define void @test16(i32 signext %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: mv s0, a1 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: .LBB19_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: mv a0, s1 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: sllw s1, s1, s0 ; CHECK-NEXT: bnez a0, .LBB19_1 ; CHECK-NEXT: # %bb.2: # %bb7 @@ -1174,12 +1174,12 @@ define void @test16(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; NOREMOVAL-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; NOREMOVAL-NEXT: mv s0, a1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: mv s1, a0 ; NOREMOVAL-NEXT: .LBB19_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, s1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: sllw s1, s1, s0 ; NOREMOVAL-NEXT: bnez a0, .LBB19_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -1211,12 +1211,12 @@ define void @test17(i32 signext %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: mv s0, a1 -; CHECK-NEXT: call bat@plt +; CHECK-NEXT: call bat ; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: .LBB20_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: mv a0, s1 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: sllw s1, s1, s0 ; CHECK-NEXT: bnez a0, .LBB20_1 ; CHECK-NEXT: # %bb.2: # %bb7 @@ -1233,12 +1233,12 @@ define void @test17(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; NOREMOVAL-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; NOREMOVAL-NEXT: mv s0, a1 -; NOREMOVAL-NEXT: call bat@plt +; NOREMOVAL-NEXT: call bat ; NOREMOVAL-NEXT: mv s1, a0 ; NOREMOVAL-NEXT: .LBB20_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, s1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: sllw s1, s1, s0 ; NOREMOVAL-NEXT: bnez a0, .LBB20_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -1276,7 +1276,7 @@ define void @test18(i32 signext %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: .LBB21_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: mv a0, s1 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: sllw s1, s1, s0 ; CHECK-NEXT: bnez a0, .LBB21_1 ; CHECK-NEXT: # %bb.2: # %bb7 @@ -1297,7 +1297,7 @@ define void @test18(i32 signext %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB21_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, s1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: sllw s1, s1, s0 ; NOREMOVAL-NEXT: bnez a0, .LBB21_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 @@ -1385,10 +1385,10 @@ define signext i32 @test19(i64 %arg, i1 zeroext %c1, i1 zeroext %c2, ptr %p) nou ; CHECK-NEXT: beqz a2, .LBB23_2 ; CHECK-NEXT: # %bb.1: # %bb2 ; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: .LBB23_2: # %bb7 -; CHECK-NEXT: call side_effect@plt +; CHECK-NEXT: call side_effect ; CHECK-NEXT: sext.w a0, s0 ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -1409,10 +1409,10 @@ define signext i32 @test19(i64 %arg, i1 zeroext %c1, i1 zeroext %c2, ptr %p) nou ; NOREMOVAL-NEXT: beqz a2, .LBB23_2 ; NOREMOVAL-NEXT: # %bb.1: # %bb2 ; NOREMOVAL-NEXT: li a0, 0 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: mv s0, a0 ; NOREMOVAL-NEXT: .LBB23_2: # %bb7 -; NOREMOVAL-NEXT: call side_effect@plt +; NOREMOVAL-NEXT: call side_effect ; NOREMOVAL-NEXT: sext.w a0, s0 ; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; NOREMOVAL-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -1450,7 +1450,7 @@ define void @test20( %arg, i32 signext %arg1) nounwind { ; CHECK-NEXT: .LBB24_1: # %bb2 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: mv a0, s1 -; CHECK-NEXT: call bar@plt +; CHECK-NEXT: call bar ; CHECK-NEXT: sllw s1, s1, s0 ; CHECK-NEXT: bnez a0, .LBB24_1 ; CHECK-NEXT: # %bb.2: # %bb7 @@ -1472,7 +1472,7 @@ define void @test20( %arg, i32 signext %arg1) nounwind { ; NOREMOVAL-NEXT: .LBB24_1: # %bb2 ; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1 ; NOREMOVAL-NEXT: sext.w a0, s1 -; NOREMOVAL-NEXT: call bar@plt +; NOREMOVAL-NEXT: call bar ; NOREMOVAL-NEXT: sllw s1, s1, s0 ; NOREMOVAL-NEXT: bnez a0, .LBB24_1 ; NOREMOVAL-NEXT: # %bb.2: # %bb7 diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll b/llvm/test/CodeGen/RISCV/shadowcallstack.ll index fee067ee3ad1..b41b87aaf4d0 100644 --- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll +++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll @@ -20,11 +20,11 @@ declare void @foo() define void @f2() shadowcallstack { ; RV32-LABEL: f2: ; RV32: # %bb.0: -; RV32-NEXT: tail foo@plt +; RV32-NEXT: tail foo ; ; RV64-LABEL: f2: ; RV64: # %bb.0: -; RV64-NEXT: tail foo@plt +; RV64-NEXT: tail foo tail call void @foo() ret void } @@ -41,7 +41,7 @@ define i32 @f3() shadowcallstack { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: call bar@plt +; RV32-NEXT: call bar ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: lw ra, -4(gp) @@ -58,7 +58,7 @@ define i32 @f3() shadowcallstack { ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: call bar@plt +; RV64-NEXT: call bar ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ld ra, -8(gp) @@ -86,13 +86,13 @@ define i32 @f4() shadowcallstack { ; RV32-NEXT: .cfi_offset s0, -8 ; RV32-NEXT: .cfi_offset s1, -12 ; RV32-NEXT: .cfi_offset s2, -16 -; RV32-NEXT: call bar@plt +; RV32-NEXT: call bar ; RV32-NEXT: mv s0, a0 -; RV32-NEXT: call bar@plt +; RV32-NEXT: call bar ; RV32-NEXT: mv s1, a0 -; RV32-NEXT: call bar@plt +; RV32-NEXT: call bar ; RV32-NEXT: mv s2, a0 -; RV32-NEXT: call bar@plt +; RV32-NEXT: call bar ; RV32-NEXT: add s0, s0, s1 ; RV32-NEXT: add a0, s2, a0 ; RV32-NEXT: add a0, s0, a0 @@ -121,13 +121,13 @@ define i32 @f4() shadowcallstack { ; RV64-NEXT: .cfi_offset s0, -16 ; RV64-NEXT: .cfi_offset s1, -24 ; RV64-NEXT: .cfi_offset s2, -32 -; RV64-NEXT: call bar@plt +; RV64-NEXT: call bar ; RV64-NEXT: mv s0, a0 -; RV64-NEXT: call bar@plt +; RV64-NEXT: call bar ; RV64-NEXT: mv s1, a0 -; RV64-NEXT: call bar@plt +; RV64-NEXT: call bar ; RV64-NEXT: mv s2, a0 -; RV64-NEXT: call bar@plt +; RV64-NEXT: call bar ; RV64-NEXT: add s0, s0, s1 ; RV64-NEXT: add a0, s2, a0 ; RV64-NEXT: addw a0, s0, a0 @@ -157,7 +157,7 @@ define i32 @f5() shadowcallstack nounwind { ; RV32-NEXT: sw ra, -4(gp) ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-NEXT: call bar@plt +; RV32-NEXT: call bar ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: lw ra, -4(gp) @@ -170,7 +170,7 @@ define i32 @f5() shadowcallstack nounwind { ; RV64-NEXT: sd ra, -8(gp) ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-NEXT: call bar@plt +; RV64-NEXT: call bar ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ld ra, -8(gp) diff --git a/llvm/test/CodeGen/RISCV/shifts.ll b/llvm/test/CodeGen/RISCV/shifts.ll index 97121c275a29..f61cbfd3ed72 100644 --- a/llvm/test/CodeGen/RISCV/shifts.ll +++ b/llvm/test/CodeGen/RISCV/shifts.ll @@ -43,7 +43,7 @@ define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __lshrdi3@plt +; RV32I-NEXT: call __lshrdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -89,7 +89,7 @@ define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ashrdi3@plt +; RV32I-NEXT: call __ashrdi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -135,7 +135,7 @@ define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __ashldi3@plt +; RV32I-NEXT: call __ashldi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll index 725b8fd6eeea..d007c245d21b 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll @@ -431,7 +431,7 @@ define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 ; NOSFB-NEXT: .LBB15_1: # %bb2 ; NOSFB-NEXT: # =>This Inner Loop Header: Depth=1 ; NOSFB-NEXT: mv a0, s1 -; NOSFB-NEXT: call bar@plt +; NOSFB-NEXT: call bar ; NOSFB-NEXT: sllw s1, s1, s0 ; NOSFB-NEXT: bnez a0, .LBB15_1 ; NOSFB-NEXT: # %bb.2: # %bb7 @@ -457,7 +457,7 @@ define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 ; RV64SFB-NEXT: .LBB15_1: # %bb2 ; RV64SFB-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64SFB-NEXT: mv a0, s0 -; RV64SFB-NEXT: call bar@plt +; RV64SFB-NEXT: call bar ; RV64SFB-NEXT: sllw s0, s0, s1 ; RV64SFB-NEXT: bnez a0, .LBB15_1 ; RV64SFB-NEXT: # %bb.2: # %bb7 @@ -483,7 +483,7 @@ define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 ; ZICOND-NEXT: .LBB15_1: # %bb2 ; ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; ZICOND-NEXT: mv a0, s0 -; ZICOND-NEXT: call bar@plt +; ZICOND-NEXT: call bar ; ZICOND-NEXT: sllw s0, s0, s1 ; ZICOND-NEXT: bnez a0, .LBB15_1 ; ZICOND-NEXT: # %bb.2: # %bb7 @@ -509,7 +509,7 @@ define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 ; RV32SFB-NEXT: .LBB15_1: # %bb2 ; RV32SFB-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32SFB-NEXT: mv a0, s0 -; RV32SFB-NEXT: call bar@plt +; RV32SFB-NEXT: call bar ; RV32SFB-NEXT: sll s0, s0, s1 ; RV32SFB-NEXT: bnez a0, .LBB15_1 ; RV32SFB-NEXT: # %bb.2: # %bb7 @@ -550,7 +550,7 @@ define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i3 ; NOSFB-NEXT: .LBB16_1: # %bb2 ; NOSFB-NEXT: # =>This Inner Loop Header: Depth=1 ; NOSFB-NEXT: mv a0, s1 -; NOSFB-NEXT: call bar@plt +; NOSFB-NEXT: call bar ; NOSFB-NEXT: sllw s1, s1, s0 ; NOSFB-NEXT: bnez a0, .LBB16_1 ; NOSFB-NEXT: # %bb.2: # %bb7 @@ -576,7 +576,7 @@ define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i3 ; RV64SFB-NEXT: .LBB16_1: # %bb2 ; RV64SFB-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64SFB-NEXT: mv a0, s0 -; RV64SFB-NEXT: call bar@plt +; RV64SFB-NEXT: call bar ; RV64SFB-NEXT: sllw s0, s0, s1 ; RV64SFB-NEXT: bnez a0, .LBB16_1 ; RV64SFB-NEXT: # %bb.2: # %bb7 @@ -602,7 +602,7 @@ define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i3 ; ZICOND-NEXT: .LBB16_1: # %bb2 ; ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; ZICOND-NEXT: mv a0, s0 -; ZICOND-NEXT: call bar@plt +; ZICOND-NEXT: call bar ; ZICOND-NEXT: sllw s0, s0, s1 ; ZICOND-NEXT: bnez a0, .LBB16_1 ; ZICOND-NEXT: # %bb.2: # %bb7 @@ -628,7 +628,7 @@ define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i3 ; RV32SFB-NEXT: .LBB16_1: # %bb2 ; RV32SFB-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32SFB-NEXT: mv a0, s0 -; RV32SFB-NEXT: call bar@plt +; RV32SFB-NEXT: call bar ; RV32SFB-NEXT: sll s0, s0, s1 ; RV32SFB-NEXT: bnez a0, .LBB16_1 ; RV32SFB-NEXT: # %bb.2: # %bb7 diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll b/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll index 1c57b0f7e603..5e557de37423 100644 --- a/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll +++ b/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll @@ -23,21 +23,21 @@ define dso_local signext i32 @test_shrinkwrap_jump_table(ptr noundef %m) local_u ; CHECK-NEXT: lw a1, 0(a1) ; CHECK-NEXT: jr a1 ; CHECK-NEXT: .LBB0_2: # %sw.bb -; CHECK-NEXT: tail func1@plt +; CHECK-NEXT: tail func1 ; CHECK-NEXT: .LBB0_3: # %sw.bb7 -; CHECK-NEXT: tail func5@plt +; CHECK-NEXT: tail func5 ; CHECK-NEXT: .LBB0_4: # %sw.bb3 -; CHECK-NEXT: tail func3@plt +; CHECK-NEXT: tail func3 ; CHECK-NEXT: .LBB0_5: # %sw.bb5 -; CHECK-NEXT: tail func4@plt +; CHECK-NEXT: tail func4 ; CHECK-NEXT: .LBB0_6: # %sw.bb1 -; CHECK-NEXT: tail func2@plt +; CHECK-NEXT: tail func2 ; CHECK-NEXT: .LBB0_7: # %sw.default ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: .cfi_offset ra, -8 -; CHECK-NEXT: call default_func@plt +; CHECK-NEXT: call default_func ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll index 16f062a78323..40577701e1e2 100644 --- a/llvm/test/CodeGen/RISCV/shrinkwrap.ll +++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll @@ -22,7 +22,7 @@ define void @eliminate_restore(i32 %n) nounwind { ; RV32I-SW-NO-NEXT: addi sp, sp, 16 ; RV32I-SW-NO-NEXT: ret ; RV32I-SW-NO-NEXT: .LBB0_2: # %if.then -; RV32I-SW-NO-NEXT: call abort@plt +; RV32I-SW-NO-NEXT: call abort ; ; RV32I-SW-LABEL: eliminate_restore: ; RV32I-SW: # %bb.0: @@ -33,7 +33,7 @@ define void @eliminate_restore(i32 %n) nounwind { ; RV32I-SW-NEXT: .LBB0_2: # %if.then ; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-SW-NEXT: call abort@plt +; RV32I-SW-NEXT: call abort ; ; RV32I-SW-SR-LABEL: eliminate_restore: ; RV32I-SW-SR: # %bb.0: @@ -43,7 +43,7 @@ define void @eliminate_restore(i32 %n) nounwind { ; RV32I-SW-SR-NEXT: ret ; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then ; RV32I-SW-SR-NEXT: call t0, __riscv_save_0 -; RV32I-SW-SR-NEXT: call abort@plt +; RV32I-SW-SR-NEXT: call abort ; ; RV64I-SW-LABEL: eliminate_restore: ; RV64I-SW: # %bb.0: @@ -55,7 +55,7 @@ define void @eliminate_restore(i32 %n) nounwind { ; RV64I-SW-NEXT: .LBB0_2: # %if.then ; RV64I-SW-NEXT: addi sp, sp, -16 ; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-SW-NEXT: call abort@plt +; RV64I-SW-NEXT: call abort %cmp = icmp ule i32 %n, 32 br i1 %cmp, label %if.then, label %if.end @@ -83,7 +83,7 @@ define void @conditional_alloca(i32 %n) nounwind { ; RV32I-SW-NO-NEXT: andi a0, a0, -16 ; RV32I-SW-NO-NEXT: sub a0, sp, a0 ; RV32I-SW-NO-NEXT: mv sp, a0 -; RV32I-SW-NO-NEXT: call notdead@plt +; RV32I-SW-NO-NEXT: call notdead ; RV32I-SW-NO-NEXT: .LBB1_2: # %if.end ; RV32I-SW-NO-NEXT: addi sp, s0, -16 ; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -104,7 +104,7 @@ define void @conditional_alloca(i32 %n) nounwind { ; RV32I-SW-NEXT: andi a0, a0, -16 ; RV32I-SW-NEXT: sub a0, sp, a0 ; RV32I-SW-NEXT: mv sp, a0 -; RV32I-SW-NEXT: call notdead@plt +; RV32I-SW-NEXT: call notdead ; RV32I-SW-NEXT: addi sp, s0, -16 ; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -123,7 +123,7 @@ define void @conditional_alloca(i32 %n) nounwind { ; RV32I-SW-SR-NEXT: andi a0, a0, -16 ; RV32I-SW-SR-NEXT: sub a0, sp, a0 ; RV32I-SW-SR-NEXT: mv sp, a0 -; RV32I-SW-SR-NEXT: call notdead@plt +; RV32I-SW-SR-NEXT: call notdead ; RV32I-SW-SR-NEXT: addi sp, s0, -16 ; RV32I-SW-SR-NEXT: tail __riscv_restore_1 ; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end @@ -145,7 +145,7 @@ define void @conditional_alloca(i32 %n) nounwind { ; RV64I-SW-NEXT: andi a0, a0, -16 ; RV64I-SW-NEXT: sub a0, sp, a0 ; RV64I-SW-NEXT: mv sp, a0 -; RV64I-SW-NEXT: call notdead@plt +; RV64I-SW-NEXT: call notdead ; RV64I-SW-NEXT: addi sp, s0, -16 ; RV64I-SW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-SW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/split-sp-adjust.ll b/llvm/test/CodeGen/RISCV/split-sp-adjust.ll index 63a2c04de6c1..7889e005399f 100644 --- a/llvm/test/CodeGen/RISCV/split-sp-adjust.ll +++ b/llvm/test/CodeGen/RISCV/split-sp-adjust.ll @@ -10,7 +10,7 @@ define i32 @SplitSP() nounwind { ; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi a0, sp, 16 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: li a0, 0 ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload @@ -29,7 +29,7 @@ define i32 @NoSplitSP() nounwind { ; RV32I-NEXT: addi sp, sp, -2032 ; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill ; RV32I-NEXT: addi a0, sp, 4 -; RV32I-NEXT: call foo@plt +; RV32I-NEXT: call foo ; RV32I-NEXT: li a0, 0 ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 2032 diff --git a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll index b15f17ea9fb5..5fa802b7f27c 100644 --- a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll @@ -121,7 +121,7 @@ define iXLen2 @test_udiv_7(iXLen2 %x) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 7 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __udivdi3@plt +; RV32-NEXT: call __udivdi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -132,7 +132,7 @@ define iXLen2 @test_udiv_7(iXLen2 %x) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: li a2, 7 ; RV64-NEXT: li a3, 0 -; RV64-NEXT: call __udivti3@plt +; RV64-NEXT: call __udivti3 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -147,7 +147,7 @@ define iXLen2 @test_udiv_9(iXLen2 %x) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 9 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __udivdi3@plt +; RV32-NEXT: call __udivdi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -158,7 +158,7 @@ define iXLen2 @test_udiv_9(iXLen2 %x) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: li a2, 9 ; RV64-NEXT: li a3, 0 -; RV64-NEXT: call __udivti3@plt +; RV64-NEXT: call __udivti3 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll b/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll index cdfb1ef0ab4d..8444520fcc77 100644 --- a/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll @@ -83,7 +83,7 @@ define iXLen2 @test_urem_7(iXLen2 %x) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 7 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __umoddi3@plt +; RV32-NEXT: call __umoddi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -94,7 +94,7 @@ define iXLen2 @test_urem_7(iXLen2 %x) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: li a2, 7 ; RV64-NEXT: li a3, 0 -; RV64-NEXT: call __umodti3@plt +; RV64-NEXT: call __umodti3 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -109,7 +109,7 @@ define iXLen2 @test_urem_9(iXLen2 %x) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a2, 9 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __umoddi3@plt +; RV32-NEXT: call __umoddi3 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -120,7 +120,7 @@ define iXLen2 @test_urem_9(iXLen2 %x) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: li a2, 9 ; RV64-NEXT: li a3, 0 -; RV64-NEXT: call __umodti3@plt +; RV64-NEXT: call __umodti3 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/srem-lkk.ll b/llvm/test/CodeGen/RISCV/srem-lkk.ll index 1dcb04382392..7c291bbceedc 100644 --- a/llvm/test/CodeGen/RISCV/srem-lkk.ll +++ b/llvm/test/CodeGen/RISCV/srem-lkk.ll @@ -12,7 +12,7 @@ define i32 @fold_srem_positive_odd(i32 %x) nounwind { ; RV32I-LABEL: fold_srem_positive_odd: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 95 -; RV32I-NEXT: tail __modsi3@plt +; RV32I-NEXT: tail __modsi3 ; ; RV32IM-LABEL: fold_srem_positive_odd: ; RV32IM: # %bb.0: @@ -34,7 +34,7 @@ define i32 @fold_srem_positive_odd(i32 %x) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: li a1, 95 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -63,7 +63,7 @@ define i32 @fold_srem_positive_even(i32 %x) nounwind { ; RV32I-LABEL: fold_srem_positive_even: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 1060 -; RV32I-NEXT: tail __modsi3@plt +; RV32I-NEXT: tail __modsi3 ; ; RV32IM-LABEL: fold_srem_positive_even: ; RV32IM: # %bb.0: @@ -84,7 +84,7 @@ define i32 @fold_srem_positive_even(i32 %x) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: li a1, 1060 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -111,7 +111,7 @@ define i32 @fold_srem_negative_odd(i32 %x) nounwind { ; RV32I-LABEL: fold_srem_negative_odd: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, -723 -; RV32I-NEXT: tail __modsi3@plt +; RV32I-NEXT: tail __modsi3 ; ; RV32IM-LABEL: fold_srem_negative_odd: ; RV32IM: # %bb.0: @@ -132,7 +132,7 @@ define i32 @fold_srem_negative_odd(i32 %x) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: li a1, -723 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -160,7 +160,7 @@ define i32 @fold_srem_negative_even(i32 %x) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, 1048570 ; RV32I-NEXT: addi a1, a1, 1595 -; RV32I-NEXT: tail __modsi3@plt +; RV32I-NEXT: tail __modsi3 ; ; RV32IM-LABEL: fold_srem_negative_even: ; RV32IM: # %bb.0: @@ -183,7 +183,7 @@ define i32 @fold_srem_negative_even(i32 %x) nounwind { ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: lui a1, 1048570 ; RV64I-NEXT: addiw a1, a1, 1595 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -217,11 +217,11 @@ define i32 @combine_srem_sdiv(i32 %x) nounwind { ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 95 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: add a0, s1, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -253,11 +253,11 @@ define i32 @combine_srem_sdiv(i32 %x) nounwind { ; RV64I-NEXT: sext.w s0, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: addw a0, s1, a0 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -391,7 +391,7 @@ define i64 @dont_fold_srem_i64(i64 %x) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 98 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __moddi3@plt +; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -402,7 +402,7 @@ define i64 @dont_fold_srem_i64(i64 %x) nounwind { ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IM-NEXT: li a2, 98 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __moddi3@plt +; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -410,7 +410,7 @@ define i64 @dont_fold_srem_i64(i64 %x) nounwind { ; RV64I-LABEL: dont_fold_srem_i64: ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, 98 -; RV64I-NEXT: tail __moddi3@plt +; RV64I-NEXT: tail __moddi3 ; ; RV64IM-LABEL: dont_fold_srem_i64: ; RV64IM: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll index 122388c1b73e..30ac8de517f6 100644 --- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll @@ -13,7 +13,7 @@ define i1 @test_srem_odd(i29 %X) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: lui a1, 128424 ; RV32-NEXT: addi a1, a1, 331 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: lui a1, 662 ; RV32-NEXT: addi a1, a1, -83 ; RV32-NEXT: add a0, a0, a1 @@ -32,7 +32,7 @@ define i1 @test_srem_odd(i29 %X) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: lui a1, 128424 ; RV64-NEXT: addiw a1, a1, 331 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: lui a1, 662 ; RV64-NEXT: addi a1, a1, -83 ; RV64-NEXT: add a0, a0, a1 @@ -117,7 +117,7 @@ define i1 @test_srem_even(i4 %X) nounwind { ; RV32-NEXT: slli a0, a0, 28 ; RV32-NEXT: srai a0, a0, 28 ; RV32-NEXT: li a1, 6 -; RV32-NEXT: call __modsi3@plt +; RV32-NEXT: call __modsi3 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: seqz a0, a0 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -131,7 +131,7 @@ define i1 @test_srem_even(i4 %X) nounwind { ; RV64-NEXT: slli a0, a0, 60 ; RV64-NEXT: srai a0, a0, 60 ; RV64-NEXT: li a1, 6 -; RV64-NEXT: call __moddi3@plt +; RV64-NEXT: call __moddi3 ; RV64-NEXT: addi a0, a0, -1 ; RV64-NEXT: seqz a0, a0 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -330,21 +330,21 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32-NEXT: srai a1, a1, 31 ; RV32-NEXT: li a2, 6 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __moddi3@plt +; RV32-NEXT: call __moddi3 ; RV32-NEXT: mv s5, a0 ; RV32-NEXT: mv s6, a1 ; RV32-NEXT: li a2, 7 ; RV32-NEXT: mv a0, s2 ; RV32-NEXT: mv a1, s4 ; RV32-NEXT: li a3, 0 -; RV32-NEXT: call __moddi3@plt +; RV32-NEXT: call __moddi3 ; RV32-NEXT: mv s2, a0 ; RV32-NEXT: mv s4, a1 ; RV32-NEXT: li a2, -5 ; RV32-NEXT: li a3, -1 ; RV32-NEXT: mv a0, s1 ; RV32-NEXT: mv a1, s3 -; RV32-NEXT: call __moddi3@plt +; RV32-NEXT: call __moddi3 ; RV32-NEXT: or a2, s5, s6 ; RV32-NEXT: snez a2, a2 ; RV32-NEXT: xori a0, a0, 2 @@ -403,18 +403,18 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64-NEXT: slli a2, a2, 31 ; RV64-NEXT: srai s2, a2, 31 ; RV64-NEXT: li a1, 7 -; RV64-NEXT: call __moddi3@plt +; RV64-NEXT: call __moddi3 ; RV64-NEXT: mv s3, a0 ; RV64-NEXT: li a1, -5 ; RV64-NEXT: mv a0, s1 -; RV64-NEXT: call __moddi3@plt +; RV64-NEXT: call __moddi3 ; RV64-NEXT: mv s1, a0 ; RV64-NEXT: lui a0, 699051 ; RV64-NEXT: addiw a1, a0, -1365 ; RV64-NEXT: slli a0, a1, 32 ; RV64-NEXT: add a1, a1, a0 ; RV64-NEXT: mv a0, s2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: lui a1, %hi(.LCPI3_0) ; RV64-NEXT: ld a1, %lo(.LCPI3_0)(a1) ; RV64-NEXT: add a0, a0, a1 @@ -482,21 +482,21 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32M-NEXT: srai a1, a1, 31 ; RV32M-NEXT: li a2, 6 ; RV32M-NEXT: li a3, 0 -; RV32M-NEXT: call __moddi3@plt +; RV32M-NEXT: call __moddi3 ; RV32M-NEXT: mv s5, a0 ; RV32M-NEXT: mv s6, a1 ; RV32M-NEXT: li a2, 7 ; RV32M-NEXT: mv a0, s2 ; RV32M-NEXT: mv a1, s4 ; RV32M-NEXT: li a3, 0 -; RV32M-NEXT: call __moddi3@plt +; RV32M-NEXT: call __moddi3 ; RV32M-NEXT: mv s2, a0 ; RV32M-NEXT: mv s4, a1 ; RV32M-NEXT: li a2, -5 ; RV32M-NEXT: li a3, -1 ; RV32M-NEXT: mv a0, s1 ; RV32M-NEXT: mv a1, s3 -; RV32M-NEXT: call __moddi3@plt +; RV32M-NEXT: call __moddi3 ; RV32M-NEXT: or a2, s5, s6 ; RV32M-NEXT: snez a2, a2 ; RV32M-NEXT: xori a0, a0, 2 @@ -632,7 +632,7 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32MV-NEXT: srai a1, a1, 31 ; RV32MV-NEXT: li a2, 6 ; RV32MV-NEXT: li a3, 0 -; RV32MV-NEXT: call __moddi3@plt +; RV32MV-NEXT: call __moddi3 ; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32MV-NEXT: vmv.v.x v8, a0 ; RV32MV-NEXT: vslide1down.vx v8, v8, a1 @@ -642,7 +642,7 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32MV-NEXT: mv a0, s2 ; RV32MV-NEXT: mv a1, s4 ; RV32MV-NEXT: li a3, 0 -; RV32MV-NEXT: call __moddi3@plt +; RV32MV-NEXT: call __moddi3 ; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32MV-NEXT: addi a2, sp, 16 ; RV32MV-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload @@ -654,7 +654,7 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32MV-NEXT: li a3, -1 ; RV32MV-NEXT: mv a0, s1 ; RV32MV-NEXT: mv a1, s3 -; RV32MV-NEXT: call __moddi3@plt +; RV32MV-NEXT: call __moddi3 ; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32MV-NEXT: addi a2, sp, 16 ; RV32MV-NEXT: vl2r.v v8, (a2) # Unknown-size Folded Reload diff --git a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll index 3335ca3a34b6..ec6e978c2c68 100644 --- a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll +++ b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll @@ -25,19 +25,19 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: li a1, -124 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 98 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: li a1, -1003 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s3) ; RV32I-NEXT: sh s1, 4(s3) ; RV32I-NEXT: sh s2, 2(s3) @@ -117,19 +117,19 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: li a1, -124 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 98 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a1, -1003 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s3) ; RV64I-NEXT: sh s1, 4(s3) ; RV64I-NEXT: sh s2, 2(s3) @@ -213,19 +213,19 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s3) ; RV32I-NEXT: sh s1, 4(s3) ; RV32I-NEXT: sh s2, 2(s3) @@ -298,19 +298,19 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s3) ; RV64I-NEXT: sh s1, 4(s3) ; RV64I-NEXT: sh s2, 2(s3) @@ -393,35 +393,35 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s4 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s3 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s4 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s3 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __divsi3@plt +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: add a0, s8, a0 ; RV32I-NEXT: add s2, s7, s2 ; RV32I-NEXT: add s3, s6, s3 @@ -510,35 +510,35 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s4 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s3 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s4 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s3 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __divdi3@plt +; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: add a0, s8, a0 ; RV64I-NEXT: add s2, s7, s2 ; RV64I-NEXT: add s3, s6, s3 @@ -640,7 +640,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) nounwind { ; RV32I-NEXT: andi a1, a1, -8 ; RV32I-NEXT: sub s3, a3, a1 ; RV32I-NEXT: li a1, 95 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh s3, 4(s0) ; RV32I-NEXT: sh s2, 2(s0) @@ -713,7 +713,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) nounwind { ; RV64I-NEXT: andi a1, a1, -8 ; RV64I-NEXT: subw s3, a3, a1 ; RV64I-NEXT: li a1, 95 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh s3, 4(s0) ; RV64I-NEXT: sh s2, 2(s0) @@ -779,16 +779,16 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 654 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 23 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s2) ; RV32I-NEXT: sh s1, 4(s2) ; RV32I-NEXT: sh s3, 2(s2) @@ -856,16 +856,16 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s2) ; RV64I-NEXT: sh s1, 4(s2) ; RV64I-NEXT: sh s3, 2(s2) @@ -941,12 +941,12 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind { ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: sub s3, a2, a1 ; RV32I-NEXT: li a1, 23 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __modsi3@plt +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh s2, 4(s0) ; RV32I-NEXT: sh zero, 0(s0) @@ -1013,12 +1013,12 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind { ; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: subw s3, a2, a1 ; RV64I-NEXT: li a1, 23 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh s2, 4(s0) ; RV64I-NEXT: sh zero, 0(s0) @@ -1097,21 +1097,21 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind { ; RV32I-NEXT: li a2, 1 ; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __moddi3@plt +; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s8, a1 ; RV32I-NEXT: li a2, 654 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __moddi3@plt +; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: li a2, 23 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __moddi3@plt +; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: lui a0, 1 @@ -1119,7 +1119,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __moddi3@plt +; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: sw a1, 28(s6) ; RV32I-NEXT: sw a0, 24(s6) ; RV32I-NEXT: sw s3, 20(s6) @@ -1166,21 +1166,21 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind { ; RV32IM-NEXT: li a2, 1 ; RV32IM-NEXT: mv a0, a3 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __moddi3@plt +; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: mv s7, a0 ; RV32IM-NEXT: mv s8, a1 ; RV32IM-NEXT: li a2, 654 ; RV32IM-NEXT: mv a0, s4 ; RV32IM-NEXT: mv a1, s5 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __moddi3@plt +; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: mv s4, a0 ; RV32IM-NEXT: mv s5, a1 ; RV32IM-NEXT: li a2, 23 ; RV32IM-NEXT: mv a0, s2 ; RV32IM-NEXT: mv a1, s3 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __moddi3@plt +; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: mv s2, a0 ; RV32IM-NEXT: mv s3, a1 ; RV32IM-NEXT: lui a0, 1 @@ -1188,7 +1188,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind { ; RV32IM-NEXT: mv a0, s0 ; RV32IM-NEXT: mv a1, s1 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __moddi3@plt +; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: sw a1, 28(s6) ; RV32IM-NEXT: sw a0, 24(s6) ; RV32IM-NEXT: sw s3, 20(s6) @@ -1224,16 +1224,16 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind { ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __moddi3@plt +; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sd a0, 24(s2) ; RV64I-NEXT: sd s1, 16(s2) ; RV64I-NEXT: sd s3, 8(s2) diff --git a/llvm/test/CodeGen/RISCV/stack-protector-target.ll b/llvm/test/CodeGen/RISCV/stack-protector-target.ll index 410b89df1f35..13abde7878f3 100644 --- a/llvm/test/CodeGen/RISCV/stack-protector-target.ll +++ b/llvm/test/CodeGen/RISCV/stack-protector-target.ll @@ -12,7 +12,7 @@ define void @func() sspreq nounwind { ; FUCHSIA-RISCV64-NEXT: ld a0, -16(tp) ; FUCHSIA-RISCV64-NEXT: sd a0, 16(sp) ; FUCHSIA-RISCV64-NEXT: addi a0, sp, 12 -; FUCHSIA-RISCV64-NEXT: call capture@plt +; FUCHSIA-RISCV64-NEXT: call capture ; FUCHSIA-RISCV64-NEXT: ld a0, -16(tp) ; FUCHSIA-RISCV64-NEXT: ld a1, 16(sp) ; FUCHSIA-RISCV64-NEXT: bne a0, a1, .LBB0_2 @@ -21,7 +21,7 @@ define void @func() sspreq nounwind { ; FUCHSIA-RISCV64-NEXT: addi sp, sp, 32 ; FUCHSIA-RISCV64-NEXT: ret ; FUCHSIA-RISCV64-NEXT: .LBB0_2: # %CallStackCheckFailBlk -; FUCHSIA-RISCV64-NEXT: call __stack_chk_fail@plt +; FUCHSIA-RISCV64-NEXT: call __stack_chk_fail %1 = alloca i32, align 4 call void @capture(ptr %1) ret void diff --git a/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll b/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll index f10dfbd313cc..c93153e8f9d1 100644 --- a/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll +++ b/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll @@ -26,7 +26,7 @@ define void @caller(i32 %n) { ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: addi sp, s0, -64 ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload @@ -55,7 +55,7 @@ define void @caller(i32 %n) { ; RV64I-NEXT: sub a0, sp, a0 ; RV64I-NEXT: mv sp, a0 ; RV64I-NEXT: mv a1, s1 -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: addi sp, s0, -64 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/stack-realignment.ll b/llvm/test/CodeGen/RISCV/stack-realignment.ll index d87db54fd5bf..afa8efedbff3 100644 --- a/llvm/test/CodeGen/RISCV/stack-realignment.ll +++ b/llvm/test/CodeGen/RISCV/stack-realignment.ll @@ -19,7 +19,7 @@ define void @caller32() { ; RV32I-NEXT: .cfi_def_cfa s0, 0 ; RV32I-NEXT: andi sp, sp, -32 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: addi sp, s0, -32 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload @@ -38,7 +38,7 @@ define void @caller32() { ; RV64I-NEXT: .cfi_def_cfa s0, 0 ; RV64I-NEXT: andi sp, sp, -32 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: addi sp, s0, -32 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -57,7 +57,7 @@ define void @caller_no_realign32() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -69,7 +69,7 @@ define void @caller_no_realign32() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -91,7 +91,7 @@ define void @caller64() { ; RV32I-NEXT: .cfi_def_cfa s0, 0 ; RV32I-NEXT: andi sp, sp, -64 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: addi sp, s0, -64 ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload @@ -110,7 +110,7 @@ define void @caller64() { ; RV64I-NEXT: .cfi_def_cfa s0, 0 ; RV64I-NEXT: andi sp, sp, -64 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: addi sp, s0, -64 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload @@ -129,7 +129,7 @@ define void @caller_no_realign64() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -141,7 +141,7 @@ define void @caller_no_realign64() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -163,7 +163,7 @@ define void @caller128() { ; RV32I-NEXT: .cfi_def_cfa s0, 0 ; RV32I-NEXT: andi sp, sp, -128 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: addi sp, s0, -128 ; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload @@ -182,7 +182,7 @@ define void @caller128() { ; RV64I-NEXT: .cfi_def_cfa s0, 0 ; RV64I-NEXT: andi sp, sp, -128 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: addi sp, s0, -128 ; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload @@ -201,7 +201,7 @@ define void @caller_no_realign128() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -213,7 +213,7 @@ define void @caller_no_realign128() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -235,7 +235,7 @@ define void @caller256() { ; RV32I-NEXT: .cfi_def_cfa s0, 0 ; RV32I-NEXT: andi sp, sp, -256 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: addi sp, s0, -256 ; RV32I-NEXT: lw ra, 252(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 248(sp) # 4-byte Folded Reload @@ -254,7 +254,7 @@ define void @caller256() { ; RV64I-NEXT: .cfi_def_cfa s0, 0 ; RV64I-NEXT: andi sp, sp, -256 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: addi sp, s0, -256 ; RV64I-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 240(sp) # 8-byte Folded Reload @@ -273,7 +273,7 @@ define void @caller_no_realign256() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -285,7 +285,7 @@ define void @caller_no_realign256() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -307,7 +307,7 @@ define void @caller512() { ; RV32I-NEXT: .cfi_def_cfa s0, 0 ; RV32I-NEXT: andi sp, sp, -512 ; RV32I-NEXT: addi a0, sp, 512 -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: addi sp, s0, -1024 ; RV32I-NEXT: lw ra, 1020(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 1016(sp) # 4-byte Folded Reload @@ -326,7 +326,7 @@ define void @caller512() { ; RV64I-NEXT: .cfi_def_cfa s0, 0 ; RV64I-NEXT: andi sp, sp, -512 ; RV64I-NEXT: addi a0, sp, 512 -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: addi sp, s0, -1024 ; RV64I-NEXT: ld ra, 1016(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 1008(sp) # 8-byte Folded Reload @@ -345,7 +345,7 @@ define void @caller_no_realign512() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -357,7 +357,7 @@ define void @caller_no_realign512() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -380,7 +380,7 @@ define void @caller1024() { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: andi sp, sp, -1024 ; RV32I-NEXT: addi a0, sp, 1024 -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: addi sp, s0, -2048 ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload @@ -401,7 +401,7 @@ define void @caller1024() { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: andi sp, sp, -1024 ; RV64I-NEXT: addi a0, sp, 1024 -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: addi sp, s0, -2048 ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload @@ -421,7 +421,7 @@ define void @caller_no_realign1024() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -433,7 +433,7 @@ define void @caller_no_realign1024() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -458,7 +458,7 @@ define void @caller2048() { ; RV32I-NEXT: andi sp, sp, -2048 ; RV32I-NEXT: addi a0, sp, 2047 ; RV32I-NEXT: addi a0, a0, 1 -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: sub sp, s0, a0 ; RV32I-NEXT: addi sp, sp, 2032 @@ -483,7 +483,7 @@ define void @caller2048() { ; RV64I-NEXT: andi sp, sp, -2048 ; RV64I-NEXT: addi a0, sp, 2047 ; RV64I-NEXT: addi a0, a0, 1 -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: sub sp, s0, a0 ; RV64I-NEXT: addi sp, sp, 2032 @@ -505,7 +505,7 @@ define void @caller_no_realign2048() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -517,7 +517,7 @@ define void @caller_no_realign2048() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -544,7 +544,7 @@ define void @caller4096() { ; RV32I-NEXT: slli sp, a0, 12 ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: add a0, sp, a0 -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lui a0, 2 ; RV32I-NEXT: sub sp, s0, a0 ; RV32I-NEXT: addi a0, a0, -2032 @@ -571,7 +571,7 @@ define void @caller4096() { ; RV64I-NEXT: slli sp, a0, 12 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: add a0, sp, a0 -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: lui a0, 2 ; RV64I-NEXT: sub sp, s0, a0 ; RV64I-NEXT: addiw a0, a0, -2032 @@ -593,7 +593,7 @@ define void @caller_no_realign4096() "no-realign-stack" { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: mv a0, sp -; RV32I-NEXT: call callee@plt +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -605,7 +605,7 @@ define void @caller_no_realign4096() "no-realign-stack" { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: mv a0, sp -; RV64I-NEXT: call callee@plt +; RV64I-NEXT: call callee ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/stack-slot-size.ll b/llvm/test/CodeGen/RISCV/stack-slot-size.ll index ab6bd20e2f22..1388eaac3a67 100644 --- a/llvm/test/CodeGen/RISCV/stack-slot-size.ll +++ b/llvm/test/CodeGen/RISCV/stack-slot-size.ll @@ -26,7 +26,7 @@ define i32 @caller129() nounwind { ; RV32I-NEXT: sw zero, 4(sp) ; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: sw zero, 0(sp) -; RV32I-NEXT: call callee129@plt +; RV32I-NEXT: call callee129 ; RV32I-NEXT: lw a0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 @@ -42,7 +42,7 @@ define i32 @caller129() nounwind { ; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: sd zero, 0(sp) -; RV64I-NEXT: call callee129@plt +; RV64I-NEXT: call callee129 ; RV64I-NEXT: lw a0, 36(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48 @@ -67,7 +67,7 @@ define i32 @caller160() nounwind { ; RV32I-NEXT: sw zero, 4(sp) ; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: sw zero, 0(sp) -; RV32I-NEXT: call callee160@plt +; RV32I-NEXT: call callee160 ; RV32I-NEXT: lw a0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 @@ -83,7 +83,7 @@ define i32 @caller160() nounwind { ; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: sd zero, 0(sp) -; RV64I-NEXT: call callee160@plt +; RV64I-NEXT: call callee160 ; RV64I-NEXT: lw a0, 36(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48 @@ -109,7 +109,7 @@ define i32 @caller161() nounwind { ; RV32I-NEXT: sw zero, 4(sp) ; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: sw zero, 0(sp) -; RV32I-NEXT: call callee161@plt +; RV32I-NEXT: call callee161 ; RV32I-NEXT: lw a0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 @@ -125,7 +125,7 @@ define i32 @caller161() nounwind { ; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: sd zero, 0(sp) -; RV64I-NEXT: call callee161@plt +; RV64I-NEXT: call callee161 ; RV64I-NEXT: lw a0, 36(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48 diff --git a/llvm/test/CodeGen/RISCV/stack-store-check.ll b/llvm/test/CodeGen/RISCV/stack-store-check.ll index 651df94bab49..91cfb2a4cef7 100644 --- a/llvm/test/CodeGen/RISCV/stack-store-check.ll +++ b/llvm/test/CodeGen/RISCV/stack-store-check.ll @@ -44,7 +44,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 600 ; CHECK-NEXT: addi a2, sp, 584 ; CHECK-NEXT: sw s6, 584(sp) -; CHECK-NEXT: call __subtf3@plt +; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: lw s1, 616(sp) ; CHECK-NEXT: lw s2, 620(sp) ; CHECK-NEXT: lw s3, 624(sp) @@ -60,7 +60,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 552 ; CHECK-NEXT: addi a2, sp, 536 ; CHECK-NEXT: sw s1, 552(sp) -; CHECK-NEXT: call __subtf3@plt +; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: lw a0, 568(sp) ; CHECK-NEXT: sw a0, 40(sp) # 4-byte Folded Spill ; CHECK-NEXT: lw a0, 572(sp) @@ -80,7 +80,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 504 ; CHECK-NEXT: addi a2, sp, 488 ; CHECK-NEXT: sw s6, 504(sp) -; CHECK-NEXT: call __addtf3@plt +; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: lw s9, 520(sp) ; CHECK-NEXT: lw s11, 524(sp) ; CHECK-NEXT: lw s5, 528(sp) @@ -106,7 +106,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 312 ; CHECK-NEXT: addi a2, sp, 296 ; CHECK-NEXT: sw s1, 312(sp) -; CHECK-NEXT: call __multf3@plt +; CHECK-NEXT: call __multf3 ; CHECK-NEXT: lw a0, 328(sp) ; CHECK-NEXT: sw a0, 44(sp) # 4-byte Folded Spill ; CHECK-NEXT: lw a0, 332(sp) @@ -126,7 +126,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 456 ; CHECK-NEXT: addi a2, sp, 440 ; CHECK-NEXT: sw s9, 440(sp) -; CHECK-NEXT: call __addtf3@plt +; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: lw a3, 472(sp) ; CHECK-NEXT: lw a0, 476(sp) ; CHECK-NEXT: lw a1, 480(sp) @@ -142,7 +142,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 408 ; CHECK-NEXT: addi a2, sp, 392 ; CHECK-NEXT: sw a3, 392(sp) -; CHECK-NEXT: call __subtf3@plt +; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: lw a0, 424(sp) ; CHECK-NEXT: lw a1, 436(sp) ; CHECK-NEXT: lw a2, 432(sp) @@ -171,7 +171,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a2, sp, 200 ; CHECK-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; CHECK-NEXT: sw s0, 216(sp) -; CHECK-NEXT: call __multf3@plt +; CHECK-NEXT: call __multf3 ; CHECK-NEXT: lw s1, 232(sp) ; CHECK-NEXT: lw a0, 236(sp) ; CHECK-NEXT: sw a0, 0(sp) # 4-byte Folded Spill @@ -189,7 +189,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 360 ; CHECK-NEXT: addi a2, sp, 344 ; CHECK-NEXT: sw s9, 360(sp) -; CHECK-NEXT: call __multf3@plt +; CHECK-NEXT: call __multf3 ; CHECK-NEXT: lw a0, 376(sp) ; CHECK-NEXT: lw a1, 388(sp) ; CHECK-NEXT: lw a2, 384(sp) @@ -215,7 +215,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a2, sp, 248 ; CHECK-NEXT: lw a3, 44(sp) # 4-byte Folded Reload ; CHECK-NEXT: sw a3, 264(sp) -; CHECK-NEXT: call __subtf3@plt +; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: lw a0, 280(sp) ; CHECK-NEXT: lw a1, 292(sp) ; CHECK-NEXT: lw a2, 288(sp) @@ -237,7 +237,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 168 ; CHECK-NEXT: addi a2, sp, 152 ; CHECK-NEXT: sw s1, 168(sp) -; CHECK-NEXT: call __addtf3@plt +; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: lw a0, 184(sp) ; CHECK-NEXT: lw a1, 196(sp) ; CHECK-NEXT: lw a2, 192(sp) @@ -259,7 +259,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a2, sp, 104 ; CHECK-NEXT: lw a3, 52(sp) # 4-byte Folded Reload ; CHECK-NEXT: sw a3, 120(sp) -; CHECK-NEXT: call __multf3@plt +; CHECK-NEXT: call __multf3 ; CHECK-NEXT: lw a3, 136(sp) ; CHECK-NEXT: lw a0, 140(sp) ; CHECK-NEXT: lw a1, 144(sp) @@ -276,7 +276,7 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: addi a1, sp, 72 ; CHECK-NEXT: addi a2, sp, 56 ; CHECK-NEXT: sw a3, 72(sp) -; CHECK-NEXT: call __addtf3@plt +; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: lw a0, 96(sp) ; CHECK-NEXT: lw a1, 100(sp) ; CHECK-NEXT: lw a2, 88(sp) diff --git a/llvm/test/CodeGen/RISCV/tls-models.ll b/llvm/test/CodeGen/RISCV/tls-models.ll index d9b37cb0c7c2..c2ed44073baa 100644 --- a/llvm/test/CodeGen/RISCV/tls-models.ll +++ b/llvm/test/CodeGen/RISCV/tls-models.ll @@ -26,7 +26,7 @@ define ptr @f1() nounwind { ; RV32-PIC-NEXT: .Lpcrel_hi0: ; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified) ; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0) -; RV32-PIC-NEXT: call __tls_get_addr@plt +; RV32-PIC-NEXT: call __tls_get_addr ; RV32-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-PIC-NEXT: addi sp, sp, 16 ; RV32-PIC-NEXT: ret @@ -38,7 +38,7 @@ define ptr @f1() nounwind { ; RV64-PIC-NEXT: .Lpcrel_hi0: ; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified) ; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0) -; RV64-PIC-NEXT: call __tls_get_addr@plt +; RV64-PIC-NEXT: call __tls_get_addr ; RV64-PIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-PIC-NEXT: addi sp, sp, 16 ; RV64-PIC-NEXT: ret @@ -73,7 +73,7 @@ define ptr @f2() nounwind { ; RV32-PIC-NEXT: .Lpcrel_hi1: ; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld) ; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1) -; RV32-PIC-NEXT: call __tls_get_addr@plt +; RV32-PIC-NEXT: call __tls_get_addr ; RV32-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-PIC-NEXT: addi sp, sp, 16 ; RV32-PIC-NEXT: ret @@ -85,7 +85,7 @@ define ptr @f2() nounwind { ; RV64-PIC-NEXT: .Lpcrel_hi1: ; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld) ; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1) -; RV64-PIC-NEXT: call __tls_get_addr@plt +; RV64-PIC-NEXT: call __tls_get_addr ; RV64-PIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-PIC-NEXT: addi sp, sp, 16 ; RV64-PIC-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll b/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll index 0772109a5525..22c0b798e146 100644 --- a/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll +++ b/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll @@ -915,7 +915,7 @@ define i32 @in_multiuse_A(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind { ; RV32-NEXT: xor a0, a0, a1 ; RV32-NEXT: and s1, a0, a3 ; RV32-NEXT: mv a0, s1 -; RV32-NEXT: call use32@plt +; RV32-NEXT: call use32 ; RV32-NEXT: xor a0, s1, s0 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -933,7 +933,7 @@ define i32 @in_multiuse_A(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind { ; RV64-NEXT: xor a0, a0, a1 ; RV64-NEXT: and s1, a0, a3 ; RV64-NEXT: mv a0, s1 -; RV64-NEXT: call use32@plt +; RV64-NEXT: call use32 ; RV64-NEXT: xor a0, s1, s0 ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -957,7 +957,7 @@ define i32 @in_multiuse_B(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind { ; RV32-NEXT: mv s0, a1 ; RV32-NEXT: xor a0, a0, a1 ; RV32-NEXT: and s1, a0, a3 -; RV32-NEXT: call use32@plt +; RV32-NEXT: call use32 ; RV32-NEXT: xor a0, s1, s0 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -974,7 +974,7 @@ define i32 @in_multiuse_B(i32 %x, i32 %y, i32 %z, i32 %mask) nounwind { ; RV64-NEXT: mv s0, a1 ; RV64-NEXT: xor a0, a0, a1 ; RV64-NEXT: and s1, a0, a3 -; RV64-NEXT: call use32@plt +; RV64-NEXT: call use32 ; RV64-NEXT: xor a0, s1, s0 ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/urem-lkk.ll b/llvm/test/CodeGen/RISCV/urem-lkk.ll index 1b2cc1398ec1..f83a933c0b5c 100644 --- a/llvm/test/CodeGen/RISCV/urem-lkk.ll +++ b/llvm/test/CodeGen/RISCV/urem-lkk.ll @@ -12,7 +12,7 @@ define i32 @fold_urem_positive_odd(i32 %x) nounwind { ; RV32I-LABEL: fold_urem_positive_odd: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 95 -; RV32I-NEXT: tail __umodsi3@plt +; RV32I-NEXT: tail __umodsi3 ; ; RV32IM-LABEL: fold_urem_positive_odd: ; RV32IM: # %bb.0: @@ -35,7 +35,7 @@ define i32 @fold_urem_positive_odd(i32 %x) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: li a1, 95 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -65,7 +65,7 @@ define i32 @fold_urem_positive_even(i32 %x) nounwind { ; RV32I-LABEL: fold_urem_positive_even: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 1060 -; RV32I-NEXT: tail __umodsi3@plt +; RV32I-NEXT: tail __umodsi3 ; ; RV32IM-LABEL: fold_urem_positive_even: ; RV32IM: # %bb.0: @@ -85,7 +85,7 @@ define i32 @fold_urem_positive_even(i32 %x) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: li a1, 1060 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -117,11 +117,11 @@ define i32 @combine_urem_udiv(i32 %x) nounwind { ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 95 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: add a0, s1, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -154,11 +154,11 @@ define i32 @combine_urem_udiv(i32 %x) nounwind { ; RV64I-NEXT: srli s0, a0, 32 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: add a0, s1, a0 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -226,7 +226,7 @@ define i64 @dont_fold_urem_i64(i64 %x) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: li a2, 98 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __umoddi3@plt +; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -237,7 +237,7 @@ define i64 @dont_fold_urem_i64(i64 %x) nounwind { ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IM-NEXT: li a2, 98 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __umoddi3@plt +; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -245,7 +245,7 @@ define i64 @dont_fold_urem_i64(i64 %x) nounwind { ; RV64I-LABEL: dont_fold_urem_i64: ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, 98 -; RV64I-NEXT: tail __umoddi3@plt +; RV64I-NEXT: tail __umoddi3 ; ; RV64IM-LABEL: dont_fold_urem_i64: ; RV64IM: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll index f629c0d17891..4544cbaf8521 100644 --- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -13,7 +13,7 @@ define i1 @test_urem_odd(i13 %X) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: lui a1, 1 ; RV32-NEXT: addi a1, a1, -819 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a0, a0, 19 ; RV32-NEXT: srli a0, a0, 19 ; RV32-NEXT: sltiu a0, a0, 1639 @@ -27,7 +27,7 @@ define i1 @test_urem_odd(i13 %X) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: lui a1, 1 ; RV64-NEXT: addiw a1, a1, -819 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a0, a0, 51 ; RV64-NEXT: srli a0, a0, 51 ; RV64-NEXT: sltiu a0, a0, 1639 @@ -86,7 +86,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: lui a1, 28087 ; RV32-NEXT: addi a1, a1, -585 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a1, a0, 26 ; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: srli a0, a0, 6 @@ -106,7 +106,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: lui a1, 28087 ; RV64-NEXT: addiw a1, a1, -585 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a1, a0, 26 ; RV64-NEXT: slli a0, a0, 37 ; RV64-NEXT: srli a0, a0, 38 @@ -259,7 +259,7 @@ define i1 @test_urem_negative_odd(i9 %X) nounwind { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: li a1, 307 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: andi a0, a0, 511 ; RV32-NEXT: sltiu a0, a0, 2 ; RV32-NEXT: xori a0, a0, 1 @@ -272,7 +272,7 @@ define i1 @test_urem_negative_odd(i9 %X) nounwind { ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: li a1, 307 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: andi a0, a0, 511 ; RV64-NEXT: sltiu a0, a0, 2 ; RV64-NEXT: xori a0, a0, 1 @@ -338,7 +338,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32-NEXT: srli s2, a1, 11 ; RV32-NEXT: andi a0, a1, 2047 ; RV32-NEXT: li a1, 683 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: slli a1, a0, 10 ; RV32-NEXT: slli a0, a0, 21 ; RV32-NEXT: srli a0, a0, 22 @@ -347,13 +347,13 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32-NEXT: sltiu s3, a0, 342 ; RV32-NEXT: li a1, 819 ; RV32-NEXT: mv a0, s1 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: addi a0, a0, -1638 ; RV32-NEXT: andi a0, a0, 2047 ; RV32-NEXT: sltiu s1, a0, 2 ; RV32-NEXT: li a1, 1463 ; RV32-NEXT: mv a0, s2 -; RV32-NEXT: call __mulsi3@plt +; RV32-NEXT: call __mulsi3 ; RV32-NEXT: addi a0, a0, -1463 ; RV32-NEXT: andi a0, a0, 2047 ; RV32-NEXT: sltiu a0, a0, 293 @@ -395,7 +395,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64-NEXT: srli s2, a0, 11 ; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: li a1, 683 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: slli a1, a0, 10 ; RV64-NEXT: slli a0, a0, 53 ; RV64-NEXT: srli a0, a0, 54 @@ -404,13 +404,13 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64-NEXT: sltiu s3, a0, 342 ; RV64-NEXT: li a1, 1463 ; RV64-NEXT: mv a0, s2 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: addi a0, a0, -1463 ; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: sltiu s2, a0, 293 ; RV64-NEXT: li a1, 819 ; RV64-NEXT: mv a0, s1 -; RV64-NEXT: call __muldi3@plt +; RV64-NEXT: call __muldi3 ; RV64-NEXT: addi a0, a0, -1638 ; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: sltiu a0, a0, 2 diff --git a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll index 32aca29d16e9..eea8e64f2ddd 100644 --- a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll +++ b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll @@ -26,19 +26,19 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: li a1, 124 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 98 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: li a1, 1003 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: sh a0, 6(s3) ; RV32I-NEXT: sh s1, 4(s3) ; RV32I-NEXT: sh s2, 2(s3) @@ -104,19 +104,19 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: li a1, 124 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 98 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a1, 1003 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: sh a0, 6(s3) ; RV64I-NEXT: sh s1, 4(s3) ; RV64I-NEXT: sh s2, 2(s3) @@ -186,19 +186,19 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: sh a0, 6(s3) ; RV32I-NEXT: sh s1, 4(s3) ; RV32I-NEXT: sh s2, 2(s3) @@ -255,19 +255,19 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: sh a0, 6(s3) ; RV64I-NEXT: sh s1, 4(s3) ; RV64I-NEXT: sh s2, 2(s3) @@ -334,35 +334,35 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s4 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s3 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s4 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s3 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s2 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __udivsi3@plt +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: add a0, s8, a0 ; RV32I-NEXT: add s2, s7, s2 ; RV32I-NEXT: add s3, s6, s3 @@ -435,35 +435,35 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s4 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s3 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s4 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s3 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s2 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __udivdi3@plt +; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: add a0, s8, a0 ; RV64I-NEXT: add s2, s7, s2 ; RV64I-NEXT: add s3, s6, s3 @@ -538,7 +538,7 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: andi a1, s3, 63 ; RV32I-NEXT: andi a2, s2, 31 ; RV32I-NEXT: andi s1, s1, 7 @@ -590,7 +590,7 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: andi a1, s3, 63 ; RV64I-NEXT: andi a2, s2, 31 ; RV64I-NEXT: andi s1, s1, 7 @@ -646,16 +646,16 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind { ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: li a1, 654 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: li a1, 23 ; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __umodsi3@plt +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: sh a0, 6(s2) ; RV32I-NEXT: sh s1, 4(s2) ; RV32I-NEXT: sh s3, 2(s2) @@ -712,16 +712,16 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind { ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: sh a0, 6(s2) ; RV64I-NEXT: sh s1, 4(s2) ; RV64I-NEXT: sh s3, 2(s2) @@ -803,21 +803,21 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind { ; RV32I-NEXT: li a2, 1 ; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __umoddi3@plt +; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s8, a1 ; RV32I-NEXT: li a2, 654 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __umoddi3@plt +; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: li a2, 23 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __umoddi3@plt +; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: lui a0, 1 @@ -825,7 +825,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: call __umoddi3@plt +; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: sw a1, 28(s6) ; RV32I-NEXT: sw a0, 24(s6) ; RV32I-NEXT: sw s3, 20(s6) @@ -872,21 +872,21 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind { ; RV32IM-NEXT: li a2, 1 ; RV32IM-NEXT: mv a0, a3 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __umoddi3@plt +; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: mv s7, a0 ; RV32IM-NEXT: mv s8, a1 ; RV32IM-NEXT: li a2, 654 ; RV32IM-NEXT: mv a0, s4 ; RV32IM-NEXT: mv a1, s5 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __umoddi3@plt +; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: mv s4, a0 ; RV32IM-NEXT: mv s5, a1 ; RV32IM-NEXT: li a2, 23 ; RV32IM-NEXT: mv a0, s2 ; RV32IM-NEXT: mv a1, s3 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __umoddi3@plt +; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: mv s2, a0 ; RV32IM-NEXT: mv s3, a1 ; RV32IM-NEXT: lui a0, 1 @@ -894,7 +894,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind { ; RV32IM-NEXT: mv a0, s0 ; RV32IM-NEXT: mv a1, s1 ; RV32IM-NEXT: li a3, 0 -; RV32IM-NEXT: call __umoddi3@plt +; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: sw a1, 28(s6) ; RV32IM-NEXT: sw a0, 24(s6) ; RV32IM-NEXT: sw s3, 20(s6) @@ -930,16 +930,16 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind { ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: mv a0, a2 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __umoddi3@plt +; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: sd a0, 24(s2) ; RV64I-NEXT: sd s1, 16(s2) ; RV64I-NEXT: sd s3, 8(s2) diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll index 67d1bfac4d61..8adce4bc466d 100644 --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -269,7 +269,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -16 ; ILP32-ILP32F-FPELIM-NEXT: sub a0, sp, a0 ; ILP32-ILP32F-FPELIM-NEXT: mv sp, a0 -; ILP32-ILP32F-FPELIM-NEXT: call notdead@plt +; ILP32-ILP32F-FPELIM-NEXT: call notdead ; ILP32-ILP32F-FPELIM-NEXT: mv a0, s1 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, s0, -16 ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -299,7 +299,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -16 ; ILP32-ILP32F-WITHFP-NEXT: sub a0, sp, a0 ; ILP32-ILP32F-WITHFP-NEXT: mv sp, a0 -; ILP32-ILP32F-WITHFP-NEXT: call notdead@plt +; ILP32-ILP32F-WITHFP-NEXT: call notdead ; ILP32-ILP32F-WITHFP-NEXT: mv a0, s1 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, s0, -16 ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -329,7 +329,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub a0, sp, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv sp, a0 -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead@plt +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, s1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, s0, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -361,7 +361,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: sub a0, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv sp, a0 -; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead@plt +; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead ; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, s1 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, s0, -32 ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -393,7 +393,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -16 ; LP64-LP64F-LP64D-WITHFP-NEXT: sub a0, sp, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv sp, a0 -; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead@plt +; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, s0, -32 ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -419,7 +419,7 @@ define void @va1_caller() nounwind { ; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 ; ILP32-ILP32F-FPELIM-NEXT: li a4, 2 ; ILP32-ILP32F-FPELIM-NEXT: li a2, 0 -; ILP32-ILP32F-FPELIM-NEXT: call va1@plt +; ILP32-ILP32F-FPELIM-NEXT: call va1 ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: ret @@ -433,7 +433,7 @@ define void @va1_caller() nounwind { ; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 ; ILP32-ILP32F-WITHFP-NEXT: li a4, 2 ; ILP32-ILP32F-WITHFP-NEXT: li a2, 0 -; ILP32-ILP32F-WITHFP-NEXT: call va1@plt +; ILP32-ILP32F-WITHFP-NEXT: call va1 ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 @@ -446,7 +446,7 @@ define void @va1_caller() nounwind { ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: li a4, 2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: li a2, 0 -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1@plt +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret @@ -458,7 +458,7 @@ define void @va1_caller() nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: li a1, 1023 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 52 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a2, 2 -; LP64-LP64F-LP64D-FPELIM-NEXT: call va1@plt +; LP64-LP64F-LP64D-FPELIM-NEXT: call va1 ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret @@ -472,7 +472,7 @@ define void @va1_caller() nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: li a1, 1023 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 52 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a2, 2 -; LP64-LP64F-LP64D-WITHFP-NEXT: call va1@plt +; LP64-LP64F-LP64D-WITHFP-NEXT: call va1 ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 @@ -725,7 +725,7 @@ define void @va2_caller() nounwind { ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 ; ILP32-ILP32F-FPELIM-NEXT: li a2, 0 -; ILP32-ILP32F-FPELIM-NEXT: call va2@plt +; ILP32-ILP32F-FPELIM-NEXT: call va2 ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: ret @@ -738,7 +738,7 @@ define void @va2_caller() nounwind { ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 ; ILP32-ILP32F-WITHFP-NEXT: li a2, 0 -; ILP32-ILP32F-WITHFP-NEXT: call va2@plt +; ILP32-ILP32F-WITHFP-NEXT: call va2 ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 @@ -750,7 +750,7 @@ define void @va2_caller() nounwind { ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: li a2, 0 -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2@plt +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret @@ -761,7 +761,7 @@ define void @va2_caller() nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-FPELIM-NEXT: li a1, 1023 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 52 -; LP64-LP64F-LP64D-FPELIM-NEXT: call va2@plt +; LP64-LP64F-LP64D-FPELIM-NEXT: call va2 ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret @@ -774,7 +774,7 @@ define void @va2_caller() nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a1, 1023 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 52 -; LP64-LP64F-LP64D-WITHFP-NEXT: call va2@plt +; LP64-LP64F-LP64D-WITHFP-NEXT: call va2 ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 @@ -1040,7 +1040,7 @@ define void @va3_caller() nounwind { ; ILP32-ILP32F-FPELIM-NEXT: lui a5, 262144 ; ILP32-ILP32F-FPELIM-NEXT: li a2, 0 ; ILP32-ILP32F-FPELIM-NEXT: li a4, 0 -; ILP32-ILP32F-FPELIM-NEXT: call va3@plt +; ILP32-ILP32F-FPELIM-NEXT: call va3 ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: ret @@ -1056,7 +1056,7 @@ define void @va3_caller() nounwind { ; ILP32-ILP32F-WITHFP-NEXT: lui a5, 262144 ; ILP32-ILP32F-WITHFP-NEXT: li a2, 0 ; ILP32-ILP32F-WITHFP-NEXT: li a4, 0 -; ILP32-ILP32F-WITHFP-NEXT: call va3@plt +; ILP32-ILP32F-WITHFP-NEXT: call va3 ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 @@ -1071,7 +1071,7 @@ define void @va3_caller() nounwind { ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 262144 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: li a2, 0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: li a4, 0 -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3@plt +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret @@ -1084,7 +1084,7 @@ define void @va3_caller() nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a2, 62 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a0, 2 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a1, 1111 -; LP64-LP64F-LP64D-FPELIM-NEXT: call va3@plt +; LP64-LP64F-LP64D-FPELIM-NEXT: call va3 ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret @@ -1099,7 +1099,7 @@ define void @va3_caller() nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 62 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a0, 2 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a1, 1111 -; LP64-LP64F-LP64D-WITHFP-NEXT: call va3@plt +; LP64-LP64F-LP64D-WITHFP-NEXT: call va3 ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 @@ -1127,7 +1127,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 24 ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 0(sp) -; ILP32-ILP32F-FPELIM-NEXT: call notdead@plt +; ILP32-ILP32F-FPELIM-NEXT: call notdead ; ILP32-ILP32F-FPELIM-NEXT: lw a0, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 3 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 @@ -1170,7 +1170,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -20(s0) -; ILP32-ILP32F-WITHFP-NEXT: call notdead@plt +; ILP32-ILP32F-WITHFP-NEXT: call notdead ; ILP32-ILP32F-WITHFP-NEXT: lw a0, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 3 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 @@ -1212,7 +1212,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 24 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 0(sp) -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead@plt +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 3 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 @@ -1253,7 +1253,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 48 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 0(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead@plt +; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 3 ; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 @@ -1296,7 +1296,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -40(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead@plt +; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 3 ; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 @@ -1384,7 +1384,7 @@ define void @va5_aligned_stack_caller() nounwind { ; ILP32-ILP32F-FPELIM-NEXT: li a4, 13 ; ILP32-ILP32F-FPELIM-NEXT: li a7, 4 ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 32(sp) -; ILP32-ILP32F-FPELIM-NEXT: call va5_aligned_stack_callee@plt +; ILP32-ILP32F-FPELIM-NEXT: call va5_aligned_stack_callee ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 64 ; ILP32-ILP32F-FPELIM-NEXT: ret @@ -1429,7 +1429,7 @@ define void @va5_aligned_stack_caller() nounwind { ; ILP32-ILP32F-WITHFP-NEXT: li a4, 13 ; ILP32-ILP32F-WITHFP-NEXT: li a7, 4 ; ILP32-ILP32F-WITHFP-NEXT: sw a5, -32(s0) -; ILP32-ILP32F-WITHFP-NEXT: call va5_aligned_stack_callee@plt +; ILP32-ILP32F-WITHFP-NEXT: call va5_aligned_stack_callee ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64 @@ -1473,7 +1473,7 @@ define void @va5_aligned_stack_caller() nounwind { ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: li a4, 13 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: li a7, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 32(sp) -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va5_aligned_stack_callee@plt +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va5_aligned_stack_callee ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 64 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret @@ -1503,7 +1503,7 @@ define void @va5_aligned_stack_caller() nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: li a5, 13 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a7, 14 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd t0, 0(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: call va5_aligned_stack_callee@plt +; LP64-LP64F-LP64D-FPELIM-NEXT: call va5_aligned_stack_callee ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 48 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret @@ -1535,7 +1535,7 @@ define void @va5_aligned_stack_caller() nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: li a5, 13 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a7, 14 ; LP64-LP64F-LP64D-WITHFP-NEXT: sd t0, 0(sp) -; LP64-LP64F-LP64D-WITHFP-NEXT: call va5_aligned_stack_callee@plt +; LP64-LP64F-LP64D-WITHFP-NEXT: call va5_aligned_stack_callee ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 48 diff --git a/llvm/test/CodeGen/RISCV/vlenb.ll b/llvm/test/CodeGen/RISCV/vlenb.ll index 6ce7f5372623..1d6c1b5d1acb 100644 --- a/llvm/test/CodeGen/RISCV/vlenb.ll +++ b/llvm/test/CodeGen/RISCV/vlenb.ll @@ -53,7 +53,7 @@ define i32 @sink_to_use_call() { ; CHECK-NEXT: .cfi_offset ra, -4 ; CHECK-NEXT: .cfi_offset s0, -8 ; CHECK-NEXT: csrr s0, vlenb -; CHECK-NEXT: call unknown@plt +; CHECK-NEXT: call unknown ; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -75,7 +75,7 @@ define void @machine_licm() { ; CHECK-NEXT: .LBB4_1: # %loop ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: call use@plt +; CHECK-NEXT: call use ; CHECK-NEXT: j .LBB4_1 entry: br label %loop diff --git a/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll b/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll index 74bf1a8929cb..6d1521c719ed 100644 --- a/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll +++ b/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll @@ -218,11 +218,11 @@ define i1 @flo(float %c, float %a, float %b) { ; CHECK-RV64I-NEXT: mv s1, a0 ; CHECK-RV64I-NEXT: mv a0, a1 ; CHECK-RV64I-NEXT: mv a1, s1 -; CHECK-RV64I-NEXT: call __gesf2@plt +; CHECK-RV64I-NEXT: call __gesf2 ; CHECK-RV64I-NEXT: mv s2, a0 ; CHECK-RV64I-NEXT: mv a0, s0 ; CHECK-RV64I-NEXT: mv a1, s1 -; CHECK-RV64I-NEXT: call __gesf2@plt +; CHECK-RV64I-NEXT: call __gesf2 ; CHECK-RV64I-NEXT: or a0, s2, a0 ; CHECK-RV64I-NEXT: slti a0, a0, 0 ; CHECK-RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -264,11 +264,11 @@ define i1 @dlo(double %c, double %a, double %b) { ; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a1, s1 -; CHECK-NEXT: call __gedf2@plt +; CHECK-NEXT: call __gedf2 ; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a1, s1 -; CHECK-NEXT: call __gedf2@plt +; CHECK-NEXT: call __gedf2 ; CHECK-NEXT: or a0, s2, a0 ; CHECK-NEXT: slti a0, a0, 0 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/zcmp-with-float.ll b/llvm/test/CodeGen/RISCV/zcmp-with-float.ll index 72213019b8c8..93f95e9709b6 100644 --- a/llvm/test/CodeGen/RISCV/zcmp-with-float.ll +++ b/llvm/test/CodeGen/RISCV/zcmp-with-float.ll @@ -15,7 +15,7 @@ define float @foo(float %arg) { ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset fs0, -20 ; RV32-NEXT: fmv.s fs0, fa0 -; RV32-NEXT: call callee@plt +; RV32-NEXT: call callee ; RV32-NEXT: fmv.s fa0, fs0 ; RV32-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: cm.popret {ra}, 32 @@ -28,7 +28,7 @@ define float @foo(float %arg) { ; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset fs0, -20 ; RV64-NEXT: fmv.s fs0, fa0 -; RV64-NEXT: call callee@plt +; RV64-NEXT: call callee ; RV64-NEXT: fmv.s fa0, fs0 ; RV64-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload ; RV64-NEXT: cm.popret {ra}, 32 @@ -48,12 +48,12 @@ define void @foo2(i32 %x, float %y) { ; RV32-NEXT: .cfi_offset fs0, -20 ; RV32-NEXT: fmv.s fs0, fa0 ; RV32-NEXT: mv s0, a0 -; RV32-NEXT: call bar@plt +; RV32-NEXT: call bar ; RV32-NEXT: mv a0, s0 ; RV32-NEXT: fmv.s fa0, fs0 ; RV32-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: cm.pop {ra, s0}, 32 -; RV32-NEXT: tail func@plt +; RV32-NEXT: tail func ; ; RV64-LABEL: foo2: ; RV64: # %bb.0: # %entry @@ -65,12 +65,12 @@ define void @foo2(i32 %x, float %y) { ; RV64-NEXT: .cfi_offset fs0, -20 ; RV64-NEXT: fmv.s fs0, fa0 ; RV64-NEXT: mv s0, a0 -; RV64-NEXT: call bar@plt +; RV64-NEXT: call bar ; RV64-NEXT: mv a0, s0 ; RV64-NEXT: fmv.s fa0, fs0 ; RV64-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload ; RV64-NEXT: cm.pop {ra, s0}, 32 -; RV64-NEXT: tail func@plt +; RV64-NEXT: tail func entry: tail call void @bar() tail call void @func(i32 %x, float %y) diff --git a/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll index 4d573d672bbd..348ca8e52962 100644 --- a/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll +++ b/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll @@ -68,7 +68,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call floorf@plt +; RV32IZFH-NEXT: call floorf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -79,7 +79,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call floorf@plt +; RV64IZFH-NEXT: call floorf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -90,7 +90,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call floorf@plt +; RV32IZHINX-NEXT: call floorf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -101,7 +101,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call floorf@plt +; RV64IZHINX-NEXT: call floorf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -112,7 +112,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call floorf@plt +; RV32IZDINXZHINX-NEXT: call floorf ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -123,7 +123,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call floorf@plt +; RV64IZDINXZHINX-NEXT: call floorf ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -140,7 +140,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call ceilf@plt +; RV32IZFH-NEXT: call ceilf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -151,7 +151,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call ceilf@plt +; RV64IZFH-NEXT: call ceilf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -162,7 +162,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call ceilf@plt +; RV32IZHINX-NEXT: call ceilf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -173,7 +173,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call ceilf@plt +; RV64IZHINX-NEXT: call ceilf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -184,7 +184,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call ceilf@plt +; RV32IZDINXZHINX-NEXT: call ceilf ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -195,7 +195,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call ceilf@plt +; RV64IZDINXZHINX-NEXT: call ceilf ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -212,7 +212,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call truncf@plt +; RV32IZFH-NEXT: call truncf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -223,7 +223,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call truncf@plt +; RV64IZFH-NEXT: call truncf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -234,7 +234,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call truncf@plt +; RV32IZHINX-NEXT: call truncf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -245,7 +245,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call truncf@plt +; RV64IZHINX-NEXT: call truncf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -256,7 +256,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call truncf@plt +; RV32IZDINXZHINX-NEXT: call truncf ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -267,7 +267,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call truncf@plt +; RV64IZDINXZHINX-NEXT: call truncf ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -284,7 +284,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call rintf@plt +; RV32IZFH-NEXT: call rintf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -295,7 +295,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call rintf@plt +; RV64IZFH-NEXT: call rintf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -306,7 +306,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call rintf@plt +; RV32IZHINX-NEXT: call rintf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -317,7 +317,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call rintf@plt +; RV64IZHINX-NEXT: call rintf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -328,7 +328,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call rintf@plt +; RV32IZDINXZHINX-NEXT: call rintf ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -339,7 +339,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call rintf@plt +; RV64IZDINXZHINX-NEXT: call rintf ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -356,7 +356,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call nearbyintf@plt +; RV32IZFH-NEXT: call nearbyintf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -367,7 +367,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call nearbyintf@plt +; RV64IZFH-NEXT: call nearbyintf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -378,7 +378,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call nearbyintf@plt +; RV32IZHINX-NEXT: call nearbyintf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -389,7 +389,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call nearbyintf@plt +; RV64IZHINX-NEXT: call nearbyintf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -400,7 +400,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call nearbyintf@plt +; RV32IZDINXZHINX-NEXT: call nearbyintf ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -411,7 +411,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call nearbyintf@plt +; RV64IZDINXZHINX-NEXT: call nearbyintf ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -428,7 +428,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call roundf@plt +; RV32IZFH-NEXT: call roundf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -439,7 +439,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call roundf@plt +; RV64IZFH-NEXT: call roundf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -450,7 +450,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call roundf@plt +; RV32IZHINX-NEXT: call roundf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -461,7 +461,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call roundf@plt +; RV64IZHINX-NEXT: call roundf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -472,7 +472,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call roundf@plt +; RV32IZDINXZHINX-NEXT: call roundf ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -483,7 +483,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call roundf@plt +; RV64IZDINXZHINX-NEXT: call roundf ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -500,7 +500,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call roundevenf@plt +; RV32IZFH-NEXT: call roundevenf ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 @@ -511,7 +511,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call roundevenf@plt +; RV64IZFH-NEXT: call roundevenf ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: addi sp, sp, 16 @@ -522,7 +522,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call roundevenf@plt +; RV32IZHINX-NEXT: call roundevenf ; RV32IZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 @@ -533,7 +533,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call roundevenf@plt +; RV64IZHINX-NEXT: call roundevenf ; RV64IZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINX-NEXT: addi sp, sp, 16 @@ -544,7 +544,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call roundevenf@plt +; RV32IZDINXZHINX-NEXT: call roundevenf ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -555,7 +555,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call roundevenf@plt +; RV64IZDINXZHINX-NEXT: call roundevenf ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 @@ -644,7 +644,7 @@ define i64 @llrint_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call llrintf@plt +; RV32IZFH-NEXT: call llrintf ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -659,7 +659,7 @@ define i64 @llrint_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call llrintf@plt +; RV32IZHINX-NEXT: call llrintf ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -674,7 +674,7 @@ define i64 @llrint_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call llrintf@plt +; RV32IZDINXZHINX-NEXT: call llrintf ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret @@ -695,7 +695,7 @@ define i64 @llround_f16(half %a) nounwind strictfp { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: call llroundf@plt +; RV32IZFH-NEXT: call llroundf ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret @@ -710,7 +710,7 @@ define i64 @llround_f16(half %a) nounwind strictfp { ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZHINX-NEXT: call llroundf@plt +; RV32IZHINX-NEXT: call llroundf ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret @@ -725,7 +725,7 @@ define i64 @llround_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: call llroundf@plt +; RV32IZDINXZHINX-NEXT: call llroundf ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINX-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll index 0475b941ec0f..097d1e0f6ee5 100644 --- a/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll +++ b/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll @@ -80,7 +80,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call floorf@plt +; RV32IZFHMIN-NEXT: call floorf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -91,7 +91,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call floorf@plt +; RV64IZFHMIN-NEXT: call floorf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -102,7 +102,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call floorf@plt +; RV32IZHINXMIN-STRICT-NEXT: call floorf ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -113,7 +113,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-STRICT-NEXT: call floorf@plt +; RV64IZHINXMIN-STRICT-NEXT: call floorf ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -124,7 +124,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call floorf@plt +; RV32IZDINXZHINXMIN-NEXT: call floorf ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -135,7 +135,7 @@ define half @floor_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINXMIN-NEXT: call floorf@plt +; RV64IZDINXZHINXMIN-NEXT: call floorf ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -152,7 +152,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call ceilf@plt +; RV32IZFHMIN-NEXT: call ceilf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -163,7 +163,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call ceilf@plt +; RV64IZFHMIN-NEXT: call ceilf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -174,7 +174,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call ceilf@plt +; RV32IZHINXMIN-STRICT-NEXT: call ceilf ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -185,7 +185,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-STRICT-NEXT: call ceilf@plt +; RV64IZHINXMIN-STRICT-NEXT: call ceilf ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -196,7 +196,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call ceilf@plt +; RV32IZDINXZHINXMIN-NEXT: call ceilf ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -207,7 +207,7 @@ define half @ceil_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINXMIN-NEXT: call ceilf@plt +; RV64IZDINXZHINXMIN-NEXT: call ceilf ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -224,7 +224,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call truncf@plt +; RV32IZFHMIN-NEXT: call truncf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -235,7 +235,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call truncf@plt +; RV64IZFHMIN-NEXT: call truncf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -246,7 +246,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call truncf@plt +; RV32IZHINXMIN-STRICT-NEXT: call truncf ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -257,7 +257,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-STRICT-NEXT: call truncf@plt +; RV64IZHINXMIN-STRICT-NEXT: call truncf ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -268,7 +268,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call truncf@plt +; RV32IZDINXZHINXMIN-NEXT: call truncf ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -279,7 +279,7 @@ define half @trunc_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINXMIN-NEXT: call truncf@plt +; RV64IZDINXZHINXMIN-NEXT: call truncf ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -296,7 +296,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call rintf@plt +; RV32IZFHMIN-NEXT: call rintf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -307,7 +307,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call rintf@plt +; RV64IZFHMIN-NEXT: call rintf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -318,7 +318,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call rintf@plt +; RV32IZHINXMIN-STRICT-NEXT: call rintf ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -329,7 +329,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-STRICT-NEXT: call rintf@plt +; RV64IZHINXMIN-STRICT-NEXT: call rintf ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -340,7 +340,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call rintf@plt +; RV32IZDINXZHINXMIN-NEXT: call rintf ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -351,7 +351,7 @@ define half @rint_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINXMIN-NEXT: call rintf@plt +; RV64IZDINXZHINXMIN-NEXT: call rintf ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -368,7 +368,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call nearbyintf@plt +; RV32IZFHMIN-NEXT: call nearbyintf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -379,7 +379,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call nearbyintf@plt +; RV64IZFHMIN-NEXT: call nearbyintf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -390,7 +390,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call nearbyintf@plt +; RV32IZHINXMIN-STRICT-NEXT: call nearbyintf ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -401,7 +401,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-STRICT-NEXT: call nearbyintf@plt +; RV64IZHINXMIN-STRICT-NEXT: call nearbyintf ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -412,7 +412,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call nearbyintf@plt +; RV32IZDINXZHINXMIN-NEXT: call nearbyintf ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -423,7 +423,7 @@ define half @nearbyint_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINXMIN-NEXT: call nearbyintf@plt +; RV64IZDINXZHINXMIN-NEXT: call nearbyintf ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -440,7 +440,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call roundf@plt +; RV32IZFHMIN-NEXT: call roundf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -451,7 +451,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call roundf@plt +; RV64IZFHMIN-NEXT: call roundf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -462,7 +462,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call roundf@plt +; RV32IZHINXMIN-STRICT-NEXT: call roundf ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -473,7 +473,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-STRICT-NEXT: call roundf@plt +; RV64IZHINXMIN-STRICT-NEXT: call roundf ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -484,7 +484,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call roundf@plt +; RV32IZDINXZHINXMIN-NEXT: call roundf ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -495,7 +495,7 @@ define half @round_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINXMIN-NEXT: call roundf@plt +; RV64IZDINXZHINXMIN-NEXT: call roundf ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -512,7 +512,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call roundevenf@plt +; RV32IZFHMIN-NEXT: call roundevenf ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 @@ -523,7 +523,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFHMIN-NEXT: call roundevenf@plt +; RV64IZFHMIN-NEXT: call roundevenf ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFHMIN-NEXT: addi sp, sp, 16 @@ -534,7 +534,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call roundevenf@plt +; RV32IZHINXMIN-STRICT-NEXT: call roundevenf ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -545,7 +545,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-STRICT-NEXT: call roundevenf@plt +; RV64IZHINXMIN-STRICT-NEXT: call roundevenf ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 @@ -556,7 +556,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call roundevenf@plt +; RV32IZDINXZHINXMIN-NEXT: call roundevenf ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -567,7 +567,7 @@ define half @roundeven_f16(half %a) nounwind strictfp { ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINXMIN-NEXT: call roundevenf@plt +; RV64IZDINXZHINXMIN-NEXT: call roundevenf ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16 @@ -668,7 +668,7 @@ define i64 @llrint_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call llrintf@plt +; RV32IZFHMIN-NEXT: call llrintf ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -684,7 +684,7 @@ define i64 @llrint_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call llrintf@plt +; RV32IZHINXMIN-STRICT-NEXT: call llrintf ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-STRICT-NEXT: ret @@ -700,7 +700,7 @@ define i64 @llrint_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call llrintf@plt +; RV32IZDINXZHINXMIN-NEXT: call llrintf ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINXMIN-NEXT: ret @@ -722,7 +722,7 @@ define i64 @llround_f16(half %a) nounwind strictfp { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFHMIN-NEXT: call llroundf@plt +; RV32IZFHMIN-NEXT: call llroundf ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret @@ -738,7 +738,7 @@ define i64 @llround_f16(half %a) nounwind strictfp { ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-STRICT-NEXT: call llroundf@plt +; RV32IZHINXMIN-STRICT-NEXT: call llroundf ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-STRICT-NEXT: ret @@ -754,7 +754,7 @@ define i64 @llround_f16(half %a) nounwind strictfp { ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINXMIN-NEXT: call llroundf@plt +; RV32IZDINXZHINXMIN-NEXT: call llroundf ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZDINXZHINXMIN-NEXT: ret diff --git a/llvm/test/MC/RISCV/function-call.s b/llvm/test/MC/RISCV/function-call.s index e0650593ec91..1521ae7e55e1 100644 --- a/llvm/test/MC/RISCV/function-call.s +++ b/llvm/test/MC/RISCV/function-call.s @@ -50,7 +50,7 @@ call foo@plt # RELOC: R_RISCV_CALL_PLT foo 0x0 # INSTR: auipc ra, 0 # INSTR: jalr ra -# FIXUP: fixup A - offset: 0, value: foo@plt, kind: fixup_riscv_call_plt +# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call_plt # Ensure that an explicit register operand can be parsed. @@ -64,4 +64,4 @@ call a0, foo@plt # RELOC: R_RISCV_CALL_PLT foo 0x0 # INSTR: auipc a0, 0 # INSTR: jalr a0 -# FIXUP: fixup A - offset: 0, value: foo@plt, kind: fixup_riscv_call_plt +# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call_plt diff --git a/llvm/test/MC/RISCV/tail-call.s b/llvm/test/MC/RISCV/tail-call.s index 3670c7749ab1..c94af672edda 100644 --- a/llvm/test/MC/RISCV/tail-call.s +++ b/llvm/test/MC/RISCV/tail-call.s @@ -50,4 +50,4 @@ tail foo@plt # RELOC: R_RISCV_CALL_PLT foo 0x0 # INSTR: auipc t1, 0 # INSTR: jr t1 -# FIXUP: fixup A - offset: 0, value: foo@plt, kind: +# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call_plt -- GitLab From 360996ac5ad26714a6ddbee45730fbcfb7dc3eea Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sun, 7 Jan 2024 12:43:39 -0800 Subject: [PATCH 005/652] [RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253) Since #72467, `@plt` in assembly output "call foo@plt" is omitted. We can trivially merge MO_PLT and MO_CALL without any functional change to assembly/relocatable file output. Earlier architectures use different call relocation types whether a PLT is potentially needed: R_386_PLT32/R_386_PC32, R_68K_PLT32/R_68K_PC32, R_SPARC_WDISP30/R_SPARC_WPLT320. However, as the PLT property is per-symbol instead of per-call-site and linkers can optimize out a PLT, the distinction has been confusing. Arm made good names R_ARM_CALL/R_AARCH64_CALL. Let's use MO_CALL instead of MO_PLT. As follow-ups, we can merge fixup_riscv_call/fixup_riscv_call_plt and VK_RISCV_CALL/VK_RISCV_CALL_PLT. --- .../Target/RISCV/GISel/RISCVCallLowering.cpp | 2 +- .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 - llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 3 - llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 15 +--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 - .../calling-conv-ilp32-ilp32f-common.ll | 8 +-- ...calling-conv-ilp32-ilp32f-ilp32d-common.ll | 30 ++++---- .../irtranslator/calling-conv-ilp32.ll | 6 +- .../irtranslator/calling-conv-ilp32d.ll | 12 ++-- .../calling-conv-ilp32f-ilp32d-common.ll | 20 +++--- .../calling-conv-lp64-lp64f-common.ll | 8 +-- .../calling-conv-lp64-lp64f-lp64d-common.ll | 30 ++++---- .../irtranslator/calling-conv-lp64.ll | 6 +- .../irtranslator/calling-conv-lp64d.ll | 10 +-- .../RISCV/GlobalISel/irtranslator/calls.ll | 64 ++++++++--------- .../RISCV/GlobalISel/irtranslator/vararg.ll | 70 +++++++++---------- .../GlobalISel/irtranslator/variadic-call.ll | 4 +- .../legalizer/legalize-div-rv32.mir | 32 ++++----- .../legalizer/legalize-div-rv64.mir | 36 +++++----- .../legalizer/legalize-fp-ceil-floor.mir | 8 +-- .../legalizer/legalize-mul-rv32.mir | 12 ++-- .../legalizer/legalize-mul-rv64.mir | 14 ++-- .../legalizer/legalize-mulo-rv32.mir | 12 ++-- .../legalizer/legalize-mulo-rv64.mir | 16 ++--- .../legalizer/legalize-rem-rv32.mir | 32 ++++----- .../legalizer/legalize-rem-rv64.mir | 36 +++++----- .../test/CodeGen/RISCV/float-select-verify.ll | 4 +- llvm/test/CodeGen/RISCV/live-sp.mir | 4 +- llvm/test/CodeGen/RISCV/make-compressible.mir | 24 +++---- llvm/test/CodeGen/RISCV/mir-target-flags.ll | 8 +-- .../RISCV/out-of-reach-emergency-slot.mir | 2 +- .../RISCV/rvv/addi-rvv-stack-object.mir | 2 +- .../rvv/fixed-vectors-emergency-slot.mir | 2 +- .../RISCV/rvv/large-rvv-stack-size.mir | 2 +- .../CodeGen/RISCV/rvv/rvv-stack-align.mir | 6 +- .../rvv/wrong-stack-offset-for-rvv-object.mir | 4 +- llvm/test/CodeGen/RISCV/vector-abi.ll | 4 +- 37 files changed, 267 insertions(+), 283 deletions(-) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index 50ed85acdec0..697ad476ff8c 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -579,7 +579,7 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, // Select the recommended relocation type R_RISCV_CALL_PLT. if (!Info.Callee.isReg()) - Info.Callee.setTargetFlags(RISCVII::MO_PLT); + Info.Callee.setTargetFlags(RISCVII::MO_CALL); MachineInstrBuilder Call = MIRBuilder diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index c32210fc1419..433e2e6f80bd 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -254,7 +254,6 @@ static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) { enum { MO_None = 0, MO_CALL = 1, - MO_PLT = 2, MO_LO = 3, MO_HI = 4, MO_PCREL_LO = 5, diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 0fd514fa87cd..f2bd5118fc07 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -747,9 +747,6 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, Kind = RISCVMCExpr::VK_RISCV_None; break; case RISCVII::MO_CALL: - Kind = RISCVMCExpr::VK_RISCV_CALL; - break; - case RISCVII::MO_PLT: Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; break; case RISCVII::MO_LO: diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index bc4b2b022c0a..79c16cf4c4c3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -18215,20 +18215,9 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, // split it and then direct call can be matched by PseudoCALL. if (GlobalAddressSDNode *S = dyn_cast(Callee)) { const GlobalValue *GV = S->getGlobal(); - - unsigned OpFlags = RISCVII::MO_CALL; - if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV)) - OpFlags = RISCVII::MO_PLT; - - Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags); + Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, RISCVII::MO_CALL); } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { - unsigned OpFlags = RISCVII::MO_CALL; - - if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(), - nullptr)) - OpFlags = RISCVII::MO_PLT; - - Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags); + Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, RISCVII::MO_CALL); } // The first call operand is the chain and the second is the target address. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index cd98438eed88..7f6a045a7d04 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2365,7 +2365,6 @@ RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { using namespace RISCVII; static const std::pair TargetFlags[] = { {MO_CALL, "riscv-call"}, - {MO_PLT, "riscv-plt"}, {MO_LO, "riscv-lo"}, {MO_HI, "riscv-hi"}, {MO_PCREL_LO, "riscv-pcrel-lo"}, diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll index 226f2eb976e7..b87cc7869a46 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll @@ -40,7 +40,7 @@ define i32 @caller_double_in_regs() nounwind { ; ILP32-NEXT: $x10 = COPY [[C]](s32) ; ILP32-NEXT: $x11 = COPY [[UV]](s32) ; ILP32-NEXT: $x12 = COPY [[UV1]](s32) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: $x10 = COPY [[COPY]](s32) @@ -55,7 +55,7 @@ define i32 @caller_double_in_regs() nounwind { ; ILP32F-NEXT: $x10 = COPY [[C]](s32) ; ILP32F-NEXT: $x11 = COPY [[UV]](s32) ; ILP32F-NEXT: $x12 = COPY [[UV1]](s32) - ; ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32F-NEXT: $x10 = COPY [[COPY]](s32) @@ -79,7 +79,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; ILP32-LABEL: name: caller_small_scalar_ret ; ILP32: bb.1 (%ir-block.0): ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -92,7 +92,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; ILP32F-LABEL: name: caller_small_scalar_ret ; ILP32F: bb.1 (%ir-block.0): ; ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll index cc48392e9ea8..1a3489521af1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -44,7 +44,7 @@ define i32 @caller_i64_in_regs() nounwind { ; ILP32-NEXT: $x10 = COPY [[C]](s32) ; ILP32-NEXT: $x11 = COPY [[UV]](s32) ; ILP32-NEXT: $x12 = COPY [[UV1]](s32) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @callee_i64_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_i64_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: $x10 = COPY [[COPY]](s32) @@ -59,7 +59,7 @@ define i32 @caller_i64_in_regs() nounwind { ; ILP32F-NEXT: $x10 = COPY [[C]](s32) ; ILP32F-NEXT: $x11 = COPY [[UV]](s32) ; ILP32F-NEXT: $x12 = COPY [[UV1]](s32) - ; ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_i64_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_i64_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32F-NEXT: $x10 = COPY [[COPY]](s32) @@ -74,7 +74,7 @@ define i32 @caller_i64_in_regs() nounwind { ; ILP32D-NEXT: $x10 = COPY [[C]](s32) ; ILP32D-NEXT: $x11 = COPY [[UV]](s32) ; ILP32D-NEXT: $x12 = COPY [[UV1]](s32) - ; ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_i64_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_i64_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32D-NEXT: $x10 = COPY [[COPY]](s32) @@ -162,7 +162,7 @@ define i32 @caller_many_scalars() nounwind { ; ILP32-NEXT: $x15 = COPY [[C4]](s32) ; ILP32-NEXT: $x16 = COPY [[C5]](s32) ; ILP32-NEXT: $x17 = COPY [[UV2]](s32) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @callee_many_scalars, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 ; ILP32-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: $x10 = COPY [[COPY1]](s32) @@ -198,7 +198,7 @@ define i32 @caller_many_scalars() nounwind { ; ILP32F-NEXT: $x15 = COPY [[C4]](s32) ; ILP32F-NEXT: $x16 = COPY [[C5]](s32) ; ILP32F-NEXT: $x17 = COPY [[UV2]](s32) - ; ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_many_scalars, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 ; ILP32F-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32F-NEXT: $x10 = COPY [[COPY1]](s32) @@ -234,7 +234,7 @@ define i32 @caller_many_scalars() nounwind { ; ILP32D-NEXT: $x15 = COPY [[C4]](s32) ; ILP32D-NEXT: $x16 = COPY [[C5]](s32) ; ILP32D-NEXT: $x17 = COPY [[UV2]](s32) - ; ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_many_scalars, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 ; ILP32D-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) @@ -261,7 +261,7 @@ define i32 @caller_small_scalar_ret() nounwind { ; ILP32: bb.1 (%ir-block.0): ; ILP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 987654321234567 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -275,7 +275,7 @@ define i32 @caller_small_scalar_ret() nounwind { ; ILP32F: bb.1 (%ir-block.0): ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 987654321234567 ; ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -289,7 +289,7 @@ define i32 @caller_small_scalar_ret() nounwind { ; ILP32D: bb.1 (%ir-block.0): ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 987654321234567 ; ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -323,7 +323,7 @@ define i32 @caller_small_struct_ret() nounwind { ; ILP32-LABEL: name: caller_small_struct_ret ; ILP32: bb.1 (%ir-block.0): ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 @@ -335,7 +335,7 @@ define i32 @caller_small_struct_ret() nounwind { ; ILP32F-LABEL: name: caller_small_struct_ret ; ILP32F: bb.1 (%ir-block.0): ; ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 @@ -347,7 +347,7 @@ define i32 @caller_small_struct_ret() nounwind { ; ILP32D-LABEL: name: caller_small_struct_ret ; ILP32D: bb.1 (%ir-block.0): ; ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 @@ -404,7 +404,7 @@ define i32 @caller_large_struct_ret() nounwind { ; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @callee_large_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1) ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 @@ -419,7 +419,7 @@ define i32 @caller_large_struct_ret() nounwind { ; ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 ; ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) - ; ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_large_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 + ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1) ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 @@ -434,7 +434,7 @@ define i32 @caller_large_struct_ret() nounwind { ; ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 ; ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) - ; ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_large_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1) ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll index 9426c77081e4..93649b5f60f7 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll @@ -31,7 +31,7 @@ define i32 @caller_float_in_regs() nounwind { ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: $x10 = COPY [[C]](s32) ; RV32I-NEXT: $x11 = COPY [[C1]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: $x10 = COPY [[COPY]](s32) @@ -94,7 +94,7 @@ define i32 @caller_float_on_stack() nounwind { ; RV32I-NEXT: $x15 = COPY [[UV5]](s32) ; RV32I-NEXT: $x16 = COPY [[UV6]](s32) ; RV32I-NEXT: $x17 = COPY [[UV7]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_on_stack, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: $x10 = COPY [[COPY1]](s32) @@ -116,7 +116,7 @@ define i32 @caller_tiny_scalar_ret() nounwind { ; RV32I-LABEL: name: caller_tiny_scalar_ret ; RV32I: bb.1 (%ir-block.0): ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_tiny_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_tiny_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: $x10 = COPY [[COPY]](s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll index 8aaf9abaf364..4d487eb5cda2 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll @@ -30,7 +30,7 @@ define i32 @caller_double_in_fpr() nounwind { ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: $x10 = COPY [[C]](s32) ; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) @@ -96,7 +96,7 @@ define i32 @caller_double_in_fpr_exhausted_gprs() nounwind { ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32) ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32) ; RV32-ILP32D-NEXT: $f10_d = COPY [[C5]](s64) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) @@ -158,7 +158,7 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind { ; RV32-ILP32D-NEXT: $f17_d = COPY [[C7]](s64) ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32) ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit $x11, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) @@ -247,7 +247,7 @@ define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind ; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64) ; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64) ; RV32-ILP32D-NEXT: $x17 = COPY [[UV6]](s32) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x17, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x17, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) @@ -339,7 +339,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind { ; RV32-ILP32D-NEXT: $f15_d = COPY [[C9]](s64) ; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64) ; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) @@ -363,7 +363,7 @@ define i32 @caller_double_ret() nounwind { ; RV32-ILP32D-LABEL: name: caller_double_ret ; RV32-ILP32D: bb.1 (%ir-block.0): ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_d + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_d ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d ; RV32-ILP32D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll index 9443b8b2fefd..a9c603bfdd74 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll @@ -33,7 +33,7 @@ define i32 @caller_float_in_fpr() nounwind { ; RV32-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32F-NEXT: $x10 = COPY [[C]](s32) ; RV32-ILP32F-NEXT: $f10_f = COPY [[C1]](s32) - ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_fpr, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10 + ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32) @@ -46,7 +46,7 @@ define i32 @caller_float_in_fpr() nounwind { ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: $x10 = COPY [[C]](s32) ; RV32-ILP32D-NEXT: $f10_f = COPY [[C1]](s32) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) @@ -112,7 +112,7 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind { ; RV32-ILP32F-NEXT: $x16 = COPY [[UV6]](s32) ; RV32-ILP32F-NEXT: $x17 = COPY [[UV7]](s32) ; RV32-ILP32F-NEXT: $f10_f = COPY [[C5]](s32) - ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_fpr_exhausted_gprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10 + ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr_exhausted_gprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY1]](s32) @@ -144,7 +144,7 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind { ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32) ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32) ; RV32-ILP32D-NEXT: $f10_f = COPY [[C5]](s32) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) @@ -202,7 +202,7 @@ define i32 @caller_float_in_gpr_exhausted_fprs() nounwind { ; RV32-ILP32F-NEXT: $f16_f = COPY [[C6]](s32) ; RV32-ILP32F-NEXT: $f17_f = COPY [[C7]](s32) ; RV32-ILP32F-NEXT: $x10 = COPY [[C8]](s32) - ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_gpr_exhausted_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10 + ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_gpr_exhausted_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32) @@ -229,7 +229,7 @@ define i32 @caller_float_in_gpr_exhausted_fprs() nounwind { ; RV32-ILP32D-NEXT: $f16_f = COPY [[C6]](s32) ; RV32-ILP32D-NEXT: $f17_f = COPY [[C7]](s32) ; RV32-ILP32D-NEXT: $x10 = COPY [[C8]](s32) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) @@ -320,7 +320,7 @@ define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind { ; RV32-ILP32F-NEXT: $f15_f = COPY [[C9]](s32) ; RV32-ILP32F-NEXT: $f16_f = COPY [[C10]](s32) ; RV32-ILP32F-NEXT: $f17_f = COPY [[C11]](s32) - ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10 + ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY1]](s32) @@ -366,7 +366,7 @@ define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind { ; RV32-ILP32D-NEXT: $f15_f = COPY [[C9]](s32) ; RV32-ILP32D-NEXT: $f16_f = COPY [[C10]](s32) ; RV32-ILP32D-NEXT: $f17_f = COPY [[C11]](s32) - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10 + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) @@ -390,7 +390,7 @@ define i32 @caller_float_ret() nounwind { ; RV32-ILP32F-LABEL: name: caller_float_ret ; RV32-ILP32F: bb.1 (%ir-block.0): ; RV32-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $f10_f + ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $f10_f ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32) @@ -399,7 +399,7 @@ define i32 @caller_float_ret() nounwind { ; RV32-ILP32D-LABEL: name: caller_float_ret ; RV32-ILP32D: bb.1 (%ir-block.0): ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_f + ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_f ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll index 72f523f089da..e4d1d3132ea4 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll @@ -33,7 +33,7 @@ define i64 @caller_double_in_regs() nounwind { ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: $x10 = COPY [[C]](s64) ; LP64-NEXT: $x11 = COPY [[C1]](s64) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: $x10 = COPY [[COPY]](s64) @@ -46,7 +46,7 @@ define i64 @caller_double_in_regs() nounwind { ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: $x10 = COPY [[C]](s64) ; LP64F-NEXT: $x11 = COPY [[C1]](s64) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: $x10 = COPY [[COPY]](s64) @@ -68,7 +68,7 @@ define i64 @caller_double_ret() nounwind { ; LP64-LABEL: name: caller_double_ret ; LP64: bb.1 (%ir-block.0): ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: $x10 = COPY [[COPY]](s64) @@ -77,7 +77,7 @@ define i64 @caller_double_ret() nounwind { ; LP64F-LABEL: name: caller_double_ret ; LP64F: bb.1 (%ir-block.0): ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: $x10 = COPY [[COPY]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll index d55c0140b831..b175b8d92e6c 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll @@ -44,7 +44,7 @@ define i64 @caller_i128_in_regs() nounwind { ; LP64-NEXT: $x10 = COPY [[C]](s64) ; LP64-NEXT: $x11 = COPY [[UV]](s64) ; LP64-NEXT: $x12 = COPY [[UV1]](s64) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_i128_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_i128_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: $x10 = COPY [[COPY]](s64) @@ -59,7 +59,7 @@ define i64 @caller_i128_in_regs() nounwind { ; LP64F-NEXT: $x10 = COPY [[C]](s64) ; LP64F-NEXT: $x11 = COPY [[UV]](s64) ; LP64F-NEXT: $x12 = COPY [[UV1]](s64) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_i128_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_i128_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: $x10 = COPY [[COPY]](s64) @@ -74,7 +74,7 @@ define i64 @caller_i128_in_regs() nounwind { ; LP64D-NEXT: $x10 = COPY [[C]](s64) ; LP64D-NEXT: $x11 = COPY [[UV]](s64) ; LP64D-NEXT: $x12 = COPY [[UV1]](s64) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_i128_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_i128_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64D-NEXT: $x10 = COPY [[COPY]](s64) @@ -171,7 +171,7 @@ define i32 @caller_many_scalars() nounwind { ; LP64-NEXT: $x15 = COPY [[ANYEXT3]](s64) ; LP64-NEXT: $x16 = COPY [[ANYEXT4]](s64) ; LP64-NEXT: $x17 = COPY [[UV2]](s64) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_many_scalars, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 ; LP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) @@ -213,7 +213,7 @@ define i32 @caller_many_scalars() nounwind { ; LP64F-NEXT: $x15 = COPY [[ANYEXT3]](s64) ; LP64F-NEXT: $x16 = COPY [[ANYEXT4]](s64) ; LP64F-NEXT: $x17 = COPY [[UV2]](s64) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_many_scalars, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 ; LP64F-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) @@ -255,7 +255,7 @@ define i32 @caller_many_scalars() nounwind { ; LP64D-NEXT: $x15 = COPY [[ANYEXT3]](s64) ; LP64D-NEXT: $x16 = COPY [[ANYEXT4]](s64) ; LP64D-NEXT: $x17 = COPY [[UV2]](s64) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_many_scalars, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 ; LP64D-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; LP64D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) @@ -284,7 +284,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; LP64: bb.1 (%ir-block.0): ; LP64-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -2 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -298,7 +298,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; LP64F: bb.1 (%ir-block.0): ; LP64F-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -2 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -312,7 +312,7 @@ define i64 @caller_small_scalar_ret() nounwind { ; LP64D: bb.1 (%ir-block.0): ; LP64D-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -2 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_scalar_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -346,7 +346,7 @@ define i64 @caller_small_struct_ret() nounwind { ; LP64-LABEL: name: caller_small_struct_ret ; LP64: bb.1 (%ir-block.0): ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 @@ -358,7 +358,7 @@ define i64 @caller_small_struct_ret() nounwind { ; LP64F-LABEL: name: caller_small_struct_ret ; LP64F: bb.1 (%ir-block.0): ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 @@ -370,7 +370,7 @@ define i64 @caller_small_struct_ret() nounwind { ; LP64D-LABEL: name: caller_small_struct_ret ; LP64D: bb.1 (%ir-block.0): ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_small_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 @@ -427,7 +427,7 @@ define i64 @caller_large_struct_ret() nounwind { ; LP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_large_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1) ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 @@ -442,7 +442,7 @@ define i64 @caller_large_struct_ret() nounwind { ; LP64F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_large_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1) ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 @@ -457,7 +457,7 @@ define i64 @caller_large_struct_ret() nounwind { ; LP64D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @callee_large_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1) ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll index 93b6747a779e..9283f1f090ed 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll @@ -37,7 +37,7 @@ define i64 @caller_float_in_regs() nounwind { ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; RV64I-NEXT: $x10 = COPY [[C]](s64) ; RV64I-NEXT: $x11 = COPY [[ANYEXT]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: $x10 = COPY [[COPY]](s64) @@ -51,7 +51,7 @@ define i64 @caller_float_in_regs() nounwind { ; RV64F-NEXT: $x10 = COPY [[C]](s64) ; RV64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; RV64F-NEXT: $x11 = COPY [[ANYEXT]](s64) - ; RV64F-NEXT: PseudoCALL target-flags(riscv-plt) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; RV64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64F-NEXT: $x10 = COPY [[COPY]](s64) @@ -74,7 +74,7 @@ define i64 @caller_tiny_scalar_ret() nounwind { ; RV64-LABEL: name: caller_tiny_scalar_ret ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64-NEXT: PseudoCALL target-flags(riscv-plt) @callee_tiny_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV64-NEXT: PseudoCALL target-flags(riscv-call) @callee_tiny_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll index 81ff2fcadc74..3d7ae6802fc4 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll @@ -30,7 +30,7 @@ define i64 @caller_double_in_regs() nounwind { ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: $x10 = COPY [[C]](s64) ; RV64I-NEXT: $f10_d = COPY [[C1]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: $x10 = COPY [[COPY]](s64) @@ -96,7 +96,7 @@ define i64 @caller_double_in_fpr_exhausted_gprs() nounwind { ; RV64I-NEXT: $x16 = COPY [[UV6]](s64) ; RV64I-NEXT: $x17 = COPY [[UV7]](s64) ; RV64I-NEXT: $f10_d = COPY [[C5]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: $x10 = COPY [[COPY1]](s64) @@ -155,7 +155,7 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind { ; RV64I-NEXT: $f16_d = COPY [[C6]](s64) ; RV64I-NEXT: $f17_d = COPY [[C7]](s64) ; RV64I-NEXT: $x10 = COPY [[C8]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) @@ -248,7 +248,7 @@ define i64 @caller_double_on_stack_exhausted_gprs_fprs() nounwind { ; RV64I-NEXT: $f15_d = COPY [[C9]](s64) ; RV64I-NEXT: $f16_d = COPY [[C10]](s64) ; RV64I-NEXT: $f17_d = COPY [[C11]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: $x10 = COPY [[COPY1]](s64) @@ -272,7 +272,7 @@ define i64 @caller_double_ret() nounwind { ; RV64I-LABEL: name: caller_double_ret ; RV64I: bb.1 (%ir-block.0): ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @callee_double_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_d + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_d ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d ; RV64I-NEXT: $x10 = COPY [[COPY]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll index e7e093f7110b..b06b539ded19 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll @@ -11,14 +11,14 @@ define void @test_call_void_noargs() { ; RV32I-LABEL: name: test_call_void_noargs ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_noargs, csr_ilp32_lp64, implicit-def $x1 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_noargs, csr_ilp32_lp64, implicit-def $x1 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; ; RV64I-LABEL: name: test_call_void_noargs ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_noargs, csr_ilp32_lp64, implicit-def $x1 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_noargs, csr_ilp32_lp64, implicit-def $x1 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -39,7 +39,7 @@ define void @test_call_void_args_i8() { ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s8) ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32) ; RV32I-NEXT: $x11 = COPY [[ANYEXT1]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i8, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; @@ -52,7 +52,7 @@ define void @test_call_void_args_i8() { ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s8) ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) ; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i8, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -73,7 +73,7 @@ define void @test_call_void_args_i8_zext() { ; RV32I-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[C1]](s8) ; RV32I-NEXT: $x10 = COPY [[ZEXT]](s32) ; RV32I-NEXT: $x11 = COPY [[ZEXT1]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i8_zext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8_zext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; @@ -86,7 +86,7 @@ define void @test_call_void_args_i8_zext() { ; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s8) ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64) ; RV64I-NEXT: $x11 = COPY [[ZEXT1]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i8_zext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8_zext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -107,7 +107,7 @@ define void @test_call_void_args_i16_sext() { ; RV32I-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16) ; RV32I-NEXT: $x10 = COPY [[SEXT]](s32) ; RV32I-NEXT: $x11 = COPY [[SEXT1]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i16_sext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i16_sext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; @@ -120,7 +120,7 @@ define void @test_call_void_args_i16_sext() { ; RV64I-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[C1]](s16) ; RV64I-NEXT: $x10 = COPY [[SEXT]](s64) ; RV64I-NEXT: $x11 = COPY [[SEXT1]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i16_sext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i16_sext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -139,7 +139,7 @@ define void @test_call_void_args_i32() { ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: $x10 = COPY [[C]](s32) ; RV32I-NEXT: $x11 = COPY [[C1]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i32, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i32, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; @@ -152,7 +152,7 @@ define void @test_call_void_args_i32() { ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) ; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i32, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i32, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -175,7 +175,7 @@ define void @test_call_void_args_i64() { ; RV32I-NEXT: $x11 = COPY [[UV1]](s32) ; RV32I-NEXT: $x12 = COPY [[UV2]](s32) ; RV32I-NEXT: $x13 = COPY [[UV3]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i64, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i64, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; @@ -186,7 +186,7 @@ define void @test_call_void_args_i64() { ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: $x10 = COPY [[C]](s64) ; RV64I-NEXT: $x11 = COPY [[C1]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_args_i64, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i64, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -201,7 +201,7 @@ define void @test_call_i8_noargs() { ; RV32I-LABEL: name: test_call_i8_noargs ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @i8_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i8_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) @@ -210,7 +210,7 @@ define void @test_call_i8_noargs() { ; RV64I-LABEL: name: test_call_i8_noargs ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @i8_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i8_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) @@ -227,7 +227,7 @@ define void @test_call_i16_noargs() { ; RV32I-LABEL: name: test_call_i16_noargs ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @i16_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i16_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) @@ -236,7 +236,7 @@ define void @test_call_i16_noargs() { ; RV64I-LABEL: name: test_call_i16_noargs ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @i16_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i16_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) @@ -253,7 +253,7 @@ define void @test_call_i32_noargs() { ; RV32I-LABEL: name: test_call_i32_noargs ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @i32_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i32_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: PseudoRET @@ -261,7 +261,7 @@ define void @test_call_i32_noargs() { ; RV64I-LABEL: name: test_call_i32_noargs ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @i32_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i32_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) @@ -278,7 +278,7 @@ define void @test_call_i64_noargs() { ; RV32I-LABEL: name: test_call_i64_noargs ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @i64_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i64_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -288,7 +288,7 @@ define void @test_call_i64_noargs() { ; RV64I-LABEL: name: test_call_i64_noargs ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @i64_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i64_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: PseudoRET @@ -303,7 +303,7 @@ define void @test_call_ptr_noargs() { ; RV32I-LABEL: name: test_call_ptr_noargs ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @ptr_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @ptr_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; RV32I-NEXT: PseudoRET @@ -311,7 +311,7 @@ define void @test_call_ptr_noargs() { ; RV64I-LABEL: name: test_call_ptr_noargs ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @ptr_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @ptr_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; RV64I-NEXT: PseudoRET @@ -326,7 +326,7 @@ define void @test_call_i32x2_noargs() { ; RV32I-LABEL: name: test_call_i32x2_noargs ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @i32x2_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i32x2_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -335,7 +335,7 @@ define void @test_call_i32x2_noargs() { ; RV64I-LABEL: name: test_call_i32x2_noargs ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @i32x2_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i32x2_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) @@ -358,7 +358,7 @@ define void @test_void_byval_args() { ; RV32I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: $x10 = COPY [[GV]](p0) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_byval_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_byval_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; @@ -367,7 +367,7 @@ define void @test_void_byval_args() { ; RV64I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: $x10 = COPY [[GV]](p0) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_byval_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_byval_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -383,7 +383,7 @@ define void @test_void_sret_args() { ; RV32I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: $x10 = COPY [[GV]](p0) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @void_sret_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_sret_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; @@ -392,7 +392,7 @@ define void @test_void_sret_args() { ; RV64I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: $x10 = COPY [[GV]](p0) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @void_sret_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_sret_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -406,14 +406,14 @@ define void @test_call_external() { ; RV32I-LABEL: name: test_call_external ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @external_function, csr_ilp32_lp64, implicit-def $x1 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @external_function, csr_ilp32_lp64, implicit-def $x1 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; ; RV64I-LABEL: name: test_call_external ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @external_function, csr_ilp32_lp64, implicit-def $x1 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @external_function, csr_ilp32_lp64, implicit-def $x1 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: @@ -427,14 +427,14 @@ define void @test_call_local() { ; RV32I-LABEL: name: test_call_local ; RV32I: bb.1.entry: ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @dso_local_function, csr_ilp32_lp64, implicit-def $x1 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @dso_local_function, csr_ilp32_lp64, implicit-def $x1 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: PseudoRET ; ; RV64I-LABEL: name: test_call_local ; RV64I: bb.1.entry: ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @dso_local_function, csr_ilp32_lp64, implicit-def $x1 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @dso_local_function, csr_ilp32_lp64, implicit-def $x1 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: PseudoRET entry: diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll index ff30ebd3a8c7..d26b3ecff7d3 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll @@ -164,7 +164,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; ILP32-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: $x10 = COPY [[VAARG]](s32) ; ILP32-NEXT: PseudoRET implicit $x10 @@ -209,7 +209,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; RV32D-ILP32-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1 ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0) - ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32-NEXT: $x10 = COPY [[VAARG]](s32) ; RV32D-ILP32-NEXT: PseudoRET implicit $x10 @@ -254,7 +254,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; RV32D-ILP32F-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1 ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32F-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0) - ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 + ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32F-NEXT: $x10 = COPY [[VAARG]](s32) ; RV32D-ILP32F-NEXT: PseudoRET implicit $x10 @@ -299,7 +299,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; RV32D-ILP32D-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1 ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32D-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0) - ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32D-NEXT: $x10 = COPY [[VAARG]](s32) ; RV32D-ILP32D-NEXT: PseudoRET implicit $x10 @@ -345,7 +345,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; LP64-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32) ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64) @@ -392,7 +392,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; LP64F-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32) ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64) @@ -439,7 +439,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind { ; LP64D-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32) ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64) @@ -542,7 +542,7 @@ define void @va1_caller() nounwind { ; ILP32-NEXT: $x12 = COPY [[UV]](s32) ; ILP32-NEXT: $x13 = COPY [[UV1]](s32) ; ILP32-NEXT: $x14 = COPY [[C1]](s32) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @va1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: PseudoRET @@ -558,7 +558,7 @@ define void @va1_caller() nounwind { ; RV32D-ILP32-NEXT: $x12 = COPY [[UV]](s32) ; RV32D-ILP32-NEXT: $x13 = COPY [[UV1]](s32) ; RV32D-ILP32-NEXT: $x14 = COPY [[C1]](s32) - ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 + ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32-NEXT: PseudoRET @@ -574,7 +574,7 @@ define void @va1_caller() nounwind { ; RV32D-ILP32F-NEXT: $x12 = COPY [[UV]](s32) ; RV32D-ILP32F-NEXT: $x13 = COPY [[UV1]](s32) ; RV32D-ILP32F-NEXT: $x14 = COPY [[C1]](s32) - ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @va1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 + ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32F-NEXT: PseudoRET @@ -590,7 +590,7 @@ define void @va1_caller() nounwind { ; RV32D-ILP32D-NEXT: $x12 = COPY [[UV]](s32) ; RV32D-ILP32D-NEXT: $x13 = COPY [[UV1]](s32) ; RV32D-ILP32D-NEXT: $x14 = COPY [[C1]](s32) - ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 + ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32D-NEXT: PseudoRET @@ -605,7 +605,7 @@ define void @va1_caller() nounwind { ; LP64-NEXT: $x10 = COPY [[DEF]](p0) ; LP64-NEXT: $x11 = COPY [[C]](s64) ; LP64-NEXT: $x12 = COPY [[ANYEXT]](s64) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @va1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) @@ -621,7 +621,7 @@ define void @va1_caller() nounwind { ; LP64F-NEXT: $x10 = COPY [[DEF]](p0) ; LP64F-NEXT: $x11 = COPY [[C]](s64) ; LP64F-NEXT: $x12 = COPY [[ANYEXT]](s64) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @va1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) @@ -637,7 +637,7 @@ define void @va1_caller() nounwind { ; LP64D-NEXT: $x10 = COPY [[DEF]](p0) ; LP64D-NEXT: $x11 = COPY [[C]](s64) ; LP64D-NEXT: $x12 = COPY [[ANYEXT]](s64) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) @@ -842,7 +842,7 @@ define void @va2_caller() nounwind { ; ILP32-NEXT: $x10 = COPY [[DEF]](p0) ; ILP32-NEXT: $x12 = COPY [[UV]](s32) ; ILP32-NEXT: $x13 = COPY [[UV1]](s32) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @va2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -858,7 +858,7 @@ define void @va2_caller() nounwind { ; RV32D-ILP32-NEXT: $x10 = COPY [[DEF]](p0) ; RV32D-ILP32-NEXT: $x12 = COPY [[UV]](s32) ; RV32D-ILP32-NEXT: $x13 = COPY [[UV1]](s32) - ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -874,7 +874,7 @@ define void @va2_caller() nounwind { ; RV32D-ILP32F-NEXT: $x10 = COPY [[DEF]](p0) ; RV32D-ILP32F-NEXT: $x12 = COPY [[UV]](s32) ; RV32D-ILP32F-NEXT: $x13 = COPY [[UV1]](s32) - ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @va2, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -890,7 +890,7 @@ define void @va2_caller() nounwind { ; RV32D-ILP32D-NEXT: $x10 = COPY [[DEF]](p0) ; RV32D-ILP32D-NEXT: $x12 = COPY [[UV]](s32) ; RV32D-ILP32D-NEXT: $x13 = COPY [[UV1]](s32) - ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -904,7 +904,7 @@ define void @va2_caller() nounwind { ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: $x10 = COPY [[DEF]](p0) ; LP64-NEXT: $x11 = COPY [[C]](s64) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @va2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: PseudoRET @@ -916,7 +916,7 @@ define void @va2_caller() nounwind { ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: $x10 = COPY [[DEF]](p0) ; LP64F-NEXT: $x11 = COPY [[C]](s64) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @va2, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: PseudoRET @@ -928,7 +928,7 @@ define void @va2_caller() nounwind { ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: $x10 = COPY [[DEF]](p0) ; LP64D-NEXT: $x11 = COPY [[C]](s64) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64D-NEXT: PseudoRET @@ -1134,7 +1134,7 @@ define void @va3_caller() nounwind { ; ILP32-NEXT: $x12 = COPY [[UV1]](s32) ; ILP32-NEXT: $x14 = COPY [[UV2]](s32) ; ILP32-NEXT: $x15 = COPY [[UV3]](s32) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @va3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -1154,7 +1154,7 @@ define void @va3_caller() nounwind { ; RV32D-ILP32-NEXT: $x12 = COPY [[UV1]](s32) ; RV32D-ILP32-NEXT: $x14 = COPY [[UV2]](s32) ; RV32D-ILP32-NEXT: $x15 = COPY [[UV3]](s32) - ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 + ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -1174,7 +1174,7 @@ define void @va3_caller() nounwind { ; RV32D-ILP32F-NEXT: $x12 = COPY [[UV1]](s32) ; RV32D-ILP32F-NEXT: $x14 = COPY [[UV2]](s32) ; RV32D-ILP32F-NEXT: $x15 = COPY [[UV3]](s32) - ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @va3, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 + ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -1194,7 +1194,7 @@ define void @va3_caller() nounwind { ; RV32D-ILP32D-NEXT: $x12 = COPY [[UV1]](s32) ; RV32D-ILP32D-NEXT: $x14 = COPY [[UV2]](s32) ; RV32D-ILP32D-NEXT: $x15 = COPY [[UV3]](s32) - ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 + ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x11 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -1211,7 +1211,7 @@ define void @va3_caller() nounwind { ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64) ; LP64-NEXT: $x11 = COPY [[C1]](s64) ; LP64-NEXT: $x12 = COPY [[C2]](s64) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @va3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64-NEXT: PseudoRET @@ -1226,7 +1226,7 @@ define void @va3_caller() nounwind { ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64) ; LP64F-NEXT: $x11 = COPY [[C1]](s64) ; LP64F-NEXT: $x12 = COPY [[C2]](s64) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @va3, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64F-NEXT: PseudoRET @@ -1241,7 +1241,7 @@ define void @va3_caller() nounwind { ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64) ; LP64D-NEXT: $x11 = COPY [[C1]](s64) ; LP64D-NEXT: $x12 = COPY [[C2]](s64) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; LP64D-NEXT: PseudoRET @@ -1288,7 +1288,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; ILP32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs) ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: $x10 = COPY [[LOAD]](p0) - ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 ; ILP32-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 @@ -1335,7 +1335,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV32D-ILP32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs) ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32-NEXT: $x10 = COPY [[LOAD]](p0) - ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 ; RV32D-ILP32-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 @@ -1382,7 +1382,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV32D-ILP32F-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs) ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32F-NEXT: $x10 = COPY [[LOAD]](p0) - ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 + ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32F-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 ; RV32D-ILP32F-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 @@ -1429,7 +1429,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV32D-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs) ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32D-NEXT: $x10 = COPY [[LOAD]](p0) - ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32D-ILP32D-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 ; RV32D-ILP32D-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 @@ -1477,7 +1477,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; LP64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4) ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: $x10 = COPY [[LOAD]](p0) - ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 ; LP64-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 @@ -1526,7 +1526,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; LP64F-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4) ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: $x10 = COPY [[LOAD]](p0) - ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 + ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 ; LP64F-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 @@ -1575,7 +1575,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; LP64D-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4) ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: $x10 = COPY [[LOAD]](p0) - ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 + ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 ; LP64D-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll index 27674ada9c28..7c156f5f01fd 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll @@ -20,7 +20,7 @@ define i32 @main() { ; RV32I-NEXT: $x11 = COPY [[C1]](s32) ; RV32I-NEXT: $x12 = COPY [[C2]](s32) ; RV32I-NEXT: $x13 = COPY [[C3]](s32) - ; RV32I-NEXT: PseudoCALL target-flags(riscv-plt) @foo, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; RV32I-NEXT: $x10 = COPY [[COPY]](s32) @@ -40,7 +40,7 @@ define i32 @main() { ; RV64I-NEXT: $x11 = COPY [[C2]](s64) ; RV64I-NEXT: $x12 = COPY [[C3]](s64) ; RV64I-NEXT: $x13 = COPY [[C4]](s64) - ; RV64I-NEXT: PseudoCALL target-flags(riscv-plt) @foo, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir index 747d579f5070..4177a40e3826 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir @@ -19,7 +19,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -63,7 +63,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -107,7 +107,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -145,7 +145,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -184,7 +184,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x12 = COPY %ylo(s32) ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -208,7 +208,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s32) ; CHECK-M-NEXT: $x12 = COPY %ylo(s32) ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -245,7 +245,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -263,7 +263,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -297,7 +297,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -337,7 +337,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -377,7 +377,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -413,7 +413,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -454,7 +454,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s32) ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -480,7 +480,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s32) ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s32) ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -517,7 +517,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -535,7 +535,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir index 09bb86bac45d..492f9530997c 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir @@ -19,7 +19,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -68,7 +68,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -117,7 +117,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -162,7 +162,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -197,7 +197,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -236,7 +236,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x12 = COPY %ylo(s64) ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -260,7 +260,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s64) ; CHECK-M-NEXT: $x12 = COPY %ylo(s64) ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -297,7 +297,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -315,7 +315,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -349,7 +349,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -392,7 +392,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -435,7 +435,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -478,7 +478,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -513,7 +513,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -554,7 +554,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s64) ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -580,7 +580,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s64) ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s64) ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -617,7 +617,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -635,7 +635,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir index 956989480c5b..1e184bd0c112 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir @@ -16,7 +16,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $f10_f = COPY [[COPY]](s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &ceilf, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit-def $f10_f + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &ceilf, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit-def $f10_f ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f ; CHECK-NEXT: $f10_f = COPY [[COPY1]](s32) @@ -39,7 +39,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $f10_f = COPY [[COPY]](s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &floorf, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit-def $f10_f + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &floorf, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit-def $f10_f ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f ; CHECK-NEXT: $f10_f = COPY [[COPY1]](s32) @@ -62,7 +62,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $f10_d = COPY [[COPY]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &ceil, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit-def $f10_d + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &ceil, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit-def $f10_d ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d ; CHECK-NEXT: $f10_d = COPY [[COPY1]](s64) @@ -85,7 +85,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $f10_d = COPY [[COPY]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &floor, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit-def $f10_d + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &floor, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit-def $f10_d ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d ; CHECK-NEXT: $f10_d = COPY [[COPY1]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir index 617471313356..1af5b686a526 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir @@ -11,7 +11,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) @@ -36,7 +36,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) @@ -86,7 +86,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) @@ -112,7 +112,7 @@ body: | ; CHECK-NEXT: $x11 = COPY %hi1(s32) ; CHECK-NEXT: $x12 = COPY %lo2(s32) ; CHECK-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -148,7 +148,7 @@ body: | ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32) ; CHECK-NEXT: $x12 = COPY [[COPY1]](s32) ; CHECK-NEXT: $x13 = COPY [[ASHR1]](s32) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x11 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir index fb41ee5bafc6..478a652dbf82 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir @@ -11,7 +11,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) @@ -36,7 +36,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) @@ -86,7 +86,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) @@ -111,7 +111,7 @@ body: | ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) @@ -137,7 +137,7 @@ body: | ; CHECK-NEXT: $x11 = COPY %hi1(s64) ; CHECK-NEXT: $x12 = COPY %lo2(s64) ; CHECK-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -173,7 +173,7 @@ body: | ; CHECK-NEXT: $x11 = COPY [[ASHR]](s64) ; CHECK-NEXT: $x12 = COPY [[COPY1]](s64) ; CHECK-NEXT: $x13 = COPY [[ASHR1]](s64) - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir index d0929fd19eb9..2e46893b8cf9 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir @@ -46,7 +46,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s32) ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s32) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 @@ -108,7 +108,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s32) ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s32) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 @@ -164,7 +164,7 @@ body: | ; LIBCALL-NEXT: $x11 = COPY [[ASHR]](s32) ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s32) ; LIBCALL-NEXT: $x13 = COPY [[ASHR1]](s32) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11 @@ -222,7 +222,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[AND]](s32) ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s32) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 @@ -278,7 +278,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[AND]](s32) ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s32) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 @@ -330,7 +330,7 @@ body: | ; LIBCALL-NEXT: $x11 = COPY [[C]](s32) ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s32) ; LIBCALL-NEXT: $x13 = COPY [[C1]](s32) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir index c2bf9ff2a61e..29f4458d5f7f 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir @@ -46,7 +46,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s64) ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 @@ -108,7 +108,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s64) ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 @@ -160,7 +160,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; LIBCALL-NEXT: $x11 = COPY [[SEXT_INREG1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 32 @@ -214,7 +214,7 @@ body: | ; LIBCALL-NEXT: $x11 = COPY [[ASHR]](s64) ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s64) ; LIBCALL-NEXT: $x13 = COPY [[ASHR1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x11 @@ -272,7 +272,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[AND]](s64) ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 @@ -328,7 +328,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[AND]](s64) ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 @@ -384,7 +384,7 @@ body: | ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: $x10 = COPY [[AND]](s64) ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 @@ -436,7 +436,7 @@ body: | ; LIBCALL-NEXT: $x11 = COPY [[C]](s64) ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s64) ; LIBCALL-NEXT: $x13 = COPY [[C1]](s64) - ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-plt) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir index cb7f0eaea59b..99ca07d954ff 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir @@ -19,7 +19,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -63,7 +63,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -107,7 +107,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -145,7 +145,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -184,7 +184,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s32) ; CHECK-I-NEXT: $x12 = COPY %ylo(s32) ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -208,7 +208,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s32) ; CHECK-M-NEXT: $x12 = COPY %ylo(s32) ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -245,7 +245,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -263,7 +263,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -297,7 +297,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -337,7 +337,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -377,7 +377,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -413,7 +413,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) @@ -454,7 +454,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s32) ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -480,7 +480,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s32) ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s32) ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -517,7 +517,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 @@ -535,7 +535,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir index fb008bae9024..64458c40f446 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir @@ -19,7 +19,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -68,7 +68,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -117,7 +117,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -162,7 +162,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -197,7 +197,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -236,7 +236,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s64) ; CHECK-I-NEXT: $x12 = COPY %ylo(s64) ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -260,7 +260,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s64) ; CHECK-M-NEXT: $x12 = COPY %ylo(s64) ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -297,7 +297,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -315,7 +315,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -349,7 +349,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -392,7 +392,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -435,7 +435,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -478,7 +478,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -513,7 +513,7 @@ body: | ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) @@ -554,7 +554,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s64) ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -580,7 +580,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s64) ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s64) ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -617,7 +617,7 @@ body: | ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 @@ -635,7 +635,7 @@ body: | ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) - ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/float-select-verify.ll b/llvm/test/CodeGen/RISCV/float-select-verify.ll index b38560fa4136..cf1a2a89229d 100644 --- a/llvm/test/CodeGen/RISCV/float-select-verify.ll +++ b/llvm/test/CodeGen/RISCV/float-select-verify.ll @@ -67,11 +67,11 @@ define dso_local void @buz(i1 %pred, float %a, float %b) { ; CHECK-NEXT: [[FMV_X_W:%[0-9]+]]:gpr = FMV_X_W killed [[PHI1]] ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[FMV_X_W]] - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 ; CHECK-NEXT: $x10 = COPY [[FCVT_L_S]] - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @foo, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 ; CHECK-NEXT: PseudoRET entry: diff --git a/llvm/test/CodeGen/RISCV/live-sp.mir b/llvm/test/CodeGen/RISCV/live-sp.mir index 5df6a79755cb..df72b1ddfebc 100644 --- a/llvm/test/CodeGen/RISCV/live-sp.mir +++ b/llvm/test/CodeGen/RISCV/live-sp.mir @@ -79,7 +79,7 @@ body: | ; CHECK-NEXT: SW renamable $x1, $x2, 4 :: (store (s32) into %ir.a) ; CHECK-NEXT: renamable $x11 = ADDIW killed renamable $x1, 0 ; CHECK-NEXT: $x10 = COPY $x0 - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2 ; CHECK-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.1) ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16 ; CHECK-NEXT: PseudoRET @@ -87,7 +87,7 @@ body: | renamable $x11 = ADDIW killed renamable $x1, 0 ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 $x10 = COPY $x0 - PseudoCALL target-flags(riscv-plt) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2 + PseudoCALL target-flags(riscv-call) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2 ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 PseudoRET diff --git a/llvm/test/CodeGen/RISCV/make-compressible.mir b/llvm/test/CodeGen/RISCV/make-compressible.mir index e526b131a017..91c2d95b5051 100644 --- a/llvm/test/CodeGen/RISCV/make-compressible.mir +++ b/llvm/test/CodeGen/RISCV/make-compressible.mir @@ -550,18 +550,18 @@ body: | ; RV32-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g) ; RV32-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1) ; RV32-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2) - ; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f ; RV64-LABEL: name: load_common_ptr_float ; RV64: liveins: $x16 ; RV64-NEXT: {{ $}} ; RV64-NEXT: renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g) ; RV64-NEXT: renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1) ; RV64-NEXT: renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2) - ; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g) renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1) renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2) - PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f ... --- @@ -578,7 +578,7 @@ body: | ; RV32-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g) ; RV32-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1) ; RV32-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2) - ; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d ; RV64-LABEL: name: load_common_ptr_double ; RV64: liveins: $x16 ; RV64-NEXT: {{ $}} @@ -586,11 +586,11 @@ body: | ; RV64-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g) ; RV64-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1) ; RV64-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2) - ; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g) renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1) renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2) - PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d ... --- @@ -746,18 +746,18 @@ body: | ; RV32-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx) ; RV32-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1) ; RV32-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2) - ; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f ; RV64-LABEL: name: load_large_offset_float ; RV64: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) ; RV64-NEXT: renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) ; RV64-NEXT: renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2) - ; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2) - PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f ... --- @@ -774,7 +774,7 @@ body: | ; RV32-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx) ; RV32-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1) ; RV32-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2) - ; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d ; RV64-LABEL: name: load_large_offset_double ; RV64: liveins: $x10 ; RV64-NEXT: {{ $}} @@ -782,11 +782,11 @@ body: | ; RV64-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx) ; RV64-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1) ; RV64-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2) - ; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2) - PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d ... --- diff --git a/llvm/test/CodeGen/RISCV/mir-target-flags.ll b/llvm/test/CodeGen/RISCV/mir-target-flags.ll index c4c6a1435732..fdc0d894b2ca 100644 --- a/llvm/test/CodeGen/RISCV/mir-target-flags.ll +++ b/llvm/test/CodeGen/RISCV/mir-target-flags.ll @@ -35,7 +35,7 @@ define i32 @caller(i32 %a) nounwind { ; RV32-SMALL: target-flags(riscv-tprel-hi) @t_le ; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_le ; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_le -; RV32-SMALL: target-flags(riscv-plt) @callee +; RV32-SMALL: target-flags(riscv-call) @callee ; ; RV32-MED-LABEL: name: caller ; RV32-MED: target-flags(riscv-got-hi) @g_e @@ -44,16 +44,16 @@ define i32 @caller(i32 %a) nounwind { ; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) ; RV32-MED: target-flags(riscv-tls-gd-hi) @t_un ; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) -; RV32-MED: target-flags(riscv-plt) &__tls_get_addr +; RV32-MED: target-flags(riscv-call) &__tls_get_addr ; RV32-MED: target-flags(riscv-tls-gd-hi) @t_ld ; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) -; RV32-MED: target-flags(riscv-plt) &__tls_get_addr +; RV32-MED: target-flags(riscv-call) &__tls_get_addr ; RV32-MED: target-flags(riscv-tls-got-hi) @t_ie ; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) ; RV32-MED: target-flags(riscv-tprel-hi) @t_le ; RV32-MED-NEXT: target-flags(riscv-tprel-add) @t_le ; RV32-MED-NEXT: target-flags(riscv-tprel-lo) @t_le -; RV32-MED: target-flags(riscv-plt) @callee +; RV32-MED: target-flags(riscv-call) @callee ; %b = load i32, ptr @g_e %c = load i32, ptr @g_i diff --git a/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir b/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir index 19ad7b16e386..7c6253b897ff 100644 --- a/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir +++ b/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir @@ -76,7 +76,7 @@ body: | ; we have to allocate a virtual register to compute it. ; A later run of the the register scavenger won't find an available register ; either so it will have to spill one to the emergency spill slot. - PseudoCALL target-flags(riscv-plt) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 PseudoRET ... diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir index f807c7693332..83fc1fc994cf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir +++ b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir @@ -53,7 +53,7 @@ body: | bb.0 (%ir-block.0): ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 $x10 = ADDI %stack.0.local0, 0 - PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 PseudoRET diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir index 0403ceda8f11..5fbfbc9f37ce 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir @@ -55,6 +55,6 @@ body: | ; we have to allocate a virtual register to compute it. ; A later run of the the register scavenger won't find an available register ; either so it will have to spill one to the emergency spill slot. - PseudoCALL target-flags(riscv-plt) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + PseudoCALL target-flags(riscv-call) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 PseudoRET ... diff --git a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir index bf78329c261f..b4d8805b65bd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir +++ b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir @@ -87,6 +87,6 @@ body: | ; A later run of the the register scavenger won't find available registers ; either so it will have to spill two to the emergency spill slots ; required for this RVV computation. - PseudoCALL target-flags(riscv-plt) @spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + PseudoCALL target-flags(riscv-call) @spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 PseudoRET ... diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir index b8a922a9fb1a..d98e18b22f69 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir @@ -188,7 +188,7 @@ body: | $x10 = ADDI %stack.0.a, 0 $x11 = ADDI %stack.1.b, 0 $x12 = ADDI %stack.2.c, 0 - PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 PseudoRET @@ -233,7 +233,7 @@ body: | $x10 = ADDI %stack.0.a, 0 $x11 = ADDI %stack.1.b, 0 $x12 = ADDI %stack.2.c, 0 - PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 PseudoRET @@ -278,7 +278,7 @@ body: | $x10 = ADDI %stack.0.a, 0 $x11 = ADDI %stack.1.b, 0 $x12 = ADDI %stack.2.c, 0 - PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 PseudoRET diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir index 6d05a8e62ea1..e629727d26c3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir +++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir @@ -189,7 +189,7 @@ body: | ; CHECK-NEXT: renamable $v8 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8) ; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3 /* e8 */, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) ; CHECK-NEXT: $x10 = COPY renamable $x9 - ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 ; CHECK-NEXT: PseudoBR %bb.1 bb.0.entry: successors: %bb.1(0x80000000) @@ -219,7 +219,7 @@ body: | PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 $x10 = COPY renamable $x9 - PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 + PseudoCALL target-flags(riscv-call) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 PseudoBR %bb.1 diff --git a/llvm/test/CodeGen/RISCV/vector-abi.ll b/llvm/test/CodeGen/RISCV/vector-abi.ll index ad371a447438..9e786e576fcb 100644 --- a/llvm/test/CodeGen/RISCV/vector-abi.ll +++ b/llvm/test/CodeGen/RISCV/vector-abi.ll @@ -21,7 +21,7 @@ define void @caller() { ; RV32: SW killed [[ADDI3]], %stack.0, 0 :: (store (s32) into %stack.0) ; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0 ; RV32: $x10 = COPY [[ADDI4]] - ; RV32: PseudoCALL target-flags(riscv-plt) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 + ; RV32: PseudoCALL target-flags(riscv-call) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 ; RV32: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 ; RV32: PseudoRET ; RV64-LABEL: name: caller @@ -41,7 +41,7 @@ define void @caller() { ; RV64: SD killed [[ADDI3]], %stack.0, 0 :: (store (s64) into %stack.0) ; RV64: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0 ; RV64: $x10 = COPY [[ADDI4]] - ; RV64: PseudoCALL target-flags(riscv-plt) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 + ; RV64: PseudoCALL target-flags(riscv-call) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 ; RV64: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 ; RV64: PseudoRET call void @callee(<4 x i8> ) -- GitLab From 4ca1b5e094280ef1af40412e3cfcb62dc3cf15bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Sun, 7 Jan 2024 23:24:06 +0200 Subject: [PATCH 006/652] [clang] [MinGW] Don't look for a GCC in path if the install base has a proper mingw sysroot (#76949) This fixes uses of the MSYS2 clang64 environment compilers, if another set of GCC based compilers are available further back in PATH (which may be explicitly added, or inherited unintentionally from other software installed). (The issue in the clang64 environment can be worked around somewhat by installing *-gcc-compat packages which present aliases named -gcc within the clang64 environment as well.) This fixes https://github.com/msys2/MINGW-packages/issues/11495 and https://github.com/msys2/MINGW-packages/issues/19279. --- clang/lib/Driver/ToolChains/MinGW.cpp | 25 ++++++++++++++++++++++-- clang/test/Driver/mingw-sysroot.cpp | 28 +++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/clang/lib/Driver/ToolChains/MinGW.cpp b/clang/lib/Driver/ToolChains/MinGW.cpp index 65512f16357d..18fc9d4b6807 100644 --- a/clang/lib/Driver/ToolChains/MinGW.cpp +++ b/clang/lib/Driver/ToolChains/MinGW.cpp @@ -471,12 +471,23 @@ findClangRelativeSysroot(const Driver &D, const llvm::Triple &LiteralTriple, return make_error_code(std::errc::no_such_file_or_directory); } +static bool looksLikeMinGWSysroot(const std::string &Directory) { + StringRef Sep = llvm::sys::path::get_separator(); + if (!llvm::sys::fs::exists(Directory + Sep + "include" + Sep + "_mingw.h")) + return false; + if (!llvm::sys::fs::exists(Directory + Sep + "lib" + Sep + "libkernel32.a")) + return false; + return true; +} + toolchains::MinGW::MinGW(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) : ToolChain(D, Triple, Args), CudaInstallation(D, Triple, Args), RocmInstallation(D, Triple, Args) { getProgramPaths().push_back(getDriver().getInstalledDir()); + std::string InstallBase = + std::string(llvm::sys::path::parent_path(getDriver().getInstalledDir())); // The sequence for detecting a sysroot here should be kept in sync with // the testTriple function below. llvm::Triple LiteralTriple = getLiteralTriple(D, getTriple()); @@ -487,13 +498,17 @@ toolchains::MinGW::MinGW(const Driver &D, const llvm::Triple &Triple, else if (llvm::ErrorOr TargetSubdir = findClangRelativeSysroot( getDriver(), LiteralTriple, getTriple(), SubdirName)) Base = std::string(llvm::sys::path::parent_path(TargetSubdir.get())); + // If the install base of Clang seems to have mingw sysroot files directly + // in the toplevel include and lib directories, use this as base instead of + // looking for a triple prefixed GCC in the path. + else if (looksLikeMinGWSysroot(InstallBase)) + Base = InstallBase; else if (llvm::ErrorOr GPPName = findGcc(LiteralTriple, getTriple())) Base = std::string(llvm::sys::path::parent_path( llvm::sys::path::parent_path(GPPName.get()))); else - Base = std::string( - llvm::sys::path::parent_path(getDriver().getInstalledDir())); + Base = InstallBase; Base += llvm::sys::path::get_separator(); findGccLibDir(LiteralTriple); @@ -778,9 +793,15 @@ static bool testTriple(const Driver &D, const llvm::Triple &Triple, if (D.SysRoot.size()) return true; llvm::Triple LiteralTriple = getLiteralTriple(D, Triple); + std::string InstallBase = + std::string(llvm::sys::path::parent_path(D.getInstalledDir())); if (llvm::ErrorOr TargetSubdir = findClangRelativeSysroot(D, LiteralTriple, Triple, SubdirName)) return true; + // If the install base itself looks like a mingw sysroot, we'll use that + // - don't use any potentially unrelated gcc to influence what triple to use. + if (looksLikeMinGWSysroot(InstallBase)) + return false; if (llvm::ErrorOr GPPName = findGcc(LiteralTriple, Triple)) return true; // If we neither found a colocated sysroot or a matching gcc executable, diff --git a/clang/test/Driver/mingw-sysroot.cpp b/clang/test/Driver/mingw-sysroot.cpp index 911dab492707..50152b2ca210 100644 --- a/clang/test/Driver/mingw-sysroot.cpp +++ b/clang/test/Driver/mingw-sysroot.cpp @@ -14,6 +14,12 @@ // RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/x86_64-w64-mingw32 %T/testroot-clang/x86_64-w64-mingw32 // RUN: ln -s %S/Inputs/mingw_arch_tree/usr/i686-w64-mingw32 %T/testroot-clang/i686-w64-mingw32 +// RUN: rm -rf %T/testroot-clang-native +// RUN: mkdir -p %T/testroot-clang-native/bin +// RUN: ln -s %clang %T/testroot-clang-native/bin/clang +// RUN: mkdir -p %T/testroot-clang-native/include/_mingw.h +// RUN: mkdir -p %T/testroot-clang-native/lib/libkernel32.a + // RUN: rm -rf %T/testroot-custom-triple // RUN: mkdir -p %T/testroot-custom-triple/bin // RUN: ln -s %clang %T/testroot-custom-triple/bin/clang @@ -58,6 +64,28 @@ // RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %T/testroot-gcc/bin/x86_64-w64-mingw32-clang -target x86_64-w64-mingw32 -rtlib=platform -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC %s +// If we're executing clang from a directory with what looks like a mingw sysroot, +// with headers in /include and libs in /lib, use that rather than looking +// for another GCC in the path. +// +// Note, this test has a surprising quirk: We're testing with an install directory, +// testroot-clang-native, which lacks the "x86_64-w64-mingw32" subdirectory, it only +// has the include and lib subdirectories without any triple prefix. +// +// Since commit fd15cb935d7aae25ad62bfe06fe9f17cea585978, we avoid using the +// /include and /lib directories when cross compiling. So technically, this +// case testcase only works exactly as expected when running on x86_64 Windows, when +// this target isn't considered cross compiling. +// +// However we do still pass the include directory /x86_64-w64-mingw32/include to +// the -cc1 interface, even if it is missing. Thus, this test looks for this path name, +// that indicates that we did choose the right base, even if this particular directory +// actually doesn't exist here. + +// RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %T/testroot-clang-native/bin/clang -target x86_64-w64-mingw32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CLANG_NATIVE %s +// CHECK_TESTROOT_CLANG_NATIVE: "{{[^"]+}}/testroot-clang-native{{/|\\\\}}x86_64-w64-mingw32{{/|\\\\}}include" + + // If the user requests a different arch via the -m32 option, which changes // x86_64 into i386, check that the driver notices that it can't find a // sysroot for i386 but there is one for i686, and uses that one. -- GitLab From f8c5541f5a6b6e4806f9fb5ab191d4a7e60609c4 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Sun, 7 Jan 2024 14:59:41 -0800 Subject: [PATCH 007/652] [NFC][ObjectSize] Make method public Windows barfs on the 'friend class SizeOffsetType;' statement. Attempt to fix by making the method called by the "friend" class public. --- llvm/include/llvm/Analysis/MemoryBuiltins.h | 28 ++++++++------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/llvm/include/llvm/Analysis/MemoryBuiltins.h b/llvm/include/llvm/Analysis/MemoryBuiltins.h index d080a5956a4d..37ce1518f00c 100644 --- a/llvm/include/llvm/Analysis/MemoryBuiltins.h +++ b/llvm/include/llvm/Analysis/MemoryBuiltins.h @@ -190,7 +190,7 @@ Value *lowerObjectSizeCall( /// SizeOffsetType - A base template class for the object size visitors. Used /// here as a self-documenting way to handle the values rather than using a /// \p std::pair. -template class SizeOffsetType { +template struct SizeOffsetType { public: T Size; T Offset; @@ -213,13 +213,11 @@ public: /// SizeOffsetAPInt - Used by \p ObjectSizeOffsetVisitor, which works with /// \p APInts. -class SizeOffsetAPInt : public SizeOffsetType { - friend class SizeOffsetType; - static bool known(APInt V) { return V.getBitWidth() > 1; } - -public: +struct SizeOffsetAPInt : public SizeOffsetType { SizeOffsetAPInt() = default; SizeOffsetAPInt(APInt Size, APInt Offset) : SizeOffsetType(Size, Offset) {} + + static bool known(APInt V) { return V.getBitWidth() > 1; } }; /// Evaluate the size and offset of an object pointed to by a Value* @@ -274,30 +272,26 @@ private: /// SizeOffsetValue - Used by \p ObjectSizeOffsetEvaluator, which works with /// \p Values. -class SizeOffsetWeakTrackingVH; -class SizeOffsetValue : public SizeOffsetType { - friend class SizeOffsetType; - static bool known(Value *V) { return V != nullptr; } - -public: +struct SizeOffsetWeakTrackingVH; +struct SizeOffsetValue : public SizeOffsetType { SizeOffsetValue() : SizeOffsetType(nullptr, nullptr) {} SizeOffsetValue(Value *Size, Value *Offset) : SizeOffsetType(Size, Offset) {} SizeOffsetValue(const SizeOffsetWeakTrackingVH &SOT); + + static bool known(Value *V) { return V != nullptr; } }; /// SizeOffsetWeakTrackingVH - Used by \p ObjectSizeOffsetEvaluator in a /// \p DenseMap. -class SizeOffsetWeakTrackingVH +struct SizeOffsetWeakTrackingVH : public SizeOffsetType { - friend class SizeOffsetType; - static bool known(WeakTrackingVH V) { return V.pointsToAliveValue(); } - -public: SizeOffsetWeakTrackingVH() : SizeOffsetType(nullptr, nullptr) {} SizeOffsetWeakTrackingVH(Value *Size, Value *Offset) : SizeOffsetType(Size, Offset) {} SizeOffsetWeakTrackingVH(const SizeOffsetValue &SOV) : SizeOffsetType(SOV.Size, SOV.Offset) {} + + static bool known(WeakTrackingVH V) { return V.pointsToAliveValue(); } }; /// Evaluate the size and offset of an object pointed to by a Value*. -- GitLab From 0359acf0f5f04da184386c886d56ee45db7b7be0 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sun, 7 Jan 2024 16:02:52 -0800 Subject: [PATCH 008/652] [ELF,test] Add eh-frame-nonzero-offset-riscv.s for #65966 I plan to define RISCV::relocateAllocate in a subsequent change. Add a test to verify `else if (auto *ehIn = dyn_cast(&sec)) secAddr += ehIn->getParent()->outSecOff;` --- lld/test/ELF/eh-frame-nonzero-offset-riscv.s | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 lld/test/ELF/eh-frame-nonzero-offset-riscv.s diff --git a/lld/test/ELF/eh-frame-nonzero-offset-riscv.s b/lld/test/ELF/eh-frame-nonzero-offset-riscv.s new file mode 100644 index 000000000000..fa78b7686373 --- /dev/null +++ b/lld/test/ELF/eh-frame-nonzero-offset-riscv.s @@ -0,0 +1,53 @@ +// REQUIRES: riscv +// RUN: rm -rf %t && split-file %s %t && cd %t + +// RUN: llvm-mc -filetype=obj -triple=riscv64 a.s -o a.o +// RUN: ld.lld a.o -T eh-frame-non-zero-offset.t -o non-zero +// RUN: llvm-readelf --program-headers --unwind --symbols -x .eh_frame non-zero | FileCheck --check-prefix=NONZERO %s +// RUN: ld.lld a.o -T eh-frame-zero-offset.t -o zero +// RUN: llvm-readelf --program-headers --unwind --symbols -x .eh_frame zero | FileCheck --check-prefix=ZERO %s + +// NONZERO: {{[0-9]+}}: 0000000000000088 {{.*}} __eh_frame_start +// NONZERO-NEXT: {{[0-9]+}}: 00000000000000b4 {{.*}} __eh_frame_end + +// NONZERO: 0x00000088 10000000 00000000 017a5200 01780101 . +// NONZERO-NEXT: 0x00000098 1b0c0200 10000000 18000000 5cffffff . +// NONZERO-NEXT: 0x000000a8 04000000 00000000 00000000 . + +// ZERO: {{[0-9]+}}: 0000000000000008 {{.*}} __eh_frame_start +// ZERO-NEXT: {{[0-9]+}}: 0000000000000034 {{.*}} __eh_frame_end + +// ZERO: 0x00000008 10000000 00000000 017a5200 01780101 . +// ZERO-NEXT: 0x00000018 1b0c0200 10000000 18000000 dcffffff . +// ZERO-NEXT: 0x00000028 04000000 00000000 00000000 . + +//--- eh-frame-non-zero-offset.t +SECTIONS { + .text : { *(.text .text.*) } + .eh_frame : { + /* Padding within .eh_frame */ + . += 128; + __eh_frame_start = .; + *(.eh_frame) ; + __eh_frame_end = .; + } +} + +//--- eh-frame-zero-offset.t +SECTIONS { + .text : { *(.text .text.*) } + .eh_frame : { + __eh_frame_start = .; + *(.eh_frame) ; + __eh_frame_end = .; + } +} + +//--- a.s +.section .text.01, "ax",%progbits +.global f1 +.type f1, %function +f1: +.cfi_startproc +.space 4 +.cfi_endproc -- GitLab From 60c4f82d3c4e9cfc337c360f489d830d0379b04d Mon Sep 17 00:00:00 2001 From: Petr Hosek Date: Sun, 7 Jan 2024 16:07:17 -0800 Subject: [PATCH 009/652] [InstrProfiling] No runtime registration for ELF, COFF, Mach-O and XCOFF (#77225) Whether runtime registration is needed is not dependent on the OS but the file format. For ELF, COFF, Mach-O or XCOFF, we can always use the linker support. This is important for baremetal platforms such as RTOS and UEFI platforms where there is no OS but we still don't want to use runtime registration and rely on linker support instead. --- .../Instrumentation/InstrProfiling.cpp | 10 ++++------ .../InstrProfiling/platform.ll | 3 +++ .../InstrProfiling/profiling.ll | 19 +++++++++---------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp index fe5a0578bd97..a19b14087254 100644 --- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp +++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp @@ -1189,12 +1189,10 @@ static inline Constant *getFuncAddrForProfData(Function *Fn) { } static bool needsRuntimeRegistrationOfSectionRange(const Triple &TT) { - // Don't do this for Darwin. compiler-rt uses linker magic. - if (TT.isOSDarwin()) - return false; - // Use linker script magic to get data/cnts/name start/end. - if (TT.isOSAIX() || TT.isOSLinux() || TT.isOSFreeBSD() || TT.isOSNetBSD() || - TT.isOSSolaris() || TT.isOSFuchsia() || TT.isPS() || TT.isOSWindows()) + // compiler-rt uses linker support to get data/counters/name start/end for + // ELF, COFF, Mach-O and XCOFF. + if (TT.isOSBinFormatELF() || TT.isOSBinFormatCOFF() || + TT.isOSBinFormatMachO() || TT.isOSBinFormatXCOFF()) return false; return true; diff --git a/llvm/test/Instrumentation/InstrProfiling/platform.ll b/llvm/test/Instrumentation/InstrProfiling/platform.ll index 81912f3c0b6a..9c76a5caf2a5 100644 --- a/llvm/test/Instrumentation/InstrProfiling/platform.ll +++ b/llvm/test/Instrumentation/InstrProfiling/platform.ll @@ -8,6 +8,7 @@ ; RUN: opt < %s -mtriple=x86_64-pc-solaris -passes=instrprof -S | FileCheck %s -check-prefixes=SOLARIS,ELF ; RUN: opt < %s -mtriple=x86_64-pc-windows -passes=instrprof -S | FileCheck %s -check-prefix=WINDOWS ; RUN: opt < %s -mtriple=powerpc64-ibm-aix-xcoff -passes=instrprof -S | FileCheck %s -check-prefix=AIX +; RUN: opt < %s -mtriple=arm-elf -passes=instrprof -S | FileCheck %s -check-prefix=BAREMETAL @__profn_foo = private constant [3 x i8] c"foo" ; MACHO-NOT: __profn_foo @@ -46,6 +47,7 @@ declare void @llvm.instrprof.increment(ptr, i64, i32, i32) ; PS4-NOT: define internal void @__llvm_profile_register_functions ; WINDOWS-NOT: define internal void @__llvm_profile_register_functions ; AIX-NOT: define internal void @__llvm_profile_register_functions +; BAREMETAL-NOT: define internal void @__llvm_profile_register_functions ;; PR38340: When dynamic registration is used, we had a bug where we'd register ;; something that's not a __profd_* variable. @@ -57,3 +59,4 @@ declare void @llvm.instrprof.increment(ptr, i64, i32, i32) ; PS4-NOT: define internal void @__llvm_profile_init ; WINDOWS-NOT: define internal void @__llvm_profile_init ; AIX-NOT: define internal void @__llvm_profile_init +; BAREMETAL-NOT: define internal void @__llvm_profile_init diff --git a/llvm/test/Instrumentation/InstrProfiling/profiling.ll b/llvm/test/Instrumentation/InstrProfiling/profiling.ll index caff611b98cc..e7678a9dce08 100644 --- a/llvm/test/Instrumentation/InstrProfiling/profiling.ll +++ b/llvm/test/Instrumentation/InstrProfiling/profiling.ll @@ -1,7 +1,6 @@ ;; Test runtime symbols and various linkages. ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -passes=instrprof -S | FileCheck %s --check-prefixes=MACHO -; RUN: opt < %s -mtriple=x86_64 -passes=instrprof -S | FileCheck %s --check-prefix=ELF_GENERIC ; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=instrprof -S | FileCheck %s --check-prefixes=ELF,ELFRT ; RUN: opt < %s -mtriple=x86_64-unknown-fuchsia -passes=instrprof -S | FileCheck %s --check-prefixes=ELF,ELFRT ; RUN: opt < %s -mtriple=x86_64-scei-ps4 -passes=instrprof -S | FileCheck %s --check-prefixes=ELF,PS @@ -9,12 +8,13 @@ ; RUN: opt < %s -mtriple=x86_64-pc-win32-coff -passes=instrprof -S | FileCheck %s --check-prefixes=COFF ; RUN: opt < %s -mtriple=powerpc64-ibm-aix-xcoff -passes=instrprof -S | FileCheck %s --check-prefixes=XCOFF ; RUN: opt < %s -mtriple=x86_64-pc-freebsd13 -passes=instrprof -S | FileCheck %s --check-prefixes=ELF +; RUN: opt < %s -mtriple=wasm32-unknown-unknown -passes=instrprof -S | FileCheck %s --check-prefix=WASM ; MACHO: @__llvm_profile_runtime = external hidden global i32 -; ELF_GENERIC: @__llvm_profile_runtime = external hidden global i32 ; ELF-NOT: @__llvm_profile_runtime = external global i32 ; XCOFF-NOT: @__llvm_profile_runtime = external hidden global i32 ; COFF: @__llvm_profile_runtime = external hidden global i32 +; WASM: @__llvm_profile_runtime = external hidden global i32 ; ELF: $__profc_foo = comdat nodeduplicate ; ELF: $__profc_foo_weak = comdat nodeduplicate @@ -98,10 +98,10 @@ define available_externally void @foo_extern() { declare void @llvm.instrprof.increment(ptr, i64, i32, i32) ; ELF: @llvm.compiler.used = appending global {{.*}} [{{.*}}ptr @__profd_foo, ptr @__profd_foo_weak, ptr @"__profd_linkage.ll:foo_internal", ptr @__profd_foo_inline, ptr @__profd_foo_extern{{.*}}] -; ELF_GENERIC: @llvm.compiler.used = appending global [6 x ptr] [ptr @__llvm_profile_runtime, ptr @__profd_foo, ptr @__profd_foo_weak, ptr @"__profd_linkage.ll:foo_internal", ptr @__profd_foo_inline, ptr @__profd_foo_extern] ; MACHO: @llvm.compiler.used = appending global [6 x ptr] [ptr @__llvm_profile_runtime_user, ptr @__profd_foo, {{.*}} ; COFF: @llvm.compiler.used = appending global [6 x ptr] [ptr @__llvm_profile_runtime_user, ptr @__profd_foo, ptr @__profd_foo_weak, ptr @"__profd_linkage.ll:foo_internal", ptr @__profd_foo_inline, ptr @__profd_foo_extern] ; XCOFF: @llvm.used = appending global [6 x ptr] [ptr @__profd_foo, ptr @__profd_foo_weak, ptr @"__profd_linkage.ll:foo_internal", ptr @__profd_foo_inline, ptr @__profd_foo_extern, ptr @__llvm_prf_nm] +; WASM: @llvm.used = appending global [7 x ptr] [ptr @__llvm_profile_runtime_user, ptr @__profd_foo, ptr @__profd_foo_weak, ptr @"__profd_linkage.ll:foo_internal", ptr @__profd_foo_inline, ptr @__profd_foo_extern, ptr @__llvm_prf_nm] ; MACHO: define linkonce_odr hidden i32 @__llvm_profile_runtime_user() {{.*}} { ; MACHO: %[[REG:.*]] = load i32, ptr @__llvm_profile_runtime @@ -114,12 +114,11 @@ declare void @llvm.instrprof.increment(ptr, i64, i32, i32) ; PS: %[[REG:.*]] = load i32, ptr @__llvm_profile_runtime ; XCOFF-NOT: define .* __llvm_profile_runtime_user -; ELF_GENERIC: define internal void @__llvm_profile_register_functions() unnamed_addr { -; ELF_GENERIC-NEXT: call void @__llvm_profile_register_function(ptr @__llvm_profile_runtime) -; ELF_GENERIC-NEXT: call void @__llvm_profile_register_function(ptr @__profd_foo) -; ELF_GENERIC-NEXT: call void @__llvm_profile_register_function(ptr @__profd_foo_weak) -; ELF_GENERIC: call void @__llvm_profile_register_names_function(ptr @__llvm_prf_nm -; ELF_GENERIC-NEXT: ret void -; ELF_GENERIC-NEXT: } +; WASM: define internal void @__llvm_profile_register_functions() unnamed_addr { +; WASM-NEXT: call void @__llvm_profile_register_function(ptr @__profd_foo) +; WASM-NEXT: call void @__llvm_profile_register_function(ptr @__profd_foo_weak) +; WASM: call void @__llvm_profile_register_names_function(ptr @__llvm_prf_nm +; WASM-NEXT: ret void +; WASM-NEXT: } ; XCOFF-NOT: internal void @__llvm_profile_register_functions() -- GitLab From c7cae61b289fd12171a2da80a6e90b867ee1c4fc Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sun, 7 Jan 2024 19:40:34 -0500 Subject: [PATCH 010/652] [NFC] Remove trailing whitespace in `llvm/lib/Target/AMDGPU/VOP2Instructions.td` --- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 0aa62ea77b11..ecee61daa1c8 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -1300,7 +1300,7 @@ class VOP2_DPP8 op, VOP2_Pseudo ps, let OtherPredicates = ps.OtherPredicates; } - + class VOP2_DPP8_Gen op, VOP2_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> : VOP2_DPP8 { -- GitLab From d6aef863d83e5a352e78a0211a935a59efda0a0c Mon Sep 17 00:00:00 2001 From: Chen Zheng Date: Mon, 8 Jan 2024 09:37:40 +0800 Subject: [PATCH 011/652] [PowerPC] make LR/LR8 CTR/CTR8 aliased (#76926) fixes https://github.com/llvm/llvm-project/issues/47156 fixes https://github.com/llvm/llvm-project/issues/47155 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 9 ++++++--- llvm/test/CodeGen/PowerPC/pr47155-47156.ll | 12 ++++++++---- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 375e63654db1..8a37e40414ee 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -270,12 +270,15 @@ def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; // Link register def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; -//let Aliases = [LR] in -def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; +def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]> { + let Aliases = [LR]; +} // Count register def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; -def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; +def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]> { + let Aliases = [CTR]; +} // VRsave register def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; diff --git a/llvm/test/CodeGen/PowerPC/pr47155-47156.ll b/llvm/test/CodeGen/PowerPC/pr47155-47156.ll index 26aa92e83f7a..02f287634578 100644 --- a/llvm/test/CodeGen/PowerPC/pr47155-47156.ll +++ b/llvm/test/CodeGen/PowerPC/pr47155-47156.ll @@ -9,9 +9,11 @@ define void @pr47155() { ; CHECK-NEXT: pr47155:%bb.0 entry ; CHECK: SU(0): INLINEASM &"mtlr 31"{{.*}}implicit-def early-clobber $lr ; CHECK: Successors: +; CHECK-NEXT: SU(1): Out Latency=0 ; CHECK-NEXT: SU(1): Ord Latency=0 Barrier ; CHECK-NEXT: SU(1): INLINEASM &"mtlr 31"{{.*}}implicit-def early-clobber $lr8 ; CHECK: Predecessors: +; CHECK-NEXT: SU(0): Out Latency=0 ; CHECK-NEXT: SU(0): Ord Latency=0 Barrier ; CHECK-NEXT: ExitSU: entry: @@ -25,11 +27,13 @@ define void @pr47156(ptr %fn) { ; CHECK: ********** MI Scheduling ********** ; CHECK-NEXT: pr47156:%bb.0 entry ; CHECK: SU(0): INLINEASM &"mtctr 31"{{.*}}implicit-def early-clobber $ctr -; CHECK-NOT: Successors: -; CHECK-NOT: Predecessors: -; CHECK: SU(1): MTCTR8 renamable $x3, implicit-def $ctr8 ; CHECK: Successors: -; CHECK-NEXT: ExitSU: +; CHECK-NEXT: SU(1): Out Latency=0 +; CHECK-NEXT: SU(1): MTCTR8 renamable $x3, implicit-def $ctr8 +; CHECK: Predecessors: +; CHECK-NEXT: SU(0): Out Latency=0 +; CHECK-NEXT: Successors: +; CHECK-NEXT: ExitSU: ; CHECK-NEXT: SU(2): entry: call void asm sideeffect "mtctr 31", "~{ctr}"() -- GitLab From 5034994134bbec92c1f1116c56008ac504f7d763 Mon Sep 17 00:00:00 2001 From: Haocong Lu <74847248+Luhaocong@users.noreply.github.com> Date: Mon, 8 Jan 2024 09:50:36 +0800 Subject: [PATCH 012/652] [Sema] Warning for _Float16 passed to format specifier '%f' (#74439) According to https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2844.pdf, default argument promotions for _FloatN types has been removed. A warning is needed to notice user to promote _Float16 to double explicitly, and then pass it to format specifier '%f', which is consistent with GCC. Fixes: https://github.com/llvm/llvm-project/issues/68538 --- clang/lib/AST/FormatString.cpp | 1 - clang/test/Sema/attr-format.c | 7 +++++++ clang/test/SemaCXX/attr-format.cpp | 1 + clang/test/SemaCXX/format-strings-scanf.cpp | 16 ++++++++++------ 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/clang/lib/AST/FormatString.cpp b/clang/lib/AST/FormatString.cpp index e0c9e18cfe3a..c5d14b4af7ff 100644 --- a/clang/lib/AST/FormatString.cpp +++ b/clang/lib/AST/FormatString.cpp @@ -488,7 +488,6 @@ ArgType::matchesType(ASTContext &C, QualType argTy) const { return NoMatchPromotionTypeConfusion; break; case BuiltinType::Half: - case BuiltinType::Float16: case BuiltinType::Float: if (T == C.DoubleTy) return MatchPromotion; diff --git a/clang/test/Sema/attr-format.c b/clang/test/Sema/attr-format.c index 1f4c864d4f78..bdfd8425c4e9 100644 --- a/clang/test/Sema/attr-format.c +++ b/clang/test/Sema/attr-format.c @@ -16,6 +16,8 @@ typedef const char *xpto; void j(xpto c, va_list list) __attribute__((format(printf, 1, 0))); // no-error void k(xpto c) __attribute__((format(printf, 1, 0))); // no-error +void l(char *a, _Float16 b) __attribute__((format(printf, 1, 2))); // expected-warning {{GCC requires a function with the 'format' attribute to be variadic}} + void y(char *str) __attribute__((format(strftime, 1, 0))); // no-error void z(char *str, int c, ...) __attribute__((format(strftime, 1, 2))); // expected-error {{strftime format attribute requires 3rd parameter to be 0}} @@ -93,6 +95,11 @@ void call_nonvariadic(void) { d3("%s", 123); // expected-warning{{format specifies type 'char *' but the argument has type 'int'}} } +void call_no_default_promotion(void) { + a("%f", (_Float16)1.0); // expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} + l("%f", (_Float16)1.0); // expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} +} + __attribute__((format(printf, 1, 2))) void forward_fixed(const char *fmt, _Bool b, char i, short j, int k, float l, double m) { // expected-warning{{GCC requires a function with the 'format' attribute to be variadic}} forward_fixed(fmt, b, i, j, k, l, m); diff --git a/clang/test/SemaCXX/attr-format.cpp b/clang/test/SemaCXX/attr-format.cpp index adc05fc46776..4509c3a95e8e 100644 --- a/clang/test/SemaCXX/attr-format.cpp +++ b/clang/test/SemaCXX/attr-format.cpp @@ -81,6 +81,7 @@ void do_format() { format("%c %c %hhd %hd %d\n", (char)'a', 'a', 'a', (short)123, (int)123); format("%f %f %f\n", (__fp16)123.f, 123.f, 123.); + format("%f", (_Float16)123.f);// expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} format("%Lf", (__fp16)123.f); // expected-warning{{format specifies type 'long double' but the argument has type '__fp16'}} format("%Lf", 123.f); // expected-warning{{format specifies type 'long double' but the argument has type 'float'}} format("%hhi %hhu %hi %hu %i %u", b, b, b, b, b, b); diff --git a/clang/test/SemaCXX/format-strings-scanf.cpp b/clang/test/SemaCXX/format-strings-scanf.cpp index 25fe5346791a..406c2069e28c 100644 --- a/clang/test/SemaCXX/format-strings-scanf.cpp +++ b/clang/test/SemaCXX/format-strings-scanf.cpp @@ -22,6 +22,7 @@ union bag { unsigned long long ull; signed long long sll; __fp16 f16; + _Float16 Float16; float ff; double fd; long double fl; @@ -51,18 +52,21 @@ void test(void) { // expected-warning@+1{{format specifies type 'int *' but the argument has type 'short *'}} scan("%hhi %i %li", &b.ss, &b.ss, &b.ss); - // expected-warning@+3{{format specifies type 'float *' but the argument has type '__fp16 *'}} + // expected-warning@+4{{format specifies type 'float *' but the argument has type '__fp16 *'}} + // expected-warning@+3{{format specifies type 'float *' but the argument has type '_Float16 *'}} // expected-warning@+2{{format specifies type 'float *' but the argument has type 'double *'}} // expected-warning@+1{{format specifies type 'float *' but the argument has type 'long double *'}} - scan("%f %f %f", &b.f16, &b.fd, &b.fl); + scan("%f %f %f %f", &b.f16, &b.Float16, &b.fd, &b.fl); - // expected-warning@+3{{format specifies type 'double *' but the argument has type '__fp16 *'}} + // expected-warning@+4{{format specifies type 'double *' but the argument has type '__fp16 *'}} + // expected-warning@+3{{format specifies type 'double *' but the argument has type '_Float16 *'}} // expected-warning@+2{{format specifies type 'double *' but the argument has type 'float *'}} // expected-warning@+1{{format specifies type 'double *' but the argument has type 'long double *'}} - scan("%lf %lf %lf", &b.f16, &b.ff, &b.fl); + scan("%lf %lf %lf %lf", &b.f16, &b.Float16, &b.ff, &b.fl); - // expected-warning@+3{{format specifies type 'long double *' but the argument has type '__fp16 *'}} + // expected-warning@+4{{format specifies type 'long double *' but the argument has type '__fp16 *'}} + // expected-warning@+3{{format specifies type 'long double *' but the argument has type '_Float16 *'}} // expected-warning@+2{{format specifies type 'long double *' but the argument has type 'float *'}} // expected-warning@+1{{format specifies type 'long double *' but the argument has type 'double *'}} - scan("%Lf %Lf %Lf", &b.f16, &b.ff, &b.fd); + scan("%Lf %Lf %Lf %Lf", &b.f16, &b.Float16, &b.ff, &b.fd); } -- GitLab From 78550bef98347bccbf0e8e5fb66dc59718fc35ec Mon Sep 17 00:00:00 2001 From: Petr Hosek Date: Sun, 7 Jan 2024 18:13:39 -0800 Subject: [PATCH 013/652] [CMake] Include riscv32-unknown-elf runtimes in Fuchsia toolchain (#76849) This contains compiler-rt builtins and llvm-libc for baremetal use. Differential Revision: https://reviews.llvm.org/D155337 --- clang/cmake/caches/Fuchsia-stage2.cmake | 38 ++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/clang/cmake/caches/Fuchsia-stage2.cmake b/clang/cmake/caches/Fuchsia-stage2.cmake index c4673c8a54c5..eee37c5e7901 100644 --- a/clang/cmake/caches/Fuchsia-stage2.cmake +++ b/clang/cmake/caches/Fuchsia-stage2.cmake @@ -6,7 +6,7 @@ set(LLVM_TARGETS_TO_BUILD X86;ARM;AArch64;RISCV CACHE STRING "") set(PACKAGE_VENDOR Fuchsia CACHE STRING "") -set(_FUCHSIA_ENABLE_PROJECTS "bolt;clang;clang-tools-extra;lld;llvm;polly") +set(_FUCHSIA_ENABLE_PROJECTS "bolt;clang;clang-tools-extra;libc;lld;llvm;polly") set(LLVM_ENABLE_RUNTIMES "compiler-rt;libcxx;libcxxabi;libunwind" CACHE STRING "") set(LLVM_ENABLE_BACKTRACES OFF CACHE BOOL "") @@ -22,8 +22,11 @@ set(LLVM_ENABLE_TERMINFO OFF CACHE BOOL "") set(LLVM_ENABLE_UNWIND_TABLES OFF CACHE BOOL "") set(LLVM_ENABLE_Z3_SOLVER OFF CACHE BOOL "") set(LLVM_ENABLE_ZLIB ON CACHE BOOL "") +set(LLVM_FORCE_BUILD_RUNTIME ON CACHE BOOL "") set(LLVM_INCLUDE_DOCS OFF CACHE BOOL "") set(LLVM_INCLUDE_EXAMPLES OFF CACHE BOOL "") +set(LLVM_LIBC_FULL_BUILD ON CACHE BOOL "") +set(LIBC_HDRGEN_ONLY ON CACHE BOOL "") set(LLVM_STATIC_LINK_CXX_STDLIB ON CACHE BOOL "") set(LLVM_USE_RELATIVE_PATHS_IN_FILES ON CACHE BOOL "") set(LLDB_ENABLE_CURSES OFF CACHE BOOL "") @@ -297,6 +300,39 @@ if(FUCHSIA_SDK) set(LLVM_RUNTIME_MULTILIB_hwasan+noexcept_TARGETS "aarch64-unknown-fuchsia;riscv64-unknown-fuchsia" CACHE STRING "") endif() +foreach(target riscv32-unknown-elf) + list(APPEND BUILTIN_TARGETS "${target}") + set(BUILTINS_${target}_CMAKE_SYSTEM_NAME Generic CACHE STRING "") + set(BUILTINS_${target}_CMAKE_SYSTEM_PROCESSOR RISCV CACHE STRING "") + set(BUILTINS_${target}_CMAKE_SYSROOT "" CACHE STRING "") + set(BUILTINS_${target}_CMAKE_BUILD_TYPE RelWithDebInfo CACHE STRING "") + foreach(lang C;CXX;ASM) + set(BUILTINS_${target}_CMAKE_${lang}_FLAGS "--target=${target} -march=rv32imafc -mabi=ilp32f" CACHE STRING "") + endforeach() + foreach(type SHARED;MODULE;EXE) + set(BUILTINS_${target}_CMAKE_${type}_LINKER_FLAGS "-fuse-ld=lld" CACHE STRING "") + endforeach() + set(BUILTINS_${target}_COMPILER_RT_BAREMETAL_BUILD ON CACHE BOOL "") + + list(APPEND RUNTIME_TARGETS "${target}") + set(RUNTIMES_${target}_CMAKE_SYSTEM_NAME Generic CACHE STRING "") + set(RUNTIMES_${target}_CMAKE_SYSTEM_PROCESSOR RISCV CACHE STRING "") + set(RUNTIMES_${target}_CMAKE_SYSROOT "" CACHE STRING "") + set(RUNTIMES_${target}_CMAKE_BUILD_TYPE RelWithDebInfo CACHE STRING "") + set(RUNTIMES_${target}_CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY CACHE STRING "") + foreach(lang C;CXX;ASM) + set(RUNTIMES_${target}_CMAKE_${lang}_FLAGS "--target=${target} -march=rv32imafc -mabi=ilp32f" CACHE STRING "") + endforeach() + foreach(type SHARED;MODULE;EXE) + set(RUNTIMES_${target}_CMAKE_${type}_LINKER_FLAGS "-fuse-ld=lld" CACHE STRING "") + endforeach() + set(RUNTIMES_${target}_LLVM_LIBC_FULL_BUILD ON CACHE BOOL "") + set(RUNTIMES_${target}_LIBC_ENABLE_USE_BY_CLANG ON CACHE BOOL "") + set(RUNTIMES_${target}_LLVM_INCLUDE_TESTS OFF CACHE BOOL "") + set(RUNTIMES_${target}_LLVM_ENABLE_ASSERTIONS OFF CACHE BOOL "") + set(RUNTIMES_${target}_LLVM_ENABLE_RUNTIMES "libc" CACHE STRING "") +endforeach() + set(LLVM_BUILTIN_TARGETS "${BUILTIN_TARGETS}" CACHE STRING "") set(LLVM_RUNTIME_TARGETS "${RUNTIME_TARGETS}" CACHE STRING "") -- GitLab From 225e2704af3c53bc0c4ee6bf92f32ace54d10fbc Mon Sep 17 00:00:00 2001 From: Kai Luo Date: Mon, 8 Jan 2024 10:10:02 +0800 Subject: [PATCH 014/652] [PowerPC] Precommit test for lowering llvm.trap on ppc64le. NFC. --- llvm/test/CodeGen/PowerPC/intrinsic-trap.ll | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/intrinsic-trap.ll diff --git a/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll new file mode 100644 index 000000000000..b02eb5d8fd27 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll @@ -0,0 +1,10 @@ +; REQUIRES: asserts +; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64le-- < %s 2>&1 | FileCheck %s +; CHECK: Bad machine code: Non-terminator instruction after the first terminator + +define i32 @test() { + call void @llvm.trap() + ret i32 0 +} + +declare void @llvm.trap() -- GitLab From b58a97d6aea12a30e2d1b01c6289abb2fd061f0b Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 8 Jan 2024 11:04:56 +0800 Subject: [PATCH 015/652] [RISCV][NFC] Move Zawrs/Zacas implementation to RISCVInstrInfoZa.td (#76940) To keep the structure of TableGen files clear. The definitions are simplified by the way. --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 17 +-------- llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 12 +------ llvm/lib/Target/RISCV/RISCVInstrInfoZa.td | 44 +++++++++++++++++++++++ 3 files changed, 46 insertions(+), 27 deletions(-) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 35e8edf5d2fa..2f4744529469 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -729,22 +729,6 @@ def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">, let imm12 = 0b110000000000; } -let Predicates = [HasStdExtZawrs] in { -def WRS_NTO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.nto", "">, - Sched<[]> { - let rs1 = 0; - let rd = 0; - let imm12 = 0b000000001101; -} - -def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">, - Sched<[]> { - let rs1 = 0; - let rd = 0; - let imm12 = 0b000000011101; -} -} // Predicates = [HasStdExtZawrs] - } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 def CSRRW : CSR_ir<0b001, "csrrw">; @@ -2095,6 +2079,7 @@ include "RISCVInstrInfoM.td" // Atomic include "RISCVInstrInfoA.td" +include "RISCVInstrInfoZa.td" // Scalar FP include "RISCVInstrInfoF.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index c8301fcc6b93..4d0567e41abc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -7,8 +7,7 @@ //===----------------------------------------------------------------------===// // // This file describes the RISC-V instructions from the standard 'A', Atomic -// Instructions extension as well as the experimental 'Zacas' (Atomic -// Compare-and-Swap) extension. +// Instructions extension. // //===----------------------------------------------------------------------===// @@ -96,15 +95,6 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">, Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>; } // Predicates = [HasStdExtA, IsRV64] -let Predicates = [HasStdExtZacas] in { -defm AMOCAS_W : AMO_rr_aq_rl<0b00101, 0b010, "amocas.w">; -defm AMOCAS_D : AMO_rr_aq_rl<0b00101, 0b011, "amocas.d">; -} // Predicates = [HasStdExtZacas] - -let Predicates = [HasStdExtZacas, IsRV64] in { -defm AMOCAS_Q : AMO_rr_aq_rl<0b00101, 0b100, "amocas.q">; -} // Predicates = [HasStdExtZacas, IsRV64] - //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td new file mode 100644 index 000000000000..a09f5715b24f --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td @@ -0,0 +1,44 @@ +//===-- RISCVInstrInfoZa.td - RISC-V Atomic instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard atomic 'Za*' +// extensions: +// - Zawrs (v1.0) : Wait-on-Reservation-Set. +// - Zacas (v1.0-rc1) : Atomic Compare-and-Swap. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Zacas (Atomic Compare-and-Swap) +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZacas] in { +defm AMOCAS_W : AMO_rr_aq_rl<0b00101, 0b010, "amocas.w">; +defm AMOCAS_D : AMO_rr_aq_rl<0b00101, 0b011, "amocas.d">; +} // Predicates = [HasStdExtZacas] + +let Predicates = [HasStdExtZacas, IsRV64] in { +defm AMOCAS_Q : AMO_rr_aq_rl<0b00101, 0b100, "amocas.q">; +} // Predicates = [HasStdExtZacas, IsRV64] + +//===----------------------------------------------------------------------===// +// Zawrs (Wait-on-Reservation-Set) +//===----------------------------------------------------------------------===// + +let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in +class WRSInst funct12, string opcodestr> + : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> { + let rs1 = 0; + let rd = 0; + let imm12 = funct12; +} + +let Predicates = [HasStdExtZawrs] in { +def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>; +def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>; +} // Predicates = [HasStdExtZawrs] -- GitLab From a90ed3e8a4ea8c5238fd660bbac0371366afe3b5 Mon Sep 17 00:00:00 2001 From: Petr Hosek Date: Mon, 8 Jan 2024 03:29:30 +0000 Subject: [PATCH 016/652] Revert "[CMake] Include riscv32-unknown-elf runtimes in Fuchsia toolchain (#76849)" This reverts commit 78550bef98347bccbf0e8e5fb66dc59718fc35ec since it broke the two stage build. --- clang/cmake/caches/Fuchsia-stage2.cmake | 38 +------------------------ 1 file changed, 1 insertion(+), 37 deletions(-) diff --git a/clang/cmake/caches/Fuchsia-stage2.cmake b/clang/cmake/caches/Fuchsia-stage2.cmake index eee37c5e7901..c4673c8a54c5 100644 --- a/clang/cmake/caches/Fuchsia-stage2.cmake +++ b/clang/cmake/caches/Fuchsia-stage2.cmake @@ -6,7 +6,7 @@ set(LLVM_TARGETS_TO_BUILD X86;ARM;AArch64;RISCV CACHE STRING "") set(PACKAGE_VENDOR Fuchsia CACHE STRING "") -set(_FUCHSIA_ENABLE_PROJECTS "bolt;clang;clang-tools-extra;libc;lld;llvm;polly") +set(_FUCHSIA_ENABLE_PROJECTS "bolt;clang;clang-tools-extra;lld;llvm;polly") set(LLVM_ENABLE_RUNTIMES "compiler-rt;libcxx;libcxxabi;libunwind" CACHE STRING "") set(LLVM_ENABLE_BACKTRACES OFF CACHE BOOL "") @@ -22,11 +22,8 @@ set(LLVM_ENABLE_TERMINFO OFF CACHE BOOL "") set(LLVM_ENABLE_UNWIND_TABLES OFF CACHE BOOL "") set(LLVM_ENABLE_Z3_SOLVER OFF CACHE BOOL "") set(LLVM_ENABLE_ZLIB ON CACHE BOOL "") -set(LLVM_FORCE_BUILD_RUNTIME ON CACHE BOOL "") set(LLVM_INCLUDE_DOCS OFF CACHE BOOL "") set(LLVM_INCLUDE_EXAMPLES OFF CACHE BOOL "") -set(LLVM_LIBC_FULL_BUILD ON CACHE BOOL "") -set(LIBC_HDRGEN_ONLY ON CACHE BOOL "") set(LLVM_STATIC_LINK_CXX_STDLIB ON CACHE BOOL "") set(LLVM_USE_RELATIVE_PATHS_IN_FILES ON CACHE BOOL "") set(LLDB_ENABLE_CURSES OFF CACHE BOOL "") @@ -300,39 +297,6 @@ if(FUCHSIA_SDK) set(LLVM_RUNTIME_MULTILIB_hwasan+noexcept_TARGETS "aarch64-unknown-fuchsia;riscv64-unknown-fuchsia" CACHE STRING "") endif() -foreach(target riscv32-unknown-elf) - list(APPEND BUILTIN_TARGETS "${target}") - set(BUILTINS_${target}_CMAKE_SYSTEM_NAME Generic CACHE STRING "") - set(BUILTINS_${target}_CMAKE_SYSTEM_PROCESSOR RISCV CACHE STRING "") - set(BUILTINS_${target}_CMAKE_SYSROOT "" CACHE STRING "") - set(BUILTINS_${target}_CMAKE_BUILD_TYPE RelWithDebInfo CACHE STRING "") - foreach(lang C;CXX;ASM) - set(BUILTINS_${target}_CMAKE_${lang}_FLAGS "--target=${target} -march=rv32imafc -mabi=ilp32f" CACHE STRING "") - endforeach() - foreach(type SHARED;MODULE;EXE) - set(BUILTINS_${target}_CMAKE_${type}_LINKER_FLAGS "-fuse-ld=lld" CACHE STRING "") - endforeach() - set(BUILTINS_${target}_COMPILER_RT_BAREMETAL_BUILD ON CACHE BOOL "") - - list(APPEND RUNTIME_TARGETS "${target}") - set(RUNTIMES_${target}_CMAKE_SYSTEM_NAME Generic CACHE STRING "") - set(RUNTIMES_${target}_CMAKE_SYSTEM_PROCESSOR RISCV CACHE STRING "") - set(RUNTIMES_${target}_CMAKE_SYSROOT "" CACHE STRING "") - set(RUNTIMES_${target}_CMAKE_BUILD_TYPE RelWithDebInfo CACHE STRING "") - set(RUNTIMES_${target}_CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY CACHE STRING "") - foreach(lang C;CXX;ASM) - set(RUNTIMES_${target}_CMAKE_${lang}_FLAGS "--target=${target} -march=rv32imafc -mabi=ilp32f" CACHE STRING "") - endforeach() - foreach(type SHARED;MODULE;EXE) - set(RUNTIMES_${target}_CMAKE_${type}_LINKER_FLAGS "-fuse-ld=lld" CACHE STRING "") - endforeach() - set(RUNTIMES_${target}_LLVM_LIBC_FULL_BUILD ON CACHE BOOL "") - set(RUNTIMES_${target}_LIBC_ENABLE_USE_BY_CLANG ON CACHE BOOL "") - set(RUNTIMES_${target}_LLVM_INCLUDE_TESTS OFF CACHE BOOL "") - set(RUNTIMES_${target}_LLVM_ENABLE_ASSERTIONS OFF CACHE BOOL "") - set(RUNTIMES_${target}_LLVM_ENABLE_RUNTIMES "libc" CACHE STRING "") -endforeach() - set(LLVM_BUILTIN_TARGETS "${BUILTIN_TARGETS}" CACHE STRING "") set(LLVM_RUNTIME_TARGETS "${RUNTIME_TARGETS}" CACHE STRING "") -- GitLab From f22cde10e7cc711bba9f43d7529ea6c1394c5b48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ningning=20Shi=28=E5=8F=B2=E5=AE=81=E5=AE=81=29?= Date: Mon, 8 Jan 2024 11:46:20 +0800 Subject: [PATCH 017/652] [GlobalISel][NFC]Delete the comments of XXLegalizerInfo (#76918) Delete the LegalizerInfo comments of AArch64/AMD64/ARM/M68k/RISCV/x86, they are copied from register bank. --- llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h | 1 - llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 1 - llvm/lib/Target/ARM/ARMLegalizerInfo.h | 1 - llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h | 1 - llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h | 1 - llvm/lib/Target/X86/GISel/X86LegalizerInfo.h | 1 - 6 files changed, 6 deletions(-) diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h index e96ec6db3a1b..c62a9d847c52 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h @@ -23,7 +23,6 @@ namespace llvm { class AArch64Subtarget; -/// This class provides the information for the target register banks. class AArch64LegalizerInfo : public LegalizerInfo { public: AArch64LegalizerInfo(const AArch64Subtarget &ST); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h index 1fa064891a2d..56aabd4f6ab7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h @@ -27,7 +27,6 @@ class MachineIRBuilder; namespace AMDGPU { struct ImageDimIntrinsicInfo; } -/// This class provides the information for the target register banks. class AMDGPULegalizerInfo final : public LegalizerInfo { const GCNSubtarget &ST; diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.h b/llvm/lib/Target/ARM/ARMLegalizerInfo.h index 3636cc6402b8..d6ce4eb1055b 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.h +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.h @@ -23,7 +23,6 @@ namespace llvm { class ARMSubtarget; -/// This class provides the information for the target register banks. class ARMLegalizerInfo : public LegalizerInfo { public: ARMLegalizerInfo(const ARMSubtarget &ST); diff --git a/llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h b/llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h index a10401ed1a9a..cbe30ec494c9 100644 --- a/llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h +++ b/llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h @@ -20,7 +20,6 @@ namespace llvm { class M68kSubtarget; -/// This struct provides the information for the target register banks. struct M68kLegalizerInfo : public LegalizerInfo { public: M68kLegalizerInfo(const M68kSubtarget &ST); diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h index 4335bd0cbbff..f3ec6be16734 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h @@ -21,7 +21,6 @@ class GISelChangeObserver; class MachineIRBuilder; class RISCVSubtarget; -/// This class provides the information for the target register banks. class RISCVLegalizerInfo : public LegalizerInfo { const RISCVSubtarget &STI; const unsigned XLen; diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h index 1f69feceae27..12134f7b00f1 100644 --- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h +++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h @@ -21,7 +21,6 @@ namespace llvm { class X86Subtarget; class X86TargetMachine; -/// This class provides the information for the target register banks. class X86LegalizerInfo : public LegalizerInfo { private: /// Keep a reference to the X86Subtarget around so that we can -- GitLab From ce944597e43ae4f77260d4683f8d6535947fb0a2 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Sun, 7 Jan 2024 23:00:39 -0500 Subject: [PATCH 018/652] [gn] port 92e243173c09 --- llvm/utils/gn/secondary/libcxx/src/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/libcxx/src/BUILD.gn b/llvm/utils/gn/secondary/libcxx/src/BUILD.gn index c1211bb384d3..095cd5bb5b7c 100644 --- a/llvm/utils/gn/secondary/libcxx/src/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/src/BUILD.gn @@ -122,6 +122,7 @@ cxx_sources = [ "condition_variable_destructor.cpp", "error_category.cpp", "exception.cpp", + "fstream.cpp", "functional.cpp", "future.cpp", "hash.cpp", -- GitLab From 1dfb9498333a6c7c6ac012eb70dc593f5165a025 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sun, 7 Jan 2024 21:36:33 -0800 Subject: [PATCH 019/652] [ELF] Improve OVERLAY tests Also test two issues: * When the start address is `.`, subsequent sections don't share the address of the first overlay section. * When the first overlay section is empty and discardable, `p_paddr` is incorrectly zero. This is because a discarded section has a zero address, causing `prev->getLMA() + prev->size` where `prev` refers to the first section to evaluate to zero. --- lld/test/ELF/linkerscript/overlay-reject.test | 13 --- .../ELF/linkerscript/overlay-reject2.test | 17 --- lld/test/ELF/linkerscript/overlay.test | 100 ++++++++++++++---- 3 files changed, 80 insertions(+), 50 deletions(-) delete mode 100644 lld/test/ELF/linkerscript/overlay-reject.test delete mode 100644 lld/test/ELF/linkerscript/overlay-reject2.test diff --git a/lld/test/ELF/linkerscript/overlay-reject.test b/lld/test/ELF/linkerscript/overlay-reject.test deleted file mode 100644 index fa8a2be37aed..000000000000 --- a/lld/test/ELF/linkerscript/overlay-reject.test +++ /dev/null @@ -1,13 +0,0 @@ -# REQUIRES: x86 -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux /dev/null -o %t.o -# RUN: not ld.lld %t.o --script %s -o /dev/null 2>&1 | FileCheck %s - -# CHECK: {{.*}}.test:{{.*}}: { expected, but got 0x3000 -# CHECK-NEXT: >>> .out.aaa 0x3000 : { *(.aaa) } -# CHECK-NEXT: >>> ^ - -SECTIONS { - OVERLAY 0x1000 : AT ( 0x2000 ) { - .out.aaa 0x3000 : { *(.aaa) } - } -} diff --git a/lld/test/ELF/linkerscript/overlay-reject2.test b/lld/test/ELF/linkerscript/overlay-reject2.test deleted file mode 100644 index be886d7c1dac..000000000000 --- a/lld/test/ELF/linkerscript/overlay-reject2.test +++ /dev/null @@ -1,17 +0,0 @@ -# REQUIRES: x86 -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux /dev/null -o %t.o -# RUN: not ld.lld %t.o --script %s -o /dev/null 2>&1 | FileCheck %s - -# CHECK: {{.*}}.test:{{.*}}: { expected, but got AX -# CHECK-NEXT: >>> .out.aaa { *(.aaa) } > AX AT>FLASH -# CHECK-NEXT: >>> ^ - -MEMORY { - AX (ax) : ORIGIN = 0x3000, LENGTH = 0x4000 -} - -SECTIONS { - OVERLAY 0x1000 : AT ( 0x2000 ) { - .out.aaa { *(.aaa) } > AX AT>FLASH - } -} diff --git a/lld/test/ELF/linkerscript/overlay.test b/lld/test/ELF/linkerscript/overlay.test index 2d3c88759c63..942e0a2971be 100644 --- a/lld/test/ELF/linkerscript/overlay.test +++ b/lld/test/ELF/linkerscript/overlay.test @@ -1,31 +1,91 @@ # REQUIRES: x86 -# RUN: echo 'nop; .section .small, "a"; .long 0; .section .big, "a"; .quad 1;' \ -# RUN: | llvm-mc -filetype=obj -triple=x86_64-unknown-linux - -o %t.o -# RUN: ld.lld %t.o --script %s -o %t +# RUN: rm -rf %t && split-file %s %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 a.s -o a.o +# RUN: ld.lld a.o -T a.t -o a -SECTIONS { - OVERLAY 0x1000 : AT ( 0x4000 ) { - .out.big { *(.big) } - .out.small { *(.small) } - } -} - -## Here we check that can handle OVERLAY which will produce sections +## Here we check that can handle OVERLAY which will produce sections ## .out.big and .out.small with the same starting VAs, but different LMAs. ## Section .big is larger than .small, we check that placing of section ## .text does not cause overlapping error and that ## .text's VA is 0x1000 + max(sizeof(.out.big), sizeof(.out.small)). -# RUN: llvm-readelf --sections -l %t | FileCheck %s +# RUN: llvm-readelf --sections -l a | FileCheck %s -# CHECK: Section Headers: -# CHECK: Name Type Address Off Size -# CHECK: .out.big PROGBITS 0000000000001000 001000 000008 -# CHECK: .out.small PROGBITS 0000000000001000 002000 000004 -# CHECK: .text PROGBITS 0000000000001008 002008 000001 +# CHECK: Name Type Address Off Size +# CHECK: .big1 PROGBITS 0000000000001000 001000 000008 +# CHECK-NEXT: .small1 PROGBITS 0000000000001000 002000 000004 +# CHECK-NEXT: .small2 PROGBITS 0000000000001008 002008 000004 +# CHECK-NEXT: .big2 PROGBITS 0000000000001008 003008 000008 +# CHECK-NEXT: .small3 PROGBITS 0000000000001010 003010 000004 +# CHECK-NEXT: .big3 PROGBITS 0000000000001014 003014 000008 +# CHECK-NEXT: .text PROGBITS 0000000000001024 003024 000001 # CHECK: Program Headers: # CHECK: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align -# CHECK-NEXT: LOAD 0x001000 0x0000000000001000 0x0000000000004000 0x000008 0x000008 R 0x1000 -# CHECK-NEXT: LOAD 0x002000 0x0000000000001000 0x0000000000004008 0x000004 0x000004 R 0x1000 -# CHECK-NEXT: LOAD 0x002008 0x0000000000001008 0x0000000000004010 0x000001 0x000001 R E 0x1000 +# CHECK-NEXT: LOAD 0x001000 0x0000000000001000 0x0000000000001000 0x000008 0x000008 R 0x1000 +# CHECK-NEXT: LOAD 0x002000 0x0000000000001000 0x0000000000001008 0x000004 0x000004 R 0x1000 +# CHECK-NEXT: LOAD 0x002008 0x0000000000001008 0x0000000000002008 0x000004 0x000004 R 0x1000 +# CHECK-NEXT: LOAD 0x003008 0x0000000000001008 0x000000000000200c 0x000008 0x000008 R 0x1000 +## FIXME Fix p_paddr when the first section in an overlay is empty and discarded. +# CHECK-NEXT: LOAD 0x003010 0x0000000000001010 0x0000000000000000 0x000004 0x000004 R 0x1000 +# CHECK-NEXT: LOAD 0x003014 0x0000000000001014 0x0000000000000004 0x000008 0x000008 R 0x1000 +# CHECK-NEXT: LOAD 0x003024 0x0000000000001024 0x0000000000000014 0x000001 0x000001 R E 0x1000 + +# RUN: not ld.lld a.o -T err1.t 2>&1 | FileCheck %s --check-prefix=ERR1 --match-full-lines --strict-whitespace +# ERR1:{{.*}}error: err1.t:3: { expected, but got 0x3000 +# ERR1-NEXT:>>> .out.aaa 0x3000 : { *(.aaa) } +# ERR1-NEXT:>>> ^ + +# RUN: not ld.lld a.o -T err2.t 2>&1 | FileCheck %s --check-prefix=ERR2 --match-full-lines --strict-whitespace +# ERR2:{{.*}}error: err2.t:{{.*}}: { expected, but got AX +# ERR2-NEXT:>>> .out.aaa { *(.aaa) } > AX AT>FLASH +# ERR2-NEXT:>>> ^ + +#--- a.s +.globl _start +_start: + nop + +.section .small1, "a"; .long 0 +.section .big1, "a"; .quad 1 + +.section .small2, "a"; .long 0 +.section .big2, "a"; .quad 1 + +.section .small3, "a"; .long 0 +.section .big3, "a"; .quad 1 + +#--- a.t +SECTIONS { + OVERLAY 0x1000 : AT( 0x1000 ) { + .big1 { *(.big1) } + .small1 { *(.small1) } + } + OVERLAY 0x1008 : AT (0x2008) { + .small2 { *(.small2) } + .big2 { *(.big2) } + } + OVERLAY . : AT (0x2014) { + .empty3 { *(.empty3) } + .small3 { *(.small3) } + .big3 { *(.big3) } + } + .text : { *(.text) } +} + +#--- err1.t +SECTIONS { + OVERLAY 0x1000 : AT ( 0x2000 ) { + .out.aaa 0x3000 : { *(.aaa) } + } +} + +#--- err2.t +MEMORY { + AX (ax) : ORIGIN = 0x3000, LENGTH = 0x4000 +} +SECTIONS { + OVERLAY 0x1000 : AT ( 0x2000 ) { + .out.aaa { *(.aaa) } > AX AT>FLASH + } +} -- GitLab From 93c8468c6cd154efb8fae16a4025e116be8181c7 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Mon, 8 Jan 2024 13:51:12 +0800 Subject: [PATCH 020/652] [X86][NFC] Remove duplicate comments in X86CompressEVEX.cpp --- llvm/lib/Target/X86/X86CompressEVEX.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp index 07b59437fe2f..3e839683b039 100644 --- a/llvm/lib/Target/X86/X86CompressEVEX.cpp +++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp @@ -15,10 +15,6 @@ // c. NDD (EVEX) -> non-NDD (legacy) // d. NF_ND (EVEX) -> NF (EVEX) // -// Compression a, b and c always reduce code size (some exception) -// fourth type of compression can help hardware decode although the instruction -// length remains unchanged. -// // Compression a, b and c can always reduce code size, with some exceptions // such as promoted 16-bit CRC32 which is as long as the legacy version. // -- GitLab From 624b48789f6941d5f10c9ddf144e2bf72365fdd1 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Sun, 7 Jan 2024 22:13:47 -0800 Subject: [PATCH 021/652] [AArch64][NFC] Pre-commit IR translator switch lowering test. --- .../GlobalISel/irtranslator-switch-split.ll | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll new file mode 100644 index 000000000000..7dba74793644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll @@ -0,0 +1,81 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -stop-after=irtranslator -o - %s | FileCheck %s --check-prefix=CHECK-TRANSLATOR + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-macosx14.0.0" + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0 + +declare i32 @logg(...) + +define i32 @scanfile(i32 %call148) { + ; CHECK-TRANSLATOR-LABEL: name: scanfile + ; CHECK-TRANSLATOR: bb.0.entry: + ; CHECK-TRANSLATOR-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $lr + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: early-clobber $sp = frame-setup STPXpre $fp, killed $lr, $sp, -2 :: (store (s64) into %stack.1), (store (s64) into %stack.0) + ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION offset $w30, -8 + ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16 + ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri renamable $w0, 0, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 12, %bb.4, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.1.entry: + ; CHECK-TRANSLATOR-NEXT: successors: %bb.4(0x55555556), %bb.2(0x2aaaaaaa) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: CBZW renamable $w0, %bb.4 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.2.entry: + ; CHECK-TRANSLATOR-NEXT: successors: %bb.5(0x00000000), %bb.3(0x80000000) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri renamable $w0, 2, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.5, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.3.entry: + ; CHECK-TRANSLATOR-NEXT: successors: %bb.5(0x00000000), %bb.4(0x80000000) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri killed renamable $w0, 1, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.5, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.4.common.ret: + ; CHECK-TRANSLATOR-NEXT: $w0 = ORRWrs $wzr, $wzr, 0 + ; CHECK-TRANSLATOR-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.1), (load (s64) from %stack.0) + ; CHECK-TRANSLATOR-NEXT: RET undef $lr, implicit killed $w0 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.5.sw.bb150: + ; CHECK-TRANSLATOR-NEXT: BL @logg, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $w0 + ; CHECK-TRANSLATOR-NEXT: BRK 1 +entry: + switch i32 %call148, label %common.ret [ + i32 -1, label %sw.bb + i32 -2, label %sw.bb150 + i32 0, label %sw.bb152 + i32 1, label %sw.bb178 + ] + +sw.bb: ; preds = %entry + %call149 = call i32 (...) @logg() + unreachable + +sw.bb150: ; preds = %entry + %call151 = call i32 (...) @logg() + unreachable + +common.ret: ; preds = %sw.bb178, %sw.bb152, %entry + ret i32 0 + +sw.bb152: ; preds = %entry + %tobool154.not = icmp eq i32 0, 0 + br label %common.ret + +sw.bb178: ; preds = %entry + call void @llvm.lifetime.start.p0(i64 0, ptr null) + br label %common.ret +} + +attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } -- GitLab From b3037ae1fc6d26459e37f813757ad30872eb2eee Mon Sep 17 00:00:00 2001 From: Christian Ulmann Date: Mon, 8 Jan 2024 07:42:33 +0100 Subject: [PATCH 022/652] [MLIR][LLVM] Add distinct identifier to DICompileUnit attribute (#77070) This commit adds a distinct attribute parameter to the DICompileUnit to enable the modeling of distinctness. LLVM requires DICompileUnits to be distinct and there are cases where one gets two equivalent compilation units but LLVM still requires differentiates them. We observed such cases for combinations of LTO and inline functions. This patch also changes the DIScopeForLLVMFuncOp pass to a module pass, to ensure that only one distinct DICompileUnit is created, instead of one for each function. --- .../Transforms/AddDebugFoundation.cpp | 6 +- .../Transforms/debug-line-table-existing.fir | 2 +- .../Transforms/debug-line-table-inc-file.fir | 2 +- flang/test/Transforms/debug-line-table.fir | 2 +- mlir/examples/toy/Ch6/toyc.cpp | 3 +- mlir/examples/toy/Ch7/toyc.cpp | 3 +- .../mlir/Dialect/LLVMIR/LLVMAttrDefs.td | 1 + .../mlir/Dialect/LLVMIR/Transforms/Passes.td | 2 +- .../Transforms/DIScopeForLLVMFuncOp.cpp | 114 +++++++++++------- mlir/lib/Target/LLVMIR/DebugImporter.cpp | 9 +- .../LLVMIR/add-debuginfo-func-scope.mlir | 32 +++-- mlir/test/Dialect/LLVMIR/call-location.mlir | 2 +- mlir/test/Dialect/LLVMIR/debuginfo.mlir | 6 +- mlir/test/Dialect/LLVMIR/global.mlir | 4 +- .../Dialect/LLVMIR/invalid-call-location.mlir | 4 +- mlir/test/Dialect/LLVMIR/loop-metadata.mlir | 2 +- mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir | 2 +- mlir/test/Target/LLVMIR/Import/debug-info.ll | 27 ++++- .../Target/LLVMIR/Import/global-variables.ll | 2 +- mlir/test/Target/LLVMIR/llvmir-debug.mlir | 22 ++-- mlir/test/Target/LLVMIR/loop-metadata.mlir | 2 +- 21 files changed, 156 insertions(+), 93 deletions(-) diff --git a/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp b/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp index be8f26dc678c..9972961de29f 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp @@ -65,9 +65,9 @@ void AddDebugFoundationPass::runOnOperation() { mlir::LLVM::DIFileAttr fileAttr = getFileAttr(inputFilePath); mlir::StringAttr producer = mlir::StringAttr::get(context, "Flang"); mlir::LLVM::DICompileUnitAttr cuAttr = mlir::LLVM::DICompileUnitAttr::get( - context, llvm::dwarf::getLanguage("DW_LANG_Fortran95"), fileAttr, - producer, /*isOptimized=*/false, - mlir::LLVM::DIEmissionKind::LineTablesOnly); + context, mlir::DistinctAttr::create(mlir::UnitAttr::get(context)), + llvm::dwarf::getLanguage("DW_LANG_Fortran95"), fileAttr, producer, + /*isOptimized=*/false, mlir::LLVM::DIEmissionKind::LineTablesOnly); module.walk([&](mlir::func::FuncOp funcOp) { mlir::Location l = funcOp->getLoc(); diff --git a/flang/test/Transforms/debug-line-table-existing.fir b/flang/test/Transforms/debug-line-table-existing.fir index 3585ef9ee2c4..3c81d75dbd66 100644 --- a/flang/test/Transforms/debug-line-table-existing.fir +++ b/flang/test/Transforms/debug-line-table-existing.fir @@ -12,7 +12,7 @@ module attributes {} { #di_file = #llvm.di_file<"simple.f90" in "/home/user01/llvm-project/build_release"> #loc = loc("/home/user01/llvm-project/build_release/simple.f90":0:0) #loc1 = loc("/home/user01/llvm-project/build_release/simple.f90":1:1) -#di_compile_unit = #llvm.di_compile_unit +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #di_file, producer = "Flang", isOptimized = false, emissionKind = LineTablesOnly> #di_subroutine_type = #llvm.di_subroutine_type #di_subprogram = #llvm.di_subprogram #loc2 = loc(fused<#di_subprogram>[#loc1]) diff --git a/flang/test/Transforms/debug-line-table-inc-file.fir b/flang/test/Transforms/debug-line-table-inc-file.fir index 5fdc384e0bdb..9ab4025a5862 100644 --- a/flang/test/Transforms/debug-line-table-inc-file.fir +++ b/flang/test/Transforms/debug-line-table-inc-file.fir @@ -30,7 +30,7 @@ module attributes {} { // CHECK: #[[MODULE_LOC]] = loc("{{.*}}simple.f90":0:0) // CHECK: #[[LOC_INC_FILE:.*]] = loc("{{.*}}inc.f90":1:1) // CHECK: #[[LOC_FILE:.*]] = loc("{{.*}}simple.f90":3:1) -// CHECK: #[[DI_CU:.*]] = #llvm.di_compile_unit +// CHECK: #[[DI_CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #[[DI_FILE]], producer = "Flang", isOptimized = false, emissionKind = LineTablesOnly> // CHECK: #[[DI_SP_INC:.*]] = #llvm.di_subprogram // CHECK: #[[DI_SP:.*]] = #llvm.di_subprogram // CHECK: #[[FUSED_LOC_INC_FILE]] = loc(fused<#[[DI_SP_INC]]>[#[[LOC_INC_FILE]]]) diff --git a/flang/test/Transforms/debug-line-table.fir b/flang/test/Transforms/debug-line-table.fir index fa59aeb4aa3a..115c6929778e 100644 --- a/flang/test/Transforms/debug-line-table.fir +++ b/flang/test/Transforms/debug-line-table.fir @@ -18,7 +18,7 @@ module attributes { fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", llvm.dat // CHECK: #di_file = #llvm.di_file<"[[FILE_NAME:.*]]" in "[[DIR_NAME:.*]]"> // CHECK: #[[MODULE_LOC]] = loc("[[DIR_NAME]]/[[FILE_NAME]]":1:1) // CHECK: #[[SB_LOC]] = loc("./simple.f90":2:1) -// CHECK: #di_compile_unit = #llvm.di_compile_unit +// CHECK: #di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #di_file, producer = "Flang", isOptimized = false, emissionKind = LineTablesOnly> // CHECK: #di_subroutine_type = #llvm.di_subroutine_type // CHECK: #di_subprogram = #llvm.di_subprogram // CHECK: #[[FUSED_SB_LOC]] = loc(fused<#di_subprogram>[#[[SB_LOC]]]) diff --git a/mlir/examples/toy/Ch6/toyc.cpp b/mlir/examples/toy/Ch6/toyc.cpp index 534f0d60e800..ddc0c2516bb3 100644 --- a/mlir/examples/toy/Ch6/toyc.cpp +++ b/mlir/examples/toy/Ch6/toyc.cpp @@ -187,8 +187,7 @@ int loadAndProcessMLIR(mlir::MLIRContext &context, // This is necessary to have line tables emitted and basic // debugger working. In the future we will add proper debug information // emission directly from our frontend. - pm.addNestedPass( - mlir::LLVM::createDIScopeForLLVMFuncOpPass()); + pm.addPass(mlir::LLVM::createDIScopeForLLVMFuncOpPass()); } if (mlir::failed(pm.run(*module))) diff --git a/mlir/examples/toy/Ch7/toyc.cpp b/mlir/examples/toy/Ch7/toyc.cpp index e4af0a3a3dce..5eb40b779bcd 100644 --- a/mlir/examples/toy/Ch7/toyc.cpp +++ b/mlir/examples/toy/Ch7/toyc.cpp @@ -188,8 +188,7 @@ int loadAndProcessMLIR(mlir::MLIRContext &context, // This is necessary to have line tables emitted and basic // debugger working. In the future we will add proper debug information // emission directly from our frontend. - pm.addNestedPass( - mlir::LLVM::createDIScopeForLLVMFuncOpPass()); + pm.addPass(mlir::LLVM::createDIScopeForLLVMFuncOpPass()); } if (mlir::failed(pm.run(*module))) diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td index f36ec0d02cf7..3b8ca9d2e3c5 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td @@ -342,6 +342,7 @@ def LLVM_DIBasicTypeAttr : LLVM_Attr<"DIBasicType", "di_basic_type", def LLVM_DICompileUnitAttr : LLVM_Attr<"DICompileUnit", "di_compile_unit", /*traits=*/[], "DIScopeAttr"> { let parameters = (ins + "DistinctAttr":$id, LLVM_DILanguageParameter:$sourceLanguage, "DIFileAttr":$file, OptionalParameter<"StringAttr">:$producer, diff --git a/mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td b/mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td index 6ebbd08acfc4..0242cfd9abb7 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td @@ -66,7 +66,7 @@ def NVVMOptimizeForTarget : Pass<"llvm-optimize-for-nvvm-target"> { let constructor = "::mlir::NVVM::createOptimizeForTargetPass()"; } -def DIScopeForLLVMFuncOp : Pass<"ensure-debug-info-scope-on-llvm-func", "LLVM::LLVMFuncOp"> { +def DIScopeForLLVMFuncOp : Pass<"ensure-debug-info-scope-on-llvm-func", "::mlir::ModuleOp"> { let summary = "Materialize LLVM debug info subprogram attribute on every LLVMFuncOp"; let description = [{ Having a debug info subprogram attribute on a function is required for diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp index ecdadd3062d3..d2e2c09e876f 100644 --- a/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp +++ b/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp @@ -34,64 +34,88 @@ static FileLineColLoc extractFileLoc(Location loc) { return FileLineColLoc(); } +/// Creates a DISubprogramAttr with the provided compile unit and attaches it +/// to the function. Does nothing when the function already has an attached +/// subprogram. +static void addScopeToFunction(LLVM::LLVMFuncOp llvmFunc, + LLVM::DICompileUnitAttr compileUnitAttr) { + + Location loc = llvmFunc.getLoc(); + if (loc->findInstanceOf>()) + return; + + MLIRContext *context = llvmFunc->getContext(); + + // Filename, line and colmun to associate to the function. + LLVM::DIFileAttr fileAttr; + int64_t line = 1, col = 1; + FileLineColLoc fileLoc = extractFileLoc(loc); + if (!fileLoc && compileUnitAttr) { + fileAttr = compileUnitAttr.getFile(); + } else if (!fileLoc) { + fileAttr = LLVM::DIFileAttr::get(context, "", ""); + } else { + line = fileLoc.getLine(); + col = fileLoc.getColumn(); + StringRef inputFilePath = fileLoc.getFilename().getValue(); + fileAttr = + LLVM::DIFileAttr::get(context, llvm::sys::path::filename(inputFilePath), + llvm::sys::path::parent_path(inputFilePath)); + } + auto subroutineTypeAttr = + LLVM::DISubroutineTypeAttr::get(context, llvm::dwarf::DW_CC_normal, {}); + + StringAttr funcNameAttr = llvmFunc.getNameAttr(); + auto subprogramAttr = LLVM::DISubprogramAttr::get( + context, compileUnitAttr, fileAttr, funcNameAttr, funcNameAttr, fileAttr, + /*line=*/line, + /*scopeline=*/col, + LLVM::DISubprogramFlags::Definition | LLVM::DISubprogramFlags::Optimized, + subroutineTypeAttr); + llvmFunc->setLoc(FusedLoc::get(context, {loc}, subprogramAttr)); +} + namespace { /// Add a debug info scope to LLVMFuncOp that are missing it. struct DIScopeForLLVMFuncOp : public LLVM::impl::DIScopeForLLVMFuncOpBase { void runOnOperation() override { - LLVM::LLVMFuncOp llvmFunc = getOperation(); - Location loc = llvmFunc.getLoc(); - if (loc->findInstanceOf>()) - return; + ModuleOp module = getOperation(); + Location loc = module.getLoc(); MLIRContext *context = &getContext(); // To find a DICompileUnitAttr attached to a parent (the module for // example), otherwise create a default one. + // Find a DICompileUnitAttr attached to the module, otherwise create a + // default one. LLVM::DICompileUnitAttr compileUnitAttr; - if (ModuleOp module = llvmFunc->getParentOfType()) { - auto fusedCompileUnitAttr = - module->getLoc() - ->findInstanceOf>(); - if (fusedCompileUnitAttr) - compileUnitAttr = fusedCompileUnitAttr.getMetadata(); - } - - // Filename, line and colmun to associate to the function. - LLVM::DIFileAttr fileAttr; - int64_t line = 1, col = 1; - FileLineColLoc fileLoc = extractFileLoc(loc); - if (!fileLoc && compileUnitAttr) { - fileAttr = compileUnitAttr.getFile(); - } else if (!fileLoc) { - fileAttr = LLVM::DIFileAttr::get(context, "", ""); + auto fusedCompileUnitAttr = + module->getLoc() + ->findInstanceOf>(); + if (fusedCompileUnitAttr) { + compileUnitAttr = fusedCompileUnitAttr.getMetadata(); } else { - line = fileLoc.getLine(); - col = fileLoc.getColumn(); - StringRef inputFilePath = fileLoc.getFilename().getValue(); - fileAttr = LLVM::DIFileAttr::get( - context, llvm::sys::path::filename(inputFilePath), - llvm::sys::path::parent_path(inputFilePath)); - } - if (!compileUnitAttr) { + LLVM::DIFileAttr fileAttr; + if (FileLineColLoc fileLoc = extractFileLoc(loc)) { + StringRef inputFilePath = fileLoc.getFilename().getValue(); + fileAttr = LLVM::DIFileAttr::get( + context, llvm::sys::path::filename(inputFilePath), + llvm::sys::path::parent_path(inputFilePath)); + } else { + fileAttr = LLVM::DIFileAttr::get(context, "", ""); + } + compileUnitAttr = LLVM::DICompileUnitAttr::get( - context, llvm::dwarf::DW_LANG_C, fileAttr, - StringAttr::get(context, "MLIR"), /*isOptimized=*/true, - LLVM::DIEmissionKind::LineTablesOnly); + context, DistinctAttr::create(UnitAttr::get(context)), + llvm::dwarf::DW_LANG_C, fileAttr, StringAttr::get(context, "MLIR"), + /*isOptimized=*/true, LLVM::DIEmissionKind::LineTablesOnly); } - auto subroutineTypeAttr = - LLVM::DISubroutineTypeAttr::get(context, llvm::dwarf::DW_CC_normal, {}); - - StringAttr funcNameAttr = llvmFunc.getNameAttr(); - auto subprogramAttr = - LLVM::DISubprogramAttr::get(context, compileUnitAttr, fileAttr, - funcNameAttr, funcNameAttr, fileAttr, - /*line=*/line, - /*scopeline=*/col, - LLVM::DISubprogramFlags::Definition | - LLVM::DISubprogramFlags::Optimized, - subroutineTypeAttr); - llvmFunc->setLoc(FusedLoc::get(context, {loc}, subprogramAttr)); + + // Create subprograms for each function with the same distinct compile unit. + module.walk([&](LLVM::LLVMFuncOp func) { + addScopeToFunction(func, compileUnitAttr); + }); } }; @@ -99,4 +123,4 @@ struct DIScopeForLLVMFuncOp std::unique_ptr mlir::LLVM::createDIScopeForLLVMFuncOpPass() { return std::make_unique(); -} \ No newline at end of file +} diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.cpp b/mlir/lib/Target/LLVMIR/DebugImporter.cpp index afc6918eae97..97871c7fe977 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DebugImporter.cpp @@ -50,10 +50,11 @@ DIBasicTypeAttr DebugImporter::translateImpl(llvm::DIBasicType *node) { DICompileUnitAttr DebugImporter::translateImpl(llvm::DICompileUnit *node) { std::optional emissionKind = symbolizeDIEmissionKind(node->getEmissionKind()); - return DICompileUnitAttr::get(context, node->getSourceLanguage(), - translate(node->getFile()), - getStringAttrOrNull(node->getRawProducer()), - node->isOptimized(), emissionKind.value()); + return DICompileUnitAttr::get( + context, DistinctAttr::create(UnitAttr::get(context)), + node->getSourceLanguage(), translate(node->getFile()), + getStringAttrOrNull(node->getRawProducer()), node->isOptimized(), + emissionKind.value()); } DICompositeTypeAttr DebugImporter::translateImpl(llvm::DICompositeType *node) { diff --git a/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir b/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir index eff4c55e6bc0..be84d401646d 100644 --- a/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir +++ b/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir @@ -1,6 +1,4 @@ -// RUN: mlir-opt %s --pass-pipeline="builtin.module(llvm.func(ensure-debug-info-scope-on-llvm-func))" --split-input-file --mlir-print-debuginfo | FileCheck %s - - +// RUN: mlir-opt %s --pass-pipeline="builtin.module(ensure-debug-info-scope-on-llvm-func)" --split-input-file --mlir-print-debuginfo | FileCheck %s // CHECK-LABEL: llvm.func @func_no_debug() // CHECK: llvm.return loc(#loc @@ -8,11 +6,12 @@ // CHECK: #di_file = #llvm.di_file<"" in ""> // CHECK: #di_subprogram = #llvm.di_subprogram // CHECK: #loc[[LOC]] = loc(fused<#di_subprogram> -llvm.func @func_no_debug() { - llvm.return loc(unknown) +module { + llvm.func @func_no_debug() { + llvm.return loc(unknown) + } loc(unknown) } loc(unknown) - // ----- // Test that existing debug info is not overwritten. @@ -31,7 +30,7 @@ module { #di_subroutine_type = #llvm.di_subroutine_type #loc = loc("foo":0:0) #loc1 = loc(unknown) -#di_compile_unit = #llvm.di_compile_unit +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", isOptimized = true, emissionKind = LineTablesOnly> #di_subprogram = #llvm.di_subprogram #loc2 = loc(fused<#di_subprogram>[#loc1]) @@ -45,7 +44,7 @@ module { // CHECK-DAG: #[[DI_FILE_MODULE:.+]] = #llvm.di_file<"bar.mlir" in "baz"> // CHECK-DAG: #[[DI_FILE_FUNC:.+]] = #llvm.di_file<"file.mlir" in ""> // CHECK-DAG: #loc[[FUNCFILELOC:[0-9]+]] = loc("file.mlir":9:8) -// CHECK-DAG: #di_compile_unit = #llvm.di_compile_unit +// CHECK-DAG: #di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[DI_FILE_MODULE]], producer = "MLIR", isOptimized = true, emissionKind = LineTablesOnly> // CHECK-DAG: #di_subprogram = #llvm.di_subprogram // CHECK-DAG: #loc[[MODULELOC]] = loc(fused<#di_compile_unit>[#loc]) // CHECK-DAG: #loc[[FUNCLOC]] = loc(fused<#di_subprogram>[#loc[[FUNCFILELOC]] @@ -55,5 +54,20 @@ module { } loc("file.mlir":9:8) } loc(#loc) #di_file = #llvm.di_file<"bar.mlir" in "baz"> -#di_compile_unit = #llvm.di_compile_unit +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", isOptimized = true, emissionKind = LineTablesOnly> #loc = loc(fused<#di_compile_unit>["foo.mlir":2:1]) + +// ----- + +// Test that only one compile unit is created. +// CHECK-LABEL: module @multiple_funcs +// CHECK: llvm.di_compile_unit +// CHECK-NOT: llvm.di_compile_unit +module @multiple_funcs { + llvm.func @func0() { + llvm.return loc(unknown) + } loc(unknown) + llvm.func @func1() { + llvm.return loc(unknown) + } loc(unknown) +} loc(unknown) diff --git a/mlir/test/Dialect/LLVMIR/call-location.mlir b/mlir/test/Dialect/LLVMIR/call-location.mlir index 1b473743bcd0..4a98c9e8d720 100644 --- a/mlir/test/Dialect/LLVMIR/call-location.mlir +++ b/mlir/test/Dialect/LLVMIR/call-location.mlir @@ -2,7 +2,7 @@ #di_file = #llvm.di_file<"file.cpp" in "/folder/"> #di_compile_unit = #llvm.di_compile_unit< - sourceLanguage = DW_LANG_C_plus_plus_14, file = #di_file, + id = distinct[0]<>, sourceLanguage = DW_LANG_C_plus_plus_14, file = #di_file, isOptimized = true, emissionKind = Full > #di_subprogram = #llvm.di_subprogram< diff --git a/mlir/test/Dialect/LLVMIR/debuginfo.mlir b/mlir/test/Dialect/LLVMIR/debuginfo.mlir index 53c38b479703..cef2ced391d6 100644 --- a/mlir/test/Dialect/LLVMIR/debuginfo.mlir +++ b/mlir/test/Dialect/LLVMIR/debuginfo.mlir @@ -3,10 +3,10 @@ // CHECK-DAG: #[[FILE:.*]] = #llvm.di_file<"debuginfo.mlir" in "/test/"> #file = #llvm.di_file<"debuginfo.mlir" in "/test/"> -// CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit +// CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[FILE]], producer = "MLIR", isOptimized = true, emissionKind = Full> #cu = #llvm.di_compile_unit< - sourceLanguage = DW_LANG_C, file = #file, producer = "MLIR", - isOptimized = true, emissionKind = Full + id = distinct[0]<>, sourceLanguage = DW_LANG_C, file = #file, + producer = "MLIR", isOptimized = true, emissionKind = Full > // CHECK-DAG: #[[NULL:.*]] = #llvm.di_null_type diff --git a/mlir/test/Dialect/LLVMIR/global.mlir b/mlir/test/Dialect/LLVMIR/global.mlir index 8133aa8913f3..0649e814bfdf 100644 --- a/mlir/test/Dialect/LLVMIR/global.mlir +++ b/mlir/test/Dialect/LLVMIR/global.mlir @@ -263,7 +263,7 @@ llvm.mlir.global @target_fail(0 : i64) : !llvm.target<"spirv.Image", i32, 0> // CHECK-DAG: #[[TYPE:.*]] = #llvm.di_basic_type // CHECK-DAG: #[[FILE:.*]] = #llvm.di_file<"not" in "existence"> -// CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit +// CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[FILE]], producer = "MLIR", isOptimized = true, emissionKind = Full> // CHECK-DAG: #[[GVAR0:.*]] = #llvm.di_global_variable // CHECK-DAG: #[[GVAR1:.*]] = #llvm.di_global_variable // CHECK-DAG: #[[GVAR2:.*]] = #llvm.di_global_variable @@ -278,7 +278,7 @@ llvm.mlir.global @target_fail(0 : i64) : !llvm.target<"spirv.Image", i32, 0> // CHECK-DAG: llvm.mlir.global external @global_with_expr4() {addr_space = 0 : i32, dbg_expr = #[[EXPR3]]} : i64 #di_file = #llvm.di_file<"not" in "existence"> -#di_compile_unit = #llvm.di_compile_unit +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", isOptimized = true, emissionKind = Full> #di_basic_type = #llvm.di_basic_type llvm.mlir.global external @global_with_expr1() {addr_space = 0 : i32, dbg_expr = #llvm.di_global_variable_expression, expr = <>>} : i64 llvm.mlir.global external @global_with_expr2() {addr_space = 0 : i32, dbg_expr = #llvm.di_global_variable_expression, expr = <[DW_OP_push_object_address, DW_OP_deref]>>} : i64 diff --git a/mlir/test/Dialect/LLVMIR/invalid-call-location.mlir b/mlir/test/Dialect/LLVMIR/invalid-call-location.mlir index ff819b656812..38b4ed9f6e83 100644 --- a/mlir/test/Dialect/LLVMIR/invalid-call-location.mlir +++ b/mlir/test/Dialect/LLVMIR/invalid-call-location.mlir @@ -5,8 +5,8 @@ #di_file = #llvm.di_file<"file.cpp" in "/folder/"> #di_compile_unit = #llvm.di_compile_unit< - sourceLanguage = DW_LANG_C_plus_plus_14, file = #di_file, - isOptimized = true, emissionKind = Full + id = distinct[0]<>, sourceLanguage = DW_LANG_C_plus_plus_14, + file = #di_file, isOptimized = true, emissionKind = Full > #di_subprogram = #llvm.di_subprogram< compileUnit = #di_compile_unit, scope = #di_file, diff --git a/mlir/test/Dialect/LLVMIR/loop-metadata.mlir b/mlir/test/Dialect/LLVMIR/loop-metadata.mlir index bae20d1d6818..97d3aa8f7ec7 100644 --- a/mlir/test/Dialect/LLVMIR/loop-metadata.mlir +++ b/mlir/test/Dialect/LLVMIR/loop-metadata.mlir @@ -90,7 +90,7 @@ llvm.func @loop_annotation() { // CHECK: #[[END_LOC:.*]] = loc("loop-metadata.mlir":52:4) #loc2 = loc("loop-metadata.mlir":52:4) -#di_compile_unit = #llvm.di_compile_unit +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file, isOptimized = false, emissionKind = None> // CHECK: #[[SUBPROGRAM:.*]] = #llvm.di_subprogram< #di_subprogram = #llvm.di_subprogram diff --git a/mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir b/mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir index bb96256f3af2..f7ddb4a7abe5 100644 --- a/mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir +++ b/mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir @@ -5,7 +5,7 @@ llvm.func @use_ptr(!llvm.ptr) #di_basic_type = #llvm.di_basic_type #di_file = #llvm.di_file<"test.ll" in ""> -#di_compile_unit = #llvm.di_compile_unit +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C_plus_plus_14, file = #di_file, producer = "clang", isOptimized = false, emissionKind = Full> #di_subprogram = #llvm.di_subprogram // CHECK: #[[$VAR:.*]] = #llvm.di_local_variable<{{.*}}name = "ptr sized var"{{.*}}> #di_local_variable = #llvm.di_local_variable diff --git a/mlir/test/Target/LLVMIR/Import/debug-info.ll b/mlir/test/Target/LLVMIR/Import/debug-info.ll index f8bf00bbf3f6..03e5e5a4837a 100644 --- a/mlir/test/Target/LLVMIR/Import/debug-info.ll +++ b/mlir/test/Target/LLVMIR/Import/debug-info.ll @@ -197,7 +197,7 @@ define void @composite_type() !dbg !3 { ; // ----- ; CHECK-DAG: #[[FILE:.+]] = #llvm.di_file<"debug-info.ll" in "/"> -; CHECK-DAG: #[[CU:.+]] = #llvm.di_compile_unit +; CHECK-DAG: #[[CU:.+]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[FILE]], isOptimized = false, emissionKind = None> ; Verify an empty subroutine types list is supported. ; CHECK-DAG: #[[SP_TYPE:.+]] = #llvm.di_subroutine_type ; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram @@ -589,3 +589,28 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) !5 = !DICompositeType(tag: DW_TAG_array_type, size: 42, baseType: !6) !6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !5) !7 = !DILocation(line: 0, scope: !3) + +; // ----- + +; Verifies that import compile units respect the distinctness of the input. +; CHECK-LABEL: @distinct_cu_func0 +define void @distinct_cu_func0() !dbg !4 { + ret void +} + +define void @distinct_cu_func1() !dbg !5 { + ret void +} + +!llvm.dbg.cu = !{!0, !1} +!llvm.module.flags = !{!3} + +; CHECK-COUNT-2: #llvm.di_compile_unit + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !2, producer: "clang") +!1 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !2, producer: "clang") +!2 = !DIFile(filename: "other.cpp", directory: "/") +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = distinct !DISubprogram(name: "func", linkageName: "func", scope: !6, file: !6, line: 1, scopeLine: 1, flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: !0) +!5 = distinct !DISubprogram(name: "func", linkageName: "func", scope: !6, file: !6, line: 1, scopeLine: 1, flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: !1) +!6 = !DIFile(filename: "file.hpp", directory: "/") diff --git a/mlir/test/Target/LLVMIR/Import/global-variables.ll b/mlir/test/Target/LLVMIR/Import/global-variables.ll index ab930084323c..c59515dbaf75 100644 --- a/mlir/test/Target/LLVMIR/Import/global-variables.ll +++ b/mlir/test/Target/LLVMIR/Import/global-variables.ll @@ -249,7 +249,7 @@ define void @bar() { ; CHECK-DAG: #[[TYPE:.*]] = #llvm.di_basic_type ; CHECK-DAG: #[[FILE:.*]] = #llvm.di_file<"source.c" in "/path/to/file"> -; CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit +; CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C99, file = #[[FILE]], isOptimized = false, emissionKind = None> ; CHECK-DAG: #[[SPROG:.*]] = #llvm.di_subprogram ; CHECK-DAG: #[[GVAR0:.*]] = #llvm.di_global_variable ; CHECK-DAG: #[[GVAR1:.*]] = #llvm.di_global_variable diff --git a/mlir/test/Target/LLVMIR/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir index 1133f57d6b61..476ed165887c 100644 --- a/mlir/test/Target/LLVMIR/llvmir-debug.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-debug.mlir @@ -35,8 +35,8 @@ llvm.func @func_no_debug() { tag = DW_TAG_pointer_type, name = "named", baseType = #si32 > #cu = #llvm.di_compile_unit< - sourceLanguage = DW_LANG_C, file = #file, producer = "MLIR", - isOptimized = true, emissionKind = Full + id = distinct[0]<>, sourceLanguage = DW_LANG_C, file = #file, + producer = "MLIR", isOptimized = true, emissionKind = Full > #composite = #llvm.di_composite_type< tag = DW_TAG_structure_type, name = "composite", file = #file, @@ -172,8 +172,8 @@ llvm.func @empty_types() { #di_basic_type = #llvm.di_basic_type #di_file = #llvm.di_file<"foo.mlir" in "/test/"> #di_compile_unit = #llvm.di_compile_unit< - sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", - isOptimized = true, emissionKind = Full + id = distinct[0]<>, sourceLanguage = DW_LANG_C, file = #di_file, + producer = "MLIR", isOptimized = true, emissionKind = Full > #di_subprogram = #llvm.di_subprogram< compileUnit = #di_compile_unit, scope = #di_file, name = "outer_func", @@ -216,8 +216,8 @@ llvm.func @func_with_inlined_dbg_value(%arg0: i32) -> (i32) { #di_basic_type = #llvm.di_basic_type #di_file = #llvm.di_file<"foo.mlir" in "/test/"> #di_compile_unit = #llvm.di_compile_unit< - sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", - isOptimized = true, emissionKind = Full + id = distinct[0]<>, sourceLanguage = DW_LANG_C, file = #di_file, + producer = "MLIR", isOptimized = true, emissionKind = Full > #di_subprogram = #llvm.di_subprogram< compileUnit = #di_compile_unit, scope = #di_file, name = "func", @@ -245,8 +245,8 @@ llvm.func @func_without_subprogram(%0 : i32) { #di_file = #llvm.di_file<"foo.mlir" in "/test/"> #di_compile_unit = #llvm.di_compile_unit< - sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", - isOptimized = true, emissionKind = Full + id = distinct[0]<>, sourceLanguage = DW_LANG_C, file = #di_file, + producer = "MLIR", isOptimized = true, emissionKind = Full > #di_subprogram = #llvm.di_subprogram< compileUnit = #di_compile_unit, scope = #di_file, name = "outer_func", @@ -285,7 +285,7 @@ llvm.func @dbg_intrinsics_with_no_location(%arg0: i32) -> (i32) { // CHECK-DAG: ![[GVALS]] = !{![[GEXPR0]], ![[GEXPR1]]} #di_file_2 = #llvm.di_file<"not" in "existence"> -#di_compile_unit_2 = #llvm.di_compile_unit +#di_compile_unit_2 = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file_2, producer = "MLIR", isOptimized = true, emissionKind = Full> #di_basic_type_2 = #llvm.di_basic_type llvm.mlir.global external @global_with_expr_1() {addr_space = 0 : i32, dbg_expr = #llvm.di_global_variable_expression, expr = <>>} : i64 llvm.mlir.global external @global_with_expr_2() {addr_space = 0 : i32, dbg_expr = #llvm.di_global_variable_expression, expr = <>>} : i64 @@ -315,9 +315,9 @@ llvm.mlir.global external constant @".str.1"() {addr_space = 0 : i32, dbg_expr = // CHECK-DAG: ![[FILE2:.*]] = !DIFile(filename: "foo2.mlir", directory: "/test/") #di_file_2 = #llvm.di_file<"foo2.mlir" in "/test/"> // CHECK-DAG: ![[SCOPE2:.*]] = distinct !DICompileUnit(language: DW_LANG_C, file: ![[FILE2]], producer: "MLIR", isOptimized: true, runtimeVersion: 0, emissionKind: DebugDirectivesOnly) -#di_compile_unit_1 = #llvm.di_compile_unit +#di_compile_unit_1 = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file_1, producer = "MLIR", isOptimized = true, emissionKind = LineTablesOnly> // CHECK-DAG: ![[SCOPE1:.*]] = distinct !DICompileUnit(language: DW_LANG_C, file: ![[FILE1]], producer: "MLIR", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly) -#di_compile_unit_2 = #llvm.di_compile_unit +#di_compile_unit_2 = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file_2, producer = "MLIR", isOptimized = true, emissionKind = DebugDirectivesOnly> #di_subprogram_1 = #llvm.di_subprogram #di_subprogram_2 = #llvm.di_subprogram diff --git a/mlir/test/Target/LLVMIR/loop-metadata.mlir b/mlir/test/Target/LLVMIR/loop-metadata.mlir index a9aeebfa4d82..2fe4a994aeb6 100644 --- a/mlir/test/Target/LLVMIR/loop-metadata.mlir +++ b/mlir/test/Target/LLVMIR/loop-metadata.mlir @@ -297,7 +297,7 @@ llvm.func @loopOptions(%arg1 : i32, %arg2 : i32) { #loc1 = loc("loop-metadata.mlir":42:4) #loc2 = loc("loop-metadata.mlir":52:4) -#di_compile_unit = #llvm.di_compile_unit +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file, isOptimized = false, emissionKind = None> #di_subprogram = #llvm.di_subprogram #start_loc_fused = loc(fused<#di_subprogram>[#loc1]) -- GitLab From 9b808a4beb8e6c8255b412fdd6f5a3e20cbcf270 Mon Sep 17 00:00:00 2001 From: Chuanqi Xu Date: Mon, 8 Jan 2024 14:40:36 +0800 Subject: [PATCH 023/652] [NFC] [Modules] Add a test case for selecting specializations with aliased template args This a test for https://github.com/llvm/llvm-project/pull/76774. In the review comments, we're concerning about the case that ODRHash may produce the different hash values for semantical same template arguments. For example, if the template argument in a specialization is not qualified and the semantical same template argument in the instantiation point is qualified, we should be able to select that template specialization. And this patch tests this behavior: we should be able to select the correct specialization with semantical same template arguments. --- .../Modules/explicit-specializations.cppm | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 clang/test/Modules/explicit-specializations.cppm diff --git a/clang/test/Modules/explicit-specializations.cppm b/clang/test/Modules/explicit-specializations.cppm new file mode 100644 index 000000000000..914144018e88 --- /dev/null +++ b/clang/test/Modules/explicit-specializations.cppm @@ -0,0 +1,133 @@ +// Testing that the compiler can select the correct template specialization +// from different template aliasing. +// +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: cd %t +// +// RUN: %clang_cc1 -std=c++20 %t/a.cppm -emit-module-interface -o %t/a.pcm +// RUN: %clang_cc1 -std=c++20 %t/b.cpp -fprebuilt-module-path=%t \ +// RUN: -fsyntax-only -verify + +//--- a.cppm + +// For template type parameters +export module a; +export template +struct S { + static constexpr bool selected = false; +}; + +export struct A {}; + +export template <> +struct S { + static constexpr bool selected = true; +}; + +export using B = A; + +// For template template parameters + +export template typename C> +struct V { + static constexpr bool selected = false; +}; + +export template <> +struct V { + static constexpr bool selected = true; +}; + +// For template non type parameters +export template +struct Numbers { + static constexpr bool selected = false; + static constexpr int value = X; +}; + +export template<> +struct Numbers<43> { + static constexpr bool selected = true; + static constexpr int value = 43; +}; + +export template +struct Pointers { + static constexpr bool selected = false; +}; + +export int IntegralValue = 0; +export template<> +struct Pointers<&IntegralValue> { + static constexpr bool selected = true; +}; + +export template +struct NullPointers { + static constexpr bool selected = false; +}; + +export template<> +struct NullPointers { + static constexpr bool selected = true; +}; + +export template +struct Array { + static constexpr bool selected = false; +}; + +export int array[5]; +export template<> +struct Array { + static constexpr bool selected = true; +}; + +//--- b.cpp +// expected-no-diagnostics +import a; + +// Testing for different qualifiers +static_assert(S::selected); +static_assert(S<::B>::selected); +static_assert(::S::selected); +static_assert(::S<::B>::selected); +typedef A C; +static_assert(S::selected); +static_assert(S<::C>::selected); +static_assert(::S::selected); +static_assert(::S<::C>::selected); + +namespace D { + C getAType(); + typedef C E; +} + +static_assert(S::selected); +static_assert(S::selected); + +// Testing we can select the correct specialization for different +// template template argument alising. + +static_assert(V::selected); +static_assert(V<::S>::selected); +static_assert(::V::selected); +static_assert(::V<::S>::selected); + +// Testing for template non type parameters +static_assert(Numbers<43>::selected); +static_assert(Numbers<21 * 2 + 1>::selected); +static_assert(Numbers<42 + 1>::selected); +static_assert(Numbers<44 - 1>::selected); +static_assert(Numbers::value>::selected); +static_assert(!Numbers<44>::selected); + +static_assert(Pointers<&IntegralValue>::selected); +static_assert(!Pointers::selected); +static_assert(NullPointers::selected); +static_assert(!NullPointers<(void*)&IntegralValue>::selected); + +static_assert(Array::selected); +int another_array[5]; +static_assert(!Array::selected); -- GitLab From fe1364f1e7ac0c4d0f9a4b15189485782241190d Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Sun, 7 Jan 2024 22:47:05 -0800 Subject: [PATCH 024/652] Update pre-committed test. Accidentally committed the wrong version, this one properly demonstrates the upcoming change. --- .../GlobalISel/irtranslator-switch-split.ll | 74 +++++++++++++++---- 1 file changed, 59 insertions(+), 15 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll index 7dba74793644..ee0dd985c1c6 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll @@ -12,42 +12,76 @@ declare i32 @logg(...) define i32 @scanfile(i32 %call148) { ; CHECK-TRANSLATOR-LABEL: name: scanfile ; CHECK-TRANSLATOR: bb.0.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000) + ; CHECK-TRANSLATOR-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000) ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $lr ; CHECK-TRANSLATOR-NEXT: {{ $}} ; CHECK-TRANSLATOR-NEXT: early-clobber $sp = frame-setup STPXpre $fp, killed $lr, $sp, -2 :: (store (s64) into %stack.1), (store (s64) into %stack.0) ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION offset $w30, -8 ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16 - ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri renamable $w0, 0, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 12, %bb.4, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: $w8 = ORRWrs $wzr, $w0, 0 + ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri killed $w0, 0, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: $w0 = ORRWrs $wzr, $wzr, 0 + ; CHECK-TRANSLATOR-NEXT: Bcc 12, %bb.5, implicit killed $nzcv ; CHECK-TRANSLATOR-NEXT: {{ $}} ; CHECK-TRANSLATOR-NEXT: bb.1.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.4(0x55555556), %bb.2(0x2aaaaaaa) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0 + ; CHECK-TRANSLATOR-NEXT: successors: %bb.9(0x55555555), %bb.2(0x2aaaaaab) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: CBZW renamable $w0, %bb.4 + ; CHECK-TRANSLATOR-NEXT: CBZW renamable $w8, %bb.9 ; CHECK-TRANSLATOR-NEXT: {{ $}} ; CHECK-TRANSLATOR-NEXT: bb.2.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.5(0x00000000), %bb.3(0x80000000) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0 + ; CHECK-TRANSLATOR-NEXT: successors: %bb.10(0x00000000), %bb.3(0x80000000) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri renamable $w0, 2, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.5, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri renamable $w8, 2, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.10, implicit $nzcv ; CHECK-TRANSLATOR-NEXT: {{ $}} ; CHECK-TRANSLATOR-NEXT: bb.3.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.5(0x00000000), %bb.4(0x80000000) + ; CHECK-TRANSLATOR-NEXT: successors: %bb.10(0x00000000), %bb.4(0x80000000) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri killed renamable $w8, 1, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.10, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.4.common.ret1: ; CHECK-TRANSLATOR-NEXT: liveins: $w0 ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri killed renamable $w0, 1, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.5, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.1), (load (s64) from %stack.0) + ; CHECK-TRANSLATOR-NEXT: RET undef $lr, implicit killed $w0 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.5.entry: + ; CHECK-TRANSLATOR-NEXT: successors: %bb.9(0x24924925), %bb.6(0x5b6db6db) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri renamable $w8, 1, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.9, implicit $nzcv ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.4.common.ret: + ; CHECK-TRANSLATOR-NEXT: bb.6.entry: + ; CHECK-TRANSLATOR-NEXT: successors: %bb.8(0x33333333), %bb.7(0x4ccccccd) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri renamable $w8, 2, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.8, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.7.entry: + ; CHECK-TRANSLATOR-NEXT: successors: %bb.8(0x55555555), %bb.4(0x2aaaaaab) + ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri killed renamable $w8, 3, 0, implicit-def $nzcv + ; CHECK-TRANSLATOR-NEXT: Bcc 1, %bb.4, implicit $nzcv + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.8.sw.bb300: + ; CHECK-TRANSLATOR-NEXT: BL @logg, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $w0 + ; CHECK-TRANSLATOR-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.1), (load (s64) from %stack.0) + ; CHECK-TRANSLATOR-NEXT: RET undef $lr, implicit killed $w0 + ; CHECK-TRANSLATOR-NEXT: {{ $}} + ; CHECK-TRANSLATOR-NEXT: bb.9.sw.bb178: ; CHECK-TRANSLATOR-NEXT: $w0 = ORRWrs $wzr, $wzr, 0 ; CHECK-TRANSLATOR-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.1), (load (s64) from %stack.0) ; CHECK-TRANSLATOR-NEXT: RET undef $lr, implicit killed $w0 ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.5.sw.bb150: + ; CHECK-TRANSLATOR-NEXT: bb.10.sw.bb150: ; CHECK-TRANSLATOR-NEXT: BL @logg, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $w0 ; CHECK-TRANSLATOR-NEXT: BRK 1 entry: @@ -56,6 +90,8 @@ entry: i32 -2, label %sw.bb150 i32 0, label %sw.bb152 i32 1, label %sw.bb178 + i32 2, label %sw.bb200 + i32 3, label %sw.bb300 ] sw.bb: ; preds = %entry @@ -66,6 +102,14 @@ sw.bb150: ; preds = %entry %call151 = call i32 (...) @logg() unreachable +sw.bb200: + %res = call i32 (...) @logg() + ret i32 %res + +sw.bb300: + %res2 = call i32 (...) @logg() + ret i32 %res2 + common.ret: ; preds = %sw.bb178, %sw.bb152, %entry ret i32 0 -- GitLab From 9de81ce87d9f99850d427c9e0440440b5ef9ebbf Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Sun, 7 Jan 2024 23:09:27 -0800 Subject: [PATCH 025/652] NFC: Another pre-commit test change. --- .../GlobalISel/irtranslator-switch-split.ll | 112 ++++++------------ 1 file changed, 36 insertions(+), 76 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll index ee0dd985c1c6..54c8eb913d5d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll @@ -1,5 +1,5 @@ -; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -stop-after=irtranslator -o - %s | FileCheck %s --check-prefix=CHECK-TRANSLATOR +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel -o - %s | FileCheck %s target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "arm64-apple-macosx14.0.0" @@ -10,80 +10,40 @@ declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0 declare i32 @logg(...) define i32 @scanfile(i32 %call148) { - ; CHECK-TRANSLATOR-LABEL: name: scanfile - ; CHECK-TRANSLATOR: bb.0.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $lr - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: early-clobber $sp = frame-setup STPXpre $fp, killed $lr, $sp, -2 :: (store (s64) into %stack.1), (store (s64) into %stack.0) - ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION offset $w30, -8 - ; CHECK-TRANSLATOR-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16 - ; CHECK-TRANSLATOR-NEXT: $w8 = ORRWrs $wzr, $w0, 0 - ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri killed $w0, 0, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: $w0 = ORRWrs $wzr, $wzr, 0 - ; CHECK-TRANSLATOR-NEXT: Bcc 12, %bb.5, implicit killed $nzcv - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.1.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.9(0x55555555), %bb.2(0x2aaaaaab) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: CBZW renamable $w8, %bb.9 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.2.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.10(0x00000000), %bb.3(0x80000000) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri renamable $w8, 2, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.10, implicit $nzcv - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.3.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.10(0x00000000), %bb.4(0x80000000) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: dead $wzr = ADDSWri killed renamable $w8, 1, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.10, implicit $nzcv - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.4.common.ret1: - ; CHECK-TRANSLATOR-NEXT: liveins: $w0 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.1), (load (s64) from %stack.0) - ; CHECK-TRANSLATOR-NEXT: RET undef $lr, implicit killed $w0 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.5.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.9(0x24924925), %bb.6(0x5b6db6db) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri renamable $w8, 1, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.9, implicit $nzcv - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.6.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.8(0x33333333), %bb.7(0x4ccccccd) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri renamable $w8, 2, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 0, %bb.8, implicit $nzcv - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.7.entry: - ; CHECK-TRANSLATOR-NEXT: successors: %bb.8(0x55555555), %bb.4(0x2aaaaaab) - ; CHECK-TRANSLATOR-NEXT: liveins: $w0, $w8 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: dead $wzr = SUBSWri killed renamable $w8, 3, 0, implicit-def $nzcv - ; CHECK-TRANSLATOR-NEXT: Bcc 1, %bb.4, implicit $nzcv - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.8.sw.bb300: - ; CHECK-TRANSLATOR-NEXT: BL @logg, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $w0 - ; CHECK-TRANSLATOR-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.1), (load (s64) from %stack.0) - ; CHECK-TRANSLATOR-NEXT: RET undef $lr, implicit killed $w0 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.9.sw.bb178: - ; CHECK-TRANSLATOR-NEXT: $w0 = ORRWrs $wzr, $wzr, 0 - ; CHECK-TRANSLATOR-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.1), (load (s64) from %stack.0) - ; CHECK-TRANSLATOR-NEXT: RET undef $lr, implicit killed $w0 - ; CHECK-TRANSLATOR-NEXT: {{ $}} - ; CHECK-TRANSLATOR-NEXT: bb.10.sw.bb150: - ; CHECK-TRANSLATOR-NEXT: BL @logg, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $w0 - ; CHECK-TRANSLATOR-NEXT: BRK 1 +; CHECK-LABEL: scanfile: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: mov w0, wzr +; CHECK-NEXT: cbz w8, LBB0_7 +; CHECK-NEXT: ; %bb.1: ; %entry +; CHECK-NEXT: cmp w8, #1 +; CHECK-NEXT: b.eq LBB0_7 +; CHECK-NEXT: ; %bb.2: ; %entry +; CHECK-NEXT: cmp w8, #2 +; CHECK-NEXT: b.eq LBB0_4 +; CHECK-NEXT: ; %bb.3: ; %entry +; CHECK-NEXT: cmp w8, #3 +; CHECK-NEXT: b.ne LBB0_5 +; CHECK-NEXT: LBB0_4: ; %sw.bb300 +; CHECK-NEXT: bl _logg +; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload +; CHECK-NEXT: ret +; CHECK-NEXT: LBB0_5: ; %entry +; CHECK-NEXT: cmn w8, #2 +; CHECK-NEXT: b.eq LBB0_8 +; CHECK-NEXT: ; %bb.6: ; %entry +; CHECK-NEXT: cmn w8, #1 +; CHECK-NEXT: b.eq LBB0_8 +; CHECK-NEXT: LBB0_7: ; %common.ret1 +; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload +; CHECK-NEXT: ret +; CHECK-NEXT: LBB0_8: ; %sw.bb150 +; CHECK-NEXT: bl _logg +; CHECK-NEXT: brk #0x1 entry: switch i32 %call148, label %common.ret [ i32 -1, label %sw.bb -- GitLab From bae1fdea712fcd0b0ea525b115e661f92263f2e7 Mon Sep 17 00:00:00 2001 From: Christian Ulmann Date: Mon, 8 Jan 2024 08:25:30 +0100 Subject: [PATCH 026/652] [MLIR][LLVM] Add distinct identifier to the DISubprogram attribute (#77093) This commit adds an optional distinct attribute parameter to the DISubprogramAttr. This enables modeling of distinct subprograms, as required for LLVM IR. This change is required to avoid accidential uniquing of subprograms on functions that would lead to invalid LLVM IR post export. --- .../Transforms/AddDebugFoundation.cpp | 12 ++++++- .../Transforms/debug-line-table-inc-file.fir | 6 ++-- flang/test/Transforms/debug-line-table.fir | 12 +++++-- .../mlir/Dialect/LLVMIR/LLVMAttrDefs.td | 11 +++--- .../Transforms/DIScopeForLLVMFuncOp.cpp | 11 ++++-- mlir/lib/Target/LLVMIR/DebugImporter.cpp | 6 +++- .../LLVMIR/add-debuginfo-func-scope.mlir | 20 ++++++++--- mlir/test/Target/LLVMIR/Import/debug-info.ll | 35 +++++++++++++------ .../Target/LLVMIR/Import/global-variables.ll | 4 +-- 9 files changed, 84 insertions(+), 33 deletions(-) diff --git a/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp b/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp index 9972961de29f..16b8db7ec8c6 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp @@ -93,8 +93,18 @@ void AddDebugFoundationPass::runOnOperation() { context, llvm::dwarf::getCallingConvention("DW_CC_normal"), {bT, bT}); mlir::LLVM::DIFileAttr funcFileAttr = getFileAttr(funcFilePath); + + // Only definitions need a distinct identifier and a compilation unit. + mlir::DistinctAttr id; + mlir::LLVM::DICompileUnitAttr compilationUnit; + if (!funcOp.isExternal()) { + id = mlir::DistinctAttr::create(mlir::UnitAttr::get(context)); + compilationUnit = cuAttr; + } mlir::LLVM::DISubprogramAttr spAttr = mlir::LLVM::DISubprogramAttr::get( - context, cuAttr, fileAttr, funcName, funcName, funcFileAttr, /*line=*/1, + context, id, compilationUnit, fileAttr, funcName, funcName, + funcFileAttr, + /*line=*/1, /*scopeline=*/1, mlir::LLVM::DISubprogramFlags::Definition, subTypeAttr); funcOp->setLoc(builder.getFusedLoc({funcOp->getLoc()}, spAttr)); diff --git a/flang/test/Transforms/debug-line-table-inc-file.fir b/flang/test/Transforms/debug-line-table-inc-file.fir index 9ab4025a5862..f809ab99b472 100644 --- a/flang/test/Transforms/debug-line-table-inc-file.fir +++ b/flang/test/Transforms/debug-line-table-inc-file.fir @@ -30,8 +30,8 @@ module attributes {} { // CHECK: #[[MODULE_LOC]] = loc("{{.*}}simple.f90":0:0) // CHECK: #[[LOC_INC_FILE:.*]] = loc("{{.*}}inc.f90":1:1) // CHECK: #[[LOC_FILE:.*]] = loc("{{.*}}simple.f90":3:1) -// CHECK: #[[DI_CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #[[DI_FILE]], producer = "Flang", isOptimized = false, emissionKind = LineTablesOnly> -// CHECK: #[[DI_SP_INC:.*]] = #llvm.di_subprogram -// CHECK: #[[DI_SP:.*]] = #llvm.di_subprogram +// CHECK: #[[DI_CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #[[DI_FILE]], producer = "Flang", isOptimized = false, emissionKind = LineTablesOnly> +// CHECK: #[[DI_SP_INC:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "_QPsinc", linkageName = "_QPsinc", file = #[[DI_INC_FILE]], {{.*}}> +// CHECK: #[[DI_SP:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "_QQmain", linkageName = "_QQmain", file = #[[DI_FILE]], {{.*}}> // CHECK: #[[FUSED_LOC_INC_FILE]] = loc(fused<#[[DI_SP_INC]]>[#[[LOC_INC_FILE]]]) // CHECK: #[[FUSED_LOC_FILE]] = loc(fused<#[[DI_SP]]>[#[[LOC_FILE]]]) diff --git a/flang/test/Transforms/debug-line-table.fir b/flang/test/Transforms/debug-line-table.fir index 115c6929778e..f091d97ce89e 100644 --- a/flang/test/Transforms/debug-line-table.fir +++ b/flang/test/Transforms/debug-line-table.fir @@ -5,20 +5,26 @@ module attributes { fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", llvm.dat func.func @_QPsb() { return loc(#loc_sb) } loc(#loc_sb) + func.func private @decl() -> i32 loc(#loc_decl) } loc(#loc_module) #loc_module = loc("./simple.f90":1:1) #loc_sb = loc("./simple.f90":2:1) +#loc_decl = loc("./simple.f90":10:1) // CHECK: module attributes // CHECK: func.func @[[SB_NAME:.*]]() { // CHECK: return loc(#[[SB_LOC:.*]]) // CHECK: } loc(#[[FUSED_SB_LOC:.*]]) +// CHECK: func.func private @[[DECL_NAME:.*]]() -> i32 loc(#[[FUSED_DECL_LOC:.*]]) // CHECK: } loc(#[[MODULE_LOC:.*]]) // CHECK: #di_basic_type = #llvm.di_basic_type // CHECK: #di_file = #llvm.di_file<"[[FILE_NAME:.*]]" in "[[DIR_NAME:.*]]"> // CHECK: #[[MODULE_LOC]] = loc("[[DIR_NAME]]/[[FILE_NAME]]":1:1) // CHECK: #[[SB_LOC]] = loc("./simple.f90":2:1) -// CHECK: #di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #di_file, producer = "Flang", isOptimized = false, emissionKind = LineTablesOnly> +// CHECK: #[[DECL_LOC:.*]] = loc("./simple.f90":10:1) +// CHECK: #di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #di_file, producer = "Flang", isOptimized = false, emissionKind = LineTablesOnly> // CHECK: #di_subroutine_type = #llvm.di_subroutine_type -// CHECK: #di_subprogram = #llvm.di_subprogram -// CHECK: #[[FUSED_SB_LOC]] = loc(fused<#di_subprogram>[#[[SB_LOC]]]) +// CHECK: #[[SB_SUBPROGRAM:.*]] = #llvm.di_subprogram, compileUnit = #di_compile_unit, scope = #di_file, name = "[[SB_NAME]]", linkageName = "[[SB_NAME]]", file = #di_file, line = 1, scopeLine = 1, subprogramFlags = Definition, type = #di_subroutine_type> +// CHECK: #[[DECL_SUBPROGRAM:.*]] = #llvm.di_subprogram +// CHECK: #[[FUSED_SB_LOC]] = loc(fused<#[[SB_SUBPROGRAM]]>[#[[SB_LOC]]]) +// CHECK: #[[FUSED_DECL_LOC]] = loc(fused<#[[DECL_SUBPROGRAM]]>[#[[DECL_LOC]]]) diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td index 3b8ca9d2e3c5..86ba9f4d3840 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td @@ -517,6 +517,7 @@ def LLVM_DILocalVariableAttr : LLVM_Attr<"DILocalVariable", "di_local_variable", def LLVM_DISubprogramAttr : LLVM_Attr<"DISubprogram", "di_subprogram", /*traits=*/[], "DIScopeAttr"> { let parameters = (ins + OptionalParameter<"DistinctAttr">:$id, OptionalParameter<"DICompileUnitAttr">:$compileUnit, "DIScopeAttr":$scope, OptionalParameter<"StringAttr">:$name, @@ -529,13 +530,13 @@ def LLVM_DISubprogramAttr : LLVM_Attr<"DISubprogram", "di_subprogram", ); let builders = [ AttrBuilderWithInferredContext<(ins - "DICompileUnitAttr":$compileUnit, "DIScopeAttr":$scope, "StringRef":$name, - "StringRef":$linkageName, "DIFileAttr":$file, "unsigned":$line, - "unsigned":$scopeLine, "DISubprogramFlags":$subprogramFlags, - "DISubroutineTypeAttr":$type + "DistinctAttr":$id, "DICompileUnitAttr":$compileUnit, + "DIScopeAttr":$scope, "StringRef":$name, "StringRef":$linkageName, + "DIFileAttr":$file, "unsigned":$line, "unsigned":$scopeLine, + "DISubprogramFlags":$subprogramFlags, "DISubroutineTypeAttr":$type ), [{ MLIRContext *ctx = file.getContext(); - return $_get(ctx, compileUnit, scope, StringAttr::get(ctx, name), + return $_get(ctx, id, compileUnit, scope, StringAttr::get(ctx, name), StringAttr::get(ctx, linkageName), file, line, scopeLine, subprogramFlags, type); }]> diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp index d2e2c09e876f..de6fb1b16977 100644 --- a/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp +++ b/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp @@ -66,8 +66,15 @@ static void addScopeToFunction(LLVM::LLVMFuncOp llvmFunc, LLVM::DISubroutineTypeAttr::get(context, llvm::dwarf::DW_CC_normal, {}); StringAttr funcNameAttr = llvmFunc.getNameAttr(); - auto subprogramAttr = LLVM::DISubprogramAttr::get( - context, compileUnitAttr, fileAttr, funcNameAttr, funcNameAttr, fileAttr, + // Only definitions need a distinct identifier and a compilation unit. + mlir::DistinctAttr id; + if (!llvmFunc.isExternal()) + id = mlir::DistinctAttr::create(mlir::UnitAttr::get(context)); + else + compileUnitAttr = {}; + mlir::LLVM::DISubprogramAttr subprogramAttr = LLVM::DISubprogramAttr::get( + context, id, compileUnitAttr, fileAttr, funcNameAttr, funcNameAttr, + fileAttr, /*line=*/line, /*scopeline=*/col, LLVM::DISubprogramFlags::Definition | LLVM::DISubprogramFlags::Optimized, diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.cpp b/mlir/lib/Target/LLVMIR/DebugImporter.cpp index 97871c7fe977..652129523009 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DebugImporter.cpp @@ -163,6 +163,10 @@ DINamespaceAttr DebugImporter::translateImpl(llvm::DINamespace *node) { } DISubprogramAttr DebugImporter::translateImpl(llvm::DISubprogram *node) { + // Only definitions require a distinct identifier. + mlir::DistinctAttr id; + if (node->isDistinct()) + id = DistinctAttr::create(UnitAttr::get(context)); std::optional subprogramFlags = symbolizeDISubprogramFlags(node->getSubprogram()->getSPFlags()); // Return nullptr if the scope or type is a cyclic dependency. @@ -172,7 +176,7 @@ DISubprogramAttr DebugImporter::translateImpl(llvm::DISubprogram *node) { DISubroutineTypeAttr type = translate(node->getType()); if (node->getType() && !type) return nullptr; - return DISubprogramAttr::get(context, translate(node->getUnit()), scope, + return DISubprogramAttr::get(context, id, translate(node->getUnit()), scope, getStringAttrOrNull(node->getRawName()), getStringAttrOrNull(node->getRawLinkageName()), translate(node->getFile()), node->getLine(), diff --git a/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir b/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir index be84d401646d..f63132d42ab7 100644 --- a/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir +++ b/mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir @@ -4,7 +4,7 @@ // CHECK: llvm.return loc(#loc // CHECK: loc(#loc[[LOC:[0-9]+]]) // CHECK: #di_file = #llvm.di_file<"" in ""> -// CHECK: #di_subprogram = #llvm.di_subprogram +// CHECK: #di_subprogram = #llvm.di_subprogram, compileUnit = #di_compile_unit, scope = #di_file, name = "func_no_debug", linkageName = "func_no_debug", file = #di_file, line = 1, scopeLine = 1, subprogramFlags = "Definition|Optimized", type = #di_subroutine_type> // CHECK: #loc[[LOC]] = loc(fused<#di_subprogram> module { llvm.func @func_no_debug() { @@ -14,12 +14,22 @@ module { // ----- +// Test that the declarations subprogram is not made distinct. +// CHECK-LABEL: llvm.func @func_decl_no_debug() +// CHECK: #di_subprogram = #llvm.di_subprogram< +// CHECK-NOT: id = distinct +module { + llvm.func @func_decl_no_debug() loc(unknown) +} loc(unknown) + +// ----- + // Test that existing debug info is not overwritten. // CHECK-LABEL: llvm.func @func_with_debug() // CHECK: llvm.return loc(#loc // CHECK: loc(#loc[[LOC:[0-9]+]]) // CHECK: #di_file = #llvm.di_file<"" in ""> -// CHECK: #di_subprogram = #llvm.di_subprogram +// CHECK: #di_subprogram = #llvm.di_subprogram, compileUnit = #di_compile_unit, scope = #di_file, name = "func_with_debug", linkageName = "func_with_debug", file = #di_file, line = 42, scopeLine = 42, subprogramFlags = "Definition|Optimized", type = #di_subroutine_type> // CHECK: #loc[[LOC]] = loc(fused<#di_subprogram> module { llvm.func @func_with_debug() { @@ -31,7 +41,7 @@ module { #loc = loc("foo":0:0) #loc1 = loc(unknown) #di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", isOptimized = true, emissionKind = LineTablesOnly> -#di_subprogram = #llvm.di_subprogram +#di_subprogram = #llvm.di_subprogram, compileUnit = #di_compile_unit, scope = #di_file, name = "func_with_debug", linkageName = "func_with_debug", file = #di_file, line = 42, scopeLine = 42, subprogramFlags = "Definition|Optimized", type = #di_subroutine_type> #loc2 = loc(fused<#di_subprogram>[#loc1]) // ----- @@ -44,8 +54,8 @@ module { // CHECK-DAG: #[[DI_FILE_MODULE:.+]] = #llvm.di_file<"bar.mlir" in "baz"> // CHECK-DAG: #[[DI_FILE_FUNC:.+]] = #llvm.di_file<"file.mlir" in ""> // CHECK-DAG: #loc[[FUNCFILELOC:[0-9]+]] = loc("file.mlir":9:8) -// CHECK-DAG: #di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[DI_FILE_MODULE]], producer = "MLIR", isOptimized = true, emissionKind = LineTablesOnly> -// CHECK-DAG: #di_subprogram = #llvm.di_subprogram +// CHECK-DAG: #di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[DI_FILE_MODULE]], producer = "MLIR", isOptimized = true, emissionKind = LineTablesOnly> +// CHECK-DAG: #di_subprogram = #llvm.di_subprogram, compileUnit = #di_compile_unit, scope = #[[DI_FILE_FUNC]], name = "propagate_compile_unit", linkageName = "propagate_compile_unit", file = #[[DI_FILE_FUNC]], line = 9, scopeLine = 8, subprogramFlags = "Definition|Optimized", type = #di_subroutine_type> // CHECK-DAG: #loc[[MODULELOC]] = loc(fused<#di_compile_unit>[#loc]) // CHECK-DAG: #loc[[FUNCLOC]] = loc(fused<#di_subprogram>[#loc[[FUNCFILELOC]] module { diff --git a/mlir/test/Target/LLVMIR/Import/debug-info.ll b/mlir/test/Target/LLVMIR/Import/debug-info.ll index 03e5e5a4837a..9ef6580bcf24 100644 --- a/mlir/test/Target/LLVMIR/Import/debug-info.ll +++ b/mlir/test/Target/LLVMIR/Import/debug-info.ll @@ -30,8 +30,8 @@ define i32 @instruction_loc(i32 %arg1) { } ; CHECK-DAG: #[[RAW_FILE_LOC:.+]] = loc("debug-info.ll":1:2) -; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #{{.*}}, name = "instruction_loc" +; CHECK-DAG: #[[CALLEE:.+]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #{{.*}}, name = "callee" ; CHECK-DAG: #[[FILE_LOC]] = loc(fused<#[[SP]]>[#[[RAW_FILE_LOC]]]) ; CHECK-DAG: #[[RAW_CALLEE_LOC:.+]] = loc("debug-info.ll":7:4) ; CHECK-DAG: #[[CALLEE_LOC:.+]] = loc(fused<#[[CALLEE]]>[#[[RAW_CALLEE_LOC]]]) @@ -63,7 +63,7 @@ define i32 @lexical_block(i32 %arg1) { ret i32 %2 } ; CHECK: #[[FILE:.+]] = #llvm.di_file<"debug-info.ll" in "/"> -; CHECK: #[[SP:.+]] = #llvm.di_subprogram, compileUnit = ; CHECK: #[[LB0:.+]] = #llvm.di_lexical_block ; CHECK: #[[LB1:.+]] = #llvm.di_lexical_block ; CHECK: #[[LOC0]] = loc(fused<#[[LB0]]>[{{.*}}]) @@ -93,7 +93,7 @@ define i32 @lexical_block_file(i32 %arg1) { ret i32 %2 } ; CHECK: #[[FILE:.+]] = #llvm.di_file<"debug-info.ll" in "/"> -; CHECK: #[[SP:.+]] = #llvm.di_subprogram, compileUnit = ; CHECK: #[[LB0:.+]] = #llvm.di_lexical_block_file ; CHECK: #[[LB1:.+]] = #llvm.di_lexical_block_file ; CHECK: #[[LOC0]] = loc(fused<#[[LB0]]>[ @@ -200,7 +200,7 @@ define void @composite_type() !dbg !3 { ; CHECK-DAG: #[[CU:.+]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[FILE]], isOptimized = false, emissionKind = None> ; Verify an empty subroutine types list is supported. ; CHECK-DAG: #[[SP_TYPE:.+]] = #llvm.di_subroutine_type -; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram +; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram, compileUnit = #[[CU]], scope = #[[FILE]], name = "subprogram", linkageName = "subprogram", file = #[[FILE]], line = 42, scopeLine = 42, subprogramFlags = Definition, type = #[[SP_TYPE]]> define void @subprogram() !dbg !3 { ret void @@ -224,7 +224,7 @@ define void @func_loc() !dbg !3 { } ; CHECK-DAG: #[[NAME_LOC:.+]] = loc("func_loc") ; CHECK-DAG: #[[FILE_LOC:.+]] = loc("debug-info.ll":42:0) -; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram +; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #{{.*}}, name = "func_loc", file = #{{.*}}, line = 42, subprogramFlags = Definition> ; CHECK: loc(fused<#[[SP]]>[#[[NAME_LOC]], #[[FILE_LOC]]] @@ -300,7 +300,7 @@ define void @class_method() { ; CHECK: #[[COMP:.+]] = #llvm.di_composite_type ; CHECK: #[[COMP_PTR:.+]] = #llvm.di_derived_type ; CHECK: #[[SP_TYPE:.+]] = #llvm.di_subroutine_type -; CHECK: #[[SP:.+]] = #llvm.di_subprogram +; CHECK: #[[SP:.+]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #[[COMP]], name = "class_method", file = #{{.*}}, subprogramFlags = Definition, type = #[[SP_TYPE]]> ; CHECK: #[[LOC]] = loc(fused<#[[SP]]> !llvm.dbg.cu = !{!1} @@ -485,7 +485,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) ; // ----- ; CHECK-DAG: #[[NAMESPACE:.+]] = #llvm.di_namespace -; CHECK-DAG: #[[SUBPROGRAM:.+]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #[[NAMESPACE]], name = "namespace" define void @namespace(ptr %arg) { call void @llvm.dbg.value(metadata ptr %arg, metadata !7, metadata !DIExpression()), !dbg !9 @@ -506,7 +506,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) ; // ----- -; CHECK-DAG: #[[SUBPROGRAM:.+]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #{{.*}}, name = "noname_variable" ; CHECK-DAG: #[[LOCAL_VARIABLE:.+]] = #llvm.di_local_variable define void @noname_variable(ptr %arg) { @@ -527,7 +527,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) ; // ----- -; CHECK: #[[SUBPROGRAM:.*]] = #llvm.di_subprogram +; CHECK: #[[SUBPROGRAM:.*]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #{{.*}}, file = #{{.*}}, subprogramFlags = Definition> ; CHECK: #[[FUNC_LOC:.*]] = loc(fused<#[[SUBPROGRAM]]>[{{.*}}]) define void @noname_subprogram(ptr %arg) !dbg !8 { ret void @@ -547,7 +547,7 @@ define void @noname_subprogram(ptr %arg) !dbg !8 { ; CHECK-SAME: configMacros = "bar", includePath = "/", ; CHECK-SAME: apinotes = "/", line = 42, isDecl = true ; CHECK-SAME: > -; CHECK: #[[SUBPROGRAM:.+]] = #llvm.di_subprogram, compileUnit = #{{.*}}, scope = #[[MODULE]], name = "func_in_module" define void @func_in_module(ptr %arg) !dbg !8 { ret void @@ -614,3 +614,16 @@ define void @distinct_cu_func1() !dbg !5 { !4 = distinct !DISubprogram(name: "func", linkageName: "func", scope: !6, file: !6, line: 1, scopeLine: 1, flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: !0) !5 = distinct !DISubprogram(name: "func", linkageName: "func", scope: !6, file: !6, line: 1, scopeLine: 1, flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: !1) !6 = !DIFile(filename: "file.hpp", directory: "/") + +; // ----- + +; CHECK-LABEL: @declaration +declare !dbg !1 void @declaration() + +; CHECK: #di_subprogram = #llvm.di_subprogram< +; CHECK-NOT: id = distinct + +!llvm.module.flags = !{!0} +!0 = !{i32 2, !"Debug Info Version", i32 3} +!1 = !DISubprogram(name: "declaration", scope: !2, file: !2, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!2 = !DIFile(filename: "debug-info.ll", directory: "/") diff --git a/mlir/test/Target/LLVMIR/Import/global-variables.ll b/mlir/test/Target/LLVMIR/Import/global-variables.ll index c59515dbaf75..9d9734045988 100644 --- a/mlir/test/Target/LLVMIR/Import/global-variables.ll +++ b/mlir/test/Target/LLVMIR/Import/global-variables.ll @@ -249,8 +249,8 @@ define void @bar() { ; CHECK-DAG: #[[TYPE:.*]] = #llvm.di_basic_type ; CHECK-DAG: #[[FILE:.*]] = #llvm.di_file<"source.c" in "/path/to/file"> -; CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C99, file = #[[FILE]], isOptimized = false, emissionKind = None> -; CHECK-DAG: #[[SPROG:.*]] = #llvm.di_subprogram +; CHECK-DAG: #[[CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C99, file = #[[FILE]], isOptimized = false, emissionKind = None> +; CHECK-DAG: #[[SPROG:.*]] = #llvm.di_subprogram, scope = #[[CU]], name = "foo", file = #[[FILE]], line = 5, subprogramFlags = Definition> ; CHECK-DAG: #[[GVAR0:.*]] = #llvm.di_global_variable ; CHECK-DAG: #[[GVAR1:.*]] = #llvm.di_global_variable ; CHECK-DAG: #[[EXPR0:.*]] = #llvm.di_global_variable_expression> -- GitLab From 7e54ae24d84bce4452ac4a28acb6568db52980fb Mon Sep 17 00:00:00 2001 From: Tobias Gysi Date: Mon, 8 Jan 2024 08:30:10 +0100 Subject: [PATCH 027/652] [mlir][llvm] Do not inline variadic functions (#77241) This revision updates the llvm dialect inliner to explicitly disallow the inlining of variadic functions. Already previously the inlining failed if the number of function arguments did not match the number of call arguments. After the change, inlining checks the function is not variadic and it does not contain a va_start intrinsic. --- mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp | 7 +++++- mlir/test/Dialect/LLVMIR/inlining.mlir | 25 +++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp index 65c1daee6711..4a6154ea6d30 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp @@ -663,6 +663,10 @@ struct LLVMInlinerInterface : public DialectInlinerInterface { << "Cannot inline: callable is not an LLVM::LLVMFuncOp\n"); return false; } + if (funcOp.isVarArg()) { + LLVM_DEBUG(llvm::dbgs() << "Cannot inline: callable is variadic\n"); + return false; + } // TODO: Generate aliasing metadata from noalias argument/result attributes. if (auto attrs = funcOp.getArgAttrs()) { for (DictionaryAttr attrDict : attrs->getAsRange()) { @@ -704,7 +708,8 @@ struct LLVMInlinerInterface : public DialectInlinerInterface { } bool isLegalToInline(Operation *op, Region *, bool, IRMapping &) const final { - return true; + // The inliner cannot handle variadic function arguments. + return !isa(op); } /// Handle the given inlined return by replacing it with a branch. This diff --git a/mlir/test/Dialect/LLVMIR/inlining.mlir b/mlir/test/Dialect/LLVMIR/inlining.mlir index 63e7a46f1bdb..3af8753bc318 100644 --- a/mlir/test/Dialect/LLVMIR/inlining.mlir +++ b/mlir/test/Dialect/LLVMIR/inlining.mlir @@ -644,3 +644,28 @@ llvm.func @caller(%ptr : !llvm.ptr) -> i32 { llvm.store %c5, %ptr { access_groups = [#caller] } : i32, !llvm.ptr llvm.return %0 : i32 } + +// ----- + +llvm.func @vararg_func(...) { + llvm.return +} + +llvm.func @vararg_intrinrics() { + %0 = llvm.mlir.constant(1 : i32) : i32 + %list = llvm.alloca %0 x !llvm.struct<"struct.va_list_opaque", (ptr)> : (i32) -> !llvm.ptr + // The vararg intinriscs should normally be part of a variadic function. + // However, this test uses a non-variadic function to ensure the presence of + // the intrinsic alone suffices to prevent inlining. + llvm.intr.vastart %list : !llvm.ptr + llvm.return +} + +// CHECK-LABEL: func @caller +llvm.func @caller() { + // CHECK-NEXT: llvm.call @vararg_func() + llvm.call @vararg_func() vararg(!llvm.func) : () -> () + // CHECK-NEXT: llvm.call @vararg_intrinrics() + llvm.call @vararg_intrinrics() : () -> () + llvm.return +} -- GitLab From c15e5836d49763e43736d13eb4b873e01dcc9ef0 Mon Sep 17 00:00:00 2001 From: Timm Baeder Date: Mon, 8 Jan 2024 08:33:15 +0100 Subject: [PATCH 028/652] [clang][Interp] Fix nullptr array dereferencing (#75798) The attached test case would cause an assertion failure in Pointer.h when operating on a null pointer. --- clang/lib/AST/Interp/Interp.cpp | 4 ++-- clang/lib/AST/Interp/Interp.h | 6 ------ clang/test/AST/Interp/arrays.cpp | 8 ++++++++ 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index a82d1c3c7c62..21ea2503b94b 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -290,10 +290,10 @@ bool CheckInitialized(InterpState &S, CodePtr OpPC, const Pointer &Ptr, } bool CheckLoad(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { - if (!CheckDummy(S, OpPC, Ptr)) - return false; if (!CheckLive(S, OpPC, Ptr, AK_Read)) return false; + if (!CheckDummy(S, OpPC, Ptr)) + return false; if (!CheckExtern(S, OpPC, Ptr)) return false; if (!CheckRange(S, OpPC, Ptr, AK_Read)) diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 828d4ea35526..c05dea0cc55d 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1813,9 +1813,6 @@ inline bool ArrayElemPtr(InterpState &S, CodePtr OpPC) { const T &Offset = S.Stk.pop(); const Pointer &Ptr = S.Stk.peek(); - if (!CheckArray(S, OpPC, Ptr)) - return false; - if (!OffsetHelper(S, OpPC, Offset, Ptr)) return false; @@ -1843,9 +1840,6 @@ inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { const T &Offset = S.Stk.pop(); const Pointer &Ptr = S.Stk.pop(); - if (!CheckArray(S, OpPC, Ptr)) - return false; - if (!OffsetHelper(S, OpPC, Offset, Ptr)) return false; diff --git a/clang/test/AST/Interp/arrays.cpp b/clang/test/AST/Interp/arrays.cpp index c455731e7669..4aa10da55dd3 100644 --- a/clang/test/AST/Interp/arrays.cpp +++ b/clang/test/AST/Interp/arrays.cpp @@ -72,6 +72,14 @@ constexpr int getElementFromEnd(const int *Arr, int size, int index) { static_assert(getElementFromEnd(data, 5, 0) == 1, ""); static_assert(getElementFromEnd(data, 5, 4) == 5, ""); +constexpr int getFirstElem(const int *a) { + return a[0]; // expected-note {{read of dereferenced null pointer}} \ + // ref-note {{read of dereferenced null pointer}} +} +static_assert(getFirstElem(nullptr) == 1, ""); // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to}} \ + // ref-error {{not an integral constant expression}} \ + // ref-note {{in call to}} constexpr static int arr[2] = {1,2}; constexpr static int arr2[2] = {3,4}; -- GitLab From 6343b4e48205fe5772f707b9023e8a57c95154a9 Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Mon, 8 Jan 2024 07:45:31 +0000 Subject: [PATCH 029/652] [mlir] Apply ClangTidy performance finding - Use '\n' instead of std::endl; https://clang.llvm.org/extra/clang-tidy/checks/performance/avoid-endl.html --- mlir/include/mlir/ExecutionEngine/RunnerUtils.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mlir/include/mlir/ExecutionEngine/RunnerUtils.h b/mlir/include/mlir/ExecutionEngine/RunnerUtils.h index b426465c5192..72001172c426 100644 --- a/mlir/include/mlir/ExecutionEngine/RunnerUtils.h +++ b/mlir/include/mlir/ExecutionEngine/RunnerUtils.h @@ -217,14 +217,14 @@ void printMemRefShape(UnrankedMemRefType &m) { template void printMemRef(const DynamicMemRefType &m) { printMemRefMetaData(std::cout, m); - std::cout << " data = " << std::endl; + std::cout << " data = \n"; if (m.rank == 0) std::cout << "["; MemRefDataPrinter::print(std::cout, m.data, m.rank, m.rank, m.offset, m.sizes, m.strides); if (m.rank == 0) std::cout << "]"; - std::cout << std::endl; + std::cout << '\n'; } template -- GitLab From ca20c99bb185838e5f275cf27fdcaccb17d7978d Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Sun, 7 Jan 2024 23:53:09 -0800 Subject: [PATCH 030/652] [GlobalISel][IRTranslator] Port switch binary tree search optimization. (#77279) This re-uses some code extracted earlier from SelectionDAG into SwitchLoweringUtils Much of the code is a straight port from SDAG's splitWorkItem(), with minor changes needed for GISel. --- .../llvm/CodeGen/GlobalISel/IRTranslator.h | 4 + llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 79 ++++++++++++++++++- .../GlobalISel/irtranslator-switch-split.ll | 34 ++++---- 3 files changed, 99 insertions(+), 18 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index bffc03ed0187..1b094d9d9fe7 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -366,6 +366,10 @@ private: BranchProbability BranchProbToNext, Register Reg, SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB); + void splitWorkItem(SwitchCG::SwitchWorkList &WorkList, + const SwitchCG::SwitchWorkListItem &W, Value *Cond, + MachineBasicBlock *SwitchMBB, MachineIRBuilder &MIB); + bool lowerJumpTableWorkItem( SwitchCG::SwitchWorkListItem W, MachineBasicBlock *SwitchMBB, MachineBasicBlock *CurMBB, MachineBasicBlock *DefaultMBB, diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 9c11113902a2..6708f2baa5ed 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -751,16 +751,91 @@ bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) { auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB); WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb}); - // FIXME: At the moment we don't do any splitting optimizations here like - // SelectionDAG does, so this worklist only has one entry. while (!WorkList.empty()) { SwitchWorkListItem W = WorkList.pop_back_val(); + + unsigned NumClusters = W.LastCluster - W.FirstCluster + 1; + // For optimized builds, lower large range as a balanced binary tree. + if (NumClusters > 3 && + MF->getTarget().getOptLevel() != CodeGenOptLevel::None && + !DefaultMBB->getParent()->getFunction().hasMinSize()) { + splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB, MIB); + continue; + } + if (!lowerSwitchWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB, MIB)) return false; } return true; } +void IRTranslator::splitWorkItem(SwitchCG::SwitchWorkList &WorkList, + const SwitchCG::SwitchWorkListItem &W, + Value *Cond, MachineBasicBlock *SwitchMBB, + MachineIRBuilder &MIB) { + using namespace SwitchCG; + assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && + "Clusters not sorted?"); + assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!"); + + auto [LastLeft, FirstRight, LeftProb, RightProb] = + SL->computeSplitWorkItemInfo(W); + + // Use the first element on the right as pivot since we will make less-than + // comparisons against it. + CaseClusterIt PivotCluster = FirstRight; + assert(PivotCluster > W.FirstCluster); + assert(PivotCluster <= W.LastCluster); + + CaseClusterIt FirstLeft = W.FirstCluster; + CaseClusterIt LastRight = W.LastCluster; + + const ConstantInt *Pivot = PivotCluster->Low; + + // New blocks will be inserted immediately after the current one. + MachineFunction::iterator BBI(W.MBB); + ++BBI; + + // We will branch to the LHS if Value < Pivot. If LHS is a single cluster, + // we can branch to its destination directly if it's squeezed exactly in + // between the known lower bound and Pivot - 1. + MachineBasicBlock *LeftMBB; + if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range && + FirstLeft->Low == W.GE && + (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) { + LeftMBB = FirstLeft->MBB; + } else { + LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); + FuncInfo.MF->insert(BBI, LeftMBB); + WorkList.push_back( + {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2}); + } + + // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a + // single cluster, RHS.Low == Pivot, and we can branch to its destination + // directly if RHS.High equals the current upper bound. + MachineBasicBlock *RightMBB; + if (FirstRight == LastRight && FirstRight->Kind == CC_Range && W.LT && + (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) { + RightMBB = FirstRight->MBB; + } else { + RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); + FuncInfo.MF->insert(BBI, RightMBB); + WorkList.push_back( + {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2}); + } + + // Create the CaseBlock record that will be used to lower the branch. + CaseBlock CB(ICmpInst::Predicate::ICMP_SLT, false, Cond, Pivot, nullptr, + LeftMBB, RightMBB, W.MBB, MIB.getDebugLoc(), LeftProb, + RightProb); + + if (W.MBB == SwitchMBB) + emitSwitchCase(CB, SwitchMBB, MIB); + else + SL->SwitchCases.push_back(CB); +} + void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT, MachineBasicBlock *MBB) { // Emit the code for the jump table diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll index 54c8eb913d5d..55cf48ed2245 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll @@ -17,31 +17,33 @@ define i32 @scanfile(i32 %call148) { ; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: cmp w0, #1 ; CHECK-NEXT: mov w0, wzr -; CHECK-NEXT: cbz w8, LBB0_7 +; CHECK-NEXT: b.ge LBB0_3 ; CHECK-NEXT: ; %bb.1: ; %entry -; CHECK-NEXT: cmp w8, #1 -; CHECK-NEXT: b.eq LBB0_7 -; CHECK-NEXT: ; %bb.2: ; %entry +; CHECK-NEXT: cbnz w8, LBB0_7 +; CHECK-NEXT: LBB0_2: ; %common.ret1 +; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload +; CHECK-NEXT: ret +; CHECK-NEXT: LBB0_3: ; %entry +; CHECK-NEXT: b.eq LBB0_2 +; CHECK-NEXT: ; %bb.4: ; %entry ; CHECK-NEXT: cmp w8, #2 -; CHECK-NEXT: b.eq LBB0_4 -; CHECK-NEXT: ; %bb.3: ; %entry +; CHECK-NEXT: b.eq LBB0_6 +; CHECK-NEXT: ; %bb.5: ; %entry ; CHECK-NEXT: cmp w8, #3 -; CHECK-NEXT: b.ne LBB0_5 -; CHECK-NEXT: LBB0_4: ; %sw.bb300 +; CHECK-NEXT: b.ne LBB0_2 +; CHECK-NEXT: LBB0_6: ; %sw.bb300 ; CHECK-NEXT: bl _logg ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ret -; CHECK-NEXT: LBB0_5: ; %entry +; CHECK-NEXT: LBB0_7: ; %entry ; CHECK-NEXT: cmn w8, #2 -; CHECK-NEXT: b.eq LBB0_8 -; CHECK-NEXT: ; %bb.6: ; %entry +; CHECK-NEXT: b.eq LBB0_9 +; CHECK-NEXT: ; %bb.8: ; %entry ; CHECK-NEXT: cmn w8, #1 -; CHECK-NEXT: b.eq LBB0_8 -; CHECK-NEXT: LBB0_7: ; %common.ret1 -; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload -; CHECK-NEXT: ret -; CHECK-NEXT: LBB0_8: ; %sw.bb150 +; CHECK-NEXT: b.ne LBB0_2 +; CHECK-NEXT: LBB0_9: ; %sw.bb150 ; CHECK-NEXT: bl _logg ; CHECK-NEXT: brk #0x1 entry: -- GitLab From 2642240de9b9004a431f4e601c055c8c135c9d39 Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Mon, 8 Jan 2024 08:02:44 +0000 Subject: [PATCH 031/652] [mlir] Add explicit call to flush ClangTidy performance suggested to use '\n' instead of std::endl, but it seems the flushing behavior was intended here (tests started failing). --- mlir/include/mlir/ExecutionEngine/RunnerUtils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/include/mlir/ExecutionEngine/RunnerUtils.h b/mlir/include/mlir/ExecutionEngine/RunnerUtils.h index 72001172c426..ebf95f90f374 100644 --- a/mlir/include/mlir/ExecutionEngine/RunnerUtils.h +++ b/mlir/include/mlir/ExecutionEngine/RunnerUtils.h @@ -224,7 +224,7 @@ void printMemRef(const DynamicMemRefType &m) { m.sizes, m.strides); if (m.rank == 0) std::cout << "]"; - std::cout << '\n'; + std::cout << '\n' << std::flush; } template -- GitLab From 3574b61013b341c96d5c9b7d2ca5480a398586b3 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Mon, 8 Jan 2024 08:42:08 +0000 Subject: [PATCH 032/652] [VFABI] Reject demangled variants with unexpected number of params. (#76855) When demangling a vector variant we are not checking that the number of parameters is the same as that of the scalar function. This check is hoisted out of getScalableECFromSignature() making the equvalent check in the unittests obsolete. --- llvm/lib/Analysis/VFABIDemangling.cpp | 9 ++-- .../Analysis/VectorFunctionABITest.cpp | 48 +++---------------- 2 files changed, 11 insertions(+), 46 deletions(-) diff --git a/llvm/lib/Analysis/VFABIDemangling.cpp b/llvm/lib/Analysis/VFABIDemangling.cpp index 426f98c0c628..8562d8fbfa1e 100644 --- a/llvm/lib/Analysis/VFABIDemangling.cpp +++ b/llvm/lib/Analysis/VFABIDemangling.cpp @@ -326,10 +326,6 @@ getScalableECFromSignature(const FunctionType *Signature, const VFISAKind ISA, // Only vector parameters are used when determining the VF; uniform or // linear are left as scalars, so do not affect VF. if (Param.ParamKind == VFParamKind::Vector) { - // If the scalar function doesn't actually have a corresponding argument, - // reject the mapping. - if (Param.ParamPos >= Signature->getNumParams()) - return std::nullopt; Type *PTy = Signature->getParamType(Param.ParamPos); std::optional EC = getElementCountForTy(ISA, PTy); @@ -427,6 +423,11 @@ std::optional VFABI::tryDemangleForVFABI(StringRef MangledName, if (Parameters.empty()) return std::nullopt; + // If the number of arguments of the scalar function does not match the + // vector variant we have just demangled then reject the mapping. + if (Parameters.size() != FTy->getNumParams()) + return std::nullopt; + // Figure out the number of lanes in vectors for this function variant. This // is easy for fixed length, as the vlen encoding just gives us the value // directly. However, if the vlen mangling indicated that this function diff --git a/llvm/unittests/Analysis/VectorFunctionABITest.cpp b/llvm/unittests/Analysis/VectorFunctionABITest.cpp index b72b4b3b21d4..d8a7d8245bb0 100644 --- a/llvm/unittests/Analysis/VectorFunctionABITest.cpp +++ b/llvm/unittests/Analysis/VectorFunctionABITest.cpp @@ -88,14 +88,6 @@ protected: /// Returns whether the parsed function contains a mask. bool isMasked() const { return Info.isMasked(); } - /// Check if the number of vectorized parameters matches the scalar ones. This - /// requires a correct scalar FunctionType string to be fed to the - /// 'invokeParser'. Mask parameters that are only required by the vector - /// function call are ignored. - bool matchParametersNum() { - return (Parameters.size() - isMasked()) == ScalarFTy->getNumParams(); - } - FunctionType *getFunctionType() { return VFABI::createFunctionType(Info, ScalarFTy); } @@ -162,7 +154,6 @@ TEST_F(VFABIParserTest, ParamListParsing) { invokeParser("_ZGVnN2vl16Ls32R3l_foo", "void(i32, i32, i32, ptr, i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_EQ(false, isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( Type::getVoidTy(Ctx), {VectorType::get(Type::getInt32Ty(Ctx), ElementCount::getFixed(2)), @@ -184,7 +175,6 @@ TEST_F(VFABIParserTest, ScalarNameAndVectorName_01) { EXPECT_TRUE(invokeParser("_ZGVnM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_EQ(true, isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(ScalarName, "foo"); EXPECT_EQ(VectorName, "vector_foo"); @@ -194,7 +184,6 @@ TEST_F(VFABIParserTest, ScalarNameAndVectorName_02) { EXPECT_TRUE(invokeParser("_ZGVnM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_EQ(true, isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(ScalarName, "foo"); EXPECT_EQ(VectorName, "vector_foo"); @@ -205,14 +194,13 @@ TEST_F(VFABIParserTest, ScalarNameAndVectorName_03) { invokeParser("_ZGVnM2v___foo_bar_abc(fooBarAbcVec)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_EQ(true, isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(ScalarName, "__foo_bar_abc"); EXPECT_EQ(VectorName, "fooBarAbcVec"); } TEST_F(VFABIParserTest, ScalarNameOnly) { - EXPECT_TRUE(invokeParser("_ZGVnM2v___foo_bar_abc")); + EXPECT_TRUE(invokeParser("_ZGVnM2v___foo_bar_abc", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_EQ(true, isMasked()); EXPECT_EQ(ScalarName, "__foo_bar_abc"); @@ -227,7 +215,6 @@ TEST_F(VFABIParserTest, Parse) { "void(i32, i32, i32, i32, ptr, i32, i32, i32, ptr)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( Type::getVoidTy(Ctx), { @@ -262,7 +249,6 @@ TEST_F(VFABIParserTest, ParseVectorName) { EXPECT_TRUE(invokeParser("_ZGVnN2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyNoMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)1); @@ -276,7 +262,6 @@ TEST_F(VFABIParserTest, LinearWithCompileTimeNegativeStep) { "void(i32, i32, i32, ptr)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( Type::getVoidTy(Ctx), {Type::getInt32Ty(Ctx), Type::getInt32Ty(Ctx), Type::getInt32Ty(Ctx), @@ -297,7 +282,6 @@ TEST_F(VFABIParserTest, ParseScalableSVE) { EXPECT_TRUE(invokeParser("_ZGVsMxv_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskedVLA_i32); EXPECT_EQ(VF, ElementCount::getScalable(4)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -311,7 +295,6 @@ TEST_F(VFABIParserTest, ParseFixedWidthSVE) { EXPECT_TRUE(invokeParser("_ZGVsM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -329,16 +312,16 @@ TEST_F(VFABIParserTest, NotAVectorFunctionABIName) { TEST_F(VFABIParserTest, LinearWithRuntimeStep) { EXPECT_FALSE(invokeParser("_ZGVnN2ls_foo")) << "A number should be present after \"ls\"."; - EXPECT_TRUE(invokeParser("_ZGVnN2ls2_foo")); + EXPECT_TRUE(invokeParser("_ZGVnN2ls2_foo", "void(i32)")); EXPECT_FALSE(invokeParser("_ZGVnN2Rs_foo")) << "A number should be present after \"Rs\"."; - EXPECT_TRUE(invokeParser("_ZGVnN2Rs4_foo")); + EXPECT_TRUE(invokeParser("_ZGVnN2Rs4_foo", "void(i32)")); EXPECT_FALSE(invokeParser("_ZGVnN2Ls_foo")) << "A number should be present after \"Ls\"."; - EXPECT_TRUE(invokeParser("_ZGVnN2Ls6_foo")); + EXPECT_TRUE(invokeParser("_ZGVnN2Ls6_foo", "void(i32)")); EXPECT_FALSE(invokeParser("_ZGVnN2Us_foo")) << "A number should be present after \"Us\"."; - EXPECT_TRUE(invokeParser("_ZGVnN2Us8_foo")); + EXPECT_TRUE(invokeParser("_ZGVnN2Us8_foo", "void(i32)")); } TEST_F(VFABIParserTest, LinearWithoutCompileTime) { @@ -346,7 +329,6 @@ TEST_F(VFABIParserTest, LinearWithoutCompileTime) { "void(i32, i32, ptr, i32, i32, i32, ptr, i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( Type::getVoidTy(Ctx), {Type::getInt32Ty(Ctx), Type::getInt32Ty(Ctx), @@ -373,7 +355,6 @@ TEST_F(VFABIParserTest, LLVM_ISA) { EXPECT_TRUE(invokeParser("_ZGV_LLVM_N2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::LLVM); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyNoMaskVLen2_i32); EXPECT_EQ(Parameters.size(), (unsigned)1); EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector})); @@ -393,7 +374,6 @@ TEST_F(VFABIParserTest, Align) { EXPECT_TRUE(invokeParser("_ZGVsN2l2a2_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(Parameters.size(), (unsigned)1); EXPECT_EQ(Parameters[0].Alignment, Align(2)); EXPECT_EQ(ScalarName, "foo"); @@ -409,7 +389,7 @@ TEST_F(VFABIParserTest, Align) { EXPECT_FALSE(invokeParser("_ZGVsM2a2_foo")); // Alignment must be a power of 2. EXPECT_FALSE(invokeParser("_ZGVsN2l2a0_foo")); - EXPECT_TRUE(invokeParser("_ZGVsN2l2a1_foo")); + EXPECT_TRUE(invokeParser("_ZGVsN2l2a1_foo", "void(i32)")); EXPECT_FALSE(invokeParser("_ZGVsN2l2a3_foo")); EXPECT_FALSE(invokeParser("_ZGVsN2l2a6_foo")); } @@ -418,7 +398,6 @@ TEST_F(VFABIParserTest, ParseUniform) { EXPECT_TRUE(invokeParser("_ZGVnN2u_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get(Type::getVoidTy(Ctx), {Type::getInt32Ty(Ctx)}, false); EXPECT_EQ(getFunctionType(), FTy); @@ -463,7 +442,6 @@ TEST_F(VFABIParserTest, ISAIndependentMangling) { do { \ EXPECT_EQ(VF, ElementCount::getFixed(2)); \ EXPECT_FALSE(isMasked()); \ - EXPECT_TRUE(matchParametersNum()); \ EXPECT_EQ(getFunctionType(), FTy); \ EXPECT_EQ(Parameters.size(), (unsigned)10); \ EXPECT_EQ(Parameters, ExpectedParams); \ @@ -539,7 +517,6 @@ TEST_F(VFABIParserTest, ParseMaskingNEON) { EXPECT_TRUE(invokeParser("_ZGVnM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -553,7 +530,6 @@ TEST_F(VFABIParserTest, ParseMaskingSVE) { EXPECT_TRUE(invokeParser("_ZGVsM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -567,7 +543,6 @@ TEST_F(VFABIParserTest, ParseMaskingSSE) { EXPECT_TRUE(invokeParser("_ZGVbM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::SSE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -581,7 +556,6 @@ TEST_F(VFABIParserTest, ParseMaskingAVX) { EXPECT_TRUE(invokeParser("_ZGVcM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AVX); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -595,7 +569,6 @@ TEST_F(VFABIParserTest, ParseMaskingAVX2) { EXPECT_TRUE(invokeParser("_ZGVdM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AVX2); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -609,7 +582,6 @@ TEST_F(VFABIParserTest, ParseMaskingAVX512) { EXPECT_TRUE(invokeParser("_ZGVeM2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::AVX512); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -623,7 +595,6 @@ TEST_F(VFABIParserTest, ParseMaskingLLVM) { EXPECT_TRUE(invokeParser("_ZGV_LLVM_M2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::LLVM); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskVLen2_i32); EXPECT_EQ(VF, ElementCount::getFixed(2)); EXPECT_EQ(Parameters.size(), (unsigned)2); @@ -642,7 +613,6 @@ TEST_F(VFABIParserTest, LLVM_InternalISA) { EXPECT_TRUE(invokeParser("_ZGV_LLVM_N2v_foo(vector_foo)", "void(i32)")); EXPECT_EQ(ISA, VFISAKind::LLVM); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyNoMaskVLen2_i32); EXPECT_EQ(Parameters.size(), (unsigned)1); EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector})); @@ -655,7 +625,6 @@ TEST_F(VFABIParserTest, LLVM_Intrinsics) { "void(float, float)")); EXPECT_EQ(ISA, VFISAKind::LLVM); EXPECT_FALSE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( Type::getVoidTy(Ctx), { @@ -678,7 +647,6 @@ TEST_F(VFABIParserTest, ParseScalableRequiresDeclaration) { EXPECT_TRUE(invokeParser(MangledName, "void(i32)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); EXPECT_EQ(getFunctionType(), FTyMaskedVLA_i32); EXPECT_EQ(Parameters.size(), (unsigned)2); EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector})); @@ -698,7 +666,6 @@ TEST_F(VFABIParserTest, ParseScalableMaskingSVE) { EXPECT_TRUE(invokeParser("_ZGVsMxv_foo(vector_foo)", "i32(i32)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( VectorType::get(Type::getInt32Ty(Ctx), ElementCount::getScalable(4)), {VectorType::get(Type::getInt32Ty(Ctx), ElementCount::getScalable(4)), @@ -718,7 +685,6 @@ TEST_F(VFABIParserTest, ParseScalableMaskingSVESincos) { "void(double, ptr, ptr)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( Type::getVoidTy(Ctx), { @@ -745,7 +711,6 @@ TEST_F(VFABIParserTest, ParseWiderReturnTypeSVE) { EXPECT_TRUE(invokeParser("_ZGVsMxvv_foo(vector_foo)", "i64(i32, i32)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( VectorType::get(Type::getInt64Ty(Ctx), ElementCount::getScalable(2)), { @@ -769,7 +734,6 @@ TEST_F(VFABIParserTest, ParseVoidReturnTypeSVE) { EXPECT_TRUE(invokeParser("_ZGVsMxv_foo(vector_foo)", "void(i16)")); EXPECT_EQ(ISA, VFISAKind::SVE); EXPECT_TRUE(isMasked()); - EXPECT_TRUE(matchParametersNum()); FunctionType *FTy = FunctionType::get( Type::getVoidTy(Ctx), { -- GitLab From 1c674666fa3bc0cf6d62d920bdddc846b8105d12 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Mon, 8 Jan 2024 16:50:23 +0800 Subject: [PATCH 033/652] [X86] Support EVEX compression for EGPR (#77202) Compress promoted instruction (EVEX) to pre-promotion instruction (legacy/VEX) when R16-R31 is not used. Alternative of #77065 --- llvm/lib/Target/X86/X86CompressEVEX.cpp | 8 +++-- llvm/lib/Target/X86/X86InstrInfo.h | 4 ++- llvm/lib/Target/X86/X86MCInstLower.cpp | 7 +++-- .../X86/crc32-intrinsics-fast-isel-x86.ll | 6 ++-- .../X86/crc32-intrinsics-fast-isel-x86_64.ll | 4 +-- llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll | 6 ++-- .../CodeGen/X86/crc32-intrinsics-x86_64.ll | 4 +-- llvm/test/CodeGen/X86/invpcid-intrinsic.ll | 4 +-- llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll | 4 +-- .../CodeGen/X86/movdir-intrinsic-x86_64.ll | 2 +- llvm/test/CodeGen/X86/sha.ll | 30 +++++++++---------- llvm/test/CodeGen/X86/x64-cet-intrinsics.ll | 8 ++--- .../TableGen/X86CompressEVEXTablesEmitter.cpp | 9 ++++-- 13 files changed, 53 insertions(+), 43 deletions(-) diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp index 3e839683b039..b5928b93ffff 100644 --- a/llvm/lib/Target/X86/X86CompressEVEX.cpp +++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp @@ -252,8 +252,12 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { if (!performCustomAdjustments(MI, I->NewOpc)) return false; - MI.setDesc(ST.getInstrInfo()->get(I->NewOpc)); - MI.setAsmPrinterFlag(X86::AC_EVEX_2_VEX); + const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc); + MI.setDesc(NewDesc); + uint64_t Encoding = NewDesc.TSFlags & X86II::EncodingMask; + auto AsmComment = + (Encoding == X86II::VEX) ? X86::AC_EVEX_2_VEX : X86::AC_EVEX_2_LEGACY; + MI.setAsmPrinterFlag(AsmComment); return true; } diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index eac8d79eb8a3..eb0734f9a618 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -29,8 +29,10 @@ class X86Subtarget; namespace X86 { enum AsmComments { + // For instr that was compressed from EVEX to LEGACY. + AC_EVEX_2_LEGACY = MachineInstr::TAsmComments, // For instr that was compressed from EVEX to VEX. - AC_EVEX_2_VEX = MachineInstr::TAsmComments + AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1 }; /// Return a pair of condition code for the given predicate and whether diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index e1a67f61e766..133ee2041565 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -2055,10 +2055,11 @@ void X86AsmPrinter::emitInstruction(const MachineInstr *MI) { } } - // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that - // are compressed from EVEX encoding to VEX encoding. + // Add a comment about EVEX compression if (TM.Options.MCOptions.ShowMCEncoding) { - if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) + if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_LEGACY) + OutStreamer->AddComment("EVEX TO LEGACY Compression ", false); + else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) OutStreamer->AddComment("EVEX TO VEX Compression ", false); } diff --git a/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll b/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll index 873986e99777..fe5182e5ef73 100644 --- a/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll +++ b/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll @@ -29,7 +29,7 @@ define i32 @test_mm_crc32_u8(i32 %a0, i32 %a1) nounwind { ; EGPR-LABEL: test_mm_crc32_u8: ; EGPR: # %bb.0: ; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8] -; EGPR-NEXT: crc32b %sil, %eax # encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xc6] +; EGPR-NEXT: crc32b %sil, %eax # EVEX TO LEGACY Compression encoding: [0xf2,0x40,0x0f,0x38,0xf0,0xc6] ; EGPR-NEXT: retq # encoding: [0xc3] %trunc = trunc i32 %a1 to i8 %res = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a0, i8 %trunc) @@ -55,7 +55,7 @@ define i32 @test_mm_crc32_u16(i32 %a0, i32 %a1) nounwind { ; EGPR-LABEL: test_mm_crc32_u16: ; EGPR: # %bb.0: ; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8] -; EGPR-NEXT: crc32w %si, %eax # encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xc6] +; EGPR-NEXT: crc32w %si, %eax # EVEX TO LEGACY Compression encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc6] ; EGPR-NEXT: retq # encoding: [0xc3] %trunc = trunc i32 %a1 to i16 %res = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a0, i16 %trunc) @@ -79,7 +79,7 @@ define i32 @test_mm_crc32_u32(i32 %a0, i32 %a1) nounwind { ; EGPR-LABEL: test_mm_crc32_u32: ; EGPR: # %bb.0: ; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8] -; EGPR-NEXT: crc32l %esi, %eax # encoding: [0x62,0xf4,0x7c,0x08,0xf1,0xc6] +; EGPR-NEXT: crc32l %esi, %eax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf1,0xc6] ; EGPR-NEXT: retq # encoding: [0xc3] %res = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a0, i32 %a1) ret i32 %res diff --git a/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll b/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll index 71d955bda752..ba5f846c22db 100644 --- a/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll +++ b/llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll @@ -15,7 +15,7 @@ define i64 @test_mm_crc64_u8(i64 %a0, i32 %a1) nounwind{ ; ; EGPR-LABEL: test_mm_crc64_u8: ; EGPR: # %bb.0: -; EGPR-NEXT: crc32b %sil, %edi # encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xfe] +; EGPR-NEXT: crc32b %sil, %edi # EVEX TO LEGACY Compression encoding: [0xf2,0x40,0x0f,0x38,0xf0,0xfe] ; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8] ; EGPR-NEXT: retq # encoding: [0xc3] %trunc = trunc i32 %a1 to i8 @@ -34,7 +34,7 @@ define i64 @test_mm_crc64_u64(i64 %a0, i64 %a1) nounwind{ ; EGPR-LABEL: test_mm_crc64_u64: ; EGPR: # %bb.0: ; EGPR-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8] -; EGPR-NEXT: crc32q %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x08,0xf1,0xc6] +; EGPR-NEXT: crc32q %rsi, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x48,0x0f,0x38,0xf1,0xc6] ; EGPR-NEXT: retq # encoding: [0xc3] %res = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a0, i64 %a1) ret i64 %res diff --git a/llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll b/llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll index 84c7f90cfe3c..ea4e0ffb109c 100644 --- a/llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll +++ b/llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll @@ -19,7 +19,7 @@ define i32 @crc32_32_8(i32 %a, i8 %b) nounwind { ; EGPR-LABEL: crc32_32_8: ; EGPR: ## %bb.0: ; EGPR-NEXT: movl %edi, %eax ## encoding: [0x89,0xf8] -; EGPR-NEXT: crc32b %sil, %eax ## encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xc6] +; EGPR-NEXT: crc32b %sil, %eax ## EVEX TO LEGACY Compression encoding: [0xf2,0x40,0x0f,0x38,0xf0,0xc6] ; EGPR-NEXT: retq ## encoding: [0xc3] %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b) ret i32 %tmp @@ -42,7 +42,7 @@ define i32 @crc32_32_16(i32 %a, i16 %b) nounwind { ; EGPR-LABEL: crc32_32_16: ; EGPR: ## %bb.0: ; EGPR-NEXT: movl %edi, %eax ## encoding: [0x89,0xf8] -; EGPR-NEXT: crc32w %si, %eax ## encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xc6] +; EGPR-NEXT: crc32w %si, %eax ## EVEX TO LEGACY Compression encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc6] ; EGPR-NEXT: retq ## encoding: [0xc3] %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b) ret i32 %tmp @@ -65,7 +65,7 @@ define i32 @crc32_32_32(i32 %a, i32 %b) nounwind { ; EGPR-LABEL: crc32_32_32: ; EGPR: ## %bb.0: ; EGPR-NEXT: movl %edi, %eax ## encoding: [0x89,0xf8] -; EGPR-NEXT: crc32l %esi, %eax ## encoding: [0x62,0xf4,0x7c,0x08,0xf1,0xc6] +; EGPR-NEXT: crc32l %esi, %eax ## EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf1,0xc6] ; EGPR-NEXT: retq ## encoding: [0xc3] %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b) ret i32 %tmp diff --git a/llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll b/llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll index bda26a15b277..af2b590b1f6b 100644 --- a/llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll +++ b/llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll @@ -15,7 +15,7 @@ define i64 @crc32_64_8(i64 %a, i8 %b) nounwind { ; EGPR-LABEL: crc32_64_8: ; EGPR: ## %bb.0: ; EGPR-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] -; EGPR-NEXT: crc32b %sil, %eax ## encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xc6] +; EGPR-NEXT: crc32b %sil, %eax ## EVEX TO LEGACY Compression encoding: [0xf2,0x40,0x0f,0x38,0xf0,0xc6] ; EGPR-NEXT: retq ## encoding: [0xc3] %tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b) ret i64 %tmp @@ -31,7 +31,7 @@ define i64 @crc32_64_64(i64 %a, i64 %b) nounwind { ; EGPR-LABEL: crc32_64_64: ; EGPR: ## %bb.0: ; EGPR-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] -; EGPR-NEXT: crc32q %rsi, %rax ## encoding: [0x62,0xf4,0xfc,0x08,0xf1,0xc6] +; EGPR-NEXT: crc32q %rsi, %rax ## EVEX TO LEGACY Compression encoding: [0xf2,0x48,0x0f,0x38,0xf1,0xc6] ; EGPR-NEXT: retq ## encoding: [0xc3] %tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b) ret i64 %tmp diff --git a/llvm/test/CodeGen/X86/invpcid-intrinsic.ll b/llvm/test/CodeGen/X86/invpcid-intrinsic.ll index 19a6249fc708..66f7855239c0 100644 --- a/llvm/test/CodeGen/X86/invpcid-intrinsic.ll +++ b/llvm/test/CodeGen/X86/invpcid-intrinsic.ll @@ -20,7 +20,7 @@ define void @test_invpcid(i32 %type, ptr %descriptor) { ; EGPR-LABEL: test_invpcid: ; EGPR: # %bb.0: # %entry ; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8] -; EGPR-NEXT: invpcid (%rsi), %rax # encoding: [0x62,0xf4,0x7e,0x08,0xf2,0x06] +; EGPR-NEXT: invpcid (%rsi), %rax # EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0x82,0x06] ; EGPR-NEXT: retq # encoding: [0xc3] entry: call void @llvm.x86.invpcid(i32 %type, ptr %descriptor) @@ -45,7 +45,7 @@ define void @test_invpcid2(ptr readonly %type, ptr %descriptor) { ; EGPR-LABEL: test_invpcid2: ; EGPR: # %bb.0: # %entry ; EGPR-NEXT: movl (%rdi), %eax # encoding: [0x8b,0x07] -; EGPR-NEXT: invpcid (%rsi), %rax # encoding: [0x62,0xf4,0x7e,0x08,0xf2,0x06] +; EGPR-NEXT: invpcid (%rsi), %rax # EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0x82,0x06] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = load i32, ptr %type, align 4 diff --git a/llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll b/llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll index 4d03510ad5d4..023dfb110502 100644 --- a/llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll +++ b/llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll @@ -18,7 +18,7 @@ define void @test_movdiri(ptr %p, i32 %v) { ; ; EGPR-LABEL: test_movdiri: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: movdiri %esi, (%rdi) # encoding: [0x62,0xf4,0x7c,0x08,0xf9,0x37] +; EGPR-NEXT: movdiri %esi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xf9,0x37] ; EGPR-NEXT: retq # encoding: [0xc3] entry: call void @llvm.x86.directstore32(ptr %p, i32 %v) @@ -42,7 +42,7 @@ define void @test_movdir64b(ptr %dst, ptr %src) { ; ; EGPR-LABEL: test_movdir64b: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: movdir64b (%rsi), %rdi # encoding: [0x62,0xf4,0x7d,0x08,0xf8,0x3e] +; EGPR-NEXT: movdir64b (%rsi), %rdi # EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0xf8,0x3e] ; EGPR-NEXT: retq # encoding: [0xc3] entry: call void @llvm.x86.movdir64b(ptr %dst, ptr %src) diff --git a/llvm/test/CodeGen/X86/movdir-intrinsic-x86_64.ll b/llvm/test/CodeGen/X86/movdir-intrinsic-x86_64.ll index ddd44f6d73d5..e3736e29a582 100644 --- a/llvm/test/CodeGen/X86/movdir-intrinsic-x86_64.ll +++ b/llvm/test/CodeGen/X86/movdir-intrinsic-x86_64.ll @@ -10,7 +10,7 @@ define void @test_movdiri(ptr %p, i64 %v) { ; ; EGPR-LABEL: test_movdiri: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: movdiri %rsi, (%rdi) # encoding: [0x62,0xf4,0xfc,0x08,0xf9,0x37] +; EGPR-NEXT: movdiri %rsi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x38,0xf9,0x37] ; EGPR-NEXT: retq # encoding: [0xc3] entry: call void @llvm.x86.directstore64(ptr %p, i64 %v) diff --git a/llvm/test/CodeGen/X86/sha.ll b/llvm/test/CodeGen/X86/sha.ll index d8fa354a3913..65222ba74023 100644 --- a/llvm/test/CodeGen/X86/sha.ll +++ b/llvm/test/CodeGen/X86/sha.ll @@ -18,7 +18,7 @@ define <4 x i32> @test_sha1rnds4rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable ; ; EGPR-LABEL: test_sha1rnds4rr: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1rnds4 $3, %xmm1, %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xd4,0xc1,0x03] +; EGPR-NEXT: sha1rnds4 $3, %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x3a,0xcc,0xc1,0x03] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3) @@ -38,7 +38,7 @@ define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, ptr %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha1rnds4rm: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xd4,0x07,0x03] +; EGPR-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x3a,0xcc,0x07,0x03] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = load <4 x i32>, ptr %b @@ -61,7 +61,7 @@ define <4 x i32> @test_sha1nexterr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable ; ; EGPR-LABEL: test_sha1nexterr: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1nexte %xmm1, %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xd8,0xc1] +; EGPR-NEXT: sha1nexte %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc8,0xc1] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b) @@ -81,7 +81,7 @@ define <4 x i32> @test_sha1nexterm(<4 x i32> %a, ptr %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha1nexterm: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1nexte (%rdi), %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xd8,0x07] +; EGPR-NEXT: sha1nexte (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc8,0x07] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = load <4 x i32>, ptr %b @@ -104,7 +104,7 @@ define <4 x i32> @test_sha1msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha1msg1rr: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1msg1 %xmm1, %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xd9,0xc1] +; EGPR-NEXT: sha1msg1 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc9,0xc1] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b) @@ -124,7 +124,7 @@ define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, ptr %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha1msg1rm: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1msg1 (%rdi), %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xd9,0x07] +; EGPR-NEXT: sha1msg1 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc9,0x07] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = load <4 x i32>, ptr %b @@ -147,7 +147,7 @@ define <4 x i32> @test_sha1msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha1msg2rr: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1msg2 %xmm1, %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xda,0xc1] +; EGPR-NEXT: sha1msg2 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xca,0xc1] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b) @@ -167,7 +167,7 @@ define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, ptr %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha1msg2rm: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1msg2 (%rdi), %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xda,0x07] +; EGPR-NEXT: sha1msg2 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xca,0x07] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = load <4 x i32>, ptr %b @@ -198,7 +198,7 @@ define <4 x i32> @test_sha256rnds2rr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) n ; EGPR: # %bb.0: # %entry ; EGPR-NEXT: movaps %xmm0, %xmm3 # encoding: [0x0f,0x28,0xd8] ; EGPR-NEXT: movaps %xmm2, %xmm0 # encoding: [0x0f,0x28,0xc2] -; EGPR-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3 # encoding: [0x62,0xf4,0x7c,0x08,0xdb,0xd9] +; EGPR-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcb,0xd9] ; EGPR-NEXT: movaps %xmm3, %xmm0 # encoding: [0x0f,0x28,0xc3] ; EGPR-NEXT: retq # encoding: [0xc3] entry: @@ -227,7 +227,7 @@ define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, ptr %b, <4 x i32> %c) nounwin ; EGPR: # %bb.0: # %entry ; EGPR-NEXT: movaps %xmm0, %xmm2 # encoding: [0x0f,0x28,0xd0] ; EGPR-NEXT: movaps %xmm1, %xmm0 # encoding: [0x0f,0x28,0xc1] -; EGPR-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2 # encoding: [0x62,0xf4,0x7c,0x08,0xdb,0x17] +; EGPR-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcb,0x17] ; EGPR-NEXT: movaps %xmm2, %xmm0 # encoding: [0x0f,0x28,0xc2] ; EGPR-NEXT: retq # encoding: [0xc3] entry: @@ -251,7 +251,7 @@ define <4 x i32> @test_sha256msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable ; ; EGPR-LABEL: test_sha256msg1rr: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha256msg1 %xmm1, %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xdc,0xc1] +; EGPR-NEXT: sha256msg1 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcc,0xc1] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %b) @@ -271,7 +271,7 @@ define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, ptr %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha256msg1rm: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha256msg1 (%rdi), %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xdc,0x07] +; EGPR-NEXT: sha256msg1 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcc,0x07] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = load <4 x i32>, ptr %b @@ -294,7 +294,7 @@ define <4 x i32> @test_sha256msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable ; ; EGPR-LABEL: test_sha256msg2rr: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha256msg2 %xmm1, %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xdd,0xc1] +; EGPR-NEXT: sha256msg2 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcd,0xc1] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %b) @@ -314,7 +314,7 @@ define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, ptr %b) nounwind uwtable { ; ; EGPR-LABEL: test_sha256msg2rm: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha256msg2 (%rdi), %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xdd,0x07] +; EGPR-NEXT: sha256msg2 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcd,0x07] ; EGPR-NEXT: retq # encoding: [0xc3] entry: %0 = load <4 x i32>, ptr %b @@ -338,7 +338,7 @@ define <8 x i32> @test_sha1rnds4_zero_extend(<4 x i32> %a, ptr %b) nounwind uwta ; ; EGPR-LABEL: test_sha1rnds4_zero_extend: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # encoding: [0x62,0xf4,0x7c,0x08,0xd4,0x07,0x03] +; EGPR-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x3a,0xcc,0x07,0x03] ; EGPR-NEXT: xorps %xmm1, %xmm1 # encoding: [0x0f,0x57,0xc9] ; EGPR-NEXT: retq # encoding: [0xc3] entry: diff --git a/llvm/test/CodeGen/X86/x64-cet-intrinsics.ll b/llvm/test/CodeGen/X86/x64-cet-intrinsics.ll index bf87ae5cac05..f73e26a309aa 100644 --- a/llvm/test/CodeGen/X86/x64-cet-intrinsics.ll +++ b/llvm/test/CodeGen/X86/x64-cet-intrinsics.ll @@ -119,7 +119,7 @@ define void @test_wrssd(i32 %a, ptr %__p) { ; ; EGPR-LABEL: test_wrssd: ; EGPR: ## %bb.0: ## %entry -; EGPR-NEXT: wrssd %edi, (%rsi) ## encoding: [0x62,0xf4,0x7c,0x08,0x66,0x3e] +; EGPR-NEXT: wrssd %edi, (%rsi) ## EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xf6,0x3e] ; EGPR-NEXT: retq ## encoding: [0xc3] entry: tail call void @llvm.x86.wrssd(i32 %a, ptr %__p) @@ -136,7 +136,7 @@ define void @test_wrssq(i64 %a, ptr %__p) { ; ; EGPR-LABEL: test_wrssq: ; EGPR: ## %bb.0: ## %entry -; EGPR-NEXT: wrssq %rdi, (%rsi) ## encoding: [0x62,0xf4,0xfc,0x08,0x66,0x3e] +; EGPR-NEXT: wrssq %rdi, (%rsi) ## EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x38,0xf6,0x3e] ; EGPR-NEXT: retq ## encoding: [0xc3] entry: tail call void @llvm.x86.wrssq(i64 %a, ptr %__p) @@ -153,7 +153,7 @@ define void @test_wrussd(i32 %a, ptr %__p) { ; ; EGPR-LABEL: test_wrussd: ; EGPR: ## %bb.0: ## %entry -; EGPR-NEXT: wrussd %edi, (%rsi) ## encoding: [0x62,0xf4,0x7d,0x08,0x65,0x3e] +; EGPR-NEXT: wrussd %edi, (%rsi) ## EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0xf5,0x3e] ; EGPR-NEXT: retq ## encoding: [0xc3] entry: tail call void @llvm.x86.wrussd(i32 %a, ptr %__p) @@ -170,7 +170,7 @@ define void @test_wrussq(i64 %a, ptr %__p) { ; ; EGPR-LABEL: test_wrussq: ; EGPR: ## %bb.0: ## %entry -; EGPR-NEXT: wrussq %rdi, (%rsi) ## encoding: [0x62,0xf4,0xfd,0x08,0x65,0x3e] +; EGPR-NEXT: wrussq %rdi, (%rsi) ## EVEX TO LEGACY Compression encoding: [0x66,0x48,0x0f,0x38,0xf5,0x3e] ; EGPR-NEXT: retq ## encoding: [0xc3] entry: tail call void @llvm.x86.wrussq(i64 %a, ptr %__p) diff --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp index b03bcb6bc26b..8366d044eb37 100644 --- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp @@ -166,13 +166,16 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) { for (const CodeGenInstruction *Inst : PreCompressionInsts) { const Record *Rec = Inst->TheDef; - uint8_t Opcode = - byteFromBitsInit(Inst->TheDef->getValueAsBitsInit("Opcode")); + uint8_t Opcode = byteFromBitsInit(Rec->getValueAsBitsInit("Opcode")); + StringRef Name = Rec->getName(); const CodeGenInstruction *NewInst = nullptr; - if (ManualMap.find(Rec->getName()) != ManualMap.end()) { + if (ManualMap.find(Name) != ManualMap.end()) { Record *NewRec = Records.getDef(ManualMap.at(Rec->getName())); assert(NewRec && "Instruction not found!"); NewInst = &Target.getInstruction(NewRec); + } else if (Name.ends_with("_EVEX")) { + if (auto *NewRec = Records.getDef(Name.drop_back(5))) + NewInst = &Target.getInstruction(NewRec); } else { // For each pre-compression instruction look for a match in the appropriate // vector (instructions with the same opcode) using function object -- GitLab From 68a1583a8900fe13e33fe9ff6005f7a3e5b82c53 Mon Sep 17 00:00:00 2001 From: Paschalis Mpeis Date: Mon, 8 Jan 2024 10:53:15 +0200 Subject: [PATCH 034/652] [TLI] replace-with-veclib works with FRem Instruction. (#76166) Updated SLEEF and ArmPL tests with Fixed-Width and Scalable cases for frem. Those are mapped to fmod/fmodf. --- llvm/lib/CodeGen/ReplaceWithVeclib.cpp | 160 ++++++++++-------- ...-armpl.ll => replace-with-veclib-armpl.ll} | 42 ++++- ... => replace-with-veclib-sleef-scalable.ll} | 20 ++- ...-sleef.ll => replace-with-veclib-sleef.ll} | 20 ++- 4 files changed, 169 insertions(+), 73 deletions(-) rename llvm/test/CodeGen/AArch64/{replace-intrinsics-with-veclib-armpl.ll => replace-with-veclib-armpl.ll} (91%) rename llvm/test/CodeGen/AArch64/{replace-intrinsics-with-veclib-sleef-scalable.ll => replace-with-veclib-sleef-scalable.ll} (95%) rename llvm/test/CodeGen/AArch64/{replace-intrinsics-with-veclib-sleef.ll => replace-with-veclib-sleef.ll} (95%) diff --git a/llvm/lib/CodeGen/ReplaceWithVeclib.cpp b/llvm/lib/CodeGen/ReplaceWithVeclib.cpp index 893aa4a91828..56025aa5c45f 100644 --- a/llvm/lib/CodeGen/ReplaceWithVeclib.cpp +++ b/llvm/lib/CodeGen/ReplaceWithVeclib.cpp @@ -6,9 +6,9 @@ // //===----------------------------------------------------------------------===// // -// Replaces calls to LLVM vector intrinsics (i.e., calls to LLVM intrinsics -// with vector operands) with matching calls to functions from a vector -// library (e.g., libmvec, SVML) according to TargetLibraryInfo. +// Replaces LLVM IR instructions with vector operands (i.e., the frem +// instruction or calls to LLVM intrinsics) with matching calls to functions +// from a vector library (e.g libmvec, SVML) using TargetLibraryInfo interface. // //===----------------------------------------------------------------------===// @@ -69,88 +69,98 @@ Function *getTLIFunction(Module *M, FunctionType *VectorFTy, return TLIFunc; } -/// Replace the call to the vector intrinsic ( \p CalltoReplace ) with a call to -/// the corresponding function from the vector library ( \p TLIVecFunc ). -static void replaceWithTLIFunction(CallInst &CalltoReplace, VFInfo &Info, +/// Replace the instruction \p I with a call to the corresponding function from +/// the vector library (\p TLIVecFunc). +static void replaceWithTLIFunction(Instruction &I, VFInfo &Info, Function *TLIVecFunc) { - IRBuilder<> IRBuilder(&CalltoReplace); - SmallVector Args(CalltoReplace.args()); + IRBuilder<> IRBuilder(&I); + auto *CI = dyn_cast(&I); + SmallVector Args(CI ? CI->args() : I.operands()); if (auto OptMaskpos = Info.getParamIndexForOptionalMask()) { - auto *MaskTy = VectorType::get(Type::getInt1Ty(CalltoReplace.getContext()), - Info.Shape.VF); + auto *MaskTy = + VectorType::get(Type::getInt1Ty(I.getContext()), Info.Shape.VF); Args.insert(Args.begin() + OptMaskpos.value(), Constant::getAllOnesValue(MaskTy)); } - // Preserve the operand bundles. + // If it is a call instruction, preserve the operand bundles. SmallVector OpBundles; - CalltoReplace.getOperandBundlesAsDefs(OpBundles); - CallInst *Replacement = IRBuilder.CreateCall(TLIVecFunc, Args, OpBundles); - CalltoReplace.replaceAllUsesWith(Replacement); + if (CI) + CI->getOperandBundlesAsDefs(OpBundles); + + auto *Replacement = IRBuilder.CreateCall(TLIVecFunc, Args, OpBundles); + I.replaceAllUsesWith(Replacement); // Preserve fast math flags for FP math. if (isa(Replacement)) - Replacement->copyFastMathFlags(&CalltoReplace); + Replacement->copyFastMathFlags(&I); } -/// Returns true when successfully replaced \p CallToReplace with a suitable -/// function taking vector arguments, based on available mappings in the \p TLI. -/// Currently only works when \p CallToReplace is a call to vectorized -/// intrinsic. +/// Returns true when successfully replaced \p I with a suitable function taking +/// vector arguments, based on available mappings in the \p TLI. Currently only +/// works when \p I is a call to vectorized intrinsic or the frem instruction. static bool replaceWithCallToVeclib(const TargetLibraryInfo &TLI, - CallInst &CallToReplace) { - if (!CallToReplace.getCalledFunction()) - return false; + Instruction &I) { + // At the moment VFABI assumes the return type is always widened unless it is + // a void type. + auto *VTy = dyn_cast(I.getType()); + ElementCount EC(VTy ? VTy->getElementCount() : ElementCount::getFixed(0)); - auto IntrinsicID = CallToReplace.getCalledFunction()->getIntrinsicID(); - // Replacement is only performed for intrinsic functions. - if (IntrinsicID == Intrinsic::not_intrinsic) - return false; - - // Compute arguments types of the corresponding scalar call. Additionally - // checks if in the vector call, all vector operands have the same EC. - ElementCount VF = ElementCount::getFixed(0); - SmallVector ScalarArgTypes; - for (auto Arg : enumerate(CallToReplace.args())) { - auto *ArgTy = Arg.value()->getType(); - if (isVectorIntrinsicWithScalarOpAtArg(IntrinsicID, Arg.index())) { - ScalarArgTypes.push_back(ArgTy); - } else if (auto *VectorArgTy = dyn_cast(ArgTy)) { - ScalarArgTypes.push_back(ArgTy->getScalarType()); - // Disallow vector arguments with different VFs. When processing the first - // vector argument, store it's VF, and for the rest ensure that they match - // it. - if (VF.isZero()) - VF = VectorArgTy->getElementCount(); - else if (VF != VectorArgTy->getElementCount()) + // Compute the argument types of the corresponding scalar call and the scalar + // function name. For calls, it additionally finds the function to replace + // and checks that all vector operands match the previously found EC. + SmallVector ScalarArgTypes; + std::string ScalarName; + Function *FuncToReplace = nullptr; + if (auto *CI = dyn_cast(&I)) { + FuncToReplace = CI->getCalledFunction(); + Intrinsic::ID IID = FuncToReplace->getIntrinsicID(); + assert(IID != Intrinsic::not_intrinsic && "Not an intrinsic"); + for (auto Arg : enumerate(CI->args())) { + auto *ArgTy = Arg.value()->getType(); + if (isVectorIntrinsicWithScalarOpAtArg(IID, Arg.index())) { + ScalarArgTypes.push_back(ArgTy); + } else if (auto *VectorArgTy = dyn_cast(ArgTy)) { + ScalarArgTypes.push_back(VectorArgTy->getElementType()); + // When return type is void, set EC to the first vector argument, and + // disallow vector arguments with different ECs. + if (EC.isZero()) + EC = VectorArgTy->getElementCount(); + else if (EC != VectorArgTy->getElementCount()) + return false; + } else + // Exit when it is supposed to be a vector argument but it isn't. return false; - } else - // Exit when it is supposed to be a vector argument but it isn't. + } + // Try to reconstruct the name for the scalar version of the instruction, + // using scalar argument types. + ScalarName = Intrinsic::isOverloaded(IID) + ? Intrinsic::getName(IID, ScalarArgTypes, I.getModule()) + : Intrinsic::getName(IID).str(); + } else { + assert(VTy && "Return type must be a vector"); + auto *ScalarTy = VTy->getScalarType(); + LibFunc Func; + if (!TLI.getLibFunc(I.getOpcode(), ScalarTy, Func)) return false; + ScalarName = TLI.getName(Func); + ScalarArgTypes = {ScalarTy, ScalarTy}; } - // Try to reconstruct the name for the scalar version of this intrinsic using - // the intrinsic ID and the argument types converted to scalar above. - std::string ScalarName = - (Intrinsic::isOverloaded(IntrinsicID) - ? Intrinsic::getName(IntrinsicID, ScalarArgTypes, - CallToReplace.getModule()) - : Intrinsic::getName(IntrinsicID).str()); - // Try to find the mapping for the scalar version of this intrinsic and the // exact vector width of the call operands in the TargetLibraryInfo. First, // check with a non-masked variant, and if that fails try with a masked one. const VecDesc *VD = - TLI.getVectorMappingInfo(ScalarName, VF, /*Masked*/ false); - if (!VD && !(VD = TLI.getVectorMappingInfo(ScalarName, VF, /*Masked*/ true))) + TLI.getVectorMappingInfo(ScalarName, EC, /*Masked*/ false); + if (!VD && !(VD = TLI.getVectorMappingInfo(ScalarName, EC, /*Masked*/ true))) return false; LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": Found TLI mapping from: `" << ScalarName - << "` and vector width " << VF << " to: `" + << "` and vector width " << EC << " to: `" << VD->getVectorFnName() << "`.\n"); // Replace the call to the intrinsic with a call to the vector library // function. - Type *ScalarRetTy = CallToReplace.getType()->getScalarType(); + Type *ScalarRetTy = I.getType()->getScalarType(); FunctionType *ScalarFTy = FunctionType::get(ScalarRetTy, ScalarArgTypes, /*isVarArg*/ false); const std::string MangledName = VD->getVectorFunctionABIVariantString(); @@ -162,27 +172,37 @@ static bool replaceWithCallToVeclib(const TargetLibraryInfo &TLI, if (!VectorFTy) return false; - Function *FuncToReplace = CallToReplace.getCalledFunction(); - Function *TLIFunc = getTLIFunction(CallToReplace.getModule(), VectorFTy, + Function *TLIFunc = getTLIFunction(I.getModule(), VectorFTy, VD->getVectorFnName(), FuncToReplace); - replaceWithTLIFunction(CallToReplace, *OptInfo, TLIFunc); - - LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": Replaced call to `" - << FuncToReplace->getName() << "` with call to `" - << TLIFunc->getName() << "`.\n"); + replaceWithTLIFunction(I, *OptInfo, TLIFunc); + LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": Replaced call to `" << ScalarName + << "` with call to `" << TLIFunc->getName() << "`.\n"); ++NumCallsReplaced; return true; } +/// Supported instruction \p I must be a vectorized frem or a call to an +/// intrinsic that returns either void or a vector. +static bool isSupportedInstruction(Instruction *I) { + Type *Ty = I->getType(); + if (auto *CI = dyn_cast(I)) + return (Ty->isVectorTy() || Ty->isVoidTy()) && CI->getCalledFunction() && + CI->getCalledFunction()->getIntrinsicID() != + Intrinsic::not_intrinsic; + if (I->getOpcode() == Instruction::FRem && Ty->isVectorTy()) + return true; + return false; +} + static bool runImpl(const TargetLibraryInfo &TLI, Function &F) { bool Changed = false; - SmallVector ReplacedCalls; + SmallVector ReplacedCalls; for (auto &I : instructions(F)) { - if (auto *CI = dyn_cast(&I)) { - if (replaceWithCallToVeclib(TLI, *CI)) { - ReplacedCalls.push_back(CI); - Changed = true; - } + if (!isSupportedInstruction(&I)) + continue; + if (replaceWithCallToVeclib(TLI, I)) { + ReplacedCalls.push_back(&I); + Changed = true; } } // Erase the calls to the intrinsics that have been replaced diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll b/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll similarity index 91% rename from llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll rename to llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll index d41870ec6e79..4480a90a2728 100644 --- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll +++ b/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll @@ -15,7 +15,7 @@ declare @llvm.cos.nxv2f64() declare @llvm.cos.nxv4f32() ;. -; CHECK: @llvm.compiler.used = appending global [32 x ptr] [ptr @armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_svcos_f64_x, ptr @armpl_svcos_f32_x, ptr @armpl_vsinq_f64, ptr @armpl_vsinq_f32, ptr @armpl_svsin_f64_x, ptr @armpl_svsin_f32_x, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr @armpl_svexp_f64_x, ptr @armpl_svexp_f32_x, ptr @armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_svexp2_f64_x, ptr @armpl_svexp2_f32_x, ptr @armpl_vexp10q_f64, ptr @armpl_vexp10q_f32, ptr @armpl_svexp10_f64_x, ptr @armpl_svexp10_f32_x, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr @armpl_svlog_f64_x, ptr @armpl_svlog_f32_x, ptr @armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_svlog2_f64_x, ptr @armpl_svlog2_f32_x, ptr @armpl_vlog10q_f64, ptr @armpl_vlog10q_f32, ptr @armpl_svlog10_f64_x, ptr @armpl_svlog10_f32_x], section "llvm.metadata" +; CHECK: @llvm.compiler.used = appending global [36 x ptr] [ptr @armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_svcos_f64_x, ptr @armpl_svcos_f32_x, ptr @armpl_vsinq_f64, ptr @armpl_vsinq_f32, ptr @armpl_svsin_f64_x, ptr @armpl_svsin_f32_x, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr @armpl_svexp_f64_x, ptr @armpl_svexp_f32_x, ptr @armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_svexp2_f64_x, ptr @armpl_svexp2_f32_x, ptr @armpl_vexp10q_f64, ptr @armpl_vexp10q_f32, ptr @armpl_svexp10_f64_x, ptr @armpl_svexp10_f32_x, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr @armpl_svlog_f64_x, ptr @armpl_svlog_f32_x, ptr @armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_svlog2_f64_x, ptr @armpl_svlog2_f32_x, ptr @armpl_vlog10q_f64, ptr @armpl_vlog10q_f32, ptr @armpl_svlog10_f64_x, ptr @armpl_svlog10_f32_x, ptr @armpl_vfmodq_f64, ptr @armpl_vfmodq_f32, ptr @armpl_svfmod_f64_x, ptr @armpl_svfmod_f32_x], section "llvm.metadata" ;. define <2 x double> @llvm_cos_f64(<2 x double> %in) { ; CHECK-LABEL: define <2 x double> @llvm_cos_f64 @@ -424,6 +424,46 @@ define @llvm_pow_vscale_f32( %in, %1 } +define <2 x double> @frem_f64(<2 x double> %in) { +; CHECK-LABEL: define <2 x double> @frem_f64 +; CHECK-SAME: (<2 x double> [[IN:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @armpl_vfmodq_f64(<2 x double> [[IN]], <2 x double> [[IN]]) +; CHECK-NEXT: ret <2 x double> [[TMP1]] +; + %1= frem <2 x double> %in, %in + ret <2 x double> %1 +} + +define <4 x float> @frem_f32(<4 x float> %in) { +; CHECK-LABEL: define <4 x float> @frem_f32 +; CHECK-SAME: (<4 x float> [[IN:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @armpl_vfmodq_f32(<4 x float> [[IN]], <4 x float> [[IN]]) +; CHECK-NEXT: ret <4 x float> [[TMP1]] +; + %1= frem <4 x float> %in, %in + ret <4 x float> %1 +} + +define @frem_vscale_f64( %in) #0 { +; CHECK-LABEL: define @frem_vscale_f64 +; CHECK-SAME: ( [[IN:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[TMP1:%.*]] = call @armpl_svfmod_f64_x( [[IN]], [[IN]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; CHECK-NEXT: ret [[TMP1]] +; + %1= frem %in, %in + ret %1 +} + +define @frem_vscale_f32( %in) #0 { +; CHECK-LABEL: define @frem_vscale_f32 +; CHECK-SAME: ( [[IN:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[TMP1:%.*]] = call @armpl_svfmod_f32_x( [[IN]], [[IN]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; CHECK-NEXT: ret [[TMP1]] +; + %1= frem %in, %in + ret %1 +} + attributes #0 = { "target-features"="+sve" } ;. ; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll b/llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll similarity index 95% rename from llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll rename to llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll index c2ff6014bc69..590dd9effac0 100644 --- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll +++ b/llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll @@ -4,7 +4,7 @@ target triple = "aarch64-unknown-linux-gnu" ;. -; CHECK: @llvm.compiler.used = appending global [16 x ptr] [ptr @_ZGVsMxv_cos, ptr @_ZGVsMxv_cosf, ptr @_ZGVsMxv_exp, ptr @_ZGVsMxv_expf, ptr @_ZGVsMxv_exp2, ptr @_ZGVsMxv_exp2f, ptr @_ZGVsMxv_exp10, ptr @_ZGVsMxv_exp10f, ptr @_ZGVsMxv_log, ptr @_ZGVsMxv_logf, ptr @_ZGVsMxv_log10, ptr @_ZGVsMxv_log10f, ptr @_ZGVsMxv_log2, ptr @_ZGVsMxv_log2f, ptr @_ZGVsMxv_sin, ptr @_ZGVsMxv_sinf], section "llvm.metadata" +; CHECK: @llvm.compiler.used = appending global [18 x ptr] [ptr @_ZGVsMxv_cos, ptr @_ZGVsMxv_cosf, ptr @_ZGVsMxv_exp, ptr @_ZGVsMxv_expf, ptr @_ZGVsMxv_exp2, ptr @_ZGVsMxv_exp2f, ptr @_ZGVsMxv_exp10, ptr @_ZGVsMxv_exp10f, ptr @_ZGVsMxv_log, ptr @_ZGVsMxv_logf, ptr @_ZGVsMxv_log10, ptr @_ZGVsMxv_log10f, ptr @_ZGVsMxv_log2, ptr @_ZGVsMxv_log2f, ptr @_ZGVsMxv_sin, ptr @_ZGVsMxv_sinf, ptr @_ZGVsMxvv_fmod, ptr @_ZGVsMxvv_fmodf], section "llvm.metadata" ;. define @llvm_ceil_vscale_f64( %in) { ; CHECK-LABEL: @llvm_ceil_vscale_f64( @@ -384,6 +384,24 @@ define @llvm_trunc_vscale_f32( %in) { ret %1 } +define @frem_f64( %in) { +; CHECK-LABEL: @frem_f64( +; CHECK-NEXT: [[TMP1:%.*]] = call @_ZGVsMxvv_fmod( [[IN:%.*]], [[IN]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; CHECK-NEXT: ret [[TMP1]] +; + %1= frem %in, %in + ret %1 +} + +define @frem_f32( %in) { +; CHECK-LABEL: @frem_f32( +; CHECK-NEXT: [[TMP1:%.*]] = call @_ZGVsMxvv_fmodf( [[IN:%.*]], [[IN]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; CHECK-NEXT: ret [[TMP1]] +; + %1= frem %in, %in + ret %1 +} + declare @llvm.ceil.nxv2f64() declare @llvm.ceil.nxv4f32() declare @llvm.copysign.nxv2f64(, ) diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll b/llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll similarity index 95% rename from llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll rename to llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll index be247de36805..865a46009b20 100644 --- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll +++ b/llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll @@ -4,7 +4,7 @@ target triple = "aarch64-unknown-linux-gnu" ;. -; CHECK: @llvm.compiler.used = appending global [16 x ptr] [ptr @_ZGVnN2v_cos, ptr @_ZGVnN4v_cosf, ptr @_ZGVnN2v_exp, ptr @_ZGVnN4v_expf, ptr @_ZGVnN2v_exp2, ptr @_ZGVnN4v_exp2f, ptr @_ZGVnN2v_exp10, ptr @_ZGVnN4v_exp10f, ptr @_ZGVnN2v_log, ptr @_ZGVnN4v_logf, ptr @_ZGVnN2v_log10, ptr @_ZGVnN4v_log10f, ptr @_ZGVnN2v_log2, ptr @_ZGVnN4v_log2f, ptr @_ZGVnN2v_sin, ptr @_ZGVnN4v_sinf], section "llvm.metadata" +; CHECK: @llvm.compiler.used = appending global [18 x ptr] [ptr @_ZGVnN2v_cos, ptr @_ZGVnN4v_cosf, ptr @_ZGVnN2v_exp, ptr @_ZGVnN4v_expf, ptr @_ZGVnN2v_exp2, ptr @_ZGVnN4v_exp2f, ptr @_ZGVnN2v_exp10, ptr @_ZGVnN4v_exp10f, ptr @_ZGVnN2v_log, ptr @_ZGVnN4v_logf, ptr @_ZGVnN2v_log10, ptr @_ZGVnN4v_log10f, ptr @_ZGVnN2v_log2, ptr @_ZGVnN4v_log2f, ptr @_ZGVnN2v_sin, ptr @_ZGVnN4v_sinf, ptr @_ZGVnN2vv_fmod, ptr @_ZGVnN4vv_fmodf], section "llvm.metadata" ;. define <2 x double> @llvm_ceil_f64(<2 x double> %in) { ; CHECK-LABEL: @llvm_ceil_f64( @@ -384,6 +384,24 @@ define <4 x float> @llvm_trunc_f32(<4 x float> %in) { ret <4 x float> %1 } +define <2 x double> @frem_f64(<2 x double> %in) { +; CHECK-LABEL: @frem_f64( +; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @_ZGVnN2vv_fmod(<2 x double> [[IN:%.*]], <2 x double> [[IN]]) +; CHECK-NEXT: ret <2 x double> [[TMP1]] +; + %1= frem <2 x double> %in, %in + ret <2 x double> %1 +} + +define <4 x float> @frem_f32(<4 x float> %in) { +; CHECK-LABEL: @frem_f32( +; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @_ZGVnN4vv_fmodf(<4 x float> [[IN:%.*]], <4 x float> [[IN]]) +; CHECK-NEXT: ret <4 x float> [[TMP1]] +; + %1= frem <4 x float> %in, %in + ret <4 x float> %1 +} + declare <2 x double> @llvm.ceil.v2f64(<2 x double>) declare <4 x float> @llvm.ceil.v4f32(<4 x float>) declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) -- GitLab From acbb491ab23fd04e201b58195f78e04c5a647d47 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 8 Jan 2024 08:55:39 +0000 Subject: [PATCH 035/652] [libcxx] Require qemu-system-arm for armv7m builder (#77067) And add a check in the python script that the binary given to `--qemu` actually exists. Otherwise you get a generic Python error: ``` # .---command stderr------------ # | Traceback (most recent call last): # | File "/home/david.spickett/modules-llvm-project/libcxx/utils/qemu_baremetal.py", line 70, in # | exit(main()) # | File "/home/david.spickett/modules-llvm-project/libcxx/utils/qemu_baremetal.py", line 66, in main # | os.execvp(qemu_commandline[0], qemu_commandline) # | File "/usr/lib/python3.8/os.py", line 568, in execvp # | _execvpe(file, args) # | File "/usr/lib/python3.8/os.py", line 610, in _execvpe # | raise last_exc # | File "/usr/lib/python3.8/os.py", line 601, in _execvpe # | exec_func(fullname, *argrest) # | FileNotFoundError: [Errno 2] No such file or directory # `----------------------------- # error: command failed with exit status: 1 ``` When it tries to run the entire command later. For the builder, it's only ever going to use qemu-system-arm so error at config time if it's not there. --- libcxx/cmake/caches/Armv7M-picolibc.cmake | 2 +- libcxx/utils/qemu_baremetal.py | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/libcxx/cmake/caches/Armv7M-picolibc.cmake b/libcxx/cmake/caches/Armv7M-picolibc.cmake index 91cc32fd376e..3ab80b960ed4 100644 --- a/libcxx/cmake/caches/Armv7M-picolibc.cmake +++ b/libcxx/cmake/caches/Armv7M-picolibc.cmake @@ -39,4 +39,4 @@ set(LIBUNWIND_ENABLE_THREADS OFF CACHE BOOL "") set(LIBUNWIND_IS_BAREMETAL ON CACHE BOOL "") set(LIBUNWIND_REMEMBER_HEAP_ALLOC ON CACHE BOOL "") set(LIBUNWIND_USE_COMPILER_RT ON CACHE BOOL "") -find_program(QEMU_SYSTEM_ARM qemu-system-arm) +find_program(QEMU_SYSTEM_ARM qemu-system-arm REQUIRED) diff --git a/libcxx/utils/qemu_baremetal.py b/libcxx/utils/qemu_baremetal.py index aaf5b8448906..126031bbb19c 100755 --- a/libcxx/utils/qemu_baremetal.py +++ b/libcxx/utils/qemu_baremetal.py @@ -16,6 +16,7 @@ output (if the underlying baremetal enviroment supports QEMU semihosting). import argparse import os import sys +import shutil def main(): @@ -32,8 +33,13 @@ def main(): parser.add_argument("test_binary") parser.add_argument("test_args", nargs=argparse.ZERO_OR_MORE, default=[]) args = parser.parse_args() + + if not shutil.which(args.qemu): + sys.exit(f"Failed to find QEMU binary from --qemu value: '{args.qemu}'") + if not os.path.exists(args.test_binary): sys.exit(f"Expected argument to be a test executable: '{args.test_binary}'") + qemu_commandline = [ args.qemu, "-chardev", -- GitLab From ed1632b72ec029256f3af60822dad54970a79577 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 8 Jan 2024 10:00:23 +0100 Subject: [PATCH 036/652] [ConstraintElim] Support signed induction variables (#77103) When adding information for induction variables, add both unsigned and signed constraints, with corresponding signed and unsigned preconditions. I believe the logic here is equally valid for signed/unsigned, we just need to add preconditions of the same type. --- .../Scalar/ConstraintElimination.cpp | 36 ++++++++++++++----- .../monotonic-int-phis-signed.ll | 18 ++++------ 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp index 5889dab16265..6fec54ac7922 100644 --- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp +++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp @@ -933,15 +933,20 @@ void State::addInfoForInductions(BasicBlock &BB) { } DomTreeNode *DTN = DT.getNode(InLoopSucc); - auto Inc = SE.getMonotonicPredicateType(AR, CmpInst::ICMP_UGT); - bool MonotonicallyIncreasing = - Inc && *Inc == ScalarEvolution::MonotonicallyIncreasing; - if (MonotonicallyIncreasing) { - // SCEV guarantees that AR does not wrap, so PN >= StartValue can be added - // unconditionally. + auto IncUnsigned = SE.getMonotonicPredicateType(AR, CmpInst::ICMP_UGT); + auto IncSigned = SE.getMonotonicPredicateType(AR, CmpInst::ICMP_SGT); + bool MonotonicallyIncreasingUnsigned = + IncUnsigned && *IncUnsigned == ScalarEvolution::MonotonicallyIncreasing; + bool MonotonicallyIncreasingSigned = + IncSigned && *IncSigned == ScalarEvolution::MonotonicallyIncreasing; + // If SCEV guarantees that AR does not wrap, PN >= StartValue can be added + // unconditionally. + if (MonotonicallyIncreasingUnsigned) WorkList.push_back( FactOrCheck::getConditionFact(DTN, CmpInst::ICMP_UGE, PN, StartValue)); - } + if (MonotonicallyIncreasingSigned) + WorkList.push_back( + FactOrCheck::getConditionFact(DTN, CmpInst::ICMP_SGE, PN, StartValue)); APInt StepOffset; if (auto *C = dyn_cast(AR->getStepRecurrence(SE))) @@ -965,11 +970,17 @@ void State::addInfoForInductions(BasicBlock &BB) { WorkList.push_back(FactOrCheck::getConditionFact( DTN, CmpInst::ICMP_UGE, StartValue, PN, ConditionTy(CmpInst::ICMP_ULE, B, StartValue))); + WorkList.push_back(FactOrCheck::getConditionFact( + DTN, CmpInst::ICMP_SGE, StartValue, PN, + ConditionTy(CmpInst::ICMP_SLE, B, StartValue))); // Add PN > B conditional on B <= StartValue which guarantees that the loop // exits when reaching B with a step of -1. WorkList.push_back(FactOrCheck::getConditionFact( DTN, CmpInst::ICMP_UGT, PN, B, ConditionTy(CmpInst::ICMP_ULE, B, StartValue))); + WorkList.push_back(FactOrCheck::getConditionFact( + DTN, CmpInst::ICMP_SGT, PN, B, + ConditionTy(CmpInst::ICMP_SLE, B, StartValue))); return; } @@ -990,14 +1001,21 @@ void State::addInfoForInductions(BasicBlock &BB) { // AR may wrap. Add PN >= StartValue conditional on StartValue <= B which // guarantees that the loop exits before wrapping in combination with the // restrictions on B and the step above. - if (!MonotonicallyIncreasing) { + if (!MonotonicallyIncreasingUnsigned) WorkList.push_back(FactOrCheck::getConditionFact( DTN, CmpInst::ICMP_UGE, PN, StartValue, ConditionTy(CmpInst::ICMP_ULE, StartValue, B))); - } + if (!MonotonicallyIncreasingSigned) + WorkList.push_back(FactOrCheck::getConditionFact( + DTN, CmpInst::ICMP_SGE, PN, StartValue, + ConditionTy(CmpInst::ICMP_SLE, StartValue, B))); + WorkList.push_back(FactOrCheck::getConditionFact( DTN, CmpInst::ICMP_ULT, PN, B, ConditionTy(CmpInst::ICMP_ULE, StartValue, B))); + WorkList.push_back(FactOrCheck::getConditionFact( + DTN, CmpInst::ICMP_SLT, PN, B, + ConditionTy(CmpInst::ICMP_SLE, StartValue, B))); } void State::addInfoFor(BasicBlock &BB) { diff --git a/llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll b/llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll index 1e95fab5c10c..7273469fc59e 100644 --- a/llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll +++ b/llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll @@ -15,10 +15,8 @@ define void @signed_iv_step_1(i64 %end) { ; CHECK-NEXT: [[CMP_I_NOT:%.*]] = icmp eq i64 [[IV]], [[END]] ; CHECK-NEXT: br i1 [[CMP_I_NOT]], label [[EXIT]], label [[LOOP_LATCH]] ; CHECK: loop.latch: -; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i64 [[IV]], [[END]] -; CHECK-NEXT: call void @use(i1 [[CMP2]]) -; CHECK-NEXT: [[CMP3:%.*]] = icmp sge i64 [[IV]], -10 -; CHECK-NEXT: call void @use(i1 [[CMP3]]) +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: call void @use(i1 true) ; CHECK-NEXT: br label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret void @@ -141,10 +139,8 @@ define void @signed_iv_step_4_start_4(i64 %count) { ; CHECK-NEXT: [[CMP_I_NOT:%.*]] = icmp eq i64 [[IV]], [[END]] ; CHECK-NEXT: br i1 [[CMP_I_NOT]], label [[EXIT]], label [[LOOP_LATCH]] ; CHECK: loop.latch: -; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i64 [[IV]], [[END]] -; CHECK-NEXT: call void @use(i1 [[CMP2]]) -; CHECK-NEXT: [[CMP3:%.*]] = icmp sge i64 [[IV]], 4 -; CHECK-NEXT: call void @use(i1 [[CMP3]]) +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: call void @use(i1 true) ; CHECK-NEXT: br label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret void @@ -226,10 +222,8 @@ define void @signed_iv_step_minus1(i64 %end) { ; CHECK-NEXT: [[CMP_I_NOT:%.*]] = icmp eq i64 [[IV]], [[END]] ; CHECK-NEXT: br i1 [[CMP_I_NOT]], label [[EXIT]], label [[LOOP_LATCH]] ; CHECK: loop.latch: -; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[IV]], [[END]] -; CHECK-NEXT: call void @use(i1 [[CMP2]]) -; CHECK-NEXT: [[CMP3:%.*]] = icmp sle i64 [[IV]], 10 -; CHECK-NEXT: call void @use(i1 [[CMP3]]) +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: call void @use(i1 true) ; CHECK-NEXT: br label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: ret void -- GitLab From 2c213c45046b78eac48809b013e7a80099607ebb Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 8 Jan 2024 15:59:20 +0700 Subject: [PATCH 037/652] [Clang] Fix reference to sve in rvv driver test comment. NFC --- clang/test/Driver/riscv-rvv-vector-bits.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/Driver/riscv-rvv-vector-bits.c b/clang/test/Driver/riscv-rvv-vector-bits.c index e92b66c972da..24af5f0c73c6 100644 --- a/clang/test/Driver/riscv-rvv-vector-bits.c +++ b/clang/test/Driver/riscv-rvv-vector-bits.c @@ -44,7 +44,7 @@ // CHECK-BAD-VALUE-ERROR: error: unsupported argument '{{.*}}' to option '-mrvv-vector-bits=' -// Error if using attribute without -msve-vector-bits= or if using -msve-vector-bits=+ syntax +// Error if using attribute without -mrvv-vector-bits= or if using -mrvv-vector-bits=+ syntax // ----------------------------------------------------------------------------- // RUN: not %clang -c %s -o /dev/null -target riscv64-linux-gnu \ // RUN: -march=rv64gc_zve64x 2>&1 | FileCheck --check-prefix=CHECK-NO-FLAG-ERROR %s -- GitLab From d02c7931d1be794a230943e300fec4172032e6a8 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 8 Jan 2024 10:21:25 +0100 Subject: [PATCH 038/652] [MSSA] Don't require clone creation to succeed (#76819) Sometimes, we create a MemoryAccess for an instruction, which is later simplified (e.g. via devirtualization) such that the new instruction has no memory effects anymore. If we later clone the instruction (e.g. during unswitching), then MSSA will not create a MemoryAccess for the new instruction, triggering an assert. Disable the assertion (by passing CreationMustSucceed=false) and adjust getDefiningAccessForClone() to work correctly in that case. This PR implements the alternative suggestion by alinas from https://github.com/llvm/llvm-project/pull/76142. --- llvm/lib/Analysis/MemorySSAUpdater.cpp | 17 +-- .../memssa-readnone-access.ll | 117 ++++++++++++++++++ 2 files changed, 121 insertions(+), 13 deletions(-) create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll diff --git a/llvm/lib/Analysis/MemorySSAUpdater.cpp b/llvm/lib/Analysis/MemorySSAUpdater.cpp index 9ad60f774e9f..e87ae7d71fff 100644 --- a/llvm/lib/Analysis/MemorySSAUpdater.cpp +++ b/llvm/lib/Analysis/MemorySSAUpdater.cpp @@ -568,7 +568,6 @@ static MemoryAccess *onlySingleValue(MemoryPhi *MP) { static MemoryAccess *getNewDefiningAccessForClone(MemoryAccess *MA, const ValueToValueMapTy &VMap, PhiToDefMap &MPhiMap, - bool CloneWasSimplified, MemorySSA *MSSA) { MemoryAccess *InsnDefining = MA; if (MemoryDef *DefMUD = dyn_cast(InsnDefining)) { @@ -578,18 +577,10 @@ static MemoryAccess *getNewDefiningAccessForClone(MemoryAccess *MA, if (Instruction *NewDefMUDI = cast_or_null(VMap.lookup(DefMUDI))) { InsnDefining = MSSA->getMemoryAccess(NewDefMUDI); - if (!CloneWasSimplified) - assert(InsnDefining && "Defining instruction cannot be nullptr."); - else if (!InsnDefining || isa(InsnDefining)) { + if (!InsnDefining || isa(InsnDefining)) { // The clone was simplified, it's no longer a MemoryDef, look up. - auto DefIt = DefMUD->getDefsIterator(); - // Since simplified clones only occur in single block cloning, a - // previous definition must exist, otherwise NewDefMUDI would not - // have been found in VMap. - assert(DefIt != MSSA->getBlockDefs(DefMUD->getBlock())->begin() && - "Previous def must exist"); InsnDefining = getNewDefiningAccessForClone( - &*(--DefIt), VMap, MPhiMap, CloneWasSimplified, MSSA); + DefMUD->getDefiningAccess(), VMap, MPhiMap, MSSA); } } } @@ -624,9 +615,9 @@ void MemorySSAUpdater::cloneUsesAndDefs(BasicBlock *BB, BasicBlock *NewBB, MemoryAccess *NewUseOrDef = MSSA->createDefinedAccess( NewInsn, getNewDefiningAccessForClone(MUD->getDefiningAccess(), VMap, - MPhiMap, CloneWasSimplified, MSSA), + MPhiMap, MSSA), /*Template=*/CloneWasSimplified ? nullptr : MUD, - /*CreationMustSucceed=*/CloneWasSimplified ? false : true); + /*CreationMustSucceed=*/false); if (NewUseOrDef) MSSA->insertIntoListsForBlock(NewUseOrDef, NewBB, MemorySSA::End); } diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll b/llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll new file mode 100644 index 000000000000..2aaf777683e1 --- /dev/null +++ b/llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll @@ -0,0 +1,117 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -passes="loop-mssa(loop-instsimplify,simple-loop-unswitch)" < %s | FileCheck %s + +@vtable = constant ptr @foo + +declare void @foo() memory(none) +declare void @bar() + +; The call becomes known readnone after simplification, but still have a +; MemoryAccess. Make sure this does not lead to an assertion failure. +define void @test(i1 %c) { +; CHECK-LABEL: define void @test( +; CHECK-SAME: i1 [[C:%.*]]) { +; CHECK-NEXT: [[C_FR:%.*]] = freeze i1 [[C]] +; CHECK-NEXT: br i1 [[C_FR]], label [[DOTSPLIT_US:%.*]], label [[DOTSPLIT:%.*]] +; CHECK: .split.us: +; CHECK-NEXT: br label [[LOOP_US:%.*]] +; CHECK: loop.us: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: br label [[EXIT_SPLIT_US:%.*]] +; CHECK: exit.split.us: +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: .split: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: br label [[LOOP]] +; CHECK: exit: +; CHECK-NEXT: ret void +; + br label %loop + +loop: + %fn = load ptr, ptr @vtable, align 8 + call void %fn() + br i1 %c, label %exit, label %loop + +exit: + ret void +} + +; Variant with another access after the call. +define void @test2(i1 %c, ptr %p) { +; CHECK-LABEL: define void @test2( +; CHECK-SAME: i1 [[C:%.*]], ptr [[P:%.*]]) { +; CHECK-NEXT: [[C_FR:%.*]] = freeze i1 [[C]] +; CHECK-NEXT: br i1 [[C_FR]], label [[DOTSPLIT_US:%.*]], label [[DOTSPLIT:%.*]] +; CHECK: .split.us: +; CHECK-NEXT: br label [[LOOP_US:%.*]] +; CHECK: loop.us: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: br label [[EXIT_SPLIT_US:%.*]] +; CHECK: exit.split.us: +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: .split: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: br label [[LOOP]] +; CHECK: exit: +; CHECK-NEXT: ret void +; + br label %loop + +loop: + %fn = load ptr, ptr @vtable, align 8 + call void %fn() + call void @bar() + br i1 %c, label %exit, label %loop + +exit: + ret void +} + +; Variant with another access after the call and no access before the call. +define void @test3(i1 %c, ptr %p) { +; CHECK-LABEL: define void @test3( +; CHECK-SAME: i1 [[C:%.*]], ptr [[P:%.*]]) { +; CHECK-NEXT: [[C_FR:%.*]] = freeze i1 [[C]] +; CHECK-NEXT: br i1 [[C_FR]], label [[DOTSPLIT_US:%.*]], label [[DOTSPLIT:%.*]] +; CHECK: .split.us: +; CHECK-NEXT: br label [[LOOP_US:%.*]] +; CHECK: loop.us: +; CHECK-NEXT: br label [[SPLIT_US:%.*]] +; CHECK: split.us: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: br label [[EXIT_SPLIT_US:%.*]] +; CHECK: exit.split.us: +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: .split: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: br label [[SPLIT:%.*]] +; CHECK: split: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: br label [[LOOP]] +; CHECK: exit: +; CHECK-NEXT: ret void +; + br label %loop + +loop: + %fn = load ptr, ptr @vtable, align 8 + br label %split + +split: + call void %fn() + call void @bar() + br i1 %c, label %exit, label %loop + +exit: + ret void +} -- GitLab From 442f67c8702a792a135d61765909b732827d6bf2 Mon Sep 17 00:00:00 2001 From: Lu Haocong Date: Mon, 8 Jan 2024 16:52:58 +0800 Subject: [PATCH 039/652] [Sema][test] Split format attribute test cases for _Float16 Fixes https://github.com/llvm/llvm-project/pull/74439#issuecomment-1880528376 --- clang/test/Sema/attr-format-Float16.c | 16 ++++++++++++++ clang/test/Sema/attr-format.c | 7 ------ clang/test/SemaCXX/attr-format-Float16.cpp | 24 +++++++++++++++++++++ clang/test/SemaCXX/attr-format.cpp | 1 - clang/test/SemaCXX/format-strings-scanf.cpp | 16 ++++++-------- 5 files changed, 46 insertions(+), 18 deletions(-) create mode 100644 clang/test/Sema/attr-format-Float16.c create mode 100644 clang/test/SemaCXX/attr-format-Float16.cpp diff --git a/clang/test/Sema/attr-format-Float16.c b/clang/test/Sema/attr-format-Float16.c new file mode 100644 index 000000000000..6c3dfe14cec3 --- /dev/null +++ b/clang/test/Sema/attr-format-Float16.c @@ -0,0 +1,16 @@ +// RUN: %clang_cc1 -fsyntax-only -verify -triple i686-linux-pc -target-feature +sse2 %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64-linux-pc %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple spir-unknown-unknown %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple armv7a-linux-gnu %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple aarch64-linux-gnu %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple riscv32 %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple riscv64 %s + +void a(const char *a, ...) __attribute__((format(printf, 1, 2))); // no-error + +void b(char *a, _Float16 b) __attribute__((format(printf, 1, 2))); // expected-warning {{GCC requires a function with the 'format' attribute to be variadic}} + +void call_no_default_promotion(void) { + a("%f", (_Float16)1.0); // expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} + b("%f", (_Float16)1.0); // expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} +} diff --git a/clang/test/Sema/attr-format.c b/clang/test/Sema/attr-format.c index bdfd8425c4e9..1f4c864d4f78 100644 --- a/clang/test/Sema/attr-format.c +++ b/clang/test/Sema/attr-format.c @@ -16,8 +16,6 @@ typedef const char *xpto; void j(xpto c, va_list list) __attribute__((format(printf, 1, 0))); // no-error void k(xpto c) __attribute__((format(printf, 1, 0))); // no-error -void l(char *a, _Float16 b) __attribute__((format(printf, 1, 2))); // expected-warning {{GCC requires a function with the 'format' attribute to be variadic}} - void y(char *str) __attribute__((format(strftime, 1, 0))); // no-error void z(char *str, int c, ...) __attribute__((format(strftime, 1, 2))); // expected-error {{strftime format attribute requires 3rd parameter to be 0}} @@ -95,11 +93,6 @@ void call_nonvariadic(void) { d3("%s", 123); // expected-warning{{format specifies type 'char *' but the argument has type 'int'}} } -void call_no_default_promotion(void) { - a("%f", (_Float16)1.0); // expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} - l("%f", (_Float16)1.0); // expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} -} - __attribute__((format(printf, 1, 2))) void forward_fixed(const char *fmt, _Bool b, char i, short j, int k, float l, double m) { // expected-warning{{GCC requires a function with the 'format' attribute to be variadic}} forward_fixed(fmt, b, i, j, k, l, m); diff --git a/clang/test/SemaCXX/attr-format-Float16.cpp b/clang/test/SemaCXX/attr-format-Float16.cpp new file mode 100644 index 000000000000..c61611d6b6a0 --- /dev/null +++ b/clang/test/SemaCXX/attr-format-Float16.cpp @@ -0,0 +1,24 @@ +// RUN: %clang_cc1 -fsyntax-only -verify -triple i686-linux-pc -target-feature +sse2 %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64-linux-pc %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple spir-unknown-unknown %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple armv7a-linux-gnu %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple aarch64-linux-gnu %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple riscv32 %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple riscv64 %s + +template +__attribute__((format(printf, 1, 2))) +void format(const char *fmt, Args &&...args); // expected-warning{{GCC requires a function with the 'format' attribute to be variadic}} + +template +__attribute__((format(scanf, 1, 2))) +int scan(const char *fmt, Args &&...args); // expected-warning{{GCC requires a function with the 'format' attribute to be variadic}} + +void do_format() { + format("%f", (_Float16)123.f); // expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} + + _Float16 Float16; + scan("%f", &Float16); // expected-warning{{format specifies type 'float *' but the argument has type '_Float16 *'}} + scan("%lf", &Float16); // expected-warning{{format specifies type 'double *' but the argument has type '_Float16 *'}} + scan("%Lf", &Float16); // expected-warning{{format specifies type 'long double *' but the argument has type '_Float16 *'}} +} diff --git a/clang/test/SemaCXX/attr-format.cpp b/clang/test/SemaCXX/attr-format.cpp index 4509c3a95e8e..adc05fc46776 100644 --- a/clang/test/SemaCXX/attr-format.cpp +++ b/clang/test/SemaCXX/attr-format.cpp @@ -81,7 +81,6 @@ void do_format() { format("%c %c %hhd %hd %d\n", (char)'a', 'a', 'a', (short)123, (int)123); format("%f %f %f\n", (__fp16)123.f, 123.f, 123.); - format("%f", (_Float16)123.f);// expected-warning{{format specifies type 'double' but the argument has type '_Float16'}} format("%Lf", (__fp16)123.f); // expected-warning{{format specifies type 'long double' but the argument has type '__fp16'}} format("%Lf", 123.f); // expected-warning{{format specifies type 'long double' but the argument has type 'float'}} format("%hhi %hhu %hi %hu %i %u", b, b, b, b, b, b); diff --git a/clang/test/SemaCXX/format-strings-scanf.cpp b/clang/test/SemaCXX/format-strings-scanf.cpp index 406c2069e28c..25fe5346791a 100644 --- a/clang/test/SemaCXX/format-strings-scanf.cpp +++ b/clang/test/SemaCXX/format-strings-scanf.cpp @@ -22,7 +22,6 @@ union bag { unsigned long long ull; signed long long sll; __fp16 f16; - _Float16 Float16; float ff; double fd; long double fl; @@ -52,21 +51,18 @@ void test(void) { // expected-warning@+1{{format specifies type 'int *' but the argument has type 'short *'}} scan("%hhi %i %li", &b.ss, &b.ss, &b.ss); - // expected-warning@+4{{format specifies type 'float *' but the argument has type '__fp16 *'}} - // expected-warning@+3{{format specifies type 'float *' but the argument has type '_Float16 *'}} + // expected-warning@+3{{format specifies type 'float *' but the argument has type '__fp16 *'}} // expected-warning@+2{{format specifies type 'float *' but the argument has type 'double *'}} // expected-warning@+1{{format specifies type 'float *' but the argument has type 'long double *'}} - scan("%f %f %f %f", &b.f16, &b.Float16, &b.fd, &b.fl); + scan("%f %f %f", &b.f16, &b.fd, &b.fl); - // expected-warning@+4{{format specifies type 'double *' but the argument has type '__fp16 *'}} - // expected-warning@+3{{format specifies type 'double *' but the argument has type '_Float16 *'}} + // expected-warning@+3{{format specifies type 'double *' but the argument has type '__fp16 *'}} // expected-warning@+2{{format specifies type 'double *' but the argument has type 'float *'}} // expected-warning@+1{{format specifies type 'double *' but the argument has type 'long double *'}} - scan("%lf %lf %lf %lf", &b.f16, &b.Float16, &b.ff, &b.fl); + scan("%lf %lf %lf", &b.f16, &b.ff, &b.fl); - // expected-warning@+4{{format specifies type 'long double *' but the argument has type '__fp16 *'}} - // expected-warning@+3{{format specifies type 'long double *' but the argument has type '_Float16 *'}} + // expected-warning@+3{{format specifies type 'long double *' but the argument has type '__fp16 *'}} // expected-warning@+2{{format specifies type 'long double *' but the argument has type 'float *'}} // expected-warning@+1{{format specifies type 'long double *' but the argument has type 'double *'}} - scan("%Lf %Lf %Lf %Lf", &b.f16, &b.Float16, &b.ff, &b.fd); + scan("%Lf %Lf %Lf", &b.f16, &b.ff, &b.fd); } -- GitLab From 0ba868db709d2822b00f4ee9552d7fe41e5f2722 Mon Sep 17 00:00:00 2001 From: Javed Absar <106147771+javedabsar1@users.noreply.github.com> Date: Mon, 8 Jan 2024 09:37:57 +0000 Subject: [PATCH 040/652] [MLIR][Bufferizer][NFC] Simplify some codes. (#77254) NFC. clean up. --- .../Bufferization/Transforms/BufferViewFlowAnalysis.cpp | 2 +- .../Bufferization/Transforms/EmptyTensorElimination.cpp | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp b/mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp index 98a60a48763a..88ef1b639fc5 100644 --- a/mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp +++ b/mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp @@ -49,7 +49,7 @@ void BufferViewFlowAnalysis::rename(Value from, Value to) { dependencies[to] = dependencies[from]; dependencies.erase(from); - for (auto &[key, value] : dependencies) { + for (auto &[_, value] : dependencies) { if (value.contains(from)) { value.insert(to); value.erase(from); diff --git a/mlir/lib/Dialect/Bufferization/Transforms/EmptyTensorElimination.cpp b/mlir/lib/Dialect/Bufferization/Transforms/EmptyTensorElimination.cpp index 4a418a05e6ff..eba1273b36e2 100644 --- a/mlir/lib/Dialect/Bufferization/Transforms/EmptyTensorElimination.cpp +++ b/mlir/lib/Dialect/Bufferization/Transforms/EmptyTensorElimination.cpp @@ -53,10 +53,9 @@ neededValuesDominateInsertionPoint(const DominanceInfo &domInfo, static bool insertionPointDominatesUses(const DominanceInfo &domInfo, Operation *insertionPoint, Operation *emptyTensorOp) { - for (Operation *user : emptyTensorOp->getUsers()) - if (!domInfo.dominates(insertionPoint, user)) - return false; - return true; + return llvm::all_of(emptyTensorOp->getUsers(), [&](Operation *user) { + return domInfo.dominates(insertionPoint, user); + }); } /// Find a valid insertion point for a replacement of `emptyTensorOp`, assuming -- GitLab From 27f547968cce89d4706ae2b27a0c15254d1670ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?kadir=20=C3=A7etinkaya?= Date: Mon, 8 Jan 2024 11:11:02 +0100 Subject: [PATCH 041/652] [clang-format] Break after string literals with trailing line breaks (#76795) This restores a subset of functionality that was forego in d68826dfbd987377ef6771d40c1d984f09ee3b9e. Streaming multiple string literals is rare enough in practice, hence that change makes sense in general. But it seems people were incidentally relying on this for having line breaks after string literals that ended with `\n`. This patch tries to restore that behavior to prevent regressions in the upcoming LLVM release, until we can implement some configuration based approach as proposed in https://github.com/llvm/llvm-project/pull/69859. --- clang/lib/Format/TokenAnnotator.cpp | 8 ++++++++ clang/unittests/Format/FormatTest.cpp | 2 ++ clang/unittests/Format/TokenAnnotatorTest.cpp | 9 +++++++++ 3 files changed, 19 insertions(+) diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 3ac3aa3c5e3a..8b43438c72df 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -5151,6 +5151,14 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, return true; if (Left.IsUnterminatedLiteral) return true; + // FIXME: Breaking after newlines seems useful in general. Turn this into an + // option and recognize more cases like endl etc, and break independent of + // what comes after operator lessless. + if (Right.is(tok::lessless) && Right.Next && + Right.Next->is(tok::string_literal) && Left.is(tok::string_literal) && + Left.TokenText.ends_with("\\n\"")) { + return true; + } if (Right.is(TT_RequiresClause)) { switch (Style.RequiresClausePosition) { case FormatStyle::RCPS_OwnLine: diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 881993ede17c..25ef5c680af8 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -26708,6 +26708,8 @@ TEST_F(FormatTest, PPBranchesInBracedInit) { TEST_F(FormatTest, StreamOutputOperator) { verifyFormat("std::cout << \"foo\" << \"bar\" << baz;"); + verifyFormat("std::cout << \"foo\\n\"\n" + " << \"bar\";"); } TEST_F(FormatTest, BreakAdjacentStringLiterals) { diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index 2cafc0438ffb..decc0785c5cd 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -2499,6 +2499,15 @@ TEST_F(TokenAnnotatorTest, BraceKind) { EXPECT_BRACE_KIND(Tokens[6], BK_Block); } +TEST_F(TokenAnnotatorTest, StreamOperator) { + auto Tokens = annotate("\"foo\\n\" << aux << \"foo\\n\" << \"foo\";"); + ASSERT_EQ(Tokens.size(), 9u) << Tokens; + EXPECT_FALSE(Tokens[1]->MustBreakBefore); + EXPECT_FALSE(Tokens[3]->MustBreakBefore); + // Only break between string literals if the former ends with \n. + EXPECT_TRUE(Tokens[5]->MustBreakBefore); +} + } // namespace } // namespace format } // namespace clang -- GitLab From a831a21e4d8d41b044edaf61a90debb2ad756bda Mon Sep 17 00:00:00 2001 From: Mitch Phillips <31459023+hctim@users.noreply.github.com> Date: Mon, 8 Jan 2024 11:22:38 +0100 Subject: [PATCH 042/652] [lld] [MTE] Allow android note for static executables. (#77078) Florian pointed out that we're accidentally eliding the Android note for static executables, as it's guarded behind the "can have memtag globals" conditional. Of course, memtag globals are unsupported for static executables, but we should still allow static binaries to produce the Android note (as that's the only way they get MTE). --- lld/ELF/Arch/AArch64.cpp | 3 +-- lld/ELF/SyntheticSections.cpp | 2 +- lld/ELF/Writer.cpp | 16 +++++++++++----- lld/ELF/Writer.h | 1 + lld/test/ELF/aarch64-memtag-android-abi.s | 12 ++++++++++++ 5 files changed, 26 insertions(+), 8 deletions(-) diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp index 048f0ec30ebd..54b0a84e5213 100644 --- a/lld/ELF/Arch/AArch64.cpp +++ b/lld/ELF/Arch/AArch64.cpp @@ -1025,8 +1025,7 @@ addTaggedSymbolReferences(InputSectionBase &sec, // symbols should also be built with tagging. But, to handle these cases, we // demote the symbol to be untagged. void lld::elf::createTaggedSymbols(const SmallVector &files) { - assert(config->emachine == EM_AARCH64 && - config->androidMemtagMode != ELF::NT_MEMTAG_LEVEL_NONE); + assert(hasMemtag()); // First, collect all symbols that are marked as tagged, and count how many // times they're marked as tagged. diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index 2b32eb3a0fe3..19fced5aff92 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -1450,7 +1450,7 @@ DynamicSection::computeContents() { if (config->zPacPlt) addInt(DT_AARCH64_PAC_PLT, 0); - if (config->androidMemtagMode != ELF::NT_MEMTAG_LEVEL_NONE) { + if (hasMemtag()) { addInt(DT_AARCH64_MEMTAG_MODE, config->androidMemtagMode == NT_MEMTAG_LEVEL_ASYNC); addInt(DT_AARCH64_MEMTAG_HEAP, config->androidMemtagHeap); addInt(DT_AARCH64_MEMTAG_STACK, config->androidMemtagStack); diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index a84e4864ab0e..7b9880a034bc 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -291,6 +291,11 @@ static void demoteSymbolsAndComputeIsPreemptible() { } } +bool elf::hasMemtag() { + return config->emachine == EM_AARCH64 && + config->androidMemtagMode != ELF::NT_MEMTAG_LEVEL_NONE; +} + // Fully static executables don't support MTE globals at this point in time, as // we currently rely on: // - A dynamic loader to process relocations, and @@ -298,8 +303,7 @@ static void demoteSymbolsAndComputeIsPreemptible() { // This restriction could be removed in future by re-using some of the ideas // that ifuncs use in fully static executables. bool elf::canHaveMemtagGlobals() { - return config->emachine == EM_AARCH64 && - config->androidMemtagMode != ELF::NT_MEMTAG_LEVEL_NONE && + return hasMemtag() && (config->relocatable || config->shared || needsInterpSection()); } @@ -397,11 +401,13 @@ template void elf::createSyntheticSections() { std::make_unique>(*part.dynStrTab); part.dynamic = std::make_unique>(); - if (canHaveMemtagGlobals()) { + if (hasMemtag()) { part.memtagAndroidNote = std::make_unique(); add(*part.memtagAndroidNote); - part.memtagDescriptors = std::make_unique(); - add(*part.memtagDescriptors); + if (canHaveMemtagGlobals()) { + part.memtagDescriptors = std::make_unique(); + add(*part.memtagDescriptors); + } } if (config->androidPackDynRelocs) diff --git a/lld/ELF/Writer.h b/lld/ELF/Writer.h index eaf021aac42e..aac8176d9098 100644 --- a/lld/ELF/Writer.h +++ b/lld/ELF/Writer.h @@ -57,6 +57,7 @@ bool isMipsN32Abi(const InputFile *f); bool isMicroMips(); bool isMipsR6(); +bool hasMemtag(); bool canHaveMemtagGlobals(); } // namespace lld::elf diff --git a/lld/test/ELF/aarch64-memtag-android-abi.s b/lld/test/ELF/aarch64-memtag-android-abi.s index e5744483e447..7c6a26aa9524 100644 --- a/lld/test/ELF/aarch64-memtag-android-abi.s +++ b/lld/test/ELF/aarch64-memtag-android-abi.s @@ -56,6 +56,18 @@ # BAD-MODE: error: unknown --android-memtag-mode value: "asymm", should be one of # BAD-MODE: {async, sync, none} +# RUN: ld.lld -static --android-memtag-mode=sync --android-memtag-heap \ +# RUN: --android-memtag-stack %t.o -o %t +# RUN: llvm-readelf --memtag %t | FileCheck %s --check-prefixes=STATIC + +# STATIC: Memtag Dynamic Entries: +# STATIC-NEXT: < none found > +# STATIC: Memtag Android Note: +# STATIC-NEXT: Tagging Mode: SYNC +# STATIC-NEXT: Heap: Enabled +# STATIC-NEXT: Stack: Enabled + + .globl _start _start: ret -- GitLab From a9ffc92fc4428723e85485102dfe10fbea966e64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nathan=20Gau=C3=ABr?= Date: Mon, 8 Jan 2024 11:41:45 +0100 Subject: [PATCH 043/652] [SPIR-V] Add pre-headers to loops. (#75844) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the first of the 7 steps outlined in #75801. This PR explicitely calls the SimplifyLoops pass. Directly following this pass should follow the 6 others required to structurize the IR. Running this pass could generate empty basic-blocks, which are implicit fallthrough to the successor BB. There was a specific condition in the SPIR-V ISel which handled implicit fallthrough, but it couldn't work on empty basic-blocks. This commits removes the old logic, and adds this new logic, which checks all basic-blocks for implicit fallthroughs, including empty ones. --------- Signed-off-by: Nathan Gauër --- llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 35 ++++++++++ llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 14 ++++ llvm/lib/Target/SPIRV/SPIRVUtils.cpp | 4 +- llvm/lib/Target/SPIRV/SPIRVUtils.h | 2 +- .../CodeGen/SPIRV/scfg-add-pre-headers.ll | 66 +++++++++++++++++++ 5 files changed, 118 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/SPIRV/scfg-add-pre-headers.ll diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index 429b08e199cd..cbc16fa98661 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -607,6 +607,40 @@ static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, } } +static bool isImplicitFallthrough(MachineBasicBlock &MBB) { + if (MBB.empty()) + return true; + + // Branching SPIR-V intrinsics are not detected by this generic method. + // Thus, we can only trust negative result. + if (!MBB.canFallThrough()) + return false; + + // Otherwise, we must manually check if we have a SPIR-V intrinsic which + // prevent an implicit fallthrough. + for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend(); + It != E; ++It) { + if (isSpvIntrinsic(*It, Intrinsic::spv_switch)) + return false; + } + return true; +} + +static void removeImplicitFallthroughs(MachineFunction &MF, + MachineIRBuilder MIB) { + // It is valid for MachineBasicBlocks to not finish with a branch instruction. + // In such cases, they will simply fallthrough their immediate successor. + for (MachineBasicBlock &MBB : MF) { + if (!isImplicitFallthrough(MBB)) + continue; + + assert(std::distance(MBB.successors().begin(), MBB.successors().end()) == + 1); + MIB.setInsertPt(MBB, MBB.end()); + MIB.buildBr(**MBB.successors().begin()); + } +} + bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) { // Initialize the type registry. const SPIRVSubtarget &ST = MF.getSubtarget(); @@ -619,6 +653,7 @@ bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) { generateAssignInstrs(MF, GR, MIB); processSwitches(MF, GR, MIB); processInstrsWithTypeFolding(MF, GR, MIB); + removeImplicitFallthroughs(MF, MIB); return true; } diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index 1503f263e42c..62d9090d289f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -29,6 +29,7 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Pass.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Transforms/Utils.h" #include using namespace llvm; @@ -151,6 +152,19 @@ TargetPassConfig *SPIRVTargetMachine::createPassConfig(PassManagerBase &PM) { } void SPIRVPassConfig::addIRPasses() { + if (TM.getSubtargetImpl()->isVulkanEnv()) { + // Once legalized, we need to structurize the CFG to follow the spec. + // This is done through the following 8 steps. + // TODO(#75801): add the remaining steps. + + // 1. Simplify loop for subsequent transformations. After this steps, loops + // have the following properties: + // - loops have a single entry edge (pre-header to loop header). + // - all loop exits are dominated by the loop pre-header. + // - loops have a single back-edge. + addPass(createLoopSimplifyPass()); + } + TargetPassConfig::addIRPasses(); addPass(createSPIRVRegularizerPass()); addPass(createSPIRVPrepareFunctionsPass(TM)); diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp index 1c0e8d84e2fd..d4f7d8e89af5 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp @@ -228,8 +228,8 @@ uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI) { return MI->getOperand(1).getCImm()->getValue().getZExtValue(); } -bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID) { - if (auto *GI = dyn_cast(&MI)) +bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID) { + if (const auto *GI = dyn_cast(&MI)) return GI->is(IntrinsicID); return false; } diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h index 30fae6c7de47..60742e2f2728 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.h +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h @@ -79,7 +79,7 @@ MachineInstr *getDefInstrMaybeConstant(Register &ConstReg, uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI); // Check if MI is a SPIR-V specific intrinsic call. -bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID); +bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID); // Get type of i-th operand of the metadata node. Type *getMDOperandAsType(const MDNode *N, unsigned I); diff --git a/llvm/test/CodeGen/SPIRV/scfg-add-pre-headers.ll b/llvm/test/CodeGen/SPIRV/scfg-add-pre-headers.ll new file mode 100644 index 000000000000..d351c9c4d2a4 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/scfg-add-pre-headers.ll @@ -0,0 +1,66 @@ +; RUN: llc -mtriple=spirv-unknown-unknown -O0 %s -o - | FileCheck %s + +; CHECK-DAG: %[[#bool:]] = OpTypeBool +; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#uint_0:]] = OpConstant %[[#uint]] 0 + +define void @main() #1 { + %1 = icmp ne i32 0, 0 + br i1 %1, label %l1, label %l2 + +; CHECK: %[[#cond:]] = OpINotEqual %[[#bool]] %[[#uint_0]] %[[#uint_0]] +; CHECK: OpBranchConditional %[[#cond]] %[[#l1_pre:]] %[[#l2_pre:]] + +; CHECK-DAG: %[[#l2_pre]] = OpLabel +; CHECK-NEXT: OpBranch %[[#l2_header:]] + +; CHECK-DAG: %[[#l1_pre]] = OpLabel +; CHECK-NEXT: OpBranch %[[#l1_header:]] + +l1: + br i1 %1, label %l1_body, label %l1_end +; CHECK-DAG: %[[#l1_header]] = OpLabel +; CHECK-NEXT: OpBranchConditional %[[#cond]] %[[#l1_body:]] %[[#l1_end:]] + +l1_body: + br label %l1_continue +; CHECK-DAG: %[[#l1_body]] = OpLabel +; CHECK-NEXT: OpBranch %[[#l1_continue:]] + +l1_continue: + br label %l1 +; CHECK-DAG: %[[#l1_continue]] = OpLabel +; CHECK-NEXT: OpBranch %[[#l1_header]] + +l1_end: + br label %end +; CHECK-DAG: %[[#l1_end]] = OpLabel +; CHECK-NEXT: OpBranch %[[#end:]] + +l2: + br i1 %1, label %l2_body, label %l2_end +; CHECK-DAG: %[[#l2_header]] = OpLabel +; CHECK-NEXT: OpBranchConditional %[[#cond]] %[[#l2_body:]] %[[#l2_end:]] + +l2_body: + br label %l2_continue +; CHECK-DAG: %[[#l2_body]] = OpLabel +; CHECK-NEXT: OpBranch %[[#l2_continue:]] + +l2_continue: + br label %l2 +; CHECK-DAG: %[[#l2_continue]] = OpLabel +; CHECK-NEXT: OpBranch %[[#l2_header]] + +l2_end: + br label %end +; CHECK-DAG: %[[#l2_end]] = OpLabel +; CHECK-NEXT: OpBranch %[[#end:]] + +end: + ret void +; CHECK-DAG: %[[#end]] = OpLabel +; CHECK-NEXT: OpReturn +} + +attributes #1 = { "hlsl.numthreads"="4,8,16" "hlsl.shader"="compute" convergent } -- GitLab From 10b5b5d6e2df25dab86fe89a78c5df6f507f6e50 Mon Sep 17 00:00:00 2001 From: Haojian Wu Date: Mon, 8 Jan 2024 11:49:36 +0100 Subject: [PATCH 044/652] [clang] Fix a crash when referencing the result if the overload fails (#77288) after 20a05677f9394d4bc9467fe7bc93a4ebd3aeda61 If the overload fails, the `Best` might point to the `end()`, referencing it leads to asan crashes. --- clang/lib/Sema/SemaOverload.cpp | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 9fb767101e1e..8e3a2d128807 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -13994,21 +13994,22 @@ ExprResult Sema::BuildOverloadedCallExpr(Scope *S, Expr *Fn, OverloadCandidateSet::iterator Best; OverloadingResult OverloadResult = CandidateSet.BestViableFunction(*this, Fn->getBeginLoc(), Best); - FunctionDecl *FDecl = Best->Function; // Model the case with a call to a templated function whose definition // encloses the call and whose return type contains a placeholder type as if // the UnresolvedLookupExpr was type-dependent. - if (OverloadResult == OR_Success && FDecl && - FDecl->isTemplateInstantiation() && - FDecl->getReturnType()->isUndeducedType()) { - if (auto TP = FDecl->getTemplateInstantiationPattern(false)) { - if (TP->willHaveBody()) { - CallExpr *CE = - CallExpr::Create(Context, Fn, Args, Context.DependentTy, VK_PRValue, - RParenLoc, CurFPFeatureOverrides()); - result = CE; - return result; + if (OverloadResult == OR_Success) { + FunctionDecl *FDecl = Best->Function; + if (FDecl && FDecl->isTemplateInstantiation() && + FDecl->getReturnType()->isUndeducedType()) { + if (auto TP = FDecl->getTemplateInstantiationPattern(false)) { + if (TP->willHaveBody()) { + CallExpr *CE = + CallExpr::Create(Context, Fn, Args, Context.DependentTy, + VK_PRValue, RParenLoc, CurFPFeatureOverrides()); + result = CE; + return result; + } } } } -- GitLab From e35c912039a644a2cc44cf88f451f7a2cdc455d9 Mon Sep 17 00:00:00 2001 From: Liao Chunyu Date: Mon, 8 Jan 2024 06:30:08 -0500 Subject: [PATCH 045/652] =?UTF-8?q?[RISCV][NFC]=20Fix=20gcc=20-Wparenthese?= =?UTF-8?q?s=20warning=20in=20RISCVISelDAGToDAG.cpp=20warning:=20RISCVISel?= =?UTF-8?q?DAGToDAG.cpp:767:=20warning:=20suggest=20parentheses=20around?= =?UTF-8?q?=20=E2=80=98&&=E2=80=99=20within=20=E2=80=98||=E2=80=99=20[-Wpa?= =?UTF-8?q?rentheses]=20=20=20767=20|=20=20=20=20=20=20=20=20=20=20AM=20?= =?UTF-8?q?=3D=3D=20ISD::POST=5FINC=20&&=20"Unexpected=20addressing=20mode?= =?UTF-8?q?");?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 7257c2e8fe1f..0d8688ba2eae 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -763,8 +763,8 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) { return false; EVT LoadVT = Ld->getMemoryVT(); - assert(AM == ISD::PRE_INC || - AM == ISD::POST_INC && "Unexpected addressing mode"); + assert((AM == ISD::PRE_INC || AM == ISD::POST_INC) && + "Unexpected addressing mode"); bool IsPre = AM == ISD::PRE_INC; bool IsPost = AM == ISD::POST_INC; int64_t Offset = C->getSExtValue(); -- GitLab From c8c525678e6dab2796c1996e0cdea31d4a865a9d Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 8 Jan 2024 18:48:35 +0700 Subject: [PATCH 046/652] [Flang] Remove unused triple variable. NFC (#77275) I'm not sure why we don't get an unused variable warning, but triple doesn't seem to be used after 898db1136e679. --- flang/lib/Frontend/FrontendActions.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index d4a3e164d207..1f8174bdcf22 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -743,9 +743,6 @@ void CodeGenAction::generateLLVMIR() { MLIRToLLVMPassPipelineConfig config(level, opts); - const auto targetOpts = ci.getInvocation().getTargetOpts(); - const llvm::Triple triple(targetOpts.triple); - if (auto vsr = getVScaleRange(ci)) { config.VScaleMin = vsr->first; config.VScaleMax = vsr->second; -- GitLab From fb72a445c1abb21034dc4a63b8489f39150a5566 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Mon, 8 Jan 2024 19:43:49 +0800 Subject: [PATCH 047/652] [X86] Emit NDD2NonNDD entris in the EVEX comprerssion table, NFCI This patch is a straightfoward change based on the design in #77202. It does not have any effect since we haven't supported compressing ND to non-ND in X86CompressEVEX.cpp. --- llvm/lib/Target/X86/X86CompressEVEX.cpp | 33 ++++++++++--------- .../TableGen/X86CompressEVEXTablesEmitter.cpp | 17 +++++++--- 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp index b5928b93ffff..b95baddd9dea 100644 --- a/llvm/lib/Target/X86/X86CompressEVEX.cpp +++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp @@ -221,21 +221,27 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { } static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { - const MCInstrDesc &Desc = MI.getDesc(); + uint64_t TSFlags = MI.getDesc().TSFlags; // Check for EVEX instructions only. - if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX) + if ((TSFlags & X86II::EncodingMask) != X86II::EVEX) return false; - // Check for EVEX instructions with mask or broadcast as in these cases - // the EVEX prefix is needed in order to carry this information - // thus preventing the transformation to VEX encoding. - if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B)) + // Instructions with mask or 512-bit vector can't be converted to VEX. + if (TSFlags & (X86II::EVEX_K | X86II::EVEX_L2)) return false; - // Check for EVEX instructions with L2 set. These instructions are 512-bits - // and can't be converted to VEX. - if (Desc.TSFlags & X86II::EVEX_L2) + // EVEX_B has several meanings. + // AVX512: + // register form: rounding control or SAE + // memory form: broadcast + // + // APX: + // MAP4: NDD + // + // For AVX512 cases, EVEX prefix is needed in order to carry this information + // thus preventing the transformation to VEX encoding. + if (TSFlags & X86II::EVEX_B) return false; ArrayRef Table = ArrayRef(X86CompressEVEXTable); @@ -245,11 +251,8 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { if (I == Table.end() || I->OldOpc != Opc) return false; - if (usesExtendedRegister(MI)) - return false; - if (!checkVEXInstPredicate(Opc, ST)) - return false; - if (!performCustomAdjustments(MI, I->NewOpc)) + if (usesExtendedRegister(MI) || !checkVEXInstPredicate(Opc, ST) || + !performCustomAdjustments(MI, I->NewOpc)) return false; const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc); @@ -272,7 +275,7 @@ bool CompressEVEXPass::runOnMachineFunction(MachineFunction &MF) { } #endif const X86Subtarget &ST = MF.getSubtarget(); - if (!ST.hasAVX512() && !ST.hasEGPR()) + if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD()) return false; bool Changed = false; diff --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp index 8366d044eb37..aa8527e75380 100644 --- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp @@ -135,10 +135,10 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) { for (const CodeGenInstruction *Inst : NumberedInstructions) { const Record *Rec = Inst->TheDef; + StringRef Name = Rec->getName(); // _REV instruction should not appear before encoding optimization if (!Rec->isSubClassOf("X86Inst") || - Rec->getValueAsBit("isAsmParserOnly") || - Rec->getName().ends_with("_REV")) + Rec->getValueAsBit("isAsmParserOnly") || Name.ends_with("_REV")) continue; // Promoted legacy instruction is in EVEX space, and has REX2-encoding @@ -149,18 +149,19 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) { X86Local::ExplicitEVEX) continue; - if (NoCompressSet.find(Rec->getName()) != NoCompressSet.end()) + if (NoCompressSet.find(Name) != NoCompressSet.end()) continue; RecognizableInstrBase RI(*Inst); + bool IsND = RI.OpMap == X86Local::T_MAP4 && RI.HasEVEX_B && RI.HasVEX_4V; // Add VEX encoded instructions to one of CompressedInsts vectors according // to it's opcode. if (RI.Encoding == X86Local::VEX) CompressedInsts[RI.Opcode].push_back(Inst); // Add relevant EVEX encoded instructions to PreCompressionInsts - else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_B && - !RI.HasEVEX_L2) + else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 && + (!RI.HasEVEX_B || IsND)) PreCompressionInsts.push_back(Inst); } @@ -176,6 +177,12 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) { } else if (Name.ends_with("_EVEX")) { if (auto *NewRec = Records.getDef(Name.drop_back(5))) NewInst = &Target.getInstruction(NewRec); + } else if (Name.ends_with("_ND")) { + if (auto *NewRec = Records.getDef(Name.drop_back(3))) { + auto &TempInst = Target.getInstruction(NewRec); + if (isRegisterOperand(TempInst.Operands[0].Rec)) + NewInst = &TempInst; + } } else { // For each pre-compression instruction look for a match in the appropriate // vector (instructions with the same opcode) using function object -- GitLab From 4fdd24b8d355e49d657c7c8a380b6f9b1b47ce1e Mon Sep 17 00:00:00 2001 From: OCHyams Date: Mon, 8 Jan 2024 11:47:58 +0000 Subject: [PATCH 048/652] [RemoveDIs][NFC] Update SelectionDAG test to check RemoveDIs mode too In line with other RemoveDIs test updates. This test fails without #76941. --- llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll b/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll index 629c236f6831..600d6d837964 100644 --- a/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll +++ b/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll @@ -5,6 +5,16 @@ ; RUN: -experimental-debug-variable-locations=true \ ; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF +; Repeat checks with experimental debginfo iterators. +; RUN: llc %s -stop-before finalize-isel -o - \ +; RUN: -try-experimental-debuginfo-iterators \ +; RUN: -experimental-debug-variable-locations=false \ +; RUN: | FileCheck %s --check-prefixes=CHECK,DBGVALUE +; RUN: llc %s -stop-before finalize-isel -o - \ +; RUN: -try-experimental-debuginfo-iterators \ +; RUN: -experimental-debug-variable-locations=true \ +; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF + ;-------------------------------------------------------------------- ; This test case is basically generated from the following C code. ; Compiled with "--target=x86_64-apple-darwin -S -g -O3" to get debug -- GitLab From bdbaf6e61b63e24b94c85d7f71c11c212cd4cc9b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 8 Jan 2024 18:59:01 +0700 Subject: [PATCH 049/652] AMDGPU: Make v8bf16/v16bf16 legal types (#76678) Depends #76217 --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 16 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 56 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 56 + llvm/test/CodeGen/AMDGPU/bf16.ll | 6663 ++++++++--------- 4 files changed, 3284 insertions(+), 3507 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 2f663571a8f9..0dbcaf5a1b13 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -387,18 +387,20 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, MVT::v9i32, MVT::v9f32, MVT::v10i32, MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32}, Custom); + + // FIXME: Why is v8f16/v8bf16 missing? setOperationAction( ISD::EXTRACT_SUBVECTOR, - {MVT::v2f16, MVT::v2i16, MVT::v2bf16, MVT::v4f16, MVT::v4i16, - MVT::v4bf16, MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32, + {MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4f16, MVT::v4bf16, + MVT::v4i16, MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32, MVT::v4f32, MVT::v4i32, MVT::v5f32, MVT::v5i32, MVT::v6f32, MVT::v6i32, MVT::v7f32, MVT::v7i32, MVT::v8f32, MVT::v8i32, MVT::v9f32, MVT::v9i32, MVT::v10i32, MVT::v10f32, MVT::v11i32, - MVT::v11f32, MVT::v12i32, MVT::v12f32, MVT::v16f16, MVT::v16i16, - MVT::v16f32, MVT::v16i32, MVT::v32f32, MVT::v32i32, MVT::v2f64, - MVT::v2i64, MVT::v3f64, MVT::v3i64, MVT::v4f64, MVT::v4i64, - MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64, MVT::v32i16, - MVT::v32f16}, + MVT::v11f32, MVT::v12i32, MVT::v12f32, MVT::v16f16, MVT::v16bf16, + MVT::v16i16, MVT::v16f32, MVT::v16i32, MVT::v32f32, MVT::v32i32, + MVT::v2f64, MVT::v2i64, MVT::v3f64, MVT::v3i64, MVT::v4f64, + MVT::v4i64, MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64, + MVT::v32i16, MVT::v32f16, MVT::v32bf16}, Custom); setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 079cae06888c..e865c73015d2 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -167,8 +167,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, addRegisterClass(MVT::v4bf16, &AMDGPU::SReg_64RegClass); addRegisterClass(MVT::v8i16, &AMDGPU::SGPR_128RegClass); addRegisterClass(MVT::v8f16, &AMDGPU::SGPR_128RegClass); + addRegisterClass(MVT::v8bf16, &AMDGPU::SGPR_128RegClass); addRegisterClass(MVT::v16i16, &AMDGPU::SGPR_256RegClass); addRegisterClass(MVT::v16f16, &AMDGPU::SGPR_256RegClass); + addRegisterClass(MVT::v16bf16, &AMDGPU::SGPR_256RegClass); addRegisterClass(MVT::v32i16, &AMDGPU::SGPR_512RegClass); addRegisterClass(MVT::v32f16, &AMDGPU::SGPR_512RegClass); } @@ -310,13 +312,14 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, // We only support LOAD/STORE and vector manipulation ops for vectors // with > 4 elements. for (MVT VT : - {MVT::v8i32, MVT::v8f32, MVT::v9i32, MVT::v9f32, MVT::v10i32, - MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32, - MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64, MVT::v4i16, - MVT::v4f16, MVT::v4bf16, MVT::v3i64, MVT::v3f64, MVT::v6i32, - MVT::v6f32, MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64, - MVT::v8i16, MVT::v8f16, MVT::v16i16, MVT::v16f16, MVT::v16i64, - MVT::v16f64, MVT::v32i32, MVT::v32f32, MVT::v32i16, MVT::v32f16}) { + {MVT::v8i32, MVT::v8f32, MVT::v9i32, MVT::v9f32, MVT::v10i32, + MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32, + MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64, MVT::v4i16, + MVT::v4f16, MVT::v4bf16, MVT::v3i64, MVT::v3f64, MVT::v6i32, + MVT::v6f32, MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64, + MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16, + MVT::v16bf16, MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32, + MVT::v32i16, MVT::v32f16, MVT::v32bf16}) { for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { switch (Op) { case ISD::LOAD: @@ -683,6 +686,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, AddPromotedToType(ISD::LOAD, MVT::v8i16, MVT::v4i32); setOperationAction(ISD::LOAD, MVT::v8f16, Promote); AddPromotedToType(ISD::LOAD, MVT::v8f16, MVT::v4i32); + setOperationAction(ISD::LOAD, MVT::v8bf16, Promote); + AddPromotedToType(ISD::LOAD, MVT::v8bf16, MVT::v4i32); setOperationAction(ISD::STORE, MVT::v4i16, Promote); AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32); @@ -693,16 +698,22 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, AddPromotedToType(ISD::STORE, MVT::v8i16, MVT::v4i32); setOperationAction(ISD::STORE, MVT::v8f16, Promote); AddPromotedToType(ISD::STORE, MVT::v8f16, MVT::v4i32); + setOperationAction(ISD::STORE, MVT::v8bf16, Promote); + AddPromotedToType(ISD::STORE, MVT::v8bf16, MVT::v4i32); setOperationAction(ISD::LOAD, MVT::v16i16, Promote); AddPromotedToType(ISD::LOAD, MVT::v16i16, MVT::v8i32); setOperationAction(ISD::LOAD, MVT::v16f16, Promote); AddPromotedToType(ISD::LOAD, MVT::v16f16, MVT::v8i32); + setOperationAction(ISD::LOAD, MVT::v16bf16, Promote); + AddPromotedToType(ISD::LOAD, MVT::v16bf16, MVT::v8i32); setOperationAction(ISD::STORE, MVT::v16i16, Promote); AddPromotedToType(ISD::STORE, MVT::v16i16, MVT::v8i32); setOperationAction(ISD::STORE, MVT::v16f16, Promote); AddPromotedToType(ISD::STORE, MVT::v16f16, MVT::v8i32); + setOperationAction(ISD::STORE, MVT::v16bf16, Promote); + AddPromotedToType(ISD::STORE, MVT::v16bf16, MVT::v8i32); setOperationAction(ISD::LOAD, MVT::v32i16, Promote); AddPromotedToType(ISD::LOAD, MVT::v32i16, MVT::v16i32); @@ -725,7 +736,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, MVT::v8i32, Expand); if (!Subtarget->hasVOP3PInsts()) - setOperationAction(ISD::BUILD_VECTOR, {MVT::v2i16, MVT::v2f16}, Custom); + setOperationAction(ISD::BUILD_VECTOR, + {MVT::v2i16, MVT::v2f16, MVT::v2bf16}, Custom); setOperationAction(ISD::FNEG, MVT::v2f16, Legal); // This isn't really legal, but this avoids the legalizer unrolling it (and @@ -743,8 +755,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16}, Expand); - for (MVT Vec16 : {MVT::v8i16, MVT::v8f16, MVT::v16i16, MVT::v16f16, - MVT::v32i16, MVT::v32f16}) { + for (MVT Vec16 : + {MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16, + MVT::v16bf16, MVT::v32i16, MVT::v32f16, MVT::v32bf16}) { setOperationAction( {ISD::BUILD_VECTOR, ISD::EXTRACT_VECTOR_ELT, ISD::SCALAR_TO_VECTOR}, Vec16, Custom); @@ -814,9 +827,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, } setOperationAction(ISD::SELECT, - {MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8, - MVT::v8i16, MVT::v8f16, MVT::v16i16, MVT::v16f16, - MVT::v32i16, MVT::v32f16}, + {MVT::v4i16, MVT::v4f16, MVT::v4bf16, MVT::v2i8, MVT::v4i8, + MVT::v8i8, MVT::v8i16, MVT::v8f16, MVT::v8bf16, + MVT::v16i16, MVT::v16f16, MVT::v16bf16, MVT::v32i16, + MVT::v32f16, MVT::v32bf16}, Custom); setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom); @@ -5431,7 +5445,9 @@ SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op, assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v4f32 || VT == MVT::v16i16 || VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 || - VT == MVT::v32f32 || VT == MVT::v32f16 || VT == MVT::v32i16); + VT == MVT::v32f32 || VT == MVT::v32f16 || VT == MVT::v32i16 || + VT == MVT::v4bf16 || VT == MVT::v8bf16 || VT == MVT::v16bf16 || + VT == MVT::v32bf16); SDValue Lo0, Hi0; SDValue Op0 = Op.getOperand(0); @@ -6854,8 +6870,8 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op, SDLoc SL(Op); EVT VT = Op.getValueType(); - if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16 || - VT == MVT::v8i16 || VT == MVT::v8f16) { + if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v8i16 || + VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) { EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), VT.getVectorNumElements() / 2); MVT HalfIntVT = MVT::getIntegerVT(HalfVT.getSizeInBits()); @@ -6878,7 +6894,7 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op, return DAG.getNode(ISD::BITCAST, SL, VT, Blend); } - if (VT == MVT::v16i16 || VT == MVT::v16f16) { + if (VT == MVT::v16i16 || VT == MVT::v16f16 || VT == MVT::v16bf16) { EVT QuarterVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), VT.getVectorNumElements() / 4); MVT QuarterIntVT = MVT::getIntegerVT(QuarterVT.getSizeInBits()); @@ -6899,7 +6915,7 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op, return DAG.getNode(ISD::BITCAST, SL, VT, Blend); } - if (VT == MVT::v32i16 || VT == MVT::v32f16) { + if (VT == MVT::v32i16 || VT == MVT::v32f16 || VT == MVT::v32bf16) { EVT QuarterVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), VT.getVectorNumElements() / 8); MVT QuarterIntVT = MVT::getIntegerVT(QuarterVT.getSizeInBits()); @@ -14182,11 +14198,11 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, EVT VT = N->getValueType(0); // v2i16 (scalar_to_vector i16:x) -> v2i16 (bitcast (any_extend i16:x)) - if (VT == MVT::v2i16 || VT == MVT::v2f16) { + if (VT == MVT::v2i16 || VT == MVT::v2f16 || VT == MVT::v2f16) { SDLoc SL(N); SDValue Src = N->getOperand(0); EVT EltVT = Src.getValueType(); - if (EltVT == MVT::f16) + if (EltVT != MVT::i16) Src = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Src); SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Src); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index ea2a8b75d074..b0b7854ffc06 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1633,6 +1633,37 @@ def : BitConvert ; def : BitConvert ; def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + + // 160-bit bitcast def : BitConvert ; def : BitConvert ; @@ -1697,6 +1728,31 @@ def : BitConvert ; def : BitConvert ; def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + + + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + + + + // 288-bit bitcast def : BitConvert ; def : BitConvert ; diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll index 2a3417e24185..4e87b4e82ba3 100644 --- a/llvm/test/CodeGen/AMDGPU/bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/bf16.ll @@ -2411,16 +2411,16 @@ define void @test_load_store_v16bf16(ptr addrspace(1) %in, ptr addrspace(1) %out ; GFX8-LABEL: test_load_store_v16bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_add_u32_e32 v4, vcc, 16, v0 -; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_dwordx4 v[4:7], v[4:5] -; GFX8-NEXT: flat_load_dwordx4 v[8:11], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v8, vcc, 16, v0 +; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dwordx4 v[4:7], v[0:1] +; GFX8-NEXT: flat_load_dwordx4 v[8:11], v[8:9] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v2 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] +; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[4:7] ; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[8:11] +; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11] ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -4395,9 +4395,7 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX11-NEXT: v_writelane_b32 v5, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: scratch_store_b64 v4, v[2:3], off offset:8 dlc -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off dlc +; GFX11-NEXT: scratch_store_b128 v4, v[0:3], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: v_readlane_b32 s31, v5, 1 ; GFX11-NEXT: v_readlane_b32 s30, v5, 0 @@ -4751,18 +4749,12 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX11-NEXT: v_writelane_b32 v9, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_add_nc_u32_e32 v10, 24, v8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_readlane_b32 s31, v9, 1 -; GFX11-NEXT: v_readlane_b32 s30, v9, 0 -; GFX11-NEXT: scratch_store_b64 v10, v[6:7], off dlc -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: scratch_store_b64 v8, v[4:5], off offset:16 dlc +; GFX11-NEXT: scratch_store_b128 v8, v[4:7], off offset:16 dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: scratch_store_b64 v8, v[2:3], off offset:8 dlc -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: scratch_store_b64 v8, v[0:1], off dlc +; GFX11-NEXT: scratch_store_b128 v8, v[0:3], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_readlane_b32 s31, v9, 1 +; GFX11-NEXT: v_readlane_b32 s30, v9, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v9, off, s33 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 @@ -5470,60 +5462,48 @@ define <5 x float> @global_extload_v5bf16_to_v5f32(ptr addrspace(1) %ptr) { ; GFX8-LABEL: global_extload_v5bf16_to_v5f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] -; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v0 -; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_ushort v4, v[0:1] -; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: flat_load_dwordx4 v[2:5], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: global_extload_v5bf16_to_v5f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v4, v[0:1], off offset:8 -; GFX9-NEXT: global_load_dwordx2 v[2:3], v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX9-NEXT: global_load_dwordx4 v[2:5], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: global_extload_v5bf16_to_v5f32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[2:3], v[0:1], off -; GFX10-NEXT: global_load_ushort v4, v[0:1], off offset:8 -; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: global_load_dwordx4 v[2:5], v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: global_extload_v5bf16_to_v5f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b64 v[2:3], v[0:1], off -; GFX11-NEXT: global_load_u16 v4, v[0:1], off offset:8 -; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: global_load_b128 v[2:5], v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX11-NEXT: s_setpc_b64 s[30:31] %load = load <5 x bfloat>, ptr addrspace(1) %ptr @@ -6045,138 +6025,138 @@ define <32 x float> @global_extload_v32bf16_to_v32f32(ptr addrspace(1) %ptr) { ; GFX9-LABEL: global_extload_v32bf16_to_v32f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[4:7], v[0:1], off -; GFX9-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16 -; GFX9-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:32 -; GFX9-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:48 +; GFX9-NEXT: global_load_dwordx4 v[16:19], v[0:1], off +; GFX9-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:16 +; GFX9-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:32 +; GFX9-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:48 ; GFX9-NEXT: s_waitcnt vmcnt(3) -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v4 -; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v5 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v6 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 -; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v17 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v19 ; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v12 -; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v13 -; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v14 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 -; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v15 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v23 ; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v21 -; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v22 -; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v23 -; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v27 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v28 -; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v29 -; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v30 -; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v31 -; GFX9-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 +; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v32 +; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v33 +; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v34 +; GFX9-NEXT: v_and_b32_e32 v31, 0xffff0000, v35 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v32 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v33 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v34 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v35 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: global_extload_v32bf16_to_v32f32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_clause 0x3 -; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off -; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16 -; GFX10-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:32 -; GFX10-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:48 +; GFX10-NEXT: global_load_dwordx4 v[32:35], v[0:1], off +; GFX10-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:16 +; GFX10-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:32 +; GFX10-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:48 ; GFX10-NEXT: s_waitcnt vmcnt(3) -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v5 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v33 +; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v34 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v35 ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v12 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v36 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v37 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v38 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v39 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v21 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v22 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v23 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v48 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 +; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v50 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v51 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v28 -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v29 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v30 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v52 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v53 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v54 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v55 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v32 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v33 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v34 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v35 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v36 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v37 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v38 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v48 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v49 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v50 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v51 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v52 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v53 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v54 +; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v55 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: global_extload_v32bf16_to_v32f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_clause 0x3 -; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off -; GFX11-NEXT: global_load_b128 v[12:15], v[0:1], off offset:16 -; GFX11-NEXT: global_load_b128 v[20:23], v[0:1], off offset:32 -; GFX11-NEXT: global_load_b128 v[28:31], v[0:1], off offset:48 +; GFX11-NEXT: global_load_b128 v[32:35], v[0:1], off +; GFX11-NEXT: global_load_b128 v[36:39], v[0:1], off offset:16 +; GFX11-NEXT: global_load_b128 v[48:51], v[0:1], off offset:32 +; GFX11-NEXT: global_load_b128 v[52:55], v[0:1], off offset:48 ; GFX11-NEXT: s_waitcnt vmcnt(3) -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v4 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v5 -; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 +; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v33 +; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v34 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v35 ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v12 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v13 -; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v14 -; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 -; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v15 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v36 +; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v37 +; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v38 +; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v39 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v21 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v22 -; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 -; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v23 -; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v48 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 +; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v50 +; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v51 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v28 -; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v28 -; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v29 -; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v29 -; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v30 -; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 -; GFX11-NEXT: v_lshlrev_b32_e32 v30, 16, v31 -; GFX11-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 +; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v52 +; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v53 +; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v54 +; GFX11-NEXT: v_and_b32_e32 v31, 0xffff0000, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v32 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v33 +; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v34 +; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v35 +; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v36 +; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v37 +; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v38 +; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v39 +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v48 +; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v49 +; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v50 +; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v51 +; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v52 +; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v53 +; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v54 +; GFX11-NEXT: v_lshlrev_b32_e32 v30, 16, v55 ; GFX11-NEXT: s_setpc_b64 s[30:31] %load = load <32 x bfloat>, ptr addrspace(1) %ptr %fpext = fpext <32 x bfloat> %load to <32 x float> @@ -6511,20 +6491,16 @@ define <5 x double> @global_extload_v5bf16_to_v5f64(ptr addrspace(1) %ptr) { ; GFX8-LABEL: global_extload_v5bf16_to_v5f64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] -; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v0 -; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_ushort v8, v[0:1] -; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v2 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v3 -; GFX8-NEXT: v_cvt_f64_f32_e32 v[0:1], v0 +; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_cvt_f64_f32_e32 v[2:3], v2 -; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX8-NEXT: v_cvt_f64_f32_e32 v[0:1], v3 +; GFX8-NEXT: v_cvt_f64_f32_e32 v[2:3], v4 +; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v5 ; GFX8-NEXT: v_cvt_f64_f32_e32 v[6:7], v6 ; GFX8-NEXT: v_cvt_f64_f32_e32 v[8:9], v8 ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -6532,34 +6508,29 @@ define <5 x double> @global_extload_v5bf16_to_v5f64(ptr addrspace(1) %ptr) { ; GFX9-LABEL: global_extload_v5bf16_to_v5f64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v4, v[0:1], off offset:8 -; GFX9-NEXT: global_load_dwordx2 v[2:3], v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v3 -; GFX9-NEXT: v_cvt_f64_f32_e32 v[8:9], v0 -; GFX9-NEXT: v_cvt_f64_f32_e32 v[0:1], v1 -; GFX9-NEXT: v_cvt_f64_f32_e32 v[2:3], v2 -; GFX9-NEXT: v_cvt_f64_f32_e32 v[4:5], v4 +; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v1 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v1 +; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v2 +; GFX9-NEXT: v_cvt_f64_f32_e32 v[0:1], v3 +; GFX9-NEXT: v_cvt_f64_f32_e32 v[2:3], v4 +; GFX9-NEXT: v_cvt_f64_f32_e32 v[4:5], v5 ; GFX9-NEXT: v_cvt_f64_f32_e32 v[6:7], v6 +; GFX9-NEXT: v_cvt_f64_f32_e32 v[8:9], v8 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: global_extload_v5bf16_to_v5f64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[2:3], v[0:1], off -; GFX10-NEXT: global_load_ushort v4, v[0:1], off offset:8 -; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: global_load_dwordx4 v[2:5], v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v3 -; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX10-NEXT: v_cvt_f64_f32_e32 v[0:1], v0 ; GFX10-NEXT: v_cvt_f64_f32_e32 v[2:3], v2 @@ -6571,15 +6542,12 @@ define <5 x double> @global_extload_v5bf16_to_v5f64(ptr addrspace(1) %ptr) { ; GFX11-LABEL: global_extload_v5bf16_to_v5f64: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b64 v[2:3], v[0:1], off -; GFX11-NEXT: global_load_u16 v4, v[0:1], off offset:8 -; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: global_load_b128 v[2:5], v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v3 ; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v3 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v4 ; GFX11-NEXT: v_cvt_f64_f32_e32 v[0:1], v0 ; GFX11-NEXT: v_cvt_f64_f32_e32 v[2:3], v2 @@ -9865,480 +9833,483 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_fadd_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_add_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_add_f32_e32 v30, v14, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_add_f32_e32 v14, v32, v14 -; GFX8-NEXT: v_add_f32_e32 v13, v13, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_add_f32_e32 v29, v32, v29 -; GFX8-NEXT: v_add_f32_e32 v12, v12, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_add_f32_e32 v28, v32, v28 -; GFX8-NEXT: v_add_f32_e32 v11, v11, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_add_f32_e32 v27, v32, v27 -; GFX8-NEXT: v_add_f32_e32 v10, v10, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_add_f32_e32 v26, v32, v26 -; GFX8-NEXT: v_add_f32_e32 v9, v9, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_add_f32_e32 v8, v8, v24 -; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX8-NEXT: v_add_f32_e32 v25, v32, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_add_f32_e32 v32, v32, v33 -; GFX8-NEXT: v_add_f32_e32 v15, v15, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_add_f32_e32 v24, v33, v24 -; GFX8-NEXT: v_add_f32_e32 v7, v7, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_add_f32_e32 v23, v33, v23 -; GFX8-NEXT: v_add_f32_e32 v6, v6, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_add_f32_e32 v22, v33, v22 -; GFX8-NEXT: v_add_f32_e32 v5, v5, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_add_f32_e32 v21, v33, v21 -; GFX8-NEXT: v_add_f32_e32 v4, v4, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_add_f32_e32 v20, v33, v20 -; GFX8-NEXT: v_add_f32_e32 v3, v3, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_add_f32_e32 v19, v33, v19 -; GFX8-NEXT: v_add_f32_e32 v2, v2, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX8-NEXT: v_add_f32_e32 v18, v33, v18 -; GFX8-NEXT: v_add_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 ; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v16 -; GFX8-NEXT: v_add_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_add_f32_e32 v31, v32, v31 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_add_f32_e32 v1, v1, v17 +; GFX8-NEXT: v_add_f32_e32 v16, v31, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX8-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_add_f32_e32 v2, v2, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX8-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_add_f32_e32 v3, v3, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX8-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_add_f32_e32 v4, v4, v17 +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_add_f32_e32 v5, v5, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_add_f32_e32 v6, v6, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_add_f32_e32 v7, v7, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX8-NEXT: v_add_f32_e32 v8, v8, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_add_f32_e32 v9, v9, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_add_f32_e32 v10, v10, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_add_f32_e32 v11, v11, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_add_f32_e32 v12, v12, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_add_f32_e32 v13, v13, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX8-NEXT: v_add_f32_e32 v14, v14, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX8-NEXT: v_add_f32_e32 v15, v15, v17 +; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 -; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fadd_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX9-NEXT: v_add_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_add_f32_e32 v14, v14, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_add_f32_e32 v30, v32, v30 -; GFX9-NEXT: v_add_f32_e32 v13, v13, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_add_f32_e32 v29, v32, v29 -; GFX9-NEXT: v_add_f32_e32 v12, v12, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_add_f32_e32 v28, v32, v28 -; GFX9-NEXT: v_add_f32_e32 v11, v11, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_add_f32_e32 v27, v32, v27 -; GFX9-NEXT: v_add_f32_e32 v10, v10, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_add_f32_e32 v26, v32, v26 -; GFX9-NEXT: v_add_f32_e32 v9, v9, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_add_f32_e32 v8, v8, v24 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX9-NEXT: v_add_f32_e32 v25, v32, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_add_f32_e32 v0, v0, v16 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 -; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 -; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 -; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 -; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 -; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 -; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_add_f32_e32 v32, v32, v33 -; GFX9-NEXT: v_add_f32_e32 v15, v15, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_add_f32_e32 v24, v33, v24 -; GFX9-NEXT: v_add_f32_e32 v7, v7, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_add_f32_e32 v23, v33, v23 -; GFX9-NEXT: v_add_f32_e32 v6, v6, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_add_f32_e32 v22, v33, v22 -; GFX9-NEXT: v_add_f32_e32 v5, v5, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_add_f32_e32 v21, v33, v21 -; GFX9-NEXT: v_add_f32_e32 v4, v4, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_add_f32_e32 v20, v33, v20 -; GFX9-NEXT: v_add_f32_e32 v3, v3, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_add_f32_e32 v19, v33, v19 -; GFX9-NEXT: v_add_f32_e32 v2, v2, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 +; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_add_f32_e32 v18, v33, v18 +; GFX9-NEXT: v_add_f32_e32 v16, v31, v16 ; GFX9-NEXT: v_add_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX9-NEXT: v_add_f32_e32 v17, v33, v17 -; GFX9-NEXT: v_add_f32_e32 v0, v0, v16 -; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 -; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 -; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 -; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 -; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 -; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 -; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 -; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 -; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: v_fadd_v32bf16: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX10-NEXT: v_add_f32_e32 v39, v48, v39 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 -; GFX10-NEXT: v_add_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_add_f32_e32 v49, v50, v49 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 -; GFX10-NEXT: v_add_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_add_f32_e32 v2, v2, v17 +; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_add_f32_e32 v3, v3, v17 +; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_add_f32_e32 v4, v4, v17 +; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_add_f32_e32 v5, v5, v17 +; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_add_f32_e32 v6, v6, v17 +; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_add_f32_e32 v7, v7, v17 +; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_add_f32_e32 v8, v8, v17 +; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_add_f32_e32 v9, v9, v17 +; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_add_f32_e32 v10, v10, v17 +; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_add_f32_e32 v11, v11, v17 +; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_add_f32_e32 v12, v12, v17 +; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_add_f32_e32 v13, v13, v17 +; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_add_f32_e32 v14, v14, v17 +; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 +; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_add_f32_e32 v15, v15, v17 +; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: v_fadd_v32bf16: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 ; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 ; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_add_f32_e32 v33, v34, v33 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 -; GFX10-NEXT: v_add_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_add_f32_e32 v35, v36, v35 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 -; GFX10-NEXT: v_add_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_add_f32_e32 v37, v38, v37 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 -; GFX10-NEXT: v_add_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 ; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_add_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_add_f32_e32 v21, v53, v52 +; GFX10-NEXT: v_add_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_add_f32_e32 v22, v55, v54 +; GFX10-NEXT: v_add_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX10-NEXT: v_add_f32_e32 v32, v33, v32 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX10-NEXT: v_add_f32_e32 v34, v35, v34 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_add_f32_e32 v51, v52, v51 -; GFX10-NEXT: v_add_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_add_f32_e32 v25, v54, v53 -; GFX10-NEXT: v_add_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_add_f32_e32 v24, v64, v55 -; GFX10-NEXT: v_add_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_add_f32_e32 v23, v66, v65 -; GFX10-NEXT: v_add_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_add_f32_e32 v22, v68, v67 -; GFX10-NEXT: v_add_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_add_f32_e32 v21, v30, v34 -; GFX10-NEXT: v_add_f32_e32 v29, v29, v36 -; GFX10-NEXT: v_add_f32_e32 v28, v28, v38 -; GFX10-NEXT: v_add_f32_e32 v27, v27, v48 -; GFX10-NEXT: v_add_f32_e32 v26, v26, v50 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 +; GFX10-NEXT: v_add_f32_e32 v36, v37, v36 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 +; GFX10-NEXT: v_add_f32_e32 v38, v39, v38 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GFX10-NEXT: v_add_f32_e32 v3, v3, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 +; GFX10-NEXT: v_add_f32_e32 v48, v49, v48 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX10-NEXT: v_add_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 -; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX10-NEXT: v_add_f32_e32 v50, v51, v50 +; GFX10-NEXT: v_add_f32_e32 v23, v65, v64 +; GFX10-NEXT: v_add_f32_e32 v8, v8, v24 +; GFX10-NEXT: v_add_f32_e32 v24, v67, v66 +; GFX10-NEXT: v_add_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_add_f32_e32 v25, v33, v68 +; GFX10-NEXT: v_add_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_add_f32_e32 v16, v35, v16 +; GFX10-NEXT: v_add_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_add_f32_e32 v17, v37, v17 +; GFX10-NEXT: v_add_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_add_f32_e32 v18, v39, v18 +; GFX10-NEXT: v_add_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_add_f32_e32 v19, v49, v19 +; GFX10-NEXT: v_add_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX10-NEXT: v_add_f32_e32 v16, v32, v16 -; GFX10-NEXT: v_add_f32_e32 v15, v15, v17 -; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 +; GFX10-NEXT: v_add_f32_e32 v20, v20, v21 +; GFX10-NEXT: v_add_f32_e32 v15, v15, v22 +; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_fadd_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 -; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX11-NEXT: v_dual_add_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 -; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 +; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 +; GFX11-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX11-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 -; GFX11-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_dual_add_f32 v2, v2, v18 :: v_dual_add_f32 v3, v3, v19 -; GFX11-NEXT: v_dual_add_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 -; GFX11-NEXT: v_dual_add_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_add_f32_e32 v6, v6, v22 -; GFX11-NEXT: v_dual_add_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 +; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_add_f32_e32 v10, v10, v26 -; GFX11-NEXT: v_add_f32_e32 v26, v52, v51 -; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX11-NEXT: v_add_f32_e32 v25, v54, v53 -; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_add_f32_e32 v24, v64, v55 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX11-NEXT: v_add_f32_e32 v7, v7, v23 -; GFX11-NEXT: v_add_f32_e32 v23, v66, v65 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 -; GFX11-NEXT: v_dual_add_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 -; GFX11-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 -; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX11-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_add_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX11-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 ; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_add_f32_e32 v37, v86, v85 -; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_dual_add_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 +; GFX11-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_add_f32_e32 v4, v4, v20 +; GFX11-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_add_f32 v9, v9, v25 +; GFX11-NEXT: v_add_f32_e32 v25, v69, v68 +; GFX11-NEXT: v_dual_add_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 +; GFX11-NEXT: v_add_f32_e32 v27, v81, v80 +; GFX11-NEXT: v_add_f32_e32 v12, v12, v28 +; GFX11-NEXT: v_dual_add_f32 v28, v83, v82 :: v_dual_add_f32 v29, v85, v84 +; GFX11-NEXT: v_dual_add_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_add_f32_e32 v22, v55, v54 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX11-NEXT: v_add_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33 -; GFX11-NEXT: v_dual_add_f32 v34, v80, v71 :: v_dual_add_f32 v35, v82, v81 -; GFX11-NEXT: v_add_f32_e32 v36, v84, v83 -; GFX11-NEXT: v_dual_add_f32 v16, v32, v16 :: v_dual_add_f32 v15, v15, v17 -; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX11-NEXT: v_dual_add_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_add_f32_e32 v23, v65, v64 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_dual_add_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_add_f32_e32 v2, v2, v18 +; GFX11-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 +; GFX11-NEXT: v_add_f32_e32 v18, v39, v38 +; GFX11-NEXT: v_dual_add_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_add_f32_e32 v19, v49, v48 +; GFX11-NEXT: v_add_f32_e32 v17, v37, v36 +; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX11-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_add_f32_e32 v21, v53, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 +; GFX11-NEXT: v_add_f32_e32 v0, v0, v16 +; GFX11-NEXT: v_add_f32_e32 v16, v35, v34 +; GFX11-NEXT: v_add_f32_e32 v32, v33, v32 +; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 +; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 +; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 +; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_add_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_add_f32_e32 v15, v15, v17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = fadd <32 x bfloat> %a, %b @@ -12177,480 +12148,483 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_fmul_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_mul_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_mul_f32_e32 v30, v14, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_mul_f32_e32 v14, v32, v14 -; GFX8-NEXT: v_mul_f32_e32 v13, v13, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_mul_f32_e32 v29, v32, v29 -; GFX8-NEXT: v_mul_f32_e32 v12, v12, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_mul_f32_e32 v28, v32, v28 -; GFX8-NEXT: v_mul_f32_e32 v11, v11, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_mul_f32_e32 v27, v32, v27 -; GFX8-NEXT: v_mul_f32_e32 v10, v10, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_mul_f32_e32 v26, v32, v26 -; GFX8-NEXT: v_mul_f32_e32 v9, v9, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_mul_f32_e32 v8, v8, v24 -; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX8-NEXT: v_mul_f32_e32 v25, v32, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_mul_f32_e32 v32, v32, v33 -; GFX8-NEXT: v_mul_f32_e32 v15, v15, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_mul_f32_e32 v24, v33, v24 -; GFX8-NEXT: v_mul_f32_e32 v7, v7, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_mul_f32_e32 v23, v33, v23 -; GFX8-NEXT: v_mul_f32_e32 v6, v6, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_mul_f32_e32 v22, v33, v22 -; GFX8-NEXT: v_mul_f32_e32 v5, v5, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_mul_f32_e32 v21, v33, v21 -; GFX8-NEXT: v_mul_f32_e32 v4, v4, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_mul_f32_e32 v20, v33, v20 -; GFX8-NEXT: v_mul_f32_e32 v3, v3, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_mul_f32_e32 v19, v33, v19 -; GFX8-NEXT: v_mul_f32_e32 v2, v2, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX8-NEXT: v_mul_f32_e32 v18, v33, v18 -; GFX8-NEXT: v_mul_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 ; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, v0, v16 -; GFX8-NEXT: v_mul_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_mul_f32_e32 v31, v32, v31 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_mul_f32_e32 v1, v1, v17 +; GFX8-NEXT: v_mul_f32_e32 v16, v31, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_mul_f32_e32 v2, v2, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_mul_f32_e32 v3, v3, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_mul_f32_e32 v4, v4, v17 +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_mul_f32_e32 v5, v5, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_mul_f32_e32 v6, v6, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_mul_f32_e32 v7, v7, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX8-NEXT: v_mul_f32_e32 v8, v8, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_mul_f32_e32 v9, v9, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_mul_f32_e32 v10, v10, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_mul_f32_e32 v11, v11, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_mul_f32_e32 v12, v12, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_mul_f32_e32 v13, v13, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX8-NEXT: v_mul_f32_e32 v14, v14, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX8-NEXT: v_mul_f32_e32 v15, v15, v17 +; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 -; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fmul_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX9-NEXT: v_mul_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_mul_f32_e32 v14, v14, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_mul_f32_e32 v30, v32, v30 -; GFX9-NEXT: v_mul_f32_e32 v13, v13, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_mul_f32_e32 v29, v32, v29 -; GFX9-NEXT: v_mul_f32_e32 v12, v12, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_mul_f32_e32 v28, v32, v28 -; GFX9-NEXT: v_mul_f32_e32 v11, v11, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_mul_f32_e32 v27, v32, v27 -; GFX9-NEXT: v_mul_f32_e32 v10, v10, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_mul_f32_e32 v26, v32, v26 -; GFX9-NEXT: v_mul_f32_e32 v9, v9, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_mul_f32_e32 v8, v8, v24 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX9-NEXT: v_mul_f32_e32 v25, v32, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_mul_f32_e32 v0, v0, v16 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 -; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 -; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 -; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 -; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 -; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 -; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_mul_f32_e32 v32, v32, v33 -; GFX9-NEXT: v_mul_f32_e32 v15, v15, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_mul_f32_e32 v24, v33, v24 -; GFX9-NEXT: v_mul_f32_e32 v7, v7, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_mul_f32_e32 v23, v33, v23 -; GFX9-NEXT: v_mul_f32_e32 v6, v6, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_mul_f32_e32 v22, v33, v22 -; GFX9-NEXT: v_mul_f32_e32 v5, v5, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_mul_f32_e32 v21, v33, v21 -; GFX9-NEXT: v_mul_f32_e32 v4, v4, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_mul_f32_e32 v20, v33, v20 -; GFX9-NEXT: v_mul_f32_e32 v3, v3, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_mul_f32_e32 v19, v33, v19 -; GFX9-NEXT: v_mul_f32_e32 v2, v2, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 +; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_mul_f32_e32 v18, v33, v18 +; GFX9-NEXT: v_mul_f32_e32 v16, v31, v16 ; GFX9-NEXT: v_mul_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX9-NEXT: v_mul_f32_e32 v17, v33, v17 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v16 -; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 -; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 -; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 -; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 -; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 -; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 -; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 -; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 -; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_mul_f32_e32 v2, v2, v17 +; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_mul_f32_e32 v3, v3, v17 +; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_mul_f32_e32 v4, v4, v17 +; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_mul_f32_e32 v5, v5, v17 +; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_mul_f32_e32 v6, v6, v17 +; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_mul_f32_e32 v7, v7, v17 +; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_mul_f32_e32 v8, v8, v17 +; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_mul_f32_e32 v9, v9, v17 +; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_mul_f32_e32 v10, v10, v17 +; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_mul_f32_e32 v11, v11, v17 +; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_mul_f32_e32 v12, v12, v17 +; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_mul_f32_e32 v13, v13, v17 +; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_mul_f32_e32 v14, v14, v17 +; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 +; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_mul_f32_e32 v15, v15, v17 +; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_fmul_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX10-NEXT: v_mul_f32_e32 v39, v48, v39 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 -; GFX10-NEXT: v_mul_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_mul_f32_e32 v49, v50, v49 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 -; GFX10-NEXT: v_mul_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 ; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 ; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_mul_f32_e32 v33, v34, v33 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 -; GFX10-NEXT: v_mul_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_mul_f32_e32 v35, v36, v35 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 -; GFX10-NEXT: v_mul_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_mul_f32_e32 v37, v38, v37 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 -; GFX10-NEXT: v_mul_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 ; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_mul_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_mul_f32_e32 v21, v53, v52 +; GFX10-NEXT: v_mul_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_mul_f32_e32 v22, v55, v54 +; GFX10-NEXT: v_mul_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX10-NEXT: v_mul_f32_e32 v32, v33, v32 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 ; GFX10-NEXT: v_mul_f32_e32 v0, v0, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX10-NEXT: v_mul_f32_e32 v34, v35, v34 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GFX10-NEXT: v_mul_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_mul_f32_e32 v51, v52, v51 -; GFX10-NEXT: v_mul_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_mul_f32_e32 v25, v54, v53 -; GFX10-NEXT: v_mul_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_mul_f32_e32 v24, v64, v55 -; GFX10-NEXT: v_mul_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_mul_f32_e32 v23, v66, v65 -; GFX10-NEXT: v_mul_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_mul_f32_e32 v22, v68, v67 -; GFX10-NEXT: v_mul_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_mul_f32_e32 v21, v30, v34 -; GFX10-NEXT: v_mul_f32_e32 v29, v29, v36 -; GFX10-NEXT: v_mul_f32_e32 v28, v28, v38 -; GFX10-NEXT: v_mul_f32_e32 v27, v27, v48 -; GFX10-NEXT: v_mul_f32_e32 v26, v26, v50 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 +; GFX10-NEXT: v_mul_f32_e32 v36, v37, v36 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 ; GFX10-NEXT: v_mul_f32_e32 v2, v2, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 +; GFX10-NEXT: v_mul_f32_e32 v38, v39, v38 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GFX10-NEXT: v_mul_f32_e32 v3, v3, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 +; GFX10-NEXT: v_mul_f32_e32 v48, v49, v48 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX10-NEXT: v_mul_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 -; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX10-NEXT: v_mul_f32_e32 v50, v51, v50 +; GFX10-NEXT: v_mul_f32_e32 v23, v65, v64 +; GFX10-NEXT: v_mul_f32_e32 v8, v8, v24 +; GFX10-NEXT: v_mul_f32_e32 v24, v67, v66 +; GFX10-NEXT: v_mul_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_mul_f32_e32 v25, v33, v68 +; GFX10-NEXT: v_mul_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_mul_f32_e32 v16, v35, v16 +; GFX10-NEXT: v_mul_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_mul_f32_e32 v17, v37, v17 +; GFX10-NEXT: v_mul_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_mul_f32_e32 v18, v39, v18 +; GFX10-NEXT: v_mul_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_mul_f32_e32 v19, v49, v19 +; GFX10-NEXT: v_mul_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX10-NEXT: v_mul_f32_e32 v16, v32, v16 -; GFX10-NEXT: v_mul_f32_e32 v15, v15, v17 -; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 +; GFX10-NEXT: v_mul_f32_e32 v20, v20, v21 +; GFX10-NEXT: v_mul_f32_e32 v15, v15, v22 +; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_fmul_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 -; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX11-NEXT: v_dual_mul_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 -; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 +; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 +; GFX11-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX11-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 -; GFX11-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_dual_mul_f32 v2, v2, v18 :: v_dual_mul_f32 v3, v3, v19 -; GFX11-NEXT: v_dual_mul_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 -; GFX11-NEXT: v_dual_mul_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_mul_f32_e32 v6, v6, v22 -; GFX11-NEXT: v_dual_mul_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 +; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mul_f32_e32 v10, v10, v26 -; GFX11-NEXT: v_mul_f32_e32 v26, v52, v51 -; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX11-NEXT: v_mul_f32_e32 v25, v54, v53 -; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_mul_f32_e32 v24, v64, v55 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX11-NEXT: v_mul_f32_e32 v7, v7, v23 -; GFX11-NEXT: v_mul_f32_e32 v23, v66, v65 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 -; GFX11-NEXT: v_dual_mul_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 -; GFX11-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 -; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX11-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_mul_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX11-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 ; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_mul_f32_e32 v37, v86, v85 -; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_dual_mul_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 +; GFX11-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_mul_f32_e32 v4, v4, v20 +; GFX11-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_mul_f32 v9, v9, v25 +; GFX11-NEXT: v_mul_f32_e32 v25, v69, v68 +; GFX11-NEXT: v_dual_mul_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 +; GFX11-NEXT: v_mul_f32_e32 v27, v81, v80 +; GFX11-NEXT: v_mul_f32_e32 v12, v12, v28 +; GFX11-NEXT: v_dual_mul_f32 v28, v83, v82 :: v_dual_mul_f32 v29, v85, v84 +; GFX11-NEXT: v_dual_mul_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_mul_f32_e32 v22, v55, v54 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX11-NEXT: v_mul_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33 -; GFX11-NEXT: v_dual_mul_f32 v34, v80, v71 :: v_dual_mul_f32 v35, v82, v81 -; GFX11-NEXT: v_mul_f32_e32 v36, v84, v83 -; GFX11-NEXT: v_dual_mul_f32 v16, v32, v16 :: v_dual_mul_f32 v15, v15, v17 -; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX11-NEXT: v_dual_mul_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_mul_f32_e32 v23, v65, v64 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_dual_mul_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_mul_f32_e32 v2, v2, v18 +; GFX11-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 +; GFX11-NEXT: v_mul_f32_e32 v18, v39, v38 +; GFX11-NEXT: v_dual_mul_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_mul_f32_e32 v19, v49, v48 +; GFX11-NEXT: v_mul_f32_e32 v17, v37, v36 +; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX11-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_mul_f32_e32 v21, v53, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v16 +; GFX11-NEXT: v_mul_f32_e32 v16, v35, v34 +; GFX11-NEXT: v_mul_f32_e32 v32, v33, v32 +; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 +; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 +; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 +; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_mul_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_mul_f32_e32 v15, v15, v17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = fmul <32 x bfloat> %a, %b @@ -14712,480 +14686,483 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_minnum_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_min_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_min_f32_e32 v30, v14, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_min_f32_e32 v14, v32, v14 -; GFX8-NEXT: v_min_f32_e32 v13, v13, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_min_f32_e32 v29, v32, v29 -; GFX8-NEXT: v_min_f32_e32 v12, v12, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_min_f32_e32 v28, v32, v28 -; GFX8-NEXT: v_min_f32_e32 v11, v11, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_min_f32_e32 v27, v32, v27 -; GFX8-NEXT: v_min_f32_e32 v10, v10, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_min_f32_e32 v26, v32, v26 -; GFX8-NEXT: v_min_f32_e32 v9, v9, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_min_f32_e32 v8, v8, v24 -; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX8-NEXT: v_min_f32_e32 v25, v32, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_min_f32_e32 v32, v32, v33 -; GFX8-NEXT: v_min_f32_e32 v15, v15, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_min_f32_e32 v24, v33, v24 -; GFX8-NEXT: v_min_f32_e32 v7, v7, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_min_f32_e32 v23, v33, v23 -; GFX8-NEXT: v_min_f32_e32 v6, v6, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_min_f32_e32 v22, v33, v22 -; GFX8-NEXT: v_min_f32_e32 v5, v5, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_min_f32_e32 v21, v33, v21 -; GFX8-NEXT: v_min_f32_e32 v4, v4, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_min_f32_e32 v20, v33, v20 -; GFX8-NEXT: v_min_f32_e32 v3, v3, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_min_f32_e32 v19, v33, v19 -; GFX8-NEXT: v_min_f32_e32 v2, v2, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX8-NEXT: v_min_f32_e32 v18, v33, v18 -; GFX8-NEXT: v_min_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 ; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX8-NEXT: v_min_f32_e32 v0, v0, v16 -; GFX8-NEXT: v_min_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_min_f32_e32 v31, v32, v31 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_min_f32_e32 v1, v1, v17 +; GFX8-NEXT: v_min_f32_e32 v16, v31, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX8-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_min_f32_e32 v2, v2, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX8-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_min_f32_e32 v3, v3, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX8-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_min_f32_e32 v4, v4, v17 +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_min_f32_e32 v5, v5, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_min_f32_e32 v6, v6, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_min_f32_e32 v7, v7, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX8-NEXT: v_min_f32_e32 v8, v8, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_min_f32_e32 v9, v9, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_min_f32_e32 v10, v10, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_min_f32_e32 v11, v11, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_min_f32_e32 v12, v12, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_min_f32_e32 v13, v13, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX8-NEXT: v_min_f32_e32 v14, v14, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX8-NEXT: v_min_f32_e32 v15, v15, v17 +; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 -; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minnum_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX9-NEXT: v_min_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_min_f32_e32 v14, v14, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_min_f32_e32 v30, v32, v30 -; GFX9-NEXT: v_min_f32_e32 v13, v13, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_min_f32_e32 v29, v32, v29 -; GFX9-NEXT: v_min_f32_e32 v12, v12, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_min_f32_e32 v28, v32, v28 -; GFX9-NEXT: v_min_f32_e32 v11, v11, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_min_f32_e32 v27, v32, v27 -; GFX9-NEXT: v_min_f32_e32 v10, v10, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_min_f32_e32 v26, v32, v26 -; GFX9-NEXT: v_min_f32_e32 v9, v9, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_min_f32_e32 v8, v8, v24 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX9-NEXT: v_min_f32_e32 v25, v32, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_min_f32_e32 v0, v0, v16 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 -; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 -; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 -; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 -; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 -; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 -; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_min_f32_e32 v32, v32, v33 -; GFX9-NEXT: v_min_f32_e32 v15, v15, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_min_f32_e32 v24, v33, v24 -; GFX9-NEXT: v_min_f32_e32 v7, v7, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_min_f32_e32 v23, v33, v23 -; GFX9-NEXT: v_min_f32_e32 v6, v6, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_min_f32_e32 v22, v33, v22 -; GFX9-NEXT: v_min_f32_e32 v5, v5, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_min_f32_e32 v21, v33, v21 -; GFX9-NEXT: v_min_f32_e32 v4, v4, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_min_f32_e32 v20, v33, v20 -; GFX9-NEXT: v_min_f32_e32 v3, v3, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_min_f32_e32 v19, v33, v19 -; GFX9-NEXT: v_min_f32_e32 v2, v2, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 +; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_min_f32_e32 v18, v33, v18 +; GFX9-NEXT: v_min_f32_e32 v16, v31, v16 ; GFX9-NEXT: v_min_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX9-NEXT: v_min_f32_e32 v17, v33, v17 -; GFX9-NEXT: v_min_f32_e32 v0, v0, v16 -; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 -; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 -; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 -; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 -; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 -; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 -; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 -; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 -; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_min_f32_e32 v2, v2, v17 +; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_min_f32_e32 v3, v3, v17 +; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_min_f32_e32 v4, v4, v17 +; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_min_f32_e32 v5, v5, v17 +; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_min_f32_e32 v6, v6, v17 +; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_min_f32_e32 v7, v7, v17 +; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_min_f32_e32 v8, v8, v17 +; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_min_f32_e32 v9, v9, v17 +; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_min_f32_e32 v10, v10, v17 +; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_min_f32_e32 v11, v11, v17 +; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_min_f32_e32 v12, v12, v17 +; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_min_f32_e32 v13, v13, v17 +; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_min_f32_e32 v14, v14, v17 +; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 +; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_min_f32_e32 v15, v15, v17 +; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minnum_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX10-NEXT: v_min_f32_e32 v39, v48, v39 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 -; GFX10-NEXT: v_min_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_min_f32_e32 v49, v50, v49 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 -; GFX10-NEXT: v_min_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 ; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 ; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_min_f32_e32 v33, v34, v33 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 -; GFX10-NEXT: v_min_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_min_f32_e32 v35, v36, v35 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 -; GFX10-NEXT: v_min_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_min_f32_e32 v37, v38, v37 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 -; GFX10-NEXT: v_min_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 ; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_min_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_min_f32_e32 v21, v53, v52 +; GFX10-NEXT: v_min_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_min_f32_e32 v22, v55, v54 +; GFX10-NEXT: v_min_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX10-NEXT: v_min_f32_e32 v32, v33, v32 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 ; GFX10-NEXT: v_min_f32_e32 v0, v0, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX10-NEXT: v_min_f32_e32 v34, v35, v34 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GFX10-NEXT: v_min_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_min_f32_e32 v51, v52, v51 -; GFX10-NEXT: v_min_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_min_f32_e32 v25, v54, v53 -; GFX10-NEXT: v_min_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_min_f32_e32 v24, v64, v55 -; GFX10-NEXT: v_min_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_min_f32_e32 v23, v66, v65 -; GFX10-NEXT: v_min_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_min_f32_e32 v22, v68, v67 -; GFX10-NEXT: v_min_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_min_f32_e32 v21, v30, v34 -; GFX10-NEXT: v_min_f32_e32 v29, v29, v36 -; GFX10-NEXT: v_min_f32_e32 v28, v28, v38 -; GFX10-NEXT: v_min_f32_e32 v27, v27, v48 -; GFX10-NEXT: v_min_f32_e32 v26, v26, v50 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 +; GFX10-NEXT: v_min_f32_e32 v36, v37, v36 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 ; GFX10-NEXT: v_min_f32_e32 v2, v2, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 +; GFX10-NEXT: v_min_f32_e32 v38, v39, v38 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GFX10-NEXT: v_min_f32_e32 v3, v3, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 +; GFX10-NEXT: v_min_f32_e32 v48, v49, v48 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX10-NEXT: v_min_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 -; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX10-NEXT: v_min_f32_e32 v50, v51, v50 +; GFX10-NEXT: v_min_f32_e32 v23, v65, v64 +; GFX10-NEXT: v_min_f32_e32 v8, v8, v24 +; GFX10-NEXT: v_min_f32_e32 v24, v67, v66 +; GFX10-NEXT: v_min_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_min_f32_e32 v25, v33, v68 +; GFX10-NEXT: v_min_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_min_f32_e32 v16, v35, v16 +; GFX10-NEXT: v_min_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_min_f32_e32 v17, v37, v17 +; GFX10-NEXT: v_min_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_min_f32_e32 v18, v39, v18 +; GFX10-NEXT: v_min_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_min_f32_e32 v19, v49, v19 +; GFX10-NEXT: v_min_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX10-NEXT: v_min_f32_e32 v16, v32, v16 -; GFX10-NEXT: v_min_f32_e32 v15, v15, v17 -; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 +; GFX10-NEXT: v_min_f32_e32 v20, v20, v21 +; GFX10-NEXT: v_min_f32_e32 v15, v15, v22 +; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minnum_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 -; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX11-NEXT: v_dual_min_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 -; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 +; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 +; GFX11-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX11-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 -; GFX11-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_dual_min_f32 v2, v2, v18 :: v_dual_min_f32 v3, v3, v19 -; GFX11-NEXT: v_dual_min_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 -; GFX11-NEXT: v_dual_min_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_min_f32_e32 v6, v6, v22 -; GFX11-NEXT: v_dual_min_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 +; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_min_f32_e32 v10, v10, v26 -; GFX11-NEXT: v_min_f32_e32 v26, v52, v51 -; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX11-NEXT: v_min_f32_e32 v25, v54, v53 -; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_min_f32_e32 v24, v64, v55 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX11-NEXT: v_min_f32_e32 v7, v7, v23 -; GFX11-NEXT: v_min_f32_e32 v23, v66, v65 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 -; GFX11-NEXT: v_dual_min_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 -; GFX11-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 -; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX11-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_min_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX11-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 ; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_min_f32_e32 v37, v86, v85 -; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_dual_min_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 +; GFX11-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_min_f32_e32 v4, v4, v20 +; GFX11-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_min_f32 v9, v9, v25 +; GFX11-NEXT: v_min_f32_e32 v25, v69, v68 +; GFX11-NEXT: v_dual_min_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 +; GFX11-NEXT: v_min_f32_e32 v27, v81, v80 +; GFX11-NEXT: v_min_f32_e32 v12, v12, v28 +; GFX11-NEXT: v_dual_min_f32 v28, v83, v82 :: v_dual_min_f32 v29, v85, v84 +; GFX11-NEXT: v_dual_min_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_min_f32_e32 v22, v55, v54 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX11-NEXT: v_min_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33 -; GFX11-NEXT: v_dual_min_f32 v34, v80, v71 :: v_dual_min_f32 v35, v82, v81 -; GFX11-NEXT: v_min_f32_e32 v36, v84, v83 -; GFX11-NEXT: v_dual_min_f32 v16, v32, v16 :: v_dual_min_f32 v15, v15, v17 -; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX11-NEXT: v_dual_min_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_min_f32_e32 v23, v65, v64 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_dual_min_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_min_f32_e32 v2, v2, v18 +; GFX11-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 +; GFX11-NEXT: v_min_f32_e32 v18, v39, v38 +; GFX11-NEXT: v_dual_min_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_min_f32_e32 v19, v49, v48 +; GFX11-NEXT: v_min_f32_e32 v17, v37, v36 +; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX11-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_min_f32_e32 v21, v53, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 +; GFX11-NEXT: v_min_f32_e32 v0, v0, v16 +; GFX11-NEXT: v_min_f32_e32 v16, v35, v34 +; GFX11-NEXT: v_min_f32_e32 v32, v33, v32 +; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 +; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 +; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 +; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_min_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_min_f32_e32 v15, v15, v17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = call <32 x bfloat> @llvm.minnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) @@ -16836,480 +16813,483 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_maxnum_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_max_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_max_f32_e32 v30, v14, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_max_f32_e32 v14, v32, v14 -; GFX8-NEXT: v_max_f32_e32 v13, v13, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_max_f32_e32 v29, v32, v29 -; GFX8-NEXT: v_max_f32_e32 v12, v12, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_max_f32_e32 v28, v32, v28 -; GFX8-NEXT: v_max_f32_e32 v11, v11, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_max_f32_e32 v27, v32, v27 -; GFX8-NEXT: v_max_f32_e32 v10, v10, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_max_f32_e32 v26, v32, v26 -; GFX8-NEXT: v_max_f32_e32 v9, v9, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_max_f32_e32 v8, v8, v24 -; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX8-NEXT: v_max_f32_e32 v25, v32, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX8-NEXT: v_max_f32_e32 v32, v32, v33 -; GFX8-NEXT: v_max_f32_e32 v15, v15, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_max_f32_e32 v24, v33, v24 -; GFX8-NEXT: v_max_f32_e32 v7, v7, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_max_f32_e32 v23, v33, v23 -; GFX8-NEXT: v_max_f32_e32 v6, v6, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_max_f32_e32 v22, v33, v22 -; GFX8-NEXT: v_max_f32_e32 v5, v5, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_max_f32_e32 v21, v33, v21 -; GFX8-NEXT: v_max_f32_e32 v4, v4, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_max_f32_e32 v20, v33, v20 -; GFX8-NEXT: v_max_f32_e32 v3, v3, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_max_f32_e32 v19, v33, v19 -; GFX8-NEXT: v_max_f32_e32 v2, v2, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX8-NEXT: v_max_f32_e32 v18, v33, v18 -; GFX8-NEXT: v_max_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 ; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX8-NEXT: v_max_f32_e32 v0, v0, v16 -; GFX8-NEXT: v_max_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_max_f32_e32 v31, v32, v31 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_max_f32_e32 v1, v1, v17 +; GFX8-NEXT: v_max_f32_e32 v16, v31, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX8-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_max_f32_e32 v2, v2, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX8-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_max_f32_e32 v3, v3, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX8-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_max_f32_e32 v4, v4, v17 +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_max_f32_e32 v5, v5, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_max_f32_e32 v6, v6, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_max_f32_e32 v7, v7, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX8-NEXT: v_max_f32_e32 v8, v8, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_max_f32_e32 v9, v9, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_max_f32_e32 v10, v10, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_max_f32_e32 v11, v11, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_max_f32_e32 v12, v12, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_max_f32_e32 v13, v13, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX8-NEXT: v_max_f32_e32 v14, v14, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX8-NEXT: v_max_f32_e32 v15, v15, v17 +; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 -; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maxnum_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 -; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX9-NEXT: v_max_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_max_f32_e32 v14, v14, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_max_f32_e32 v30, v32, v30 -; GFX9-NEXT: v_max_f32_e32 v13, v13, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_max_f32_e32 v29, v32, v29 -; GFX9-NEXT: v_max_f32_e32 v12, v12, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 -; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_max_f32_e32 v28, v32, v28 -; GFX9-NEXT: v_max_f32_e32 v11, v11, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 -; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_max_f32_e32 v27, v32, v27 -; GFX9-NEXT: v_max_f32_e32 v10, v10, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 -; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_max_f32_e32 v26, v32, v26 -; GFX9-NEXT: v_max_f32_e32 v9, v9, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_max_f32_e32 v8, v8, v24 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 -; GFX9-NEXT: v_max_f32_e32 v25, v32, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_max_f32_e32 v0, v0, v16 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 -; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 -; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 -; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 -; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 -; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 -; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 -; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX9-NEXT: v_max_f32_e32 v32, v32, v33 -; GFX9-NEXT: v_max_f32_e32 v15, v15, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 -; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_max_f32_e32 v24, v33, v24 -; GFX9-NEXT: v_max_f32_e32 v7, v7, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 -; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_max_f32_e32 v23, v33, v23 -; GFX9-NEXT: v_max_f32_e32 v6, v6, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 -; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_max_f32_e32 v22, v33, v22 -; GFX9-NEXT: v_max_f32_e32 v5, v5, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 -; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_max_f32_e32 v21, v33, v21 -; GFX9-NEXT: v_max_f32_e32 v4, v4, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 -; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_max_f32_e32 v20, v33, v20 -; GFX9-NEXT: v_max_f32_e32 v3, v3, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_max_f32_e32 v19, v33, v19 -; GFX9-NEXT: v_max_f32_e32 v2, v2, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 +; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_max_f32_e32 v18, v33, v18 +; GFX9-NEXT: v_max_f32_e32 v16, v31, v16 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX9-NEXT: v_max_f32_e32 v17, v33, v17 -; GFX9-NEXT: v_max_f32_e32 v0, v0, v16 -; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 -; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 -; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 -; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 -; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 -; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 -; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 -; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 -; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_max_f32_e32 v2, v2, v17 +; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_max_f32_e32 v3, v3, v17 +; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_max_f32_e32 v4, v4, v17 +; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_max_f32_e32 v5, v5, v17 +; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_max_f32_e32 v6, v6, v17 +; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_max_f32_e32 v7, v7, v17 +; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_max_f32_e32 v8, v8, v17 +; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_max_f32_e32 v9, v9, v17 +; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_max_f32_e32 v10, v10, v17 +; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_max_f32_e32 v11, v11, v17 +; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_max_f32_e32 v12, v12, v17 +; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_max_f32_e32 v13, v13, v17 +; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX9-NEXT: v_max_f32_e32 v14, v14, v17 +; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 +; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX9-NEXT: v_max_f32_e32 v15, v15, v17 +; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maxnum_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 +; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_max_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_max_f32_e32 v21, v53, v52 +; GFX10-NEXT: v_max_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_max_f32_e32 v22, v55, v54 +; GFX10-NEXT: v_max_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX10-NEXT: v_max_f32_e32 v32, v33, v32 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 ; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX10-NEXT: v_max_f32_e32 v0, v0, v16 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 +; GFX10-NEXT: v_max_f32_e32 v34, v35, v34 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX10-NEXT: v_max_f32_e32 v1, v1, v17 +; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 +; GFX10-NEXT: v_max_f32_e32 v36, v37, v36 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 ; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 ; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX10-NEXT: v_max_f32_e32 v39, v48, v39 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 -; GFX10-NEXT: v_max_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_max_f32_e32 v49, v50, v49 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 -; GFX10-NEXT: v_max_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX10-NEXT: v_max_f32_e32 v2, v2, v18 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 +; GFX10-NEXT: v_max_f32_e32 v38, v39, v38 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX10-NEXT: v_max_f32_e32 v3, v3, v19 +; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 +; GFX10-NEXT: v_max_f32_e32 v48, v49, v48 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX10-NEXT: v_max_f32_e32 v4, v4, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 ; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_max_f32_e32 v33, v34, v33 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 -; GFX10-NEXT: v_max_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_max_f32_e32 v35, v36, v35 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 -; GFX10-NEXT: v_max_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_max_f32_e32 v37, v38, v37 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 -; GFX10-NEXT: v_max_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_max_f32_e32 v0, v0, v16 -; GFX10-NEXT: v_max_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_max_f32_e32 v51, v52, v51 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_max_f32_e32 v25, v54, v53 +; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX10-NEXT: v_max_f32_e32 v50, v51, v50 +; GFX10-NEXT: v_max_f32_e32 v23, v65, v64 ; GFX10-NEXT: v_max_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_max_f32_e32 v24, v64, v55 -; GFX10-NEXT: v_max_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_max_f32_e32 v23, v66, v65 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_max_f32_e32 v22, v68, v67 -; GFX10-NEXT: v_max_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_max_f32_e32 v21, v30, v34 -; GFX10-NEXT: v_max_f32_e32 v29, v29, v36 -; GFX10-NEXT: v_max_f32_e32 v28, v28, v38 -; GFX10-NEXT: v_max_f32_e32 v27, v27, v48 -; GFX10-NEXT: v_max_f32_e32 v26, v26, v50 -; GFX10-NEXT: v_max_f32_e32 v2, v2, v18 -; GFX10-NEXT: v_max_f32_e32 v3, v3, v19 -; GFX10-NEXT: v_max_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 -; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX10-NEXT: v_max_f32_e32 v24, v67, v66 +; GFX10-NEXT: v_max_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_max_f32_e32 v25, v33, v68 +; GFX10-NEXT: v_max_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_max_f32_e32 v16, v35, v16 +; GFX10-NEXT: v_max_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_max_f32_e32 v17, v37, v17 +; GFX10-NEXT: v_max_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_max_f32_e32 v18, v39, v18 +; GFX10-NEXT: v_max_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_max_f32_e32 v19, v49, v19 +; GFX10-NEXT: v_max_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX10-NEXT: v_max_f32_e32 v16, v32, v16 -; GFX10-NEXT: v_max_f32_e32 v15, v15, v17 -; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 +; GFX10-NEXT: v_max_f32_e32 v20, v20, v21 +; GFX10-NEXT: v_max_f32_e32 v15, v15, v22 +; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maxnum_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 -; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 -; GFX11-NEXT: v_dual_max_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 -; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 -; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 +; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 +; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 +; GFX11-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 -; GFX11-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 -; GFX11-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_dual_max_f32 v2, v2, v18 :: v_dual_max_f32 v3, v3, v19 -; GFX11-NEXT: v_dual_max_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 -; GFX11-NEXT: v_dual_max_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_max_f32_e32 v6, v6, v22 -; GFX11-NEXT: v_dual_max_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 +; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_max_f32_e32 v10, v10, v26 -; GFX11-NEXT: v_max_f32_e32 v26, v52, v51 -; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 -; GFX11-NEXT: v_max_f32_e32 v25, v54, v53 -; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_max_f32_e32 v24, v64, v55 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 -; GFX11-NEXT: v_max_f32_e32 v7, v7, v23 -; GFX11-NEXT: v_max_f32_e32 v23, v66, v65 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 -; GFX11-NEXT: v_dual_max_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 -; GFX11-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 -; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 -; GFX11-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_max_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 +; GFX11-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 ; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_max_f32_e32 v37, v86, v85 -; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_dual_max_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 +; GFX11-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_max_f32_e32 v4, v4, v20 +; GFX11-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_max_f32 v9, v9, v25 +; GFX11-NEXT: v_max_f32_e32 v25, v69, v68 +; GFX11-NEXT: v_dual_max_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 +; GFX11-NEXT: v_max_f32_e32 v27, v81, v80 +; GFX11-NEXT: v_max_f32_e32 v12, v12, v28 +; GFX11-NEXT: v_dual_max_f32 v28, v83, v82 :: v_dual_max_f32 v29, v85, v84 +; GFX11-NEXT: v_dual_max_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_max_f32_e32 v22, v55, v54 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX11-NEXT: v_max_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33 -; GFX11-NEXT: v_dual_max_f32 v34, v80, v71 :: v_dual_max_f32 v35, v82, v81 -; GFX11-NEXT: v_max_f32_e32 v36, v84, v83 -; GFX11-NEXT: v_dual_max_f32 v16, v32, v16 :: v_dual_max_f32 v15, v15, v17 -; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 +; GFX11-NEXT: v_dual_max_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_max_f32_e32 v23, v65, v64 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_dual_max_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_max_f32_e32 v2, v2, v18 +; GFX11-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 +; GFX11-NEXT: v_max_f32_e32 v18, v39, v38 +; GFX11-NEXT: v_dual_max_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_max_f32_e32 v19, v49, v48 +; GFX11-NEXT: v_max_f32_e32 v17, v37, v36 +; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX11-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_max_f32_e32 v21, v53, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 +; GFX11-NEXT: v_max_f32_e32 v0, v0, v16 +; GFX11-NEXT: v_max_f32_e32 v16, v35, v34 +; GFX11-NEXT: v_max_f32_e32 v32, v33, v32 +; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 +; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 +; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 +; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_max_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_max_f32_e32 v15, v15, v17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = call <32 x bfloat> @llvm.maxnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) @@ -25401,38 +25381,36 @@ define <3 x bfloat> @v_select_v3bf16(i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b) ; GCN-LABEL: v_select_v3bf16: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 ; GCN-NEXT: v_and_b32_e32 v0, 1, v0 +; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GCN-NEXT: v_alignbit_b32 v2, v5, v4, 16 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GCN-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: v_select_v3bf16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GFX7-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v5 +; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX7-NEXT: v_alignbit_b32 v2, v2, v4, 16 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v6 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; @@ -25441,14 +25419,8 @@ define <3 x bfloat> @v_select_v3bf16(i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_mov_b32_e32 v1, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_select_v3bf16: @@ -25485,47 +25457,43 @@ define <4 x bfloat> @v_select_v4bf16(i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b) ; GCN-LABEL: v_select_v4bf16: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 ; GCN-NEXT: v_and_b32_e32 v0, 1, v0 +; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GCN-NEXT: v_alignbit_b32 v2, v6, v5, 16 +; GCN-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GCN-NEXT: v_alignbit_b32 v4, v8, v7, 16 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GCN-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc -; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: v_select_v4bf16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7 ; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX7-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v6 +; GFX7-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v8 +; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX7-NEXT: v_alignbit_b32 v2, v2, v5, 16 +; GFX7-NEXT: v_alignbit_b32 v4, v4, v7, 16 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_select_v4bf16: @@ -25533,18 +25501,8 @@ define <4 x bfloat> @v_select_v4bf16(i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v5 -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_select_v4bf16: @@ -25581,63 +25539,57 @@ define <6 x bfloat> @v_select_v6bf16(i1 %cond, <6 x bfloat> %a, <6 x bfloat> %b) ; GCN-LABEL: v_select_v6bf16: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 ; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 ; GCN-NEXT: v_and_b32_e32 v0, 1, v0 +; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GCN-NEXT: v_alignbit_b32 v2, v8, v7, 16 +; GCN-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GCN-NEXT: v_alignbit_b32 v4, v10, v9, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v5, 16 +; GCN-NEXT: v_alignbit_b32 v6, v12, v11, 16 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GCN-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc -; GCN-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc -; GCN-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc -; GCN-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v6 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: v_select_v6bf16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7 ; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v9 ; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v11 ; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX7-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v8 +; GFX7-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v10 +; GFX7-NEXT: v_alignbit_b32 v5, v6, v5, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v12 +; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX7-NEXT: v_alignbit_b32 v2, v2, v7, 16 +; GFX7-NEXT: v_alignbit_b32 v4, v4, v9, 16 +; GFX7-NEXT: v_alignbit_b32 v6, v6, v11, 16 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GFX7-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6 +; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_select_v6bf16: @@ -25645,24 +25597,9 @@ define <6 x bfloat> @v_select_v6bf16(i1 %cond, <6 x bfloat> %a, <6 x bfloat> %b) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v6 -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7 -; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_select_v6bf16: @@ -25702,79 +25639,71 @@ define <8 x bfloat> @v_select_v8bf16(i1 %cond, <8 x bfloat> %a, <8 x bfloat> %b) ; GCN-LABEL: v_select_v8bf16: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 ; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 ; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 ; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 ; GCN-NEXT: v_and_b32_e32 v0, 1, v0 +; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GCN-NEXT: v_alignbit_b32 v2, v10, v9, 16 +; GCN-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GCN-NEXT: v_alignbit_b32 v4, v12, v11, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v5, 16 +; GCN-NEXT: v_alignbit_b32 v6, v14, v13, 16 +; GCN-NEXT: v_alignbit_b32 v7, v8, v7, 16 +; GCN-NEXT: v_alignbit_b32 v8, v16, v15, 16 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GCN-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc -; GCN-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc -; GCN-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc -; GCN-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc -; GCN-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc -; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GCN-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v6 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v8 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: v_select_v8bf16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v9 ; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v11 ; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v13 ; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v15 ; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX7-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v10 +; GFX7-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v12 +; GFX7-NEXT: v_alignbit_b32 v5, v6, v5, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v14 +; GFX7-NEXT: v_alignbit_b32 v7, v8, v7, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v16 +; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX7-NEXT: v_alignbit_b32 v2, v2, v9, 16 +; GFX7-NEXT: v_alignbit_b32 v4, v4, v11, 16 +; GFX7-NEXT: v_alignbit_b32 v6, v6, v13, 16 +; GFX7-NEXT: v_alignbit_b32 v8, v8, v15, 16 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GFX7-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6 +; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v8 +; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_select_v8bf16: @@ -25782,30 +25711,10 @@ define <8 x bfloat> @v_select_v8bf16(i1 %cond, <8 x bfloat> %a, <8 x bfloat> %b) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v4 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v8 -; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v9 -; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v8, v4, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_select_v8bf16: @@ -25847,151 +25756,135 @@ define <16 x bfloat> @v_select_v16bf16(i1 %cond, <16 x bfloat> %a, <16 x bfloat> ; GCN-LABEL: v_select_v16bf16: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v0, 1, v0 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v14 -; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v30 -; GCN-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v13 -; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v29 -; GCN-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v12 -; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v28 -; GCN-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v11 -; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v27 -; GCN-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v10 -; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v26 -; GCN-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v9 -; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v25 -; GCN-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v8 -; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v24 -; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v7 -; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v23 -; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v18 +; GCN-NEXT: v_alignbit_b32 v2, v2, v17, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v20 +; GCN-NEXT: v_alignbit_b32 v4, v4, v19, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_alignbit_b32 v5, v6, v5, 16 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v22 -; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v5 -; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v21 -; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc -; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 +; GCN-NEXT: v_alignbit_b32 v6, v6, v21, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v7, v8, v7, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v24 +; GCN-NEXT: v_alignbit_b32 v8, v8, v23, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_alignbit_b32 v9, v10, v9, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v26 +; GCN-NEXT: v_alignbit_b32 v10, v10, v25, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v30 ; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v4 -; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v20 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc -; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 -; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v17 -; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v18 -; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v19 -; GCN-NEXT: v_cndmask_b32_e32 v3, v18, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v17, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GCN-NEXT: v_alignbit_b32 v11, v12, v11, 16 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:4 +; GCN-NEXT: v_alignbit_b32 v12, v17, v27, 16 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 +; GCN-NEXT: v_and_b32_e32 v0, 1, v0 +; GCN-NEXT: v_alignbit_b32 v13, v14, v13, 16 +; GCN-NEXT: v_alignbit_b32 v14, v18, v29, 16 +; GCN-NEXT: v_alignbit_b32 v15, v16, v15, 16 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v13, v14, v13, vcc +; GCN-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc +; GCN-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc +; GCN-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v6 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v8 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v9 -; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v10 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v11 -; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v19 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v20 -; GCN-NEXT: v_cndmask_b32_e32 v16, v14, v16, vcc -; GCN-NEXT: v_cndmask_b32_e32 v14, v17, v15, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v16 +; GCN-NEXT: v_alignbit_b32 v14, v14, v17, 16 +; GCN-NEXT: v_cndmask_b32_e32 v15, v14, v15, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: v_select_v16bf16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX7-NEXT: v_alignbit_b32 v11, v12, v11, 16 +; GFX7-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:4 +; GFX7-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v18 +; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s32 +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX7-NEXT: v_alignbit_b32 v7, v8, v7, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v24 ; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX7-NEXT: v_alignbit_b32 v3, v4, v3, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v20 +; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX7-NEXT: v_alignbit_b32 v8, v8, v23, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v14 -; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v30 -; GFX7-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v13 -; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v29 -; GFX7-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v12 -; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v28 -; GFX7-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v11 -; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v27 -; GFX7-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v10 -; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v26 -; GFX7-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v9 -; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v25 -; GFX7-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v8 -; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v24 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v7 -; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v23 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v6 +; GFX7-NEXT: v_alignbit_b32 v2, v2, v17, 16 +; GFX7-NEXT: v_alignbit_b32 v4, v4, v19, 16 +; GFX7-NEXT: v_alignbit_b32 v5, v6, v5, 16 ; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v22 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v5 -; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v21 -; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX7-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc -; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc -; GFX7-NEXT: buffer_load_dword v20, off, s[0:3], s32 -; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX7-NEXT: v_alignbit_b32 v9, v10, v9, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v26 +; GFX7-NEXT: v_lshrrev_b32_e32 v17, 16, v28 +; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX7-NEXT: v_lshrrev_b32_e32 v19, 16, v30 ; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc -; GFX7-NEXT: s_waitcnt vmcnt(1) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v16, v0, v16, vcc -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX7-NEXT: v_cndmask_b32_e32 v15, v18, v15, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GFX7-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc +; GFX7-NEXT: v_alignbit_b32 v6, v6, v21, 16 +; GFX7-NEXT: v_alignbit_b32 v10, v10, v25, 16 +; GFX7-NEXT: v_alignbit_b32 v17, v17, v27, 16 +; GFX7-NEXT: v_alignbit_b32 v13, v14, v13, 16 +; GFX7-NEXT: v_alignbit_b32 v14, v19, v29, 16 +; GFX7-NEXT: v_alignbit_b32 v15, v16, v15, 16 +; GFX7-NEXT: v_cndmask_b32_e32 v13, v14, v13, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6 +; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v8 -; GFX7-NEXT: v_lshlrev_b32_e32 v8, 16, v9 -; GFX7-NEXT: v_lshlrev_b32_e32 v9, 16, v10 +; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GFX7-NEXT: v_lshlrev_b32_e32 v10, 16, v11 -; GFX7-NEXT: v_lshlrev_b32_e32 v11, 16, v12 +; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v12 ; GFX7-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX7-NEXT: v_lshlrev_b32_e32 v13, 16, v14 +; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_alignbit_b32 v8, v8, v18, 16 +; GFX7-NEXT: v_cndmask_b32_e32 v15, v8, v15, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v8, 16, v9 +; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 ; GFX7-NEXT: v_lshlrev_b32_e32 v14, 16, v15 -; GFX7-NEXT: v_lshlrev_b32_e32 v15, 16, v16 +; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_select_v16bf16: @@ -25999,54 +25892,14 @@ define <16 x bfloat> @v_select_v16bf16(i1 %cond, <16 x bfloat> %a, <16 x bfloat> ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v7 -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v6 -; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5 -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v4 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v11 -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v12 -; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v13 -; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v14 -; GFX8-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc -; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v16 -; GFX8-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v17 -; GFX8-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v16, v8, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_select_v16bf16: @@ -26098,407 +25951,365 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat> ; GCN-LABEL: v_select_v32bf16: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v4 +; GCN-NEXT: v_alignbit_b32 v2, v2, v3, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v6 +; GCN-NEXT: v_alignbit_b32 v3, v3, v5, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v8 +; GCN-NEXT: v_alignbit_b32 v4, v4, v7, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v10 +; GCN-NEXT: v_alignbit_b32 v5, v5, v9, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v12 +; GCN-NEXT: v_alignbit_b32 v6, v6, v11, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v14 +; GCN-NEXT: v_alignbit_b32 v7, v7, v13, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v16 +; GCN-NEXT: v_alignbit_b32 v8, v8, v15, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v18 +; GCN-NEXT: v_alignbit_b32 v9, v9, v17, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v20 +; GCN-NEXT: v_alignbit_b32 v10, v10, v19, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v22 +; GCN-NEXT: v_alignbit_b32 v11, v11, v21, 16 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:12 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v24 +; GCN-NEXT: v_alignbit_b32 v12, v12, v23, 16 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:8 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v26 +; GCN-NEXT: v_alignbit_b32 v13, v13, v25, 16 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:20 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v28 +; GCN-NEXT: v_alignbit_b32 v14, v14, v27, 16 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:16 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v30 +; GCN-NEXT: v_alignbit_b32 v15, v15, v29, 16 +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:28 ; GCN-NEXT: v_and_b32_e32 v0, 1, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128 -; GCN-NEXT: s_waitcnt vmcnt(2) -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_cndmask_b32_e32 v31, v0, v31, vcc -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v32 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:124 -; GCN-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v30 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:120 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:116 -; GCN-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v28 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:112 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v27 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:108 -; GCN-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v26 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:104 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:100 -; GCN-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v24 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:96 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v23 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:92 -; GCN-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v22 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:88 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v21 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84 -; GCN-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v20 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v19 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:76 -; GCN-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v18 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:72 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v18, v18, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v17 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68 -; GCN-NEXT: v_cndmask_b32_e32 v17, v17, v0, vcc +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:24 +; GCN-NEXT: s_waitcnt vmcnt(5) ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v16 -; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64 -; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v15 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v34 -; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:60 -; GCN-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v14 -; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 +; GCN-NEXT: s_waitcnt vmcnt(4) +; GCN-NEXT: v_alignbit_b32 v0, v0, v17, 16 +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:36 +; GCN-NEXT: s_waitcnt vmcnt(4) +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v18 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_alignbit_b32 v16, v16, v19, 16 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:32 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v20 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v17, v17, v21, 16 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:40 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v22 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v18, v21, v18, 16 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GCN-NEXT: v_cndmask_b32_e32 v33, v33, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v14 -; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:52 -; GCN-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v12 -; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48 +; GCN-NEXT: v_alignbit_b32 v19, v19, v20, 16 +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:56 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v20, v20, v21, 16 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GCN-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v22 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v12 -; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:44 -; GCN-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v10 -; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:40 +; GCN-NEXT: v_alignbit_b32 v21, v21, v23, 16 +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v22, v22, v23, 16 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GCN-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v24 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v10 -; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:36 -; GCN-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v8 -; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32 +; GCN-NEXT: v_alignbit_b32 v23, v23, v25, 16 +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:92 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v24, v24, v25, 16 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GCN-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v26 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v8 -; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28 -; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v6 -; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 +; GCN-NEXT: v_alignbit_b32 v25, v25, v27, 16 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:100 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:96 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v26, v26, v27, 16 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v28 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v6 -; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:20 -; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v4 -; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16 +; GCN-NEXT: v_alignbit_b32 v27, v27, v29, 16 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:112 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 +; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v28, v28, v29, 16 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v30 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v4 -; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12 -; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8 +; GCN-NEXT: v_alignbit_b32 v29, v29, v31, 16 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 +; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_alignbit_b32 v30, v30, v31, 16 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v32 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v2 -; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4 +; GCN-NEXT: v_alignbit_b32 v31, v31, v33, 16 +; GCN-NEXT: v_cndmask_b32_e32 v31, v31, v30, vcc +; GCN-NEXT: v_cndmask_b32_e32 v29, v29, v15, vcc +; GCN-NEXT: v_cndmask_b32_e32 v28, v28, v14, vcc +; GCN-NEXT: v_cndmask_b32_e32 v27, v27, v13, vcc +; GCN-NEXT: v_cndmask_b32_e32 v26, v26, v12, vcc +; GCN-NEXT: v_cndmask_b32_e32 v25, v25, v11, vcc +; GCN-NEXT: v_cndmask_b32_e32 v24, v24, v10, vcc +; GCN-NEXT: v_cndmask_b32_e32 v23, v23, v9, vcc +; GCN-NEXT: v_cndmask_b32_e32 v15, v22, v8, vcc +; GCN-NEXT: v_cndmask_b32_e32 v13, v21, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v11, v20, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v9, v19, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v7, v18, v4, vcc +; GCN-NEXT: v_cndmask_b32_e32 v5, v17, v3, vcc +; GCN-NEXT: v_cndmask_b32_e32 v3, v16, v2, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v6 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v8 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v10 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v9 -; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v11 -; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v14 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v33 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v15 -; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v16 -; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v18 -; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v20 -; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v21 -; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22 -; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v23 -; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v24 -; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v25 -; GCN-NEXT: v_lshlrev_b32_e32 v25, 16, v26 -; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v27 -; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v23 +; GCN-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v24 +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v25 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v26 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v26 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v27 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v28 +; GCN-NEXT: v_and_b32_e32 v27, 0xffff0000, v28 ; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v29 -; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v30 -; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v32 -; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GCN-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v31 +; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: v_select_v32bf16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX7-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v4 +; GFX7-NEXT: v_alignbit_b32 v2, v2, v3, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v6 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v8 +; GFX7-NEXT: v_alignbit_b32 v3, v3, v5, 16 +; GFX7-NEXT: v_alignbit_b32 v4, v4, v7, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v10 +; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v12 +; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v14 +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v16 +; GFX7-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 +; GFX7-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:16 +; GFX7-NEXT: v_alignbit_b32 v6, v6, v11, 16 +; GFX7-NEXT: v_alignbit_b32 v7, v7, v13, 16 +; GFX7-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:24 +; GFX7-NEXT: v_alignbit_b32 v8, v8, v15, 16 +; GFX7-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:40 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72 +; GFX7-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:8 +; GFX7-NEXT: v_alignbit_b32 v5, v5, v9, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v18 +; GFX7-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX7-NEXT: v_alignbit_b32 v9, v9, v17, 16 +; GFX7-NEXT: v_alignbit_b32 v25, v26, v25, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX7-NEXT: v_alignbit_b32 v21, v22, v21, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX7-NEXT: v_alignbit_b32 v29, v30, v29, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX7-NEXT: v_alignbit_b32 v19, v20, v19, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX7-NEXT: v_alignbit_b32 v23, v24, v23, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX7-NEXT: v_alignbit_b32 v27, v28, v27, 16 ; GFX7-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 -; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 -; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128 -; GFX7-NEXT: s_waitcnt vmcnt(2) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: s_waitcnt vmcnt(1) -; GFX7-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX7-NEXT: v_cndmask_b32_e32 v31, v31, v0, vcc -; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 -; GFX7-NEXT: v_lshlrev_b32_e32 v31, 16, v31 -; GFX7-NEXT: s_waitcnt vmcnt(1) -; GFX7-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v30 +; GFX7-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:32 +; GFX7-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56 +; GFX7-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 +; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48 +; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 +; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; GFX7-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX7-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX7-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; GFX7-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v28 +; GFX7-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 +; GFX7-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 ; GFX7-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; GFX7-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v27 -; GFX7-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; GFX7-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v26 -; GFX7-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 -; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128 +; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 +; GFX7-NEXT: s_waitcnt vmcnt(14) +; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX7-NEXT: s_waitcnt vmcnt(12) +; GFX7-NEXT: v_alignbit_b32 v10, v10, v11, 16 +; GFX7-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:20 +; GFX7-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX7-NEXT: s_waitcnt vmcnt(10) ; GFX7-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; GFX7-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX7-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; GFX7-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v24 -; GFX7-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX7-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v23 -; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; GFX7-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v22 -; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 -; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: s_waitcnt vmcnt(8) ; GFX7-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; GFX7-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v21 -; GFX7-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; GFX7-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v20 -; GFX7-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 -; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: s_waitcnt vmcnt(6) +; GFX7-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX7-NEXT: s_waitcnt vmcnt(5) ; GFX7-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; GFX7-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v19 -; GFX7-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v18 -; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v17 -; GFX7-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v16 -; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v15 -; GFX7-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX7-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v14 -; GFX7-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX7-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v13 -; GFX7-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX7-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v12 -; GFX7-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX7-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v11 -; GFX7-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48 +; GFX7-NEXT: s_waitcnt vmcnt(4) +; GFX7-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX7-NEXT: s_waitcnt vmcnt(3) +; GFX7-NEXT: v_lshrrev_b32_e32 v28, 16, v28 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX7-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v10 -; GFX7-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX7-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v9 -; GFX7-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX7-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v8 -; GFX7-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v7 -; GFX7-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32 +; GFX7-NEXT: v_alignbit_b32 v11, v11, v12, 16 +; GFX7-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v6 -; GFX7-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 +; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX7-NEXT: v_alignbit_b32 v12, v12, v13, 16 +; GFX7-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:36 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v5 -; GFX7-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 +; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX7-NEXT: v_alignbit_b32 v13, v13, v14, 16 +; GFX7-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:44 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v4 -; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 +; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX7-NEXT: v_alignbit_b32 v14, v14, v15, 16 +; GFX7-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:52 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v3 -; GFX7-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 +; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX7-NEXT: v_alignbit_b32 v15, v15, v16, 16 +; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 +; GFX7-NEXT: v_cndmask_b32_e32 v15, v15, v6, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v10, 16, v15 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX7-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 +; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX7-NEXT: v_alignbit_b32 v16, v16, v17, 16 +; GFX7-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 +; GFX7-NEXT: v_cndmask_b32_e32 v16, v16, v7, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v7, v13, v4, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v16 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GFX7-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 +; GFX7-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX7-NEXT: v_alignbit_b32 v17, v17, v18, 16 +; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 +; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v8, vcc ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; GFX7-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX7-NEXT: v_alignbit_b32 v18, v18, v31, 16 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80 +; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v9, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v9, v14, v5, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v5, v12, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v2, vcc ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3 -; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6 -; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v7 -; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v8 +; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 ; GFX7-NEXT: v_lshlrev_b32_e32 v8, 16, v9 -; GFX7-NEXT: v_lshlrev_b32_e32 v9, 16, v10 -; GFX7-NEXT: v_lshlrev_b32_e32 v10, 16, v11 -; GFX7-NEXT: v_lshlrev_b32_e32 v11, 16, v12 -; GFX7-NEXT: v_lshlrev_b32_e32 v12, 16, v13 -; GFX7-NEXT: v_lshlrev_b32_e32 v13, 16, v14 -; GFX7-NEXT: v_lshlrev_b32_e32 v14, 16, v15 -; GFX7-NEXT: v_lshlrev_b32_e32 v15, 16, v16 -; GFX7-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX7-NEXT: v_lshlrev_b32_e32 v17, 16, v18 +; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v15 +; GFX7-NEXT: v_lshlrev_b32_e32 v12, 16, v16 +; GFX7-NEXT: v_lshlrev_b32_e32 v14, 16, v17 +; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v17 +; GFX7-NEXT: v_lshlrev_b32_e32 v16, 16, v18 +; GFX7-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_alignbit_b32 v20, v20, v31, 16 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:88 +; GFX7-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc ; GFX7-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; GFX7-NEXT: v_lshlrev_b32_e32 v19, 16, v20 +; GFX7-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_alignbit_b32 v22, v22, v31, 16 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 +; GFX7-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc ; GFX7-NEXT: v_lshlrev_b32_e32 v20, 16, v21 -; GFX7-NEXT: v_lshlrev_b32_e32 v21, 16, v22 +; GFX7-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_alignbit_b32 v24, v24, v31, 16 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:104 +; GFX7-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc ; GFX7-NEXT: v_lshlrev_b32_e32 v22, 16, v23 -; GFX7-NEXT: v_lshlrev_b32_e32 v23, 16, v24 +; GFX7-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_alignbit_b32 v26, v26, v31, 16 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112 +; GFX7-NEXT: v_cndmask_b32_e32 v25, v26, v25, vcc ; GFX7-NEXT: v_lshlrev_b32_e32 v24, 16, v25 -; GFX7-NEXT: v_lshlrev_b32_e32 v25, 16, v26 +; GFX7-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_alignbit_b32 v28, v28, v31, 16 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120 +; GFX7-NEXT: v_cndmask_b32_e32 v27, v28, v27, vcc ; GFX7-NEXT: v_lshlrev_b32_e32 v26, 16, v27 -; GFX7-NEXT: v_lshlrev_b32_e32 v27, 16, v28 +; GFX7-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_alignbit_b32 v30, v30, v31, 16 +; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4 +; GFX7-NEXT: v_cndmask_b32_e32 v29, v30, v29, vcc ; GFX7-NEXT: v_lshlrev_b32_e32 v28, 16, v29 -; GFX7-NEXT: v_lshlrev_b32_e32 v29, 16, v30 -; GFX7-NEXT: v_lshlrev_b32_e32 v30, 16, v32 +; GFX7-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX7-NEXT: v_alignbit_b32 v31, v31, v32, 16 +; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX7-NEXT: v_alignbit_b32 v32, v32, v33, 16 +; GFX7-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v30, 16, v31 +; GFX7-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_select_v32bf16: @@ -26506,106 +26317,26 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat> ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v31, 16, v14 -; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v30 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v29 -; GFX8-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v12 -; GFX8-NEXT: v_lshrrev_b32_e32 v29, 16, v28 -; GFX8-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v11 -; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v27 -; GFX8-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v10 -; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v26 -; GFX8-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v7 -; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v6 -; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5 -; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc -; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 -; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 -; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v20 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v2, vcc +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 +; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:4 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v11, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v13, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v14, vcc ; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_cndmask_b32_e32 v16, v0, v16, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v33, v0, v33, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v15 +; GFX8-NEXT: v_cndmask_b32_e32 v14, v17, v15, vcc ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v15, v32, v15, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v19 -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v20 -; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v21 -; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v22 -; GFX8-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v23 -; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v24 -; GFX8-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v25 -; GFX8-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v26 -; GFX8-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v27 -; GFX8-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v28 -; GFX8-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v29 -; GFX8-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v30 -; GFX8-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v31 -; GFX8-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v32 -; GFX8-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v33 -; GFX8-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e32 v15, v18, v16, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_select_v32bf16: @@ -26689,75 +26420,51 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat> define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat> inreg %b, i32 %c) { ; GCN-LABEL: s_select_v3bf16: ; GCN: ; %bb.0: -; GCN-NEXT: s_lshr_b32 s2, s2, 16 -; GCN-NEXT: s_lshr_b32 s5, s5, 16 ; GCN-NEXT: s_lshr_b32 s1, s1, 16 -; GCN-NEXT: s_lshr_b32 s0, s0, 16 -; GCN-NEXT: s_lshr_b32 s3, s3, 16 -; GCN-NEXT: s_lshr_b32 s4, s4, 16 -; GCN-NEXT: v_mov_b32_e32 v1, s3 -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GCN-NEXT: v_mov_b32_e32 v1, s4 -; GCN-NEXT: v_mov_b32_e32 v2, s1 -; GCN-NEXT: v_mov_b32_e32 v3, s5 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: s_lshr_b32 s0, s4, 16 +; GCN-NEXT: v_mov_b32_e32 v2, s3 +; GCN-NEXT: s_lshr_b32 s2, s2, 16 +; GCN-NEXT: s_lshr_b32 s3, s5, 16 +; GCN-NEXT: v_alignbit_b32 v1, s1, v1, 16 +; GCN-NEXT: v_alignbit_b32 v2, s0, v2, 16 +; GCN-NEXT: v_mov_b32_e32 v3, s3 ; GCN-NEXT: v_mov_b32_e32 v4, s2 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_or_b32_e32 v0, v0, v1 -; GCN-NEXT: v_readfirstlane_b32 s0, v0 -; GCN-NEXT: v_readfirstlane_b32 s1, v2 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_readfirstlane_b32 s0, v1 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 ; GCN-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: s_select_v3bf16: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_lshr_b32 s0, s0, 16 -; GFX7-NEXT: s_lshr_b32 s3, s3, 16 ; GFX7-NEXT: s_lshr_b32 s1, s1, 16 -; GFX7-NEXT: s_lshr_b32 s4, s4, 16 -; GFX7-NEXT: v_mov_b32_e32 v1, s3 -; GFX7-NEXT: v_mov_b32_e32 v2, s0 +; GFX7-NEXT: v_mov_b32_e32 v1, s0 +; GFX7-NEXT: s_lshr_b32 s0, s4, 16 +; GFX7-NEXT: v_mov_b32_e32 v2, s3 +; GFX7-NEXT: v_alignbit_b32 v1, s1, v1, 16 +; GFX7-NEXT: v_alignbit_b32 v2, s0, v2, 16 +; GFX7-NEXT: s_lshr_b32 s0, s2, 16 +; GFX7-NEXT: s_lshr_b32 s1, s5, 16 +; GFX7-NEXT: v_mov_b32_e32 v3, s1 +; GFX7-NEXT: v_mov_b32_e32 v4, s0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX7-NEXT: v_mov_b32_e32 v1, s4 -; GFX7-NEXT: v_mov_b32_e32 v2, s1 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX7-NEXT: s_lshr_b32 s2, s2, 16 -; GFX7-NEXT: s_lshr_b32 s5, s5, 16 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: v_mov_b32_e32 v2, s2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX7-NEXT: v_readfirstlane_b32 s0, v0 -; GFX7-NEXT: v_readfirstlane_b32 s1, v1 +; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_readfirstlane_b32 s0, v1 +; GFX7-NEXT: v_readfirstlane_b32 s1, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_select_v3bf16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_lshr_b32 s4, s0, 16 -; GFX8-NEXT: s_lshr_b32 s5, s2, 16 -; GFX8-NEXT: v_mov_b32_e32 v1, s5 -; GFX8-NEXT: v_mov_b32_e32 v2, s4 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v1, s2 -; GFX8-NEXT: v_mov_b32_e32 v2, s0 -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX8-NEXT: s_lshr_b32 s0, s1, 16 -; GFX8-NEXT: s_lshr_b32 s2, s3, 16 -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_mov_b32_e32 v1, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s3 -; GFX8-NEXT: v_mov_b32_e32 v3, s1 -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1 @@ -26819,88 +26526,54 @@ define amdgpu_ps <2 x i32> @s_select_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat> ; GCN-LABEL: s_select_v4bf16: ; GCN: ; %bb.0: ; GCN-NEXT: s_lshr_b32 s1, s1, 16 -; GCN-NEXT: s_lshr_b32 s5, s5, 16 -; GCN-NEXT: s_lshr_b32 s0, s0, 16 -; GCN-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: s_lshr_b32 s0, s5, 16 +; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: s_lshr_b32 s3, s3, 16 -; GCN-NEXT: s_lshr_b32 s2, s2, 16 -; GCN-NEXT: s_lshr_b32 s6, s6, 16 -; GCN-NEXT: s_lshr_b32 s7, s7, 16 -; GCN-NEXT: v_mov_b32_e32 v1, s6 -; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s2 +; GCN-NEXT: s_lshr_b32 s2, s7, 16 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_alignbit_b32 v1, s1, v1, 16 +; GCN-NEXT: v_alignbit_b32 v2, s0, v2, 16 +; GCN-NEXT: v_alignbit_b32 v3, s3, v3, 16 +; GCN-NEXT: v_alignbit_b32 v4, s2, v4, 16 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GCN-NEXT: v_mov_b32_e32 v1, s7 -; GCN-NEXT: v_mov_b32_e32 v2, s3 -; GCN-NEXT: v_mov_b32_e32 v3, s4 -; GCN-NEXT: v_mov_b32_e32 v4, s0 -; GCN-NEXT: v_mov_b32_e32 v5, s5 -; GCN-NEXT: v_mov_b32_e32 v6, s1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GCN-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GCN-NEXT: v_or_b32_e32 v0, v0, v1 -; GCN-NEXT: v_or_b32_e32 v1, v2, v3 +; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GCN-NEXT: v_readfirstlane_b32 s0, v1 ; GCN-NEXT: v_readfirstlane_b32 s1, v0 ; GCN-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: s_select_v4bf16: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_lshr_b32 s2, s2, 16 -; GFX7-NEXT: s_lshr_b32 s6, s6, 16 -; GFX7-NEXT: s_lshr_b32 s3, s3, 16 -; GFX7-NEXT: s_lshr_b32 s7, s7, 16 -; GFX7-NEXT: v_mov_b32_e32 v1, s6 -; GFX7-NEXT: v_mov_b32_e32 v2, s2 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX7-NEXT: v_mov_b32_e32 v1, s7 -; GFX7-NEXT: v_mov_b32_e32 v2, s3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX7-NEXT: s_lshr_b32 s0, s0, 16 -; GFX7-NEXT: s_lshr_b32 s4, s4, 16 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-NEXT: v_mov_b32_e32 v1, s0 +; GFX7-NEXT: s_lshr_b32 s0, s5, 16 +; GFX7-NEXT: v_mov_b32_e32 v2, s4 +; GFX7-NEXT: v_alignbit_b32 v2, s0, v2, 16 +; GFX7-NEXT: s_lshr_b32 s0, s3, 16 +; GFX7-NEXT: v_mov_b32_e32 v3, s2 ; GFX7-NEXT: s_lshr_b32 s1, s1, 16 -; GFX7-NEXT: s_lshr_b32 s5, s5, 16 -; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX7-NEXT: v_mov_b32_e32 v1, s4 -; GFX7-NEXT: v_mov_b32_e32 v2, s0 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX7-NEXT: v_mov_b32_e32 v2, s5 -; GFX7-NEXT: v_mov_b32_e32 v3, s1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX7-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX7-NEXT: v_alignbit_b32 v3, s0, v3, 16 +; GFX7-NEXT: s_lshr_b32 s0, s7, 16 +; GFX7-NEXT: v_mov_b32_e32 v4, s6 +; GFX7-NEXT: v_alignbit_b32 v1, s1, v1, 16 +; GFX7-NEXT: v_alignbit_b32 v4, s0, v4, 16 +; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX7-NEXT: v_readfirstlane_b32 s0, v1 ; GFX7-NEXT: v_readfirstlane_b32 s1, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_select_v4bf16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_lshr_b32 s4, s1, 16 -; GFX8-NEXT: s_lshr_b32 s5, s3, 16 -; GFX8-NEXT: v_mov_b32_e32 v1, s5 -; GFX8-NEXT: v_mov_b32_e32 v2, s4 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v1, s3 -; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX8-NEXT: s_lshr_b32 s1, s0, 16 -; GFX8-NEXT: s_lshr_b32 s3, s2, 16 -; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, s2 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s2 -; GFX8-NEXT: v_mov_b32_e32 v3, s0 -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_readfirstlane_b32 s0, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v0 ; GFX8-NEXT: ; return to shader part epilog @@ -28555,235 +28228,171 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_writelane_b32 v31, s30, 0 ; GFX8-NEXT: v_writelane_b32 v31, s31, 1 ; GFX8-NEXT: v_writelane_b32 v31, s34, 2 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_writelane_b32 v31, s35, 3 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v1 ; GFX8-NEXT: v_writelane_b32 v31, s36, 4 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v2 ; GFX8-NEXT: v_writelane_b32 v31, s37, 5 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v3 +; GFX8-NEXT: v_and_b32_e32 v21, 1, v21 +; GFX8-NEXT: v_and_b32_e32 v18, 1, v18 ; GFX8-NEXT: v_writelane_b32 v31, s38, 6 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v4 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v21 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v18 +; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68 +; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 +; GFX8-NEXT: v_and_b32_e32 v17, 1, v17 +; GFX8-NEXT: v_and_b32_e32 v16, 1, v16 ; GFX8-NEXT: v_writelane_b32 v31, s39, 7 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v5 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v17 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v16 +; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:8 +; GFX8-NEXT: v_and_b32_e32 v15, 1, v15 +; GFX8-NEXT: v_and_b32_e32 v14, 1, v14 ; GFX8-NEXT: v_writelane_b32 v31, s40, 8 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v6 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v15 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v14 +; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:76 +; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:12 ; GFX8-NEXT: v_writelane_b32 v31, s41, 9 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v7 ; GFX8-NEXT: v_writelane_b32 v31, s42, 10 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v8 +; GFX8-NEXT: v_and_b32_e32 v13, 1, v13 +; GFX8-NEXT: v_and_b32_e32 v12, 1, v12 ; GFX8-NEXT: v_writelane_b32 v31, s43, 11 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v9 +; GFX8-NEXT: v_and_b32_e32 v20, 1, v20 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v13 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v12 +; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:80 +; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:16 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v20 +; GFX8-NEXT: buffer_load_ushort v20, off, s[0:3], s32 ; GFX8-NEXT: v_writelane_b32 v31, s44, 12 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v10 ; GFX8-NEXT: v_writelane_b32 v31, s45, 13 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v11 ; GFX8-NEXT: v_writelane_b32 v31, s46, 14 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v12 ; GFX8-NEXT: v_writelane_b32 v31, s47, 15 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v13 ; GFX8-NEXT: v_writelane_b32 v31, s48, 16 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v14 ; GFX8-NEXT: v_writelane_b32 v31, s49, 17 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v15 ; GFX8-NEXT: v_writelane_b32 v31, s50, 18 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v16 ; GFX8-NEXT: v_writelane_b32 v31, s51, 19 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v17 ; GFX8-NEXT: v_writelane_b32 v31, s52, 20 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v18 ; GFX8-NEXT: v_writelane_b32 v31, s53, 21 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v19 ; GFX8-NEXT: v_writelane_b32 v31, s54, 22 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v20 ; GFX8-NEXT: v_writelane_b32 v31, s55, 23 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v21 ; GFX8-NEXT: v_writelane_b32 v31, s56, 24 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v22 ; GFX8-NEXT: v_writelane_b32 v31, s57, 25 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v23 ; GFX8-NEXT: v_writelane_b32 v31, s58, 26 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v24 ; GFX8-NEXT: v_writelane_b32 v31, s59, 27 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v25 ; GFX8-NEXT: v_writelane_b32 v31, s60, 28 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v26 ; GFX8-NEXT: v_writelane_b32 v31, s61, 29 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v27 ; GFX8-NEXT: v_writelane_b32 v31, s62, 30 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v28 ; GFX8-NEXT: v_writelane_b32 v31, s63, 31 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v29 ; GFX8-NEXT: v_writelane_b32 v31, s64, 32 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v30 +; GFX8-NEXT: v_and_b32_e32 v8, 1, v8 +; GFX8-NEXT: v_and_b32_e32 v7, 1, v7 ; GFX8-NEXT: v_writelane_b32 v31, s65, 33 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v0 -; GFX8-NEXT: buffer_load_ushort v0, off, s[0:3], s32 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v8 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v7 +; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:84 +; GFX8-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20 +; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX8-NEXT: v_and_b32_e32 v1, 1, v1 ; GFX8-NEXT: v_writelane_b32 v31, s66, 34 -; GFX8-NEXT: v_writelane_b32 v31, s67, 35 -; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v2 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v1 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX8-NEXT: v_writelane_b32 v31, s67, 35 +; GFX8-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX8-NEXT: v_and_b32_e32 v5, 1, v5 +; GFX8-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v3 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[66:67], 1, v0 -; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:68 -; GFX8-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 -; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 -; GFX8-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 -; GFX8-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 -; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12 -; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 -; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16 -; GFX8-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84 -; GFX8-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20 -; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88 -; GFX8-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:24 -; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92 -; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:28 -; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 -; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:32 -; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 -; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:36 -; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 -; GFX8-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 -; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 -; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 -; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 -; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:48 -; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 -; GFX8-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 -; GFX8-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 -; GFX8-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:56 -; GFX8-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 -; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60 -; GFX8-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:128 -; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 -; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v29 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v33 -; GFX8-NEXT: v_cndmask_b32_e64 v28, v34, v28, s[66:67] -; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v33, s[64:65] -; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v32 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30 -; GFX8-NEXT: v_cndmask_b32_e64 v33, v34, v33, s[62:63] -; GFX8-NEXT: v_cndmask_b32_e64 v30, v30, v32, s[60:61] -; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v27 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v26 -; GFX8-NEXT: v_cndmask_b32_e64 v32, v34, v32, s[58:59] -; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, v27, s[56:57] -; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v25 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v24 -; GFX8-NEXT: v_cndmask_b32_e64 v27, v34, v27, s[54:55] -; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, v25, s[52:53] -; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v23 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v22 -; GFX8-NEXT: v_cndmask_b32_e64 v25, v34, v25, s[50:51] -; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, v23, s[48:49] -; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v21 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v20 -; GFX8-NEXT: v_cndmask_b32_e64 v23, v34, v23, s[46:47] -; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, v21, s[44:45] -; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v19 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v18 -; GFX8-NEXT: v_cndmask_b32_e64 v21, v34, v21, s[42:43] -; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, v19, s[40:41] -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v17 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v16 -; GFX8-NEXT: v_cndmask_b32_e64 v19, v34, v19, s[38:39] -; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v17, s[36:37] -; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v14 -; GFX8-NEXT: v_cndmask_b32_e64 v17, v34, v17, s[34:35] -; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[30:31] -; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v12 -; GFX8-NEXT: v_cndmask_b32_e64 v15, v34, v15, s[28:29] -; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[26:27] -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v11 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v10 -; GFX8-NEXT: v_cndmask_b32_e64 v13, v34, v13, s[24:25] -; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[22:23] -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v8 -; GFX8-NEXT: v_cndmask_b32_e64 v11, v34, v11, s[20:21] -; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[18:19] -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v6 -; GFX8-NEXT: v_cndmask_b32_e64 v9, v34, v9, s[16:17] -; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[14:15] -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v5 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v4 -; GFX8-NEXT: v_cndmask_b32_e64 v7, v34, v7, s[12:13] -; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[10:11] -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e64 v5, v34, v5, s[8:9] -; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[6:7] -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v0 -; GFX8-NEXT: v_cndmask_b32_e64 v3, v34, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v6 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v5 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v4 +; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 +; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 +; GFX8-NEXT: v_and_b32_e32 v10, 1, v10 +; GFX8-NEXT: v_and_b32_e32 v9, 1, v9 +; GFX8-NEXT: v_and_b32_e32 v11, 1, v11 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v10 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v9 +; GFX8-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:92 +; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:28 +; GFX8-NEXT: v_and_b32_e32 v25, 1, v25 +; GFX8-NEXT: v_and_b32_e32 v24, 1, v24 +; GFX8-NEXT: v_and_b32_e32 v23, 1, v23 +; GFX8-NEXT: v_and_b32_e32 v22, 1, v22 +; GFX8-NEXT: v_and_b32_e32 v19, 1, v19 +; GFX8-NEXT: s_waitcnt vmcnt(14) +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v18 +; GFX8-NEXT: s_waitcnt vmcnt(13) +; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v21 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[64:65] +; GFX8-NEXT: v_cndmask_b32_e64 v0, v18, v21, s[66:67] +; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX8-NEXT: s_waitcnt vmcnt(13) +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v16 +; GFX8-NEXT: s_waitcnt vmcnt(12) +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v17 +; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[60:61] ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v5 -; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7 -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v9 -; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v11 -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v13 -; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v15 -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v17 -; GFX8-NEXT: v_or_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v6, v12, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v7, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v32 -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v33 -; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v28 -; GFX8-NEXT: v_or_b32_sdwa v8, v16, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v9, v18, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v11, v22, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v12, v24, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v13, v26, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v14, v30, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v15, v29, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[62:63] +; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:40 +; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56 +; GFX8-NEXT: s_waitcnt vmcnt(13) +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v15 +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v14 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[56:57] +; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e64 v2, v14, v15, s[58:59] +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_waitcnt vmcnt(11) +; GFX8-NEXT: v_cndmask_b32_e64 v3, v12, v13, s[54:55] +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v13 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v11 +; GFX8-NEXT: s_waitcnt vmcnt(10) +; GFX8-NEXT: v_and_b32_e32 v11, 1, v20 +; GFX8-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[52:53] +; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 +; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v25 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v24 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v23 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v22 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v19 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v11 +; GFX8-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 +; GFX8-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:108 +; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96 +; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:32 +; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 +; GFX8-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 +; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:48 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 +; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:124 +; GFX8-NEXT: v_and_b32_e32 v26, 1, v26 +; GFX8-NEXT: v_and_b32_e32 v28, 1, v28 +; GFX8-NEXT: v_and_b32_e32 v27, 1, v27 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v26 +; GFX8-NEXT: v_and_b32_e32 v29, 1, v29 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v28 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v27 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29 +; GFX8-NEXT: v_and_b32_e32 v30, 1, v30 +; GFX8-NEXT: s_waitcnt vmcnt(14) +; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v8, s[50:51] +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[48:49] +; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX8-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30 ; GFX8-NEXT: v_readlane_b32 s67, v31, 35 ; GFX8-NEXT: v_readlane_b32 s66, v31, 34 ; GFX8-NEXT: v_readlane_b32 s65, v31, 33 @@ -28794,6 +28403,18 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_readlane_b32 s60, v31, 28 ; GFX8-NEXT: v_readlane_b32 s59, v31, 27 ; GFX8-NEXT: v_readlane_b32 s58, v31, 26 +; GFX8-NEXT: v_cndmask_b32_e64 v7, v5, v6, s[46:47] +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[44:45] +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX8-NEXT: v_or_b32_sdwa v5, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v10 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v9 +; GFX8-NEXT: v_cndmask_b32_e64 v6, v9, v10, s[42:43] +; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[40:41] +; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX8-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_readlane_b32 s57, v31, 25 ; GFX8-NEXT: v_readlane_b32 s56, v31, 24 ; GFX8-NEXT: v_readlane_b32 s55, v31, 23 @@ -28812,6 +28433,43 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_readlane_b32 s42, v31, 10 ; GFX8-NEXT: v_readlane_b32 s41, v31, 9 ; GFX8-NEXT: v_readlane_b32 s40, v31, 8 +; GFX8-NEXT: s_waitcnt vmcnt(6) +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v22 +; GFX8-NEXT: s_waitcnt vmcnt(5) +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v23 +; GFX8-NEXT: v_cndmask_b32_e64 v8, v9, v8, s[36:37] +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v18 +; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v25 +; GFX8-NEXT: v_cndmask_b32_e64 v7, v22, v23, s[38:39] +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v9, v10, v9, s[30:31] +; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e64 v8, v25, v18, s[34:35] +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e64 v9, v24, v16, s[28:29] +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v16 +; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v24 +; GFX8-NEXT: v_cndmask_b32_e64 v10, v16, v10, s[26:27] +; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52 +; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_cndmask_b32_e64 v10, v11, v21, s[24:25] +; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v21 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[22:23] +; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 +; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_or_b32_sdwa v10, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_waitcnt vmcnt(4) +; GFX8-NEXT: v_cndmask_b32_e64 v11, v19, v20, s[20:21] +; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[16:17] +; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX8-NEXT: v_or_b32_sdwa v11, v11, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_readlane_b32 s39, v31, 7 ; GFX8-NEXT: v_readlane_b32 s38, v31, 6 ; GFX8-NEXT: v_readlane_b32 s37, v31, 5 @@ -28820,6 +28478,33 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_readlane_b32 s34, v31, 2 ; GFX8-NEXT: v_readlane_b32 s31, v31, 1 ; GFX8-NEXT: v_readlane_b32 s30, v31, 0 +; GFX8-NEXT: s_waitcnt vmcnt(2) +; GFX8-NEXT: v_cndmask_b32_e64 v19, v12, v18, s[14:15] +; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v18, s[12:13] +; GFX8-NEXT: v_cndmask_b32_e64 v18, v13, v17, s[10:11] +; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[8:9] +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_cndmask_b32_e64 v17, v14, v16, s[6:7] +; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[4:5] +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX8-NEXT: v_or_b32_sdwa v14, v17, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_cndmask_b32_e32 v16, v15, v20, vcc +; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v20 +; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[18:19] +; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GFX8-NEXT: v_or_b32_sdwa v12, v19, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v13, v18, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; GFX8-NEXT: s_mov_b64 exec, s[4:5] @@ -28835,223 +28520,169 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX9-NEXT: v_writelane_b32 v31, s30, 0 ; GFX9-NEXT: v_writelane_b32 v31, s31, 1 ; GFX9-NEXT: v_writelane_b32 v31, s34, 2 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_writelane_b32 v31, s35, 3 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v3 ; GFX9-NEXT: v_writelane_b32 v31, s36, 4 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v2 ; GFX9-NEXT: v_writelane_b32 v31, s37, 5 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v5 ; GFX9-NEXT: v_writelane_b32 v31, s38, 6 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v4 ; GFX9-NEXT: v_writelane_b32 v31, s39, 7 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v7 ; GFX9-NEXT: v_writelane_b32 v31, s40, 8 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v6 ; GFX9-NEXT: v_writelane_b32 v31, s41, 9 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v9 ; GFX9-NEXT: v_writelane_b32 v31, s42, 10 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v8 ; GFX9-NEXT: v_writelane_b32 v31, s43, 11 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v11 ; GFX9-NEXT: v_writelane_b32 v31, s44, 12 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v10 ; GFX9-NEXT: v_writelane_b32 v31, s45, 13 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v13 ; GFX9-NEXT: v_writelane_b32 v31, s46, 14 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v12 ; GFX9-NEXT: v_writelane_b32 v31, s47, 15 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v15 ; GFX9-NEXT: v_writelane_b32 v31, s48, 16 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v14 ; GFX9-NEXT: v_writelane_b32 v31, s49, 17 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v17 ; GFX9-NEXT: v_writelane_b32 v31, s50, 18 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v16 ; GFX9-NEXT: v_writelane_b32 v31, s51, 19 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v19 +; GFX9-NEXT: v_and_b32_e32 v21, 1, v21 +; GFX9-NEXT: v_and_b32_e32 v18, 1, v18 ; GFX9-NEXT: v_writelane_b32 v31, s52, 20 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v18 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v21 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v18 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68 +; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 +; GFX9-NEXT: v_and_b32_e32 v17, 1, v17 +; GFX9-NEXT: v_and_b32_e32 v16, 1, v16 ; GFX9-NEXT: v_writelane_b32 v31, s53, 21 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v21 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v17 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v16 +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_writelane_b32 v31, s54, 22 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v20 +; GFX9-NEXT: v_and_b32_e32 v15, 1, v15 +; GFX9-NEXT: v_and_b32_e32 v14, 1, v14 ; GFX9-NEXT: v_writelane_b32 v31, s55, 23 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v23 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v15 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v14 +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:76 +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:12 ; GFX9-NEXT: v_writelane_b32 v31, s56, 24 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v22 +; GFX9-NEXT: v_and_b32_e32 v13, 1, v13 +; GFX9-NEXT: v_and_b32_e32 v12, 1, v12 ; GFX9-NEXT: v_writelane_b32 v31, s57, 25 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v25 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v13 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v12 +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:80 +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:16 ; GFX9-NEXT: v_writelane_b32 v31, s58, 26 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v24 +; GFX9-NEXT: v_and_b32_e32 v5, 1, v5 +; GFX9-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX9-NEXT: v_writelane_b32 v31, s59, 27 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v27 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v5 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v4 +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84 +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:20 +; GFX9-NEXT: v_and_b32_e32 v20, 1, v20 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v20 +; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 ; GFX9-NEXT: v_writelane_b32 v31, s60, 28 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v26 ; GFX9-NEXT: v_writelane_b32 v31, s61, 29 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v29 ; GFX9-NEXT: v_writelane_b32 v31, s62, 30 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v28 ; GFX9-NEXT: v_writelane_b32 v31, s63, 31 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0 -; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 ; GFX9-NEXT: v_writelane_b32 v31, s64, 32 ; GFX9-NEXT: v_writelane_b32 v31, s65, 33 ; GFX9-NEXT: v_writelane_b32 v31, s66, 34 +; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX9-NEXT: v_writelane_b32 v31, s67, 35 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v30 +; GFX9-NEXT: v_writelane_b32 v31, s67, 35 +; GFX9-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v2 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v1 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[66:67], 1, v0 -; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:68 -; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 -; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 -; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 -; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12 -; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 -; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16 -; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84 -; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20 -; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88 -; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:24 -; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92 -; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:28 -; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:32 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:36 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 -; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 -; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v3 +; GFX9-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX9-NEXT: v_and_b32_e32 v7, 1, v7 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v6 +; GFX9-NEXT: v_and_b32_e32 v8, 1, v8 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v7 +; GFX9-NEXT: v_and_b32_e32 v9, 1, v9 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v8 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v9 +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:24 +; GFX9-NEXT: v_and_b32_e32 v24, 1, v24 +; GFX9-NEXT: v_and_b32_e32 v11, 1, v11 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v24 +; GFX9-NEXT: v_and_b32_e32 v23, 1, v23 +; GFX9-NEXT: v_and_b32_e32 v22, 1, v22 +; GFX9-NEXT: v_and_b32_e32 v19, 1, v19 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v11 +; GFX9-NEXT: v_and_b32_e32 v10, 1, v10 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:48 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v23 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v22 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v19 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v10 +; GFX9-NEXT: v_and_b32_e32 v26, 1, v26 +; GFX9-NEXT: v_and_b32_e32 v25, 1, v25 +; GFX9-NEXT: v_and_b32_e32 v28, 1, v28 +; GFX9-NEXT: v_and_b32_e32 v27, 1, v27 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v26 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v25 +; GFX9-NEXT: v_and_b32_e32 v29, 1, v29 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v28 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v27 +; GFX9-NEXT: v_and_b32_e32 v30, 1, v30 +; GFX9-NEXT: s_waitcnt vmcnt(13) +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v18 +; GFX9-NEXT: s_waitcnt vmcnt(12) +; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v21 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v18, v21, s[66:67] +; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[64:65] +; GFX9-NEXT: s_mov_b32 s64, 0x5040100 +; GFX9-NEXT: v_perm_b32 v0, v1, v0, s64 +; GFX9-NEXT: s_waitcnt vmcnt(11) +; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v16 +; GFX9-NEXT: s_waitcnt vmcnt(10) +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v17 +; GFX9-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[62:63] +; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[60:61] +; GFX9-NEXT: v_perm_b32 v1, v2, v1, s64 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:40 ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 -; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:48 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 -; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 -; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:56 -; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:124 -; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:60 -; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128 -; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e64 v29, v32, v33, s[66:67] -; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX9-NEXT: v_cndmask_b32_e64 v32, v32, v33, s[64:65] -; GFX9-NEXT: v_cndmask_b32_e64 v33, v28, v30, s[62:63] -; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; GFX9-NEXT: v_cndmask_b32_e64 v28, v28, v30, s[60:61] -; GFX9-NEXT: v_cndmask_b32_e64 v30, v26, v27, s[58:59] -; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; GFX9-NEXT: v_cndmask_b32_e64 v26, v26, v27, s[56:57] -; GFX9-NEXT: v_cndmask_b32_e64 v27, v24, v25, s[54:55] -; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX9-NEXT: v_cndmask_b32_e64 v24, v24, v25, s[52:53] -; GFX9-NEXT: v_cndmask_b32_e64 v25, v22, v23, s[50:51] -; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; GFX9-NEXT: v_cndmask_b32_e64 v22, v22, v23, s[48:49] -; GFX9-NEXT: v_cndmask_b32_e64 v23, v20, v21, s[46:47] -; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; GFX9-NEXT: v_cndmask_b32_e64 v20, v20, v21, s[44:45] -; GFX9-NEXT: v_cndmask_b32_e64 v21, v18, v19, s[42:43] -; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX9-NEXT: v_cndmask_b32_e64 v18, v18, v19, s[40:41] -; GFX9-NEXT: v_cndmask_b32_e64 v19, v16, v17, s[38:39] -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX9-NEXT: v_cndmask_b32_e64 v16, v16, v17, s[36:37] -; GFX9-NEXT: v_cndmask_b32_e64 v17, v14, v15, s[34:35] -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX9-NEXT: s_waitcnt vmcnt(11) +; GFX9-NEXT: v_cndmask_b32_e64 v2, v14, v15, s[58:59] +; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v15 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[30:31] -; GFX9-NEXT: v_cndmask_b32_e64 v15, v12, v13, s[28:29] +; GFX9-NEXT: v_cndmask_b32_e64 v3, v14, v3, s[56:57] +; GFX9-NEXT: v_perm_b32 v2, v3, v2, s64 +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:124 +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 +; GFX9-NEXT: s_waitcnt vmcnt(11) +; GFX9-NEXT: v_cndmask_b32_e64 v3, v12, v13, s[54:55] ; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 ; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[26:27] -; GFX9-NEXT: v_cndmask_b32_e64 v13, v10, v11, s[24:25] -; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[22:23] -; GFX9-NEXT: v_cndmask_b32_e64 v11, v8, v9, s[20:21] -; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[18:19] -; GFX9-NEXT: v_cndmask_b32_e64 v9, v6, v7, s[16:17] -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[14:15] -; GFX9-NEXT: v_cndmask_b32_e64 v7, v4, v5, s[12:13] +; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[52:53] +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 +; GFX9-NEXT: v_perm_b32 v3, v12, v3, s64 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29 +; GFX9-NEXT: s_waitcnt vmcnt(10) +; GFX9-NEXT: v_cndmask_b32_e64 v12, v4, v5, s[50:51] ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[10:11] -; GFX9-NEXT: v_cndmask_b32_e64 v5, v2, v3, s[8:9] -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v3, v0, v1, s[4:5] -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4 -; GFX9-NEXT: v_perm_b32 v1, v2, v5, s4 -; GFX9-NEXT: v_perm_b32 v2, v4, v7, s4 -; GFX9-NEXT: v_perm_b32 v3, v6, v9, s4 -; GFX9-NEXT: v_perm_b32 v4, v8, v11, s4 -; GFX9-NEXT: v_perm_b32 v5, v10, v13, s4 -; GFX9-NEXT: v_perm_b32 v6, v12, v15, s4 -; GFX9-NEXT: v_perm_b32 v7, v14, v17, s4 -; GFX9-NEXT: v_perm_b32 v8, v16, v19, s4 -; GFX9-NEXT: v_perm_b32 v9, v18, v21, s4 -; GFX9-NEXT: v_perm_b32 v10, v20, v23, s4 -; GFX9-NEXT: v_perm_b32 v11, v22, v25, s4 -; GFX9-NEXT: v_perm_b32 v12, v24, v27, s4 -; GFX9-NEXT: v_perm_b32 v13, v26, v30, s4 -; GFX9-NEXT: v_perm_b32 v14, v28, v33, s4 -; GFX9-NEXT: v_perm_b32 v15, v32, v29, s4 +; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[48:49] +; GFX9-NEXT: v_perm_b32 v4, v4, v12, s64 +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 +; GFX9-NEXT: s_waitcnt vmcnt(10) +; GFX9-NEXT: v_and_b32_e32 v11, 1, v20 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v11 +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:92 +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28 +; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:104 +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:100 +; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96 +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:32 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30 ; GFX9-NEXT: v_readlane_b32 s67, v31, 35 ; GFX9-NEXT: v_readlane_b32 s66, v31, 34 ; GFX9-NEXT: v_readlane_b32 s65, v31, 33 -; GFX9-NEXT: v_readlane_b32 s64, v31, 32 ; GFX9-NEXT: v_readlane_b32 s63, v31, 31 ; GFX9-NEXT: v_readlane_b32 s62, v31, 30 ; GFX9-NEXT: v_readlane_b32 s61, v31, 29 @@ -29067,11 +28698,54 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX9-NEXT: v_readlane_b32 s51, v31, 19 ; GFX9-NEXT: v_readlane_b32 s50, v31, 18 ; GFX9-NEXT: v_readlane_b32 s49, v31, 17 +; GFX9-NEXT: s_waitcnt vmcnt(16) +; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v7, s[46:47] +; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[44:45] +; GFX9-NEXT: v_perm_b32 v5, v6, v5, s64 ; GFX9-NEXT: v_readlane_b32 s48, v31, 16 ; GFX9-NEXT: v_readlane_b32 s47, v31, 15 ; GFX9-NEXT: v_readlane_b32 s46, v31, 14 ; GFX9-NEXT: v_readlane_b32 s45, v31, 13 ; GFX9-NEXT: v_readlane_b32 s44, v31, 12 +; GFX9-NEXT: s_waitcnt vmcnt(6) +; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v9, s[42:43] +; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v9 +; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[40:41] +; GFX9-NEXT: v_perm_b32 v6, v7, v6, s64 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v22 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v23 +; GFX9-NEXT: v_cndmask_b32_e64 v7, v22, v23, s[38:39] +; GFX9-NEXT: v_cndmask_b32_e64 v8, v9, v8, s[36:37] +; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v18 +; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v20 +; GFX9-NEXT: v_perm_b32 v7, v8, v7, s64 +; GFX9-NEXT: v_cndmask_b32_e64 v8, v20, v18, s[34:35] +; GFX9-NEXT: v_cndmask_b32_e64 v9, v17, v9, s[30:31] +; GFX9-NEXT: v_perm_b32 v8, v9, v8, s64 +; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, v16, s[28:29] +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52 +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56 +; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[26:27] +; GFX9-NEXT: v_perm_b32 v9, v11, v9, s64 +; GFX9-NEXT: v_cndmask_b32_e64 v11, v10, v21, s[24:25] +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v21 +; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v16, s[22:23] +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 +; GFX9-NEXT: v_perm_b32 v10, v10, v11, s64 +; GFX9-NEXT: v_cndmask_b32_e64 v11, v19, v24, s[20:21] +; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v24 +; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX9-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[16:17] +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 +; GFX9-NEXT: v_perm_b32 v11, v19, v11, s64 ; GFX9-NEXT: v_readlane_b32 s43, v31, 11 ; GFX9-NEXT: v_readlane_b32 s42, v31, 10 ; GFX9-NEXT: v_readlane_b32 s41, v31, 9 @@ -29084,6 +28758,31 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX9-NEXT: v_readlane_b32 s34, v31, 2 ; GFX9-NEXT: v_readlane_b32 s31, v31, 1 ; GFX9-NEXT: v_readlane_b32 s30, v31, 0 +; GFX9-NEXT: s_waitcnt vmcnt(3) +; GFX9-NEXT: v_cndmask_b32_e64 v19, v12, v18, s[14:15] +; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v18, s[12:13] +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_cndmask_b32_e64 v18, v13, v17, s[10:11] +; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[8:9] +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_cndmask_b32_e64 v17, v14, v16, s[6:7] +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[4:5] +; GFX9-NEXT: v_perm_b32 v14, v14, v17, s64 +; GFX9-NEXT: v_perm_b32 v12, v12, v19, s64 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_cndmask_b32_e32 v16, v15, v20, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v20 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[18:19] +; GFX9-NEXT: v_perm_b32 v13, v13, v18, s64 +; GFX9-NEXT: v_perm_b32 v15, v15, v16, s64 +; GFX9-NEXT: v_readlane_b32 s64, v31, 32 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -29097,208 +28796,205 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX10-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s4 -; GFX10-NEXT: v_and_b32_e32 v29, 1, v29 -; GFX10-NEXT: v_and_b32_e32 v30, 1, v30 -; GFX10-NEXT: v_and_b32_e32 v28, 1, v28 -; GFX10-NEXT: v_and_b32_e32 v26, 1, v26 -; GFX10-NEXT: v_and_b32_e32 v24, 1, v24 -; GFX10-NEXT: v_and_b32_e32 v22, 1, v22 -; GFX10-NEXT: v_and_b32_e32 v20, 1, v20 -; GFX10-NEXT: v_and_b32_e32 v18, 1, v18 -; GFX10-NEXT: v_and_b32_e32 v16, 1, v16 -; GFX10-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX10-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v3 +; GFX10-NEXT: v_and_b32_e32 v3, 1, v6 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v8 +; GFX10-NEXT: v_and_b32_e32 v10, 1, v10 ; GFX10-NEXT: v_and_b32_e32 v12, 1, v12 -; GFX10-NEXT: s_clause 0x14 -; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60 -; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:124 -; GFX10-NEXT: buffer_load_ushort v34, off, s[0:3], s32 -; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:128 -; GFX10-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:64 -; GFX10-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:48 -; GFX10-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:116 -; GFX10-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:52 -; GFX10-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:120 -; GFX10-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:56 -; GFX10-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32 -; GFX10-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:100 -; GFX10-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:36 -; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:104 -; GFX10-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:40 -; GFX10-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:108 -; GFX10-NEXT: buffer_load_dword v64, off, s[0:3], s32 offset:44 -; GFX10-NEXT: buffer_load_dword v65, off, s[0:3], s32 offset:112 -; GFX10-NEXT: buffer_load_dword v66, off, s[0:3], s32 offset:72 -; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:76 -; GFX10-NEXT: buffer_load_dword v68, off, s[0:3], s32 offset:80 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29 +; GFX10-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX10-NEXT: v_and_b32_e32 v16, 1, v16 +; GFX10-NEXT: s_clause 0x15 +; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:68 +; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 +; GFX10-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:72 +; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8 +; GFX10-NEXT: buffer_load_ushort v36, off, s[0:3], s32 +; GFX10-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:76 +; GFX10-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:12 +; GFX10-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:80 +; GFX10-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16 +; GFX10-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:20 +; GFX10-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:84 +; GFX10-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:88 +; GFX10-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24 +; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92 +; GFX10-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:28 +; GFX10-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:96 +; GFX10-NEXT: buffer_load_dword v64, off, s[0:3], s32 offset:32 +; GFX10-NEXT: buffer_load_dword v65, off, s[0:3], s32 offset:36 +; GFX10-NEXT: buffer_load_dword v66, off, s[0:3], s32 offset:104 +; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:40 +; GFX10-NEXT: buffer_load_dword v68, off, s[0:3], s32 offset:100 +; GFX10-NEXT: buffer_load_dword v69, off, s[0:3], s32 offset:52 +; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v0 +; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112 +; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v2 +; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:48 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v4 +; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 +; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v3 +; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 +; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v8 ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:92 -; GFX10-NEXT: buffer_load_dword v69, off, s[0:3], s32 offset:28 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v30 -; GFX10-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 -; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v28 -; GFX10-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 -; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v26 -; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v24 -; GFX10-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 -; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v22 -; GFX10-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:20 -; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v20 -; GFX10-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:16 -; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v18 -; GFX10-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:12 -; GFX10-NEXT: v_cmp_eq_u32_e64 s11, 1, v16 -; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:8 +; GFX10-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 +; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 +; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v10 +; GFX10-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 +; GFX10-NEXT: v_cmp_eq_u32_e64 s11, 1, v12 +; GFX10-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:60 ; GFX10-NEXT: v_cmp_eq_u32_e64 s12, 1, v14 +; GFX10-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:128 +; GFX10-NEXT: v_cmp_eq_u32_e64 s13, 1, v16 ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:68 -; GFX10-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:24 -; GFX10-NEXT: v_cmp_eq_u32_e64 s13, 1, v12 -; GFX10-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:4 +; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64 +; GFX10-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:44 ; GFX10-NEXT: v_writelane_b32 v31, s30, 0 -; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX10-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX10-NEXT: v_and_b32_e32 v30, 1, v30 +; GFX10-NEXT: v_and_b32_e32 v28, 1, v28 +; GFX10-NEXT: v_and_b32_e32 v26, 1, v26 +; GFX10-NEXT: v_and_b32_e32 v24, 1, v24 ; GFX10-NEXT: v_writelane_b32 v31, s31, 1 -; GFX10-NEXT: v_and_b32_e32 v8, 1, v8 -; GFX10-NEXT: v_and_b32_e32 v10, 1, v10 -; GFX10-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 -; GFX10-NEXT: v_writelane_b32 v31, s34, 2 -; GFX10-NEXT: v_and_b32_e32 v5, 1, v5 -; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 -; GFX10-NEXT: v_and_b32_e32 v9, 1, v9 -; GFX10-NEXT: v_and_b32_e32 v11, 1, v11 -; GFX10-NEXT: v_and_b32_e32 v13, 1, v13 -; GFX10-NEXT: v_and_b32_e32 v15, 1, v15 +; GFX10-NEXT: v_and_b32_e32 v22, 1, v22 +; GFX10-NEXT: v_and_b32_e32 v20, 1, v20 ; GFX10-NEXT: v_and_b32_e32 v17, 1, v17 -; GFX10-NEXT: v_and_b32_e32 v19, 1, v19 -; GFX10-NEXT: v_and_b32_e32 v21, 1, v21 -; GFX10-NEXT: v_and_b32_e32 v23, 1, v23 -; GFX10-NEXT: v_and_b32_e32 v25, 1, v25 +; GFX10-NEXT: v_and_b32_e32 v9, 1, v9 +; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 +; GFX10-NEXT: v_writelane_b32 v31, s34, 2 +; GFX10-NEXT: v_and_b32_e32 v29, 1, v29 ; GFX10-NEXT: v_and_b32_e32 v27, 1, v27 -; GFX10-NEXT: v_cmp_eq_u32_e64 s14, 1, v10 -; GFX10-NEXT: v_cmp_eq_u32_e64 s15, 1, v8 -; GFX10-NEXT: v_cmp_eq_u32_e64 s16, 1, v6 -; GFX10-NEXT: v_cmp_eq_u32_e64 s17, 1, v4 -; GFX10-NEXT: v_cmp_eq_u32_e64 s18, 1, v2 -; GFX10-NEXT: v_cmp_eq_u32_e64 s19, 1, v0 +; GFX10-NEXT: v_and_b32_e32 v25, 1, v25 +; GFX10-NEXT: v_and_b32_e32 v23, 1, v23 +; GFX10-NEXT: v_and_b32_e32 v21, 1, v21 +; GFX10-NEXT: v_and_b32_e32 v19, 1, v19 +; GFX10-NEXT: v_and_b32_e32 v18, 1, v18 +; GFX10-NEXT: v_and_b32_e32 v15, 1, v15 +; GFX10-NEXT: v_and_b32_e32 v13, 1, v13 +; GFX10-NEXT: v_and_b32_e32 v11, 1, v11 +; GFX10-NEXT: v_and_b32_e32 v5, 1, v5 +; GFX10-NEXT: v_cmp_eq_u32_e64 s15, 1, v20 +; GFX10-NEXT: v_cmp_eq_u32_e64 s16, 1, v22 +; GFX10-NEXT: v_cmp_eq_u32_e64 s17, 1, v24 +; GFX10-NEXT: v_cmp_eq_u32_e64 s18, 1, v26 +; GFX10-NEXT: v_cmp_eq_u32_e64 s19, 1, v28 +; GFX10-NEXT: v_cmp_eq_u32_e64 s20, 1, v30 +; GFX10-NEXT: v_cmp_eq_u32_e64 s22, 1, v7 +; GFX10-NEXT: v_cmp_eq_u32_e64 s23, 1, v9 +; GFX10-NEXT: v_cmp_eq_u32_e64 s27, 1, v17 ; GFX10-NEXT: v_writelane_b32 v31, s35, 3 -; GFX10-NEXT: v_cmp_eq_u32_e64 s20, 1, v27 -; GFX10-NEXT: v_cmp_eq_u32_e64 s21, 1, v25 -; GFX10-NEXT: v_cmp_eq_u32_e64 s22, 1, v23 -; GFX10-NEXT: v_cmp_eq_u32_e64 s23, 1, v21 -; GFX10-NEXT: v_cmp_eq_u32_e64 s24, 1, v19 -; GFX10-NEXT: v_cmp_eq_u32_e64 s25, 1, v17 +; GFX10-NEXT: v_cmp_eq_u32_e64 s14, 1, v18 +; GFX10-NEXT: v_cmp_eq_u32_e64 s21, 1, v5 +; GFX10-NEXT: v_cmp_eq_u32_e64 s24, 1, v11 +; GFX10-NEXT: v_cmp_eq_u32_e64 s25, 1, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s26, 1, v15 -; GFX10-NEXT: v_cmp_eq_u32_e64 s27, 1, v13 -; GFX10-NEXT: v_cmp_eq_u32_e64 s28, 1, v11 -; GFX10-NEXT: v_cmp_eq_u32_e64 s29, 1, v7 -; GFX10-NEXT: v_cmp_eq_u32_e64 s30, 1, v3 -; GFX10-NEXT: v_cmp_eq_u32_e64 s31, 1, v1 -; GFX10-NEXT: v_cmp_eq_u32_e64 s34, 1, v5 -; GFX10-NEXT: v_cmp_eq_u32_e64 s35, 1, v9 +; GFX10-NEXT: v_cmp_eq_u32_e64 s28, 1, v19 +; GFX10-NEXT: v_cmp_eq_u32_e64 s29, 1, v21 +; GFX10-NEXT: v_cmp_eq_u32_e64 s30, 1, v23 +; GFX10-NEXT: v_cmp_eq_u32_e64 s31, 1, v25 +; GFX10-NEXT: v_cmp_eq_u32_e64 s34, 1, v27 +; GFX10-NEXT: v_cmp_eq_u32_e64 s35, 1, v29 ; GFX10-NEXT: s_waitcnt vmcnt(32) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v32 +; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v32 ; GFX10-NEXT: s_waitcnt vmcnt(31) -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v33 -; GFX10-NEXT: s_waitcnt vmcnt(30) -; GFX10-NEXT: v_and_b32_e32 v2, 1, v34 +; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v33 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v32, v33, s4 ; GFX10-NEXT: s_waitcnt vmcnt(29) -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v35 +; GFX10-NEXT: v_cndmask_b32_e64 v11, v34, v35, s5 ; GFX10-NEXT: s_waitcnt vmcnt(28) -; GFX10-NEXT: v_cndmask_b32_e64 v15, v35, v36, s4 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v36 -; GFX10-NEXT: v_cndmask_b32_e64 v17, v33, v32, s5 -; GFX10-NEXT: s_waitcnt vmcnt(25) -; GFX10-NEXT: v_cndmask_b32_e64 v19, v38, v39, s7 +; GFX10-NEXT: v_and_b32_e32 v17, 1, v36 +; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v35 +; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v34 +; GFX10-NEXT: s_waitcnt vmcnt(26) +; GFX10-NEXT: v_cndmask_b32_e64 v18, v37, v38, s7 +; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v38 +; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v37 ; GFX10-NEXT: s_waitcnt vmcnt(24) -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v48 -; GFX10-NEXT: s_waitcnt vmcnt(23) -; GFX10-NEXT: v_cndmask_b32_e64 v13, v48, v49, s6 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v49 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v39 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v38 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v37 +; GFX10-NEXT: v_cndmask_b32_e64 v21, v39, v48, s8 +; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v48 +; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v39 +; GFX10-NEXT: s_waitcnt vmcnt(22) +; GFX10-NEXT: v_cndmask_b32_e64 v24, v50, v49, s9 +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v49 +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v50 +; GFX10-NEXT: s_waitcnt vmcnt(20) +; GFX10-NEXT: v_cndmask_b32_e64 v27, v51, v52, s10 +; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v52 +; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v51 ; GFX10-NEXT: s_waitcnt vmcnt(18) -; GFX10-NEXT: v_cndmask_b32_e64 v27, v53, v54, s10 -; GFX10-NEXT: s_waitcnt vmcnt(17) -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v55 -; GFX10-NEXT: s_waitcnt vmcnt(16) -; GFX10-NEXT: v_cndmask_b32_e64 v21, v55, v64, s9 -; GFX10-NEXT: s_waitcnt vmcnt(15) -; GFX10-NEXT: v_cndmask_b32_e64 v11, v65, v37, s8 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v65 -; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v64 +; GFX10-NEXT: v_cndmask_b32_e64 v30, v53, v54, s11 ; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v54 ; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v53 -; GFX10-NEXT: v_cndmask_b32_e64 v34, v51, v52, s11 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v52 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v51 +; GFX10-NEXT: s_waitcnt vmcnt(16) +; GFX10-NEXT: v_cndmask_b32_e64 v34, v55, v64, s12 +; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v64 +; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v55 +; GFX10-NEXT: s_waitcnt vmcnt(12) +; GFX10-NEXT: v_cndmask_b32_e64 v37, v68, v65, s13 +; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v65 +; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v68 +; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v67 +; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v66 ; GFX10-NEXT: s_waitcnt vmcnt(9) -; GFX10-NEXT: v_cndmask_b32_e64 v37, v30, v50, s12 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v50 -; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX10-NEXT: v_cndmask_b32_e64 v39, v29, v69, s13 -; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v69 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX10-NEXT: v_cndmask_b32_e64 v52, v0, v2, s16 +; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX10-NEXT: s_waitcnt vmcnt(6) -; GFX10-NEXT: v_cndmask_b32_e64 v50, v24, v22, s15 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX10-NEXT: s_waitcnt vmcnt(5) -; GFX10-NEXT: v_cndmask_b32_e64 v51, v68, v20, s16 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v68 -; GFX10-NEXT: s_waitcnt vmcnt(4) -; GFX10-NEXT: v_cndmask_b32_e64 v53, v67, v18, s17 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: v_cndmask_b32_e64 v49, v28, v26, s14 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v67 -; GFX10-NEXT: v_cndmask_b32_e64 v55, v66, v16, s18 -; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v66 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e64 v65, v14, v12, s19 +; GFX10-NEXT: v_cndmask_b32_e64 v53, v8, v69, s17 +; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v69 +; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v4, v3, s18 +; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX10-NEXT: s_waitcnt vmcnt(3) +; GFX10-NEXT: v_cndmask_b32_e64 v64, v10, v12, s19 ; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cndmask_b32_e64 v51, v1, v6, s15 +; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX10-NEXT: v_cndmask_b32_e64 v65, v14, v16, s20 +; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v16 ; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v66, v1, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v67, v6, v5, s20 -; GFX10-NEXT: v_cndmask_b32_e64 v68, v8, v7, s21 -; GFX10-NEXT: v_cndmask_b32_e64 v69, v10, v9, s22 -; GFX10-NEXT: v_cndmask_b32_e64 v10, v25, v23, s23 -; GFX10-NEXT: v_cndmask_b32_e64 v9, v33, v32, s24 -; GFX10-NEXT: v_cndmask_b32_e64 v8, v36, v35, s25 -; GFX10-NEXT: v_cndmask_b32_e64 v7, v30, v38, s26 -; GFX10-NEXT: v_cndmask_b32_e64 v6, v29, v48, s27 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v28, v26, s28 -; GFX10-NEXT: v_cndmask_b32_e64 v20, v52, v20, s29 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v14, v12, s31 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v64, v16, s30 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v54, v18, s34 -; GFX10-NEXT: v_cndmask_b32_e64 v12, v24, v22, s35 -; GFX10-NEXT: v_cndmask_b32_e64 v16, v4, v3, s4 -; GFX10-NEXT: v_perm_b32 v0, v0, v65, 0x5040100 -; GFX10-NEXT: v_perm_b32 v1, v1, v55, 0x5040100 -; GFX10-NEXT: v_perm_b32 v2, v2, v53, 0x5040100 -; GFX10-NEXT: v_perm_b32 v3, v20, v51, 0x5040100 -; GFX10-NEXT: v_perm_b32 v4, v12, v50, 0x5040100 -; GFX10-NEXT: v_perm_b32 v5, v5, v49, 0x5040100 -; GFX10-NEXT: v_perm_b32 v6, v6, v39, 0x5040100 -; GFX10-NEXT: v_perm_b32 v7, v7, v37, 0x5040100 -; GFX10-NEXT: v_perm_b32 v8, v8, v34, 0x5040100 -; GFX10-NEXT: v_perm_b32 v9, v9, v27, 0x5040100 -; GFX10-NEXT: v_perm_b32 v10, v10, v21, 0x5040100 -; GFX10-NEXT: v_perm_b32 v11, v69, v11, 0x5040100 -; GFX10-NEXT: v_perm_b32 v12, v68, v19, 0x5040100 -; GFX10-NEXT: v_perm_b32 v13, v67, v13, 0x5040100 -; GFX10-NEXT: v_perm_b32 v14, v66, v17, 0x5040100 -; GFX10-NEXT: v_perm_b32 v15, v16, v15, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 +; GFX10-NEXT: v_cndmask_b32_e64 v48, v66, v67, s14 +; GFX10-NEXT: v_cndmask_b32_e64 v9, v15, v13, s6 +; GFX10-NEXT: v_cndmask_b32_e64 v13, v20, v19, s21 +; GFX10-NEXT: v_cndmask_b32_e64 v15, v23, v22, s22 +; GFX10-NEXT: v_cndmask_b32_e64 v19, v26, v25, s23 +; GFX10-NEXT: v_cndmask_b32_e64 v20, v29, v28, s24 +; GFX10-NEXT: v_cndmask_b32_e64 v22, v33, v32, s25 +; GFX10-NEXT: v_cndmask_b32_e64 v23, v36, v35, s26 +; GFX10-NEXT: v_cndmask_b32_e64 v25, v39, v38, s27 +; GFX10-NEXT: v_cndmask_b32_e64 v26, v50, v49, s28 +; GFX10-NEXT: v_cndmask_b32_e64 v28, v1, v6, s29 +; GFX10-NEXT: v_cndmask_b32_e64 v17, v0, v2, s30 +; GFX10-NEXT: v_cndmask_b32_e64 v29, v8, v54, s31 +; GFX10-NEXT: v_cndmask_b32_e64 v32, v4, v3, s34 +; GFX10-NEXT: v_cndmask_b32_e64 v33, v10, v12, s35 +; GFX10-NEXT: v_cndmask_b32_e32 v16, v14, v16, vcc_lo +; GFX10-NEXT: v_perm_b32 v0, v7, v5, 0x5040100 +; GFX10-NEXT: v_perm_b32 v1, v9, v11, 0x5040100 +; GFX10-NEXT: v_perm_b32 v2, v13, v18, 0x5040100 +; GFX10-NEXT: v_perm_b32 v3, v15, v21, 0x5040100 +; GFX10-NEXT: v_perm_b32 v4, v19, v24, 0x5040100 +; GFX10-NEXT: v_perm_b32 v5, v20, v27, 0x5040100 +; GFX10-NEXT: v_perm_b32 v6, v22, v30, 0x5040100 +; GFX10-NEXT: v_perm_b32 v7, v23, v34, 0x5040100 +; GFX10-NEXT: v_perm_b32 v8, v25, v37, 0x5040100 +; GFX10-NEXT: v_perm_b32 v9, v26, v48, 0x5040100 +; GFX10-NEXT: v_perm_b32 v10, v28, v51, 0x5040100 +; GFX10-NEXT: v_perm_b32 v11, v17, v52, 0x5040100 +; GFX10-NEXT: v_perm_b32 v12, v29, v53, 0x5040100 +; GFX10-NEXT: v_perm_b32 v13, v32, v55, 0x5040100 +; GFX10-NEXT: v_perm_b32 v14, v33, v64, 0x5040100 +; GFX10-NEXT: v_perm_b32 v15, v16, v65, 0x5040100 ; GFX10-NEXT: v_readlane_b32 s35, v31, 3 ; GFX10-NEXT: v_readlane_b32 s34, v31, 2 ; GFX10-NEXT: v_readlane_b32 s31, v31, 1 @@ -29315,198 +29011,205 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_clause 0x20 ; GFX11-NEXT: scratch_load_u16 v31, off, s32 -; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:124 -; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:4 -; GFX11-NEXT: v_and_b32_e32 v30, 1, v30 -; GFX11-NEXT: v_and_b32_e32 v28, 1, v28 -; GFX11-NEXT: v_and_b32_e32 v26, 1, v26 -; GFX11-NEXT: v_and_b32_e32 v24, 1, v24 -; GFX11-NEXT: v_and_b32_e32 v22, 1, v22 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v30 -; GFX11-NEXT: v_and_b32_e32 v3, 1, v3 -; GFX11-NEXT: v_and_b32_e32 v20, 1, v20 -; GFX11-NEXT: v_and_b32_e32 v18, 1, v18 -; GFX11-NEXT: v_and_b32_e32 v16, 1, v16 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:76 +; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:80 +; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:84 +; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:88 +; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:92 +; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:96 +; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:100 +; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:104 +; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:108 +; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:112 +; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:116 +; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:120 +; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:124 +; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:128 +; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:64 +; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX11-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX11-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX11-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX11-NEXT: v_and_b32_e32 v8, 1, v8 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_and_b32_e32 v27, 1, v27 +; GFX11-NEXT: v_and_b32_e32 v10, 1, v10 +; GFX11-NEXT: v_and_b32_e32 v12, 1, v12 +; GFX11-NEXT: v_and_b32_e32 v14, 1, v14 ; GFX11-NEXT: s_waitcnt vmcnt(30) -; GFX11-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28 -; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v32, v33, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 +; GFX11-NEXT: v_and_b32_e32 v29, 1, v29 ; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v33 ; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX11-NEXT: v_and_b32_e32 v30, 1, v30 ; GFX11-NEXT: s_waitcnt vmcnt(28) -; GFX11-NEXT: v_cndmask_b32_e32 v28, v34, v35, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26 -; GFX11-NEXT: v_and_b32_e32 v7, 1, v7 +; GFX11-NEXT: v_cndmask_b32_e32 v2, v34, v35, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 +; GFX11-NEXT: v_and_b32_e32 v23, 1, v23 ; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v35 ; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX11-NEXT: v_and_b32_e32 v28, 1, v28 ; GFX11-NEXT: s_waitcnt vmcnt(26) -; GFX11-NEXT: v_cndmask_b32_e32 v26, v36, v37, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24 -; GFX11-NEXT: v_and_b32_e32 v5, 1, v5 +; GFX11-NEXT: v_cndmask_b32_e32 v4, v36, v37, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 +; GFX11-NEXT: v_and_b32_e32 v25, 1, v25 ; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v37 ; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX11-NEXT: v_and_b32_e32 v26, 1, v26 ; GFX11-NEXT: s_waitcnt vmcnt(24) -; GFX11-NEXT: v_cndmask_b32_e32 v24, v38, v39, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22 -; GFX11-NEXT: v_and_b32_e32 v11, 1, v11 +; GFX11-NEXT: v_cndmask_b32_e32 v6, v38, v39, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 +; GFX11-NEXT: v_and_b32_e32 v19, 1, v19 ; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v39 ; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v38 -; GFX11-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX11-NEXT: v_and_b32_e32 v24, 1, v24 ; GFX11-NEXT: s_waitcnt vmcnt(22) -; GFX11-NEXT: v_cndmask_b32_e32 v22, v48, v49, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20 -; GFX11-NEXT: v_and_b32_e32 v9, 1, v9 +; GFX11-NEXT: v_cndmask_b32_e32 v8, v48, v49, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 +; GFX11-NEXT: v_and_b32_e32 v21, 1, v21 ; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v49 ; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v48 -; GFX11-NEXT: v_and_b32_e32 v8, 1, v8 +; GFX11-NEXT: v_and_b32_e32 v22, 1, v22 ; GFX11-NEXT: s_waitcnt vmcnt(20) -; GFX11-NEXT: v_cndmask_b32_e32 v20, v50, v51, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18 +; GFX11-NEXT: v_cndmask_b32_e32 v10, v50, v51, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX11-NEXT: v_and_b32_e32 v15, 1, v15 ; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v51 ; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v50 -; GFX11-NEXT: v_and_b32_e32 v10, 1, v10 +; GFX11-NEXT: v_and_b32_e32 v20, 1, v20 ; GFX11-NEXT: s_waitcnt vmcnt(18) -; GFX11-NEXT: v_cndmask_b32_e32 v18, v52, v53, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 -; GFX11-NEXT: v_and_b32_e32 v13, 1, v13 +; GFX11-NEXT: v_cndmask_b32_e32 v12, v52, v53, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 +; GFX11-NEXT: v_and_b32_e32 v17, 1, v17 ; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v53 ; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v52 -; GFX11-NEXT: v_and_b32_e32 v12, 1, v12 +; GFX11-NEXT: v_and_b32_e32 v18, 1, v18 ; GFX11-NEXT: s_waitcnt vmcnt(16) -; GFX11-NEXT: v_cndmask_b32_e32 v16, v54, v55, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v14, v54, v55, vcc_lo ; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v55 ; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v54 -; GFX11-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX11-NEXT: v_and_b32_e32 v16, 1, v16 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 ; GFX11-NEXT: s_waitcnt vmcnt(14) -; GFX11-NEXT: v_dual_cndmask_b32 v14, v64, v65 :: v_dual_and_b32 v19, 1, v19 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 -; GFX11-NEXT: v_and_b32_e32 v17, 1, v17 +; GFX11-NEXT: v_dual_cndmask_b32 v16, v64, v65 :: v_dual_and_b32 v11, 1, v11 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18 +; GFX11-NEXT: v_and_b32_e32 v13, 1, v13 ; GFX11-NEXT: v_lshrrev_b32_e32 v65, 16, v65 ; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v64 ; GFX11-NEXT: s_waitcnt vmcnt(12) -; GFX11-NEXT: v_cndmask_b32_e32 v12, v66, v67, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 -; GFX11-NEXT: v_and_b32_e32 v23, 1, v23 +; GFX11-NEXT: v_cndmask_b32_e32 v18, v66, v67, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20 +; GFX11-NEXT: v_and_b32_e32 v7, 1, v7 ; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v67 ; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v66 ; GFX11-NEXT: s_waitcnt vmcnt(10) -; GFX11-NEXT: v_cndmask_b32_e32 v10, v68, v69, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 -; GFX11-NEXT: v_and_b32_e32 v21, 1, v21 +; GFX11-NEXT: v_cndmask_b32_e32 v20, v68, v69, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22 +; GFX11-NEXT: v_and_b32_e32 v9, 1, v9 ; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v69 ; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v68 ; GFX11-NEXT: s_waitcnt vmcnt(8) -; GFX11-NEXT: v_cndmask_b32_e32 v8, v70, v71, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 -; GFX11-NEXT: v_and_b32_e32 v27, 1, v27 +; GFX11-NEXT: v_cndmask_b32_e32 v22, v70, v71, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24 +; GFX11-NEXT: v_and_b32_e32 v3, 1, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v71 ; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v70 ; GFX11-NEXT: s_waitcnt vmcnt(6) -; GFX11-NEXT: v_cndmask_b32_e32 v6, v80, v81, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 -; GFX11-NEXT: v_and_b32_e32 v25, 1, v25 +; GFX11-NEXT: v_cndmask_b32_e32 v24, v80, v81, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26 +; GFX11-NEXT: v_and_b32_e32 v5, 1, v5 ; GFX11-NEXT: v_lshrrev_b32_e32 v81, 16, v81 ; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v80 ; GFX11-NEXT: s_waitcnt vmcnt(4) -; GFX11-NEXT: v_cndmask_b32_e32 v4, v82, v83, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 +; GFX11-NEXT: v_cndmask_b32_e32 v26, v82, v83, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28 ; GFX11-NEXT: v_and_b32_e32 v31, 1, v31 ; GFX11-NEXT: v_lshrrev_b32_e32 v83, 16, v83 ; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v82 ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_cndmask_b32_e32 v2, v84, v85, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_and_b32_e32 v29, 1, v29 +; GFX11-NEXT: v_cndmask_b32_e32 v28, v84, v85, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v30 +; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v85 ; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v84 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v86, v87, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v31 +; GFX11-NEXT: v_cndmask_b32_e32 v30, v86, v87, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v87 ; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v86 -; GFX11-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29 -; GFX11-NEXT: v_cndmask_b32_e32 v29, v34, v35, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27 -; GFX11-NEXT: v_cndmask_b32_e32 v27, v36, v37, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25 -; GFX11-NEXT: v_cndmask_b32_e32 v25, v38, v39, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23 -; GFX11-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21 -; GFX11-NEXT: v_cndmask_b32_e32 v21, v50, v51, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v19, v52, v53, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 -; GFX11-NEXT: v_cndmask_b32_e32 v17, v54, v55, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v64, v65, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v13, v66, v67, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v11, v68, v69, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v80, v81, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v84, v85, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v86, v87, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v82, v83, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 +; GFX11-NEXT: v_cndmask_b32_e32 v3, v34, v35, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 ; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 -; GFX11-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 -; GFX11-NEXT: v_perm_b32 v6, v13, v12, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v5, v36, v37, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v70, v71, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v7, v38, v39, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 +; GFX11-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v9, v48, v49, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v11, v50, v51, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 ; GFX11-NEXT: v_perm_b32 v5, v11, v10, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v13, v52, v53, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_perm_b32 v6, v13, v12, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v15, v54, v55, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 ; GFX11-NEXT: v_perm_b32 v7, v15, v14, 0x5040100 -; GFX11-NEXT: v_perm_b32 v10, v21, v20, 0x5040100 -; GFX11-NEXT: v_perm_b32 v11, v23, v22, 0x5040100 -; GFX11-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v17, v64, v65, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v8, v17, v16, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v19, v66, v67, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21 ; GFX11-NEXT: v_perm_b32 v9, v19, v18, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v21, v68, v69, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_perm_b32 v10, v21, v20, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v23, v70, v71, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25 +; GFX11-NEXT: v_perm_b32 v11, v23, v22, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v25, v80, v81, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v12, v25, v24, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v27, v82, v83, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29 ; GFX11-NEXT: v_perm_b32 v13, v27, v26, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v29, v84, v85, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v31 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v14, v29, v28, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v31, v86, v87, vcc_lo ; GFX11-NEXT: v_perm_b32 v15, v31, v30, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = select <32 x i1> %cond, <32 x bfloat> %a, <32 x bfloat> %b -- GitLab From 67782d2de5ea9c8653b8f0110237a3c355291c0e Mon Sep 17 00:00:00 2001 From: SiHuaN Date: Mon, 8 Jan 2024 19:59:48 +0800 Subject: [PATCH 050/652] [flang] Remove duplicate tests. (#77059) --- flang/unittests/Runtime/ExternalIOTest.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/flang/unittests/Runtime/ExternalIOTest.cpp b/flang/unittests/Runtime/ExternalIOTest.cpp index 76fdb6cb68ae..13327964e12a 100644 --- a/flang/unittests/Runtime/ExternalIOTest.cpp +++ b/flang/unittests/Runtime/ExternalIOTest.cpp @@ -931,10 +931,6 @@ TEST(ExternalIOTests, BigUnitNumbers) { static_cast(std::numeric_limits::min()) - 1; EXPECT_EQ(IONAME(CheckUnitNumberInRange64)(unit64Ok, true), IostatOk); EXPECT_EQ(IONAME(CheckUnitNumberInRange64)(unit64Ok, false), IostatOk); - EXPECT_EQ( - IONAME(CheckUnitNumberInRange64)(unit64Bad, true), IostatUnitOverflow); - EXPECT_EQ( - IONAME(CheckUnitNumberInRange64)(unit64Bad2, true), IostatUnitOverflow); EXPECT_EQ( IONAME(CheckUnitNumberInRange64)(unit64Bad, true), IostatUnitOverflow); EXPECT_EQ( @@ -945,7 +941,7 @@ TEST(ExternalIOTests, BigUnitNumbers) { std::snprintf(expectedMsg, n, "UNIT number %jd is out of range", static_cast(unit64Bad)); EXPECT_DEATH( - IONAME(CheckUnitNumberInRange64)(2147483648, false), expectedMsg); + IONAME(CheckUnitNumberInRange64)(unit64Bad, false), expectedMsg); for (auto i{std::strlen(expectedMsg)}; i < n; ++i) { expectedMsg[i] = ' '; } -- GitLab From d218092543b3f9ba2204d7c8fe5ac70befa3d772 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Mon, 8 Jan 2024 20:08:42 +0800 Subject: [PATCH 051/652] [SCCP] Check whether the default case is reachable (#76295) This patch eliminates unreachable default cases using range information. Fixes #76085. --- llvm/lib/Transforms/Utils/SCCPSolver.cpp | 10 ++- llvm/test/Transforms/SCCP/switch.ll | 91 ++++++++++++++++++++---- 2 files changed, 86 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Transforms/Utils/SCCPSolver.cpp b/llvm/lib/Transforms/Utils/SCCPSolver.cpp index ab95698abc43..3dc6016a0a37 100644 --- a/llvm/lib/Transforms/Utils/SCCPSolver.cpp +++ b/llvm/lib/Transforms/Utils/SCCPSolver.cpp @@ -310,6 +310,7 @@ bool SCCPSolver::removeNonFeasibleEdges(BasicBlock *BB, DomTreeUpdater &DTU, new UnreachableInst(DefaultDest->getContext(), NewUnreachableBB); } + DefaultDest->removePredecessor(BB); SI->setDefaultDest(NewUnreachableBB); Updates.push_back({DominatorTree::Delete, BB, DefaultDest}); Updates.push_back({DominatorTree::Insert, BB, NewUnreachableBB}); @@ -1063,14 +1064,17 @@ void SCCPInstVisitor::getFeasibleSuccessors(Instruction &TI, // is ready. if (SCValue.isConstantRange(/*UndefAllowed=*/false)) { const ConstantRange &Range = SCValue.getConstantRange(); + unsigned ReachableCaseCount = 0; for (const auto &Case : SI->cases()) { const APInt &CaseValue = Case.getCaseValue()->getValue(); - if (Range.contains(CaseValue)) + if (Range.contains(CaseValue)) { Succs[Case.getSuccessorIndex()] = true; + ++ReachableCaseCount; + } } - // TODO: Determine whether default case is reachable. - Succs[SI->case_default()->getSuccessorIndex()] = true; + Succs[SI->case_default()->getSuccessorIndex()] = + Range.isSizeLargerThan(ReachableCaseCount); return; } diff --git a/llvm/test/Transforms/SCCP/switch.ll b/llvm/test/Transforms/SCCP/switch.ll index 19e72217fd03..306f0eebf2b4 100644 --- a/llvm/test/Transforms/SCCP/switch.ll +++ b/llvm/test/Transforms/SCCP/switch.ll @@ -4,6 +4,8 @@ ; Make sure we always consider the default edge executable for a switch ; with no cases. declare void @foo() +declare i32 @g(i32) + define void @test1() { ; CHECK-LABEL: @test1( ; CHECK-NEXT: switch i32 undef, label [[D:%.*]] [ @@ -115,17 +117,16 @@ switch.1: ret i32 %phi } -; TODO: Determine that the default destination is dead. define i32 @test_local_range(ptr %p) { ; CHECK-LABEL: @test_local_range( ; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P:%.*]], align 4, !range [[RNG0]] -; CHECK-NEXT: switch i32 [[X]], label [[SWITCH_DEFAULT:%.*]] [ +; CHECK-NEXT: switch i32 [[X]], label [[DEFAULT_UNREACHABLE:%.*]] [ ; CHECK-NEXT: i32 0, label [[SWITCH_0:%.*]] ; CHECK-NEXT: i32 1, label [[SWITCH_1:%.*]] ; CHECK-NEXT: i32 2, label [[SWITCH_2:%.*]] ; CHECK-NEXT: ] -; CHECK: switch.default: -; CHECK-NEXT: ret i32 -1 +; CHECK: default.unreachable: +; CHECK-NEXT: unreachable ; CHECK: switch.0: ; CHECK-NEXT: ret i32 0 ; CHECK: switch.1: @@ -161,14 +162,14 @@ switch.3: define i32 @test_duplicate_successors(ptr %p) { ; CHECK-LABEL: @test_duplicate_successors( ; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P:%.*]], align 4, !range [[RNG0]] -; CHECK-NEXT: switch i32 [[X]], label [[SWITCH_DEFAULT:%.*]] [ +; CHECK-NEXT: switch i32 [[X]], label [[DEFAULT_UNREACHABLE:%.*]] [ ; CHECK-NEXT: i32 0, label [[SWITCH_0:%.*]] ; CHECK-NEXT: i32 1, label [[SWITCH_0]] ; CHECK-NEXT: i32 2, label [[SWITCH_1:%.*]] ; CHECK-NEXT: i32 3, label [[SWITCH_1]] ; CHECK-NEXT: ] -; CHECK: switch.default: -; CHECK-NEXT: ret i32 -1 +; CHECK: default.unreachable: +; CHECK-NEXT: unreachable ; CHECK: switch.0: ; CHECK-NEXT: ret i32 0 ; CHECK: switch.1: @@ -201,13 +202,13 @@ switch.2: ; range information. define internal i32 @test_ip_range(i32 %x) { ; CHECK-LABEL: @test_ip_range( -; CHECK-NEXT: switch i32 [[X:%.*]], label [[SWITCH_DEFAULT:%.*]] [ +; CHECK-NEXT: switch i32 [[X:%.*]], label [[DEFAULT_UNREACHABLE:%.*]] [ ; CHECK-NEXT: i32 3, label [[SWITCH_3:%.*]] ; CHECK-NEXT: i32 1, label [[SWITCH_1:%.*]] ; CHECK-NEXT: i32 2, label [[SWITCH_2:%.*]] ; CHECK-NEXT: ], !prof [[PROF1:![0-9]+]] -; CHECK: switch.default: -; CHECK-NEXT: ret i32 -1 +; CHECK: default.unreachable: +; CHECK-NEXT: unreachable ; CHECK: switch.1: ; CHECK-NEXT: ret i32 1 ; CHECK: switch.2: @@ -240,8 +241,8 @@ switch.3: define void @call_test_ip_range() { ; CHECK-LABEL: @call_test_ip_range( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @test_ip_range(i32 1) -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @test_ip_range(i32 3) +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @test_ip_range(i32 1), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @test_ip_range(i32 3), !range [[RNG2]] ; CHECK-NEXT: ret void ; call i32 @test_ip_range(i32 1) @@ -301,6 +302,72 @@ end.2: ret i32 20 } +define i32 @test_default_unreachable_by_dom_cond(i32 %x) { +; CHECK-LABEL: @test_default_unreachable_by_dom_cond( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[OR_COND:%.*]] = icmp ult i32 [[X:%.*]], 4 +; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_THEN:%.*]], label [[RETURN:%.*]] +; CHECK: if.then: +; CHECK-NEXT: switch i32 [[X]], label [[DEFAULT_UNREACHABLE:%.*]] [ +; CHECK-NEXT: i32 0, label [[SW_BB:%.*]] +; CHECK-NEXT: i32 1, label [[SW_BB2:%.*]] +; CHECK-NEXT: i32 2, label [[SW_BB4:%.*]] +; CHECK-NEXT: i32 3, label [[SW_BB6:%.*]] +; CHECK-NEXT: ] +; CHECK: sw.bb: +; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @g(i32 2) +; CHECK-NEXT: br label [[RETURN]] +; CHECK: sw.bb2: +; CHECK-NEXT: [[CALL3:%.*]] = tail call i32 @g(i32 3) +; CHECK-NEXT: br label [[RETURN]] +; CHECK: sw.bb4: +; CHECK-NEXT: [[CALL5:%.*]] = tail call i32 @g(i32 4) +; CHECK-NEXT: br label [[RETURN]] +; CHECK: sw.bb6: +; CHECK-NEXT: [[CALL7:%.*]] = tail call i32 @g(i32 5) +; CHECK-NEXT: br label [[RETURN]] +; CHECK: default.unreachable: +; CHECK-NEXT: unreachable +; CHECK: return: +; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL7]], [[SW_BB6]] ], [ [[CALL5]], [[SW_BB4]] ], [ [[CALL3]], [[SW_BB2]] ], [ [[CALL]], [[SW_BB]] ], [ -23, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i32 [[RETVAL_0]] +; +entry: + %or.cond = icmp ult i32 %x, 4 + br i1 %or.cond, label %if.then, label %return + +if.then: + switch i32 %x, label %sw.epilog [ + i32 0, label %sw.bb + i32 1, label %sw.bb2 + i32 2, label %sw.bb4 + i32 3, label %sw.bb6 + ] + +sw.bb: + %call = tail call i32 @g(i32 2) + br label %return + +sw.bb2: + %call3 = tail call i32 @g(i32 3) + br label %return + +sw.bb4: + %call5 = tail call i32 @g(i32 4) + br label %return + +sw.bb6: + %call7 = tail call i32 @g(i32 5) + br label %return + +sw.epilog: + call void @foo() + br label %return + +return: + %retval.0 = phi i32 [ %call7, %sw.bb6 ], [ %call5, %sw.bb4 ], [ %call3, %sw.bb2 ], [ %call, %sw.bb ], [ -23, %sw.epilog ], [ -23, %entry ] + ret i32 %retval.0 +} declare void @llvm.assume(i1) -- GitLab From 8b49ed8ba1ba5ecd35bd1efa4be5a0f56b0135b8 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 8 Jan 2024 12:10:51 +0000 Subject: [PATCH 052/652] [lldb][test] Skip DWARF inline source file test on Windows This was added by 917b404e2ccdcc31d2d64971ad094b80967a240b and fails for unknown reasons. --- .../functionalities/inline-sourcefile/TestInlineSourceFiles.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py b/lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py index 20ed0ce00661..ad10a63e6013 100644 --- a/lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py +++ b/lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py @@ -8,6 +8,8 @@ from lldbsuite.test import lldbutil class InlineSourceFilesTestCase(TestBase): @skipIf(compiler="gcc") @skipIf(compiler="clang", compiler_version=["<", "18.0"]) + # Fails on Windows for unknown reasons. + @skipIfWindows def test(self): """Test DWARF inline source files.""" self.build() -- GitLab From ba4cf31facdaf9bb9943c057d325ff0968331e9a Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 8 Jan 2024 12:17:16 +0000 Subject: [PATCH 053/652] [lldb][test] Skip part of nested expressions test on Windows This was added by e42edb5547618c172abe25914000bb61f5278c4c and has been failing: https://lab.llvm.org/buildbot/#/builders/219/builds/8012 --- .../API/commands/expression/nested/TestNestedExpressions.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lldb/test/API/commands/expression/nested/TestNestedExpressions.py b/lldb/test/API/commands/expression/nested/TestNestedExpressions.py index 7f194e921e56..6a97d4f34e67 100644 --- a/lldb/test/API/commands/expression/nested/TestNestedExpressions.py +++ b/lldb/test/API/commands/expression/nested/TestNestedExpressions.py @@ -33,6 +33,8 @@ class NestedExpressions(TestBase): self.expect_expr("sizeof(A::B::C)", result_value="1") self.expect_expr("sizeof(A::B)", result_value="2") + # Fails on Windows for unknown reasons. + @skipIfWindows def test_static_in_nested_structs(self): """ Test expressions that references a static variable in nested structs. -- GitLab From eb523a4d272e81c8f7bf48da3923ed502f41c187 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:33:47 +0000 Subject: [PATCH 054/652] [X86] vec_extract - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. --- llvm/test/CodeGen/X86/vec_extract-avx.ll | 122 +++++++++++----------- llvm/test/CodeGen/X86/vec_extract-mmx.ll | 66 ++++++------ llvm/test/CodeGen/X86/vec_extract-sse4.ll | 50 ++++----- llvm/test/CodeGen/X86/vec_extract.ll | 86 +++++++-------- 4 files changed, 162 insertions(+), 162 deletions(-) diff --git a/llvm/test/CodeGen/X86/vec_extract-avx.ll b/llvm/test/CodeGen/X86/vec_extract-avx.ll index 6ca4e73d2f98..341a703a21bd 100644 --- a/llvm/test/CodeGen/X86/vec_extract-avx.ll +++ b/llvm/test/CodeGen/X86/vec_extract-avx.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 ; When extracting multiple consecutive elements from a larger @@ -9,12 +9,12 @@ ; Extracting the low elements only requires using the right kind of store. define void @low_v8f32_to_v4f32(<8 x float> %v, ptr %ptr) { -; X32-LABEL: low_v8f32_to_v4f32: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vmovaps %xmm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: low_v8f32_to_v4f32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vmovaps %xmm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: low_v8f32_to_v4f32: ; X64: # %bb.0: @@ -35,12 +35,12 @@ define void @low_v8f32_to_v4f32(<8 x float> %v, ptr %ptr) { ; Extracting the high elements requires just one AVX instruction. define void @high_v8f32_to_v4f32(<8 x float> %v, ptr %ptr) { -; X32-LABEL: high_v8f32_to_v4f32: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vextractf128 $1, %ymm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: high_v8f32_to_v4f32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vextractf128 $1, %ymm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: high_v8f32_to_v4f32: ; X64: # %bb.0: @@ -63,12 +63,12 @@ define void @high_v8f32_to_v4f32(<8 x float> %v, ptr %ptr) { ; if we were actually using the vector in this function and ; have AVX2, we should generate vextracti128 (the int version). define void @high_v8i32_to_v4i32(<8 x i32> %v, ptr %ptr) { -; X32-LABEL: high_v8i32_to_v4i32: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vextractf128 $1, %ymm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: high_v8i32_to_v4i32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vextractf128 $1, %ymm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: high_v8i32_to_v4i32: ; X64: # %bb.0: @@ -89,12 +89,12 @@ define void @high_v8i32_to_v4i32(<8 x i32> %v, ptr %ptr) { ; Make sure that element size doesn't alter the codegen. define void @high_v4f64_to_v2f64(<4 x double> %v, ptr %ptr) { -; X32-LABEL: high_v4f64_to_v2f64: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vextractf128 $1, %ymm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: high_v4f64_to_v2f64: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vextractf128 $1, %ymm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: high_v4f64_to_v2f64: ; X64: # %bb.0: @@ -113,16 +113,16 @@ define void @high_v4f64_to_v2f64(<4 x double> %v, ptr %ptr) { ; FIXME - Ideally these should just call VMOVD/VMOVQ/VMOVSS/VMOVSD define void @legal_vzmovl_2i32_8i32(ptr %in, ptr %out) { -; X32-LABEL: legal_vzmovl_2i32_8i32: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1 -; X32-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] -; X32-NEXT: vmovaps %ymm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: legal_vzmovl_2i32_8i32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; X86-NEXT: vmovaps %ymm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: legal_vzmovl_2i32_8i32: ; X64: # %bb.0: @@ -140,14 +140,14 @@ define void @legal_vzmovl_2i32_8i32(ptr %in, ptr %out) { } define void @legal_vzmovl_2i64_4i64(ptr %in, ptr %out) { -; X32-LABEL: legal_vzmovl_2i64_4i64: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: vmovaps %ymm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: legal_vzmovl_2i64_4i64: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vmovaps %ymm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: legal_vzmovl_2i64_4i64: ; X64: # %bb.0: @@ -163,16 +163,16 @@ define void @legal_vzmovl_2i64_4i64(ptr %in, ptr %out) { } define void @legal_vzmovl_2f32_8f32(ptr %in, ptr %out) { -; X32-LABEL: legal_vzmovl_2f32_8f32: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1 -; X32-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] -; X32-NEXT: vmovaps %ymm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: legal_vzmovl_2f32_8f32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; X86-NEXT: vmovaps %ymm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: legal_vzmovl_2f32_8f32: ; X64: # %bb.0: @@ -190,14 +190,14 @@ define void @legal_vzmovl_2f32_8f32(ptr %in, ptr %out) { } define void @legal_vzmovl_2f64_4f64(ptr %in, ptr %out) { -; X32-LABEL: legal_vzmovl_2f64_4f64: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: vmovaps %ymm0, (%eax) -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: legal_vzmovl_2f64_4f64: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vmovaps %ymm0, (%eax) +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: legal_vzmovl_2f64_4f64: ; X64: # %bb.0: diff --git a/llvm/test/CodeGen/X86/vec_extract-mmx.ll b/llvm/test/CodeGen/X86/vec_extract-mmx.ll index d9afc6f45931..672b4591316c 100644 --- a/llvm/test/CodeGen/X86/vec_extract-mmx.ll +++ b/llvm/test/CodeGen/X86/vec_extract-mmx.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64 define i32 @test0(ptr %v4) nounwind { -; X32-LABEL: test0: -; X32: # %bb.0: # %entry -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: pshufw $238, (%eax), %mm0 # mm0 = mem[2,3,2,3] -; X32-NEXT: movd %mm0, %eax -; X32-NEXT: addl $32, %eax -; X32-NEXT: retl +; X86-LABEL: test0: +; X86: # %bb.0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: pshufw $238, (%eax), %mm0 # mm0 = mem[2,3,2,3] +; X86-NEXT: movd %mm0, %eax +; X86-NEXT: addl $32, %eax +; X86-NEXT: retl ; ; X64-LABEL: test0: ; X64: # %bb.0: # %entry @@ -32,14 +32,14 @@ entry: } define i32 @test1(ptr nocapture readonly %ptr) nounwind { -; X32-LABEL: test1: -; X32: # %bb.0: # %entry -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movd (%eax), %mm0 -; X32-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3] -; X32-NEXT: movd %mm0, %eax -; X32-NEXT: emms -; X32-NEXT: retl +; X86-LABEL: test1: +; X86: # %bb.0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movd (%eax), %mm0 +; X86-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3] +; X86-NEXT: movd %mm0, %eax +; X86-NEXT: emms +; X86-NEXT: retl ; ; X64-LABEL: test1: ; X64: # %bb.0: # %entry @@ -67,13 +67,13 @@ entry: } define i32 @test2(ptr nocapture readonly %ptr) nounwind { -; X32-LABEL: test2: -; X32: # %bb.0: # %entry -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: pshufw $232, (%eax), %mm0 # mm0 = mem[0,2,2,3] -; X32-NEXT: movd %mm0, %eax -; X32-NEXT: emms -; X32-NEXT: retl +; X86-LABEL: test2: +; X86: # %bb.0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: pshufw $232, (%eax), %mm0 # mm0 = mem[0,2,2,3] +; X86-NEXT: movd %mm0, %eax +; X86-NEXT: emms +; X86-NEXT: retl ; ; X64-LABEL: test2: ; X64: # %bb.0: # %entry @@ -94,10 +94,10 @@ entry: } define i32 @test3(x86_mmx %a) nounwind { -; X32-LABEL: test3: -; X32: # %bb.0: -; X32-NEXT: movd %mm0, %eax -; X32-NEXT: retl +; X86-LABEL: test3: +; X86: # %bb.0: +; X86-NEXT: movd %mm0, %eax +; X86-NEXT: retl ; ; X64-LABEL: test3: ; X64: # %bb.0: @@ -110,12 +110,12 @@ define i32 @test3(x86_mmx %a) nounwind { ; Verify we don't muck with extractelts from the upper lane. define i32 @test4(x86_mmx %a) nounwind { -; X32-LABEL: test4: -; X32: # %bb.0: -; X32-NEXT: movq2dq %mm0, %xmm0 -; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] -; X32-NEXT: movd %xmm0, %eax -; X32-NEXT: retl +; X86-LABEL: test4: +; X86: # %bb.0: +; X86-NEXT: movq2dq %mm0, %xmm0 +; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] +; X86-NEXT: movd %xmm0, %eax +; X86-NEXT: retl ; ; X64-LABEL: test4: ; X64: # %bb.0: diff --git a/llvm/test/CodeGen/X86/vec_extract-sse4.ll b/llvm/test/CodeGen/X86/vec_extract-sse4.ll index ea444d3a00af..1f384861b373 100644 --- a/llvm/test/CodeGen/X86/vec_extract-sse4.ll +++ b/llvm/test/CodeGen/X86/vec_extract-sse4.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64 define void @t1(ptr %R, ptr %P1) nounwind { -; X32-LABEL: t1: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32-NEXT: movss %xmm0, (%eax) -; X32-NEXT: retl +; X86-LABEL: t1: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss %xmm0, (%eax) +; X86-NEXT: retl ; ; X64-LABEL: t1: ; X64: # %bb.0: @@ -23,11 +23,11 @@ define void @t1(ptr %R, ptr %P1) nounwind { } define float @t2(ptr %P1) nounwind { -; X32-LABEL: t2: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: flds 8(%eax) -; X32-NEXT: retl +; X86-LABEL: t2: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: flds 8(%eax) +; X86-NEXT: retl ; ; X64-LABEL: t2: ; X64: # %bb.0: @@ -39,13 +39,13 @@ define float @t2(ptr %P1) nounwind { } define void @t3(ptr %R, ptr %P1) nounwind { -; X32-LABEL: t3: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movl 12(%ecx), %ecx -; X32-NEXT: movl %ecx, (%eax) -; X32-NEXT: retl +; X86-LABEL: t3: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl 12(%ecx), %ecx +; X86-NEXT: movl %ecx, (%eax) +; X86-NEXT: retl ; ; X64-LABEL: t3: ; X64: # %bb.0: @@ -59,11 +59,11 @@ define void @t3(ptr %R, ptr %P1) nounwind { } define i32 @t4(ptr %P1) nounwind { -; X32-LABEL: t4: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl 12(%eax), %eax -; X32-NEXT: retl +; X86-LABEL: t4: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl 12(%eax), %eax +; X86-NEXT: retl ; ; X64-LABEL: t4: ; X64: # %bb.0: diff --git a/llvm/test/CodeGen/X86/vec_extract.ll b/llvm/test/CodeGen/X86/vec_extract.ll index e753019593d8..087cd30abee9 100644 --- a/llvm/test/CodeGen/X86/vec_extract.ll +++ b/llvm/test/CodeGen/X86/vec_extract.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64 define void @test1(ptr %F, ptr %f) nounwind { -; X32-LABEL: test1: -; X32: # %bb.0: # %entry -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32-NEXT: addss %xmm0, %xmm0 -; X32-NEXT: movss %xmm0, (%eax) -; X32-NEXT: retl +; X86-LABEL: test1: +; X86: # %bb.0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: addss %xmm0, %xmm0 +; X86-NEXT: movss %xmm0, (%eax) +; X86-NEXT: retl ; ; X64-LABEL: test1: ; X64: # %bb.0: # %entry @@ -27,17 +27,17 @@ entry: } define float @test2(ptr %F, ptr %f) nounwind { -; X32-LABEL: test2: -; X32: # %bb.0: # %entry -; X32-NEXT: pushl %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movaps (%eax), %xmm0 -; X32-NEXT: addps %xmm0, %xmm0 -; X32-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] -; X32-NEXT: movss %xmm0, (%esp) -; X32-NEXT: flds (%esp) -; X32-NEXT: popl %eax -; X32-NEXT: retl +; X86-LABEL: test2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movaps (%eax), %xmm0 +; X86-NEXT: addps %xmm0, %xmm0 +; X86-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl ; ; X64-LABEL: test2: ; X64: # %bb.0: # %entry @@ -53,14 +53,14 @@ entry: } define void @test3(ptr %R, ptr %P1) nounwind { -; X32-LABEL: test3: -; X32: # %bb.0: # %entry -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movaps (%ecx), %xmm0 -; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] -; X32-NEXT: movss %xmm0, (%eax) -; X32-NEXT: retl +; X86-LABEL: test3: +; X86: # %bb.0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movaps (%ecx), %xmm0 +; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] +; X86-NEXT: movss %xmm0, (%eax) +; X86-NEXT: retl ; ; X64-LABEL: test3: ; X64: # %bb.0: # %entry @@ -76,16 +76,16 @@ entry: } define double @test4(double %A) nounwind { -; X32-LABEL: test4: -; X32: # %bb.0: # %entry -; X32-NEXT: subl $12, %esp -; X32-NEXT: calll foo@PLT -; X32-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] -; X32-NEXT: addsd {{[0-9]+}}(%esp), %xmm0 -; X32-NEXT: movsd %xmm0, (%esp) -; X32-NEXT: fldl (%esp) -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test4: +; X86: # %bb.0: # %entry +; X86-NEXT: subl $12, %esp +; X86-NEXT: calll foo@PLT +; X86-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] +; X86-NEXT: addsd {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: movsd %xmm0, (%esp) +; X86-NEXT: fldl (%esp) +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; ; X64-LABEL: test4: ; X64: # %bb.0: # %entry @@ -107,11 +107,11 @@ declare <2 x double> @foo() ; OSS-Fuzz #15662 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15662 define <4 x i32> @ossfuzz15662(ptr %in) { -; X32-LABEL: ossfuzz15662: -; X32: # %bb.0: -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, (%eax) -; X32-NEXT: retl +; X86-LABEL: ossfuzz15662: +; X86: # %bb.0: +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, (%eax) +; X86-NEXT: retl ; ; X64-LABEL: ossfuzz15662: ; X64: # %bb.0: -- GitLab From e3f8e44b00ecb95818bc68c693b6637460112b2a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:35:48 +0000 Subject: [PATCH 055/652] [X86] vector-lzcnt-256.ll / vector-tzcnt-256.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. --- llvm/test/CodeGen/X86/vector-lzcnt-256.ll | 394 +++++++++++----------- llvm/test/CodeGen/X86/vector-tzcnt-256.ll | 302 ++++++++--------- 2 files changed, 348 insertions(+), 348 deletions(-) diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-256.ll b/llvm/test/CodeGen/X86/vector-lzcnt-256.ll index 3c53d211bae5..fe6836c045f3 100644 --- a/llvm/test/CodeGen/X86/vector-lzcnt-256.ll +++ b/llvm/test/CodeGen/X86/vector-lzcnt-256.ll @@ -7,7 +7,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512cd | FileCheck %s --check-prefixes=X64,AVX512,AVX512CD ; ; Just one 32-bit run to make sure we do reasonable things for i64 lzcnt. -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32-AVX +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X86-AVX define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX1-LABEL: testv4i64: @@ -162,34 +162,34 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: retq ; -; X32-AVX-LABEL: testv4i64: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 -; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 -; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 -; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 -; X32-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm2 -; X32-AVX-NEXT: vpsrld $16, %ymm2, %ymm2 -; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddd %ymm2, %ymm1, %ymm1 -; X32-AVX-NEXT: vpcmpeqd %ymm4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsrlq $32, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrlq $32, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddq %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv4i64: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 +; X86-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 +; X86-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 +; X86-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 +; X86-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm2 +; X86-AVX-NEXT: vpsrld $16, %ymm2, %ymm2 +; X86-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddd %ymm2, %ymm1, %ymm1 +; X86-AVX-NEXT: vpcmpeqd %ymm4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsrlq $32, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrlq $32, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddq %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %in, i1 0) ret <4 x i64> %out @@ -348,34 +348,34 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: retq ; -; X32-AVX-LABEL: testv4i64u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 -; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 -; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 -; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 -; X32-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm2 -; X32-AVX-NEXT: vpsrld $16, %ymm2, %ymm2 -; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddd %ymm2, %ymm1, %ymm1 -; X32-AVX-NEXT: vpcmpeqd %ymm4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsrlq $32, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrlq $32, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddq %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv4i64u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 +; X86-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 +; X86-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 +; X86-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 +; X86-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm2 +; X86-AVX-NEXT: vpsrld $16, %ymm2, %ymm2 +; X86-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddd %ymm2, %ymm1, %ymm1 +; X86-AVX-NEXT: vpcmpeqd %ymm4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsrlq $32, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrlq $32, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddq %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %in, i1 -1) ret <4 x i64> %out @@ -509,29 +509,29 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: retq ; -; X32-AVX-LABEL: testv8i32: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 -; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 -; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 -; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 -; X32-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsrld $16, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddd %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv8i32: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 +; X86-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 +; X86-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 +; X86-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 +; X86-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsrld $16, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddd %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: retl %out = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %in, i1 0) ret <8 x i32> %out @@ -665,29 +665,29 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: retq ; -; X32-AVX-LABEL: testv8i32u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 -; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 -; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 -; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 -; X32-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsrld $16, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddd %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv8i32u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 +; X86-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 +; X86-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 +; X86-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm2, %ymm1, %ymm1 +; X86-AVX-NEXT: vpcmpeqw %ymm4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsrld $16, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrld $16, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddd %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: retl %out = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %in, i1 -1) ret <8 x i32> %out @@ -792,24 +792,24 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; AVX512-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: retq ; -; X32-AVX-LABEL: testv16i16: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 -; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 -; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv16i16: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 +; X86-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 +; X86-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: retl %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %in, i1 0) ret <16 x i16> %out } @@ -913,24 +913,24 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind { ; AVX512-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: retq ; -; X32-AVX-LABEL: testv16i16u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 -; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 -; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 -; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv16i16u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3 +; X86-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 +; X86-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; X86-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: retl %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %in, i1 -1) ret <16 x i16> %out } @@ -1014,19 +1014,19 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; AVX512-NEXT: vpsubb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: retq ; -; X32-AVX-LABEL: testv32i8: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 -; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv32i8: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 +; X86-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; X86-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0 +; X86-AVX-NEXT: retl %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 0) ret <32 x i8> %out } @@ -1110,19 +1110,19 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; AVX512-NEXT: vpsubb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: retq ; -; X32-AVX-LABEL: testv32i8u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; X32-AVX-NEXT: # ymm1 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 -; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3 -; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv32i8u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; X86-AVX-NEXT: # ymm1 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 +; X86-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; X86-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3 +; X86-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0 +; X86-AVX-NEXT: retl %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 -1) ret <32 x i8> %out } @@ -1133,10 +1133,10 @@ define <4 x i64> @foldv4i64() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv4i64: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,0,0,64,0,56,0] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv4i64: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,0,0,64,0,56,0] +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> , i1 0) ret <4 x i64> %out } @@ -1147,10 +1147,10 @@ define <4 x i64> @foldv4i64u() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv4i64u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,0,0,64,0,56,0] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv4i64u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,0,0,64,0,56,0] +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> , i1 -1) ret <4 x i64> %out } @@ -1161,10 +1161,10 @@ define <8 x i32> @foldv8i32() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv8i32: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv8i32: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25] +; X86-AVX-NEXT: retl %out = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> , i1 0) ret <8 x i32> %out } @@ -1175,10 +1175,10 @@ define <8 x i32> @foldv8i32u() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv8i32u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv8i32u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25] +; X86-AVX-NEXT: retl %out = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> , i1 -1) ret <8 x i32> %out } @@ -1189,10 +1189,10 @@ define <16 x i16> @foldv16i16() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [7,0,16,8,16,13,11,9,0,8,15,14,13,12,11,10] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv16i16: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [7,0,16,8,16,13,11,9,0,8,15,14,13,12,11,10] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv16i16: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [7,0,16,8,16,13,11,9,0,8,15,14,13,12,11,10] +; X86-AVX-NEXT: retl %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> , i1 0) ret <16 x i16> %out } @@ -1203,10 +1203,10 @@ define <16 x i16> @foldv16i16u() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [7,0,16,8,16,13,11,9,0,8,15,14,13,12,11,10] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv16i16u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [7,0,16,8,16,13,11,9,0,8,15,14,13,12,11,10] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv16i16u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [7,0,16,8,16,13,11,9,0,8,15,14,13,12,11,10] +; X86-AVX-NEXT: retl %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> , i1 -1) ret <16 x i16> %out } @@ -1217,10 +1217,10 @@ define <32 x i8> @foldv32i8() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,5,3,1,0,0,7,6,5,4,3,2,1,0,8,8,0,0,0,0,0,0,0,0,6,5,5,1] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv32i8: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,5,3,1,0,0,7,6,5,4,3,2,1,0,8,8,0,0,0,0,0,0,0,0,6,5,5,1] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv32i8: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,5,3,1,0,0,7,6,5,4,3,2,1,0,8,8,0,0,0,0,0,0,0,0,6,5,5,1] +; X86-AVX-NEXT: retl %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> , i1 0) ret <32 x i8> %out } @@ -1231,10 +1231,10 @@ define <32 x i8> @foldv32i8u() nounwind { ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,5,3,1,0,0,7,6,5,4,3,2,1,0,8,8,0,0,0,0,0,0,0,0,6,5,5,1] ; X64-NEXT: retq ; -; X32-AVX-LABEL: foldv32i8u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,5,3,1,0,0,7,6,5,4,3,2,1,0,8,8,0,0,0,0,0,0,0,0,6,5,5,1] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv32i8u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,8,0,8,5,3,1,0,0,7,6,5,4,3,2,1,0,8,8,0,0,0,0,0,0,0,0,6,5,5,1] +; X86-AVX-NEXT: retl %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> , i1 -1) ret <32 x i8> %out } diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-256.ll b/llvm/test/CodeGen/X86/vector-tzcnt-256.ll index cf3803aa460e..5bcdf0e22a5a 100644 --- a/llvm/test/CodeGen/X86/vector-tzcnt-256.ll +++ b/llvm/test/CodeGen/X86/vector-tzcnt-256.ll @@ -9,7 +9,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bitalg,+avx512vl | FileCheck %s --check-prefixes=ALL,BITALG ; ; Just one 32-bit run to make sure we do reasonable things for i64 tzcnt. -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,X32-AVX +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,X86-AVX define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX1-LABEL: testv4i64: @@ -115,23 +115,23 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv4i64: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddq %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; X32-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv4i64: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddq %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X86-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %in, i1 0) ret <4 x i64> %out } @@ -240,23 +240,23 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; BITALG-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv4i64u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddq %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; X32-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv4i64u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddq %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X86-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %in, i1 -1) ret <4 x i64> %out } @@ -385,27 +385,27 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv8i32: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; X32-AVX-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] -; X32-AVX-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 -; X32-AVX-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] -; X32-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv8i32: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X86-AVX-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] +; X86-AVX-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 +; X86-AVX-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] +; X86-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %in, i1 0) ret <8 x i32> %out } @@ -534,27 +534,27 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; BITALG-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv8i32u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; X32-AVX-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] -; X32-AVX-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 -; X32-AVX-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] -; X32-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv8i32u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X86-AVX-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] +; X86-AVX-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 +; X86-AVX-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] +; X86-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %in, i1 -1) ret <8 x i32> %out } @@ -685,24 +685,24 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; BITALG-NEXT: vpopcntw %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv16i16: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsllw $8, %ymm0, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv16i16: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsllw $8, %ymm0, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %in, i1 0) ret <16 x i16> %out } @@ -833,24 +833,24 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind { ; BITALG-NEXT: vpopcntw %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv16i16u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: vpsllw $8, %ymm0, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0 -; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv16i16u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: vpsllw $8, %ymm0, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0 +; X86-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %in, i1 -1) ret <16 x i16> %out } @@ -978,21 +978,21 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; BITALG-NEXT: vpopcntb %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv32i8: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv32i8: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 0) ret <32 x i8> %out } @@ -1120,21 +1120,21 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; BITALG-NEXT: vpopcntb %ymm0, %ymm0 ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: testv32i8u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; X32-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm1 -; X32-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 -; X32-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; X32-AVX-NEXT: # ymm3 = mem[0,1,0,1] -; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 -; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 -; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; X32-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: testv32i8u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; X86-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm1 +; X86-AVX-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpbroadcastb {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 +; X86-AVX-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; X86-AVX-NEXT: # ymm3 = mem[0,1,0,1] +; X86-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; X86-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 +; X86-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 +; X86-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; X86-AVX-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; X86-AVX-NEXT: retl %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 -1) ret <32 x i8> %out } @@ -1155,10 +1155,10 @@ define <4 x i64> @foldv4i64() nounwind { ; BITALG-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0] ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: foldv4i64: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,0,0,64,0,0,0] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv4i64: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,0,0,64,0,0,0] +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> , i1 0) ret <4 x i64> %out } @@ -1179,10 +1179,10 @@ define <4 x i64> @foldv4i64u() nounwind { ; BITALG-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0] ; BITALG-NEXT: retq ; -; X32-AVX-LABEL: foldv4i64u: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,0,0,64,0,0,0] -; X32-AVX-NEXT: retl +; X86-AVX-LABEL: foldv4i64u: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,0,0,64,0,0,0] +; X86-AVX-NEXT: retl %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> , i1 -1) ret <4 x i64> %out } -- GitLab From f1e3a8f1eb7877b07d386af1a02cd7578a76c7d1 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:37:06 +0000 Subject: [PATCH 056/652] [X86] avx2-gather.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. --- llvm/test/CodeGen/X86/avx2-gather.ll | 106 +++++++++++++-------------- 1 file changed, 53 insertions(+), 53 deletions(-) diff --git a/llvm/test/CodeGen/X86/avx2-gather.ll b/llvm/test/CodeGen/X86/avx2-gather.ll index e02ae09a0981..4b77edefa820 100644 --- a/llvm/test/CodeGen/X86/avx2-gather.ll +++ b/llvm/test/CodeGen/X86/avx2-gather.ll @@ -1,18 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, ptr, <4 x i32>, <4 x float>, i8) nounwind readonly define <4 x float> @test_x86_avx2_gather_d_ps(ptr %a1, <4 x i32> %idx, <4 x float> %mask) { -; X32-LABEL: test_x86_avx2_gather_d_ps: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; X32-NEXT: vgatherdps %xmm1, (%eax,%xmm0,2), %xmm2 -; X32-NEXT: vmovaps %xmm2, %xmm0 -; X32-NEXT: retl +; X86-LABEL: test_x86_avx2_gather_d_ps: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; X86-NEXT: vgatherdps %xmm1, (%eax,%xmm0,2), %xmm2 +; X86-NEXT: vmovaps %xmm2, %xmm0 +; X86-NEXT: retl ; ; X64-LABEL: test_x86_avx2_gather_d_ps: ; X64: # %bb.0: @@ -29,13 +29,13 @@ declare <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double>, ptr, <4 x i32>, <2 x double>, i8) nounwind readonly define <2 x double> @test_x86_avx2_gather_d_pd(ptr %a1, <4 x i32> %idx, <2 x double> %mask) { -; X32-LABEL: test_x86_avx2_gather_d_pd: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vxorpd %xmm2, %xmm2, %xmm2 -; X32-NEXT: vgatherdpd %xmm1, (%eax,%xmm0,2), %xmm2 -; X32-NEXT: vmovapd %xmm2, %xmm0 -; X32-NEXT: retl +; X86-LABEL: test_x86_avx2_gather_d_pd: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vxorpd %xmm2, %xmm2, %xmm2 +; X86-NEXT: vgatherdpd %xmm1, (%eax,%xmm0,2), %xmm2 +; X86-NEXT: vmovapd %xmm2, %xmm0 +; X86-NEXT: retl ; ; X64-LABEL: test_x86_avx2_gather_d_pd: ; X64: # %bb.0: @@ -52,13 +52,13 @@ declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, ptr, <8 x i32>, <8 x float>, i8) nounwind readonly define <8 x float> @test_x86_avx2_gather_d_ps_256(ptr %a1, <8 x i32> %idx, <8 x float> %mask) { -; X32-LABEL: test_x86_avx2_gather_d_ps_256: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; X32-NEXT: vgatherdps %ymm1, (%eax,%ymm0,4), %ymm2 -; X32-NEXT: vmovaps %ymm2, %ymm0 -; X32-NEXT: retl +; X86-LABEL: test_x86_avx2_gather_d_ps_256: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; X86-NEXT: vgatherdps %ymm1, (%eax,%ymm0,4), %ymm2 +; X86-NEXT: vmovaps %ymm2, %ymm0 +; X86-NEXT: retl ; ; X64-LABEL: test_x86_avx2_gather_d_ps_256: ; X64: # %bb.0: @@ -75,13 +75,13 @@ declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, ptr, <4 x i32>, <4 x double>, i8) nounwind readonly define <4 x double> @test_x86_avx2_gather_d_pd_256(ptr %a1, <4 x i32> %idx, <4 x double> %mask) { -; X32-LABEL: test_x86_avx2_gather_d_pd_256: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vxorpd %xmm2, %xmm2, %xmm2 -; X32-NEXT: vgatherdpd %ymm1, (%eax,%xmm0,8), %ymm2 -; X32-NEXT: vmovapd %ymm2, %ymm0 -; X32-NEXT: retl +; X86-LABEL: test_x86_avx2_gather_d_pd_256: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vxorpd %xmm2, %xmm2, %xmm2 +; X86-NEXT: vgatherdpd %ymm1, (%eax,%xmm0,8), %ymm2 +; X86-NEXT: vmovapd %ymm2, %ymm0 +; X86-NEXT: retl ; ; X64-LABEL: test_x86_avx2_gather_d_pd_256: ; X64: # %bb.0: @@ -95,14 +95,14 @@ define <4 x double> @test_x86_avx2_gather_d_pd_256(ptr %a1, <4 x i32> %idx, <4 x } define <2 x i64> @test_mm_i32gather_epi32(ptr%a0, <2 x i64> %a1) { -; X32-LABEL: test_mm_i32gather_epi32: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; X32-NEXT: vpgatherdd %xmm2, (%eax,%xmm0,2), %xmm1 -; X32-NEXT: vmovdqa %xmm1, %xmm0 -; X32-NEXT: retl +; X86-LABEL: test_mm_i32gather_epi32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm0,2), %xmm1 +; X86-NEXT: vmovdqa %xmm1, %xmm0 +; X86-NEXT: retl ; ; X64-LABEL: test_mm_i32gather_epi32: ; X64: # %bb.0: @@ -121,14 +121,14 @@ define <2 x i64> @test_mm_i32gather_epi32(ptr%a0, <2 x i64> %a1) { declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32>, ptr, <4 x i32>, <4 x i32>, i8) nounwind readonly define <2 x double> @test_mm_i32gather_pd(ptr%a0, <2 x i64> %a1) { -; X32-LABEL: test_mm_i32gather_pd: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1 -; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; X32-NEXT: vgatherdpd %xmm2, (%eax,%xmm0,2), %xmm1 -; X32-NEXT: vmovapd %xmm1, %xmm0 -; X32-NEXT: retl +; X86-LABEL: test_mm_i32gather_pd: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm0,2), %xmm1 +; X86-NEXT: vmovapd %xmm1, %xmm0 +; X86-NEXT: retl ; ; X64-LABEL: test_mm_i32gather_pd: ; X64: # %bb.0: @@ -149,14 +149,14 @@ define <2 x double> @test_mm_i32gather_pd(ptr%a0, <2 x i64> %a1) { @x = dso_local global [1024 x float] zeroinitializer, align 16 define <4 x float> @gather_global(<4 x i64>, ptr nocapture readnone) { -; X32-LABEL: gather_global: -; X32: # %bb.0: -; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1 -; X32-NEXT: vgatherqps %xmm2, x(,%ymm0,4), %xmm1 -; X32-NEXT: vmovaps %xmm1, %xmm0 -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: gather_global: +; X86: # %bb.0: +; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X86-NEXT: vgatherqps %xmm2, x(,%ymm0,4), %xmm1 +; X86-NEXT: vmovaps %xmm1, %xmm0 +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: gather_global: ; X64: # %bb.0: -- GitLab From 0e4a38018a7228d93d72a31d9fae6855f866dded Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:37:34 +0000 Subject: [PATCH 057/652] [X86] avx2-nontemporal.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. --- llvm/test/CodeGen/X86/avx2-nontemporal.ll | 68 +++++++++++------------ 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/llvm/test/CodeGen/X86/avx2-nontemporal.ll b/llvm/test/CodeGen/X86/avx2-nontemporal.ll index 95568e7b3d0a..cd16b3018448 100644 --- a/llvm/test/CodeGen/X86/avx2-nontemporal.ll +++ b/llvm/test/CodeGen/X86/avx2-nontemporal.ll @@ -1,41 +1,41 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefix=X64 define i32 @f(<8 x float> %A, ptr %B, <4 x double> %C, <4 x i64> %E, <8 x i32> %F, <16 x i16> %G, <32 x i8> %H, ptr %loadptr) nounwind { -; X32-LABEL: f: -; X32: # %bb.0: -; X32-NEXT: pushl %ebp -; X32-NEXT: movl %esp, %ebp -; X32-NEXT: andl $-32, %esp -; X32-NEXT: subl $32, %esp -; X32-NEXT: vmovdqa 104(%ebp), %ymm3 -; X32-NEXT: vmovdqa 72(%ebp), %ymm4 -; X32-NEXT: vmovdqa 40(%ebp), %ymm5 -; X32-NEXT: movl 8(%ebp), %ecx -; X32-NEXT: movl 136(%ebp), %edx -; X32-NEXT: movl (%edx), %eax -; X32-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 -; X32-NEXT: vmovntps %ymm0, (%ecx) -; X32-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm0 -; X32-NEXT: addl (%edx), %eax -; X32-NEXT: vmovntdq %ymm0, (%ecx) -; X32-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0 -; X32-NEXT: addl (%edx), %eax -; X32-NEXT: vmovntpd %ymm0, (%ecx) -; X32-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm5, %ymm0 -; X32-NEXT: addl (%edx), %eax -; X32-NEXT: vmovntdq %ymm0, (%ecx) -; X32-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm4, %ymm0 -; X32-NEXT: addl (%edx), %eax -; X32-NEXT: vmovntdq %ymm0, (%ecx) -; X32-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm0 -; X32-NEXT: addl (%edx), %eax -; X32-NEXT: vmovntdq %ymm0, (%ecx) -; X32-NEXT: movl %ebp, %esp -; X32-NEXT: popl %ebp -; X32-NEXT: vzeroupper -; X32-NEXT: retl +; X86-LABEL: f: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-32, %esp +; X86-NEXT: subl $32, %esp +; X86-NEXT: vmovdqa 104(%ebp), %ymm3 +; X86-NEXT: vmovdqa 72(%ebp), %ymm4 +; X86-NEXT: vmovdqa 40(%ebp), %ymm5 +; X86-NEXT: movl 8(%ebp), %ecx +; X86-NEXT: movl 136(%ebp), %edx +; X86-NEXT: movl (%edx), %eax +; X86-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 +; X86-NEXT: vmovntps %ymm0, (%ecx) +; X86-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm0 +; X86-NEXT: addl (%edx), %eax +; X86-NEXT: vmovntdq %ymm0, (%ecx) +; X86-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0 +; X86-NEXT: addl (%edx), %eax +; X86-NEXT: vmovntpd %ymm0, (%ecx) +; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %ymm5, %ymm0 +; X86-NEXT: addl (%edx), %eax +; X86-NEXT: vmovntdq %ymm0, (%ecx) +; X86-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}, %ymm4, %ymm0 +; X86-NEXT: addl (%edx), %eax +; X86-NEXT: vmovntdq %ymm0, (%ecx) +; X86-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm0 +; X86-NEXT: addl (%edx), %eax +; X86-NEXT: vmovntdq %ymm0, (%ecx) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: vzeroupper +; X86-NEXT: retl ; ; X64-LABEL: f: ; X64: # %bb.0: -- GitLab From 2edce427a8b17d1d2192c1ee4a2227b6eb2971a0 Mon Sep 17 00:00:00 2001 From: Xing Xue <57193974+xingxue-ibm@users.noreply.github.com> Date: Mon, 8 Jan 2024 08:33:00 -0500 Subject: [PATCH 058/652] [openmp][AIX]Initial changes for porting to AIX (#76841) This PR contains initial changes for building and testing libomp on AIX. More changes will follow. - `KMP_OS_AIX` is defined for the AIX platform - `KMP_ARCH_PPC` is defined for 32-bit PPC - `KMP_ARCH_PPC_XCOFF` and `KMP_ARCH_PPC64_XCOFF` are for 32- and 64-bit XCOFF object formats respectively - Assembly file `z_AIX_asm.S` is used for AIX specific assembly code and will be added in a separate PR - The target library is disabled because AIX does not have the device support - OMPT is temporarily disabled --- openmp/CMakeLists.txt | 3 +- openmp/cmake/OpenMPTesting.cmake | 3 ++ openmp/runtime/CMakeLists.txt | 21 +++++++++--- .../runtime/cmake/LibompGetArchitecture.cmake | 2 ++ openmp/runtime/cmake/config-ix.cmake | 3 +- openmp/runtime/src/CMakeLists.txt | 6 +++- openmp/runtime/src/kmp.h | 7 ++++ openmp/runtime/src/kmp_config.h.cmake | 2 +- openmp/runtime/src/kmp_ftn_entry.h | 2 +- openmp/runtime/src/kmp_global.cpp | 2 +- openmp/runtime/src/kmp_gsupport.cpp | 3 +- openmp/runtime/src/kmp_os.h | 9 +++--- openmp/runtime/src/kmp_platform.h | 32 +++++++++++++++---- openmp/runtime/src/kmp_runtime.cpp | 8 ++--- openmp/runtime/src/kmp_settings.cpp | 4 +-- openmp/runtime/src/kmp_wrapper_getpid.h | 5 +++ openmp/runtime/src/z_Linux_util.cpp | 21 +++++++++--- openmp/runtime/test/lit.cfg | 12 +++++++ 18 files changed, 112 insertions(+), 33 deletions(-) diff --git a/openmp/CMakeLists.txt b/openmp/CMakeLists.txt index 307c8dbbc0c3..c1c79f8e0ca9 100644 --- a/openmp/CMakeLists.txt +++ b/openmp/CMakeLists.txt @@ -94,7 +94,8 @@ set(ENABLE_LIBOMPTARGET ON) # Since the device plugins are only supported on Linux anyway, # there is no point in trying to compile libomptarget on other OSes. # 32-bit systems are not supported either. -if (APPLE OR WIN32 OR WASM OR NOT "cxx_std_17" IN_LIST CMAKE_CXX_COMPILE_FEATURES OR NOT CMAKE_SIZEOF_VOID_P EQUAL 8) +if (APPLE OR WIN32 OR WASM OR NOT "cxx_std_17" IN_LIST CMAKE_CXX_COMPILE_FEATURES + OR NOT CMAKE_SIZEOF_VOID_P EQUAL 8 OR ${CMAKE_SYSTEM_NAME} MATCHES "AIX") set(ENABLE_LIBOMPTARGET OFF) endif() diff --git a/openmp/cmake/OpenMPTesting.cmake b/openmp/cmake/OpenMPTesting.cmake index a771efdf9e69..df41956dadd4 100644 --- a/openmp/cmake/OpenMPTesting.cmake +++ b/openmp/cmake/OpenMPTesting.cmake @@ -55,6 +55,9 @@ if (${OPENMP_STANDALONE_BUILD}) if (MSVC OR XCODE) set(DEFAULT_LIT_ARGS "${DEFAULT_LIT_ARGS} --no-progress-bar") endif() + if (${CMAKE_SYSTEM_NAME} MATCHES "AIX") + set(DEFAULT_LIT_ARGS "${DEFAULT_LIT_ARGS} --time-tests --timeout=1800") + endif() set(OPENMP_LIT_ARGS "${DEFAULT_LIT_ARGS}" CACHE STRING "Options for lit.") separate_arguments(OPENMP_LIT_ARGS) else() diff --git a/openmp/runtime/CMakeLists.txt b/openmp/runtime/CMakeLists.txt index 80064170db19..041b60efac5c 100644 --- a/openmp/runtime/CMakeLists.txt +++ b/openmp/runtime/CMakeLists.txt @@ -30,7 +30,7 @@ if(${OPENMP_STANDALONE_BUILD}) # If adding a new architecture, take a look at cmake/LibompGetArchitecture.cmake libomp_get_architecture(LIBOMP_DETECTED_ARCH) set(LIBOMP_ARCH ${LIBOMP_DETECTED_ARCH} CACHE STRING - "The architecture to build for (x86_64/i386/arm/ppc64/ppc64le/aarch64/mic/mips/mips64/riscv64/loongarch64/ve/s390x/wasm32).") + "The architecture to build for (x86_64/i386/arm/ppc/ppc64/ppc64le/aarch64/mic/mips/mips64/riscv64/loongarch64/ve/s390x/wasm32).") # Should assertions be enabled? They are on by default. set(LIBOMP_ENABLE_ASSERTIONS TRUE CACHE BOOL "enable assertions?") @@ -51,8 +51,10 @@ else() # Part of LLVM build set(LIBOMP_ARCH x86_64) elseif(LIBOMP_NATIVE_ARCH MATCHES "powerpc64le") set(LIBOMP_ARCH ppc64le) - elseif(LIBOMP_NATIVE_ARCH MATCHES "powerpc") + elseif(LIBOMP_NATIVE_ARCH MATCHES "powerpc64") set(LIBOMP_ARCH ppc64) + elseif(LIBOMP_NATIVE_ARCH MATCHES "powerpc") + set(LIBOMP_ARCH ppc) elseif(LIBOMP_NATIVE_ARCH MATCHES "aarch64") set(LIBOMP_ARCH aarch64) elseif(LIBOMP_NATIVE_ARCH MATCHES "arm64") @@ -89,7 +91,7 @@ if(LIBOMP_ARCH STREQUAL "aarch64") endif() endif() -libomp_check_variable(LIBOMP_ARCH 32e x86_64 32 i386 arm ppc64 ppc64le aarch64 aarch64_a64fx mic mips mips64 riscv64 loongarch64 ve s390x wasm32) +libomp_check_variable(LIBOMP_ARCH 32e x86_64 32 i386 arm ppc ppc64 ppc64le aarch64 aarch64_a64fx mic mips mips64 riscv64 loongarch64 ve s390x wasm32) set(LIBOMP_LIB_TYPE normal CACHE STRING "Performance,Profiling,Stubs library (normal/profile/stubs)") @@ -128,8 +130,14 @@ set(LIBOMP_ASMFLAGS "" CACHE STRING "Appended user specified assembler flags.") set(LIBOMP_LDFLAGS "" CACHE STRING "Appended user specified linker flags.") -set(LIBOMP_LIBFLAGS "" CACHE STRING - "Appended user specified linked libs flags. (e.g., -lm)") +if("${LIBOMP_ARCH}" STREQUAL "ppc" AND ${CMAKE_SYSTEM_NAME} MATCHES "AIX") + # PPC (32-bit) on AIX needs libatomic for __atomic_load_8, etc. + set(LIBOMP_LIBFLAGS "-latomic" CACHE STRING + "Appended user specified linked libs flags. (e.g., -lm)") +else() + set(LIBOMP_LIBFLAGS "" CACHE STRING + "Appended user specified linked libs flags. (e.g., -lm)") +endif() set(LIBOMP_FFLAGS "" CACHE STRING "Appended user specified Fortran compiler flags. These are only used if LIBOMP_FORTRAN_MODULES==TRUE.") @@ -171,12 +179,15 @@ set(LOONGARCH64 FALSE) set(VE FALSE) set(S390X FALSE) set(WASM FALSE) +set(PPC FALSE) if("${LIBOMP_ARCH}" STREQUAL "i386" OR "${LIBOMP_ARCH}" STREQUAL "32") # IA-32 architecture set(IA32 TRUE) elseif("${LIBOMP_ARCH}" STREQUAL "x86_64" OR "${LIBOMP_ARCH}" STREQUAL "32e") # Intel(R) 64 architecture set(INTEL64 TRUE) elseif("${LIBOMP_ARCH}" STREQUAL "arm") # ARM architecture set(ARM TRUE) +elseif("${LIBOMP_ARCH}" STREQUAL "ppc") # PPC32 architecture + set(PPC TRUE) elseif("${LIBOMP_ARCH}" STREQUAL "ppc64") # PPC64BE architecture set(PPC64BE TRUE) set(PPC64 TRUE) diff --git a/openmp/runtime/cmake/LibompGetArchitecture.cmake b/openmp/runtime/cmake/LibompGetArchitecture.cmake index cd85267020bd..d7f81870f9ef 100644 --- a/openmp/runtime/cmake/LibompGetArchitecture.cmake +++ b/openmp/runtime/cmake/LibompGetArchitecture.cmake @@ -41,6 +41,8 @@ function(libomp_get_architecture return_arch) #error ARCHITECTURE=ppc64le #elif defined(__powerpc64__) #error ARCHITECTURE=ppc64 + #elif defined(__powerpc__) && !defined(__powerpc64__) + #error ARCHITECTURE=ppc #elif defined(__mips__) && defined(__mips64) #error ARCHITECTURE=mips64 #elif defined(__mips__) && !defined(__mips64) diff --git a/openmp/runtime/cmake/config-ix.cmake b/openmp/runtime/cmake/config-ix.cmake index 90b9af4cd382..76f471a44380 100644 --- a/openmp/runtime/cmake/config-ix.cmake +++ b/openmp/runtime/cmake/config-ix.cmake @@ -333,7 +333,8 @@ else() (LIBOMP_ARCH STREQUAL loongarch64) OR (LIBOMP_ARCH STREQUAL s390x)) AND # OS supported? - ((WIN32 AND LIBOMP_HAVE_PSAPI) OR APPLE OR (NOT WIN32 AND LIBOMP_HAVE_WEAK_ATTRIBUTE))) + ((WIN32 AND LIBOMP_HAVE_PSAPI) OR APPLE OR + (NOT (WIN32 OR ${CMAKE_SYSTEM_NAME} MATCHES "AIX") AND LIBOMP_HAVE_WEAK_ATTRIBUTE))) set(LIBOMP_HAVE_OMPT_SUPPORT TRUE) else() set(LIBOMP_HAVE_OMPT_SUPPORT FALSE) diff --git a/openmp/runtime/src/CMakeLists.txt b/openmp/runtime/src/CMakeLists.txt index 8b2445ac58bf..619d4f7ba458 100644 --- a/openmp/runtime/src/CMakeLists.txt +++ b/openmp/runtime/src/CMakeLists.txt @@ -108,7 +108,11 @@ else() # Unix specific files libomp_append(LIBOMP_CXXFILES z_Linux_util.cpp) libomp_append(LIBOMP_CXXFILES kmp_gsupport.cpp) - libomp_append(LIBOMP_GNUASMFILES z_Linux_asm.S) # Unix assembly file + if(${CMAKE_SYSTEM_NAME} MATCHES "AIX") + libomp_append(LIBOMP_GNUASMFILES z_AIX_asm.S) # AIX assembly file + else() + libomp_append(LIBOMP_GNUASMFILES z_Linux_asm.S) # Unix assembly file + endif() endif() libomp_append(LIBOMP_CXXFILES thirdparty/ittnotify/ittnotify_static.cpp LIBOMP_USE_ITT_NOTIFY) libomp_append(LIBOMP_CXXFILES kmp_debugger.cpp LIBOMP_USE_DEBUGGER) diff --git a/openmp/runtime/src/kmp.h b/openmp/runtime/src/kmp.h index 3dbf8c71c48d..c287a31e0b1b 100644 --- a/openmp/runtime/src/kmp.h +++ b/openmp/runtime/src/kmp.h @@ -1192,6 +1192,9 @@ extern void __kmp_init_target_task(); // Minimum stack size for pthread for VE is 4MB. // https://www.hpc.nec/documents/veos/en/glibc/Difference_Points_glibc.htm #define KMP_DEFAULT_STKSIZE ((size_t)(4 * 1024 * 1024)) +#elif KMP_OS_AIX +// The default stack size for worker threads on AIX is 4MB. +#define KMP_DEFAULT_STKSIZE ((size_t)(4 * 1024 * 1024)) #else #define KMP_DEFAULT_STKSIZE ((size_t)(1024 * 1024)) #endif @@ -1354,6 +1357,10 @@ extern kmp_uint64 __kmp_now_nsec(); /* TODO: tune for KMP_OS_WASI */ #define KMP_INIT_WAIT 1024U /* initial number of spin-tests */ #define KMP_NEXT_WAIT 512U /* susequent number of spin-tests */ +#elif KMP_OS_AIX +/* TODO: tune for KMP_OS_AIX */ +#define KMP_INIT_WAIT 1024U /* initial number of spin-tests */ +#define KMP_NEXT_WAIT 512U /* susequent number of spin-tests */ #endif #if KMP_ARCH_X86 || KMP_ARCH_X86_64 diff --git a/openmp/runtime/src/kmp_config.h.cmake b/openmp/runtime/src/kmp_config.h.cmake index 5f04301c91c6..b0cd0ed296e7 100644 --- a/openmp/runtime/src/kmp_config.h.cmake +++ b/openmp/runtime/src/kmp_config.h.cmake @@ -100,7 +100,7 @@ #define ENABLE_LIBOMPTARGET OPENMP_ENABLE_LIBOMPTARGET // Configured cache line based on architecture -#if KMP_ARCH_PPC64 +#if KMP_ARCH_PPC64 || KMP_ARCH_PPC # define CACHE_LINE 128 #elif KMP_ARCH_AARCH64_A64FX # define CACHE_LINE 256 diff --git a/openmp/runtime/src/kmp_ftn_entry.h b/openmp/runtime/src/kmp_ftn_entry.h index d54c5bfd10fe..713561734c48 100644 --- a/openmp/runtime/src/kmp_ftn_entry.h +++ b/openmp/runtime/src/kmp_ftn_entry.h @@ -582,7 +582,7 @@ int FTN_STDCALL KMP_EXPAND_NAME(FTN_GET_THREAD_NUM)(void) { int gtid; #if KMP_OS_DARWIN || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || \ - KMP_OS_OPENBSD || KMP_OS_HURD || KMP_OS_SOLARIS + KMP_OS_OPENBSD || KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_AIX gtid = __kmp_entry_gtid(); #elif KMP_OS_WINDOWS if (!__kmp_init_parallel || diff --git a/openmp/runtime/src/kmp_global.cpp b/openmp/runtime/src/kmp_global.cpp index b132f38fd3b0..5017cd3de4be 100644 --- a/openmp/runtime/src/kmp_global.cpp +++ b/openmp/runtime/src/kmp_global.cpp @@ -172,7 +172,7 @@ int __kmp_ncores = 0; int __kmp_chunk = 0; int __kmp_force_monotonic = 0; int __kmp_abort_delay = 0; -#if KMP_OS_LINUX && defined(KMP_TDATA_GTID) +#if (KMP_OS_LINUX || KMP_OS_AIX) && defined(KMP_TDATA_GTID) int __kmp_gtid_mode = 3; /* use __declspec(thread) TLS to store gtid */ int __kmp_adjust_gtid_mode = FALSE; #elif KMP_OS_WINDOWS diff --git a/openmp/runtime/src/kmp_gsupport.cpp b/openmp/runtime/src/kmp_gsupport.cpp index 78af39533549..88189659a234 100644 --- a/openmp/runtime/src/kmp_gsupport.cpp +++ b/openmp/runtime/src/kmp_gsupport.cpp @@ -357,7 +357,8 @@ void KMP_EXPAND_NAME(KMP_API_NAME_GOMP_ORDERED_END)(void) { // They come in two flavors: 64-bit unsigned, and either 32-bit signed // (IA-32 architecture) or 64-bit signed (Intel(R) 64). -#if KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_MIPS || KMP_ARCH_WASM +#if KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_MIPS || KMP_ARCH_WASM || \ + KMP_ARCH_PPC #define KMP_DISPATCH_INIT __kmp_aux_dispatch_init_4 #define KMP_DISPATCH_FINI_CHUNK __kmp_aux_dispatch_fini_chunk_4 #define KMP_DISPATCH_NEXT __kmpc_dispatch_next_4 diff --git a/openmp/runtime/src/kmp_os.h b/openmp/runtime/src/kmp_os.h index 4ffe9f2d8c95..6862fd89b630 100644 --- a/openmp/runtime/src/kmp_os.h +++ b/openmp/runtime/src/kmp_os.h @@ -176,7 +176,8 @@ typedef unsigned long long kmp_uint64; #define KMP_UINT64_SPEC "llu" #endif /* KMP_OS_UNIX */ -#if KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_MIPS || KMP_ARCH_WASM +#if KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_MIPS || KMP_ARCH_WASM || \ + KMP_ARCH_PPC #define KMP_SIZE_T_SPEC KMP_UINT32_SPEC #elif KMP_ARCH_X86_64 || KMP_ARCH_PPC64 || KMP_ARCH_AARCH64 || \ KMP_ARCH_MIPS64 || KMP_ARCH_RISCV64 || KMP_ARCH_LOONGARCH64 || \ @@ -186,7 +187,7 @@ typedef unsigned long long kmp_uint64; #error "Can't determine size_t printf format specifier." #endif -#if KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_WASM +#if KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_WASM || KMP_ARCH_PPC #define KMP_SIZE_T_MAX (0xFFFFFFFF) #else #define KMP_SIZE_T_MAX (0xFFFFFFFFFFFFFFFF) @@ -1046,7 +1047,7 @@ extern kmp_real64 __kmp_xchg_real64(volatile kmp_real64 *p, kmp_real64 v); #if KMP_ARCH_PPC64 || KMP_ARCH_ARM || KMP_ARCH_AARCH64 || KMP_ARCH_MIPS || \ KMP_ARCH_MIPS64 || KMP_ARCH_RISCV64 || KMP_ARCH_LOONGARCH64 || \ - KMP_ARCH_VE || KMP_ARCH_S390X + KMP_ARCH_VE || KMP_ARCH_S390X || KMP_ARCH_PPC #if KMP_OS_WINDOWS #undef KMP_MB #define KMP_MB() std::atomic_thread_fence(std::memory_order_seq_cst) @@ -1146,7 +1147,7 @@ extern kmp_real64 __kmp_xchg_real64(volatile kmp_real64 *p, kmp_real64 v); KMP_COMPARE_AND_STORE_REL64((volatile kmp_int64 *)(volatile void *)&(a), \ (kmp_int64)(b), (kmp_int64)(c)) -#if KMP_ARCH_X86 || KMP_ARCH_MIPS || KMP_ARCH_WASM +#if KMP_ARCH_X86 || KMP_ARCH_MIPS || KMP_ARCH_WASM || KMP_ARCH_PPC // What about ARM? #define TCR_PTR(a) ((void *)TCR_4(a)) #define TCW_PTR(a, b) TCW_4((a), (b)) diff --git a/openmp/runtime/src/kmp_platform.h b/openmp/runtime/src/kmp_platform.h index 45f411b9c219..c06f46db2d49 100644 --- a/openmp/runtime/src/kmp_platform.h +++ b/openmp/runtime/src/kmp_platform.h @@ -82,15 +82,20 @@ #define KMP_OS_WASI 1 #endif +#if (defined _AIX) +#undef KMP_OS_AIX +#define KMP_OS_AIX 1 +#endif + #if (1 != KMP_OS_LINUX + KMP_OS_DRAGONFLY + KMP_OS_FREEBSD + KMP_OS_NETBSD + \ KMP_OS_OPENBSD + KMP_OS_DARWIN + KMP_OS_WINDOWS + KMP_OS_HURD + \ - KMP_OS_SOLARIS + KMP_OS_WASI) + KMP_OS_SOLARIS + KMP_OS_WASI + KMP_OS_AIX) #error Unknown OS #endif #if KMP_OS_LINUX || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || \ KMP_OS_OPENBSD || KMP_OS_DARWIN || KMP_OS_HURD || KMP_OS_SOLARIS || \ - KMP_OS_WASI + KMP_OS_WASI || KMP_OS_AIX #undef KMP_OS_UNIX #define KMP_OS_UNIX 1 #endif @@ -102,7 +107,8 @@ #define KMP_ARCH_AARCH64 0 #define KMP_ARCH_PPC64_ELFv1 0 #define KMP_ARCH_PPC64_ELFv2 0 -#define KMP_ARCH_PPC64 (KMP_ARCH_PPC64_ELFv2 || KMP_ARCH_PPC64_ELFv1) +#define KMP_ARCH_PPC64_XCOFF 0 +#define KMP_ARCH_PPC_XCOFF 0 #define KMP_ARCH_MIPS 0 #define KMP_ARCH_MIPS64 0 #define KMP_ARCH_RISCV64 0 @@ -134,13 +140,23 @@ #undef KMP_ARCH_X86 #define KMP_ARCH_X86 1 #elif defined __powerpc64__ -#if defined(_CALL_ELF) && _CALL_ELF == 2 +#if defined(_CALL_ELF) +#if _CALL_ELF == 2 #undef KMP_ARCH_PPC64_ELFv2 #define KMP_ARCH_PPC64_ELFv2 1 #else #undef KMP_ARCH_PPC64_ELFv1 #define KMP_ARCH_PPC64_ELFv1 1 #endif +#elif defined KMP_OS_AIX +#undef KMP_ARCH_PPC64_XCOFF +#define KMP_ARCH_PPC64_XCOFF 1 +#endif +#elif defined(__powerpc__) && defined(KMP_OS_AIX) +#undef KMP_ARCH_PPC_XCOFF +#define KMP_ARCH_PPC_XCOFF 1 +#undef KMP_ARCH_PPC +#define KMP_ARCH_PPC 1 #elif defined __aarch64__ #undef KMP_ARCH_AARCH64 #define KMP_ARCH_AARCH64 1 @@ -207,6 +223,9 @@ #define KMP_ARCH_WASM 1 #endif +#define KMP_ARCH_PPC64 \ + (KMP_ARCH_PPC64_ELFv2 || KMP_ARCH_PPC64_ELFv1 || KMP_ARCH_PPC64_XCOFF) + #if defined(__MIC__) || defined(__MIC2__) #define KMP_MIC 1 #if __MIC2__ || __KNC__ @@ -224,7 +243,8 @@ /* Specify 32 bit architectures here */ #define KMP_32_BIT_ARCH \ - (KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_MIPS || KMP_ARCH_WASM) + (KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_MIPS || KMP_ARCH_WASM || \ + KMP_ARCH_PPC) // Platforms which support Intel(R) Many Integrated Core Architecture #define KMP_MIC_SUPPORTED \ @@ -234,7 +254,7 @@ #if (1 != KMP_ARCH_X86 + KMP_ARCH_X86_64 + KMP_ARCH_ARM + KMP_ARCH_PPC64 + \ KMP_ARCH_AARCH64 + KMP_ARCH_MIPS + KMP_ARCH_MIPS64 + \ KMP_ARCH_RISCV64 + KMP_ARCH_LOONGARCH64 + KMP_ARCH_VE + \ - KMP_ARCH_S390X + KMP_ARCH_WASM) + KMP_ARCH_S390X + KMP_ARCH_WASM + KMP_ARCH_PPC) #error Unknown or unsupported architecture #endif diff --git a/openmp/runtime/src/kmp_runtime.cpp b/openmp/runtime/src/kmp_runtime.cpp index 4e1074a893a2..fc5e8405a415 100644 --- a/openmp/runtime/src/kmp_runtime.cpp +++ b/openmp/runtime/src/kmp_runtime.cpp @@ -8901,7 +8901,7 @@ __kmp_determine_reduction_method( #if KMP_OS_LINUX || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || \ KMP_OS_OPENBSD || KMP_OS_WINDOWS || KMP_OS_DARWIN || KMP_OS_HURD || \ - KMP_OS_SOLARIS || KMP_OS_WASI + KMP_OS_SOLARIS || KMP_OS_WASI || KMP_OS_AIX int teamsize_cutoff = 4; @@ -8926,14 +8926,14 @@ __kmp_determine_reduction_method( #error "Unknown or unsupported OS" #endif // KMP_OS_LINUX || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || // KMP_OS_OPENBSD || KMP_OS_WINDOWS || KMP_OS_DARWIN || KMP_OS_HURD || - // KMP_OS_SOLARIS || KMP_OS_WASI + // KMP_OS_SOLARIS || KMP_OS_WASI || KMP_OS_AIX #elif KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_AARCH || KMP_ARCH_MIPS || \ - KMP_ARCH_WASM + KMP_ARCH_WASM || KMP_ARCH_PPC #if KMP_OS_LINUX || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || \ KMP_OS_OPENBSD || KMP_OS_WINDOWS || KMP_OS_HURD || KMP_OS_SOLARIS || \ - KMP_OS_WASI + KMP_OS_WASI || KMP_OS_AIX // basic tuning diff --git a/openmp/runtime/src/kmp_settings.cpp b/openmp/runtime/src/kmp_settings.cpp index e731bf45e8ee..30a4c05fe76b 100644 --- a/openmp/runtime/src/kmp_settings.cpp +++ b/openmp/runtime/src/kmp_settings.cpp @@ -6171,9 +6171,9 @@ void __kmp_env_initialize(char const *string) { // specifier, even as substrings. // // I can't find a case-insensitive version of strstr on Windows* OS. - // Use the case-sensitive version for now. + // Use the case-sensitive version for now. AIX does the same. -#if KMP_OS_WINDOWS +#if KMP_OS_WINDOWS || KMP_OS_AIX #define FIND strstr #else #define FIND strcasestr diff --git a/openmp/runtime/src/kmp_wrapper_getpid.h b/openmp/runtime/src/kmp_wrapper_getpid.h index f9d7f4804fbc..d31c6e80f75d 100644 --- a/openmp/runtime/src/kmp_wrapper_getpid.h +++ b/openmp/runtime/src/kmp_wrapper_getpid.h @@ -17,7 +17,9 @@ // On Unix-like systems (Linux* OS and OS X*) getpid() is declared in standard // headers. +#if !defined(KMP_OS_AIX) #include +#endif #include #include #if KMP_OS_DARWIN @@ -31,6 +33,9 @@ #define __kmp_gettid() _lwp_self() #elif KMP_OS_OPENBSD #define __kmp_gettid() getthrid() +#elif KMP_OS_AIX +#include +#define __kmp_gettid() pthread_self() #elif defined(SYS_gettid) // Hopefully other Unix systems define SYS_gettid syscall for getting os thread // id diff --git a/openmp/runtime/src/z_Linux_util.cpp b/openmp/runtime/src/z_Linux_util.cpp index c2df8895e887..f01fa647c4d4 100644 --- a/openmp/runtime/src/z_Linux_util.cpp +++ b/openmp/runtime/src/z_Linux_util.cpp @@ -29,7 +29,9 @@ #include #endif // KMP_OS_LINUX #include +#if !KMP_OS_AIX #include +#endif #include #include #include @@ -1832,7 +1834,7 @@ static int __kmp_get_xproc(void) { __kmp_type_convert(sysconf(_SC_NPROCESSORS_CONF), &(r)); #elif KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || KMP_OS_OPENBSD || \ - KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_WASI + KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_WASI || KMP_OS_AIX __kmp_type_convert(sysconf(_SC_NPROCESSORS_ONLN), &(r)); @@ -2210,9 +2212,9 @@ int __kmp_is_address_mapped(void *addr) { } #elif KMP_OS_WASI found = (int)addr < (__builtin_wasm_memory_size(0) * PAGESIZE); -#elif KMP_OS_DRAGONFLY || KMP_OS_SOLARIS +#elif KMP_OS_DRAGONFLY || KMP_OS_SOLARIS || KMP_OS_AIX - // FIXME(DragonFly, Solaris): Implement this + // FIXME(DragonFly, Solaris, AIX): Implement this found = 1; #else @@ -2317,7 +2319,7 @@ int __kmp_get_load_balance(int max) { // Open "/proc/" directory. proc_dir = opendir("/proc"); if (proc_dir == NULL) { - // Cannot open "/prroc/". Probably the kernel does not support it. Return an + // Cannot open "/proc/". Probably the kernel does not support it. Return an // error now and in subsequent calls. running_threads = -1; permanent_error = 1; @@ -2330,9 +2332,14 @@ int __kmp_get_load_balance(int max) { proc_entry = readdir(proc_dir); while (proc_entry != NULL) { +#if KMP_OS_AIX + // Proc entry name starts with a digit. Assume it is a process' directory. + if (isdigit(proc_entry->d_name[0])) { +#else // Proc entry is a directory and name starts with a digit. Assume it is a // process' directory. if (proc_entry->d_type == DT_DIR && isdigit(proc_entry->d_name[0])) { +#endif #ifdef KMP_DEBUG ++total_processes; @@ -2376,7 +2383,11 @@ int __kmp_get_load_balance(int max) { task_entry = readdir(task_dir); while (task_entry != NULL) { // It is a directory and name starts with a digit. +#if KMP_OS_AIX + if (isdigit(task_entry->d_name[0])) { +#else if (proc_entry->d_type == DT_DIR && isdigit(task_entry->d_name[0])) { +#endif // Construct complete stat file path. Easiest way would be: // __kmp_str_buf_print( & stat_path, "%s/%s/stat", task_path.str, @@ -2486,7 +2497,7 @@ finish: // Clean up and exit. #if !(KMP_ARCH_X86 || KMP_ARCH_X86_64 || KMP_MIC || \ ((KMP_OS_LINUX || KMP_OS_DARWIN) && KMP_ARCH_AARCH64) || \ KMP_ARCH_PPC64 || KMP_ARCH_RISCV64 || KMP_ARCH_LOONGARCH64 || \ - KMP_ARCH_ARM || KMP_ARCH_VE || KMP_ARCH_S390X) + KMP_ARCH_ARM || KMP_ARCH_VE || KMP_ARCH_S390X || KMP_ARCH_PPC_XCOFF) // we really only need the case with 1 argument, because CLANG always build // a struct of pointers to shared variables referenced in the outlined function diff --git a/openmp/runtime/test/lit.cfg b/openmp/runtime/test/lit.cfg index 27ff057c85f6..4a457f4cc41f 100644 --- a/openmp/runtime/test/lit.cfg +++ b/openmp/runtime/test/lit.cfg @@ -108,6 +108,18 @@ if config.has_ompt: if config.has_ompx_taskgraph: config.available_features.add("ompx_taskgraph") +if config.operating_system == 'AIX': + config.available_features.add("aix") + object_mode = os.environ.get('OBJECT_MODE', '32') + if object_mode == '64': + config.test_flags += " -m64" + elif object_mode == '32': + # Set user data area to 2GB since the default size 256MB in 32-bit mode + # is not sufficient to run LIT tests on systems that have a lot of + # CPUs when creating one worker thread for each CPU and each worker + # thread uses 4MB stack size. + config.test_flags += " -Wl,-bmaxdata:0x80000000" + if 'Linux' in config.operating_system: config.available_features.add("linux") -- GitLab From 763109e346b90193027b24743e266495d992b1c6 Mon Sep 17 00:00:00 2001 From: Guray Ozen Date: Mon, 8 Jan 2024 14:49:19 +0100 Subject: [PATCH 059/652] [mlir][gpu] Use `known_block_size` to set `maxntid` for NVVM target (#77301) Setting thread block size with `maxntid` on the kernel has great performance benefits. In this way, downstream PTX compiler can do better register allocation. MLIR's `gpu.launch` and `gpu.launch_func` already has an attribute (`known_block_size`) that keeps the thread block size when it is known. This PR simply uses this attribute to set `maxntid`. --- .../Conversion/GPUCommon/GPUOpsLowering.cpp | 20 ++++++++++++++++++- .../lib/Conversion/GPUCommon/GPUOpsLowering.h | 13 ++++++++---- .../GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 4 +++- .../Conversion/GPUToNVVM/gpu-to-nvvm.mlir | 9 +++++++++ 4 files changed, 40 insertions(+), 6 deletions(-) diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp index 6a005e67ca95..eeb8fbbb180b 100644 --- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp +++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp @@ -85,8 +85,26 @@ GPUFuncOpLowering::matchAndRewrite(gpu::GPUFuncOp gpuFuncOp, OpAdaptor adaptor, // Add a dialect specific kernel attribute in addition to GPU kernel // attribute. The former is necessary for further translation while the // latter is expected by gpu.launch_func. - if (gpuFuncOp.isKernel()) + if (gpuFuncOp.isKernel()) { attributes.emplace_back(kernelAttributeName, rewriter.getUnitAttr()); + + // Set the block size attribute if it is present. + if (kernelBlockSizeAttributeName.has_value()) { + std::optional dimX = + gpuFuncOp.getKnownBlockSize(gpu::Dimension::x); + std::optional dimY = + gpuFuncOp.getKnownBlockSize(gpu::Dimension::y); + std::optional dimZ = + gpuFuncOp.getKnownBlockSize(gpu::Dimension::z); + if (dimX.has_value() || dimY.has_value() || dimZ.has_value()) { + // If any of the dimensions are missing, fill them in with 1. + attributes.emplace_back( + kernelBlockSizeAttributeName.value(), + rewriter.getI32ArrayAttr( + {dimX.value_or(1), dimY.value_or(1), dimZ.value_or(1)})); + } + } + } auto llvmFuncOp = rewriter.create( gpuFuncOp.getLoc(), gpuFuncOp.getName(), funcType, LLVM::Linkage::External, /*dsoLocal=*/false, /*cconv=*/LLVM::CConv::C, diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h index a77db4a036ba..471a688e8546 100644 --- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h +++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h @@ -36,13 +36,15 @@ private: }; struct GPUFuncOpLowering : ConvertOpToLLVMPattern { - GPUFuncOpLowering(const LLVMTypeConverter &converter, - unsigned allocaAddrSpace, unsigned workgroupAddrSpace, - StringAttr kernelAttributeName) + GPUFuncOpLowering( + const LLVMTypeConverter &converter, unsigned allocaAddrSpace, + unsigned workgroupAddrSpace, StringAttr kernelAttributeName, + std::optional kernelBlockSizeAttributeName = std::nullopt) : ConvertOpToLLVMPattern(converter), allocaAddrSpace(allocaAddrSpace), workgroupAddrSpace(workgroupAddrSpace), - kernelAttributeName(kernelAttributeName) {} + kernelAttributeName(kernelAttributeName), + kernelBlockSizeAttributeName(kernelBlockSizeAttributeName) {} LogicalResult matchAndRewrite(gpu::GPUFuncOp gpuFuncOp, OpAdaptor adaptor, @@ -56,6 +58,9 @@ private: /// The attribute name to use instead of `gpu.kernel`. StringAttr kernelAttributeName; + + /// The attribute name to to set block size + std::optional kernelBlockSizeAttributeName; }; /// The lowering of gpu.printf to a call to HIP hostcalls diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp index e60fe5cbd760..a7ac2332961a 100644 --- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp +++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp @@ -352,7 +352,9 @@ void mlir::populateGpuToNVVMConversionPatterns(LLVMTypeConverter &converter, /*workgroupAddrSpace=*/ static_cast(NVVM::NVVMMemorySpace::kSharedMemorySpace), StringAttr::get(&converter.getContext(), - NVVM::NVVMDialect::getKernelFuncAttrName())); + NVVM::NVVMDialect::getKernelFuncAttrName()), + StringAttr::get(&converter.getContext(), + NVVM::NVVMDialect::getMaxntidAttrName())); populateOpPatterns(converter, patterns, "__nv_fabsf", "__nv_fabs"); diff --git a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir index 20a200e812c1..c7f1d4f124c1 100644 --- a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir +++ b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir @@ -627,6 +627,15 @@ gpu.module @test_module_31 { } } +gpu.module @gpumodule { +// CHECK-LABEL: func @kernel_with_block_size() +// CHECK: attributes {gpu.kernel, gpu.known_block_size = array, nvvm.kernel, nvvm.maxntid = [128 : i32, 1 : i32, 1 : i32]} + gpu.func @kernel_with_block_size() kernel attributes {gpu.known_block_size = array} { + gpu.return + } +} + + module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%toplevel_module: !transform.any_op {transform.readonly}) { %gpu_module = transform.structured.match ops{["gpu.module"]} in %toplevel_module -- GitLab From 4a456489e051ff037655597a0b54654aa1f5a2a5 Mon Sep 17 00:00:00 2001 From: Kiran Chandramohan Date: Mon, 8 Jan 2024 13:54:50 +0000 Subject: [PATCH 060/652] [Flang][OpenMP] Disable declarate target tests on Windows (#77306) These tests seem to be failing in Windows bots. See https://github.com/llvm/llvm-project/issues/77086 --- .../FIR/declare-target-implicit-func-and-subr-cap-enter.f90 | 2 ++ .../OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 | 2 ++ .../OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 | 2 ++ .../Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 | 2 ++ 4 files changed, 8 insertions(+) diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 index 8e88d1b0f52a..ff0f70444c60 100644 --- a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 +++ b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 @@ -3,6 +3,8 @@ !RUN: bbc -emit-fir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE +!XFAIL: system-windows + ! CHECK-LABEL: func.func @_QPimplicitly_captured_twice ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured_twice() result(k) diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 index a90b04246e6d..0b3f2db8ca1f 100644 --- a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 +++ b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 @@ -3,6 +3,8 @@ !RUN: bbc -emit-fir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE +!XFAIL: system-windows + ! CHECK-LABEL: func.func @_QPimplicitly_captured ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured(toggle) result(k) diff --git a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 index ed718a485e3d..4e0fa1fdc74c 100644 --- a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 +++ b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 @@ -3,6 +3,8 @@ !RUN: bbc -emit-hlfir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE +!XFAIL: system-windows + ! CHECK-LABEL: func.func @_QPimplicitly_captured_twice ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured_twice() result(k) diff --git a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 index df81c43a2fe6..f7fd836e50e9 100644 --- a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 +++ b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 @@ -3,6 +3,8 @@ !RUN: bbc -emit-hlfir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE +!XFAIL: system-windows + ! CHECK-LABEL: func.func @_QPimplicitly_captured ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured(toggle) result(k) -- GitLab From f0f16be77e1977d04535556ef69eaccd5bfef36f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 8 Jan 2024 14:55:41 +0100 Subject: [PATCH 061/652] [clang][Sema][NFC] Clean up BuildOverloadedCallExpr --- clang/lib/Sema/SemaOverload.cpp | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 8e3a2d128807..07da5cb150b4 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -13999,17 +13999,14 @@ ExprResult Sema::BuildOverloadedCallExpr(Scope *S, Expr *Fn, // encloses the call and whose return type contains a placeholder type as if // the UnresolvedLookupExpr was type-dependent. if (OverloadResult == OR_Success) { - FunctionDecl *FDecl = Best->Function; + const FunctionDecl *FDecl = Best->Function; if (FDecl && FDecl->isTemplateInstantiation() && FDecl->getReturnType()->isUndeducedType()) { - if (auto TP = FDecl->getTemplateInstantiationPattern(false)) { - if (TP->willHaveBody()) { - CallExpr *CE = - CallExpr::Create(Context, Fn, Args, Context.DependentTy, - VK_PRValue, RParenLoc, CurFPFeatureOverrides()); - result = CE; - return result; - } + if (const auto *TP = + FDecl->getTemplateInstantiationPattern(/*ForDefinition=*/false); + TP && TP->willHaveBody()) { + return CallExpr::Create(Context, Fn, Args, Context.DependentTy, + VK_PRValue, RParenLoc, CurFPFeatureOverrides()); } } } -- GitLab From 7ca4473dd97328ebaa95dd3411e3c817935389de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mirko=20Brku=C5=A1anin?= Date: Mon, 8 Jan 2024 15:06:58 +0100 Subject: [PATCH 062/652] [AMDGPU] Add new cache flushing instructions for GFX12 (#76944) Co-authored-by: Diana Picus --- llvm/lib/Target/AMDGPU/BUFInstructions.td | 6 +- llvm/lib/Target/AMDGPU/FLATInstructions.td | 39 ++- llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 10 + llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 70 +++- .../CodeGen/AMDGPU/GlobalISel/mubuf-global.ll | 30 +- .../atomic_optimizations_global_pointer.ll | 66 ++-- llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll | 9 +- llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll | 313 +++++++----------- llvm/test/CodeGen/AMDGPU/global-saddr-load.ll | 12 +- .../test/CodeGen/AMDGPU/global_atomics_i64.ll | 277 ++++++---------- .../CodeGen/AMDGPU/waitcnt-global-inv-wb.mir | 29 ++ llvm/test/MC/AMDGPU/gfx12_asm_vflat.s | 27 ++ .../Disassembler/AMDGPU/gfx12_dasm_vflat.txt | 27 ++ 13 files changed, 461 insertions(+), 454 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 43d35fa5291c..15a54856cb2e 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -1222,8 +1222,10 @@ defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Pseudo_Stores < } // End HasD16LoadStore -def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1", - int_amdgcn_buffer_wbinvl1>; +let SubtargetPredicate = isNotGFX12Plus in +def BUFFER_WBINVL1 : MUBUF_Invalidate < + "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1 +>; let SubtargetPredicate = HasAtomicFaddNoRtnInsts in defm BUFFER_ATOMIC_ADD_F32 : MUBUF_Pseudo_Atomics_NO_RTN< diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 615f8cd54d8f..345564c06af1 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -60,6 +60,7 @@ class FLAT_Pseudo has_sve = 0; // Scratch VGPR Enable bits<1> lds = 0; bits<1> sve = 0; + bits<1> has_offset = 1; let SubtargetPredicate = !if(is_flat_global, HasFlatGlobalInsts, !if(is_flat_scratch, HasFlatScratchInsts, HasFlatAddressSpace)); @@ -182,7 +183,7 @@ class VFLAT_Real op, FLAT_Pseudo ps, string opName = ps.Mnemonic> : let Inst{51-50} = cpol{4-3}; // scope let Inst{62-55} = !if(ps.has_data, vdata{7-0}, ?); let Inst{71-64} = !if(ps.has_vaddr, vaddr, ?); - let Inst{95-72} = offset; + let Inst{95-72} = !if(ps.has_offset, offset, ?); } class GlobalSaddrTable { @@ -340,6 +341,34 @@ multiclass FLAT_Global_Store_AddTid_Pseudo; } +class FLAT_Global_Invalidate_Writeback : + FLAT_Pseudo { + + let AsmMatchConverter = ""; + + let hasSideEffects = 1; + let mayLoad = 0; + let mayStore = 0; + let is_flat_global = 1; + + let has_offset = 0; + let has_saddr = 0; + let enabled_saddr = 0; + let saddr_value = 0; + let has_vdst = 0; + let has_data = 0; + let has_vaddr = 0; + let has_glc = 0; + let has_dlc = 0; + let glcValue = 0; + let dlcValue = 0; + let has_sccb = 0; + let sccbValue = 0; + let has_sve = 0; + let lds = 0; + let sve = 0; +} + class FlatScratchInst { string SVOp = sv_op; string Mode = mode; @@ -928,6 +957,10 @@ defm GLOBAL_LOAD_LDS_DWORD : FLAT_Global_Load_LDS_Pseudo <"global_load_lds_dwor let SubtargetPredicate = isGFX12Plus in { defm GLOBAL_ATOMIC_ORDERED_ADD_B64 : FLAT_Global_Atomic_Pseudo <"global_atomic_ordered_add_b64", VReg_64, i64>; + + def GLOBAL_INV : FLAT_Global_Invalidate_Writeback<"global_inv">; + def GLOBAL_WB : FLAT_Global_Invalidate_Writeback<"global_wb">; + def GLOBAL_WBINV : FLAT_Global_Invalidate_Writeback<"global_wbinv">; } // End SubtargetPredicate = isGFX12Plus } // End is_flat_global = 1 @@ -2662,6 +2695,10 @@ defm GLOBAL_ATOMIC_MAX_NUM_F32 : VGLOBAL_Real_Atomics_gfx12<0x052, "GLOBAL_A defm GLOBAL_ATOMIC_ADD_F32 : VGLOBAL_Real_Atomics_gfx12<0x056, "GLOBAL_ATOMIC_ADD_F32", "global_atomic_add_f32">; defm GLOBAL_ATOMIC_ORDERED_ADD_B64 : VGLOBAL_Real_Atomics_gfx12<0x073, "GLOBAL_ATOMIC_ORDERED_ADD_B64", "global_atomic_ordered_add_b64">; +defm GLOBAL_INV : VFLAT_Real_Base_gfx12<0x02b, "GLOBAL_INV", "global_inv">; +defm GLOBAL_WB : VFLAT_Real_Base_gfx12<0x02c, "GLOBAL_WB", "global_wb">; +defm GLOBAL_WBINV : VFLAT_Real_Base_gfx12<0x04f, "GLOBAL_WBINV", "global_wbinv">; + // ENC_VSCRATCH. defm SCRATCH_LOAD_U8 : VSCRATCH_Real_AllAddr_gfx12<0x10, "SCRATCH_LOAD_UBYTE", "scratch_load_u8", true>; defm SCRATCH_LOAD_I8 : VSCRATCH_Real_AllAddr_gfx12<0x11, "SCRATCH_LOAD_SBYTE", "scratch_load_i8", true>; diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 55ddb540c51e..1cb1d32707f2 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -1424,6 +1424,12 @@ bool SIInsertWaitcnts::mayAccessScratchThroughFlat( }); } +static bool isCacheInvOrWBInst(MachineInstr &Inst) { + auto Opc = Inst.getOpcode(); + return Opc == AMDGPU::GLOBAL_INV || Opc == AMDGPU::GLOBAL_WB || + Opc == AMDGPU::GLOBAL_WBINV; +} + void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst, WaitcntBrackets *ScoreBrackets) { // Now look at the instruction opcode. If it is a memory access @@ -1439,6 +1445,10 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst, ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst); } } else if (TII->isFLAT(Inst)) { + // TODO: Track this properly. + if (isCacheInvOrWBInst(Inst)) + return; + assert(Inst.mayLoadOrStore()); int FlatASCount = 0; diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp index 10ec54d3317f..6d749ad1ad24 100644 --- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -578,6 +578,14 @@ public: bool IsNonTemporal) const override; }; +class SIGfx12CacheControl : public SIGfx11CacheControl { +public: + SIGfx12CacheControl(const GCNSubtarget &ST) : SIGfx11CacheControl(ST) {} + + bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope, + SIAtomicAddrSpace AddrSpace, Position Pos) const override; +}; + class SIMemoryLegalizer final : public MachineFunctionPass { private: @@ -857,7 +865,9 @@ std::unique_ptr SICacheControl::create(const GCNSubtarget &ST) { return std::make_unique(ST); if (Generation < AMDGPUSubtarget::GFX11) return std::make_unique(ST); - return std::make_unique(ST); + if (Generation < AMDGPUSubtarget::GFX12) + return std::make_unique(ST); + return std::make_unique(ST); } bool SIGfx6CacheControl::enableLoadCacheBypass( @@ -1423,7 +1433,7 @@ bool SIGfx90ACacheControl::insertRelease(MachineBasicBlock::iterator &MI, bool Changed = false; MachineBasicBlock &MBB = *MI->getParent(); - DebugLoc DL = MI->getDebugLoc(); + const DebugLoc &DL = MI->getDebugLoc(); if (Pos == Position::AFTER) ++MI; @@ -2132,6 +2142,62 @@ bool SIGfx11CacheControl::enableVolatileAndOrNonTemporal( return Changed; } +bool SIGfx12CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, + SIAtomicScope Scope, + SIAtomicAddrSpace AddrSpace, + Position Pos) const { + if (!InsertCacheInv) + return false; + + MachineBasicBlock &MBB = *MI->getParent(); + DebugLoc DL = MI->getDebugLoc(); + + /// The scratch address space does not need the global memory cache + /// to be flushed as all memory operations by the same thread are + /// sequentially consistent, and no other thread can access scratch + /// memory. + + /// Other address spaces do not have a cache. + if ((AddrSpace & SIAtomicAddrSpace::GLOBAL) == SIAtomicAddrSpace::NONE) + return false; + + AMDGPU::CPol::CPol ScopeImm = AMDGPU::CPol::SCOPE_DEV; + switch (Scope) { + case SIAtomicScope::SYSTEM: + ScopeImm = AMDGPU::CPol::SCOPE_SYS; + break; + case SIAtomicScope::AGENT: + ScopeImm = AMDGPU::CPol::SCOPE_DEV; + break; + case SIAtomicScope::WORKGROUP: + // In WGP mode the waves of a work-group can be executing on either CU of + // the WGP. Therefore we need to invalidate the L0 which is per CU. + // Otherwise in CU mode all waves of a work-group are on the same CU, and so + // the L0 does not need to be invalidated. + if (ST.isCuModeEnabled()) + return false; + + ScopeImm = AMDGPU::CPol::SCOPE_SE; + break; + case SIAtomicScope::WAVEFRONT: + case SIAtomicScope::SINGLETHREAD: + // No cache to invalidate. + return false; + default: + llvm_unreachable("Unsupported synchronization scope"); + } + + if (Pos == Position::AFTER) + ++MI; + + BuildMI(MBB, MI, DL, TII->get(AMDGPU::GLOBAL_INV)).addImm(ScopeImm); + + if (Pos == Position::AFTER) + --MI; + + return true; +} + bool SIMemoryLegalizer::removeAtomicPseudoMIs() { if (AtomicPseudoMIs.empty()) return false; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll index 8ca09973a8ed..904120e7d118 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll @@ -1295,8 +1295,7 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4095(ptr addrspace(1) inr ; GFX12-NEXT: v_dual_mov_b32 v0, 2 :: v_dual_mov_b32 v1, 0 ; GFX12-NEXT: global_atomic_add_u32 v0, v1, v0, s[2:3] offset:16380 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095 %result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst @@ -1347,8 +1346,7 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4294967296(ptr addrspace( ; GFX12-NEXT: v_mov_b32_e32 v2, 2 ; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296 %result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst @@ -1389,8 +1387,7 @@ define amdgpu_ps float @mubuf_atomicrmw_vgpr_ptr_offset4095(ptr addrspace(1) %pt ; GFX12-NEXT: v_mov_b32_e32 v2, 2 ; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v2, off offset:16380 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095 %result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst @@ -1438,8 +1435,7 @@ define amdgpu_ps float @mubuf_atomicrmw_vgpr_ptr_offset4294967296(ptr addrspace( ; GFX12-NEXT: v_mov_b32_e32 v2, 2 ; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296 %result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst @@ -1491,8 +1487,7 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_vgpr_offset(ptr addrspace(1) in ; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v4, off th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %voffset %result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst @@ -1536,8 +1531,7 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4095(ptr addrspace(1) inreg ; GFX12-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[1:2], s[2:3] offset:16380 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095 %result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst @@ -1590,8 +1584,7 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4294967296(ptr addrspace(1) ; GFX12-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0 ; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[3:4], v[1:2], off th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296 %result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst @@ -1633,8 +1626,7 @@ define amdgpu_ps float @mubuf_cmpxchg_vgpr_ptr_offset4095(ptr addrspace(1) %ptr, ; GFX12-NEXT: v_mov_b32_e32 v4, v2 ; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[0:1], v[3:4], off offset:16380 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095 %result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst @@ -1682,8 +1674,7 @@ define amdgpu_ps float @mubuf_cmpxchg_vgpr_ptr_offset4294967296(ptr addrspace(1) ; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo ; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296 %result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst @@ -1736,8 +1727,7 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_vgpr_offset(ptr addrspace(1) inre ; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo ; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %voffset %result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll index 9f97f1f4bace..26d981ad7b4b 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll @@ -240,8 +240,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1264-NEXT: s_mov_b32 s9, s3 ; GFX1264-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB0_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -276,8 +275,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-NEXT: s_mov_b32 s9, s3 ; GFX1232-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB0_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -571,8 +569,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_mov_b32 s13, s7 ; GFX1264-NEXT: buffer_atomic_add_u32 v1, off, s[12:15], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB1_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -610,8 +607,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_mov_b32 s9, s7 ; GFX1232-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB1_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -967,8 +963,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_mov_b32 s9, s3 ; GFX1264-NEXT: buffer_atomic_add_u32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB2_4: ; GFX1264-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -1016,8 +1011,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_mov_b32 s9, s3 ; GFX1232-NEXT: buffer_atomic_add_u32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB2_4: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s5 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -1284,8 +1278,7 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1264-NEXT: s_mov_b32 s9, s3 ; GFX1264-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB3_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -1321,8 +1314,7 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-NEXT: s_mov_b32 s9, s3 ; GFX1232-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB3_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -1673,8 +1665,7 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_mov_b32 s9, s7 ; GFX1264-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB4_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1264-NEXT: v_readfirstlane_b32 s2, v0 @@ -1718,8 +1709,7 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_mov_b32 s9, s7 ; GFX1232-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB4_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1232-NEXT: v_readfirstlane_b32 s2, v0 @@ -1836,8 +1826,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX12-NEXT: s_mov_b32 s4, s0 ; GFX12-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_mov_b32 s5, s1 ; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null ; GFX12-NEXT: s_nop 0 @@ -2117,8 +2106,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1264-NEXT: s_mov_b32 s9, s3 ; GFX1264-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB6_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -2154,8 +2142,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-NEXT: s_mov_b32 s9, s3 ; GFX1232-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB6_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -2454,8 +2441,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_mov_b32 s13, s7 ; GFX1264-NEXT: buffer_atomic_sub_u32 v1, off, s[12:15], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB7_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -2493,8 +2479,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_mov_b32 s9, s7 ; GFX1232-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB7_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -2850,8 +2835,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_mov_b32 s9, s3 ; GFX1264-NEXT: buffer_atomic_sub_u32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB8_4: ; GFX1264-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -2899,8 +2883,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_mov_b32 s9, s3 ; GFX1232-NEXT: buffer_atomic_sub_u32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB8_4: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s5 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -3218,8 +3201,7 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1264-NEXT: s_mov_b32 s9, s3 ; GFX1264-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB9_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -3258,8 +3240,7 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-NEXT: s_mov_b32 s9, s3 ; GFX1232-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB9_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -3626,8 +3607,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_mov_b32 s9, s7 ; GFX1264-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1264-NEXT: s_waitcnt vmcnt(0) -; GFX1264-NEXT: buffer_gl0_inv -; GFX1264-NEXT: buffer_gl1_inv +; GFX1264-NEXT: global_inv scope:SCOPE_DEV ; GFX1264-NEXT: .LBB10_2: ; GFX1264-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) @@ -3674,8 +3654,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_mov_b32 s9, s7 ; GFX1232-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) -; GFX1232-NEXT: buffer_gl0_inv -; GFX1232-NEXT: buffer_gl1_inv +; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB10_2: ; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -3795,8 +3774,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX12-NEXT: s_mov_b32 s4, s0 ; GFX12-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_mov_b32 s5, s1 ; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null ; GFX12-NEXT: s_nop 0 diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll index 1df9a250a315..e18bdc89e7d4 100644 --- a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll +++ b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll @@ -101,8 +101,7 @@ define float @syncscope_system(ptr %addr, float %val) #0 { ; GFX1200-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1200-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN ; GFX1200-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1200-NEXT: buffer_gl0_inv -; GFX1200-NEXT: buffer_gl1_inv +; GFX1200-NEXT: global_inv scope:SCOPE_SYS ; GFX1200-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4 ; GFX1200-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -209,7 +208,7 @@ define float @syncscope_workgroup_rtn(ptr %addr, float %val) #0 { ; GFX1200-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1200-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN ; GFX1200-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1200-NEXT: buffer_gl0_inv +; GFX1200-NEXT: global_inv scope:SCOPE_SE ; GFX1200-NEXT: s_setpc_b64 s[30:31] %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst ret float %res @@ -340,7 +339,7 @@ define void @syncscope_workgroup_nortn(ptr %addr, float %val) #0 { ; GFX1200-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX1200-NEXT: s_waitcnt lgkmcnt(0) ; GFX1200-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX1200-NEXT: buffer_gl0_inv +; GFX1200-NEXT: global_inv scope:SCOPE_SE ; GFX1200-NEXT: s_setpc_b64 s[30:31] %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst ret void @@ -435,7 +434,7 @@ define float @no_unsafe(ptr %addr, float %val) { ; GFX1200-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1200-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN ; GFX1200-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1200-NEXT: buffer_gl0_inv +; GFX1200-NEXT: global_inv scope:SCOPE_SE ; GFX1200-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4 ; GFX1200-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll index f1879f287667..d7f780e414ca 100644 --- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll +++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll @@ -43,8 +43,7 @@ define amdgpu_kernel void @atomic_add_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_add_u64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -101,8 +100,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_add_u64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -166,8 +164,7 @@ define amdgpu_kernel void @atomic_add_i64_addr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_add_u64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -230,8 +227,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_add_u64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -279,8 +275,7 @@ define amdgpu_kernel void @atomic_add_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_add_u64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile add ptr %out, i64 %in syncscope("agent") seq_cst @@ -332,8 +327,7 @@ define amdgpu_kernel void @atomic_add_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_add_u64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -392,8 +386,7 @@ define amdgpu_kernel void @atomic_add_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_add_u64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -451,8 +444,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_add_u64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -503,8 +495,7 @@ define amdgpu_kernel void @atomic_and_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_and_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -561,8 +552,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_and_b64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -626,8 +616,7 @@ define amdgpu_kernel void @atomic_and_i64_addr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_and_b64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -690,8 +679,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_and_b64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -739,8 +727,7 @@ define amdgpu_kernel void @atomic_and_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_and_b64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile and ptr %out, i64 %in syncscope("agent") seq_cst @@ -792,8 +779,7 @@ define amdgpu_kernel void @atomic_and_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_and_b64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -852,8 +838,7 @@ define amdgpu_kernel void @atomic_and_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_and_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -911,8 +896,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_and_b64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -963,8 +947,7 @@ define amdgpu_kernel void @atomic_sub_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_sub_u64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -1021,8 +1004,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_sub_u64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1086,8 +1068,7 @@ define amdgpu_kernel void @atomic_sub_i64_addr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_sub_u64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -1150,8 +1131,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_sub_u64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1199,8 +1179,7 @@ define amdgpu_kernel void @atomic_sub_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_sub_u64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile sub ptr %out, i64 %in syncscope("agent") seq_cst @@ -1252,8 +1231,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_sub_u64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1312,8 +1290,7 @@ define amdgpu_kernel void @atomic_sub_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_sub_u64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -1371,8 +1348,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_sub_u64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1421,7 +1397,7 @@ define amdgpu_kernel void @atomic_max_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_max_i64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -1478,7 +1454,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_max_i64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1540,7 +1516,7 @@ define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_max_i64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -1603,7 +1579,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_max_i64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1649,7 +1625,7 @@ define amdgpu_kernel void @atomic_max_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_max_i64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile max ptr %out, i64 %in syncscope("workgroup") seq_cst @@ -1701,7 +1677,7 @@ define amdgpu_kernel void @atomic_max_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_max_i64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1758,7 +1734,7 @@ define amdgpu_kernel void @atomic_max_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_max_i64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -1816,7 +1792,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_max_i64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1865,7 +1841,7 @@ define amdgpu_kernel void @atomic_umax_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_max_u64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -1922,7 +1898,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_offset(ptr %out, ptr %out2, i64 % ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_max_u64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -1984,7 +1960,7 @@ define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr %out, i64 %in, i64 ; GFX12-NEXT: flat_atomic_max_u64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -2047,7 +2023,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr %out, ptr %out2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_max_u64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2093,7 +2069,7 @@ define amdgpu_kernel void @atomic_umax_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_max_u64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile umax ptr %out, i64 %in syncscope("workgroup") seq_cst @@ -2145,7 +2121,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_max_u64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2202,7 +2178,7 @@ define amdgpu_kernel void @atomic_umax_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_max_u64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -2260,7 +2236,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr %out, ptr %out2, i64 % ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_max_u64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2309,7 +2285,7 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_min_i64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -2366,7 +2342,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_min_i64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2428,7 +2404,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_min_i64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -2491,7 +2467,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_min_i64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2537,7 +2513,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_min_i64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile min ptr %out, i64 %in syncscope("workgroup") seq_cst @@ -2589,7 +2565,7 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_min_i64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2646,7 +2622,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_min_i64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -2704,7 +2680,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_min_i64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2753,7 +2729,7 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_min_u64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -2810,7 +2786,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 % ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_min_u64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2872,7 +2848,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64 ; GFX12-NEXT: flat_atomic_min_u64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -2935,7 +2911,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_min_u64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -2981,7 +2957,7 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_min_u64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile umin ptr %out, i64 %in syncscope("workgroup") seq_cst @@ -3033,7 +3009,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_min_u64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3090,7 +3066,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_min_u64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -3148,7 +3124,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 % ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_min_u64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3199,8 +3175,7 @@ define amdgpu_kernel void @atomic_or_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_or_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -3257,8 +3232,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_offset(ptr %out, ptr %out2, i64 %in ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_or_b64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3322,8 +3296,7 @@ define amdgpu_kernel void @atomic_or_i64_addr64_offset(ptr %out, i64 %in, i64 %i ; GFX12-NEXT: flat_atomic_or_b64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -3386,8 +3359,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_or_b64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3435,8 +3407,7 @@ define amdgpu_kernel void @atomic_or_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_or_b64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile or ptr %out, i64 %in syncscope("agent") seq_cst @@ -3488,8 +3459,7 @@ define amdgpu_kernel void @atomic_or_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_or_b64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3548,8 +3518,7 @@ define amdgpu_kernel void @atomic_or_i64_addr64(ptr %out, i64 %in, i64 %index) { ; GFX12-NEXT: flat_atomic_or_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -3607,8 +3576,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64(ptr %out, ptr %out2, i64 %in ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_or_b64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3659,8 +3627,7 @@ define amdgpu_kernel void @atomic_xchg_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -3708,8 +3675,7 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr %out, double %in) { ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr double, ptr %out, i64 4 @@ -3757,8 +3723,7 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr %out, ptr %in) { ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr ptr, ptr %out, i32 4 @@ -3815,8 +3780,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_offset(ptr %out, ptr %out2, i64 % ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3880,8 +3844,7 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(ptr %out, i64 %in, i64 ; GFX12-NEXT: flat_atomic_swap_b64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -3944,8 +3907,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(ptr %out, ptr %out2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -3993,8 +3955,7 @@ define amdgpu_kernel void @atomic_xchg_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile xchg ptr %out, i64 %in syncscope("agent") seq_cst @@ -4046,8 +4007,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -4106,8 +4066,7 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_swap_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -4165,8 +4124,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(ptr %out, ptr %out2, i64 % ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -4217,8 +4175,7 @@ define amdgpu_kernel void @atomic_xor_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_xor_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -4275,8 +4232,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_xor_b64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -4340,8 +4296,7 @@ define amdgpu_kernel void @atomic_xor_i64_addr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_xor_b64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -4404,8 +4359,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_xor_b64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -4453,8 +4407,7 @@ define amdgpu_kernel void @atomic_xor_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_xor_b64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile xor ptr %out, i64 %in syncscope("agent") seq_cst @@ -4506,8 +4459,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_xor_b64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -4566,8 +4518,7 @@ define amdgpu_kernel void @atomic_xor_i64_addr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_xor_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -4625,8 +4576,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_xor_b64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -4678,8 +4628,7 @@ define amdgpu_kernel void @atomic_load_i64_offset(ptr %in, ptr %out) { ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] offset:32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -4726,8 +4675,7 @@ define amdgpu_kernel void @atomic_load_i64(ptr %in, ptr %out) { ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -4790,8 +4738,7 @@ define amdgpu_kernel void @atomic_load_i64_addr64_offset(ptr %in, ptr %out, i64 ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] offset:32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -4852,8 +4799,7 @@ define amdgpu_kernel void @atomic_load_i64_addr64(ptr %in, ptr %out, i64 %index) ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -5094,8 +5040,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr %out, i64 %in, i64 %old ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -5152,8 +5097,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr %out, i64 %in, i64 %ol ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:3] offset:72000 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 9000 @@ -5211,8 +5155,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(ptr %out, ptr %out2, i6 ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[0:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -5277,8 +5220,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr %out, i64 %in, i ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -5349,8 +5291,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr %out, ptr %o ; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[0:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -5408,8 +5349,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64(ptr %out, i64 %in, i64 %old) { ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %val = cmpxchg volatile ptr %out, i64 %old, i64 %in syncscope("agent") seq_cst seq_cst @@ -5462,8 +5402,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret(ptr %out, ptr %out2, i64 %in, ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[0:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -5523,8 +5462,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr %out, i64 %in, i64 %ind ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -5590,8 +5528,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr %out, ptr %out2, i6 ; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 ; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[0:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -5644,8 +5581,7 @@ define amdgpu_kernel void @atomic_load_f64_offset(ptr %in, ptr %out) { ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] offset:32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -5692,8 +5628,7 @@ define amdgpu_kernel void @atomic_load_f64(ptr %in, ptr %out) { ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -5756,8 +5691,7 @@ define amdgpu_kernel void @atomic_load_f64_addr64_offset(ptr %in, ptr %out, i64 ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] offset:32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -5818,8 +5752,7 @@ define amdgpu_kernel void @atomic_load_f64_addr64(ptr %in, ptr %out, i64 %index) ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm entry: @@ -6051,8 +5984,7 @@ define amdgpu_kernel void @atomic_inc_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_inc_u64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -6109,8 +6041,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_inc_u64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -6174,8 +6105,7 @@ define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_inc_u64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -6238,8 +6168,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_inc_u64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -6287,8 +6216,7 @@ define amdgpu_kernel void @atomic_inc_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_inc_u64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile uinc_wrap ptr %out, i64 %in syncscope("agent") seq_cst @@ -6340,8 +6268,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_inc_u64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -6400,8 +6327,7 @@ define amdgpu_kernel void @atomic_inc_i64_incr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_inc_u64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -6459,8 +6385,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_inc_u64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -6511,8 +6436,7 @@ define amdgpu_kernel void @atomic_dec_i64_offset(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_dec_u64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr %out, i64 4 @@ -6569,8 +6493,7 @@ define amdgpu_kernel void @atomic_dec_i64_ret_offset(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_dec_u64 v[0:1], v[0:1], v[2:3] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -6634,8 +6557,7 @@ define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr %out, i64 %in, i64 % ; GFX12-NEXT: flat_atomic_dec_u64 v[2:3], v[0:1] offset:32 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -6698,8 +6620,7 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64_offset(ptr %out, ptr %out2, ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_dec_u64 v[0:1], v[2:3], v[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -6747,8 +6668,7 @@ define amdgpu_kernel void @atomic_dec_i64(ptr %out, i64 %in) { ; GFX12-NEXT: flat_atomic_dec_u64 v[0:1], v[2:3] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile udec_wrap ptr %out, i64 %in syncscope("agent") seq_cst @@ -6800,8 +6720,7 @@ define amdgpu_kernel void @atomic_dec_i64_ret(ptr %out, ptr %out2, i64 %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 ; GFX12-NEXT: flat_atomic_dec_u64 v[0:1], v[0:1], v[2:3] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm @@ -6860,8 +6779,7 @@ define amdgpu_kernel void @atomic_dec_i64_decr64(ptr %out, i64 %in, i64 %index) ; GFX12-NEXT: flat_atomic_dec_u64 v[2:3], v[0:1] ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr %out, i64 %index @@ -6919,8 +6837,7 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64(ptr %out, ptr %out2, i64 %i ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: flat_atomic_dec_u64 v[0:1], v[2:3], v[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1] ; GFX12-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll index de4f748413e6..b2b3f3e1bfbd 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll @@ -3583,8 +3583,7 @@ define amdgpu_ps float @atomic_global_load_saddr_i32(ptr addrspace(1) inreg %sba ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3621,8 +3620,7 @@ define amdgpu_ps float @atomic_global_load_saddr_i32_immneg128(ptr addrspace(1) ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3660,8 +3658,7 @@ define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64(ptr addrspace(1) inre ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3698,8 +3695,7 @@ define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64_immneg128(ptr addrspa ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll index 3d11c8bc499e..325dae172d52 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll @@ -51,8 +51,7 @@ define amdgpu_kernel void @atomic_add_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_add_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -123,8 +122,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -202,8 +200,7 @@ define amdgpu_kernel void @atomic_add_i64_addr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_add_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -284,8 +281,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(ptr addrspace(1) %ou ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -349,8 +345,7 @@ define amdgpu_kernel void @atomic_add_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_add_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile add ptr addrspace(1) %out, i64 %in syncscope("agent") seq_cst @@ -420,8 +415,7 @@ define amdgpu_kernel void @atomic_add_i64_ret(ptr addrspace(1) %out, ptr addrspa ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -496,8 +490,7 @@ define amdgpu_kernel void @atomic_add_i64_addr64(ptr addrspace(1) %out, i64 %in, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_add_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -575,8 +568,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -635,8 +627,7 @@ define amdgpu_kernel void @atomic_and_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_and_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -707,8 +698,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_and_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -786,8 +776,7 @@ define amdgpu_kernel void @atomic_and_i64_addr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_and_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -868,8 +857,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(ptr addrspace(1) %ou ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_and_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -933,8 +921,7 @@ define amdgpu_kernel void @atomic_and_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_and_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile and ptr addrspace(1) %out, i64 %in syncscope("agent") seq_cst @@ -1004,8 +991,7 @@ define amdgpu_kernel void @atomic_and_i64_ret(ptr addrspace(1) %out, ptr addrspa ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_and_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -1080,8 +1066,7 @@ define amdgpu_kernel void @atomic_and_i64_addr64(ptr addrspace(1) %out, i64 %in, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_and_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -1159,8 +1144,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_and_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -1219,8 +1203,7 @@ define amdgpu_kernel void @atomic_sub_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_sub_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -1291,8 +1274,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -1370,8 +1352,7 @@ define amdgpu_kernel void @atomic_sub_i64_addr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_sub_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -1452,8 +1433,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr addrspace(1) %ou ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -1517,8 +1497,7 @@ define amdgpu_kernel void @atomic_sub_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_sub_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile sub ptr addrspace(1) %out, i64 %in syncscope("agent") seq_cst @@ -1588,8 +1567,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret(ptr addrspace(1) %out, ptr addrspa ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -1664,8 +1642,7 @@ define amdgpu_kernel void @atomic_sub_i64_addr64(ptr addrspace(1) %out, i64 %in, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_sub_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -1743,8 +1720,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -1797,7 +1773,7 @@ define amdgpu_kernel void @atomic_max_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_max_i64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -1865,7 +1841,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -1937,7 +1913,7 @@ define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_max_i64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -2015,7 +1991,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr addrspace(1) %ou ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -2073,7 +2049,7 @@ define amdgpu_kernel void @atomic_max_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_max_i64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile max ptr addrspace(1) %out, i64 %in syncscope("workgroup") seq_cst @@ -2140,7 +2116,7 @@ define amdgpu_kernel void @atomic_max_i64_ret(ptr addrspace(1) %out, ptr addrspa ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -2209,7 +2185,7 @@ define amdgpu_kernel void @atomic_max_i64_addr64(ptr addrspace(1) %out, i64 %in, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_max_i64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -2284,7 +2260,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -2337,7 +2313,7 @@ define amdgpu_kernel void @atomic_umax_i64_offset(ptr addrspace(1) %out, i64 %in ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_max_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -2405,7 +2381,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -2477,7 +2453,7 @@ define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr addrspace(1) %out, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_max_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -2555,7 +2531,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr addrspace(1) %o ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -2613,7 +2589,7 @@ define amdgpu_kernel void @atomic_umax_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_max_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile umax ptr addrspace(1) %out, i64 %in syncscope("workgroup") seq_cst @@ -2680,7 +2656,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret(ptr addrspace(1) %out, ptr addrsp ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -2749,7 +2725,7 @@ define amdgpu_kernel void @atomic_umax_i64_addr64(ptr addrspace(1) %out, i64 %in ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_max_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -2824,7 +2800,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -2877,7 +2853,7 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_min_i64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -2945,7 +2921,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3017,7 +2993,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_min_i64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -3095,7 +3071,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr addrspace(1) %ou ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3153,7 +3129,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_min_i64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile min ptr addrspace(1) %out, i64 %in syncscope("workgroup") seq_cst @@ -3220,7 +3196,7 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr addrspace(1) %out, ptr addrspa ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3289,7 +3265,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr addrspace(1) %out, i64 %in, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_min_i64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -3364,7 +3340,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3417,7 +3393,7 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr addrspace(1) %out, i64 %in ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_min_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -3485,7 +3461,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3557,7 +3533,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr addrspace(1) %out, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_min_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -3635,7 +3611,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr addrspace(1) %o ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3693,7 +3669,7 @@ define amdgpu_kernel void @atomic_umin_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_min_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile umin ptr addrspace(1) %out, i64 %in syncscope("workgroup") seq_cst @@ -3760,7 +3736,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr addrspace(1) %out, ptr addrsp ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3829,7 +3805,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr addrspace(1) %out, i64 %in ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_min_u64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -3904,7 +3880,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv +; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -3963,8 +3939,7 @@ define amdgpu_kernel void @atomic_or_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_or_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -4035,8 +4010,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_offset(ptr addrspace(1) %out, ptr a ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_or_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -4114,8 +4088,7 @@ define amdgpu_kernel void @atomic_or_i64_addr64_offset(ptr addrspace(1) %out, i6 ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_or_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -4196,8 +4169,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(ptr addrspace(1) %out ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_or_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -4261,8 +4233,7 @@ define amdgpu_kernel void @atomic_or_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_or_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile or ptr addrspace(1) %out, i64 %in syncscope("agent") seq_cst @@ -4332,8 +4303,7 @@ define amdgpu_kernel void @atomic_or_i64_ret(ptr addrspace(1) %out, ptr addrspac ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_or_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -4408,8 +4378,7 @@ define amdgpu_kernel void @atomic_or_i64_addr64(ptr addrspace(1) %out, i64 %in, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_or_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -4487,8 +4456,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64(ptr addrspace(1) %out, ptr a ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_or_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -4547,8 +4515,7 @@ define amdgpu_kernel void @atomic_xchg_i64_offset(ptr addrspace(1) %out, i64 %in ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -4603,8 +4570,7 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr addrspace(1) %out, double ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr double, ptr addrspace(1) %out, i64 4 @@ -4659,8 +4625,7 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr ptr, ptr addrspace(1) %out, i64 4 @@ -4731,8 +4696,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -4810,8 +4774,7 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(ptr addrspace(1) %out, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -4892,8 +4855,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(ptr addrspace(1) %o ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -4957,8 +4919,7 @@ define amdgpu_kernel void @atomic_xchg_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile xchg ptr addrspace(1) %out, i64 %in syncscope("agent") seq_cst @@ -5028,8 +4989,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret(ptr addrspace(1) %out, ptr addrsp ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -5104,8 +5064,7 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64(ptr addrspace(1) %out, i64 %in ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -5183,8 +5142,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -5243,8 +5201,7 @@ define amdgpu_kernel void @atomic_xor_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_xor_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -5315,8 +5272,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -5394,8 +5350,7 @@ define amdgpu_kernel void @atomic_xor_i64_addr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_xor_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -5476,8 +5431,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(ptr addrspace(1) %ou ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -5541,8 +5495,7 @@ define amdgpu_kernel void @atomic_xor_i64(ptr addrspace(1) %out, i64 %in) { ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_xor_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %tmp0 = atomicrmw volatile xor ptr addrspace(1) %out, i64 %in syncscope("agent") seq_cst @@ -5612,8 +5565,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret(ptr addrspace(1) %out, ptr addrspa ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -5688,8 +5640,7 @@ define amdgpu_kernel void @atomic_xor_i64_addr64(ptr addrspace(1) %out, i64 %in, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_xor_b64 v2, v[0:1], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -5767,8 +5718,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64(ptr addrspace(1) %out, ptr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -5843,8 +5793,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr addrspace(1) %out, i64 ; GFX12-NEXT: v_mov_b32_e32 v2, s0 ; GFX12-NEXT: global_atomic_cmpswap_b64 v4, v[0:3], s[4:5] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -5917,8 +5866,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr addrspace(1) %out, i64 ; GFX12-NEXT: v_mov_b32_e32 v2, s0 ; GFX12-NEXT: global_atomic_cmpswap_b64 v4, v[0:3], s[4:5] offset:72000 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 9000 @@ -5991,8 +5939,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(ptr addrspace(1) %out, ; GFX12-NEXT: v_mov_b32_e32 v2, s6 ; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v4, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6074,8 +6021,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr addrspace(1) %ou ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-NEXT: global_atomic_cmpswap_b64 v4, v[0:3], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -6168,8 +6114,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr addrspace(1) ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v4, v[0:1], s[6:7] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6246,8 +6191,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64(ptr addrspace(1) %out, i64 %in, i6 ; GFX12-NEXT: v_mov_b32_e32 v2, s0 ; GFX12-NEXT: global_atomic_cmpswap_b64 v4, v[0:3], s[4:5] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %val = cmpxchg volatile ptr addrspace(1) %out, i64 %old, i64 %in syncscope("agent") seq_cst seq_cst @@ -6319,8 +6263,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret(ptr addrspace(1) %out, ptr add ; GFX12-NEXT: v_mov_b32_e32 v2, s6 ; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v4, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6399,8 +6342,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr addrspace(1) %out, i64 ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-NEXT: global_atomic_cmpswap_b64 v4, v[0:3], s[0:1] ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -6490,8 +6432,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr addrspace(1) %out, ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[0:1] th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v4, v[0:1], s[6:7] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6557,8 +6498,7 @@ define amdgpu_kernel void @atomic_load_i64_offset(ptr addrspace(1) %in, ptr addr ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: global_load_b64 v[0:1], v2, s[0:1] offset:32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6625,8 +6565,7 @@ define amdgpu_kernel void @atomic_load_i64_neg_offset(ptr addrspace(1) %in, ptr ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: global_load_b64 v[0:1], v2, s[0:1] offset:-32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6689,8 +6628,7 @@ define amdgpu_kernel void @atomic_load_i64(ptr addrspace(1) %in, ptr addrspace(1 ; GFX12-NEXT: s_waitcnt lgkmcnt(0) ; GFX12-NEXT: global_load_b64 v[0:1], v2, s[0:1] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6771,8 +6709,7 @@ define amdgpu_kernel void @atomic_load_i64_addr64_offset(ptr addrspace(1) %in, p ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_load_b64 v[0:1], v2, s[0:1] offset:32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6853,8 +6790,7 @@ define amdgpu_kernel void @atomic_load_i64_addr64(ptr addrspace(1) %in, ptr addr ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_load_b64 v[0:1], v2, s[0:1] th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -6936,8 +6872,7 @@ define amdgpu_kernel void @atomic_load_f64_addr64_offset(ptr addrspace(1) %in, p ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5] ; GFX12-NEXT: global_load_b64 v[0:1], v2, s[0:1] offset:32 th:TH_LOAD_NT ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -7307,8 +7242,7 @@ define amdgpu_kernel void @atomic_inc_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_inc_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -7379,8 +7313,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_inc_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -7458,8 +7391,7 @@ define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_inc_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index @@ -7515,8 +7447,7 @@ define amdgpu_kernel void @atomic_dec_i64_offset(ptr addrspace(1) %out, i64 %in) ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_dec_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %out, i64 4 @@ -7587,8 +7518,7 @@ define amdgpu_kernel void @atomic_dec_i64_ret_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s4 ; GFX12-NEXT: global_atomic_dec_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_waitcnt vmcnt(0) -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[2:3] ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -7666,8 +7596,7 @@ define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr addrspace(1) %out, i ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[0:1] ; GFX12-NEXT: global_atomic_dec_u64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX12-NEXT: buffer_gl0_inv -; GFX12-NEXT: buffer_gl1_inv +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %ptr = getelementptr i64, ptr addrspace(1) %out, i64 %index diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir new file mode 100644 index 000000000000..c06e931c65d5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir @@ -0,0 +1,29 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck -check-prefix=GFX12 %s + +# Check that we correctly track that GLOBAL_INV increases LOAD_cnt. +# We use a straightforward dependency between a GLOBAL_LOAD and an instruction +# that uses its result - the S_WAIT_LOADCNT introduced before the use should +# reflect the fact that there is a GLOBAL_INV between them. +# FIXME: We could get away with a S_WAIT_LOADCNT 1 here. +--- +name: waitcnt-global-inv +machineFunctionInfo: + isEntryFunction: true +body: | + bb.0: + liveins: $vgpr0, $vgpr1, $sgpr2_sgpr3 + + ; GFX12-LABEL: name: waitcnt-global-inv + ; GFX12: liveins: $vgpr0, $vgpr1, $sgpr2_sgpr3 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: renamable $vgpr0 = GLOBAL_LOAD_DWORD_SADDR renamable $sgpr2_sgpr3, killed $vgpr0, 0, 0, implicit $exec :: (load (s32), addrspace 1) + ; GFX12-NEXT: GLOBAL_INV 16, implicit $exec + ; GFX12-NEXT: S_WAITCNT 1015 + ; GFX12-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $exec + renamable $vgpr0 = GLOBAL_LOAD_DWORD_SADDR renamable $sgpr2_sgpr3, killed $vgpr0, 0, 0, implicit $exec :: (load (s32), addrspace 1) + GLOBAL_INV 16, implicit $exec + $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $exec +... + +# TODO: Test for GLOBAL_WB, GLOBAL_WBINV diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vflat.s b/llvm/test/MC/AMDGPU/gfx12_asm_vflat.s index 95d352b421a2..daf25d314c78 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vflat.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vflat.s @@ -1920,6 +1920,33 @@ global_store_d16_hi_b8 v[0:1], v2, off offset:64 global_store_d16_hi_b8 v[3:4], v1, off // GFX12: encoding: [0x7c,0x00,0x09,0xee,0x00,0x00,0x80,0x00,0x03,0x00,0x00,0x00] +global_inv +// GFX12: encoding: [0x7c,0xc0,0x0a,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] + +global_inv scope:SCOPE_DEV +// GFX12: encoding: [0x7c,0xc0,0x0a,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00] + +global_inv scope:SCOPE_SYS +// GFX12: encoding: [0x7c,0xc0,0x0a,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00] + +global_wb +// GFX12: encoding: [0x7c,0x00,0x0b,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] + +global_wb scope:SCOPE_DEV +// GFX12: encoding: [0x7c,0x00,0x0b,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00] + +global_wb scope:SCOPE_SYS +// GFX12: encoding: [0x7c,0x00,0x0b,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00] + +global_wbinv +// GFX12: encoding: [0x7c,0xc0,0x13,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] + +global_wbinv scope:SCOPE_DEV +// GFX12: encoding: [0x7c,0xc0,0x13,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00] + +global_wbinv scope:SCOPE_SYS +// GFX12: encoding: [0x7c,0xc0,0x13,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00] + scratch_load_b128 v[1:4], off, off offset:-64 // GFX12: encoding: [0x7c,0xc0,0x05,0xed,0x01,0x00,0x00,0x00,0x00,0xc0,0xff,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt index f4038cf10f50..7365adb864fd 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt @@ -1137,6 +1137,33 @@ # GFX12: global_store_d16_hi_b8 v[3:4], v1, off ; encoding: [0x7c,0x00,0x09,0xee,0x00,0x00,0x80,0x00,0x03,0x00,0x00,0x00] 0x7c,0x00,0x09,0xee,0x00,0x00,0x80,0x00,0x03,0x00,0x00,0x00 +# GFX12: global_inv ; encoding: [0x7c,0xc0,0x0a,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] +0x7c,0xc0,0x0a,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_inv scope:SCOPE_DEV ; encoding: [0x7c,0xc0,0x0a,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00] +0x7c,0xc0,0x0a,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_inv scope:SCOPE_SYS ; encoding: [0x7c,0xc0,0x0a,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00] +0x7c,0xc0,0x0a,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_wb ; encoding: [0x7c,0x00,0x0b,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] +0x7c,0x00,0x0b,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_wb scope:SCOPE_DEV ; encoding: [0x7c,0x00,0x0b,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00] +0x7c,0x00,0x0b,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_wb scope:SCOPE_SYS ; encoding: [0x7c,0x00,0x0b,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00] +0x7c,0x00,0x0b,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_wbinv ; encoding: [0x7c,0xc0,0x13,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] +0x7c,0xc0,0x13,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_wbinv scope:SCOPE_DEV ; encoding: [0x7c,0xc0,0x13,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00] +0x7c,0xc0,0x13,0xee,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00 + +# GFX12: global_wbinv scope:SCOPE_SYS ; encoding: [0x7c,0xc0,0x13,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00] +0x7c,0xc0,0x13,0xee,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00 + # GFX12: scratch_load_b128 v[1:4], off, off offset:-64 ; encoding: [0x7c,0xc0,0x05,0xed,0x01,0x00,0x00,0x00,0x00,0xc0,0xff,0xff] 0x7c,0xc0,0x05,0xed,0x01,0x00,0x00,0x00,0x00,0xc0,0xff,0xff -- GitLab From 2bf01d73f6ebca11f36c17a65b7a86109d44681e Mon Sep 17 00:00:00 2001 From: Michael Buch Date: Mon, 8 Jan 2024 14:10:02 +0000 Subject: [PATCH 063/652] [lldb][DWARFASTParserClang] GetClangDeclForDIE: don't create VarDecl for static data members (#77155) With DWARFv5, C++ static data members are represented as `DW_TAG_variable`s (see `faa3a5ea9ae481da757dab1c95c589e2d5645982`). In GetClangDeclForDIE, when trying to parse the `DW_AT_specification` that a static data member's CU-level `DW_TAG_variable` points to, we would try to `CreateVariableDeclaration`. Whereas previously it was a no-op (for `DW_TAG_member`s). However, adding `VarDecls` to RecordDecls for static data members should always be done in `CreateStaticMemberVariable`. The test-case is an exapmle where we would crash if we tried to create a `VarDecl` from within `GetClangDeclForDIE` for a static data member. This patch simply checks whether the `DW_TAG_variable` being parsed is a static data member, and if so, trivially returns from `GetClangDeclForDIE` (as we previously did for `DW_TAG_member`s). --- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 21 +++++++++++++++- .../DWARF/Inputs/dwo-static-data-member.cpp | 8 +++++++ .../DWARF/dwo-static-data-member-access.test | 24 +++++++++++++++++++ 3 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 lldb/test/Shell/SymbolFile/DWARF/Inputs/dwo-static-data-member.cpp create mode 100644 lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp index 009722b85aa1..54d06b1115a2 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp @@ -142,6 +142,18 @@ static bool ShouldIgnoreArtificialField(llvm::StringRef FieldName) { || FieldName.starts_with("_vptr."); } +/// Returns true for C++ constructs represented by clang::CXXRecordDecl +static bool TagIsRecordType(dw_tag_t tag) { + switch (tag) { + case DW_TAG_class_type: + case DW_TAG_structure_type: + case DW_TAG_union_type: + return true; + default: + return false; + } +} + TypeSP DWARFASTParserClang::ParseTypeFromClangModule(const SymbolContext &sc, const DWARFDIE &die, Log *log) { @@ -3304,12 +3316,19 @@ clang::Decl *DWARFASTParserClang::GetClangDeclForDIE(const DWARFDIE &die) { return nullptr; switch (die.Tag()) { - case DW_TAG_variable: case DW_TAG_constant: case DW_TAG_formal_parameter: case DW_TAG_imported_declaration: case DW_TAG_imported_module: break; + case DW_TAG_variable: + // This means 'die' is a C++ static data member. + // We don't want to create decls for such members + // here. + if (auto parent = die.GetParent(); + parent.IsValid() && TagIsRecordType(parent.Tag())) + return nullptr; + break; default: return nullptr; } diff --git a/lldb/test/Shell/SymbolFile/DWARF/Inputs/dwo-static-data-member.cpp b/lldb/test/Shell/SymbolFile/DWARF/Inputs/dwo-static-data-member.cpp new file mode 100644 index 000000000000..fa7c3500df0f --- /dev/null +++ b/lldb/test/Shell/SymbolFile/DWARF/Inputs/dwo-static-data-member.cpp @@ -0,0 +1,8 @@ +struct NoCtor { + NoCtor(); + static int i; +}; + +int NoCtor::i = 15; + +int main() { return NoCtor::i; } diff --git a/lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test b/lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test new file mode 100644 index 000000000000..6e4deae7b9a0 --- /dev/null +++ b/lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test @@ -0,0 +1,24 @@ +# In DWARFv5, C++ static data members are represented +# as DW_TAG_variable. We make sure LLDB's expression +# evaluator doesn't crash when trying to parse such +# a DW_TAG_variable DIE, whose parent DIE is only +# a forward declaration. + +# RUN: %clangxx_host %S/Inputs/dwo-static-data-member.cpp \ +# RUN: -g -gdwarf-5 -gsplit-dwarf -flimit-debug-info -o %t +# RUN: %lldb %t -s %s -o exit 2>&1 | FileCheck %s + +breakpoint set -n main +process launch + +# CHECK: Process {{.*}} stopped + +# FIXME: The expression evaluator tries to attach +# the static member's VarDecl to the NoCtor RecordDecl +# before passing the AST to clang; this requires the +# RecordDecl to be a full definition. But the debug-info +# only contains forward declaration for NoCtor. So +# LLDB fails to evaluate the expression. +expression NoCtor::i +# CHECK-LABEL: expression NoCtor::i +# CHECK: use of undeclared identifier 'NoCtor' -- GitLab From b4ee7d6119f97931d9f38ac8c6bc7409eed87aab Mon Sep 17 00:00:00 2001 From: Felipe de Azevedo Piovezan Date: Mon, 8 Jan 2024 11:16:22 -0300 Subject: [PATCH 064/652] [lldb][DWARFIndex][nfc] Factor out fully qualified name query (#76977) This moves the functionally of finding a DIE based on a fully qualified name from SymbolFileDWARF into DWARFIndex itself, so that specializations of DWARFIndex can implement faster versions of this query. --- .../Plugins/SymbolFile/DWARF/DWARFIndex.cpp | 20 +++++++++++++++++++ .../Plugins/SymbolFile/DWARF/DWARFIndex.h | 14 +++++++++++++ .../SymbolFile/DWARF/SymbolFileDWARF.cpp | 9 ++------- 3 files changed, 36 insertions(+), 7 deletions(-) diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp index b1c323b101ce..20c07a94b507 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp @@ -7,6 +7,8 @@ //===----------------------------------------------------------------------===// #include "Plugins/SymbolFile/DWARF/DWARFIndex.h" +#include "DWARFDebugInfoEntry.h" +#include "DWARFDeclContext.h" #include "Plugins/Language/ObjC/ObjCLanguage.h" #include "Plugins/SymbolFile/DWARF/DWARFDIE.h" #include "Plugins/SymbolFile/DWARF/SymbolFileDWARF.h" @@ -112,3 +114,21 @@ void DWARFIndex::ReportInvalidDIERef(DIERef ref, llvm::StringRef name) const { "bad die {0:x16} for '{1}')\n", ref.die_offset(), name.str().c_str()); } + +void DWARFIndex::GetFullyQualifiedType( + const DWARFDeclContext &context, + llvm::function_ref callback) { + GetTypes(context, [&](DWARFDIE die) { + return GetFullyQualifiedTypeImpl(context, die, callback); + }); +} + +bool DWARFIndex::GetFullyQualifiedTypeImpl( + const DWARFDeclContext &context, DWARFDIE die, + llvm::function_ref callback) { + DWARFDeclContext dwarf_decl_ctx = + die.GetDIE()->GetDWARFDeclContext(die.GetCU()); + if (dwarf_decl_ctx == context) + return callback(die); + return true; +} diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h index 9aadeddbb217..0551b07100a9 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h @@ -53,6 +53,14 @@ public: llvm::function_ref callback) = 0; virtual void GetTypes(const DWARFDeclContext &context, llvm::function_ref callback) = 0; + + /// Finds all DIEs whose fully qualified name matches `context`. A base + /// implementation is provided, and it uses the entire CU to check the DIE + /// parent hierarchy. Specializations should override this if they are able + /// to provide a faster implementation. + virtual void + GetFullyQualifiedType(const DWARFDeclContext &context, + llvm::function_ref callback); virtual void GetNamespaces(ConstString name, llvm::function_ref callback) = 0; @@ -102,6 +110,12 @@ protected: } void ReportInvalidDIERef(DIERef ref, llvm::StringRef name) const; + + /// Implementation of `GetFullyQualifiedType` to check a single entry, + /// shareable with derived classes. + bool + GetFullyQualifiedTypeImpl(const DWARFDeclContext &context, DWARFDIE die, + llvm::function_ref callback); }; } // namespace dwarf } // namespace lldb_private::plugin diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index 447930ffe07b..737da7798b82 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -3138,7 +3138,7 @@ SymbolFileDWARF::FindDefinitionTypeForDWARFDeclContext(const DWARFDIE &die) { } const DWARFDeclContext die_dwarf_decl_ctx = GetDWARFDeclContext(die); - m_index->GetTypes(die_dwarf_decl_ctx, [&](DWARFDIE type_die) { + m_index->GetFullyQualifiedType(die_dwarf_decl_ctx, [&](DWARFDIE type_die) { // Make sure type_die's language matches the type system we are // looking for. We don't want to find a "Foo" type from Java if we // are looking for a "Foo" type for C, C++, ObjC, or ObjC++. @@ -3165,9 +3165,8 @@ SymbolFileDWARF::FindDefinitionTypeForDWARFDeclContext(const DWARFDIE &die) { return true; } - DWARFDeclContext type_dwarf_decl_ctx = GetDWARFDeclContext(type_die); - if (log) { + DWARFDeclContext type_dwarf_decl_ctx = GetDWARFDeclContext(type_die); GetObjectFile()->GetModule()->LogMessage( log, "SymbolFileDWARF::" @@ -3177,10 +3176,6 @@ SymbolFileDWARF::FindDefinitionTypeForDWARFDeclContext(const DWARFDIE &die) { type_dwarf_decl_ctx.GetQualifiedName()); } - // Make sure the decl contexts match all the way up - if (die_dwarf_decl_ctx != type_dwarf_decl_ctx) - return true; - Type *resolved_type = ResolveType(type_die, false); if (!resolved_type || resolved_type == DIE_IS_BEING_PARSED) return true; -- GitLab From ade7ae4760a0b0e74cddd8f852830ca946295930 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 8 Jan 2024 15:47:55 +0100 Subject: [PATCH 065/652] [InstSimplify] Add test for #77320 (NFC) --- llvm/test/Transforms/InstSimplify/select.ll | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll index 1b229f551093..899179e1ccbc 100644 --- a/llvm/test/Transforms/InstSimplify/select.ll +++ b/llvm/test/Transforms/InstSimplify/select.ll @@ -1733,3 +1733,17 @@ define i8 @select_or_disjoint_eq(i8 %x, i8 %y) { %sel = select i1 %cmp, i8 %x, i8 %or ret i8 %sel } + +; FIXME: This is a miscompile. +define <4 x i32> @select_vector_cmp_with_bitcasts(<2 x i64> %x, <4 x i32> %y) { +; CHECK-LABEL: @select_vector_cmp_with_bitcasts( +; CHECK-NEXT: ret <4 x i32> zeroinitializer +; + %x.bc = bitcast <2 x i64> %x to <4 x i32> + %y.bc = bitcast <4 x i32> %y to <2 x i64> + %sub = sub <2 x i64> %x, %y.bc + %sub.bc = bitcast <2 x i64> %sub to <4 x i32> + %cmp = icmp eq <4 x i32> %y, %x.bc + %sel = select <4 x i1> %cmp, <4 x i32> %sub.bc, <4 x i32> zeroinitializer + ret <4 x i32> %sel +} -- GitLab From 97e3220d6312ae00bcbe08673f218bd0f705776b Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 8 Jan 2024 15:49:47 +0100 Subject: [PATCH 066/652] [InstSimplify] Consider bitcast as potential cross-lane operation The bitcast might change the number of vector lanes, in which case it will be a cross-lane operation. Fixes https://github.com/llvm/llvm-project/issues/77320. --- llvm/lib/Analysis/InstructionSimplify.cpp | 2 +- llvm/test/Transforms/InstSimplify/select.ll | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 241bdd81b75a..d0c27cae0dff 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -4313,7 +4313,7 @@ static Value *simplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp, // For vector types, the simplification must hold per-lane, so forbid // potentially cross-lane operations like shufflevector. if (!I->getType()->isVectorTy() || isa(I) || - isa(I)) + isa(I) || isa(I)) return nullptr; } diff --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll index 899179e1ccbc..fe93a0c3f212 100644 --- a/llvm/test/Transforms/InstSimplify/select.ll +++ b/llvm/test/Transforms/InstSimplify/select.ll @@ -1734,10 +1734,15 @@ define i8 @select_or_disjoint_eq(i8 %x, i8 %y) { ret i8 %sel } -; FIXME: This is a miscompile. define <4 x i32> @select_vector_cmp_with_bitcasts(<2 x i64> %x, <4 x i32> %y) { ; CHECK-LABEL: @select_vector_cmp_with_bitcasts( -; CHECK-NEXT: ret <4 x i32> zeroinitializer +; CHECK-NEXT: [[X_BC:%.*]] = bitcast <2 x i64> [[X:%.*]] to <4 x i32> +; CHECK-NEXT: [[Y_BC:%.*]] = bitcast <4 x i32> [[Y:%.*]] to <2 x i64> +; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i64> [[X]], [[Y_BC]] +; CHECK-NEXT: [[SUB_BC:%.*]] = bitcast <2 x i64> [[SUB]] to <4 x i32> +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[Y]], [[X_BC]] +; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP]], <4 x i32> [[SUB_BC]], <4 x i32> zeroinitializer +; CHECK-NEXT: ret <4 x i32> [[SEL]] ; %x.bc = bitcast <2 x i64> %x to <4 x i32> %y.bc = bitcast <4 x i32> %y to <2 x i64> -- GitLab From 16cd344380aa89a4bc47939ae65fd59fe8c77181 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 8 Jan 2024 22:11:54 +0700 Subject: [PATCH 067/652] [RISCV] Fix collectNonISAExtFeature returning negative extension features (#76962) collectNonISAExtFeature was returning any negative extension features, e.g. given an input of +zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa It would return +save-restore,-zbb,-relax,-zfa Because negative extensions aren't emitted when calling toFeatureVector(), and so were considered missing. Hence why we still see "-zfa" and "-zfb" in the tests for the full arch string attributes, even though with a full arch string we should be overriding the extensions. This fixes it by using RISCVISAInfo::isSupportedExtensionFeature instead to check if a feature is an ISA extension. --- clang/lib/Basic/Targets/RISCV.cpp | 19 ++++++------------- .../CodeGen/RISCV/riscv-func-attr-target.c | 8 ++++---- 2 files changed, 10 insertions(+), 17 deletions(-) diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 6bc57a83a2d5..59ae12eed940 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -237,22 +237,15 @@ ArrayRef RISCVTargetInfo::getTargetBuiltins() const { static std::vector collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) { - auto ParseResult = - llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride); - - if (!ParseResult) { - consumeError(ParseResult.takeError()); - return std::vector(); - } - - std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector(); - std::vector NonISAExtFeatureVec; + auto IsNonISAExtFeature = [](const std::string &Feature) { + assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-')); + StringRef Ext = StringRef(Feature).drop_front(); // drop the +/- + return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext); + }; llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec), - [&](const std::string &Feat) { - return !llvm::is_contained(ImpliedFeatures, Feat); - }); + IsNonISAExtFeature); return NonISAExtFeatureVec; } diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c index 506acaba6874..759c33a22506 100644 --- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c +++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c @@ -40,8 +40,8 @@ __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {} // CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" } // CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" } // CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } -// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax,-zfa" } -// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" } +// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax" } +// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,-relax" } // CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" } -// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" } -// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax,-zbb,-zfa" } +// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,-relax" } +// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax" } -- GitLab From e6b7c8c4951a470cc63a1721bc5f5ac7f3748a2f Mon Sep 17 00:00:00 2001 From: erichkeane Date: Mon, 8 Jan 2024 07:12:27 -0800 Subject: [PATCH 068/652] [OpenACC] Implement 'if' clause The 'if' clause takes a required 'condition' expression. This patch implements that as an expression we will later ensure is convertible to a binary expression. --- clang/include/clang/Basic/OpenACCKinds.h | 3 + clang/lib/Parse/ParseOpenACC.cpp | 26 +++++++- clang/test/ParserOpenACC/parse-clauses.c | 84 ++++++++++++++++++++++++ 3 files changed, 110 insertions(+), 3 deletions(-) diff --git a/clang/include/clang/Basic/OpenACCKinds.h b/clang/include/clang/Basic/OpenACCKinds.h index 3eb0bf84208f..f6a628db29cf 100644 --- a/clang/include/clang/Basic/OpenACCKinds.h +++ b/clang/include/clang/Basic/OpenACCKinds.h @@ -93,6 +93,9 @@ enum class OpenACCClauseKind { /// 'default' clause, allowed on parallel, serial, kernel (and compound) /// constructs. Default, + /// 'if' clause, allowed on all the Compute Constructs, Data Constructs, + /// Executable Constructs, and Combined Constructs. + If, /// Represents an invalid clause, for the purposes of parsing. Invalid, }; diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 94c3d0c4e164..84e994ef0081 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -80,6 +80,10 @@ OpenACCClauseKind getOpenACCClauseKind(Token Tok) { if (Tok.is(tok::kw_default)) return OpenACCClauseKind::Default; + // if is also a keyword, make sure we parse it correctly. + if (Tok.is(tok::kw_if)) + return OpenACCClauseKind::If; + if (!Tok.is(tok::identifier)) return OpenACCClauseKind::Invalid; @@ -88,6 +92,7 @@ OpenACCClauseKind getOpenACCClauseKind(Token Tok) { .Case("auto", OpenACCClauseKind::Auto) .Case("default", OpenACCClauseKind::Default) .Case("finalize", OpenACCClauseKind::Finalize) + .Case("if", OpenACCClauseKind::If) .Case("if_present", OpenACCClauseKind::IfPresent) .Case("independent", OpenACCClauseKind::Independent) .Case("nohost", OpenACCClauseKind::NoHost) @@ -324,7 +329,7 @@ OpenACCDirectiveKind ParseOpenACCDirectiveKind(Parser &P) { } bool ClauseHasRequiredParens(OpenACCClauseKind Kind) { - return Kind == OpenACCClauseKind::Default; + return Kind == OpenACCClauseKind::Default || Kind == OpenACCClauseKind::If; } bool ParseOpenACCClauseParams(Parser &P, OpenACCClauseKind Kind) { @@ -356,6 +361,19 @@ bool ParseOpenACCClauseParams(Parser &P, OpenACCClauseKind Kind) { break; } + case OpenACCClauseKind::If: { + // FIXME: It isn't clear if the spec saying 'condition' means the same as + // it does in an if/while/etc (See ParseCXXCondition), however as it was + // written with Fortran/C in mind, we're going to assume it just means an + // 'expression evaluating to boolean'. + ExprResult CondExpr = + P.getActions().CorrectDelayedTyposInExpr(P.ParseExpression()); + // An invalid expression can be just about anything, so just give up on + // this clause list. + if (CondExpr.isInvalid()) + return true; + break; + } default: llvm_unreachable("Not a required parens type?"); } @@ -372,8 +390,10 @@ bool ParseOpenACCClauseParams(Parser &P, OpenACCClauseKind Kind) { // However, they all are named with a single-identifier (or auto/default!) // token, followed in some cases by either braces or parens. bool ParseOpenACCClause(Parser &P) { - if (!P.getCurToken().isOneOf(tok::identifier, tok::kw_auto, tok::kw_default)) - return P.Diag(P.getCurToken(), diag::err_expected) << tok::identifier; + // A number of clause names are actually keywords, so accept a keyword that + // can be converted to a name. + if (expectIdentifierOrKeyword(P)) + return true; OpenACCClauseKind Kind = getOpenACCClauseKind(P.getCurToken()); diff --git a/clang/test/ParserOpenACC/parse-clauses.c b/clang/test/ParserOpenACC/parse-clauses.c index aedf0c711ad1..b247210ff6c7 100644 --- a/clang/test/ParserOpenACC/parse-clauses.c +++ b/clang/test/ParserOpenACC/parse-clauses.c @@ -148,8 +148,92 @@ void DefaultClause() { // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc serial default(present), seq for(;;){} +} + +void IfClause() { + // expected-error@+2{{expected '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop if + for(;;){} + // expected-error@+2{{expected '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if seq + for(;;){} + + // expected-error@+2{{expected '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if, seq + for(;;){} + + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if( + for(;;){} + // expected-error@+2{{use of undeclared identifier 'seq'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if( seq + for(;;){} + + // expected-error@+3{{expected expression}} + // expected-error@+2{{use of undeclared identifier 'seq'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if(, seq + for(;;){} + + // expected-error@+3{{expected '('}} + // expected-error@+2{{expected identifier}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if) + for(;;){} + + // expected-error@+3{{expected '('}} + // expected-error@+2{{expected identifier}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if) seq + for(;;){} + + // expected-error@+3{{expected '('}} + // expected-error@+2{{expected identifier}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if), seq + for(;;){} + + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if() + for(;;){} + + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if() seq + for(;;){} + + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if(), seq + for(;;){} + + // expected-error@+2{{use of undeclared identifier 'invalid_expr'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if(invalid_expr) + for(;;){} + + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if() seq + for(;;){} + + int i, j; + + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if(i > j) + for(;;){} + + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial if(1+5>3), seq + for(;;){} } // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} -- GitLab From 0deb27c95722311c1ebedbbb8c8c4ac7735701fc Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Mon, 8 Jan 2024 16:43:38 +0100 Subject: [PATCH 069/652] Revert "[Flang][OpenMP] Disable declarate target tests on Windows" (#77324) Reverts llvm/llvm-project#77306 These tests aren't broken on Windows, marking them XFAIL will just ~ consistently fail the build. --- .../FIR/declare-target-implicit-func-and-subr-cap-enter.f90 | 2 -- .../OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 | 2 -- .../OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 | 2 -- .../Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 | 2 -- 4 files changed, 8 deletions(-) diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 index ff0f70444c60..8e88d1b0f52a 100644 --- a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 +++ b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 @@ -3,8 +3,6 @@ !RUN: bbc -emit-fir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE -!XFAIL: system-windows - ! CHECK-LABEL: func.func @_QPimplicitly_captured_twice ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured_twice() result(k) diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 index 0b3f2db8ca1f..a90b04246e6d 100644 --- a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 +++ b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 @@ -3,8 +3,6 @@ !RUN: bbc -emit-fir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE -!XFAIL: system-windows - ! CHECK-LABEL: func.func @_QPimplicitly_captured ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured(toggle) result(k) diff --git a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 index 4e0fa1fdc74c..ed718a485e3d 100644 --- a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 +++ b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 @@ -3,8 +3,6 @@ !RUN: bbc -emit-hlfir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE -!XFAIL: system-windows - ! CHECK-LABEL: func.func @_QPimplicitly_captured_twice ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured_twice() result(k) diff --git a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 index f7fd836e50e9..df81c43a2fe6 100644 --- a/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 +++ b/flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90 @@ -3,8 +3,6 @@ !RUN: bbc -emit-hlfir -fopenmp %s -o - | FileCheck %s !RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE -!XFAIL: system-windows - ! CHECK-LABEL: func.func @_QPimplicitly_captured ! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} function implicitly_captured(toggle) result(k) -- GitLab From 036e48e2f5f890e1f9574cdb610e2336f12038a2 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 8 Jan 2024 07:35:04 -0800 Subject: [PATCH 070/652] [SLP]Fix PR76850: do the analysis of the submask. Need to limit the transformation of the VecMask by the corresponding part of the mask of SliceSize size to avoid compiler crash during further cost analysis. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 16 +++++++----- .../SLPVectorizer/X86/splat-buildvector.ll | 25 +++++++++++++++++++ 2 files changed, 35 insertions(+), 6 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/splat-buildvector.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index cbe767537a1d..8e22b54f002d 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -10596,7 +10596,8 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { inversePermutation(E->ReorderIndices, ReorderMask); if (!ReorderMask.empty()) reorderScalars(GatheredScalars, ReorderMask); - auto FindReusedSplat = [&](MutableArrayRef Mask, unsigned InputVF) { + auto FindReusedSplat = [&](MutableArrayRef Mask, unsigned InputVF, + unsigned I, unsigned SliceSize) { if (!isSplat(E->Scalars) || none_of(E->Scalars, [](Value *V) { return isa(V) && !isa(V); })) @@ -10619,11 +10620,13 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { Idx == 0) || (Mask.size() == InputVF && ShuffleVectorInst::isIdentityMask(Mask, Mask.size()))) { - std::iota(Mask.begin(), Mask.end(), 0); + std::iota(std::next(Mask.begin(), I * SliceSize), + std::next(Mask.begin(), (I + 1) * SliceSize), 0); } else { - unsigned I = + unsigned IVal = *find_if_not(Mask, [](int Idx) { return Idx == PoisonMaskElem; }); - std::fill(Mask.begin(), Mask.end(), I); + std::fill(std::next(Mask.begin(), I * SliceSize), + std::next(Mask.begin(), (I + 1) * SliceSize), IVal); } return true; }; @@ -10872,7 +10875,8 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { } else if (Vec1) { IsUsedInExpr &= FindReusedSplat( ExtractMask, - cast(Vec1->getType())->getNumElements()); + cast(Vec1->getType())->getNumElements(), 0, + ExtractMask.size()); ShuffleBuilder.add(Vec1, ExtractMask, /*ForExtracts=*/true); IsNonPoisoned &= isGuaranteedNotToBePoison(Vec1); } else { @@ -10898,7 +10902,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { copy(SubMask, std::next(VecMask.begin(), I * SliceSize)); if (TEs.size() == 1) { IsUsedInExpr &= - FindReusedSplat(VecMask, TEs.front()->getVectorFactor()); + FindReusedSplat(VecMask, TEs.front()->getVectorFactor(), I, SliceSize); ShuffleBuilder.add(*TEs.front(), VecMask); if (TEs.front()->VectorizedValue) IsNonPoisoned &= diff --git a/llvm/test/Transforms/SLPVectorizer/X86/splat-buildvector.ll b/llvm/test/Transforms/SLPVectorizer/X86/splat-buildvector.ll new file mode 100644 index 000000000000..5e5981bdaaa8 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/splat-buildvector.ll @@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt --passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu %s -o - -slp-threshold=-100 | FileCheck %s +declare i64 @llvm.smax.i64(i64, i64) + +define i8 @foo(i64 %val_i64_57) { +; CHECK-LABEL: define i8 @foo( +; CHECK-SAME: i64 [[VAL_I64_57:%.*]]) { +; CHECK-NEXT: entry_1: +; CHECK-NEXT: [[VAL_I64_58:%.*]] = call i64 @llvm.smax.i64(i64 0, i64 1) +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> , i64 [[VAL_I64_57]], i32 1 +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[VAL_I64_58]], i32 2 +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> poison, <4 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule <4 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp sle <4 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i1> [[TMP3]], <4 x i1> [[TMP4]], <4 x i32> +; CHECK-NEXT: ret i8 0 +; +entry_1: + %val_i64_58 = call i64 @llvm.smax.i64(i64 0, i64 1) + %val_i1_89 = icmp ule i64 %val_i64_57, %val_i64_58 + %val_i1_95 = icmp sle i64 0, undef + %val_i1_98 = icmp uge i64 %val_i64_58, %val_i64_58 + %val_i1_99 = icmp ule i64 0, %val_i64_58 + ret i8 0 +} -- GitLab From 34dbaddc6fa1ce0892ecf3ca06866e7038b2a9b3 Mon Sep 17 00:00:00 2001 From: Michael Buch Date: Mon, 8 Jan 2024 15:57:53 +0000 Subject: [PATCH 071/652] [clang][ASTImporter] Only reorder fields of RecordDecls (#77079) Prior to `e9536698720ec524cc8b72599363622bc1a31558` (https://reviews.llvm.org/D154764) we only re-ordered the fields of `RecordDecl`s. The change refactored this logic to make sure `FieldDecl`s are imported before other member decls. However, this change also widened the types of `DeclContext`s we consider for re-ordering from `RecordDecl` to anything that's a `DeclContext`. This seems to have been just a drive-by cleanup. Internally we've seen numerous crashes in LLDB where we try to perform this re-ordering on fields of `ObjCInterfaceDecl`s. This patch restores old behaviour where we limit the re-ordering to just `RecordDecl`s. rdar://119343184 rdar://119636274 rdar://119832131 --- clang/lib/AST/ASTImporter.cpp | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 9ffae72346f2..5e5570bb42a1 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -2034,23 +2034,25 @@ ASTNodeImporter::ImportDeclContext(DeclContext *FromDC, bool ForceImport) { return ToDCOrErr.takeError(); } - DeclContext *ToDC = *ToDCOrErr; - // Remove all declarations, which may be in wrong order in the - // lexical DeclContext and then add them in the proper order. - for (auto *D : FromDC->decls()) { - if (!MightNeedReordering(D)) - continue; + if (const auto *FromRD = dyn_cast(FromDC)) { + DeclContext *ToDC = *ToDCOrErr; + // Remove all declarations, which may be in wrong order in the + // lexical DeclContext and then add them in the proper order. + for (auto *D : FromRD->decls()) { + if (!MightNeedReordering(D)) + continue; - assert(D && "DC contains a null decl"); - if (Decl *ToD = Importer.GetAlreadyImportedOrNull(D)) { - // Remove only the decls which we successfully imported. - assert(ToDC == ToD->getLexicalDeclContext() && ToDC->containsDecl(ToD)); - // Remove the decl from its wrong place in the linked list. - ToDC->removeDecl(ToD); - // Add the decl to the end of the linked list. - // This time it will be at the proper place because the enclosing for - // loop iterates in the original (good) order of the decls. - ToDC->addDeclInternal(ToD); + assert(D && "DC contains a null decl"); + if (Decl *ToD = Importer.GetAlreadyImportedOrNull(D)) { + // Remove only the decls which we successfully imported. + assert(ToDC == ToD->getLexicalDeclContext() && ToDC->containsDecl(ToD)); + // Remove the decl from its wrong place in the linked list. + ToDC->removeDecl(ToD); + // Add the decl to the end of the linked list. + // This time it will be at the proper place because the enclosing for + // loop iterates in the original (good) order of the decls. + ToDC->addDeclInternal(ToD); + } } } -- GitLab From 69066ab31959968ebcbca71f3872bdedef8fb8cd Mon Sep 17 00:00:00 2001 From: cor3ntin Date: Mon, 8 Jan 2024 16:58:48 +0100 Subject: [PATCH 072/652] [Clang] Fix IsOverload for function templates (#77323) Functions which correspond but have different template parameter lists are not redeclarations. Fixes a regression introduced by af4751 (The patch just moves the template parameters check above if the signature check) Fixes #76358 --- clang/lib/Sema/SemaOverload.cpp | 74 ++++++++++++------------- clang/test/CXX/over/over.load/p2-0x.cpp | 5 ++ 2 files changed, 42 insertions(+), 37 deletions(-) diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 07da5cb150b4..e6c267bb79e6 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -1259,6 +1259,43 @@ static bool IsOverloadOrOverrideImpl(Sema &SemaRef, FunctionDecl *New, if ((OldTemplate == nullptr) != (NewTemplate == nullptr)) return true; + if (NewTemplate) { + // C++ [temp.over.link]p4: + // The signature of a function template consists of its function + // signature, its return type and its template parameter list. The names + // of the template parameters are significant only for establishing the + // relationship between the template parameters and the rest of the + // signature. + // + // We check the return type and template parameter lists for function + // templates first; the remaining checks follow. + bool SameTemplateParameterList = SemaRef.TemplateParameterListsAreEqual( + NewTemplate, NewTemplate->getTemplateParameters(), OldTemplate, + OldTemplate->getTemplateParameters(), false, Sema::TPL_TemplateMatch); + bool SameReturnType = SemaRef.Context.hasSameType( + Old->getDeclaredReturnType(), New->getDeclaredReturnType()); + // FIXME(GH58571): Match template parameter list even for non-constrained + // template heads. This currently ensures that the code prior to C++20 is + // not newly broken. + bool ConstraintsInTemplateHead = + NewTemplate->getTemplateParameters()->hasAssociatedConstraints() || + OldTemplate->getTemplateParameters()->hasAssociatedConstraints(); + // C++ [namespace.udecl]p11: + // The set of declarations named by a using-declarator that inhabits a + // class C does not include member functions and member function + // templates of a base class that "correspond" to (and thus would + // conflict with) a declaration of a function or function template in + // C. + // Comparing return types is not required for the "correspond" check to + // decide whether a member introduced by a shadow declaration is hidden. + if (UseMemberUsingDeclRules && ConstraintsInTemplateHead && + !SameTemplateParameterList) + return true; + if (!UseMemberUsingDeclRules && + (!SameTemplateParameterList || !SameReturnType)) + return true; + } + // Is the function New an overload of the function Old? QualType OldQType = SemaRef.Context.getCanonicalType(Old->getType()); QualType NewQType = SemaRef.Context.getCanonicalType(New->getType()); @@ -1410,43 +1447,6 @@ static bool IsOverloadOrOverrideImpl(Sema &SemaRef, FunctionDecl *New, } } - if (NewTemplate) { - // C++ [temp.over.link]p4: - // The signature of a function template consists of its function - // signature, its return type and its template parameter list. The names - // of the template parameters are significant only for establishing the - // relationship between the template parameters and the rest of the - // signature. - // - // We check the return type and template parameter lists for function - // templates first; the remaining checks follow. - bool SameTemplateParameterList = SemaRef.TemplateParameterListsAreEqual( - NewTemplate, NewTemplate->getTemplateParameters(), OldTemplate, - OldTemplate->getTemplateParameters(), false, Sema::TPL_TemplateMatch); - bool SameReturnType = SemaRef.Context.hasSameType( - Old->getDeclaredReturnType(), New->getDeclaredReturnType()); - // FIXME(GH58571): Match template parameter list even for non-constrained - // template heads. This currently ensures that the code prior to C++20 is - // not newly broken. - bool ConstraintsInTemplateHead = - NewTemplate->getTemplateParameters()->hasAssociatedConstraints() || - OldTemplate->getTemplateParameters()->hasAssociatedConstraints(); - // C++ [namespace.udecl]p11: - // The set of declarations named by a using-declarator that inhabits a - // class C does not include member functions and member function - // templates of a base class that "correspond" to (and thus would - // conflict with) a declaration of a function or function template in - // C. - // Comparing return types is not required for the "correspond" check to - // decide whether a member introduced by a shadow declaration is hidden. - if (UseMemberUsingDeclRules && ConstraintsInTemplateHead && - !SameTemplateParameterList) - return true; - if (!UseMemberUsingDeclRules && - (!SameTemplateParameterList || !SameReturnType)) - return true; - } - if (!UseOverrideRules) { Expr *NewRC = New->getTrailingRequiresClause(), *OldRC = Old->getTrailingRequiresClause(); diff --git a/clang/test/CXX/over/over.load/p2-0x.cpp b/clang/test/CXX/over/over.load/p2-0x.cpp index 183f3cb322af..8fd9a1ce1e87 100644 --- a/clang/test/CXX/over/over.load/p2-0x.cpp +++ b/clang/test/CXX/over/over.load/p2-0x.cpp @@ -24,6 +24,11 @@ class Y { void k() &&; // expected-error{{cannot overload a member function with ref-qualifier '&&' with a member function without a ref-qualifier}} }; +struct GH76358 { + template void f() && {} + template void f() const {} +}; + #if __cplusplus >= 202002L namespace GH58962 { -- GitLab From bda562519b89ea3832be00d8ac75cfcdb924dce2 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 8 Jan 2024 10:02:44 -0600 Subject: [PATCH 073/652] [Libomptarget][NFC] Fix unhandled allocator enum value --- .../libomptarget/plugins-nextgen/common/src/PluginInterface.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp index be9ace571f54..9490e58fc669 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp @@ -1398,6 +1398,7 @@ Expected GenericDeviceTy::dataAlloc(int64_t Size, void *HostPtr, switch (Kind) { case TARGET_ALLOC_DEFAULT: + case TARGET_ALLOC_DEVICE_NON_BLOCKING: case TARGET_ALLOC_DEVICE: if (MemoryManager) { Alloc = MemoryManager->allocate(Size, HostPtr); -- GitLab From 01410103a6eb50436c39f71299773749b7de9dec Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Mon, 8 Jan 2024 17:24:42 +0100 Subject: [PATCH 074/652] [libc++][doc] Marks LWG3257 as complete (#77237) The macros were already updated - __cpp_lib_string_view in 466df1718e41fe2fca6ce6bd98c01b18f42c05e4 - __cpp_lib_array_constexpr in 77b9abfc8e89ca627e4f9a1cc206bea131db6db1 Based on the dates of the commit and that P0858 "Constexpr iterator requirements" was completed in LLVM 12, set this issue as completed in the same version. Completes - LWG3257 Missing feature testing macro update from P0858 --- libcxx/docs/Status/Cxx20Issues.csv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/docs/Status/Cxx20Issues.csv b/libcxx/docs/Status/Cxx20Issues.csv index e07db8d919dd..964c21df97e2 100644 --- a/libcxx/docs/Status/Cxx20Issues.csv +++ b/libcxx/docs/Status/Cxx20Issues.csv @@ -176,7 +176,7 @@ "`3245 `__","Unnecessary restriction on ``'%p'``\ parse specifier","Belfast","","","|chrono|" "`3244 `__","Constraints for ``Source``\ in |sect|\ [fs.path.req] insufficiently constrainty","Belfast","","" "`3241 `__","``chrono-spec``\ grammar ambiguity in |sect|\ [time.format]","Belfast","|Complete|","16.0","|chrono| |format|" -"`3257 `__","Missing feature testing macro update from P0858","Belfast","","" +"`3257 `__","Missing feature testing macro update from P0858","Belfast","|Complete|","12.0" "`3256 `__","Feature testing macro for ``constexpr``\ algorithms","Belfast","|Complete|","13.0" "`3273 `__","Specify ``weekday_indexed``\ to range of ``[0, 7]``\ ","Belfast","|Complete|","16.0","|chrono|" "`3070 `__","``path::lexically_relative``\ causes surprising results if a filename can also be a *root-name*","Belfast","","" -- GitLab From 053aed2024a1014736ffe35b001710b263c7a4b5 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Mon, 8 Jan 2024 08:30:26 -0800 Subject: [PATCH 075/652] [X86] Check if machine loop is passed while getting loop alignment (#77283) After d6bb96e677759375b2bea00115918b2cb6552f5b, calling getPrefLoopAlignment without passing in a pointer to a MachineLoop causes a segmentation fault. This conflicts with the API in TargetLoweringBase where the default MachineLoop pointer passed is nullptr. This patch fixes this by checking if the pointer points to something before enabling the optional functionality. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8c4f091c793d..c14e03197aae 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -57672,7 +57672,7 @@ X86TargetLowering::getStackProbeSize(const MachineFunction &MF) const { } Align X86TargetLowering::getPrefLoopAlignment(MachineLoop *ML) const { - if (ML->isInnermost() && + if (ML && ML->isInnermost() && ExperimentalPrefInnermostLoopAlignment.getNumOccurrences()) return Align(1ULL << ExperimentalPrefInnermostLoopAlignment); return TargetLowering::getPrefLoopAlignment(); -- GitLab From ff47989ec238dafe4a68c6a716e8dbccc9f559f5 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Mon, 8 Jan 2024 08:35:59 -0800 Subject: [PATCH 076/652] [AArch64][GlobalISel] Allow anyexting loads from 32b -> 64b to be legal. We can already support selection of these through imported patterns, we were just missing the legalizer rule to allow these to be formed. Nano size benefit overall. --- .../AArch64/GISel/AArch64LegalizerInfo.cpp | 3 ++- .../GlobalISel/combine-ext-debugloc.mir | 2 +- .../postlegalizercombiner-extending-loads.mir | 25 ++++++++++--------- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 470742cdc30e..b657a0954d78 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -366,7 +366,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {v4s32, p0, s128, 8}, {v2s64, p0, s128, 8}}) // These extends are also legal - .legalForTypesWithMemDesc({{s32, p0, s8, 8}, {s32, p0, s16, 8}}) + .legalForTypesWithMemDesc( + {{s32, p0, s8, 8}, {s32, p0, s16, 8}, {s64, p0, s32, 8}}) .widenScalarToNextPow2(0, /* MinSize = */ 8) .lowerIfMemSizeNotByteSizePow2() .clampScalar(0, s8, s64) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir index 860df510b211..4c0e191f7196 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir @@ -2,7 +2,7 @@ # Check that when we combine ZEXT/ANYEXT we assign the correct location. # CHECK: !8 = !DILocation(line: 23, column: 5, scope: !4) -# CHECK: G_AND %15, %16, debug-location !8 +# CHECK: G_AND %14, %15, debug-location !8 --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir index db576419a764..7b3547159f18 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir @@ -8,7 +8,7 @@ entry: ret void } - define void @test_no_anyext(i8* %addr) { + define void @test_s32_to_s64(i8* %addr) { entry: ret void } @@ -21,9 +21,11 @@ body: | bb.0.entry: liveins: $x0 ; CHECK-LABEL: name: test_zeroext - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.addr) - ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32) + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.addr) + ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32) %0:_(p0) = COPY $x0 %1:_(s8) = G_LOAD %0 :: (load (s8) from %ir.addr) %2:_(s32) = G_ZEXT %1 @@ -31,18 +33,17 @@ body: | ... --- -name: test_no_anyext +name: test_s32_to_s64 legalized: true body: | bb.0.entry: liveins: $x0 - ; Check that we don't try to do an anyext combine. We don't want to do this - ; because an anyexting load like s64 = G_LOAD %p (load 4) isn't legal. - ; CHECK-LABEL: name: test_no_anyext - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.addr) - ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) - ; CHECK: $x0 = COPY [[ANYEXT]](s64) + ; CHECK-LABEL: name: test_s32_to_s64 + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.addr) + ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64) %0:_(p0) = COPY $x0 %1:_(s32) = G_LOAD %0 :: (load (s32) from %ir.addr) %2:_(s64) = G_ANYEXT %1 -- GitLab From 12101ca8e322c4cbf40e44b5b1fbf7ea76aff581 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 08:51:44 -0800 Subject: [PATCH 077/652] [libc] set -Wno-frame-address for thread.cpp (#77140) The aarch64 code is using __builtin_return_address with a non-zero parameter, which generates the following warning: llvm-project/libc/src/__support/threads/linux/thread.cpp:171:38: error: calling '__builtin_frame_address' with a nonzero argument is unsafe [-Werror,-Wframe-address] 171 | return reinterpret_cast(__builtin_frame_address(1)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~ Disable this diagnostic just for this file so that we can enable -Werror. Fixes: #77007 --- libc/src/__support/threads/linux/CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libc/src/__support/threads/linux/CMakeLists.txt b/libc/src/__support/threads/linux/CMakeLists.txt index 642eead72772..148a0ba061c5 100644 --- a/libc/src/__support/threads/linux/CMakeLists.txt +++ b/libc/src/__support/threads/linux/CMakeLists.txt @@ -39,6 +39,8 @@ add_object_library( -O3 -fno-omit-frame-pointer # This allows us to sniff out the thread args from # the new thread's stack reliably. + -Wno-frame-address # Yes, calling __builtin_return_address with a + # value other than 0 is dangerous. We know. ) add_object_library( -- GitLab From 0e7199cf3d08c83d18549c9cd083e9fec6e9db54 Mon Sep 17 00:00:00 2001 From: arpilipe Date: Mon, 8 Jan 2024 08:54:53 -0800 Subject: [PATCH 078/652] Replace print-at-pass-number cl::opt with print-before-pass-number (#76211) The existing option prints the IR after the pass, but it's not clear from its name. In this patch I change the option to print the IR before the pass and change the name to make the behavior clear. Printing the IR before the pass is slightly simpler than after as I don't need to worry about printAfterPassInvalidated case. Either before or after the pass would be ok for the original use case this option was introduced for. --- .../llvm/Passes/StandardInstrumentations.h | 2 +- llvm/lib/Passes/StandardInstrumentations.cpp | 52 ++++++++----------- llvm/test/Other/print-at-pass-number.ll | 10 ++-- 3 files changed, 26 insertions(+), 38 deletions(-) diff --git a/llvm/include/llvm/Passes/StandardInstrumentations.h b/llvm/include/llvm/Passes/StandardInstrumentations.h index 2ec36cad244f..8c6a44876d54 100644 --- a/llvm/include/llvm/Passes/StandardInstrumentations.h +++ b/llvm/include/llvm/Passes/StandardInstrumentations.h @@ -65,7 +65,7 @@ private: bool shouldPrintBeforePass(StringRef PassID); bool shouldPrintAfterPass(StringRef PassID); bool shouldPrintPassNumbers(); - bool shouldPrintAtPassNumber(); + bool shouldPrintBeforePassNumber(); void pushPassRunDescriptor(StringRef PassID, Any IR, std::string &DumpIRFilename); diff --git a/llvm/lib/Passes/StandardInstrumentations.cpp b/llvm/lib/Passes/StandardInstrumentations.cpp index fd1317e3eb25..d467fe5c9a8e 100644 --- a/llvm/lib/Passes/StandardInstrumentations.cpp +++ b/llvm/lib/Passes/StandardInstrumentations.cpp @@ -118,10 +118,10 @@ static cl::opt PrintPassNumbers( "print-pass-numbers", cl::init(false), cl::Hidden, cl::desc("Print pass names and their ordinals")); -static cl::opt - PrintAtPassNumber("print-at-pass-number", cl::init(0), cl::Hidden, - cl::desc("Print IR at pass with this number as " - "reported by print-passes-names")); +static cl::opt PrintBeforePassNumber( + "print-before-pass-number", cl::init(0), cl::Hidden, + cl::desc("Print IR before the pass with this number as " + "reported by print-pass-numbers")); static cl::opt IRDumpDirectory( "ir-dump-directory", @@ -806,8 +806,7 @@ void PrintIRInstrumentation::printBeforePass(StringRef PassID, Any IR) { // Note: here we rely on a fact that we do not change modules while // traversing the pipeline, so the latest captured module is good // for all print operations that has not happen yet. - if (shouldPrintPassNumbers() || shouldPrintAtPassNumber() || - shouldPrintAfterPass(PassID)) + if (shouldPrintAfterPass(PassID)) pushPassRunDescriptor(PassID, IR, DumpIRFilename); if (!shouldPrintIR(IR)) @@ -823,8 +822,10 @@ void PrintIRInstrumentation::printBeforePass(StringRef PassID, Any IR) { return; auto WriteIRToStream = [&](raw_ostream &Stream) { - Stream << "; *** IR Dump Before " << PassID << " on " << getIRName(IR) - << " ***\n"; + Stream << "; *** IR Dump Before "; + if (shouldPrintBeforePassNumber()) + Stream << CurrentPassNumber << "-"; + Stream << PassID << " on " << getIRName(IR) << " ***\n"; unwrapAndPrint(Stream, IR); }; @@ -842,8 +843,7 @@ void PrintIRInstrumentation::printAfterPass(StringRef PassID, Any IR) { if (isIgnored(PassID)) return; - if (!shouldPrintAfterPass(PassID) && !shouldPrintPassNumbers() && - !shouldPrintAtPassNumber()) + if (!shouldPrintAfterPass(PassID)) return; auto [M, DumpIRFilename, IRName, StoredPassID] = popPassRunDescriptor(PassID); @@ -853,10 +853,7 @@ void PrintIRInstrumentation::printAfterPass(StringRef PassID, Any IR) { return; auto WriteIRToStream = [&](raw_ostream &Stream, const StringRef IRName) { - Stream << "; *** IR Dump " - << (shouldPrintAtPassNumber() - ? StringRef(formatv("At {0}-{1}", CurrentPassNumber, PassID)) - : StringRef(formatv("After {0}", PassID))) + Stream << "; *** IR Dump " << StringRef(formatv("After {0}", PassID)) << " on " << IRName << " ***\n"; unwrapAndPrint(Stream, IR); }; @@ -879,8 +876,7 @@ void PrintIRInstrumentation::printAfterPassInvalidated(StringRef PassID) { if (isIgnored(PassID)) return; - if (!shouldPrintAfterPass(PassID) && !shouldPrintPassNumbers() && - !shouldPrintAtPassNumber()) + if (!shouldPrintAfterPass(PassID)) return; auto [M, DumpIRFilename, IRName, StoredPassID] = popPassRunDescriptor(PassID); @@ -893,12 +889,8 @@ void PrintIRInstrumentation::printAfterPassInvalidated(StringRef PassID) { auto WriteIRToStream = [&](raw_ostream &Stream, const Module *M, const StringRef IRName) { SmallString<20> Banner; - if (shouldPrintAtPassNumber()) - Banner = formatv("; *** IR Dump At {0}-{1} on {2} (invalidated) ***", - CurrentPassNumber, PassID, IRName); - else - Banner = formatv("; *** IR Dump After {0} on {1} (invalidated) ***", - PassID, IRName); + Banner = formatv("; *** IR Dump After {0} on {1} (invalidated) ***", PassID, + IRName); Stream << Banner << "\n"; printIR(Stream, M); }; @@ -921,6 +913,10 @@ bool PrintIRInstrumentation::shouldPrintBeforePass(StringRef PassID) { if (shouldPrintBeforeAll()) return true; + if (shouldPrintBeforePassNumber() && + CurrentPassNumber == PrintBeforePassNumber) + return true; + StringRef PassName = PIC->getPassNameForClassName(PassID); return is_contained(printBeforePasses(), PassName); } @@ -929,9 +925,6 @@ bool PrintIRInstrumentation::shouldPrintAfterPass(StringRef PassID) { if (shouldPrintAfterAll()) return true; - if (shouldPrintAtPassNumber() && CurrentPassNumber == PrintAtPassNumber) - return true; - StringRef PassName = PIC->getPassNameForClassName(PassID); return is_contained(printAfterPasses(), PassName); } @@ -940,8 +933,8 @@ bool PrintIRInstrumentation::shouldPrintPassNumbers() { return PrintPassNumbers; } -bool PrintIRInstrumentation::shouldPrintAtPassNumber() { - return PrintAtPassNumber > 0; +bool PrintIRInstrumentation::shouldPrintBeforePassNumber() { + return PrintBeforePassNumber > 0; } void PrintIRInstrumentation::registerCallbacks( @@ -950,13 +943,12 @@ void PrintIRInstrumentation::registerCallbacks( // BeforePass callback is not just for printing, it also saves a Module // for later use in AfterPassInvalidated. - if (shouldPrintPassNumbers() || shouldPrintAtPassNumber() || + if (shouldPrintPassNumbers() || shouldPrintBeforePassNumber() || shouldPrintBeforeSomePass() || shouldPrintAfterSomePass()) PIC.registerBeforeNonSkippedPassCallback( [this](StringRef P, Any IR) { this->printBeforePass(P, IR); }); - if (shouldPrintPassNumbers() || shouldPrintAtPassNumber() || - shouldPrintAfterSomePass()) { + if (shouldPrintAfterSomePass()) { PIC.registerAfterPassCallback( [this](StringRef P, Any IR, const PreservedAnalyses &) { this->printAfterPass(P, IR); diff --git a/llvm/test/Other/print-at-pass-number.ll b/llvm/test/Other/print-at-pass-number.ll index 8b2d3144e092..b9c09a36ca1f 100644 --- a/llvm/test/Other/print-at-pass-number.ll +++ b/llvm/test/Other/print-at-pass-number.ll @@ -1,13 +1,9 @@ ; RUN: opt -passes="loop(indvars,loop-deletion,loop-unroll-full)" -print-pass-numbers -S -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=NUMBER -; RUN: opt -passes="loop(indvars,loop-deletion,loop-unroll-full)" -print-module-scope -print-at-pass-number=3 -S -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=AT -; RUN: opt -passes="loop(indvars,loop-deletion,loop-unroll-full)" -print-module-scope -print-at-pass-number=4 -S -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=AT-INVALIDATE +; RUN: opt -passes="loop(indvars,loop-deletion,loop-unroll-full)" -print-module-scope -print-before-pass-number=3 -S -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=BEFORE define i32 @bar(i32 %arg) { -; AT: *** IR Dump At 3-IndVarSimplifyPass on bb1 *** -; AT: define i32 @bar(i32 %arg) { - -; AT-INVALIDATE: *** IR Dump At 4-LoopDeletionPass on bb1 (invalidated) *** -; AT-INVALIDATE: define i32 @bar(i32 %arg) { +; BEFORE: *** IR Dump Before 3-IndVarSimplifyPass on bb1 *** +; BEFORE: define i32 @bar(i32 %arg) { bb: br label %bb1 -- GitLab From c68a9d25e99a096f6862fc4b57dd380a21245d31 Mon Sep 17 00:00:00 2001 From: Tacet Date: Mon, 8 Jan 2024 18:02:17 +0100 Subject: [PATCH 079/652] [ASan][libc++] String annotations optimizations fix with lambda (#76200) This commit addresses optimization and instrumentation challenges encountered within comma constructors. 1) _LIBCPP_STRING_INTERNAL_MEMORY_ACCESS does not work in comma constructors. 2) Code inside comma constructors is not always correctly optimized. Problematic code examples: - `: __r_(((__str.__is_long() ? 0 : (__str.__annotate_delete(), 0)), std::move(__str.__r_))) {` - `: __r_(__r_([&](){ if(!__s.__is_long()) __s.__annotate_delete(); return std::move(__s.__r_);}())) {` However, lambda with argument seems to be correctly optimized. The patch employs this. Use of lambda based on an idea from @ldionne. --- libcxx/include/string | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/include/string b/libcxx/include/string index c676182fba8b..e2be53eaee24 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -922,7 +922,7 @@ public: // Turning off ASan instrumentation for variable initialization with _LIBCPP_STRING_INTERNAL_MEMORY_ACCESS // does not work consistently during initialization of __r_, so we instead unpoison __str's memory manually first. // __str's memory needs to be unpoisoned only in the case where it's a short string. - : __r_(((__str.__is_long() ? 0 : (__str.__annotate_delete(), 0)), std::move(__str.__r_))) { + : __r_([](basic_string &__s){ if(!__s.__is_long()) __s.__annotate_delete(); return std::move(__s.__r_); }(__str)) { __str.__r_.first() = __rep(); __str.__annotate_new(0); if (!__is_long()) -- GitLab From c52b467875e26d5d3554514489d965eda3ab0cd2 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 09:07:35 -0800 Subject: [PATCH 080/652] Reapply "[libc] build with -Werror (#73966)" (#74506) This reverts commit 6886a52d6dbefff77f33de12ff85d654e2557f81. Most of the errors observed in postsubmit have been addressed. We can fix-forward the remaining ones. Link: https://lab.llvm.org/buildbot/#/changes/117129 --- libc/cmake/modules/LLVMLibCObjectRules.cmake | 4 ++++ libc/docs/dev/code_style.rst | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/libc/cmake/modules/LLVMLibCObjectRules.cmake b/libc/cmake/modules/LLVMLibCObjectRules.cmake index c3e3fa2dccfe..6eba17ae9201 100644 --- a/libc/cmake/modules/LLVMLibCObjectRules.cmake +++ b/libc/cmake/modules/LLVMLibCObjectRules.cmake @@ -43,6 +43,10 @@ function(_get_common_compile_options output_var flags) list(APPEND compile_options "-fno-rtti") list(APPEND compile_options "-Wall") list(APPEND compile_options "-Wextra") + # -DLIBC_WNO_ERROR=ON if you can't build cleanly with -Werror. + if(NOT LIBC_WNO_ERROR) + list(APPEND compile_options "-Werror") + endif() list(APPEND compile_options "-Wconversion") list(APPEND compile_options "-Wno-sign-conversion") list(APPEND compile_options "-Wimplicit-fallthrough") diff --git a/libc/docs/dev/code_style.rst b/libc/docs/dev/code_style.rst index a050a4c1d3dd..eeeced0359ad 100644 --- a/libc/docs/dev/code_style.rst +++ b/libc/docs/dev/code_style.rst @@ -178,3 +178,11 @@ these functions do not call the constructors and destructors of the allocated/deallocated objects. So, use these functions carefully and only when it is absolutely clear that constructor and destructor invocation is not required. + +Warnings in sources +=================== + +We expect contributions to be free of warnings from the `minimum supported +compiler versions`__ (and newer). + +.. __: https://libc.llvm.org/compiler_support.html#minimum-supported-versions -- GitLab From f3f66773117259185b76574de9385e25e3902658 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:40:06 +0000 Subject: [PATCH 081/652] [X86] combine-bextr.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. Add nounwind to remove cfi noise as well. --- llvm/test/CodeGen/X86/combine-bextr.ll | 48 ++++++++++++-------------- 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/llvm/test/CodeGen/X86/combine-bextr.ll b/llvm/test/CodeGen/X86/combine-bextr.ll index c36723732b5c..6eea67cb43ec 100644 --- a/llvm/test/CodeGen/X86/combine-bextr.ll +++ b/llvm/test/CodeGen/X86/combine-bextr.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2,+bmi | FileCheck %s --check-prefixes=CHECK,X32 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2,+bmi | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2,+bmi | FileCheck %s --check-prefixes=CHECK,X64 declare i32 @llvm.x86.bmi.bextr.32(i32, i32) -define i32 @bextr_zero_length(i32 %x, i32 %y) { +define i32 @bextr_zero_length(i32 %x, i32 %y) nounwind { ; CHECK-LABEL: bextr_zero_length: ; CHECK: # %bb.0: ; CHECK-NEXT: xorl %eax, %eax @@ -14,13 +14,13 @@ define i32 @bextr_zero_length(i32 %x, i32 %y) { ret i32 %2 } -define i32 @bextr_big_shift(i32 %x, i32 %y) { -; X32-LABEL: bextr_big_shift: -; X32: # %bb.0: -; X32-NEXT: movl $255, %eax -; X32-NEXT: orl {{[0-9]+}}(%esp), %eax -; X32-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax -; X32-NEXT: retl +define i32 @bextr_big_shift(i32 %x, i32 %y) nounwind { +; X86-LABEL: bextr_big_shift: +; X86: # %bb.0: +; X86-NEXT: movl $255, %eax +; X86-NEXT: orl {{[0-9]+}}(%esp), %eax +; X86-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax +; X86-NEXT: retl ; ; X64-LABEL: bextr_big_shift: ; X64: # %bb.0: @@ -32,22 +32,20 @@ define i32 @bextr_big_shift(i32 %x, i32 %y) { ret i32 %2 } -define float @bextr_uitofp(i32 %x, i32 %y) { -; X32-LABEL: bextr_uitofp: -; X32: # %bb.0: -; X32-NEXT: pushl %eax -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: movl $3855, %eax # imm = 0xF0F -; X32-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax -; X32-NEXT: movd %eax, %xmm0 -; X32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: cvtsd2ss %xmm0, %xmm0 -; X32-NEXT: movss %xmm0, (%esp) -; X32-NEXT: flds (%esp) -; X32-NEXT: popl %eax -; X32-NEXT: .cfi_def_cfa_offset 4 -; X32-NEXT: retl +define float @bextr_uitofp(i32 %x, i32 %y) nounwind { +; X86-LABEL: bextr_uitofp: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: movl $3855, %eax # imm = 0xF0F +; X86-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movd %eax, %xmm0 +; X86-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: cvtsd2ss %xmm0, %xmm0 +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl ; ; X64-LABEL: bextr_uitofp: ; X64: # %bb.0: -- GitLab From 61dcfaa745e22b0e5330fc82ee4b7de4b6c99ab7 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:41:51 +0000 Subject: [PATCH 082/652] [X86] i64-mem-copy.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. Add nounwind to remove cfi noise as well. --- llvm/test/CodeGen/X86/i64-mem-copy.ll | 186 +++++++++++++------------- 1 file changed, 91 insertions(+), 95 deletions(-) diff --git a/llvm/test/CodeGen/X86/i64-mem-copy.ll b/llvm/test/CodeGen/X86/i64-mem-copy.ll index 500c6c787694..4cdb079d4399 100644 --- a/llvm/test/CodeGen/X86/i64-mem-copy.ll +++ b/llvm/test/CodeGen/X86/i64-mem-copy.ll @@ -1,33 +1,33 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X64 -; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X32 -; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X32AVX +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X86AVX ; Use movq or movsd to load / store i64 values if sse2 is available. ; rdar://6659858 -define void @foo(ptr %x, ptr %y) { +define void @foo(ptr %x, ptr %y) nounwind { ; X64-LABEL: foo: ; X64: # %bb.0: ; X64-NEXT: movq (%rsi), %rax ; X64-NEXT: movq %rax, (%rdi) ; X64-NEXT: retq ; -; X32-LABEL: foo: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: movsd %xmm0, (%eax) -; X32-NEXT: retl +; X86-LABEL: foo: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: movsd %xmm0, (%eax) +; X86-NEXT: retl ; -; X32AVX-LABEL: foo: -; X32AVX: # %bb.0: -; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32AVX-NEXT: vmovsd %xmm0, (%eax) -; X32AVX-NEXT: retl +; X86AVX-LABEL: foo: +; X86AVX: # %bb.0: +; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86AVX-NEXT: vmovsd %xmm0, (%eax) +; X86AVX-NEXT: retl %tmp1 = load i64, ptr %y, align 8 store i64 %tmp1, ptr %x, align 8 ret void @@ -36,26 +36,26 @@ define void @foo(ptr %x, ptr %y) { ; Verify that a 64-bit chunk extracted from a vector is stored with a movq ; regardless of whether the system is 64-bit. -define void @store_i64_from_vector(<8 x i16> %x, <8 x i16> %y, ptr %i) { +define void @store_i64_from_vector(<8 x i16> %x, <8 x i16> %y, ptr %i) nounwind { ; X64-LABEL: store_i64_from_vector: ; X64: # %bb.0: ; X64-NEXT: paddw %xmm1, %xmm0 ; X64-NEXT: movq %xmm0, (%rdi) ; X64-NEXT: retq ; -; X32-LABEL: store_i64_from_vector: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: paddw %xmm1, %xmm0 -; X32-NEXT: movq %xmm0, (%eax) -; X32-NEXT: retl +; X86-LABEL: store_i64_from_vector: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: paddw %xmm1, %xmm0 +; X86-NEXT: movq %xmm0, (%eax) +; X86-NEXT: retl ; -; X32AVX-LABEL: store_i64_from_vector: -; X32AVX: # %bb.0: -; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 -; X32AVX-NEXT: vmovq %xmm0, (%eax) -; X32AVX-NEXT: retl +; X86AVX-LABEL: store_i64_from_vector: +; X86AVX: # %bb.0: +; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; X86AVX-NEXT: vmovq %xmm0, (%eax) +; X86AVX-NEXT: retl %z = add <8 x i16> %x, %y ; force execution domain %bc = bitcast <8 x i16> %z to <2 x i64> %vecext = extractelement <2 x i64> %bc, i32 0 @@ -63,39 +63,35 @@ define void @store_i64_from_vector(<8 x i16> %x, <8 x i16> %y, ptr %i) { ret void } -define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, ptr %i) { +define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, ptr %i) nounwind { ; X64-LABEL: store_i64_from_vector256: ; X64: # %bb.0: ; X64-NEXT: paddw %xmm3, %xmm1 ; X64-NEXT: movq %xmm1, (%rdi) ; X64-NEXT: retq ; -; X32-LABEL: store_i64_from_vector256: -; X32: # %bb.0: -; X32-NEXT: pushl %ebp -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: .cfi_offset %ebp, -8 -; X32-NEXT: movl %esp, %ebp -; X32-NEXT: .cfi_def_cfa_register %ebp -; X32-NEXT: andl $-16, %esp -; X32-NEXT: subl $16, %esp -; X32-NEXT: movl 24(%ebp), %eax -; X32-NEXT: paddw 8(%ebp), %xmm1 -; X32-NEXT: movq %xmm1, (%eax) -; X32-NEXT: movl %ebp, %esp -; X32-NEXT: popl %ebp -; X32-NEXT: .cfi_def_cfa %esp, 4 -; X32-NEXT: retl +; X86-LABEL: store_i64_from_vector256: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-16, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 24(%ebp), %eax +; X86-NEXT: paddw 8(%ebp), %xmm1 +; X86-NEXT: movq %xmm1, (%eax) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl ; -; X32AVX-LABEL: store_i64_from_vector256: -; X32AVX: # %bb.0: -; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32AVX-NEXT: vextracti128 $1, %ymm1, %xmm1 -; X32AVX-NEXT: vextracti128 $1, %ymm0, %xmm0 -; X32AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 -; X32AVX-NEXT: vmovq %xmm0, (%eax) -; X32AVX-NEXT: vzeroupper -; X32AVX-NEXT: retl +; X86AVX-LABEL: store_i64_from_vector256: +; X86AVX: # %bb.0: +; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86AVX-NEXT: vextracti128 $1, %ymm1, %xmm1 +; X86AVX-NEXT: vextracti128 $1, %ymm0, %xmm0 +; X86AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; X86AVX-NEXT: vmovq %xmm0, (%eax) +; X86AVX-NEXT: vzeroupper +; X86AVX-NEXT: retl %z = add <16 x i16> %x, %y ; force execution domain %bc = bitcast <16 x i16> %z to <4 x i64> %vecext = extractelement <4 x i64> %bc, i32 2 @@ -125,46 +121,46 @@ define void @PR23476(<5 x i64> %in, ptr %out, i32 %index) nounwind { ; X64-NEXT: movq %rax, (%r9) ; X64-NEXT: retq ; -; X32-LABEL: PR23476: -; X32: # %bb.0: -; X32-NEXT: pushl %ebp -; X32-NEXT: movl %esp, %ebp -; X32-NEXT: andl $-16, %esp -; X32-NEXT: subl $80, %esp -; X32-NEXT: movl 52(%ebp), %eax -; X32-NEXT: andl $7, %eax -; X32-NEXT: movl 48(%ebp), %ecx -; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: movups 8(%ebp), %xmm1 -; X32-NEXT: movups 24(%ebp), %xmm2 -; X32-NEXT: movaps %xmm2, {{[0-9]+}}(%esp) -; X32-NEXT: movaps %xmm1, (%esp) -; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) -; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: movsd %xmm0, (%ecx) -; X32-NEXT: movl %ebp, %esp -; X32-NEXT: popl %ebp -; X32-NEXT: retl +; X86-LABEL: PR23476: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-16, %esp +; X86-NEXT: subl $80, %esp +; X86-NEXT: movl 52(%ebp), %eax +; X86-NEXT: andl $7, %eax +; X86-NEXT: movl 48(%ebp), %ecx +; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: movups 8(%ebp), %xmm1 +; X86-NEXT: movups 24(%ebp), %xmm2 +; X86-NEXT: movaps %xmm2, {{[0-9]+}}(%esp) +; X86-NEXT: movaps %xmm1, (%esp) +; X86-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) +; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: movsd %xmm0, (%ecx) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl ; -; X32AVX-LABEL: PR23476: -; X32AVX: # %bb.0: -; X32AVX-NEXT: pushl %ebp -; X32AVX-NEXT: movl %esp, %ebp -; X32AVX-NEXT: andl $-32, %esp -; X32AVX-NEXT: subl $96, %esp -; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32AVX-NEXT: movl 52(%ebp), %eax -; X32AVX-NEXT: andl $7, %eax -; X32AVX-NEXT: movl 48(%ebp), %ecx -; X32AVX-NEXT: vmovups 8(%ebp), %ymm1 -; X32AVX-NEXT: vmovaps %ymm1, (%esp) -; X32AVX-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) -; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32AVX-NEXT: vmovsd %xmm0, (%ecx) -; X32AVX-NEXT: movl %ebp, %esp -; X32AVX-NEXT: popl %ebp -; X32AVX-NEXT: vzeroupper -; X32AVX-NEXT: retl +; X86AVX-LABEL: PR23476: +; X86AVX: # %bb.0: +; X86AVX-NEXT: pushl %ebp +; X86AVX-NEXT: movl %esp, %ebp +; X86AVX-NEXT: andl $-32, %esp +; X86AVX-NEXT: subl $96, %esp +; X86AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86AVX-NEXT: movl 52(%ebp), %eax +; X86AVX-NEXT: andl $7, %eax +; X86AVX-NEXT: movl 48(%ebp), %ecx +; X86AVX-NEXT: vmovups 8(%ebp), %ymm1 +; X86AVX-NEXT: vmovaps %ymm1, (%esp) +; X86AVX-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) +; X86AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86AVX-NEXT: vmovsd %xmm0, (%ecx) +; X86AVX-NEXT: movl %ebp, %esp +; X86AVX-NEXT: popl %ebp +; X86AVX-NEXT: vzeroupper +; X86AVX-NEXT: retl %ext = extractelement <5 x i64> %in, i32 %index store i64 %ext, ptr %out, align 8 ret void -- GitLab From 8bd16789ff0af00270936c4536dd18b48e4d3897 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:53:28 +0000 Subject: [PATCH 083/652] [X86] lea-2.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only (although in this case the gnux32 tests share the X64 checks) --- llvm/test/CodeGen/X86/lea-2.ll | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/llvm/test/CodeGen/X86/lea-2.ll b/llvm/test/CodeGen/X86/lea-2.ll index c91e2f297405..a48c02ff3e0b 100644 --- a/llvm/test/CodeGen/X86/lea-2.ll +++ b/llvm/test/CodeGen/X86/lea-2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-linux | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-linux | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=X64 @@ -7,12 +7,12 @@ ; The computation of %t4 should match a single lea, without using actual add instructions. define i32 @test1(i32 %A, i32 %B) { -; X32-LABEL: test1: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: leal -5(%ecx,%eax,4), %eax -; X32-NEXT: retl +; X86-LABEL: test1: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal -5(%ecx,%eax,4), %eax +; X86-NEXT: retl ; ; X64-LABEL: test1: ; X64: # %bb.0: @@ -29,16 +29,16 @@ define i32 @test1(i32 %A, i32 %B) { ; The addlike OR instruction should fold into the LEA. define i64 @test2(i32 %a0, i64 %a1) { -; X32-LABEL: test2: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: movl %edx, %eax -; X32-NEXT: andl $2147483640, %eax # imm = 0x7FFFFFF8 -; X32-NEXT: shrl $31, %edx -; X32-NEXT: leal 4(%eax,%eax), %eax -; X32-NEXT: addl {{[0-9]+}}(%esp), %eax -; X32-NEXT: adcl {{[0-9]+}}(%esp), %edx -; X32-NEXT: retl +; X86-LABEL: test2: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %edx, %eax +; X86-NEXT: andl $2147483640, %eax # imm = 0x7FFFFFF8 +; X86-NEXT: shrl $31, %edx +; X86-NEXT: leal 4(%eax,%eax), %eax +; X86-NEXT: addl {{[0-9]+}}(%esp), %eax +; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx +; X86-NEXT: retl ; ; X64-LABEL: test2: ; X64: # %bb.0: -- GitLab From 635f6d384596950e73b2485842c587a2954c655f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:54:29 +0000 Subject: [PATCH 084/652] [X86] inline-sse.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. --- llvm/test/CodeGen/X86/inline-sse.ll | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/llvm/test/CodeGen/X86/inline-sse.ll b/llvm/test/CodeGen/X86/inline-sse.ll index 4e09359afa82..87aa882a1f49 100644 --- a/llvm/test/CodeGen/X86/inline-sse.ll +++ b/llvm/test/CodeGen/X86/inline-sse.ll @@ -1,23 +1,23 @@ -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32 -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 ; PR16133 - we must treat XMM registers as v4f32 as SSE1 targets don't permit other vector types. define void @nop() nounwind { -; X32-LABEL: nop: -; X32: # %bb.0: -; X32-NEXT: pushl %ebp -; X32-NEXT: movl %esp, %ebp -; X32-NEXT: andl $-16, %esp -; X32-NEXT: subl $32, %esp -; X32-NEXT: #APP -; X32-NEXT: #NO_APP -; X32-NEXT: movaps %xmm0, (%esp) -; X32-NEXT: movl %ebp, %esp -; X32-NEXT: popl %ebp -; X32-NEXT: retl +; X86-LABEL: nop: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-16, %esp +; X86-NEXT: subl $32, %esp +; X86-NEXT: #APP +; X86-NEXT: #NO_APP +; X86-NEXT: movaps %xmm0, (%esp) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl ; ; X64-LABEL: nop: ; X64: # %bb.0: -- GitLab From 9632f987161b4efeb8c087f19a3eb4f7c69cc920 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 12:59:00 +0000 Subject: [PATCH 085/652] [X86] legalize-shl-vec.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. Add nounwind to remove cfi noise as well. --- llvm/test/CodeGen/X86/legalize-shl-vec.ll | 332 ++++++++++------------ 1 file changed, 152 insertions(+), 180 deletions(-) diff --git a/llvm/test/CodeGen/X86/legalize-shl-vec.ll b/llvm/test/CodeGen/X86/legalize-shl-vec.ll index cf423227f23b..5e168a82e03e 100644 --- a/llvm/test/CodeGen/X86/legalize-shl-vec.ll +++ b/llvm/test/CodeGen/X86/legalize-shl-vec.ll @@ -1,46 +1,46 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 -define <2 x i256> @test_shl(<2 x i256> %In) { -; X32-LABEL: test_shl: -; X32: # %bb.0: -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: shldl $2, %ecx, %edx -; X32-NEXT: movl %edx, 60(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: shldl $2, %edx, %ecx -; X32-NEXT: movl %ecx, 56(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: shldl $2, %ecx, %edx -; X32-NEXT: movl %edx, 52(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: shldl $2, %edx, %ecx -; X32-NEXT: movl %ecx, 48(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: shldl $2, %ecx, %edx -; X32-NEXT: movl %edx, 44(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: shldl $2, %edx, %ecx -; X32-NEXT: movl %ecx, 40(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: shldl $2, %ecx, %edx -; X32-NEXT: movl %edx, 36(%eax) -; X32-NEXT: shll $2, %ecx -; X32-NEXT: movl %ecx, 32(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: shll $31, %ecx -; X32-NEXT: movl %ecx, 28(%eax) -; X32-NEXT: movl $0, 24(%eax) -; X32-NEXT: movl $0, 20(%eax) -; X32-NEXT: movl $0, 16(%eax) -; X32-NEXT: movl $0, 12(%eax) -; X32-NEXT: movl $0, 8(%eax) -; X32-NEXT: movl $0, 4(%eax) -; X32-NEXT: movl $0, (%eax) -; X32-NEXT: retl $4 +define <2 x i256> @test_shl(<2 x i256> %In) nounwind { +; X86-LABEL: test_shl: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: shldl $2, %ecx, %edx +; X86-NEXT: movl %edx, 60(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: shldl $2, %edx, %ecx +; X86-NEXT: movl %ecx, 56(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shldl $2, %ecx, %edx +; X86-NEXT: movl %edx, 52(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: shldl $2, %edx, %ecx +; X86-NEXT: movl %ecx, 48(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shldl $2, %ecx, %edx +; X86-NEXT: movl %edx, 44(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: shldl $2, %edx, %ecx +; X86-NEXT: movl %ecx, 40(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shldl $2, %ecx, %edx +; X86-NEXT: movl %edx, 36(%eax) +; X86-NEXT: shll $2, %ecx +; X86-NEXT: movl %ecx, 32(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shll $31, %ecx +; X86-NEXT: movl %ecx, 28(%eax) +; X86-NEXT: movl $0, 24(%eax) +; X86-NEXT: movl $0, 20(%eax) +; X86-NEXT: movl $0, 16(%eax) +; X86-NEXT: movl $0, 12(%eax) +; X86-NEXT: movl $0, 8(%eax) +; X86-NEXT: movl $0, 4(%eax) +; X86-NEXT: movl $0, (%eax) +; X86-NEXT: retl $4 ; ; X64-LABEL: test_shl: ; X64: # %bb.0: @@ -67,76 +67,62 @@ define <2 x i256> @test_shl(<2 x i256> %In) { ret <2 x i256> %Out } -define <2 x i256> @test_srl(<2 x i256> %In) { -; X32-LABEL: test_srl: -; X32: # %bb.0: -; X32-NEXT: pushl %ebp -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: pushl %ebx -; X32-NEXT: .cfi_def_cfa_offset 12 -; X32-NEXT: pushl %edi -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: pushl %esi -; X32-NEXT: .cfi_def_cfa_offset 20 -; X32-NEXT: subl $8, %esp -; X32-NEXT: .cfi_def_cfa_offset 28 -; X32-NEXT: .cfi_offset %esi, -20 -; X32-NEXT: .cfi_offset %edi, -16 -; X32-NEXT: .cfi_offset %ebx, -12 -; X32-NEXT: .cfi_offset %ebp, -8 -; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %edi -; X32-NEXT: movl %ebp, %esi -; X32-NEXT: shldl $28, %edx, %esi -; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: shldl $28, %ebx, %edx -; X32-NEXT: movl %edx, (%esp) # 4-byte Spill -; X32-NEXT: shldl $28, %ecx, %ebx -; X32-NEXT: movl %ecx, %esi -; X32-NEXT: shldl $28, %edi, %esi -; X32-NEXT: shldl $28, %eax, %edi -; X32-NEXT: movl %eax, %edx -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: shldl $28, %eax, %edx -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: shrdl $4, %eax, %ecx -; X32-NEXT: shrl $4, %ebp -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl %ebp, 60(%eax) -; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload -; X32-NEXT: movl %ebp, 56(%eax) -; X32-NEXT: movl (%esp), %ebp # 4-byte Reload -; X32-NEXT: movl %ebp, 52(%eax) -; X32-NEXT: movl %ebx, 48(%eax) -; X32-NEXT: movl %esi, 44(%eax) -; X32-NEXT: movl %edi, 40(%eax) -; X32-NEXT: movl %edx, 36(%eax) -; X32-NEXT: movl %ecx, 32(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: shrl $31, %ecx -; X32-NEXT: movl %ecx, (%eax) -; X32-NEXT: movl $0, 28(%eax) -; X32-NEXT: movl $0, 24(%eax) -; X32-NEXT: movl $0, 20(%eax) -; X32-NEXT: movl $0, 16(%eax) -; X32-NEXT: movl $0, 12(%eax) -; X32-NEXT: movl $0, 8(%eax) -; X32-NEXT: movl $0, 4(%eax) -; X32-NEXT: addl $8, %esp -; X32-NEXT: .cfi_def_cfa_offset 20 -; X32-NEXT: popl %esi -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: popl %edi -; X32-NEXT: .cfi_def_cfa_offset 12 -; X32-NEXT: popl %ebx -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: popl %ebp -; X32-NEXT: .cfi_def_cfa_offset 4 -; X32-NEXT: retl $4 +define <2 x i256> @test_srl(<2 x i256> %In) nounwind { +; X86-LABEL: test_srl: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $8, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %ebp, %esi +; X86-NEXT: shldl $28, %edx, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $28, %ebx, %edx +; X86-NEXT: movl %edx, (%esp) # 4-byte Spill +; X86-NEXT: shldl $28, %ecx, %ebx +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: shldl $28, %edi, %esi +; X86-NEXT: shldl $28, %eax, %edi +; X86-NEXT: movl %eax, %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: shldl $28, %eax, %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shrdl $4, %eax, %ecx +; X86-NEXT: shrl $4, %ebp +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl %ebp, 60(%eax) +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload +; X86-NEXT: movl %ebp, 56(%eax) +; X86-NEXT: movl (%esp), %ebp # 4-byte Reload +; X86-NEXT: movl %ebp, 52(%eax) +; X86-NEXT: movl %ebx, 48(%eax) +; X86-NEXT: movl %esi, 44(%eax) +; X86-NEXT: movl %edi, 40(%eax) +; X86-NEXT: movl %edx, 36(%eax) +; X86-NEXT: movl %ecx, 32(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shrl $31, %ecx +; X86-NEXT: movl %ecx, (%eax) +; X86-NEXT: movl $0, 28(%eax) +; X86-NEXT: movl $0, 24(%eax) +; X86-NEXT: movl $0, 20(%eax) +; X86-NEXT: movl $0, 16(%eax) +; X86-NEXT: movl $0, 12(%eax) +; X86-NEXT: movl $0, 8(%eax) +; X86-NEXT: movl $0, 4(%eax) +; X86-NEXT: addl $8, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: popl %ebp +; X86-NEXT: retl $4 ; ; X64-LABEL: test_srl: ; X64: # %bb.0: @@ -163,76 +149,62 @@ define <2 x i256> @test_srl(<2 x i256> %In) { ret <2 x i256> %Out } -define <2 x i256> @test_sra(<2 x i256> %In) { -; X32-LABEL: test_sra: -; X32: # %bb.0: -; X32-NEXT: pushl %ebp -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: pushl %ebx -; X32-NEXT: .cfi_def_cfa_offset 12 -; X32-NEXT: pushl %edi -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: pushl %esi -; X32-NEXT: .cfi_def_cfa_offset 20 -; X32-NEXT: subl $8, %esp -; X32-NEXT: .cfi_def_cfa_offset 28 -; X32-NEXT: .cfi_offset %esi, -20 -; X32-NEXT: .cfi_offset %edi, -16 -; X32-NEXT: .cfi_offset %ebx, -12 -; X32-NEXT: .cfi_offset %ebp, -8 -; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl {{[0-9]+}}(%esp), %edi -; X32-NEXT: movl %ebp, %esi -; X32-NEXT: shldl $26, %edx, %esi -; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: shldl $26, %ebx, %edx -; X32-NEXT: movl %edx, (%esp) # 4-byte Spill -; X32-NEXT: shldl $26, %ecx, %ebx -; X32-NEXT: movl %ecx, %esi -; X32-NEXT: shldl $26, %edi, %esi -; X32-NEXT: shldl $26, %eax, %edi -; X32-NEXT: movl %eax, %edx -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: shldl $26, %eax, %edx -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: shrdl $6, %eax, %ecx -; X32-NEXT: sarl $6, %ebp -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movl %ebp, 60(%eax) -; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload -; X32-NEXT: movl %ebp, 56(%eax) -; X32-NEXT: movl (%esp), %ebp # 4-byte Reload -; X32-NEXT: movl %ebp, 52(%eax) -; X32-NEXT: movl %ebx, 48(%eax) -; X32-NEXT: movl %esi, 44(%eax) -; X32-NEXT: movl %edi, 40(%eax) -; X32-NEXT: movl %edx, 36(%eax) -; X32-NEXT: movl %ecx, 32(%eax) -; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: sarl $31, %ecx -; X32-NEXT: movl %ecx, 28(%eax) -; X32-NEXT: movl %ecx, 24(%eax) -; X32-NEXT: movl %ecx, 20(%eax) -; X32-NEXT: movl %ecx, 16(%eax) -; X32-NEXT: movl %ecx, 12(%eax) -; X32-NEXT: movl %ecx, 8(%eax) -; X32-NEXT: movl %ecx, 4(%eax) -; X32-NEXT: movl %ecx, (%eax) -; X32-NEXT: addl $8, %esp -; X32-NEXT: .cfi_def_cfa_offset 20 -; X32-NEXT: popl %esi -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: popl %edi -; X32-NEXT: .cfi_def_cfa_offset 12 -; X32-NEXT: popl %ebx -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: popl %ebp -; X32-NEXT: .cfi_def_cfa_offset 4 -; X32-NEXT: retl $4 +define <2 x i256> @test_sra(<2 x i256> %In) nounwind { +; X86-LABEL: test_sra: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $8, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %ebp, %esi +; X86-NEXT: shldl $26, %edx, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $26, %ebx, %edx +; X86-NEXT: movl %edx, (%esp) # 4-byte Spill +; X86-NEXT: shldl $26, %ecx, %ebx +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: shldl $26, %edi, %esi +; X86-NEXT: shldl $26, %eax, %edi +; X86-NEXT: movl %eax, %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: shldl $26, %eax, %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shrdl $6, %eax, %ecx +; X86-NEXT: sarl $6, %ebp +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl %ebp, 60(%eax) +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload +; X86-NEXT: movl %ebp, 56(%eax) +; X86-NEXT: movl (%esp), %ebp # 4-byte Reload +; X86-NEXT: movl %ebp, 52(%eax) +; X86-NEXT: movl %ebx, 48(%eax) +; X86-NEXT: movl %esi, 44(%eax) +; X86-NEXT: movl %edi, 40(%eax) +; X86-NEXT: movl %edx, 36(%eax) +; X86-NEXT: movl %ecx, 32(%eax) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: sarl $31, %ecx +; X86-NEXT: movl %ecx, 28(%eax) +; X86-NEXT: movl %ecx, 24(%eax) +; X86-NEXT: movl %ecx, 20(%eax) +; X86-NEXT: movl %ecx, 16(%eax) +; X86-NEXT: movl %ecx, 12(%eax) +; X86-NEXT: movl %ecx, 8(%eax) +; X86-NEXT: movl %ecx, 4(%eax) +; X86-NEXT: movl %ecx, (%eax) +; X86-NEXT: addl $8, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: popl %ebp +; X86-NEXT: retl $4 ; ; X64-LABEL: test_sra: ; X64: # %bb.0: -- GitLab From fbfc9cb7ea756ea645cc55eea478b819573fc7a5 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 13:00:08 +0000 Subject: [PATCH 086/652] [X86] vector-shuffle-mmx.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. Add nounwind to remove cfi noise as well. --- llvm/test/CodeGen/X86/vector-shuffle-mmx.ll | 84 ++++++++++----------- 1 file changed, 41 insertions(+), 43 deletions(-) diff --git a/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll b/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll index 422f522e11f8..709be6534d77 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll @@ -1,17 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck --check-prefix=X32 %s +; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck --check-prefix=X86 %s ; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck --check-prefix=X64 %s ; If there is no explicit MMX type usage, always promote to XMM. -define void @test0(ptr %x) { -; X32-LABEL: test0: -; X32: ## %bb.0: ## %entry -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] -; X32-NEXT: movlps %xmm0, (%eax) -; X32-NEXT: retl +define void @test0(ptr %x) nounwind { +; X86-LABEL: test0: +; X86: ## %bb.0: ## %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] +; X86-NEXT: movlps %xmm0, (%eax) +; X86-NEXT: retl ; ; X64-LABEL: test0: ; X64: ## %bb.0: ## %entry @@ -28,18 +28,16 @@ entry: ret void } -define void @test1() { -; X32-LABEL: test1: -; X32: ## %bb.0: ## %entry -; X32-NEXT: pushl %edi -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: .cfi_offset %edi, -8 -; X32-NEXT: pxor %mm0, %mm0 -; X32-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}, %mm1 ## mm1 = 0x7070606040400000 -; X32-NEXT: xorl %edi, %edi -; X32-NEXT: maskmovq %mm1, %mm0 -; X32-NEXT: popl %edi -; X32-NEXT: retl +define void @test1() nounwind { +; X86-LABEL: test1: +; X86: ## %bb.0: ## %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pxor %mm0, %mm0 +; X86-NEXT: movq {{\.?LCPI[0-9]+_[0-9]+}}, %mm1 ## mm1 = 0x7070606040400000 +; X86-NEXT: xorl %edi, %edi +; X86-NEXT: maskmovq %mm1, %mm0 +; X86-NEXT: popl %edi +; X86-NEXT: retl ; ; X64-LABEL: test1: ; X64: ## %bb.0: ## %entry @@ -63,13 +61,13 @@ entry: @tmp_V2i = common global <2 x i32> zeroinitializer define void @test2() nounwind { -; X32-LABEL: test2: -; X32: ## %bb.0: ## %entry -; X32-NEXT: movl L_tmp_V2i$non_lazy_ptr, %eax -; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1] -; X32-NEXT: movlps %xmm0, (%eax) -; X32-NEXT: retl +; X86-LABEL: test2: +; X86: ## %bb.0: ## %entry +; X86-NEXT: movl L_tmp_V2i$non_lazy_ptr, %eax +; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1] +; X86-NEXT: movlps %xmm0, (%eax) +; X86-NEXT: retl ; ; X64-LABEL: test2: ; X64: ## %bb.0: ## %entry @@ -86,21 +84,21 @@ entry: } define <4 x float> @pr35869() nounwind { -; X32-LABEL: pr35869: -; X32: ## %bb.0: -; X32-NEXT: movl $64, %eax -; X32-NEXT: movd %eax, %mm0 -; X32-NEXT: pxor %mm1, %mm1 -; X32-NEXT: punpcklbw %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3] -; X32-NEXT: pcmpgtw %mm0, %mm1 -; X32-NEXT: movq %mm0, %mm2 -; X32-NEXT: punpckhwd %mm1, %mm2 ## mm2 = mm2[2],mm1[2],mm2[3],mm1[3] -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: cvtpi2ps %mm2, %xmm0 -; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0] -; X32-NEXT: punpcklwd %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1] -; X32-NEXT: cvtpi2ps %mm0, %xmm0 -; X32-NEXT: retl +; X86-LABEL: pr35869: +; X86: ## %bb.0: +; X86-NEXT: movl $64, %eax +; X86-NEXT: movd %eax, %mm0 +; X86-NEXT: pxor %mm1, %mm1 +; X86-NEXT: punpcklbw %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3] +; X86-NEXT: pcmpgtw %mm0, %mm1 +; X86-NEXT: movq %mm0, %mm2 +; X86-NEXT: punpckhwd %mm1, %mm2 ## mm2 = mm2[2],mm1[2],mm2[3],mm1[3] +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: cvtpi2ps %mm2, %xmm0 +; X86-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0] +; X86-NEXT: punpcklwd %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1] +; X86-NEXT: cvtpi2ps %mm0, %xmm0 +; X86-NEXT: retl ; ; X64-LABEL: pr35869: ; X64: ## %bb.0: -- GitLab From 52ebf61bac9d17a960908fe0c5e75dea76de165a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 13:02:13 +0000 Subject: [PATCH 087/652] [X86] ftrunc.ll - replace X32 checks with X86. NFC. We try to use X32 for gnux32 triples only. Add common AVX check prefix for 32/64 bit test coverage --- llvm/test/CodeGen/X86/ftrunc.ll | 720 +++++++++++++++----------------- 1 file changed, 345 insertions(+), 375 deletions(-) diff --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll index d52d14572082..08705e9cdc59 100644 --- a/llvm/test/CodeGen/X86/ftrunc.ll +++ b/llvm/test/CodeGen/X86/ftrunc.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 -; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=X64_AVX1 -; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=X32_AVX1 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,X64-AVX1 +; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,X86-AVX1 declare i32 @llvm.fptoui.sat.i32.f32(float) declare i64 @llvm.fptosi.sat.i64.f64(double) @@ -21,20 +21,20 @@ define float @trunc_unsigned_f32(float %x) #0 { ; SSE41-NEXT: roundss $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_unsigned_f32: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_unsigned_f32: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %eax -; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovss %xmm0, (%esp) -; X32_AVX1-NEXT: flds (%esp) -; X32_AVX1-NEXT: popl %eax -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_unsigned_f32: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_unsigned_f32: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %eax +; X86-AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovss %xmm0, (%esp) +; X86-AVX1-NEXT: flds (%esp) +; X86-AVX1-NEXT: popl %eax +; X86-AVX1-NEXT: retl %i = fptoui float %x to i32 %r = uitofp i32 %i to float ret float %r @@ -63,24 +63,24 @@ define double @trunc_unsigned_f64(double %x) #0 { ; SSE41-NEXT: roundsd $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_unsigned_f64: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_unsigned_f64: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $8, %esp -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovsd %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: movl %ebp, %esp -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_unsigned_f64: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_unsigned_f64: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $8, %esp +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovsd %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: movl %ebp, %esp +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: retl %i = fptoui double %x to i64 %r = uitofp i64 %i to double ret double %r @@ -110,15 +110,10 @@ define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 { ; SSE41-NEXT: roundps $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_unsigned_v4f32: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundps $11, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_unsigned_v4f32: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: vroundps $11, %xmm0, %xmm0 -; X32_AVX1-NEXT: retl +; AVX-LABEL: trunc_unsigned_v4f32: +; AVX: # %bb.0: +; AVX-NEXT: vroundps $11, %xmm0, %xmm0 +; AVX-NEXT: ret{{[l|q]}} %i = fptoui <4 x float> %x to <4 x i32> %r = uitofp <4 x i32> %i to <4 x float> ret <4 x float> %r @@ -162,15 +157,10 @@ define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 { ; SSE41-NEXT: roundpd $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_unsigned_v2f64: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_unsigned_v2f64: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0 -; X32_AVX1-NEXT: retl +; AVX-LABEL: trunc_unsigned_v2f64: +; AVX: # %bb.0: +; AVX-NEXT: vroundpd $11, %xmm0, %xmm0 +; AVX-NEXT: ret{{[l|q]}} %i = fptoui <2 x double> %x to <2 x i64> %r = uitofp <2 x i64> %i to <2 x double> ret <2 x double> %r @@ -244,15 +234,10 @@ define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 { ; SSE41-NEXT: roundpd $11, %xmm1, %xmm1 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_unsigned_v4f64: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_unsigned_v4f64: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0 -; X32_AVX1-NEXT: retl +; AVX-LABEL: trunc_unsigned_v4f64: +; AVX: # %bb.0: +; AVX-NEXT: vroundpd $11, %ymm0, %ymm0 +; AVX-NEXT: ret{{[l|q]}} %i = fptoui <4 x double> %x to <4 x i64> %r = uitofp <4 x i64> %i to <4 x double> ret <4 x double> %r @@ -265,24 +250,24 @@ define float @trunc_signed_f32_no_fast_math(float %x) { ; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_f32_no_fast_math: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 -; X64_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_f32_no_fast_math: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %eax -; X32_AVX1-NEXT: .cfi_def_cfa_offset 8 -; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 -; X32_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovss %xmm0, (%esp) -; X32_AVX1-NEXT: flds (%esp) -; X32_AVX1-NEXT: popl %eax -; X32_AVX1-NEXT: .cfi_def_cfa_offset 4 -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_signed_f32_no_fast_math: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 +; X64-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_signed_f32_no_fast_math: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %eax +; X86-AVX1-NEXT: .cfi_def_cfa_offset 8 +; X86-AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 +; X86-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovss %xmm0, (%esp) +; X86-AVX1-NEXT: flds (%esp) +; X86-AVX1-NEXT: popl %eax +; X86-AVX1-NEXT: .cfi_def_cfa_offset 4 +; X86-AVX1-NEXT: retl %i = fptosi float %x to i32 %r = sitofp i32 %i to float ret float %r @@ -302,20 +287,20 @@ define float @trunc_signed_f32_nsz(float %x) #0 { ; SSE41-NEXT: roundss $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_f32_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_f32_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %eax -; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovss %xmm0, (%esp) -; X32_AVX1-NEXT: flds (%esp) -; X32_AVX1-NEXT: popl %eax -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_signed_f32_nsz: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_signed_f32_nsz: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %eax +; X86-AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovss %xmm0, (%esp) +; X86-AVX1-NEXT: flds (%esp) +; X86-AVX1-NEXT: popl %eax +; X86-AVX1-NEXT: retl %i = fptosi float %x to i32 %r = sitofp i32 %i to float ret float %r @@ -328,30 +313,30 @@ define double @trunc_signed32_f64_no_fast_math(double %x) { ; SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed32_f64_no_fast_math: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 -; X64_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed32_f64_no_fast_math: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: .cfi_def_cfa_offset 8 -; X32_AVX1-NEXT: .cfi_offset %ebp, -8 -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: .cfi_def_cfa_register %ebp -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $8, %esp -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 -; X32_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovlps %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: movl %ebp, %esp -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: .cfi_def_cfa %esp, 4 -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_signed32_f64_no_fast_math: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 +; X64-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_signed32_f64_no_fast_math: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: .cfi_def_cfa_offset 8 +; X86-AVX1-NEXT: .cfi_offset %ebp, -8 +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $8, %esp +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 +; X86-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovlps %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: movl %ebp, %esp +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4 +; X86-AVX1-NEXT: retl %i = fptosi double %x to i32 %r = sitofp i32 %i to double ret double %r @@ -369,24 +354,24 @@ define double @trunc_signed32_f64_nsz(double %x) #0 { ; SSE41-NEXT: roundsd $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed32_f64_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed32_f64_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $8, %esp -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovsd %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: movl %ebp, %esp -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_signed32_f64_nsz: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_signed32_f64_nsz: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $8, %esp +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovsd %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: movl %ebp, %esp +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: retl %i = fptosi double %x to i32 %r = sitofp i32 %i to double ret double %r @@ -399,30 +384,30 @@ define double @trunc_f32_signed32_f64_no_fast_math(float %x) { ; SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 -; X64_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: .cfi_def_cfa_offset 8 -; X32_AVX1-NEXT: .cfi_offset %ebp, -8 -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: .cfi_def_cfa_register %ebp -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $8, %esp -; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 -; X32_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovlps %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: movl %ebp, %esp -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: .cfi_def_cfa %esp, 4 -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 +; X64-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: .cfi_def_cfa_offset 8 +; X86-AVX1-NEXT: .cfi_offset %ebp, -8 +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $8, %esp +; X86-AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 +; X86-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovlps %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: movl %ebp, %esp +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4 +; X86-AVX1-NEXT: retl %i = fptosi float %x to i32 %r = sitofp i32 %i to double ret double %r @@ -435,26 +420,26 @@ define double @trunc_f32_signed32_f64_nsz(float %x) #0 { ; SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_f32_signed32_f64_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 -; X64_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_f32_signed32_f64_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $8, %esp -; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 -; X32_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovlps %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: movl %ebp, %esp -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_f32_signed32_f64_nsz: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 +; X64-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_f32_signed32_f64_nsz: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $8, %esp +; X86-AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 +; X86-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovlps %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: movl %ebp, %esp +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: retl %i = fptosi float %x to i32 %r = sitofp i32 %i to double ret double %r @@ -467,24 +452,24 @@ define float @trunc_f64_signed32_f32_no_fast_math(double %x) { ; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 -; X64_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %eax -; X32_AVX1-NEXT: .cfi_def_cfa_offset 8 -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 -; X32_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovss %xmm0, (%esp) -; X32_AVX1-NEXT: flds (%esp) -; X32_AVX1-NEXT: popl %eax -; X32_AVX1-NEXT: .cfi_def_cfa_offset 4 -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 +; X64-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %eax +; X86-AVX1-NEXT: .cfi_def_cfa_offset 8 +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 +; X86-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovss %xmm0, (%esp) +; X86-AVX1-NEXT: flds (%esp) +; X86-AVX1-NEXT: popl %eax +; X86-AVX1-NEXT: .cfi_def_cfa_offset 4 +; X86-AVX1-NEXT: retl %i = fptosi double %x to i32 %r = sitofp i32 %i to float ret float %r @@ -497,22 +482,22 @@ define float @trunc_f64_signed32_f32_nsz(double %x) #0 { ; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_f64_signed32_f32_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 -; X64_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_f64_signed32_f32_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %eax -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 -; X32_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovss %xmm0, (%esp) -; X32_AVX1-NEXT: flds (%esp) -; X32_AVX1-NEXT: popl %eax -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_f64_signed32_f32_nsz: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 +; X64-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_f64_signed32_f32_nsz: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %eax +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 +; X86-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovss %xmm0, (%esp) +; X86-AVX1-NEXT: flds (%esp) +; X86-AVX1-NEXT: popl %eax +; X86-AVX1-NEXT: retl %i = fptosi double %x to i32 %r = sitofp i32 %i to float ret float %r @@ -526,34 +511,34 @@ define double @trunc_signed_f64_no_fast_math(double %x) { ; SSE-NEXT: cvtsi2sd %rax, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_f64_no_fast_math: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttsd2si %xmm0, %rax -; X64_AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_f64_no_fast_math: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: .cfi_def_cfa_offset 8 -; X32_AVX1-NEXT: .cfi_offset %ebp, -8 -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: .cfi_def_cfa_register %ebp -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $24, %esp -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vmovsd %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: fisttpll (%esp) -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: fildll {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: fstpl {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: fldl {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: movl %ebp, %esp -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: .cfi_def_cfa %esp, 4 -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_signed_f64_no_fast_math: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttsd2si %xmm0, %rax +; X64-AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_signed_f64_no_fast_math: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: .cfi_def_cfa_offset 8 +; X86-AVX1-NEXT: .cfi_offset %ebp, -8 +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $24, %esp +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vmovsd %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: fisttpll (%esp) +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: fildll {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: fstpl {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: fldl {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: movl %ebp, %esp +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4 +; X86-AVX1-NEXT: retl %i = fptosi double %x to i64 %r = sitofp i64 %i to double ret double %r @@ -572,24 +557,24 @@ define double @trunc_signed_f64_nsz(double %x) #0 { ; SSE41-NEXT: roundsd $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_f64_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_f64_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $8, %esp -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovsd %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: movl %ebp, %esp -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_signed_f64_nsz: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_signed_f64_nsz: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $8, %esp +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovsd %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: movl %ebp, %esp +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: retl %i = fptosi double %x to i64 %r = sitofp i64 %i to double ret double %r @@ -607,15 +592,10 @@ define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) #0 { ; SSE41-NEXT: roundps $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_v4f32_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundps $11, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_v4f32_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: vroundps $11, %xmm0, %xmm0 -; X32_AVX1-NEXT: retl +; AVX-LABEL: trunc_signed_v4f32_nsz: +; AVX: # %bb.0: +; AVX-NEXT: vroundps $11, %xmm0, %xmm0 +; AVX-NEXT: ret{{[l|q]}} %i = fptosi <4 x float> %x to <4 x i32> %r = sitofp <4 x i32> %i to <4 x float> ret <4 x float> %r @@ -638,15 +618,10 @@ define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 { ; SSE41-NEXT: roundpd $11, %xmm0, %xmm0 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_v2f64_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_v2f64_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0 -; X32_AVX1-NEXT: retl +; AVX-LABEL: trunc_signed_v2f64_nsz: +; AVX: # %bb.0: +; AVX-NEXT: vroundpd $11, %xmm0, %xmm0 +; AVX-NEXT: ret{{[l|q]}} %i = fptosi <2 x double> %x to <2 x i64> %r = sitofp <2 x i64> %i to <2 x double> ret <2 x double> %r @@ -678,15 +653,10 @@ define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 { ; SSE41-NEXT: roundpd $11, %xmm1, %xmm1 ; SSE41-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_v4f64_nsz: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_v4f64_nsz: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0 -; X32_AVX1-NEXT: retl +; AVX-LABEL: trunc_signed_v4f64_nsz: +; AVX: # %bb.0: +; AVX-NEXT: vroundpd $11, %ymm0, %ymm0 +; AVX-NEXT: ret{{[l|q]}} %i = fptosi <4 x double> %x to <4 x i64> %r = sitofp <4 x i64> %i to <4 x double> ret <4 x double> %r @@ -715,45 +685,45 @@ define float @trunc_unsigned_f32_disable_via_intrinsic(float %x) #0 { ; SSE-NEXT: cvtsi2ss %rax, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_unsigned_f32_disable_via_intrinsic: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttss2si %xmm0, %rax -; X64_AVX1-NEXT: xorl %ecx, %ecx -; X64_AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 -; X64_AVX1-NEXT: vucomiss %xmm1, %xmm0 -; X64_AVX1-NEXT: cmovael %eax, %ecx -; X64_AVX1-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; X64_AVX1-NEXT: movl $-1, %eax -; X64_AVX1-NEXT: cmovbel %ecx, %eax -; X64_AVX1-NEXT: vcvtsi2ss %rax, %xmm2, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_unsigned_f32_disable_via_intrinsic: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %eax -; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32_AVX1-NEXT: vcvttss2si %xmm0, %eax -; X32_AVX1-NEXT: movl %eax, %ecx -; X32_AVX1-NEXT: sarl $31, %ecx -; X32_AVX1-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1 -; X32_AVX1-NEXT: vcvttss2si %xmm1, %edx -; X32_AVX1-NEXT: andl %ecx, %edx -; X32_AVX1-NEXT: orl %eax, %edx -; X32_AVX1-NEXT: xorl %eax, %eax -; X32_AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 -; X32_AVX1-NEXT: vucomiss %xmm1, %xmm0 -; X32_AVX1-NEXT: cmovael %edx, %eax -; X32_AVX1-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32_AVX1-NEXT: movl $-1, %ecx -; X32_AVX1-NEXT: cmovbel %eax, %ecx -; X32_AVX1-NEXT: vmovd %ecx, %xmm0 -; X32_AVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 -; X32_AVX1-NEXT: vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 -; X32_AVX1-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovss %xmm0, (%esp) -; X32_AVX1-NEXT: flds (%esp) -; X32_AVX1-NEXT: popl %eax -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_unsigned_f32_disable_via_intrinsic: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttss2si %xmm0, %rax +; X64-AVX1-NEXT: xorl %ecx, %ecx +; X64-AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X64-AVX1-NEXT: vucomiss %xmm1, %xmm0 +; X64-AVX1-NEXT: cmovael %eax, %ecx +; X64-AVX1-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; X64-AVX1-NEXT: movl $-1, %eax +; X64-AVX1-NEXT: cmovbel %ecx, %eax +; X64-AVX1-NEXT: vcvtsi2ss %rax, %xmm2, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_unsigned_f32_disable_via_intrinsic: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %eax +; X86-AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-AVX1-NEXT: vcvttss2si %xmm0, %eax +; X86-AVX1-NEXT: movl %eax, %ecx +; X86-AVX1-NEXT: sarl $31, %ecx +; X86-AVX1-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1 +; X86-AVX1-NEXT: vcvttss2si %xmm1, %edx +; X86-AVX1-NEXT: andl %ecx, %edx +; X86-AVX1-NEXT: orl %eax, %edx +; X86-AVX1-NEXT: xorl %eax, %eax +; X86-AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X86-AVX1-NEXT: vucomiss %xmm1, %xmm0 +; X86-AVX1-NEXT: cmovael %edx, %eax +; X86-AVX1-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-AVX1-NEXT: movl $-1, %ecx +; X86-AVX1-NEXT: cmovbel %eax, %ecx +; X86-AVX1-NEXT: vmovd %ecx, %xmm0 +; X86-AVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 +; X86-AVX1-NEXT: vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 +; X86-AVX1-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovss %xmm0, (%esp) +; X86-AVX1-NEXT: flds (%esp) +; X86-AVX1-NEXT: popl %eax +; X86-AVX1-NEXT: retl %i = call i32 @llvm.fptoui.sat.i32.f32(float %x) %r = uitofp i32 %i to float ret float %r @@ -773,56 +743,56 @@ define double @trunc_signed_f64_disable_via_intrinsic(double %x) #0 { ; SSE-NEXT: cvtsi2sd %rax, %xmm0 ; SSE-NEXT: retq ; -; X64_AVX1-LABEL: trunc_signed_f64_disable_via_intrinsic: -; X64_AVX1: # %bb.0: -; X64_AVX1-NEXT: vcvttsd2si %xmm0, %rax -; X64_AVX1-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; X64_AVX1-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF -; X64_AVX1-NEXT: cmovbeq %rax, %rcx -; X64_AVX1-NEXT: xorl %eax, %eax -; X64_AVX1-NEXT: vucomisd %xmm0, %xmm0 -; X64_AVX1-NEXT: cmovnpq %rcx, %rax -; X64_AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0 -; X64_AVX1-NEXT: retq -; -; X32_AVX1-LABEL: trunc_signed_f64_disable_via_intrinsic: -; X32_AVX1: # %bb.0: -; X32_AVX1-NEXT: pushl %ebp -; X32_AVX1-NEXT: movl %esp, %ebp -; X32_AVX1-NEXT: pushl %esi -; X32_AVX1-NEXT: andl $-8, %esp -; X32_AVX1-NEXT: subl $32, %esp -; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32_AVX1-NEXT: vmovsd %xmm0, (%esp) -; X32_AVX1-NEXT: fldl (%esp) -; X32_AVX1-NEXT: fisttpll (%esp) -; X32_AVX1-NEXT: xorl %eax, %eax -; X32_AVX1-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32_AVX1-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X32_AVX1-NEXT: movl $0, %edx -; X32_AVX1-NEXT: jb .LBB19_2 -; X32_AVX1-NEXT: # %bb.1: -; X32_AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32_AVX1-NEXT: movl (%esp), %edx -; X32_AVX1-NEXT: .LBB19_2: -; X32_AVX1-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32_AVX1-NEXT: movl $-1, %esi -; X32_AVX1-NEXT: cmovbel %edx, %esi -; X32_AVX1-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF -; X32_AVX1-NEXT: cmovbel %ecx, %edx -; X32_AVX1-NEXT: vucomisd %xmm0, %xmm0 -; X32_AVX1-NEXT: cmovpl %eax, %edx -; X32_AVX1-NEXT: cmovpl %eax, %esi -; X32_AVX1-NEXT: vmovd %esi, %xmm0 -; X32_AVX1-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0 -; X32_AVX1-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: fildll {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: fstpl {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: fldl {{[0-9]+}}(%esp) -; X32_AVX1-NEXT: leal -4(%ebp), %esp -; X32_AVX1-NEXT: popl %esi -; X32_AVX1-NEXT: popl %ebp -; X32_AVX1-NEXT: retl +; X64-AVX1-LABEL: trunc_signed_f64_disable_via_intrinsic: +; X64-AVX1: # %bb.0: +; X64-AVX1-NEXT: vcvttsd2si %xmm0, %rax +; X64-AVX1-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; X64-AVX1-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF +; X64-AVX1-NEXT: cmovbeq %rax, %rcx +; X64-AVX1-NEXT: xorl %eax, %eax +; X64-AVX1-NEXT: vucomisd %xmm0, %xmm0 +; X64-AVX1-NEXT: cmovnpq %rcx, %rax +; X64-AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0 +; X64-AVX1-NEXT: retq +; +; X86-AVX1-LABEL: trunc_signed_f64_disable_via_intrinsic: +; X86-AVX1: # %bb.0: +; X86-AVX1-NEXT: pushl %ebp +; X86-AVX1-NEXT: movl %esp, %ebp +; X86-AVX1-NEXT: pushl %esi +; X86-AVX1-NEXT: andl $-8, %esp +; X86-AVX1-NEXT: subl $32, %esp +; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-AVX1-NEXT: vmovsd %xmm0, (%esp) +; X86-AVX1-NEXT: fldl (%esp) +; X86-AVX1-NEXT: fisttpll (%esp) +; X86-AVX1-NEXT: xorl %eax, %eax +; X86-AVX1-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-AVX1-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 +; X86-AVX1-NEXT: movl $0, %edx +; X86-AVX1-NEXT: jb .LBB19_2 +; X86-AVX1-NEXT: # %bb.1: +; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-AVX1-NEXT: movl (%esp), %edx +; X86-AVX1-NEXT: .LBB19_2: +; X86-AVX1-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-AVX1-NEXT: movl $-1, %esi +; X86-AVX1-NEXT: cmovbel %edx, %esi +; X86-AVX1-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF +; X86-AVX1-NEXT: cmovbel %ecx, %edx +; X86-AVX1-NEXT: vucomisd %xmm0, %xmm0 +; X86-AVX1-NEXT: cmovpl %eax, %edx +; X86-AVX1-NEXT: cmovpl %eax, %esi +; X86-AVX1-NEXT: vmovd %esi, %xmm0 +; X86-AVX1-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0 +; X86-AVX1-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: fildll {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: fstpl {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: fldl {{[0-9]+}}(%esp) +; X86-AVX1-NEXT: leal -4(%ebp), %esp +; X86-AVX1-NEXT: popl %esi +; X86-AVX1-NEXT: popl %ebp +; X86-AVX1-NEXT: retl %i = call i64 @llvm.fptosi.sat.i64.f64(double %x) %r = sitofp i64 %i to double ret double %r -- GitLab From a14650572c2752c0e08a66ce94c43578abf378f8 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 8 Jan 2024 09:31:57 -0800 Subject: [PATCH 088/652] [Sema] Clean up -Wc++11-narrowing-const-reference code after #76094. NFC (#77278) --- .../clang/Basic/DiagnosticSemaKinds.td | 10 ++-- clang/lib/Sema/SemaInit.cpp | 52 +++++++++---------- 2 files changed, 27 insertions(+), 35 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index d150e08d5f5e..a97182cad5d5 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -6160,23 +6160,19 @@ def err_illegal_initializer_type : Error<"illegal initializer type %0">; def ext_init_list_type_narrowing : ExtWarn< "type %0 cannot be narrowed to %1 in initializer list">, InGroup, DefaultError, SFINAEFailure; -// *_narrowing_const_reference diagnostics have the same messages, but are -// controlled by -Wc++11-narrowing-const-reference for narrowing involving a -// const reference. def ext_init_list_type_narrowing_const_reference : ExtWarn< - "type %0 cannot be narrowed to %1 in initializer list">, + ext_init_list_type_narrowing.Summary>, InGroup, DefaultError, SFINAEFailure; def ext_init_list_variable_narrowing : ExtWarn< "non-constant-expression cannot be narrowed from type %0 to %1 in " "initializer list">, InGroup, DefaultError, SFINAEFailure; def ext_init_list_variable_narrowing_const_reference : ExtWarn< - "non-constant-expression cannot be narrowed from type %0 to %1 in " - "initializer list">, InGroup, DefaultError, SFINAEFailure; + ext_init_list_variable_narrowing.Summary>, InGroup, DefaultError, SFINAEFailure; def ext_init_list_constant_narrowing : ExtWarn< "constant expression evaluates to %0 which cannot be narrowed to type %1">, InGroup, DefaultError, SFINAEFailure; def ext_init_list_constant_narrowing_const_reference : ExtWarn< - "constant expression evaluates to %0 which cannot be narrowed to type %1">, + ext_init_list_constant_narrowing.Summary>, InGroup, DefaultError, SFINAEFailure; def warn_init_list_type_narrowing : Warning< "type %0 cannot be narrowed to %1 in initializer list in C++11">, diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index e469e420f14f..408ee5f77580 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -10377,11 +10377,6 @@ void InitializationSequence::dump() const { dump(llvm::errs()); } -static bool NarrowingErrs(const LangOptions &L) { - return L.CPlusPlus11 && - (!L.MicrosoftExt || L.isCompatibleWithMSVC(LangOptions::MSVC2015)); -} - static void DiagnoseNarrowingInInitList(Sema &S, const ImplicitConversionSequence &ICS, QualType PreNarrowingType, @@ -10402,6 +10397,19 @@ static void DiagnoseNarrowingInInitList(Sema &S, return; } + auto MakeDiag = [&](bool IsConstRef, unsigned DefaultDiagID, + unsigned ConstRefDiagID, unsigned WarnDiagID) { + unsigned DiagID; + auto &L = S.getLangOpts(); + if (L.CPlusPlus11 && + (!L.MicrosoftExt || L.isCompatibleWithMSVC(LangOptions::MSVC2015))) + DiagID = IsConstRef ? ConstRefDiagID : DefaultDiagID; + else + DiagID = WarnDiagID; + return S.Diag(PostInit->getBeginLoc(), DiagID) + << PostInit->getSourceRange(); + }; + // C++11 [dcl.init.list]p7: Check whether this is a narrowing conversion. APValue ConstantValue; QualType ConstantType; @@ -10417,13 +10425,9 @@ static void DiagnoseNarrowingInInitList(Sema &S, // narrowing conversion even if the value is a constant and can be // represented exactly as an integer. QualType T = EntityType.getNonReferenceType(); - S.Diag(PostInit->getBeginLoc(), - NarrowingErrs(S.getLangOpts()) - ? (T == EntityType - ? diag::ext_init_list_type_narrowing - : diag::ext_init_list_type_narrowing_const_reference) - : diag::warn_init_list_type_narrowing) - << PostInit->getSourceRange() + MakeDiag(T != EntityType, diag::ext_init_list_type_narrowing, + diag::ext_init_list_type_narrowing_const_reference, + diag::warn_init_list_type_narrowing) << PreNarrowingType.getLocalUnqualifiedType() << T.getLocalUnqualifiedType(); break; @@ -10431,14 +10435,10 @@ static void DiagnoseNarrowingInInitList(Sema &S, case NK_Constant_Narrowing: { // A constant value was narrowed. - QualType T = EntityType.getNonReferenceType(); - S.Diag(PostInit->getBeginLoc(), - NarrowingErrs(S.getLangOpts()) - ? (T == EntityType - ? diag::ext_init_list_constant_narrowing - : diag::ext_init_list_constant_narrowing_const_reference) - : diag::warn_init_list_constant_narrowing) - << PostInit->getSourceRange() + MakeDiag(EntityType.getNonReferenceType() != EntityType, + diag::ext_init_list_constant_narrowing, + diag::ext_init_list_constant_narrowing_const_reference, + diag::warn_init_list_constant_narrowing) << ConstantValue.getAsString(S.getASTContext(), ConstantType) << EntityType.getNonReferenceType().getLocalUnqualifiedType(); break; @@ -10446,14 +10446,10 @@ static void DiagnoseNarrowingInInitList(Sema &S, case NK_Variable_Narrowing: { // A variable's value may have been narrowed. - QualType T = EntityType.getNonReferenceType(); - S.Diag(PostInit->getBeginLoc(), - NarrowingErrs(S.getLangOpts()) - ? (T == EntityType - ? diag::ext_init_list_variable_narrowing - : diag::ext_init_list_variable_narrowing_const_reference) - : diag::warn_init_list_variable_narrowing) - << PostInit->getSourceRange() + MakeDiag(EntityType.getNonReferenceType() != EntityType, + diag::ext_init_list_variable_narrowing, + diag::ext_init_list_variable_narrowing_const_reference, + diag::warn_init_list_variable_narrowing) << PreNarrowingType.getLocalUnqualifiedType() << EntityType.getNonReferenceType().getLocalUnqualifiedType(); break; -- GitLab From 61968286f9a39815040b0d94299c3732834661bf Mon Sep 17 00:00:00 2001 From: Karthika Devi C Date: Mon, 8 Jan 2024 23:18:02 +0530 Subject: [PATCH 089/652] [polly][ScheduleOptimizer] Reland Fix long compile time(hang) reported in polly (#77280) There is no upper cap set on current Schedule Optimizer to compute schedule. In some cases a very long compile time taken to compute the schedule resulting in hang kind of behavior. This patch introduces a flag 'polly-schedule-computeout' to pass the capwhich is initialized to 300000. This patch handles the compute out cases by bailing out and exiting gracefully. Fixed the test that failed in previous commit. Fixes #69090 --- polly/lib/Transform/ScheduleOptimizer.cpp | 25 +++++ .../ScheduleOptimizer/schedule_computeout.ll | 99 +++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 polly/test/ScheduleOptimizer/schedule_computeout.ll diff --git a/polly/lib/Transform/ScheduleOptimizer.cpp b/polly/lib/Transform/ScheduleOptimizer.cpp index 35a0a4def040..8ee2b66339ad 100644 --- a/polly/lib/Transform/ScheduleOptimizer.cpp +++ b/polly/lib/Transform/ScheduleOptimizer.cpp @@ -96,6 +96,13 @@ static cl::opt cl::desc("Maximize the band depth (yes/no)"), cl::Hidden, cl::init("yes"), cl::cat(PollyCategory)); +static cl::opt + ScheduleComputeOut("polly-schedule-computeout", + cl::desc("Bound the scheduler by maximal amount" + "of computational steps. "), + cl::Hidden, cl::init(300000), cl::ZeroOrMore, + cl::cat(PollyCategory)); + static cl::opt GreedyFusion("polly-loopfusion-greedy", cl::desc("Aggressively try to fuse everything"), cl::Hidden, @@ -860,7 +867,25 @@ static void runIslScheduleOptimizer( SC = SC.set_proximity(Proximity); SC = SC.set_validity(Validity); SC = SC.set_coincidence(Validity); + + // Save error handling behavior + long MaxOperations = isl_ctx_get_max_operations(Ctx); + isl_ctx_set_max_operations(Ctx, ScheduleComputeOut); Schedule = SC.compute_schedule(); + bool ScheduleQuota = false; + if (isl_ctx_last_error(Ctx) == isl_error_quota) { + isl_ctx_reset_error(Ctx); + LLVM_DEBUG( + dbgs() << "Schedule optimizer calculation exceeds ISL quota\n"); + ScheduleQuota = true; + } + isl_options_set_on_error(Ctx, ISL_ON_ERROR_ABORT); + isl_ctx_reset_operations(Ctx); + isl_ctx_set_max_operations(Ctx, MaxOperations); + + if (ScheduleQuota) + return; + isl_options_set_on_error(Ctx, OnErrorStatus); ScopsRescheduled++; diff --git a/polly/test/ScheduleOptimizer/schedule_computeout.ll b/polly/test/ScheduleOptimizer/schedule_computeout.ll new file mode 100644 index 000000000000..eb59f0e36ac6 --- /dev/null +++ b/polly/test/ScheduleOptimizer/schedule_computeout.ll @@ -0,0 +1,99 @@ +; RUN: opt %loadPolly -S -polly-optree -polly-delicm -polly-opt-isl -polly-schedule-computeout=100000 -debug-only="polly-opt-isl" < %s 2>&1 | FileCheck %s +; REQUIRES: asserts + +; Bailout if the computations of schedule compute exceeds the max scheduling quota. +; Max compute out is initialized to 300000, Here it is set to 100000 for test purpose. + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64-unknown-linux-gnu" + +@a = dso_local local_unnamed_addr global ptr null, align 8 +@b = dso_local local_unnamed_addr global ptr null, align 8 +@c = dso_local local_unnamed_addr global ptr null, align 8 + +define dso_local void @foo(i32 noundef %I, i32 noundef %J, i32 noundef %K1, i32 noundef %K2, i32 noundef %L1, i32 noundef %L2) local_unnamed_addr { +entry: + %j = alloca i32, align 4 + store volatile i32 0, ptr %j, align 4 + %j.0.j.0.j.0.54 = load volatile i32, ptr %j, align 4 + %cmp55 = icmp slt i32 %j.0.j.0.j.0.54, %J + br i1 %cmp55, label %for.body.lr.ph, label %for.cond.cleanup + +for.body.lr.ph: ; preds = %entry + %0 = load ptr, ptr @a, align 8 + %1 = load ptr, ptr @b, align 8 + %2 = load ptr, ptr %1, align 8 + %cmp352 = icmp slt i32 %L1, %L2 + %cmp750 = icmp slt i32 %K1, %K2 + %3 = sext i32 %K1 to i64 + %4 = sext i32 %L1 to i64 + br label %for.body + +for.cond.cleanup: ; preds = %for.cond.cleanup4, %entry + ret void + +for.body: ; preds = %for.cond.cleanup4, %for.body.lr.ph + br i1 %cmp352, label %for.cond6.preheader.preheader, label %for.cond.cleanup4 + +for.cond6.preheader.preheader: ; preds = %for.body + %wide.trip.count66 = sext i32 %L2 to i64 + br label %for.cond6.preheader + +for.cond6.preheader: ; preds = %for.cond.cleanup8, %for.cond6.preheader.preheader + %indvars.iv61 = phi i64 [ %4, %for.cond6.preheader.preheader ], [ %indvars.iv.next62, %for.cond.cleanup8 ] + br i1 %cmp750, label %for.cond10.preheader.lr.ph, label %for.cond.cleanup8 + +for.cond10.preheader.lr.ph: ; preds = %for.cond6.preheader + %5 = mul nsw i64 %indvars.iv61, 516 + %6 = mul nsw i64 %indvars.iv61, 516 + %wide.trip.count = sext i32 %K2 to i64 + br label %for.cond10.preheader + +for.cond.cleanup4: ; preds = %for.cond.cleanup8, %for.body + %j.0.j.0.j.0.45 = load volatile i32, ptr %j, align 4 + %inc34 = add nsw i32 %j.0.j.0.j.0.45, 1 + store volatile i32 %inc34, ptr %j, align 4 + %j.0.j.0.j.0. = load volatile i32, ptr %j, align 4 + %cmp = icmp slt i32 %j.0.j.0.j.0., %J + br i1 %cmp, label %for.body, label %for.cond.cleanup + +for.cond10.preheader: ; preds = %for.cond.cleanup12, %for.cond10.preheader.lr.ph + %indvars.iv = phi i64 [ %3, %for.cond10.preheader.lr.ph ], [ %indvars.iv.next, %for.cond.cleanup12 ] + %7 = getelementptr float, ptr %0, i64 %indvars.iv + %arrayidx18 = getelementptr float, ptr %7, i64 %5 + %8 = load float, ptr %arrayidx18, align 4 + br label %for.cond14.preheader + +for.cond.cleanup8: ; preds = %for.cond.cleanup12, %for.cond6.preheader + %indvars.iv.next62 = add nsw i64 %indvars.iv61, 1 + %exitcond67.not = icmp eq i64 %indvars.iv.next62, %wide.trip.count66 + br i1 %exitcond67.not, label %for.cond.cleanup4, label %for.cond6.preheader + +for.cond14.preheader: ; preds = %for.cond.cleanup16, %for.cond10.preheader + %m.049 = phi i32 [ -2, %for.cond10.preheader ], [ %inc21, %for.cond.cleanup16 ] + %sum.048 = phi float [ 0.000000e+00, %for.cond10.preheader ], [ %add19, %for.cond.cleanup16 ] + br label %for.body17 + +for.cond.cleanup12: ; preds = %for.cond.cleanup16 + %9 = getelementptr float, ptr %2, i64 %indvars.iv + %arrayidx26 = getelementptr float, ptr %9, i64 %6 + store float %add19, ptr %arrayidx26, align 4 + %indvars.iv.next = add nsw i64 %indvars.iv, 1 + %exitcond60.not = icmp eq i64 %indvars.iv.next, %wide.trip.count + br i1 %exitcond60.not, label %for.cond.cleanup8, label %for.cond10.preheader + +for.cond.cleanup16: ; preds = %for.body17 + %inc21 = add nsw i32 %m.049, 1 + %exitcond56.not = icmp eq i32 %inc21, 3 + br i1 %exitcond56.not, label %for.cond.cleanup12, label %for.cond14.preheader + +for.body17: ; preds = %for.body17, %for.cond14.preheader + %n.047 = phi i32 [ -2, %for.cond14.preheader ], [ %inc, %for.body17 ] + %sum.146 = phi float [ %sum.048, %for.cond14.preheader ], [ %add19, %for.body17 ] + %add19 = fadd float %sum.146, %8 + %inc = add nsw i32 %n.047, 1 + %exitcond.not = icmp eq i32 %inc, 3 + br i1 %exitcond.not, label %for.cond.cleanup16, label %for.body17 +} + +; CHECK: Schedule optimizer calculation exceeds ISL quota -- GitLab From de15c5501903a5a52dcae976e40b8b1f6a838911 Mon Sep 17 00:00:00 2001 From: Craig Hesling Date: Mon, 8 Jan 2024 12:54:12 -0500 Subject: [PATCH 090/652] Revert "[GitHub] Fix slow sccache install on macOS by upgrading macOS version (#77165)" (#77270) This reverts commit 602c8fa2d8da6562e4f36df3bd63c26a4c7461e7, due to an sccache issue seen on larger builds using macOS-12 runners. The issue is documented in in the following issue: https://github.com/hendrikmuhs/ccache-action/issues/174 The original PR is the following: https://github.com/llvm/llvm-project/pull/77165 --- .github/workflows/llvm-project-tests.yml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/.github/workflows/llvm-project-tests.yml b/.github/workflows/llvm-project-tests.yml index 594831ee6b5f..fadaea129e50 100644 --- a/.github/workflows/llvm-project-tests.yml +++ b/.github/workflows/llvm-project-tests.yml @@ -14,7 +14,7 @@ on: required: false os_list: required: false - default: '["ubuntu-latest", "windows-2019", "macOS-12"]' + default: '["ubuntu-latest", "windows-2019", "macOS-11"]' workflow_call: inputs: build_target: @@ -34,7 +34,9 @@ on: type: string # Use windows-2019 due to: # https://developercommunity.visualstudio.com/t/Prev-Issue---with-__assume-isnan-/1597317 - default: '["ubuntu-latest", "windows-2019", "macOS-12"]' + # We're using a specific version of macOS due to: + # https://github.com/actions/virtual-environments/issues/5900 + default: '["ubuntu-latest", "windows-2019", "macOS-11"]' concurrency: # Skip intermediate builds: always. @@ -89,6 +91,10 @@ jobs: variant: sccache - name: Build and Test uses: llvm/actions/build-test-llvm-project@main + env: + # Workaround for https://github.com/actions/virtual-environments/issues/5900. + # This should be a no-op for non-mac OSes + PKG_CONFIG_PATH: /usr/local/Homebrew/Library/Homebrew/os/mac/pkgconfig//12 with: cmake_args: '-GNinja -DLLVM_ENABLE_PROJECTS="${{ inputs.projects }}" -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_ASSERTIONS=ON -DLLDB_INCLUDE_TESTS=OFF -DCMAKE_C_COMPILER_LAUNCHER=sccache -DCMAKE_CXX_COMPILER_LAUNCHER=sccache ${{ inputs.extra_cmake_args }}' build_target: '${{ inputs.build_target }}' -- GitLab From 5351ded68d579921a61b26a34e36046c22f668bd Mon Sep 17 00:00:00 2001 From: Tacet Date: Mon, 8 Jan 2024 18:56:43 +0100 Subject: [PATCH 091/652] [libc++] Remove usage of internal string function in sstream (#75858) This function replaces a call to `__move_assign` (internal function) with two calls to public member functions (`resize` and `erase`). The order of calls is chosen for the best performance. This change is required to [turn on ASan string annotations for short strings](https://github.com/llvm/llvm-project/pull/75882) (Short String Optimization - SSO). The `std::basic_string` class's `void __move_assign(basic_string&& __str, size_type __pos, size_type __len)` function operates on uninitialized strings, where it is reasonable to assume that the memory is not poisoned. However, in `sstream` this function is applied to existing strings that already have poisoned memory. String ASan annotations turned on here: https://github.com/llvm/llvm-project/pull/72677 --- libcxx/include/sstream | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libcxx/include/sstream b/libcxx/include/sstream index bd5cea9a5e94..9f75b7e0ac9e 100644 --- a/libcxx/include/sstream +++ b/libcxx/include/sstream @@ -398,9 +398,9 @@ public: typename string_type::size_type __pos = __view.empty() ? 0 : __view.data() - __str_.data(); // In C++23, this is just string_type(std::move(__str_), __pos, __view.size(), __str_.get_allocator()); // But we need something that works in C++20 also. - string_type __result(__str_.get_allocator()); - __result.__move_assign(std::move(__str_), __pos, __view.size()); - __str_.clear(); + string_type __result(std::move(__str_), __str_.get_allocator()); + __result.resize(__pos + __view.size()); + __result.erase(0, __pos); __init_buf_ptrs(); return __result; } -- GitLab From d460c1de3b989cea919b9d60c21644f28f987950 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Jan 2024 18:01:41 +0000 Subject: [PATCH 092/652] [DAG] SimplifyDemandedBits - don't fold sext(x) -> aext(x) if we lose an 0/-1 allsignbits mask (#77296) For targets that use 0/-1 boolean results, we want to keep this pattern through extensions/truncations as much as possible - so avoid simplifying to any_extend even if we don't demand the upper bits. Noticed in triage for https://reviews.llvm.org/D152928 --- .../CodeGen/SelectionDAG/TargetLowering.cpp | 27 +++++++++++-------- llvm/test/CodeGen/AArch64/arm64-zip.ll | 2 +- llvm/test/CodeGen/AArch64/vselect-ext.ll | 14 +++++----- llvm/test/CodeGen/SystemZ/vec-perm-14.ll | 8 +++--- llvm/test/CodeGen/X86/test-shrink-bug.ll | 4 +-- llvm/test/CodeGen/X86/vec_setcc.ll | 2 +- 6 files changed, 30 insertions(+), 27 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f8400e8e94df..e3e3e375d6a6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2444,6 +2444,13 @@ bool TargetLowering::SimplifyDemandedBits( unsigned InElts = SrcVT.isFixedLengthVector() ? SrcVT.getVectorNumElements() : 1; bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; + APInt InDemandedElts = DemandedElts.zext(InElts); + APInt InDemandedBits = DemandedBits.trunc(InBits); + + // Since some of the sign extended bits are demanded, we know that the sign + // bit is demanded. + InDemandedBits.setBit(InBits - 1); + // If none of the top bits are demanded, convert this into an any_extend. if (DemandedBits.getActiveBits() <= InBits) { // If we only need the non-extended bits of the bottom element @@ -2452,19 +2459,17 @@ bool TargetLowering::SimplifyDemandedBits( VT.getSizeInBits() == SrcVT.getSizeInBits()) return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); - unsigned Opc = - IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; - if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) - return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); + // Don't lose an all signbits 0/-1 splat on targets with 0/-1 booleans. + if (getBooleanContents(VT) != ZeroOrNegativeOneBooleanContent || + TLO.DAG.ComputeNumSignBits(Src, InDemandedElts, Depth + 1) != + InBits) { + unsigned Opc = + IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; + if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) + return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); + } } - APInt InDemandedBits = DemandedBits.trunc(InBits); - APInt InDemandedElts = DemandedElts.zext(InElts); - - // Since some of the sign extended bits are demanded, we know that the sign - // bit is demanded. - InDemandedBits.setBit(InBits - 1); - if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, Depth + 1)) return true; diff --git a/llvm/test/CodeGen/AArch64/arm64-zip.ll b/llvm/test/CodeGen/AArch64/arm64-zip.ll index e22b57c8af44..c6e3c3540f6e 100644 --- a/llvm/test/CodeGen/AArch64/arm64-zip.ll +++ b/llvm/test/CodeGen/AArch64/arm64-zip.ll @@ -328,7 +328,7 @@ define <4 x i32> @shuffle_zip3(<4 x i32> %arg) { ; CHECK-NEXT: zip2.4h v0, v0, v1 ; CHECK-NEXT: movi.4s v1, #1 ; CHECK-NEXT: zip1.4h v0, v0, v0 -; CHECK-NEXT: ushll.4s v0, v0, #0 +; CHECK-NEXT: sshll.4s v0, v0, #0 ; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: ret bb: diff --git a/llvm/test/CodeGen/AArch64/vselect-ext.ll b/llvm/test/CodeGen/AArch64/vselect-ext.ll index b80955665c74..0b90343a40c8 100644 --- a/llvm/test/CodeGen/AArch64/vselect-ext.ll +++ b/llvm/test/CodeGen/AArch64/vselect-ext.ll @@ -219,17 +219,17 @@ define <3 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v3i16(<3 x i8> ; CHECK-NEXT: fmov s0, w0 ; CHECK-NEXT: Lloh0: ; CHECK-NEXT: adrp x8, lCPI9_0@PAGE +; CHECK-NEXT: movi.2d v3, #0x0000ff000000ff ; CHECK-NEXT: Lloh1: ; CHECK-NEXT: ldr d2, [x8, lCPI9_0@PAGEOFF] ; CHECK-NEXT: mov.h v0[1], w1 ; CHECK-NEXT: mov.h v0[2], w2 -; CHECK-NEXT: fmov d1, d0 -; CHECK-NEXT: bic.4h v1, #255, lsl #8 -; CHECK-NEXT: cmhi.4h v1, v1, v2 -; CHECK-NEXT: and.8b v0, v0, v1 -; CHECK-NEXT: movi.2d v1, #0x0000ff000000ff -; CHECK-NEXT: ushll.4s v0, v0, #0 -; CHECK-NEXT: and.16b v0, v0, v1 +; CHECK-NEXT: ushll.4s v1, v0, #0 +; CHECK-NEXT: bic.4h v0, #255, lsl #8 +; CHECK-NEXT: cmhi.4h v0, v0, v2 +; CHECK-NEXT: and.16b v1, v1, v3 +; CHECK-NEXT: sshll.4s v0, v0, #0 +; CHECK-NEXT: and.16b v0, v1, v0 ; CHECK-NEXT: ret ; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1 %ext = zext <3 x i8> %a to <3 x i32> diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-14.ll b/llvm/test/CodeGen/SystemZ/vec-perm-14.ll index fb3ece96017b..0b392676fa3e 100644 --- a/llvm/test/CodeGen/SystemZ/vec-perm-14.ll +++ b/llvm/test/CodeGen/SystemZ/vec-perm-14.ll @@ -1,16 +1,14 @@ ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -; -; Test that only one vperm of the vector compare is needed for both extracts. +; Test that no vperm of the vector compare is needed for the extracts. define void @fun() { ; CHECK-LABEL: fun: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: vlrepf %v0, 0(%r1) ; CHECK-NEXT: vgbm %v1, 0 -; CHECK-NEXT: larl %r1, .LCPI0_0 ; CHECK-NEXT: vceqb %v0, %v0, %v1 -; CHECK-NEXT: vl %v1, 0(%r1), 3 -; CHECK-NEXT: vperm %v0, %v0, %v0, %v1 +; CHECK-NEXT: vuphb %v0, %v0 +; CHECK-NEXT: vuphh %v0, %v0 ; CHECK-NEXT: vlgvf %r0, %v0, 0 ; CHECK-NEXT: tmll %r0, 1 ; CHECK-NEXT: je .LBB0_2 diff --git a/llvm/test/CodeGen/X86/test-shrink-bug.ll b/llvm/test/CodeGen/X86/test-shrink-bug.ll index f05459f751bc..51a00d211421 100644 --- a/llvm/test/CodeGen/X86/test-shrink-bug.ll +++ b/llvm/test/CodeGen/X86/test-shrink-bug.ll @@ -68,8 +68,8 @@ define dso_local void @fail(i16 %a, <2 x i8> %b) { ; CHECK-X64-NEXT: je .LBB1_3 ; CHECK-X64-NEXT: # %bb.1: ; CHECK-X64-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; CHECK-X64-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8] -; CHECK-X64-NEXT: pextrw $4, %xmm0, %eax +; CHECK-X64-NEXT: pslld $8, %xmm0 +; CHECK-X64-NEXT: pextrw $1, %xmm0, %eax ; CHECK-X64-NEXT: testb $1, %al ; CHECK-X64-NEXT: jne .LBB1_3 ; CHECK-X64-NEXT: # %bb.2: # %no diff --git a/llvm/test/CodeGen/X86/vec_setcc.ll b/llvm/test/CodeGen/X86/vec_setcc.ll index e7232a34f471..87e29261eaa4 100644 --- a/llvm/test/CodeGen/X86/vec_setcc.ll +++ b/llvm/test/CodeGen/X86/vec_setcc.ll @@ -308,9 +308,9 @@ define <3 x i1> @test_setcc_v3i1_v3i16(ptr %a) nounwind { ; SSE2-LABEL: test_setcc_v3i1_v3i16: ; SSE2: # %bb.0: ; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqw %xmm0, %xmm1 -; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3] ; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx -- GitLab From 4c66180e46eaed0cd6aa37102a1e3b37cc9d85fa Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 8 Jan 2024 09:54:40 -0800 Subject: [PATCH 093/652] [RISCV] Use COPY to create artificial 64-bit uses in RISCVOptWInstrs's tests In reflection of 4dd5d967975fa8d52b8c60596d892d9dd5615809, we can now use COPY to physical registers to create artificial 64-bit uses to prevent RISCVOptWInstrs from optimizing away sext in absent of the IsSignExtendingOpW flag. NFCI. --- llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir index ebac5a42fbcd..3d25a17a9f7e 100644 --- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir +++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir @@ -6,26 +6,20 @@ name: fcvtmod_w_d tracksRegLiveness: true body: | bb.0.entry: - liveins: $x10, $x11 + liveins: $x10 ; CHECK-ZFA-LABEL: name: fcvtmod_w_d - ; CHECK-ZFA: liveins: $x10, $x11 + ; CHECK-ZFA: liveins: $x10 ; CHECK-ZFA-NEXT: {{ $}} ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10 - ; CHECK-ZFA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-ZFA-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1 - ; CHECK-ZFA-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[FCVTMOD_W_D]] - ; CHECK-ZFA-NEXT: $x10 = COPY [[ADD]] - ; CHECK-ZFA-NEXT: $x11 = COPY [[FCVTMOD_W_D]] + ; CHECK-ZFA-NEXT: $x10 = COPY [[FCVTMOD_W_D]] ; CHECK-ZFA-NEXT: PseudoRET %0:fpr64 = COPY $x10 - %1:gpr = COPY $x11 - %2:gpr = nofpexcept FCVTMOD_W_D %0, 1 - %3:gpr = ADD %1, %2 - %4:gpr = ADDIW %2, 0 - $x10 = COPY %3 - $x11 = COPY %4 + %1:gpr = nofpexcept FCVTMOD_W_D %0, 1 + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 PseudoRET ... -- GitLab From c1023c585de2629911a529cdf32490b99df83345 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 10:18:36 -0800 Subject: [PATCH 094/652] [libc] fix -Wmissing-braces (#77345) Fixes the following errors observed on the aarch64 fullbuild: /home/libc-buildbot/libc-aarch64-ubuntu/libc-aarch64-ubuntu-fullbuild-dbg/llvm-project/libc/src/__support/HashTable/generic/bitmask_impl.inc:116:13: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] return {static_cast(mask_available().word ^ repeat_byte(0x80))}; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { } In file included from /home/libc-buildbot/libc-aarch64-ubuntu/libc-aarch64-ubuntu-fullbuild-dbg/llvm-project/libc/src/search/hdestroy.cpp:10: /home/libc-buildbot/libc-aarch64-ubuntu/libc-aarch64-ubuntu-fullbuild-dbg/llvm-project/libc/src/__support/HashTable/table.h:336:41: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] iterator end() const { return {0, 0, {0}, *this}; } ^ {} Link: https://lab.llvm.org/buildbot/#/builders/223/builds/33868/steps/6/logs/stdio Link: https://github.com/llvm/llvm-project/pull/74506 --- libc/src/__support/HashTable/generic/bitmask_impl.inc | 3 ++- libc/src/__support/HashTable/table.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/libc/src/__support/HashTable/generic/bitmask_impl.inc b/libc/src/__support/HashTable/generic/bitmask_impl.inc index b825cb5fbc44..56b540d568d0 100644 --- a/libc/src/__support/HashTable/generic/bitmask_impl.inc +++ b/libc/src/__support/HashTable/generic/bitmask_impl.inc @@ -113,7 +113,8 @@ struct Group { } LIBC_INLINE IteratableBitMask occupied() const { - return {static_cast(mask_available().word ^ repeat_byte(0x80))}; + return { + {static_cast(mask_available().word ^ repeat_byte(0x80))}}; } }; } // namespace internal diff --git a/libc/src/__support/HashTable/table.h b/libc/src/__support/HashTable/table.h index d70ca4d23380..288829b1cac9 100644 --- a/libc/src/__support/HashTable/table.h +++ b/libc/src/__support/HashTable/table.h @@ -333,7 +333,7 @@ public: return {0, full_capacity() - available_slots, Group::load_aligned(&control(0)).occupied(), *this}; } - iterator end() const { return {0, 0, {0}, *this}; } + iterator end() const { return {0, 0, {BitMask{0}}, *this}; } LIBC_INLINE ENTRY *find(const char *key) { uint64_t primary = oneshot_hash(key); -- GitLab From eb42868f25665ba6301a94a30e9df33e0d6ae61f Mon Sep 17 00:00:00 2001 From: Billy Zhu Date: Mon, 8 Jan 2024 10:29:32 -0800 Subject: [PATCH 095/652] [MLIR] Handle materializeConstant failure in GreedyPatternRewriteDriver (#77258) Make GreedyPatternRewriteDriver handle failures of `materializeConstant` gracefully. Previously it was not checking whether the returned op was null and crashing. This PR handles it similarly to how OperationFolder does it. --- .../Utils/GreedyPatternRewriteDriver.cpp | 34 ++++++++++++++++--- mlir/test/Transforms/canonicalize.mlir | 11 ++++++ 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp b/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp index 82438e2bf706..67c2d9d59f4c 100644 --- a/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp +++ b/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp @@ -434,10 +434,10 @@ bool GreedyPatternRewriteDriver::processWorklist() { SmallVector foldResults; if (succeeded(op->fold(foldResults))) { LLVM_DEBUG(logResultWithLine("success", "operation was folded")); - changed = true; if (foldResults.empty()) { // Op was modified in-place. notifyOperationModified(op); + changed = true; #if MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS if (config.scope && failed(verify(config.scope->getParentOp()))) llvm::report_fatal_error("IR failed to verify after folding"); @@ -451,6 +451,7 @@ bool GreedyPatternRewriteDriver::processWorklist() { OpBuilder::InsertionGuard g(*this); setInsertionPoint(op); SmallVector replacements; + bool materializationSucceeded = true; for (auto [ofr, resultType] : llvm::zip_equal(foldResults, op->getResultTypes())) { if (auto value = ofr.dyn_cast()) { @@ -462,18 +463,41 @@ bool GreedyPatternRewriteDriver::processWorklist() { // Materialize Attributes as SSA values. Operation *constOp = op->getDialect()->materializeConstant( *this, ofr.get(), resultType, op->getLoc()); + + if (!constOp) { + // If materialization fails, cleanup any operations generated for + // the previous results. + llvm::SmallDenseSet replacementOps; + for (Value replacement : replacements) { + assert(replacement.use_empty() && + "folder reused existing op for one result but constant " + "materialization failed for another result"); + replacementOps.insert(replacement.getDefiningOp()); + } + for (Operation *op : replacementOps) { + eraseOp(op); + } + + materializationSucceeded = false; + break; + } + assert(constOp->hasTrait() && "materializeConstant produced op that is not a ConstantLike"); assert(constOp->getResultTypes()[0] == resultType && "materializeConstant produced incorrect result type"); replacements.push_back(constOp->getResult(0)); } - replaceOp(op, replacements); + + if (materializationSucceeded) { + replaceOp(op, replacements); + changed = true; #if MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS - if (config.scope && failed(verify(config.scope->getParentOp()))) - llvm::report_fatal_error("IR failed to verify after folding"); + if (config.scope && failed(verify(config.scope->getParentOp()))) + llvm::report_fatal_error("IR failed to verify after folding"); #endif // MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS - continue; + continue; + } } } diff --git a/mlir/test/Transforms/canonicalize.mlir b/mlir/test/Transforms/canonicalize.mlir index 47a19bb598c2..9b578e6c2631 100644 --- a/mlir/test/Transforms/canonicalize.mlir +++ b/mlir/test/Transforms/canonicalize.mlir @@ -1224,3 +1224,14 @@ func.func @clone_nested_region(%arg0: index, %arg1: index, %arg2: index) -> memr // CHECK-NEXT: scf.yield %[[ALLOC3_2]] // CHECK: memref.dealloc %[[ALLOC1]] // CHECK-NEXT: return %[[ALLOC2]] + +// ----- + +// CHECK-LABEL: func @test_materialize_failure +func.func @test_materialize_failure() -> i64 { + %const = index.constant 1234 + // Cannot materialize this castu's output constant. + // CHECK: index.castu + %u = index.castu %const : index to i64 + return %u: i64 +} -- GitLab From 07d6fbf8d80083470b4371f2ddabd656a9c317e6 Mon Sep 17 00:00:00 2001 From: Alex Langford Date: Mon, 8 Jan 2024 10:51:00 -0800 Subject: [PATCH 096/652] [lldb][NFCI] Remove BreakpointIDList::InsertStringArray (#77161) This abstraction is leaky and BreakpointIDList does not need to know about CommandReturnObject. Additionally, setting the CommandReturnObject inout param to a success state does very little. The function returns immediately if the input ArrayRef is empty, and reading CommandObjectMultiwordBreakpoint::VerifyIDs more closely, the input is always empty if the previous call to BreakpointIDList::FindAndReplaceIDRanges failed. If the call was successful, then the CommandReturnObject is already in a success state. I have opted to remove the function altogether and inline the functionality where it was used. --- lldb/include/lldb/Breakpoint/BreakpointIDList.h | 3 --- lldb/source/Breakpoint/BreakpointIDList.cpp | 13 ------------- lldb/source/Commands/CommandObjectBreakpoint.cpp | 4 +++- 3 files changed, 3 insertions(+), 17 deletions(-) diff --git a/lldb/include/lldb/Breakpoint/BreakpointIDList.h b/lldb/include/lldb/Breakpoint/BreakpointIDList.h index 924cb1f26b8b..161d1a2d314e 100644 --- a/lldb/include/lldb/Breakpoint/BreakpointIDList.h +++ b/lldb/include/lldb/Breakpoint/BreakpointIDList.h @@ -48,9 +48,6 @@ public: bool FindBreakpointID(const char *bp_id, size_t *position) const; - void InsertStringArray(llvm::ArrayRef string_array, - CommandReturnObject &result); - // Returns a pair consisting of the beginning and end of a breakpoint // ID range expression. If the input string is not a valid specification, // returns an empty pair. diff --git a/lldb/source/Breakpoint/BreakpointIDList.cpp b/lldb/source/Breakpoint/BreakpointIDList.cpp index dd16d3b6388c..c4fdbc370b22 100644 --- a/lldb/source/Breakpoint/BreakpointIDList.cpp +++ b/lldb/source/Breakpoint/BreakpointIDList.cpp @@ -82,19 +82,6 @@ bool BreakpointIDList::FindBreakpointID(const char *bp_id_str, return FindBreakpointID(*bp_id, position); } -void BreakpointIDList::InsertStringArray( - llvm::ArrayRef string_array, CommandReturnObject &result) { - if(string_array.empty()) - return; - - for (const char *str : string_array) { - auto bp_id = BreakpointID::ParseCanonicalReference(str); - if (bp_id) - m_breakpoint_ids.push_back(*bp_id); - } - result.SetStatus(eReturnStatusSuccessFinishNoResult); -} - // This function takes OLD_ARGS, which is usually the result of breaking the // command string arguments into // an array of space-separated strings, and searches through the arguments for diff --git a/lldb/source/Commands/CommandObjectBreakpoint.cpp b/lldb/source/Commands/CommandObjectBreakpoint.cpp index 63492590d32d..f9ba68eda3ff 100644 --- a/lldb/source/Commands/CommandObjectBreakpoint.cpp +++ b/lldb/source/Commands/CommandObjectBreakpoint.cpp @@ -2494,7 +2494,9 @@ void CommandObjectMultiwordBreakpoint::VerifyIDs( // NOW, convert the list of breakpoint id strings in TEMP_ARGS into an actual // BreakpointIDList: - valid_ids->InsertStringArray(temp_args.GetArgumentArrayRef(), result); + for (llvm::StringRef temp_arg : temp_args.GetArgumentArrayRef()) + if (auto bp_id = BreakpointID::ParseCanonicalReference(temp_arg)) + valid_ids->AddBreakpointID(*bp_id); // At this point, all of the breakpoint ids that the user passed in have // been converted to breakpoint IDs and put into valid_ids. -- GitLab From 5cbf74b012c10e9cc841a27cd5d7335e556f47dd Mon Sep 17 00:00:00 2001 From: Alex Langford Date: Mon, 8 Jan 2024 10:52:00 -0800 Subject: [PATCH 097/652] [lldb][NFCI] Change return type of BreakpointIDList::GetBreakpointIDAtIndex (#77166) There are 2 motivations here: 1.) There is no need to hand out constant references to BreakpointIDs, they are only 8 bytes big. In addition, every use of this method already makes a copy anyway. 2.) Each BreakpointIDList held onto an invalid BreakpointID specifically to prevent lifetime issues. Returning a value means you can return an invalid BreakpointID instead of needing to allocate storage for an invalid BreakpointID. --- lldb/include/lldb/Breakpoint/BreakpointIDList.h | 3 +-- lldb/source/Breakpoint/BreakpointIDList.cpp | 8 +++----- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/lldb/include/lldb/Breakpoint/BreakpointIDList.h b/lldb/include/lldb/Breakpoint/BreakpointIDList.h index 161d1a2d314e..6910024695d8 100644 --- a/lldb/include/lldb/Breakpoint/BreakpointIDList.h +++ b/lldb/include/lldb/Breakpoint/BreakpointIDList.h @@ -33,7 +33,7 @@ public: size_t GetSize() const; - const BreakpointID &GetBreakpointIDAtIndex(size_t index) const; + BreakpointID GetBreakpointIDAtIndex(size_t index) const; bool RemoveBreakpointIDAtIndex(size_t index); @@ -63,7 +63,6 @@ public: private: BreakpointIDArray m_breakpoint_ids; - BreakpointID m_invalid_id; BreakpointIDList(const BreakpointIDList &) = delete; const BreakpointIDList &operator=(const BreakpointIDList &) = delete; diff --git a/lldb/source/Breakpoint/BreakpointIDList.cpp b/lldb/source/Breakpoint/BreakpointIDList.cpp index c4fdbc370b22..05c461827cad 100644 --- a/lldb/source/Breakpoint/BreakpointIDList.cpp +++ b/lldb/source/Breakpoint/BreakpointIDList.cpp @@ -20,17 +20,15 @@ using namespace lldb_private; // class BreakpointIDList -BreakpointIDList::BreakpointIDList() - : m_invalid_id(LLDB_INVALID_BREAK_ID, LLDB_INVALID_BREAK_ID) {} +BreakpointIDList::BreakpointIDList() : m_breakpoint_ids() {} BreakpointIDList::~BreakpointIDList() = default; size_t BreakpointIDList::GetSize() const { return m_breakpoint_ids.size(); } -const BreakpointID & -BreakpointIDList::GetBreakpointIDAtIndex(size_t index) const { +BreakpointID BreakpointIDList::GetBreakpointIDAtIndex(size_t index) const { return ((index < m_breakpoint_ids.size()) ? m_breakpoint_ids[index] - : m_invalid_id); + : BreakpointID()); } bool BreakpointIDList::RemoveBreakpointIDAtIndex(size_t index) { -- GitLab From 478ec63312582c24c8d6ecab280da2380137c0b7 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 8 Jan 2024 10:59:06 -0800 Subject: [PATCH 098/652] [RISCV] Mark VFIRST and VCPOP as SignExtendingOpW (#77022) Since their values are small enough ([-1, 65535] & [0, 65535], respectively) to fit into signed 32 bits, any sext (or downcasting + sext) will be redundnat. Hence marking them as SignExtendingOpW. --- .../Target/RISCV/RISCVInstrInfoVPseudos.td | 2 + llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 76 +++++++++++++++---- 2 files changed, 63 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 30deeaa06448..fcb18b67623e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -6719,12 +6719,14 @@ defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">; // 15.2. Vector mask population count vcpop //===----------------------------------------------------------------------===// +let IsSignExtendingOpW = 1 in defm PseudoVCPOP: VPseudoVPOP_M; //===----------------------------------------------------------------------===// // 15.3. vfirst find-first-set mask bit //===----------------------------------------------------------------------===// +let IsSignExtendingOpW = 1 in defm PseudoVFIRST: VPseudoV1ST_M; //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir index 3d25a17a9f7e..8c22eaf917e8 100644 --- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir +++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 -# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s --check-prefix=CHECK-ZFA +# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s --- name: fcvtmod_w_d @@ -8,13 +8,13 @@ body: | bb.0.entry: liveins: $x10 - ; CHECK-ZFA-LABEL: name: fcvtmod_w_d - ; CHECK-ZFA: liveins: $x10 - ; CHECK-ZFA-NEXT: {{ $}} - ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10 - ; CHECK-ZFA-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1 - ; CHECK-ZFA-NEXT: $x10 = COPY [[FCVTMOD_W_D]] - ; CHECK-ZFA-NEXT: PseudoRET + ; CHECK-LABEL: name: fcvtmod_w_d + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10 + ; CHECK-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVTMOD_W_D]] + ; CHECK-NEXT: PseudoRET %0:fpr64 = COPY $x10 %1:gpr = nofpexcept FCVTMOD_W_D %0, 1 @@ -30,15 +30,61 @@ body: | bb.0.entry: liveins: $x10, $x11 - ; CHECK-ZFA-LABEL: name: physreg - ; CHECK-ZFA: liveins: $x10, $x11 - ; CHECK-ZFA-NEXT: {{ $}} - ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 - ; CHECK-ZFA-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0 - ; CHECK-ZFA-NEXT: $x10 = COPY [[ADDIW]] - ; CHECK-ZFA-NEXT: PseudoRET + ; CHECK-LABEL: name: physreg + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET %0:gpr = COPY $x10 %1:gpr = ADDIW %0, 0 $x10 = COPY %1 PseudoRET ... +--- + name: vfirst + tracksRegLiveness: true + body: | + bb.0.entry: + liveins: $x10, $v8 + + ; CHECK-LABEL: name: vfirst + ; CHECK: liveins: $x10, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */ + ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]] + ; CHECK-NEXT: PseudoRET + %0:vr = COPY $v8 + %1:gprnox0 = COPY $x10 + + %2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0 + %3:gpr = ADDIW %2, 0 + $x11 = COPY %3 + PseudoRET +... +--- + name: vcpop + tracksRegLiveness: true + body: | + bb.0.entry: + liveins: $x10, $v8 + + ; CHECK-LABEL: name: vcpop + ; CHECK: liveins: $x10, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */ + ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]] + ; CHECK-NEXT: PseudoRET + %0:vr = COPY $v8 + %1:gprnox0 = COPY $x10 + + %2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0 + %3:gpr = ADDIW %2, 0 + $x11 = COPY %3 + PseudoRET +... -- GitLab From f4bc70e886f2eb1b646d84871b93897db749c826 Mon Sep 17 00:00:00 2001 From: Juergen Ributzka Date: Mon, 8 Jan 2024 11:04:22 -0800 Subject: [PATCH 099/652] [clang][modules] Remove `_Private` suffix from framework auto-link hints. (#77120) - [clang][modules] Remove no longer needed autolink test for TBD files. - [clang][modules] Remove `_Private` suffix from framework auto-link hints. --- clang/lib/Lex/ModuleMap.cpp | 4 ++- .../AutolinkTBD.framework/AutolinkTBD.tbd | 1 - .../Headers/AutolinkTBD.h | 1 - clang/test/Modules/autolinkTBD.m | 16 ------------ clang/test/Modules/autolink_private_module.m | 25 +++++++++++++++++++ 5 files changed, 28 insertions(+), 19 deletions(-) delete mode 100644 clang/test/Modules/Inputs/AutolinkTBD.framework/AutolinkTBD.tbd delete mode 100644 clang/test/Modules/Inputs/AutolinkTBD.framework/Headers/AutolinkTBD.h delete mode 100644 clang/test/Modules/autolinkTBD.m create mode 100644 clang/test/Modules/autolink_private_module.m diff --git a/clang/lib/Lex/ModuleMap.cpp b/clang/lib/Lex/ModuleMap.cpp index ea5d13deb114..42d55d09ea5a 100644 --- a/clang/lib/Lex/ModuleMap.cpp +++ b/clang/lib/Lex/ModuleMap.cpp @@ -984,7 +984,9 @@ static void inferFrameworkLink(Module *Mod) { assert(!Mod->isSubFramework() && "Can only infer linking for top-level frameworks"); - Mod->LinkLibraries.push_back(Module::LinkLibrary(Mod->Name, + StringRef FrameworkName(Mod->Name); + FrameworkName.consume_back("_Private"); + Mod->LinkLibraries.push_back(Module::LinkLibrary(FrameworkName.str(), /*IsFramework=*/true)); } diff --git a/clang/test/Modules/Inputs/AutolinkTBD.framework/AutolinkTBD.tbd b/clang/test/Modules/Inputs/AutolinkTBD.framework/AutolinkTBD.tbd deleted file mode 100644 index 4aa0f85d0d56..000000000000 --- a/clang/test/Modules/Inputs/AutolinkTBD.framework/AutolinkTBD.tbd +++ /dev/null @@ -1 +0,0 @@ -empty file - clang only needs to check if it exists. diff --git a/clang/test/Modules/Inputs/AutolinkTBD.framework/Headers/AutolinkTBD.h b/clang/test/Modules/Inputs/AutolinkTBD.framework/Headers/AutolinkTBD.h deleted file mode 100644 index 914983c49636..000000000000 --- a/clang/test/Modules/Inputs/AutolinkTBD.framework/Headers/AutolinkTBD.h +++ /dev/null @@ -1 +0,0 @@ -extern int foo(void); diff --git a/clang/test/Modules/autolinkTBD.m b/clang/test/Modules/autolinkTBD.m deleted file mode 100644 index 69253294f7b8..000000000000 --- a/clang/test/Modules/autolinkTBD.m +++ /dev/null @@ -1,16 +0,0 @@ -// UNSUPPORTED: target={{.*}}-zos{{.*}}, target={{.*}}-aix{{.*}} -// RUN: rm -rf %t -// RUN: %clang_cc1 -emit-llvm -o - -fmodules-cache-path=%t -fmodules -fimplicit-module-maps -F %S/Inputs %s | FileCheck %s -// RUN: %clang_cc1 -emit-llvm -fno-autolink -o - -fmodules-cache-path=%t -fmodules -fimplicit-module-maps -F %S/Inputs %s | FileCheck --check-prefix=CHECK-AUTOLINK-DISABLED %s - -@import AutolinkTBD; - -int f(void) { - return foo(); -} - -// CHECK: !llvm.linker.options = !{![[AUTOLINK_FRAMEWORK:[0-9]+]]} -// CHECK: ![[AUTOLINK_FRAMEWORK]] = !{!"-framework", !"AutolinkTBD"} - -// CHECK-AUTOLINK-DISABLED: !llvm.module.flags -// CHECK-AUTOLINK-DISABLED-NOT: !llvm.linker.options diff --git a/clang/test/Modules/autolink_private_module.m b/clang/test/Modules/autolink_private_module.m new file mode 100644 index 000000000000..54bebc3a587b --- /dev/null +++ b/clang/test/Modules/autolink_private_module.m @@ -0,0 +1,25 @@ +// Test that autolink hints for frameworks don't use the private module name. +// RUN: rm -rf %t && mkdir %t +// RUN: split-file %s %t + +// RUN: %clang_cc1 -emit-llvm -o - -fmodules-cache-path=%t/ModuleCache -fmodules -fimplicit-module-maps -F %t/Frameworks %t/test.m | FileCheck %s + +// CHECK: !{!"-framework", !"Autolink"} +// CHECK-NOT: !{!"-framework", !"Autolink_Private"} + +//--- test.m +#include +#include + +//--- Frameworks/Autolink.framework/Headers/Autolink.h +void public(); + +//--- Frameworks/Autolink.framework/PrivateHeaders/Autolink_Private.h +void private(); + +//--- Frameworks/Autolink.framework/Modules/module.modulemap +framework module Autolink { header "Autolink.h"} + +//--- Frameworks/Autolink.framework/Modules/module.private.modulemap +framework module Autolink_Private { header "Autolink_Private.h"} + -- GitLab From 23e03a85dc665c784c8b77d429f0f0e2e6d0c2fe Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 8 Jan 2024 11:04:00 -0800 Subject: [PATCH 100/652] [BOLT] Update test case after #77253 PR #77253 removed the '@plt' suffix from callee symbols. Update RISCV/relax.s accordingly. --- bolt/test/RISCV/relax.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bolt/test/RISCV/relax.s b/bolt/test/RISCV/relax.s index bf9287e1d0d8..ec390ea76b5c 100644 --- a/bolt/test/RISCV/relax.s +++ b/bolt/test/RISCV/relax.s @@ -6,7 +6,7 @@ // CHECK: Binary Function "_start" after building cfg { // CHECK: jal ra, near_f -// CHECK-NEXT: auipc ra, far_f@plt +// CHECK-NEXT: auipc ra, far_f // CHECK-NEXT: jalr ra, 0xc(ra) // CHECK-NEXT: j near_f -- GitLab From daa4728deed3d222ff163cfb963321938549ddf1 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 8 Jan 2024 19:13:38 +0000 Subject: [PATCH 101/652] [AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825) --- llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 9 +- .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 24 +- .../AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 34 + .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 150 +++- .../Target/AMDGPU/AMDGPURegisterBankInfo.h | 3 + llvm/lib/Target/AMDGPU/GCNSubtarget.h | 2 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 66 +- llvm/lib/Target/AMDGPU/SIISelLowering.h | 1 + llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 194 ++++ llvm/lib/Target/AMDGPU/SIInstrInfo.h | 6 + llvm/lib/Target/AMDGPU/SIInstructions.td | 12 + llvm/lib/Target/AMDGPU/SOPInstructions.td | 10 + .../AMDGPU/GlobalISel/legalize-mul.mir | 787 +++++++---------- llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 819 +++++++++++++++++ .../GlobalISel/postlegalizercombiner-mul.mir | 60 ++ .../AMDGPU/GlobalISel/regbankselect-mul.mir | 122 +++ .../atomic_optimizations_global_pointer.ll | 130 ++- llvm/test/CodeGen/AMDGPU/mul.ll | 831 ++++++++++++++++-- 18 files changed, 2632 insertions(+), 628 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td index 8d4cad4c07bc..0c77fe725958 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -104,6 +104,13 @@ def foldable_fneg : GICombineRule< [{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]), (apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>; +// Detects s_mul_u64 instructions whose higher bits are zero/sign extended. +def smulu64 : GICombineRule< + (defs root:$smul, unsigned_matchinfo:$matchinfo), + (match (wip_match_opcode G_MUL):$smul, + [{ return matchCombine_s_mul_u64(*${smul}, ${matchinfo}); }]), + (apply [{ applyCombine_s_mul_u64(*${smul}, ${matchinfo}); }])>; + def sign_exension_in_reg_matchdata : GIDefMatchData<"MachineInstr *">; def sign_extension_in_reg : GICombineRule< @@ -149,7 +156,7 @@ def AMDGPUPostLegalizerCombiner: GICombiner< "AMDGPUPostLegalizerCombinerImpl", [all_combines, gfx6gfx7_combines, gfx8_combines, uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg, - rcp_sqrt_to_rsq, sign_extension_in_reg]> { + rcp_sqrt_to_rsq, sign_extension_in_reg, smulu64]> { let CombineAllMethodName = "tryCombineAllImpl"; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index dfbe5c7fed88..aa235c07e995 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -701,13 +701,23 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, .maxScalar(0, S32); } - getActionDefinitionsBuilder(G_MUL) - .legalFor({S32, S16, V2S16}) - .clampMaxNumElementsStrict(0, S16, 2) - .scalarize(0) - .minScalar(0, S16) - .widenScalarToNextMultipleOf(0, 32) - .custom(); + if (ST.hasScalarSMulU64()) { + getActionDefinitionsBuilder(G_MUL) + .legalFor({S64, S32, S16, V2S16}) + .clampMaxNumElementsStrict(0, S16, 2) + .scalarize(0) + .minScalar(0, S16) + .widenScalarToNextMultipleOf(0, 32) + .custom(); + } else { + getActionDefinitionsBuilder(G_MUL) + .legalFor({S32, S16, V2S16}) + .clampMaxNumElementsStrict(0, S16, 2) + .scalarize(0) + .minScalar(0, S16) + .widenScalarToNextMultipleOf(0, 32) + .custom(); + } assert(ST.hasMad64_32()); getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT, G_SADDSAT, G_SSUBSAT}) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp index 7b18e1f805d8..21bfab52c6c4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -104,6 +104,14 @@ public: void applyCombineSignExtendInReg(MachineInstr &MI, MachineInstr *&MatchInfo) const; + // Find the s_mul_u64 instructions where the higher bits are either + // zero-extended or sign-extended. + bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const; + // Replace the s_mul_u64 instructions with S_MUL_I64_I32_PSEUDO if the higher + // 33 bits are sign extended and with S_MUL_U64_U32_PSEUDO if the higher 32 + // bits are zero extended. + void applyCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const; + private: #define GET_GICOMBINER_CLASS_MEMBERS #define AMDGPUSubtarget GCNSubtarget @@ -419,6 +427,32 @@ void AMDGPUPostLegalizerCombinerImpl::applyCombineSignExtendInReg( MI.eraseFromParent(); } +bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64( + MachineInstr &MI, unsigned &NewOpcode) const { + Register Src0 = MI.getOperand(1).getReg(); + Register Src1 = MI.getOperand(2).getReg(); + if (MRI.getType(Src0) != LLT::scalar(64)) + return false; + + if (KB->getKnownBits(Src1).countMinLeadingZeros() >= 32 && + KB->getKnownBits(Src0).countMinLeadingZeros() >= 32) { + NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32; + return true; + } + + if (KB->computeNumSignBits(Src1) >= 33 && + KB->computeNumSignBits(Src0) >= 33) { + NewOpcode = AMDGPU::G_AMDGPU_S_MUL_I64_I32; + return true; + } + return false; +} + +void AMDGPUPostLegalizerCombinerImpl::applyCombine_s_mul_u64( + MachineInstr &MI, unsigned &NewOpcode) const { + Helper.replaceOpcodeWith(MI, NewOpcode); +} + // Pass boilerplate // ================ diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 92182ec06942..ecb7bb9d1d97 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -2094,6 +2094,74 @@ bool AMDGPURegisterBankInfo::foldInsertEltToCmpSelect( return true; } +// Break s_mul_u64 into 32-bit vector operations. +void AMDGPURegisterBankInfo::applyMappingSMULU64( + MachineIRBuilder &B, const OperandsMapper &OpdMapper) const { + SmallVector DefRegs(OpdMapper.getVRegs(0)); + SmallVector Src0Regs(OpdMapper.getVRegs(1)); + SmallVector Src1Regs(OpdMapper.getVRegs(2)); + + // All inputs are SGPRs, nothing special to do. + if (DefRegs.empty()) { + assert(Src0Regs.empty() && Src1Regs.empty()); + applyDefaultMapping(OpdMapper); + return; + } + + assert(DefRegs.size() == 2); + assert(Src0Regs.size() == Src1Regs.size() && + (Src0Regs.empty() || Src0Regs.size() == 2)); + + MachineRegisterInfo &MRI = OpdMapper.getMRI(); + MachineInstr &MI = OpdMapper.getMI(); + Register DstReg = MI.getOperand(0).getReg(); + LLT HalfTy = LLT::scalar(32); + + // Depending on where the source registers came from, the generic code may + // have decided to split the inputs already or not. If not, we still need to + // extract the values. + + if (Src0Regs.empty()) + split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg()); + else + setRegsToType(MRI, Src0Regs, HalfTy); + + if (Src1Regs.empty()) + split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); + else + setRegsToType(MRI, Src1Regs, HalfTy); + + setRegsToType(MRI, DefRegs, HalfTy); + + // The multiplication is done as follows: + // + // Op1H Op1L + // * Op0H Op0L + // -------------------- + // Op1H*Op0L Op1L*Op0L + // + Op1H*Op0H Op1L*Op0H + // ----------------------------------------- + // (Op1H*Op0L + Op1L*Op0H + carry) Op1L*Op0L + // + // We drop Op1H*Op0H because the result of the multiplication is a 64-bit + // value and that would overflow. + // The low 32-bit value is Op1L*Op0L. + // The high 32-bit value is Op1H*Op0L + Op1L*Op0H + carry (from + // Op1L*Op0L). + + ApplyRegBankMapping ApplyBank(B, *this, MRI, &AMDGPU::VGPRRegBank); + + Register Hi = B.buildUMulH(HalfTy, Src0Regs[0], Src1Regs[0]).getReg(0); + Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0); + Register Add = B.buildAdd(HalfTy, Hi, MulLoHi).getReg(0); + Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0); + B.buildAdd(DefRegs[1], Add, MulHiLo); + B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]); + + MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); + MI.eraseFromParent(); +} + void AMDGPURegisterBankInfo::applyMappingImpl( MachineIRBuilder &B, const OperandsMapper &OpdMapper) const { MachineInstr &MI = OpdMapper.getMI(); @@ -2394,13 +2462,21 @@ void AMDGPURegisterBankInfo::applyMappingImpl( Register DstReg = MI.getOperand(0).getReg(); LLT DstTy = MRI.getType(DstReg); + // Special case for s_mul_u64. There is not a vector equivalent of + // s_mul_u64. Hence, we have to break down s_mul_u64 into 32-bit vector + // multiplications. + if (Opc == AMDGPU::G_MUL && DstTy.getSizeInBits() == 64) { + applyMappingSMULU64(B, OpdMapper); + return; + } + // 16-bit operations are VALU only, but can be promoted to 32-bit SALU. // Packed 16-bit operations need to be scalarized and promoted. if (DstTy != LLT::scalar(16) && DstTy != LLT::fixed_vector(2, 16)) break; const RegisterBank *DstBank = - OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; + OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; if (DstBank == &AMDGPU::VGPRRegBank) break; @@ -2451,6 +2527,72 @@ void AMDGPURegisterBankInfo::applyMappingImpl( return; } + case AMDGPU::G_AMDGPU_S_MUL_I64_I32: + case AMDGPU::G_AMDGPU_S_MUL_U64_U32: { + // This is a special case for s_mul_u64. We use + // G_AMDGPU_S_MUL_I64_I32 opcode to represent an s_mul_u64 operation + // where the 33 higher bits are sign-extended and + // G_AMDGPU_S_MUL_U64_U32 opcode to represent an s_mul_u64 operation + // where the 32 higher bits are zero-extended. In case scalar registers are + // selected, both opcodes are lowered as s_mul_u64. If the vector registers + // are selected, then G_AMDGPU_S_MUL_I64_I32 and + // G_AMDGPU_S_MUL_U64_U32 are lowered with a vector mad instruction. + + // Insert basic copies. + applyDefaultMapping(OpdMapper); + + Register DstReg = MI.getOperand(0).getReg(); + Register SrcReg0 = MI.getOperand(1).getReg(); + Register SrcReg1 = MI.getOperand(2).getReg(); + const LLT S32 = LLT::scalar(32); + const LLT S64 = LLT::scalar(64); + assert(MRI.getType(DstReg) == S64 && "This is a special case for s_mul_u64 " + "that handles only 64-bit operands."); + const RegisterBank *DstBank = + OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; + + // Replace G_AMDGPU_S_MUL_I64_I32 and G_AMDGPU_S_MUL_U64_U32 + // with s_mul_u64 operation. + if (DstBank == &AMDGPU::SGPRRegBank) { + MI.setDesc(TII->get(AMDGPU::S_MUL_U64)); + MRI.setRegClass(DstReg, &AMDGPU::SGPR_64RegClass); + MRI.setRegClass(SrcReg0, &AMDGPU::SGPR_64RegClass); + MRI.setRegClass(SrcReg1, &AMDGPU::SGPR_64RegClass); + return; + } + + // Replace G_AMDGPU_S_MUL_I64_I32 and G_AMDGPU_S_MUL_U64_U32 + // with a vector mad. + assert(MRI.getRegBankOrNull(DstReg) == &AMDGPU::VGPRRegBank && + "The destination operand should be in vector registers."); + + DebugLoc DL = MI.getDebugLoc(); + + // Extract the lower subregister from the first operand. + Register Op0L = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass); + MRI.setType(Op0L, S32); + B.buildTrunc(Op0L, SrcReg0); + + // Extract the lower subregister from the second operand. + Register Op1L = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + MRI.setRegClass(Op1L, &AMDGPU::VGPR_32RegClass); + MRI.setType(Op1L, S32); + B.buildTrunc(Op1L, SrcReg1); + + unsigned NewOpc = Opc == AMDGPU::G_AMDGPU_S_MUL_U64_U32 + ? AMDGPU::G_AMDGPU_MAD_U64_U32 + : AMDGPU::G_AMDGPU_MAD_I64_I32; + + MachineIRBuilder B(MI); + Register Zero64 = B.buildConstant(S64, 0).getReg(0); + MRI.setRegClass(Zero64, &AMDGPU::VReg_64RegClass); + Register CarryOut = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); + MRI.setRegClass(CarryOut, &AMDGPU::VReg_64RegClass); + B.buildInstr(NewOpc, {DstReg, CarryOut}, {Op0L, Op1L, Zero64}); + MI.eraseFromParent(); + return; + } case AMDGPU::G_SEXT_INREG: { SmallVector SrcRegs(OpdMapper.getVRegs(1)); if (SrcRegs.empty()) @@ -3669,7 +3811,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_AND: case AMDGPU::G_OR: - case AMDGPU::G_XOR: { + case AMDGPU::G_XOR: + case AMDGPU::G_MUL: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); if (Size == 1) { const RegisterBank *DstBank @@ -3737,7 +3880,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_PTRMASK: case AMDGPU::G_ADD: case AMDGPU::G_SUB: - case AMDGPU::G_MUL: case AMDGPU::G_SHL: case AMDGPU::G_LSHR: case AMDGPU::G_ASHR: @@ -3755,6 +3897,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_SHUFFLE_VECTOR: case AMDGPU::G_SBFX: case AMDGPU::G_UBFX: + case AMDGPU::G_AMDGPU_S_MUL_I64_I32: + case AMDGPU::G_AMDGPU_S_MUL_U64_U32: if (isSALUMapping(MI)) return getDefaultMappingSOP(MI); return getDefaultMappingVOP(MI); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h index b5d16e70ab23..2bb5ef57fe03 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h @@ -84,6 +84,9 @@ public: bool applyMappingMAD_64_32(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const; + void applyMappingSMULU64(MachineIRBuilder &B, + const OperandsMapper &OpdMapper) const; + Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const; diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index ce3164d7b92e..f6f37f5170a4 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -683,6 +683,8 @@ public: bool hasScalarAddSub64() const { return getGeneration() >= GFX12; } + bool hasScalarSMulU64() const { return getGeneration() >= GFX12; } + bool hasUnpackedD16VMem() const { return HasUnpackedD16VMem; } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index e865c73015d2..209debb3a105 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -835,6 +835,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom); + if (Subtarget->hasScalarSMulU64()) + setOperationAction(ISD::MUL, MVT::i64, Custom); + if (Subtarget->hasMad64_32()) setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, MVT::i32, Custom); @@ -5566,7 +5569,6 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SRL: case ISD::ADD: case ISD::SUB: - case ISD::MUL: case ISD::SMIN: case ISD::SMAX: case ISD::UMIN: @@ -5580,6 +5582,8 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SADDSAT: case ISD::SSUBSAT: return splitBinaryVectorOp(Op, DAG); + case ISD::MUL: + return lowerMUL(Op, DAG); case ISD::SMULO: case ISD::UMULO: return lowerXMULO(Op, DAG); @@ -6235,6 +6239,66 @@ SDValue SITargetLowering::lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(ISD::FLDEXP, DL, VT, Op.getOperand(0), TruncExp); } +// Custom lowering for vector multiplications and s_mul_u64. +SDValue SITargetLowering::lowerMUL(SDValue Op, SelectionDAG &DAG) const { + EVT VT = Op.getValueType(); + + // Split vector operands. + if (VT.isVector()) + return splitBinaryVectorOp(Op, DAG); + + assert(VT == MVT::i64 && "The following code is a special for s_mul_u64"); + + // There are four ways to lower s_mul_u64: + // + // 1. If all the operands are uniform, then we lower it as it is. + // + // 2. If the operands are divergent, then we have to split s_mul_u64 in 32-bit + // multiplications because there is not a vector equivalent of s_mul_u64. + // + // 3. If the cost model decides that it is more efficient to use vector + // registers, then we have to split s_mul_u64 in 32-bit multiplications. + // This happens in splitScalarSMULU64() in SIInstrInfo.cpp . + // + // 4. If the cost model decides to use vector registers and both of the + // operands are zero-extended/sign-extended from 32-bits, then we split the + // s_mul_u64 in two 32-bit multiplications. The problem is that it is not + // possible to check if the operands are zero-extended or sign-extended in + // SIInstrInfo.cpp. For this reason, here, we replace s_mul_u64 with + // s_mul_u64_u32_pseudo if both operands are zero-extended and we replace + // s_mul_u64 with s_mul_i64_i32_pseudo if both operands are sign-extended. + // If the cost model decides that we have to use vector registers, then + // splitScalarSMulPseudo() (in SIInstrInfo.cpp) split s_mul_u64_u32/ + // s_mul_i64_i32_pseudo in two vector multiplications. If the cost model + // decides that we should use scalar registers, then s_mul_u64_u32_pseudo/ + // s_mul_i64_i32_pseudo is lowered as s_mul_u64 in expandPostRAPseudo() in + // SIInstrInfo.cpp . + + if (Op->isDivergent()) + return SDValue(); + + SDValue Op0 = Op.getOperand(0); + SDValue Op1 = Op.getOperand(1); + // If all the operands are zero-enteted to 32-bits, then we replace s_mul_u64 + // with s_mul_u64_u32_pseudo. If all the operands are sign-extended to + // 32-bits, then we replace s_mul_u64 with s_mul_i64_i32_pseudo. + KnownBits Op0KnownBits = DAG.computeKnownBits(Op0); + unsigned Op0LeadingZeros = Op0KnownBits.countMinLeadingZeros(); + KnownBits Op1KnownBits = DAG.computeKnownBits(Op1); + unsigned Op1LeadingZeros = Op1KnownBits.countMinLeadingZeros(); + SDLoc SL(Op); + if (Op0LeadingZeros >= 32 && Op1LeadingZeros >= 32) + return SDValue( + DAG.getMachineNode(AMDGPU::S_MUL_U64_U32_PSEUDO, SL, VT, Op0, Op1), 0); + unsigned Op0SignBits = DAG.ComputeNumSignBits(Op0); + unsigned Op1SignBits = DAG.ComputeNumSignBits(Op1); + if (Op0SignBits >= 33 && Op1SignBits >= 33) + return SDValue( + DAG.getMachineNode(AMDGPU::S_MUL_I64_I32_PSEUDO, SL, VT, Op0, Op1), 0); + // If all the operands are uniform, then we lower s_mul_u64 as it is. + return Op; +} + SDValue SITargetLowering::lowerXMULO(SDValue Op, SelectionDAG &DAG) const { EVT VT = Op.getValueType(); SDLoc SL(Op); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 00f9ddf11ea7..92b38ebade62 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -146,6 +146,7 @@ private: SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const; SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 67992929ab35..d4c7a457e9aa 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2475,6 +2475,11 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MI.eraseFromParent(); break; } + + case AMDGPU::S_MUL_U64_U32_PSEUDO: + case AMDGPU::S_MUL_I64_I32_PSEUDO: + MI.setDesc(get(AMDGPU::S_MUL_U64)); + break; } return true; } @@ -6845,6 +6850,21 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist, // Default handling break; } + + case AMDGPU::S_MUL_U64: + // Split s_mul_u64 in 32-bit vector multiplications. + splitScalarSMulU64(Worklist, Inst, MDT); + Inst.eraseFromParent(); + return; + + case AMDGPU::S_MUL_U64_U32_PSEUDO: + case AMDGPU::S_MUL_I64_I32_PSEUDO: + // This is a special case of s_mul_u64 where all the operands are either + // zero extended or sign extended. + splitScalarSMulPseudo(Worklist, Inst, MDT); + Inst.eraseFromParent(); + return; + case AMDGPU::S_AND_B64: splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32, MDT); Inst.eraseFromParent(); @@ -7654,6 +7674,180 @@ void SIInstrInfo::splitScalar64BitUnaryOp(SIInstrWorklist &Worklist, addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist); } +// There is not a vector equivalent of s_mul_u64. For this reason, we need to +// split the s_mul_u64 in 32-bit vector multiplications. +void SIInstrInfo::splitScalarSMulU64(SIInstrWorklist &Worklist, + MachineInstr &Inst, + MachineDominatorTree *MDT) const { + MachineBasicBlock &MBB = *Inst.getParent(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + + Register FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); + Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + + MachineOperand &Dest = Inst.getOperand(0); + MachineOperand &Src0 = Inst.getOperand(1); + MachineOperand &Src1 = Inst.getOperand(2); + const DebugLoc &DL = Inst.getDebugLoc(); + MachineBasicBlock::iterator MII = Inst; + + const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg()); + const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); + const TargetRegisterClass *Src0SubRC = + RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); + if (RI.isSGPRClass(Src0SubRC)) + Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC); + const TargetRegisterClass *Src1SubRC = + RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); + if (RI.isSGPRClass(Src1SubRC)) + Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC); + + // First, we extract the low 32-bit and high 32-bit values from each of the + // operands. + MachineOperand Op0L = + buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); + MachineOperand Op1L = + buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); + MachineOperand Op0H = + buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); + MachineOperand Op1H = + buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); + + // The multilication is done as follows: + // + // Op1H Op1L + // * Op0H Op0L + // -------------------- + // Op1H*Op0L Op1L*Op0L + // + Op1H*Op0H Op1L*Op0H + // ----------------------------------------- + // (Op1H*Op0L + Op1L*Op0H + carry) Op1L*Op0L + // + // We drop Op1H*Op0H because the result of the multiplication is a 64-bit + // value and that would overflow. + // The low 32-bit value is Op1L*Op0L. + // The high 32-bit value is Op1H*Op0L + Op1L*Op0H + carry (from Op1L*Op0L). + + Register Op1L_Op0H_Reg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + MachineInstr *Op1L_Op0H = + BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), Op1L_Op0H_Reg) + .add(Op1L) + .add(Op0H); + + Register Op1H_Op0L_Reg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + MachineInstr *Op1H_Op0L = + BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), Op1H_Op0L_Reg) + .add(Op1H) + .add(Op0L); + + Register CarryReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + MachineInstr *Carry = + BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_HI_U32_e64), CarryReg) + .add(Op1L) + .add(Op0L); + + MachineInstr *LoHalf = + BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) + .add(Op1L) + .add(Op0L); + + Register AddReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + MachineInstr *Add = BuildMI(MBB, MII, DL, get(AMDGPU::V_ADD_U32_e32), AddReg) + .addReg(Op1L_Op0H_Reg) + .addReg(Op1H_Op0L_Reg); + + MachineInstr *HiHalf = + BuildMI(MBB, MII, DL, get(AMDGPU::V_ADD_U32_e32), DestSub1) + .addReg(AddReg) + .addReg(CarryReg); + + BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) + .addReg(DestSub0) + .addImm(AMDGPU::sub0) + .addReg(DestSub1) + .addImm(AMDGPU::sub1); + + MRI.replaceRegWith(Dest.getReg(), FullDestReg); + + // Try to legalize the operands in case we need to swap the order to keep it + // valid. + legalizeOperands(*Op1L_Op0H, MDT); + legalizeOperands(*Op1H_Op0L, MDT); + legalizeOperands(*Carry, MDT); + legalizeOperands(*LoHalf, MDT); + legalizeOperands(*Add, MDT); + legalizeOperands(*HiHalf, MDT); + + // Move all users of this moved value. + addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist); +} + +// Lower S_MUL_U64_U32_PSEUDO/S_MUL_I64_I32_PSEUDO in two 32-bit vector +// multiplications. +void SIInstrInfo::splitScalarSMulPseudo(SIInstrWorklist &Worklist, + MachineInstr &Inst, + MachineDominatorTree *MDT) const { + MachineBasicBlock &MBB = *Inst.getParent(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + + Register FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); + Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + + MachineOperand &Dest = Inst.getOperand(0); + MachineOperand &Src0 = Inst.getOperand(1); + MachineOperand &Src1 = Inst.getOperand(2); + const DebugLoc &DL = Inst.getDebugLoc(); + MachineBasicBlock::iterator MII = Inst; + + const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg()); + const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); + const TargetRegisterClass *Src0SubRC = + RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); + if (RI.isSGPRClass(Src0SubRC)) + Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC); + const TargetRegisterClass *Src1SubRC = + RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); + if (RI.isSGPRClass(Src1SubRC)) + Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC); + + // First, we extract the low 32-bit and high 32-bit values from each of the + // operands. + MachineOperand Op0L = + buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); + MachineOperand Op1L = + buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); + + unsigned Opc = Inst.getOpcode(); + unsigned NewOpc = Opc == AMDGPU::S_MUL_U64_U32_PSEUDO + ? AMDGPU::V_MUL_HI_U32_e64 + : AMDGPU::V_MUL_HI_I32_e64; + MachineInstr *HiHalf = + BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L); + + MachineInstr *LoHalf = + BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) + .add(Op1L) + .add(Op0L); + + BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) + .addReg(DestSub0) + .addImm(AMDGPU::sub0) + .addReg(DestSub1) + .addImm(AMDGPU::sub1); + + MRI.replaceRegWith(Dest.getReg(), FullDestReg); + + // Try to legalize the operands in case we need to swap the order to keep it + // valid. + legalizeOperands(*HiHalf, MDT); + legalizeOperands(*LoHalf, MDT); + + // Move all users of this moved value. + addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist); +} + void SIInstrInfo::splitScalar64BitBinaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst, unsigned Opcode, MachineDominatorTree *MDT) const { diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 46eee6fae0a5..37ee159362a2 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -138,6 +138,12 @@ private: unsigned Opcode, MachineDominatorTree *MDT = nullptr) const; + void splitScalarSMulU64(SIInstrWorklist &Worklist, MachineInstr &Inst, + MachineDominatorTree *MDT) const; + + void splitScalarSMulPseudo(SIInstrWorklist &Worklist, MachineInstr &Inst, + MachineDominatorTree *MDT) const; + void splitScalar64BitXnor(SIInstrWorklist &Worklist, MachineInstr &Inst, MachineDominatorTree *MDT = nullptr) const; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index b0b7854ffc06..1cd8a37c3aa9 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3853,6 +3853,18 @@ def G_AMDGPU_S_BUFFER_LOAD : AMDGPUGenericInstruction { let mayStore = 0; } +def G_AMDGPU_S_MUL_U64_U32 : AMDGPUGenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src0, type0:$src1); + let hasSideEffects = 0; +} + +def G_AMDGPU_S_MUL_I64_I32 : AMDGPUGenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src0, type0:$src1); + let hasSideEffects = 0; +} + // This is equivalent to the G_INTRINSIC*, but the operands may have // been legalized depending on the subtarget requirements. def G_AMDGPU_INTRIN_IMAGE_LOAD : AMDGPUGenericInstruction { diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index c9687ac368d3..5f021307e18e 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -673,6 +673,16 @@ let SubtargetPredicate = isGFX12Plus in { let isCommutable = 1; } + // The higher 32-bits of the inputs contain the sign extension bits. + def S_MUL_I64_I32_PSEUDO : SPseudoInstSI < + (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1) + >; + + // The higher 32-bits of the inputs are zero. + def S_MUL_U64_U32_PSEUDO : SPseudoInstSI < + (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1) + >; + } // End SubtargetPredicate = isGFX12Plus let Uses = [SCC] in { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir index 5b0ed61a3313..2bf8649e7624 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir @@ -1,9 +1,10 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX8 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GCN,GFX8PLUS,GFX89,GFX8 %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GCN,GFX8PLUS,GFX89,GFX9PLUS %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GCN,GFX8PLUS,GFX9PLUS,GFX1011 %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GCN,GFX8PLUS,GFX9PLUS,GFX1011 %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GCN,GFX8PLUS,GFX9PLUS,GFX12 %s --- name: test_mul_s32 @@ -11,34 +12,13 @@ body: | bb.0: liveins: $vgpr0, $vgpr1 - ; GFX6-LABEL: name: test_mul_s32 - ; GFX6: liveins: $vgpr0, $vgpr1 - ; GFX6-NEXT: {{ $}} - ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX6-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX6-NEXT: $vgpr0 = COPY [[MUL]](s32) - ; GFX8-LABEL: name: test_mul_s32 - ; GFX8: liveins: $vgpr0, $vgpr1 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX8-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX8-NEXT: $vgpr0 = COPY [[MUL]](s32) - ; GFX9-LABEL: name: test_mul_s32 - ; GFX9: liveins: $vgpr0, $vgpr1 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX9-NEXT: $vgpr0 = COPY [[MUL]](s32) - ; GFX10-LABEL: name: test_mul_s32 - ; GFX10: liveins: $vgpr0, $vgpr1 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX10-NEXT: $vgpr0 = COPY [[MUL]](s32) + ; GCN-LABEL: name: test_mul_s32 + ; GCN: liveins: $vgpr0, $vgpr1 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GCN-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; GCN-NEXT: $vgpr0 = COPY [[MUL]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_MUL %0, %1 @@ -51,50 +31,17 @@ body: | bb.0: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX6-LABEL: name: test_mul_v2s32 - ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX6-NEXT: {{ $}} - ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 - ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 - ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX6-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]] - ; GFX6-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]] - ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32) - ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) - ; GFX8-LABEL: name: test_mul_v2s32 - ; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 - ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; GFX8-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX8-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]] - ; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]] - ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32) - ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) - ; GFX9-LABEL: name: test_mul_v2s32 - ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 - ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]] - ; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]] - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32) - ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) - ; GFX10-LABEL: name: test_mul_v2s32 - ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 - ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]] - ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]] - ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32) - ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) + ; GCN-LABEL: name: test_mul_v2s32 + ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 + ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 + ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) + ; GCN-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) + ; GCN-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]] + ; GCN-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]] + ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32) + ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3 %2:_(<2 x s32>) = G_MUL %0, %1 @@ -122,54 +69,48 @@ body: | ; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32) ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) - ; GFX8-LABEL: name: test_mul_s64 - ; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 - ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) - ; GFX8-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) - ; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] - ; GFX8-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV5]](s32) - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[ANYEXT]] - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV2]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) - ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV6]](s32) - ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) - ; GFX9-LABEL: name: test_mul_s64 - ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 - ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) - ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) - ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] - ; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV5]](s32) - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[ANYEXT]] - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV2]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) - ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV6]](s32) - ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) - ; GFX10-LABEL: name: test_mul_s64 - ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 - ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) - ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) - ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] - ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]] - ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]] - ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]] - ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]] - ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32) - ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) + ; + ; GFX89-LABEL: name: test_mul_s64 + ; GFX89: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GFX89-NEXT: {{ $}} + ; GFX89-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; GFX89-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; GFX89-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) + ; GFX89-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) + ; GFX89-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] + ; GFX89-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX89-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV5]](s32) + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[ANYEXT]] + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV2]], [[AMDGPU_MAD_U64_U32_2]] + ; GFX89-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) + ; GFX89-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV6]](s32) + ; GFX89-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) + ; + ; GFX1011-LABEL: name: test_mul_s64 + ; GFX1011: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GFX1011-NEXT: {{ $}} + ; GFX1011-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; GFX1011-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; GFX1011-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) + ; GFX1011-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) + ; GFX1011-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX1011-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] + ; GFX1011-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX1011-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]] + ; GFX1011-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]] + ; GFX1011-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]] + ; GFX1011-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]] + ; GFX1011-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32) + ; GFX1011-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) + ; + ; GFX12-LABEL: name: test_mul_s64 + ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; GFX12-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[MUL]](s64) %0:_(s64) = COPY $vgpr0_vgpr1 %1:_(s64) = COPY $vgpr2_vgpr3 %2:_(s64) = G_MUL %0, %1 @@ -209,90 +150,76 @@ body: | ; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL3]](s32), [[ADD3]](s32) ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) - ; GFX8-LABEL: name: test_mul_v2s64 - ; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 - ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) - ; GFX8-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>) - ; GFX8-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) - ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) - ; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV6]], [[C]] - ; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV9]](s32) - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV7]], [[ANYEXT]] - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV5]](s32), [[UV6]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) - ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[UV10]](s32) - ; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) - ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_6:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_7:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV12]](s32), [[UV14]], [[C]] - ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_6]](s64) - ; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV17]](s32) - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_8:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_9:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV12]](s32), [[UV15]], [[ANYEXT1]] - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_10:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_11:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV13]](s32), [[UV14]], [[AMDGPU_MAD_U64_U32_8]] - ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_10]](s64) - ; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV16]](s32), [[UV18]](s32) - ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) - ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) - ; GFX9-LABEL: name: test_mul_v2s64 - ; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 - ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) - ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>) - ; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) - ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) - ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV6]], [[C]] - ; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV9]](s32) - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV7]], [[ANYEXT]] - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV5]](s32), [[UV6]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) - ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[UV10]](s32) - ; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) - ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_6:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_7:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV12]](s32), [[UV14]], [[C]] - ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_6]](s64) - ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV17]](s32) - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_8:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_9:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV12]](s32), [[UV15]], [[ANYEXT1]] - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_10:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_11:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV13]](s32), [[UV14]], [[AMDGPU_MAD_U64_U32_8]] - ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_10]](s64) - ; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV16]](s32), [[UV18]](s32) - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) - ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) - ; GFX10-LABEL: name: test_mul_v2s64 - ; GFX10: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 - ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) - ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>) - ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) - ; GFX10-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) - ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV6]], [[C]] - ; GFX10-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV4]], [[UV7]] - ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[MUL]] - ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV5]], [[UV6]] - ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]] - ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[ADD1]](s32) - ; GFX10-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) - ; GFX10-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) - ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV10]](s32), [[UV12]], [[C]] - ; GFX10-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_2]](s64) - ; GFX10-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UV13]] - ; GFX10-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[MUL2]] - ; GFX10-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UV12]] - ; GFX10-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[MUL3]] - ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV14]](s32), [[ADD3]](s32) - ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) - ; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) + ; + ; GFX89-LABEL: name: test_mul_v2s64 + ; GFX89: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 + ; GFX89-NEXT: {{ $}} + ; GFX89-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; GFX89-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 + ; GFX89-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) + ; GFX89-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>) + ; GFX89-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) + ; GFX89-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) + ; GFX89-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV6]], [[C]] + ; GFX89-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX89-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV9]](s32) + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV7]], [[ANYEXT]] + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV5]](s32), [[UV6]], [[AMDGPU_MAD_U64_U32_2]] + ; GFX89-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) + ; GFX89-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[UV10]](s32) + ; GFX89-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) + ; GFX89-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_6:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_7:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV12]](s32), [[UV14]], [[C]] + ; GFX89-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_6]](s64) + ; GFX89-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV17]](s32) + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_8:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_9:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV12]](s32), [[UV15]], [[ANYEXT1]] + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_10:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_11:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV13]](s32), [[UV14]], [[AMDGPU_MAD_U64_U32_8]] + ; GFX89-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_10]](s64) + ; GFX89-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV16]](s32), [[UV18]](s32) + ; GFX89-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) + ; GFX89-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) + ; + ; GFX1011-LABEL: name: test_mul_v2s64 + ; GFX1011: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 + ; GFX1011-NEXT: {{ $}} + ; GFX1011-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; GFX1011-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 + ; GFX1011-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) + ; GFX1011-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>) + ; GFX1011-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) + ; GFX1011-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) + ; GFX1011-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX1011-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV4]](s32), [[UV6]], [[C]] + ; GFX1011-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX1011-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV4]], [[UV7]] + ; GFX1011-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[MUL]] + ; GFX1011-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV5]], [[UV6]] + ; GFX1011-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]] + ; GFX1011-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[ADD1]](s32) + ; GFX1011-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) + ; GFX1011-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) + ; GFX1011-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV10]](s32), [[UV12]], [[C]] + ; GFX1011-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_2]](s64) + ; GFX1011-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UV13]] + ; GFX1011-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[MUL2]] + ; GFX1011-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UV12]] + ; GFX1011-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[MUL3]] + ; GFX1011-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV14]](s32), [[ADD3]](s32) + ; GFX1011-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) + ; GFX1011-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) + ; + ; GFX12-LABEL: name: test_mul_v2s64 + ; GFX12: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 + ; GFX12-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) + ; GFX12-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>) + ; GFX12-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UV]], [[UV2]] + ; GFX12-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[UV1]], [[UV3]] + ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL1]](s64) + ; GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 %2:_(<2 x s64>) = G_MUL %0, %1 @@ -314,36 +241,17 @@ body: | ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]] ; GFX6-NEXT: $vgpr0 = COPY [[AND]](s32) - ; GFX8-LABEL: name: test_mul_s16 - ; GFX8: liveins: $vgpr0, $vgpr1 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) - ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX8-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[TRUNC]], [[TRUNC1]] - ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[MUL]](s16) - ; GFX8-NEXT: $vgpr0 = COPY [[ZEXT]](s32) - ; GFX9-LABEL: name: test_mul_s16 - ; GFX9: liveins: $vgpr0, $vgpr1 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) - ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[TRUNC]], [[TRUNC1]] - ; GFX9-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[MUL]](s16) - ; GFX9-NEXT: $vgpr0 = COPY [[ZEXT]](s32) - ; GFX10-LABEL: name: test_mul_s16 - ; GFX10: liveins: $vgpr0, $vgpr1 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) - ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[TRUNC]], [[TRUNC1]] - ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[MUL]](s16) - ; GFX10-NEXT: $vgpr0 = COPY [[ZEXT]](s32) + ; + ; GFX8PLUS-LABEL: name: test_mul_s16 + ; GFX8PLUS: liveins: $vgpr0, $vgpr1 + ; GFX8PLUS-NEXT: {{ $}} + ; GFX8PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX8PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX8PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; GFX8PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; GFX8PLUS-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[TRUNC]], [[TRUNC1]] + ; GFX8PLUS-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[MUL]](s16) + ; GFX8PLUS-NEXT: $vgpr0 = COPY [[ZEXT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s16) = G_TRUNC %0 @@ -378,6 +286,7 @@ body: | ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; ; GFX8-LABEL: name: test_mul_v2s16 ; GFX8: liveins: $vgpr0, $vgpr1 ; GFX8-NEXT: {{ $}} @@ -400,20 +309,14 @@ body: | ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) - ; GFX9-LABEL: name: test_mul_v2s16 - ; GFX9: liveins: $vgpr0, $vgpr1 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 - ; GFX9-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[COPY]], [[COPY1]] - ; GFX9-NEXT: $vgpr0 = COPY [[MUL]](<2 x s16>) - ; GFX10-LABEL: name: test_mul_v2s16 - ; GFX10: liveins: $vgpr0, $vgpr1 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[COPY]], [[COPY1]] - ; GFX10-NEXT: $vgpr0 = COPY [[MUL]](<2 x s16>) + ; + ; GFX9PLUS-LABEL: name: test_mul_v2s16 + ; GFX9PLUS: liveins: $vgpr0, $vgpr1 + ; GFX9PLUS-NEXT: {{ $}} + ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 + ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 + ; GFX9PLUS-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[COPY]], [[COPY1]] + ; GFX9PLUS-NEXT: $vgpr0 = COPY [[MUL]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 %2:_(<2 x s16>) = G_MUL %0, %1 @@ -441,6 +344,7 @@ body: | ; GFX6-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY5]] ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[MUL2]](s32) ; GFX6-NEXT: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16) + ; ; GFX8-LABEL: name: test_mul_v3s16 ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX8-NEXT: {{ $}} @@ -460,66 +364,37 @@ body: | ; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s16) = G_MUL [[TRUNC1]], [[TRUNC4]] ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s16) = G_MUL [[TRUNC2]], [[TRUNC5]] ; GFX8-NEXT: S_ENDPGM 0, implicit [[MUL]](s16), implicit [[MUL1]](s16), implicit [[MUL2]](s16) - ; GFX9-LABEL: name: test_mul_v3s16 - ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 - ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 - ; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 - ; GFX9-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 - ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) - ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) - ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32) - ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32) - ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) - ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) - ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF]](s16) - ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC4]](s16) - ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](s16), [[DEF]](s16) - ; GFX9-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR]], [[BUILD_VECTOR2]] - ; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR3]] - ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[MUL]](<2 x s16>) - ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) - ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[MUL1]](<2 x s16>) - ; GFX9-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32) - ; GFX9-NEXT: S_ENDPGM 0, implicit [[TRUNC6]](s16), implicit [[TRUNC7]](s16), implicit [[TRUNC8]](s16) - ; GFX10-LABEL: name: test_mul_v3s16 - ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 - ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 - ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 - ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 - ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) - ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) - ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32) - ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32) - ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) - ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF - ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) - ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF]](s16) - ; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC4]](s16) - ; GFX10-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](s16), [[DEF]](s16) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR]], [[BUILD_VECTOR2]] - ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR3]] - ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[MUL]](<2 x s16>) - ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) - ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[MUL1]](<2 x s16>) - ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32) - ; GFX10-NEXT: S_ENDPGM 0, implicit [[TRUNC6]](s16), implicit [[TRUNC7]](s16), implicit [[TRUNC8]](s16) + ; + ; GFX9PLUS-LABEL: name: test_mul_v3s16 + ; GFX9PLUS: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX9PLUS-NEXT: {{ $}} + ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX9PLUS-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX9PLUS-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX9PLUS-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX9PLUS-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 + ; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; GFX9PLUS-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; GFX9PLUS-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32) + ; GFX9PLUS-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32) + ; GFX9PLUS-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) + ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF + ; GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) + ; GFX9PLUS-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF]](s16) + ; GFX9PLUS-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC4]](s16) + ; GFX9PLUS-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](s16), [[DEF]](s16) + ; GFX9PLUS-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR]], [[BUILD_VECTOR2]] + ; GFX9PLUS-NEXT: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR3]] + ; GFX9PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[MUL]](<2 x s16>) + ; GFX9PLUS-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) + ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; GFX9PLUS-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) + ; GFX9PLUS-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) + ; GFX9PLUS-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[MUL1]](<2 x s16>) + ; GFX9PLUS-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32) + ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[TRUNC6]](s16), implicit [[TRUNC7]](s16), implicit [[TRUNC8]](s16) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = COPY $vgpr2 @@ -578,6 +453,7 @@ body: | ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>) ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) + ; ; GFX8-LABEL: name: test_mul_v4s16 ; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 ; GFX8-NEXT: {{ $}} @@ -618,28 +494,18 @@ body: | ; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>) ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) - ; GFX9-LABEL: name: test_mul_v4s16 - ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 - ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) - ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) - ; GFX9-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[UV]], [[UV2]] - ; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[UV1]], [[UV3]] - ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[MUL]](<2 x s16>), [[MUL1]](<2 x s16>) - ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) - ; GFX10-LABEL: name: test_mul_v4s16 - ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 - ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) - ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[UV]], [[UV2]] - ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[UV1]], [[UV3]] - ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[MUL]](<2 x s16>), [[MUL1]](<2 x s16>) - ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) + ; + ; GFX9PLUS-LABEL: name: test_mul_v4s16 + ; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GFX9PLUS-NEXT: {{ $}} + ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 + ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 + ; GFX9PLUS-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) + ; GFX9PLUS-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) + ; GFX9PLUS-NEXT: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[UV]], [[UV2]] + ; GFX9PLUS-NEXT: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[UV1]], [[UV3]] + ; GFX9PLUS-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[MUL]](<2 x s16>), [[MUL1]](<2 x s16>) + ; GFX9PLUS-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %1:_(<4 x s16>) = COPY $vgpr2_vgpr3 %2:_(<4 x s16>) = G_MUL %0, %1 @@ -652,34 +518,13 @@ body: | bb.0: liveins: $vgpr0, $vgpr1 - ; GFX6-LABEL: name: test_mul_s24 - ; GFX6: liveins: $vgpr0, $vgpr1 - ; GFX6-NEXT: {{ $}} - ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX6-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX6-NEXT: $vgpr0 = COPY [[MUL]](s32) - ; GFX8-LABEL: name: test_mul_s24 - ; GFX8: liveins: $vgpr0, $vgpr1 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX8-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX8-NEXT: $vgpr0 = COPY [[MUL]](s32) - ; GFX9-LABEL: name: test_mul_s24 - ; GFX9: liveins: $vgpr0, $vgpr1 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX9-NEXT: $vgpr0 = COPY [[MUL]](s32) - ; GFX10-LABEL: name: test_mul_s24 - ; GFX10: liveins: $vgpr0, $vgpr1 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] - ; GFX10-NEXT: $vgpr0 = COPY [[MUL]](s32) + ; GCN-LABEL: name: test_mul_s24 + ; GCN: liveins: $vgpr0, $vgpr1 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GCN-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; GCN-NEXT: $vgpr0 = COPY [[MUL]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s24) = G_TRUNC %0 @@ -709,54 +554,48 @@ body: | ; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32) ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) - ; GFX8-LABEL: name: test_mul_s33 - ; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 - ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) - ; GFX8-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) - ; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] - ; GFX8-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV5]](s32) - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[ANYEXT]] - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV2]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) - ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV6]](s32) - ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) - ; GFX9-LABEL: name: test_mul_s33 - ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 - ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) - ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) - ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] - ; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV5]](s32) - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[ANYEXT]] - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV2]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) - ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV6]](s32) - ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) - ; GFX10-LABEL: name: test_mul_s33 - ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 - ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) - ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) - ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] - ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]] - ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]] - ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]] - ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]] - ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32) - ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) + ; + ; GFX89-LABEL: name: test_mul_s33 + ; GFX89: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GFX89-NEXT: {{ $}} + ; GFX89-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; GFX89-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; GFX89-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) + ; GFX89-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) + ; GFX89-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] + ; GFX89-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX89-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV5]](s32) + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[ANYEXT]] + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV2]], [[AMDGPU_MAD_U64_U32_2]] + ; GFX89-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) + ; GFX89-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV6]](s32) + ; GFX89-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) + ; + ; GFX1011-LABEL: name: test_mul_s33 + ; GFX1011: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GFX1011-NEXT: {{ $}} + ; GFX1011-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; GFX1011-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; GFX1011-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) + ; GFX1011-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) + ; GFX1011-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX1011-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]] + ; GFX1011-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX1011-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]] + ; GFX1011-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]] + ; GFX1011-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]] + ; GFX1011-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]] + ; GFX1011-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32) + ; GFX1011-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) + ; + ; GFX12-LABEL: name: test_mul_s33 + ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; GFX12-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[MUL]](s64) %0:_(s64) = COPY $vgpr0_vgpr1 %1:_(s64) = COPY $vgpr2_vgpr3 %2:_(s33) = G_TRUNC %0 @@ -800,67 +639,71 @@ body: | ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD]] ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[MUL]](s32), [[UADDO2]](s32), [[ADD5]](s32) ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96) - ; GFX8-LABEL: name: test_mul_s96 - ; GFX8: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5 - ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 - ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5 - ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96) - ; GFX8-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96) - ; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[C]] - ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV5]], [[C]] - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV4]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_6:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_7:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV2]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_4]] - ; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_6]](s64) - ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32) - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_8:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_9:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV4]], [[MV]] - ; GFX8-NEXT: [[AMDGPU_MAD_U64_U32_10:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_11:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_8]] - ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_10]](s64) - ; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV10]](s32), [[UV11]](s32) - ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV1]](s96) - ; GFX9-LABEL: name: test_mul_s96 - ; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5 - ; GFX9-NEXT: {{ $}} - ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 - ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5 - ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96) - ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96) - ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[C]] - ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV5]], [[C]] - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV4]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_6:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_7:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV2]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_4]] - ; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_6]](s64) - ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32) - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_8:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_9:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV4]], [[MV]] - ; GFX9-NEXT: [[AMDGPU_MAD_U64_U32_10:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_11:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_8]] - ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_10]](s64) - ; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV10]](s32), [[UV11]](s32) - ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV1]](s96) - ; GFX10-LABEL: name: test_mul_s96 - ; GFX10: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5 - ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 - ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5 - ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96) - ; GFX10-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96) - ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[C]] - ; GFX10-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) - ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV5]] - ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV4]] - ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]] - ; GFX10-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV2]], [[UV3]] - ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL2]] - ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[ADD1]](s32) - ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV4]], [[MV]] - ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_2]] - ; GFX10-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) - ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV8]](s32), [[UV9]](s32) - ; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV1]](s96) + ; + ; GFX89-LABEL: name: test_mul_s96 + ; GFX89: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5 + ; GFX89-NEXT: {{ $}} + ; GFX89-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 + ; GFX89-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5 + ; GFX89-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96) + ; GFX89-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96) + ; GFX89-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[C]] + ; GFX89-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV5]], [[C]] + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV4]], [[AMDGPU_MAD_U64_U32_2]] + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_6:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_7:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV2]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_4]] + ; GFX89-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_6]](s64) + ; GFX89-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32) + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_8:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_9:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV4]], [[MV]] + ; GFX89-NEXT: [[AMDGPU_MAD_U64_U32_10:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_11:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_8]] + ; GFX89-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_10]](s64) + ; GFX89-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV10]](s32), [[UV11]](s32) + ; GFX89-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV1]](s96) + ; + ; GFX1011-LABEL: name: test_mul_s96 + ; GFX1011: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5 + ; GFX1011-NEXT: {{ $}} + ; GFX1011-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 + ; GFX1011-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5 + ; GFX1011-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96) + ; GFX1011-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96) + ; GFX1011-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX1011-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[C]] + ; GFX1011-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX1011-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV5]] + ; GFX1011-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV4]] + ; GFX1011-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]] + ; GFX1011-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV2]], [[UV3]] + ; GFX1011-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL2]] + ; GFX1011-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[ADD1]](s32) + ; GFX1011-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV4]], [[MV]] + ; GFX1011-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_2]] + ; GFX1011-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) + ; GFX1011-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV8]](s32), [[UV9]](s32) + ; GFX1011-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV1]](s96) + ; + ; GFX12-LABEL: name: test_mul_s96 + ; GFX12: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5 + ; GFX12-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96) + ; GFX12-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96) + ; GFX12-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GFX12-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV3]], [[C]] + ; GFX12-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64) + ; GFX12-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV5]] + ; GFX12-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV4]] + ; GFX12-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]] + ; GFX12-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV2]], [[UV3]] + ; GFX12-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL2]] + ; GFX12-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[ADD1]](s32) + ; GFX12-NEXT: [[AMDGPU_MAD_U64_U32_2:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_3:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV4]], [[MV]] + ; GFX12-NEXT: [[AMDGPU_MAD_U64_U32_4:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_5:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV1]](s32), [[UV3]], [[AMDGPU_MAD_U64_U32_2]] + ; GFX12-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_4]](s64) + ; GFX12-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV8]](s32), [[UV9]](s32) + ; GFX12-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV1]](s96) %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2 %1:_(s96) = COPY $vgpr3_vgpr4_vgpr5 %2:_(s96) = G_MUL %0, %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll index eb3f74be71de..0840f58ecd1a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll @@ -4,6 +4,7 @@ ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) { ; GFX7-LABEL: s_mul_i16: @@ -31,6 +32,14 @@ define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) { ; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff ; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_and_b32 s0, s0, 0xffff +; GFX12-NEXT: s_and_b32 s1, s1, 0xffff +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s0, s0, s1 +; GFX12-NEXT: ; return to shader part epilog %result = mul i16 %num, %den ret i16 %result } @@ -61,6 +70,12 @@ define i16 @v_mul_i16(i16 %num, i16 %den) { ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10PLUS-NEXT: v_mul_lo_u16 v0, v0, v1 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_lo_u16 v0, v0, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i16 %num, %den ret i16 %result } @@ -95,6 +110,15 @@ define amdgpu_ps zeroext i16 @s_mul_i16_zeroext(i16 inreg zeroext %num, i16 inre ; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 ; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i16_zeroext: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_and_b32 s0, s0, 0xffff +; GFX12-NEXT: s_and_b32 s1, s1, 0xffff +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s0, s0, s1 +; GFX12-NEXT: s_and_b32 s0, s0, 0xffff +; GFX12-NEXT: ; return to shader part epilog %result = mul i16 %num, %den ret i16 %result } @@ -125,6 +149,14 @@ define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) { ; GFX10PLUS-NEXT: v_mul_lo_u16 v0, v0, v1 ; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i16_zeroext: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_lo_u16 v0, v0, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i16 %num, %den ret i16 %result } @@ -159,6 +191,15 @@ define amdgpu_ps signext i16 @s_mul_i16_signext(i16 inreg signext %num, i16 inre ; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 ; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i16_signext: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_and_b32 s0, s0, 0xffff +; GFX12-NEXT: s_and_b32 s1, s1, 0xffff +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s0, s0, s1 +; GFX12-NEXT: s_sext_i32_i16 s0, s0 +; GFX12-NEXT: ; return to shader part epilog %result = mul i16 %num, %den ret i16 %result } @@ -193,6 +234,14 @@ define signext i16 @v_mul_i16_signext(i16 signext %num, i16 signext %den) { ; GFX10PLUS-NEXT: v_mul_lo_u16 v0, v0, v1 ; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i16_signext: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_lo_u16 v0, v0, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i16 %num, %den ret i16 %result } @@ -207,6 +256,11 @@ define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) { ; GFX10PLUS: ; %bb.0: ; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mul_i32 s0, s0, s1 +; GFX12-NEXT: ; return to shader part epilog %result = mul i32 %num, %den ret i32 %result } @@ -223,6 +277,12 @@ define i32 @v_mul_i32(i32 %num, i32 %den) { ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10PLUS-NEXT: v_mul_lo_u32 v0, v0, v1 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_lo_u32 v0, v0, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i32 %num, %den ret i32 %result } @@ -239,6 +299,12 @@ define amdgpu_ps <2 x i32> @s_mul_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %d ; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2 ; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s3 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_v2i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mul_i32 s0, s0, s2 +; GFX12-NEXT: s_mul_i32 s1, s1, s3 +; GFX12-NEXT: ; return to shader part epilog %result = mul <2 x i32> %num, %den ret <2 x i32> %result } @@ -257,6 +323,13 @@ define <2 x i32> @v_mul_v2i32(<2 x i32> %num, <2 x i32> %den) { ; GFX10PLUS-NEXT: v_mul_lo_u32 v0, v0, v2 ; GFX10PLUS-NEXT: v_mul_lo_u32 v1, v1, v3 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_v2i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_lo_u32 v0, v0, v2 +; GFX12-NEXT: v_mul_lo_u32 v1, v1, v3 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul <2 x i32> %num, %den ret <2 x i32> %result } @@ -308,6 +381,11 @@ define amdgpu_cs i33 @s_mul_i33(i33 inreg %num, i33 inreg %den) { ; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2 ; GFX10PLUS-NEXT: s_add_i32 s1, s3, s1 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i33: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3] +; GFX12-NEXT: ; return to shader part epilog %result = mul i33 %num, %den ret i33 %result } @@ -359,6 +437,11 @@ define amdgpu_ps i64 @s_mul_i64(i64 inreg %num, i64 inreg %den) { ; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2 ; GFX10PLUS-NEXT: s_add_i32 s1, s3, s1 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3] +; GFX12-NEXT: ; return to shader part epilog %result = mul i64 %num, %den ret i64 %result } @@ -394,6 +477,17 @@ define i64 @v_mul_i64(i64 %num, i64 %den) { ; GFX11-NEXT: v_mul_lo_u32 v2, v5, v2 ; GFX11-NEXT: v_add3_u32 v1, v1, v3, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_hi_u32 v4, v0, v2 +; GFX12-NEXT: v_mul_lo_u32 v3, v0, v3 +; GFX12-NEXT: v_mul_lo_u32 v1, v1, v2 +; GFX12-NEXT: v_mul_lo_u32 v0, v0, v2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_add3_u32 v1, v4, v3, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i64 %num, %den ret i64 %result } @@ -490,6 +584,26 @@ define amdgpu_ps <3 x i32> @s_mul_i96(i96 inreg %num, i96 inreg %den) { ; GFX10PLUS-NEXT: s_addc_u32 s2, s3, s0 ; GFX10PLUS-NEXT: s_mov_b32 s0, s5 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i96: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mul_i32 s6, s0, s5 +; GFX12-NEXT: s_mul_i32 s7, s1, s4 +; GFX12-NEXT: s_mul_i32 s2, s2, s3 +; GFX12-NEXT: s_add_co_i32 s6, s6, s7 +; GFX12-NEXT: s_mul_hi_u32 s7, s0, s3 +; GFX12-NEXT: s_add_co_i32 s6, s6, s2 +; GFX12-NEXT: s_mul_i32 s2, s0, s4 +; GFX12-NEXT: s_mul_i32 s5, s0, s3 +; GFX12-NEXT: s_mul_hi_u32 s0, s0, s4 +; GFX12-NEXT: s_add_co_u32 s2, s2, s7 +; GFX12-NEXT: s_mul_i32 s4, s1, s3 +; GFX12-NEXT: s_add_co_ci_u32 s0, s0, s6 +; GFX12-NEXT: s_mul_hi_u32 s3, s1, s3 +; GFX12-NEXT: s_add_co_u32 s1, s4, s2 +; GFX12-NEXT: s_add_co_ci_u32 s2, s3, s0 +; GFX12-NEXT: s_mov_b32 s0, s5 +; GFX12-NEXT: ; return to shader part epilog %result = mul i96 %num, %den %cast = bitcast i96 %result to <3 x i32> ret <3 x i32> %cast @@ -536,6 +650,22 @@ define i96 @v_mul_i96(i96 %num, i96 %den) { ; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v6, v4, v[1:2] ; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v7, v3, v[1:2] ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i96: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1 +; GFX12-NEXT: v_mul_lo_u32 v2, v2, v3 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mul_lo_u32 v5, v6, v5 +; GFX12-NEXT: v_mul_lo_u32 v8, v7, v4 +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v6, v3, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add3_u32 v2, v5, v8, v2 +; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v6, v4, v[1:2] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v7, v3, v[1:2] +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i96 %num, %den ret i96 %result } @@ -709,6 +839,42 @@ define amdgpu_ps <4 x i32> @s_mul_i128(i128 inreg %num, i128 inreg %den) { ; GFX10PLUS-NEXT: s_mov_b32 s1, s8 ; GFX10PLUS-NEXT: s_mov_b32 s2, s7 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i128: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mul_i32 s9, s0, s6 +; GFX12-NEXT: s_mul_i32 s11, s1, s5 +; GFX12-NEXT: s_mul_hi_u32 s10, s0, s6 +; GFX12-NEXT: s_mul_hi_u32 s12, s1, s5 +; GFX12-NEXT: s_add_co_u32 s9, s11, s9 +; GFX12-NEXT: s_mul_i32 s11, s2, s4 +; GFX12-NEXT: s_add_co_ci_u32 s10, s12, s10 +; GFX12-NEXT: s_mul_hi_u32 s12, s2, s4 +; GFX12-NEXT: s_mul_hi_u32 s8, s0, s4 +; GFX12-NEXT: s_add_co_u32 s9, s11, s9 +; GFX12-NEXT: s_mul_i32 s11, s0, s5 +; GFX12-NEXT: s_add_co_ci_u32 s10, s12, s10 +; GFX12-NEXT: s_mul_hi_u32 s12, s0, s5 +; GFX12-NEXT: s_add_co_u32 s8, s11, s8 +; GFX12-NEXT: s_add_co_ci_u32 s9, s12, s9 +; GFX12-NEXT: s_mul_i32 s12, s1, s4 +; GFX12-NEXT: s_mul_hi_u32 s13, s1, s4 +; GFX12-NEXT: s_cselect_b32 s11, 1, 0 +; GFX12-NEXT: s_add_co_u32 s8, s12, s8 +; GFX12-NEXT: s_mul_i32 s12, s0, s7 +; GFX12-NEXT: s_add_co_ci_u32 s7, s13, s9 +; GFX12-NEXT: s_add_co_ci_u32 s9, s10, s12 +; GFX12-NEXT: s_mul_i32 s1, s1, s6 +; GFX12-NEXT: s_cmp_lg_u32 s11, 0 +; GFX12-NEXT: s_mul_i32 s2, s2, s5 +; GFX12-NEXT: s_add_co_ci_u32 s1, s9, s1 +; GFX12-NEXT: s_mul_i32 s3, s3, s4 +; GFX12-NEXT: s_add_co_i32 s1, s1, s2 +; GFX12-NEXT: s_mul_i32 s0, s0, s4 +; GFX12-NEXT: s_add_co_i32 s3, s1, s3 +; GFX12-NEXT: s_mov_b32 s1, s8 +; GFX12-NEXT: s_mov_b32 s2, s7 +; GFX12-NEXT: ; return to shader part epilog %result = mul i128 %num, %den %cast = bitcast i128 %result to <4 x i32> ret <4 x i32> %cast @@ -820,6 +986,32 @@ define i128 @v_mul_i128(i128 %num, i128 %den) { ; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v7, v6, vcc_lo ; GFX11-NEXT: v_add3_u32 v3, v4, v5, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i128: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v9, v1 +; GFX12-NEXT: v_mov_b32_e32 v10, v2 +; GFX12-NEXT: v_mul_lo_u32 v3, v3, v4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v8, v6, 0 +; GFX12-NEXT: v_mul_lo_u32 v7, v8, v7 +; GFX12-NEXT: v_mul_lo_u32 v6, v9, v6 +; GFX12-NEXT: v_mad_co_u64_u32 v[11:12], null, v9, v5, v[0:1] +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v8, v4, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_u64_u32 v[11:12], null, v10, v4, v[11:12] +; GFX12-NEXT: v_mov_b32_e32 v2, v11 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], vcc_lo, v8, v5, v[1:2] +; GFX12-NEXT: v_mul_lo_u32 v5, v10, v5 +; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], s0, v9, v4, v[1:2] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_co_ci_u32_e64 v7, s0, v12, v7, s0 +; GFX12-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v7, v6, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_add3_u32 v3, v4, v5, v3 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i128 %num, %den ret i128 %result } @@ -1625,6 +1817,185 @@ define amdgpu_ps <8 x i32> @s_mul_i256(i256 inreg %num, i256 inreg %den) { ; GFX10PLUS-NEXT: s_add_i32 s7, s1, s7 ; GFX10PLUS-NEXT: s_mov_b32 s1, s16 ; GFX10PLUS-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: s_mul_i256: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mul_i32 s17, s0, s10 +; GFX12-NEXT: s_mul_i32 s19, s1, s9 +; GFX12-NEXT: s_mul_hi_u32 s18, s0, s10 +; GFX12-NEXT: s_mul_hi_u32 s20, s1, s9 +; GFX12-NEXT: s_add_co_u32 s17, s19, s17 +; GFX12-NEXT: s_add_co_ci_u32 s18, s20, s18 +; GFX12-NEXT: s_mul_i32 s20, s2, s8 +; GFX12-NEXT: s_mul_hi_u32 s21, s2, s8 +; GFX12-NEXT: s_cselect_b32 s19, 1, 0 +; GFX12-NEXT: s_add_co_u32 s17, s20, s17 +; GFX12-NEXT: s_mul_hi_u32 s16, s0, s8 +; GFX12-NEXT: s_add_co_ci_u32 s18, s21, s18 +; GFX12-NEXT: s_mul_i32 s21, s0, s9 +; GFX12-NEXT: s_mul_hi_u32 s22, s0, s9 +; GFX12-NEXT: s_cselect_b32 s20, 1, 0 +; GFX12-NEXT: s_add_co_u32 s16, s21, s16 +; GFX12-NEXT: s_add_co_ci_u32 s17, s22, s17 +; GFX12-NEXT: s_mul_i32 s22, s1, s8 +; GFX12-NEXT: s_mul_hi_u32 s23, s1, s8 +; GFX12-NEXT: s_cselect_b32 s21, 1, 0 +; GFX12-NEXT: s_add_co_u32 s16, s22, s16 +; GFX12-NEXT: s_add_co_ci_u32 s17, s23, s17 +; GFX12-NEXT: s_mul_i32 s23, s0, s12 +; GFX12-NEXT: s_mul_i32 s25, s1, s11 +; GFX12-NEXT: s_mul_hi_u32 s24, s0, s12 +; GFX12-NEXT: s_mul_hi_u32 s26, s1, s11 +; GFX12-NEXT: s_cselect_b32 s22, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s25, s23 +; GFX12-NEXT: s_add_co_ci_u32 s24, s26, s24 +; GFX12-NEXT: s_mul_i32 s26, s2, s10 +; GFX12-NEXT: s_mul_hi_u32 s27, s2, s10 +; GFX12-NEXT: s_cselect_b32 s25, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s26, s23 +; GFX12-NEXT: s_add_co_ci_u32 s24, s27, s24 +; GFX12-NEXT: s_mul_i32 s27, s3, s9 +; GFX12-NEXT: s_mul_hi_u32 s28, s3, s9 +; GFX12-NEXT: s_cselect_b32 s26, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s27, s23 +; GFX12-NEXT: s_add_co_ci_u32 s24, s28, s24 +; GFX12-NEXT: s_mul_i32 s28, s4, s8 +; GFX12-NEXT: s_mul_hi_u32 s29, s4, s8 +; GFX12-NEXT: s_cselect_b32 s27, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s28, s23 +; GFX12-NEXT: s_add_co_ci_u32 s24, s29, s24 +; GFX12-NEXT: s_mul_i32 s29, s0, s11 +; GFX12-NEXT: s_mul_hi_u32 s30, s0, s11 +; GFX12-NEXT: s_cselect_b32 s28, 1, 0 +; GFX12-NEXT: s_add_co_u32 s18, s29, s18 +; GFX12-NEXT: s_add_co_ci_u32 s23, s30, s23 +; GFX12-NEXT: s_mul_i32 s30, s1, s10 +; GFX12-NEXT: s_mul_hi_u32 s31, s1, s10 +; GFX12-NEXT: s_cselect_b32 s29, 1, 0 +; GFX12-NEXT: s_add_co_u32 s18, s30, s18 +; GFX12-NEXT: s_add_co_ci_u32 s23, s31, s23 +; GFX12-NEXT: s_mul_i32 s31, s2, s9 +; GFX12-NEXT: s_mul_hi_u32 s33, s2, s9 +; GFX12-NEXT: s_cselect_b32 s30, 1, 0 +; GFX12-NEXT: s_add_co_u32 s18, s31, s18 +; GFX12-NEXT: s_add_co_ci_u32 s23, s33, s23 +; GFX12-NEXT: s_mul_i32 s33, s3, s8 +; GFX12-NEXT: s_mul_hi_u32 s34, s3, s8 +; GFX12-NEXT: s_cselect_b32 s31, 1, 0 +; GFX12-NEXT: s_add_co_u32 s18, s33, s18 +; GFX12-NEXT: s_add_co_ci_u32 s23, s34, s23 +; GFX12-NEXT: s_cselect_b32 s33, 1, 0 +; GFX12-NEXT: s_cmp_lg_u32 s22, 0 +; GFX12-NEXT: s_mul_hi_u32 s22, s0, s14 +; GFX12-NEXT: s_add_co_ci_u32 s18, s21, s18 +; GFX12-NEXT: s_cselect_b32 s21, 1, 0 +; GFX12-NEXT: s_cmp_lg_u32 s20, 0 +; GFX12-NEXT: s_mul_hi_u32 s34, s1, s13 +; GFX12-NEXT: s_add_co_ci_u32 s19, s19, 0 +; GFX12-NEXT: s_cmp_lg_u32 s21, 0 +; GFX12-NEXT: s_mul_i32 s21, s0, s14 +; GFX12-NEXT: s_add_co_ci_u32 s19, s19, s23 +; GFX12-NEXT: s_mul_i32 s23, s1, s13 +; GFX12-NEXT: s_cselect_b32 s20, 1, 0 +; GFX12-NEXT: s_add_co_u32 s21, s23, s21 +; GFX12-NEXT: s_mul_i32 s23, s2, s12 +; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s22 +; GFX12-NEXT: s_mul_hi_u32 s34, s2, s12 +; GFX12-NEXT: s_add_co_u32 s21, s23, s21 +; GFX12-NEXT: s_mul_i32 s23, s3, s11 +; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s22 +; GFX12-NEXT: s_mul_hi_u32 s34, s3, s11 +; GFX12-NEXT: s_add_co_u32 s21, s23, s21 +; GFX12-NEXT: s_mul_i32 s23, s4, s10 +; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s22 +; GFX12-NEXT: s_mul_hi_u32 s34, s4, s10 +; GFX12-NEXT: s_add_co_u32 s21, s23, s21 +; GFX12-NEXT: s_mul_i32 s23, s5, s9 +; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s22 +; GFX12-NEXT: s_mul_hi_u32 s34, s5, s9 +; GFX12-NEXT: s_add_co_u32 s21, s23, s21 +; GFX12-NEXT: s_mul_i32 s23, s6, s8 +; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s22 +; GFX12-NEXT: s_mul_hi_u32 s34, s6, s8 +; GFX12-NEXT: s_add_co_u32 s21, s23, s21 +; GFX12-NEXT: s_mul_i32 s23, s0, s13 +; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s22 +; GFX12-NEXT: s_mul_hi_u32 s34, s0, s13 +; GFX12-NEXT: s_add_co_u32 s23, s23, s24 +; GFX12-NEXT: s_add_co_ci_u32 s21, s34, s21 +; GFX12-NEXT: s_mul_i32 s34, s1, s12 +; GFX12-NEXT: s_mul_hi_u32 s35, s1, s12 +; GFX12-NEXT: s_cselect_b32 s24, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s34, s23 +; GFX12-NEXT: s_add_co_ci_u32 s21, s35, s21 +; GFX12-NEXT: s_mul_i32 s35, s2, s11 +; GFX12-NEXT: s_mul_hi_u32 s36, s2, s11 +; GFX12-NEXT: s_cselect_b32 s34, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s35, s23 +; GFX12-NEXT: s_add_co_ci_u32 s21, s36, s21 +; GFX12-NEXT: s_mul_i32 s36, s3, s10 +; GFX12-NEXT: s_mul_hi_u32 s37, s3, s10 +; GFX12-NEXT: s_cselect_b32 s35, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s36, s23 +; GFX12-NEXT: s_add_co_ci_u32 s21, s37, s21 +; GFX12-NEXT: s_mul_i32 s37, s4, s9 +; GFX12-NEXT: s_mul_hi_u32 s38, s4, s9 +; GFX12-NEXT: s_cselect_b32 s36, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s37, s23 +; GFX12-NEXT: s_add_co_ci_u32 s21, s38, s21 +; GFX12-NEXT: s_mul_i32 s38, s5, s8 +; GFX12-NEXT: s_mul_hi_u32 s39, s5, s8 +; GFX12-NEXT: s_cselect_b32 s37, 1, 0 +; GFX12-NEXT: s_add_co_u32 s23, s38, s23 +; GFX12-NEXT: s_add_co_ci_u32 s21, s39, s21 +; GFX12-NEXT: s_cselect_b32 s38, 1, 0 +; GFX12-NEXT: s_cmp_lg_u32 s30, 0 +; GFX12-NEXT: s_mul_i32 s1, s1, s14 +; GFX12-NEXT: s_add_co_ci_u32 s29, s29, 0 +; GFX12-NEXT: s_cmp_lg_u32 s31, 0 +; GFX12-NEXT: s_mul_i32 s2, s2, s13 +; GFX12-NEXT: s_add_co_ci_u32 s29, s29, 0 +; GFX12-NEXT: s_cmp_lg_u32 s33, 0 +; GFX12-NEXT: s_mul_i32 s3, s3, s12 +; GFX12-NEXT: s_add_co_ci_u32 s29, s29, 0 +; GFX12-NEXT: s_cmp_lg_u32 s20, 0 +; GFX12-NEXT: s_mul_i32 s4, s4, s11 +; GFX12-NEXT: s_add_co_ci_u32 s20, s29, s23 +; GFX12-NEXT: s_cselect_b32 s23, 1, 0 +; GFX12-NEXT: s_cmp_lg_u32 s26, 0 +; GFX12-NEXT: s_mul_i32 s26, s0, s15 +; GFX12-NEXT: s_add_co_ci_u32 s25, s25, 0 +; GFX12-NEXT: s_cmp_lg_u32 s27, 0 +; GFX12-NEXT: s_mul_i32 s5, s5, s10 +; GFX12-NEXT: s_add_co_ci_u32 s25, s25, 0 +; GFX12-NEXT: s_cmp_lg_u32 s28, 0 +; GFX12-NEXT: s_mul_i32 s6, s6, s9 +; GFX12-NEXT: s_add_co_ci_u32 s25, s25, 0 +; GFX12-NEXT: s_cmp_lg_u32 s23, 0 +; GFX12-NEXT: s_mul_i32 s7, s7, s8 +; GFX12-NEXT: s_add_co_ci_u32 s15, s25, s21 +; GFX12-NEXT: s_add_co_ci_u32 s21, s22, s26 +; GFX12-NEXT: s_cmp_lg_u32 s38, 0 +; GFX12-NEXT: s_mul_i32 s0, s0, s8 +; GFX12-NEXT: s_add_co_ci_u32 s1, s21, s1 +; GFX12-NEXT: s_cmp_lg_u32 s37, 0 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s2 +; GFX12-NEXT: s_cmp_lg_u32 s36, 0 +; GFX12-NEXT: s_mov_b32 s2, s17 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s3 +; GFX12-NEXT: s_cmp_lg_u32 s35, 0 +; GFX12-NEXT: s_mov_b32 s3, s18 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s4 +; GFX12-NEXT: s_cmp_lg_u32 s34, 0 +; GFX12-NEXT: s_mov_b32 s4, s19 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s5 +; GFX12-NEXT: s_cmp_lg_u32 s24, 0 +; GFX12-NEXT: s_mov_b32 s5, s20 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s6 +; GFX12-NEXT: s_mov_b32 s6, s15 +; GFX12-NEXT: s_add_co_i32 s7, s1, s7 +; GFX12-NEXT: s_mov_b32 s1, s16 +; GFX12-NEXT: ; return to shader part epilog %result = mul i256 %num, %den %cast = bitcast i256 %result to <8 x i32> ret <8 x i32> %cast @@ -1978,6 +2349,454 @@ define i256 @v_mul_i256(i256 %num, i256 %den) { ; GFX11-NEXT: v_add_co_ci_u32_e64 v8, vcc_lo, v9, v27, s0 ; GFX11-NEXT: v_add_nc_u32_e32 v7, v8, v7 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_mul_i256: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1 +; GFX12-NEXT: v_mul_lo_u32 v27, v6, v9 +; GFX12-NEXT: v_mul_lo_u32 v7, v7, v8 +; GFX12-NEXT: v_mul_lo_u32 v28, v5, v10 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v16, v14, 0 +; GFX12-NEXT: v_mad_co_u64_u32 v[18:19], null, v16, v12, 0 +; GFX12-NEXT: v_mul_lo_u32 v30, v17, v14 +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v17, v13, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_u64_u32 v[18:19], s0, v17, v11, v[18:19] +; GFX12-NEXT: v_cndmask_b32_e64 v20, 0, 1, s0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v2, v12, v[0:1] +; GFX12-NEXT: v_mad_co_u64_u32 v[18:19], vcc_lo, v2, v10, v[18:19] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo +; GFX12-NEXT: v_mad_co_u64_u32 v[20:21], null, v16, v10, 0 +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v3, v11, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_mad_co_u64_u32 v[18:19], vcc_lo, v3, v9, v[18:19] +; GFX12-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v4, v10, v[0:1] +; GFX12-NEXT: v_mad_co_u64_u32 v[18:19], vcc_lo, v4, v8, v[18:19] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_add_co_ci_u32_e32 v26, vcc_lo, 0, v24, vcc_lo +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v5, v9, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_u64_u32 v[22:23], null, v6, v8, v[0:1] +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], s0, v17, v9, v[20:21] +; GFX12-NEXT: v_cndmask_b32_e64 v25, 0, 1, s0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mov_b32_e32 v20, v22 +; GFX12-NEXT: v_mad_co_u64_u32 v[21:22], vcc_lo, v2, v8, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_add_co_ci_u32_e32 v29, vcc_lo, 0, v25, vcc_lo +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], s0, v16, v13, v[19:20] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mov_b32_e32 v19, v22 +; GFX12-NEXT: v_mul_lo_u32 v22, v16, v15 +; GFX12-NEXT: v_mad_co_u64_u32 v[24:25], vcc_lo, v17, v12, v[0:1] +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v16, v8, 0 +; GFX12-NEXT: v_mov_b32_e32 v20, v18 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_mad_co_u64_u32 v[14:15], s2, v16, v11, v[19:20] +; GFX12-NEXT: v_mad_co_u64_u32 v[18:19], s1, v2, v11, v[24:25] +; GFX12-NEXT: v_mul_lo_u32 v20, v4, v11 +; GFX12-NEXT: v_mul_lo_u32 v25, v3, v12 +; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2 +; GFX12-NEXT: v_mul_lo_u32 v24, v2, v13 +; GFX12-NEXT: v_mov_b32_e32 v13, v1 +; GFX12-NEXT: v_mad_co_u64_u32 v[11:12], s2, v17, v10, v[14:15] +; GFX12-NEXT: v_mad_co_u64_u32 v[18:19], s3, v3, v10, v[18:19] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, s2, 0, v6, s2 +; GFX12-NEXT: v_mov_b32_e32 v14, v21 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], s2, v2, v9, v[11:12] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, s2, 0, v6, s2 +; GFX12-NEXT: v_mad_co_u64_u32 v[10:11], s2, v4, v9, v[18:19] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_u64_u32 v[12:13], s4, v16, v9, v[13:14] +; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4 +; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], s4, v3, v8, v[1:2] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_co_ci_u32_e64 v14, s4, 0, v6, s4 +; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], s4, v5, v8, v[10:11] +; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], s5, v17, v8, v[12:13] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, s5, v9, v3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_co_ci_u32_e64 v4, s5, v29, v4, s5 +; GFX12-NEXT: v_add_co_ci_u32_e64 v5, s5, v14, v5, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, s5, v26, v6, s5 +; GFX12-NEXT: v_add_co_ci_u32_e64 v9, s5, v23, v22, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_co_ci_u32_e64 v9, s4, v9, v30, s4 +; GFX12-NEXT: v_add_co_ci_u32_e64 v9, s2, v9, v24, s2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_co_ci_u32_e64 v9, s2, v9, v25, s3 +; GFX12-NEXT: v_add_co_ci_u32_e64 v9, s1, v9, v20, s1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v9, v28, vcc_lo +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, vcc_lo, v9, v27, s0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_add_nc_u32_e32 v7, v8, v7 +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = mul i256 %num, %den ret i256 %result } + +define amdgpu_ps void @s_mul_u64_zext_with_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GFX7-LABEL: s_mul_u64_zext_with_vregs: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b64 s[0:1], 0 +; GFX7-NEXT: buffer_load_dword v2, v[2:3], s[0:3], 0 addr64 +; GFX7-NEXT: v_mov_b32_e32 v3, 0x50 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, v3, 0 +; GFX7-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: s_mul_u64_zext_with_vregs: +; GFX8: ; %bb.0: +; GFX8-NEXT: flat_load_dword v2, v[2:3] +; GFX8-NEXT: v_mov_b32_e32 v3, 0x50 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, v3, 0 +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: s_mul_u64_zext_with_vregs: +; GFX9: ; %bb.0: +; GFX9-NEXT: global_load_dword v2, v[2:3], off +; GFX9-NEXT: v_mov_b32_e32 v3, 0x50 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, v3, 0 +; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: s_mul_u64_zext_with_vregs: +; GFX10: ; %bb.0: +; GFX10-NEXT: global_load_dword v2, v[2:3], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, 0x50, v2, 0 +; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: s_mul_u64_zext_with_vregs: +; GFX11: ; %bb.0: +; GFX11-NEXT: global_load_b32 v2, v[2:3], off +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0x50, v2, 0 +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_nop 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: s_mul_u64_zext_with_vregs: +; GFX12: ; %bb.0: +; GFX12-NEXT: global_load_b32 v2, v[2:3], off +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, 0x50, v2, 0 +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm + %val = load i32, ptr addrspace(1) %in, align 4 + %ext = zext i32 %val to i64 + %mul = mul i64 %ext, 80 + store i64 %mul, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_kernel void @s_mul_u64_zext_with_sregs(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GFX7-LABEL: s_mul_u64_zext_with_sregs: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GFX7-NEXT: v_mov_b32_e32 v0, 0x50 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s3, s[2:3], 0x0 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mul_hi_u32 v0, s3, v0 +; GFX7-NEXT: s_mul_i32 s4, s3, 0x50 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_readfirstlane_b32 s5, v0 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: s_mul_u64_zext_with_sregs: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v0, 0x50 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 +; GFX8-NEXT: s_mulk_i32 s2, 0x50 +; GFX8-NEXT: v_readfirstlane_b32 s3, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: s_mul_u64_zext_with_sregs: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s3, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_mul_i32 s2, s3, 0x50 +; GFX9-NEXT: s_mul_hi_u32 s3, s3, 0x50 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: s_mul_u64_zext_with_sregs: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_load_dword s3, s[2:3], 0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_mul_i32 s2, s3, 0x50 +; GFX10-NEXT: s_mul_hi_u32 s3, s3, 0x50 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: s_mul_u64_zext_with_sregs: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s3, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_mul_i32 s2, s3, 0x50 +; GFX11-NEXT: s_mul_hi_u32 s3, s3, 0x50 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_nop 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: s_mul_u64_zext_with_sregs: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX12-NEXT: s_mov_b32 s3, 0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mul_u64 s[2:3], s[2:3], 0x50 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm + %val = load i32, ptr addrspace(1) %in, align 4 + %ext = zext i32 %val to i64 + %mul = mul i64 %ext, 80 + store i64 %mul, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @s_mul_u64_sext_with_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GFX7-LABEL: s_mul_u64_sext_with_vregs: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b64 s[0:1], 0 +; GFX7-NEXT: buffer_load_dword v4, v[2:3], s[0:3], 0 addr64 +; GFX7-NEXT: v_mov_b32_e32 v5, 0x50 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v5, 0 +; GFX7-NEXT: v_ashrrev_i32_e32 v4, 31, v4 +; GFX7-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v5, v[3:4] +; GFX7-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: s_mul_u64_sext_with_vregs: +; GFX8: ; %bb.0: +; GFX8-NEXT: flat_load_dword v4, v[2:3] +; GFX8-NEXT: v_mov_b32_e32 v5, 0x50 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v5, 0 +; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v4 +; GFX8-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v4, v5, v[3:4] +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: s_mul_u64_sext_with_vregs: +; GFX9: ; %bb.0: +; GFX9-NEXT: global_load_dword v4, v[2:3], off +; GFX9-NEXT: v_mov_b32_e32 v5, 0x50 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v5, 0 +; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v4 +; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v4, v5, v[3:4] +; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: s_mul_u64_sext_with_vregs: +; GFX10: ; %bb.0: +; GFX10-NEXT: global_load_dword v2, v[2:3], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v2 +; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, 0x50, v2, 0 +; GFX10-NEXT: v_mul_lo_u32 v4, 0x50, v4 +; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4 +; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: s_mul_u64_sext_with_vregs: +; GFX11: ; %bb.0: +; GFX11-NEXT: global_load_b32 v2, v[2:3], off +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v2 +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0x50, v2, 0 +; GFX11-NEXT: v_mul_lo_u32 v4, 0x50, v4 +; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4 +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_nop 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: s_mul_u64_sext_with_vregs: +; GFX12: ; %bb.0: +; GFX12-NEXT: global_load_b32 v2, v[2:3], off +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mad_co_i64_i32 v[2:3], null, 0x50, v2, 0 +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm + %val = load i32, ptr addrspace(1) %in, align 4 + %ext = sext i32 %val to i64 + %mul = mul i64 %ext, 80 + store i64 %mul, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_kernel void @s_mul_u64_sext_with_sregs(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GFX7-LABEL: s_mul_u64_sext_with_sregs: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GFX7-NEXT: v_mov_b32_e32 v0, 0x50 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s3, s[2:3], 0x0 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mul_hi_u32 v0, s3, v0 +; GFX7-NEXT: s_ashr_i32 s5, s3, 31 +; GFX7-NEXT: s_mul_i32 s4, s3, 0x50 +; GFX7-NEXT: s_mulk_i32 s5, 0x50 +; GFX7-NEXT: v_readfirstlane_b32 s3, v0 +; GFX7-NEXT: s_add_u32 s5, s5, s3 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: s_mul_u64_sext_with_sregs: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v0, 0x50 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 +; GFX8-NEXT: s_ashr_i32 s3, s2, 31 +; GFX8-NEXT: s_mulk_i32 s2, 0x50 +; GFX8-NEXT: s_mulk_i32 s3, 0x50 +; GFX8-NEXT: v_readfirstlane_b32 s4, v0 +; GFX8-NEXT: s_add_u32 s3, s3, s4 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: s_mul_u64_sext_with_sregs: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s3, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_ashr_i32 s4, s3, 31 +; GFX9-NEXT: s_mul_i32 s2, s3, 0x50 +; GFX9-NEXT: s_mul_hi_u32 s3, s3, 0x50 +; GFX9-NEXT: s_mulk_i32 s4, 0x50 +; GFX9-NEXT: s_add_u32 s3, s4, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: s_mul_u64_sext_with_sregs: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_ashr_i32 s3, s2, 31 +; GFX10-NEXT: s_mul_hi_u32 s4, s2, 0x50 +; GFX10-NEXT: s_mulk_i32 s3, 0x50 +; GFX10-NEXT: s_mulk_i32 s2, 0x50 +; GFX10-NEXT: s_add_i32 s3, s4, s3 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: s_mul_u64_sext_with_sregs: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_ashr_i32 s3, s2, 31 +; GFX11-NEXT: s_mul_hi_u32 s4, s2, 0x50 +; GFX11-NEXT: s_mulk_i32 s3, 0x50 +; GFX11-NEXT: s_mulk_i32 s2, 0x50 +; GFX11-NEXT: s_add_i32 s3, s4, s3 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_nop 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: s_mul_u64_sext_with_sregs: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_u64 s[2:3], s[2:3], 0x50 +; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm + %val = load i32, ptr addrspace(1) %in, align 4 + %ext = sext i32 %val to i64 + %mul = mul i64 %ext, 80 + store i64 %mul, ptr addrspace(1) %out, align 8 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir new file mode 100644 index 000000000000..f74a575ac931 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -march=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s + +--- +name: mul_s64 +body: | + bb.0: + liveins: $vgpr0_vgpr1 + ; CHECK-LABEL: name: mul_s64 + ; CHECK: liveins: $vgpr0_vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12345 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[C]] + ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MUL]](s64) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = G_CONSTANT i64 12345 + %2:_(s64) = G_MUL %0, %1 + $vgpr0_vgpr1 = COPY %2 +... + +--- +name: mul_s64_zext +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: mul_s64_zext + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12345 + ; CHECK-NEXT: [[AMDGPU_:%[0-9]+]]:_(s64) = G_AMDGPU_S_MUL_U64_U32 [[ZEXT]], [[C]] + ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_]](s64) + %0:_(s32) = COPY $vgpr0 + %1:_(s64) = G_ZEXT %0 + %2:_(s64) = G_CONSTANT i64 12345 + %3:_(s64) = G_MUL %1, %2 + $vgpr0_vgpr1 = COPY %3 +... + +--- +name: mul_s64_sext +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: mul_s64_sext + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12345 + ; CHECK-NEXT: [[AMDGPU_:%[0-9]+]]:_(s64) = G_AMDGPU_S_MUL_I64_I32 [[SEXT]], [[C]] + ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_]](s64) + %0:_(s32) = COPY $vgpr0 + %1:_(s64) = G_SEXT %0 + %2:_(s64) = G_CONSTANT i64 12345 + %3:_(s64) = G_MUL %1, %2 + $vgpr0_vgpr1 = COPY %3 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir index a5b61641e0c2..a6cc6c92d9f8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir @@ -74,3 +74,125 @@ body: | %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_MUL %0, %1 ... + +--- +name: mul_s64_ss +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-LABEL: name: mul_s64_ss + ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:sgpr(s64) = G_MUL [[COPY]], [[COPY1]] + %0:_(s64) = COPY $sgpr0_sgpr1 + %1:_(s64) = COPY $sgpr2_sgpr3 + %2:_(s64) = G_MUL %0, %1 +... + +--- +name: mul_s64_vv +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-LABEL: name: mul_s64_vv + ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64) + ; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY1]](s64) + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[UV]], [[UV2]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[UV]], [[UV3]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[UMULH]], [[MUL]] + ; CHECK-NEXT: [[MUL1:%[0-9]+]]:vgpr(s32) = G_MUL [[UV1]], [[UV2]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[MUL1]] + ; CHECK-NEXT: [[MUL2:%[0-9]+]]:vgpr(s32) = G_MUL [[UV]], [[UV2]] + ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[MUL2]](s32), [[ADD1]](s32) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s64) = G_MUL %0, %1 +... + +--- +name: mul_s64_zext_ss +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-LABEL: name: mul_s64_zext_ss + ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr2_sgpr3 + ; CHECK-NEXT: [[S_MUL_U64_:%[0-9]+]]:sgpr_64(s64) = S_MUL_U64 [[COPY]](s64), [[COPY1]](s64) + %0:_(s64) = COPY $sgpr0_sgpr1 + %1:_(s64) = COPY $sgpr2_sgpr3 + %2:_(s64) = G_AMDGPU_S_MUL_U64_U32 %0, %1 +... + +--- +name: mul_s64_zext_vv +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-LABEL: name: mul_s64_zext_vv + ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:vreg_64(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vreg_64 = G_AMDGPU_MAD_U64_U32 [[TRUNC]](s32), [[TRUNC1]], [[C]] + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s64) = G_AMDGPU_S_MUL_U64_U32 %0, %1 +... + +--- +name: mul_s64_sext_ss +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-LABEL: name: mul_s64_sext_ss + ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr2_sgpr3 + ; CHECK-NEXT: [[S_MUL_U64_:%[0-9]+]]:sgpr_64(s64) = S_MUL_U64 [[COPY]](s64), [[COPY1]](s64) + %0:_(s64) = COPY $sgpr0_sgpr1 + %1:_(s64) = COPY $sgpr2_sgpr3 + %2:_(s64) = G_AMDGPU_S_MUL_I64_I32 %0, %1 +... + +--- +name: mul_s64_sext_vv +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-LABEL: name: mul_s64_sext_vv + ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:vreg_64(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[AMDGPU_MAD_I64_I32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_I64_I32_1:%[0-9]+]]:vreg_64 = G_AMDGPU_MAD_I64_I32 [[TRUNC]](s32), [[TRUNC1]], [[C]] + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s64) = G_AMDGPU_S_MUL_I64_I32 %0, %1 +... diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll index 26d981ad7b4b..b4c8da44337a 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll @@ -1259,20 +1259,21 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1264: ; %bb.0: ; %entry ; GFX1264-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX1264-NEXT: s_mov_b64 s[6:7], exec -; GFX1264-NEXT: s_mov_b64 s[4:5], exec +; GFX1264-NEXT: s_mov_b32 s9, 0 ; GFX1264-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX1264-NEXT: s_mov_b64 s[4:5], exec ; GFX1264-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1264-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX1264-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1264-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1264-NEXT: s_cbranch_execz .LBB3_2 ; GFX1264-NEXT: ; %bb.1: -; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7] -; GFX1264-NEXT: v_mov_b32_e32 v1, 0 -; GFX1264-NEXT: s_mul_i32 s6, s6, 5 +; GFX1264-NEXT: s_bcnt1_i32_b64 s8, s[6:7] ; GFX1264-NEXT: s_mov_b32 s11, 0x31016000 -; GFX1264-NEXT: v_mov_b32_e32 v0, s6 +; GFX1264-NEXT: s_mul_u64 s[6:7], s[8:9], 5 ; GFX1264-NEXT: s_mov_b32 s10, -1 +; GFX1264-NEXT: v_mov_b32_e32 v0, s6 +; GFX1264-NEXT: v_mov_b32_e32 v1, s7 ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) ; GFX1264-NEXT: s_mov_b32 s8, s2 ; GFX1264-NEXT: s_mov_b32 s9, s3 @@ -1296,19 +1297,20 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-LABEL: add_i64_constant: ; GFX1232: ; %bb.0: ; %entry ; GFX1232-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX1232-NEXT: s_mov_b32 s5, exec_lo ; GFX1232-NEXT: s_mov_b32 s4, exec_lo -; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0 +; GFX1232-NEXT: s_mov_b32 s5, 0 +; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s4, 0 +; GFX1232-NEXT: s_mov_b32 s6, exec_lo ; GFX1232-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1232-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1232-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1232-NEXT: s_cbranch_execz .LBB3_2 ; GFX1232-NEXT: ; %bb.1: -; GFX1232-NEXT: s_bcnt1_i32_b32 s5, s5 +; GFX1232-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX1232-NEXT: s_mov_b32 s11, 0x31016000 -; GFX1232-NEXT: s_mul_i32 s5, s5, 5 +; GFX1232-NEXT: s_mul_u64 s[4:5], s[4:5], 5 ; GFX1232-NEXT: s_mov_b32 s10, -1 -; GFX1232-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, 0 +; GFX1232-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) ; GFX1232-NEXT: s_mov_b32 s8, s2 ; GFX1232-NEXT: s_mov_b32 s9, s3 @@ -1316,7 +1318,7 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-NEXT: s_waitcnt vmcnt(0) ; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB3_2: -; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s6 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) ; GFX1232-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1232-NEXT: v_readfirstlane_b32 s3, v1 @@ -1643,23 +1645,21 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX1264-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 ; GFX1264-NEXT: s_mov_b64 s[8:9], exec -; GFX1264-NEXT: s_mov_b64 s[2:3], exec +; GFX1264-NEXT: s_mov_b32 s11, 0 ; GFX1264-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 +; GFX1264-NEXT: s_mov_b64 s[2:3], exec ; GFX1264-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1264-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX1264-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1264-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1264-NEXT: s_cbranch_execz .LBB4_2 ; GFX1264-NEXT: ; %bb.1: -; GFX1264-NEXT: s_bcnt1_i32_b64 s8, s[8:9] -; GFX1264-NEXT: s_mov_b32 s11, 0x31016000 +; GFX1264-NEXT: s_bcnt1_i32_b64 s10, s[8:9] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) -; GFX1264-NEXT: s_mul_i32 s9, s1, s8 -; GFX1264-NEXT: s_mul_hi_u32 s10, s0, s8 -; GFX1264-NEXT: s_mul_i32 s8, s0, s8 -; GFX1264-NEXT: s_add_co_i32 s10, s10, s9 +; GFX1264-NEXT: s_mul_u64 s[8:9], s[0:1], s[10:11] +; GFX1264-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1264-NEXT: v_mov_b32_e32 v0, s8 -; GFX1264-NEXT: v_mov_b32_e32 v1, s10 +; GFX1264-NEXT: v_mov_b32_e32 v1, s9 ; GFX1264-NEXT: s_mov_b32 s10, -1 ; GFX1264-NEXT: s_mov_b32 s8, s6 ; GFX1264-NEXT: s_mov_b32 s9, s7 @@ -1687,31 +1687,28 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_clause 0x1 ; GFX1232-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX1232-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 -; GFX1232-NEXT: s_mov_b32 s3, exec_lo ; GFX1232-NEXT: s_mov_b32 s2, exec_lo -; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s3, 0 +; GFX1232-NEXT: s_mov_b32 s3, 0 +; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s2, 0 +; GFX1232-NEXT: s_mov_b32 s8, exec_lo ; GFX1232-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1232-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1232-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1232-NEXT: s_cbranch_execz .LBB4_2 ; GFX1232-NEXT: ; %bb.1: -; GFX1232-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1232-NEXT: s_mov_b32 s11, 0x31016000 +; GFX1232-NEXT: s_bcnt1_i32_b32 s2, s2 +; GFX1232-NEXT: s_mov_b32 s15, 0x31016000 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) -; GFX1232-NEXT: s_mul_i32 s8, s1, s3 -; GFX1232-NEXT: s_mul_hi_u32 s9, s0, s3 -; GFX1232-NEXT: s_mul_i32 s3, s0, s3 -; GFX1232-NEXT: s_add_co_i32 s9, s9, s8 -; GFX1232-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1232-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s9 -; GFX1232-NEXT: s_mov_b32 s10, -1 -; GFX1232-NEXT: s_mov_b32 s8, s6 -; GFX1232-NEXT: s_mov_b32 s9, s7 -; GFX1232-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN +; GFX1232-NEXT: s_mul_u64 s[2:3], s[0:1], s[2:3] +; GFX1232-NEXT: s_mov_b32 s14, -1 +; GFX1232-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX1232-NEXT: s_mov_b32 s12, s6 +; GFX1232-NEXT: s_mov_b32 s13, s7 +; GFX1232-NEXT: buffer_atomic_add_u64 v[0:1], off, s[12:15], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) ; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB4_2: -; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s8 ; GFX1232-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1232-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) @@ -3182,20 +3179,21 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1264: ; %bb.0: ; %entry ; GFX1264-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX1264-NEXT: s_mov_b64 s[6:7], exec -; GFX1264-NEXT: s_mov_b64 s[4:5], exec +; GFX1264-NEXT: s_mov_b32 s9, 0 ; GFX1264-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX1264-NEXT: s_mov_b64 s[4:5], exec ; GFX1264-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1264-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX1264-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1264-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1264-NEXT: s_cbranch_execz .LBB9_2 ; GFX1264-NEXT: ; %bb.1: -; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7] -; GFX1264-NEXT: v_mov_b32_e32 v1, 0 -; GFX1264-NEXT: s_mul_i32 s6, s6, 5 +; GFX1264-NEXT: s_bcnt1_i32_b64 s8, s[6:7] ; GFX1264-NEXT: s_mov_b32 s11, 0x31016000 -; GFX1264-NEXT: v_mov_b32_e32 v0, s6 +; GFX1264-NEXT: s_mul_u64 s[6:7], s[8:9], 5 ; GFX1264-NEXT: s_mov_b32 s10, -1 +; GFX1264-NEXT: v_mov_b32_e32 v0, s6 +; GFX1264-NEXT: v_mov_b32_e32 v1, s7 ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) ; GFX1264-NEXT: s_mov_b32 s8, s2 ; GFX1264-NEXT: s_mov_b32 s9, s3 @@ -3222,19 +3220,20 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-LABEL: sub_i64_constant: ; GFX1232: ; %bb.0: ; %entry ; GFX1232-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX1232-NEXT: s_mov_b32 s5, exec_lo ; GFX1232-NEXT: s_mov_b32 s4, exec_lo -; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0 +; GFX1232-NEXT: s_mov_b32 s5, 0 +; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s4, 0 +; GFX1232-NEXT: s_mov_b32 s6, exec_lo ; GFX1232-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1232-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1232-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1232-NEXT: s_cbranch_execz .LBB9_2 ; GFX1232-NEXT: ; %bb.1: -; GFX1232-NEXT: s_bcnt1_i32_b32 s5, s5 +; GFX1232-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX1232-NEXT: s_mov_b32 s11, 0x31016000 -; GFX1232-NEXT: s_mul_i32 s5, s5, 5 +; GFX1232-NEXT: s_mul_u64 s[4:5], s[4:5], 5 ; GFX1232-NEXT: s_mov_b32 s10, -1 -; GFX1232-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, 0 +; GFX1232-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) ; GFX1232-NEXT: s_mov_b32 s8, s2 ; GFX1232-NEXT: s_mov_b32 s9, s3 @@ -3242,7 +3241,7 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1232-NEXT: s_waitcnt vmcnt(0) ; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB9_2: -; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s6 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) ; GFX1232-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1232-NEXT: v_mul_u32_u24_e32 v0, 5, v2 @@ -3585,23 +3584,21 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1264-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX1264-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 ; GFX1264-NEXT: s_mov_b64 s[8:9], exec -; GFX1264-NEXT: s_mov_b64 s[2:3], exec +; GFX1264-NEXT: s_mov_b32 s11, 0 ; GFX1264-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 +; GFX1264-NEXT: s_mov_b64 s[2:3], exec ; GFX1264-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1264-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX1264-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1264-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1264-NEXT: s_cbranch_execz .LBB10_2 ; GFX1264-NEXT: ; %bb.1: -; GFX1264-NEXT: s_bcnt1_i32_b64 s8, s[8:9] -; GFX1264-NEXT: s_mov_b32 s11, 0x31016000 +; GFX1264-NEXT: s_bcnt1_i32_b64 s10, s[8:9] ; GFX1264-NEXT: s_waitcnt lgkmcnt(0) -; GFX1264-NEXT: s_mul_i32 s9, s1, s8 -; GFX1264-NEXT: s_mul_hi_u32 s10, s0, s8 -; GFX1264-NEXT: s_mul_i32 s8, s0, s8 -; GFX1264-NEXT: s_add_co_i32 s10, s10, s9 +; GFX1264-NEXT: s_mul_u64 s[8:9], s[0:1], s[10:11] +; GFX1264-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1264-NEXT: v_mov_b32_e32 v0, s8 -; GFX1264-NEXT: v_mov_b32_e32 v1, s10 +; GFX1264-NEXT: v_mov_b32_e32 v1, s9 ; GFX1264-NEXT: s_mov_b32 s10, -1 ; GFX1264-NEXT: s_mov_b32 s8, s6 ; GFX1264-NEXT: s_mov_b32 s9, s7 @@ -3632,31 +3629,28 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1232-NEXT: s_clause 0x1 ; GFX1232-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX1232-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 -; GFX1232-NEXT: s_mov_b32 s3, exec_lo ; GFX1232-NEXT: s_mov_b32 s2, exec_lo -; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s3, 0 +; GFX1232-NEXT: s_mov_b32 s3, 0 +; GFX1232-NEXT: v_mbcnt_lo_u32_b32 v2, s2, 0 +; GFX1232-NEXT: s_mov_b32 s8, exec_lo ; GFX1232-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1232-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1232-NEXT: v_cmpx_eq_u32_e32 0, v2 ; GFX1232-NEXT: s_cbranch_execz .LBB10_2 ; GFX1232-NEXT: ; %bb.1: -; GFX1232-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1232-NEXT: s_mov_b32 s11, 0x31016000 +; GFX1232-NEXT: s_bcnt1_i32_b32 s2, s2 +; GFX1232-NEXT: s_mov_b32 s15, 0x31016000 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) -; GFX1232-NEXT: s_mul_i32 s8, s1, s3 -; GFX1232-NEXT: s_mul_hi_u32 s9, s0, s3 -; GFX1232-NEXT: s_mul_i32 s3, s0, s3 -; GFX1232-NEXT: s_add_co_i32 s9, s9, s8 -; GFX1232-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1232-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s9 -; GFX1232-NEXT: s_mov_b32 s10, -1 -; GFX1232-NEXT: s_mov_b32 s8, s6 -; GFX1232-NEXT: s_mov_b32 s9, s7 -; GFX1232-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN +; GFX1232-NEXT: s_mul_u64 s[2:3], s[0:1], s[2:3] +; GFX1232-NEXT: s_mov_b32 s14, -1 +; GFX1232-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX1232-NEXT: s_mov_b32 s12, s6 +; GFX1232-NEXT: s_mov_b32 s13, s7 +; GFX1232-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[12:15], null th:TH_ATOMIC_RETURN ; GFX1232-NEXT: s_waitcnt vmcnt(0) ; GFX1232-NEXT: global_inv scope:SCOPE_DEV ; GFX1232-NEXT: .LBB10_2: -; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s8 ; GFX1232-NEXT: s_waitcnt lgkmcnt(0) ; GFX1232-NEXT: v_mul_lo_u32 v5, s1, v2 ; GFX1232-NEXT: v_mad_co_u64_u32 v[3:4], null, s0, v2, 0 diff --git a/llvm/test/CodeGen/AMDGPU/mul.ll b/llvm/test/CodeGen/AMDGPU/mul.ll index 5e90c33f3c8c..e2617fc453b5 100644 --- a/llvm/test/CodeGen/AMDGPU/mul.ll +++ b/llvm/test/CodeGen/AMDGPU/mul.ll @@ -4,6 +4,7 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG %s ; mul24 and mad24 are affected @@ -106,6 +107,27 @@ define amdgpu_kernel void @test_mul_v2i32(ptr addrspace(1) %out, ptr addrspace(1 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: test_mul_v2i32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_lo_u32 v1, v1, v3 +; GFX12-NEXT: v_mul_lo_u32 v0, v0, v2 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: test_mul_v2i32: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] @@ -247,6 +269,31 @@ define amdgpu_kernel void @v_mul_v4i32(ptr addrspace(1) %out, ptr addrspace(1) % ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_mul_v4i32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[8:11], null +; GFX12-NEXT: buffer_load_b128 v[4:7], off, s[8:11], null offset:16 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_lo_u32 v3, v3, v7 +; GFX12-NEXT: v_mul_lo_u32 v2, v2, v6 +; GFX12-NEXT: v_mul_lo_u32 v1, v1, v5 +; GFX12-NEXT: v_mul_lo_u32 v0, v0, v4 +; GFX12-NEXT: buffer_store_b128 v[0:3], off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_mul_v4i32: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] @@ -351,6 +398,21 @@ define amdgpu_kernel void @s_trunc_i64_mul_to_i32(ptr addrspace(1) %out, i64 %a, ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: s_trunc_i64_mul_to_i32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX12-NEXT: s_load_b32 s0, s[0:1], 0x34 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mul_i32 s0, s0, s6 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: s_trunc_i64_mul_to_i32: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] @@ -483,6 +545,31 @@ define amdgpu_kernel void @v_trunc_i64_mul_to_i32(ptr addrspace(1) %out, ptr add ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_trunc_i64_mul_to_i32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s2, s10 +; GFX12-NEXT: s_mov_b32 s3, s11 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s12, s6 +; GFX12-NEXT: s_mov_b32 s13, s7 +; GFX12-NEXT: buffer_load_b32 v0, off, s[12:15], null +; GFX12-NEXT: buffer_load_b32 v1, off, s[0:3], null +; GFX12-NEXT: s_mov_b32 s8, s4 +; GFX12-NEXT: s_mov_b32 s9, s5 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_lo_u32 v0, v1, v0 +; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_trunc_i64_mul_to_i32: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] @@ -587,6 +674,21 @@ define amdgpu_kernel void @mul64_sext_c(ptr addrspace(1) %out, i32 %in) { ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: mul64_sext_c: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x24 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_u64 s[4:5], s[2:3], 0x50 +; GFX12-NEXT: s_mov_b32 s3, 0x31016000 +; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: mul64_sext_c: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[] @@ -606,6 +708,113 @@ entry: ret void } +define amdgpu_kernel void @mul64_zext_c(ptr addrspace(1) %out, i32 %in) { +; SI-LABEL: mul64_zext_c: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_load_dword s4, s[0:1], 0xb +; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-NEXT: v_mov_b32_e32 v0, 0x50 +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_mov_b32 s2, -1 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: v_mul_hi_u32 v1, s4, v0 +; SI-NEXT: s_mulk_i32 s4, 0x50 +; SI-NEXT: v_mov_b32_e32 v0, s4 +; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: mul64_zext_c: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-NEXT: v_mov_b32_e32 v0, 0x50 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s2, v0, 0 +; VI-NEXT: s_mov_b32 s3, 0xf000 +; VI-NEXT: s_mov_b32 s2, -1 +; VI-NEXT: s_nop 2 +; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: mul64_zext_c: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX9-NEXT: s_mov_b32 s7, 0xf000 +; GFX9-NEXT: s_mov_b32 s6, -1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_mul_hi_u32 s0, s2, 0x50 +; GFX9-NEXT: s_mulk_i32 s2, 0x50 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: mul64_zext_c: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c +; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX10-NEXT: s_mov_b32 s7, 0x31016000 +; GFX10-NEXT: s_mov_b32 s6, -1 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_mul_i32 s0, s2, 0x50 +; GFX10-NEXT: s_mul_hi_u32 s1, s2, 0x50 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: mul64_zext_c: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_mul_i32 s3, s2, 0x50 +; GFX11-NEXT: s_mul_hi_u32 s2, s2, 0x50 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2 +; GFX11-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-NEXT: s_mov_b32 s2, -1 +; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 +; GFX11-NEXT: s_nop 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: mul64_zext_c: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s3, 0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mul_u64 s[4:5], s[2:3], 0x50 +; GFX12-NEXT: s_mov_b32 s3, 0x31016000 +; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; +; EG-LABEL: mul64_zext_c: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: MULHI * T0.Y, KC0[2].Z, literal.x, +; EG-NEXT: 80(1.121039e-43), 0(0.000000e+00) +; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; EG-NEXT: MULLO_INT * T0.X, KC0[2].Z, literal.y, +; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43) +entry: + %0 = zext i32 %in to i64 + %1 = mul i64 %0, 80 + store i64 %1, ptr addrspace(1) %out + ret void +} + define amdgpu_kernel void @v_mul64_sext_c(ptr addrspace(1) %out, ptr addrspace(1) %in) { ; SI-LABEL: v_mul64_sext_c: ; SI: ; %bb.0: ; %entry @@ -706,6 +915,27 @@ define amdgpu_kernel void @v_mul64_sext_c(ptr addrspace(1) %out, ptr addrspace(1 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_mul64_sext_c: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_hi_i32 v1, 0x50, v0 +; GFX12-NEXT: v_mul_lo_u32 v0, 0x50, v0 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_mul64_sext_c: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] @@ -732,6 +962,153 @@ entry: ret void } +define amdgpu_kernel void @v_mul64_zext_c(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; SI-LABEL: v_mul64_zext_c: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, -1 +; SI-NEXT: s_mov_b32 s10, s6 +; SI-NEXT: s_mov_b32 s11, s7 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b32 s8, s2 +; SI-NEXT: s_mov_b32 s9, s3 +; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; SI-NEXT: s_movk_i32 s2, 0x50 +; SI-NEXT: s_mov_b32 s4, s0 +; SI-NEXT: s_mov_b32 s5, s1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_hi_u32 v1, v0, s2 +; SI-NEXT: v_mul_lo_u32 v0, v0, s2 +; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: v_mul64_zext_c: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-NEXT: s_mov_b32 s7, 0xf000 +; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_mov_b32 s10, s6 +; VI-NEXT: s_mov_b32 s11, s7 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_mov_b32 s8, s2 +; VI-NEXT: s_mov_b32 s9, s3 +; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; VI-NEXT: s_movk_i32 s2, 0x50 +; VI-NEXT: s_mov_b32 s4, s0 +; VI-NEXT: s_mov_b32 s5, s1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v0, s2, 0 +; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v_mul64_zext_c: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: s_mov_b32 s7, 0xf000 +; GFX9-NEXT: s_mov_b32 s6, -1 +; GFX9-NEXT: s_mov_b32 s10, s6 +; GFX9-NEXT: s_mov_b32 s11, s7 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_mov_b32 s8, s2 +; GFX9-NEXT: s_mov_b32 s9, s3 +; GFX9-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; GFX9-NEXT: s_movk_i32 s2, 0x50 +; GFX9-NEXT: s_mov_b32 s4, s0 +; GFX9-NEXT: s_mov_b32 s5, s1 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_mul_hi_u32 v1, v0, s2 +; GFX9-NEXT: v_mul_lo_u32 v0, v0, s2 +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: v_mul64_zext_c: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX10-NEXT: s_mov_b32 s6, -1 +; GFX10-NEXT: s_mov_b32 s7, 0x31016000 +; GFX10-NEXT: s_mov_b32 s10, s6 +; GFX10-NEXT: s_mov_b32 s11, s7 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s8, s2 +; GFX10-NEXT: s_mov_b32 s9, s3 +; GFX10-NEXT: s_mov_b32 s4, s0 +; GFX10-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; GFX10-NEXT: s_mov_b32 s5, s1 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mul_hi_u32 v1, 0x50, v0 +; GFX10-NEXT: v_mul_lo_u32 v0, 0x50, v0 +; GFX10-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: v_mul64_zext_c: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s6, -1 +; GFX11-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-NEXT: s_mov_b32 s10, s6 +; GFX11-NEXT: s_mov_b32 s11, s7 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s8, s2 +; GFX11-NEXT: s_mov_b32 s9, s3 +; GFX11-NEXT: s_mov_b32 s4, s0 +; GFX11-NEXT: buffer_load_b32 v0, off, s[8:11], 0 +; GFX11-NEXT: s_mov_b32 s5, s1 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mul_hi_u32 v1, 0x50, v0 +; GFX11-NEXT: v_mul_lo_u32 v0, 0x50, v0 +; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[4:7], 0 +; GFX11-NEXT: s_nop 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_mul64_zext_c: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_hi_u32 v1, 0x50, v0 +; GFX12-NEXT: v_mul_lo_u32 v0, 0x50, v0 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; +; EG-LABEL: v_mul64_zext_c: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MULHI * T0.Y, T0.X, literal.x, +; EG-NEXT: 80(1.121039e-43), 0(0.000000e+00) +; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; EG-NEXT: MULLO_INT * T0.X, T0.X, literal.y, +; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43) +entry: + %val = load i32, ptr addrspace(1) %in, align 4 + %ext = zext i32 %val to i64 + %mul = mul i64 %ext, 80 + store i64 %mul, ptr addrspace(1) %out, align 8 + ret void +} + define amdgpu_kernel void @v_mul64_sext_inline_imm(ptr addrspace(1) %out, ptr addrspace(1) %in) { ; SI-LABEL: v_mul64_sext_inline_imm: ; SI: ; %bb.0: ; %entry @@ -829,6 +1206,27 @@ define amdgpu_kernel void @v_mul64_sext_inline_imm(ptr addrspace(1) %out, ptr ad ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_mul64_sext_inline_imm: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_hi_i32 v1, 9, v0 +; GFX12-NEXT: v_mul_lo_u32 v0, 9, v0 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_mul64_sext_inline_imm: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] @@ -925,6 +1323,22 @@ define amdgpu_kernel void @s_mul_i32(ptr addrspace(1) %out, [8 x i32], i32 %a, [ ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: s_mul_i32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_clause 0x2 +; GFX12-NEXT: s_load_b32 s2, s[0:1], 0x4c +; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x70 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mul_i32 s2, s2, s3 +; GFX12-NEXT: s_mov_b32 s3, 0x31016000 +; GFX12-NEXT: v_mov_b32_e32 v0, s2 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: s_mul_i32: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] @@ -1034,6 +1448,26 @@ define amdgpu_kernel void @v_mul_i32(ptr addrspace(1) %out, ptr addrspace(1) %in ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_mul_i32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_b64 v[0:1], off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_lo_u32 v0, v0, v1 +; GFX12-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_mul_i32: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] @@ -1133,6 +1567,23 @@ define amdgpu_kernel void @s_mul_i1(ptr addrspace(1) %out, [8 x i32], i1 %a, [8 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: s_mul_i1: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_clause 0x2 +; GFX12-NEXT: s_load_b32 s2, s[0:1], 0x4c +; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x70 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: v_mul_lo_u16 v0, s2, s3 +; GFX12-NEXT: s_mov_b32 s3, 0x31016000 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX12-NEXT: buffer_store_b8 v0, off, s[0:3], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: s_mul_i1: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 0, @10, KC0[], KC1[] @@ -1272,6 +1723,30 @@ define amdgpu_kernel void @v_mul_i1(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_mul_i1: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: buffer_load_u8 v0, off, s[8:11], null +; GFX12-NEXT: buffer_load_u8 v1, off, s[8:11], null offset:4 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_lo_u16 v0, v0, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX12-NEXT: buffer_store_b8 v0, off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_mul_i1: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] @@ -1418,6 +1893,21 @@ define amdgpu_kernel void @s_mul_i64(ptr addrspace(1) %out, i64 %a, i64 %b) noun ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: s_mul_i64: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mul_u64 s[0:1], s[6:7], s[0:1] +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: s_mul_i64: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] @@ -1579,6 +2069,37 @@ define amdgpu_kernel void @v_mul_i64(ptr addrspace(1) %out, ptr addrspace(1) %ap ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_mul_i64: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s2, s10 +; GFX12-NEXT: s_mov_b32 s3, s11 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s12, s6 +; GFX12-NEXT: s_mov_b32 s13, s7 +; GFX12-NEXT: buffer_load_b64 v[0:1], off, s[0:3], null +; GFX12-NEXT: buffer_load_b64 v[2:3], off, s[12:15], null +; GFX12-NEXT: s_mov_b32 s8, s4 +; GFX12-NEXT: s_mov_b32 s9, s5 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mul_lo_u32 v3, v0, v3 +; GFX12-NEXT: v_mul_lo_u32 v1, v1, v2 +; GFX12-NEXT: v_mul_hi_u32 v4, v0, v2 +; GFX12-NEXT: v_mul_lo_u32 v0, v0, v2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_add_nc_u32_e32 v1, v3, v1 +; GFX12-NEXT: v_add_nc_u32_e32 v1, v1, v4 +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_mul_i64: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] @@ -1616,30 +2137,30 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_cmp_lg_u32 s2, 0 -; SI-NEXT: s_cbranch_scc0 .LBB13_2 +; SI-NEXT: s_cbranch_scc0 .LBB15_2 ; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: s_mul_i32 s6, s2, s3 ; SI-NEXT: s_mov_b64 s[4:5], 0 -; SI-NEXT: s_branch .LBB13_3 -; SI-NEXT: .LBB13_2: +; SI-NEXT: s_branch .LBB15_3 +; SI-NEXT: .LBB15_2: ; SI-NEXT: s_mov_b64 s[4:5], -1 ; SI-NEXT: ; implicit-def: $sgpr6 -; SI-NEXT: .LBB13_3: ; %Flow +; SI-NEXT: .LBB15_3: ; %Flow ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_mov_b64 vcc, vcc -; SI-NEXT: s_cbranch_vccnz .LBB13_5 +; SI-NEXT: s_cbranch_vccnz .LBB15_5 ; SI-NEXT: ; %bb.4: ; %if ; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s4, s2 ; SI-NEXT: s_mov_b32 s5, s3 ; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0 -; SI-NEXT: s_branch .LBB13_6 -; SI-NEXT: .LBB13_5: +; SI-NEXT: s_branch .LBB15_6 +; SI-NEXT: .LBB15_5: ; SI-NEXT: v_mov_b32_e32 v0, s6 -; SI-NEXT: .LBB13_6: ; %endif +; SI-NEXT: .LBB15_6: ; %endif ; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_waitcnt vmcnt(0) @@ -1651,18 +2172,18 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_cmp_lg_u32 s2, 0 -; VI-NEXT: s_cbranch_scc0 .LBB13_2 +; VI-NEXT: s_cbranch_scc0 .LBB15_2 ; VI-NEXT: ; %bb.1: ; %else ; VI-NEXT: s_mul_i32 s6, s2, s3 ; VI-NEXT: s_mov_b64 s[4:5], 0 -; VI-NEXT: s_branch .LBB13_3 -; VI-NEXT: .LBB13_2: +; VI-NEXT: s_branch .LBB15_3 +; VI-NEXT: .LBB15_2: ; VI-NEXT: s_mov_b64 s[4:5], -1 ; VI-NEXT: ; implicit-def: $sgpr6 -; VI-NEXT: .LBB13_3: ; %Flow +; VI-NEXT: .LBB15_3: ; %Flow ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_andn2_b64 vcc, exec, s[4:5] -; VI-NEXT: s_cbranch_vccnz .LBB13_5 +; VI-NEXT: s_cbranch_vccnz .LBB15_5 ; VI-NEXT: ; %bb.4: ; %if ; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s6, -1 @@ -1670,10 +2191,10 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; VI-NEXT: s_mov_b32 s4, s2 ; VI-NEXT: s_mov_b32 s5, s3 ; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0 -; VI-NEXT: s_branch .LBB13_6 -; VI-NEXT: .LBB13_5: +; VI-NEXT: s_branch .LBB15_6 +; VI-NEXT: .LBB15_5: ; VI-NEXT: v_mov_b32_e32 v0, s6 -; VI-NEXT: .LBB13_6: ; %endif +; VI-NEXT: .LBB15_6: ; %endif ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s2, -1 @@ -1686,18 +2207,18 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 -; GFX9-NEXT: s_cbranch_scc0 .LBB13_2 +; GFX9-NEXT: s_cbranch_scc0 .LBB15_2 ; GFX9-NEXT: ; %bb.1: ; %else ; GFX9-NEXT: s_mul_i32 s6, s2, s3 ; GFX9-NEXT: s_mov_b64 s[4:5], 0 -; GFX9-NEXT: s_branch .LBB13_3 -; GFX9-NEXT: .LBB13_2: +; GFX9-NEXT: s_branch .LBB15_3 +; GFX9-NEXT: .LBB15_2: ; GFX9-NEXT: s_mov_b64 s[4:5], -1 ; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: .LBB13_3: ; %Flow +; GFX9-NEXT: .LBB15_3: ; %Flow ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_andn2_b64 vcc, exec, s[4:5] -; GFX9-NEXT: s_cbranch_vccnz .LBB13_5 +; GFX9-NEXT: s_cbranch_vccnz .LBB15_5 ; GFX9-NEXT: ; %bb.4: ; %if ; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s6, -1 @@ -1705,10 +2226,10 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: buffer_load_dword v0, off, s[4:7], 0 -; GFX9-NEXT: s_branch .LBB13_6 -; GFX9-NEXT: .LBB13_5: +; GFX9-NEXT: s_branch .LBB15_6 +; GFX9-NEXT: .LBB15_5: ; GFX9-NEXT: v_mov_b32_e32 v0, s6 -; GFX9-NEXT: .LBB13_6: ; %endif +; GFX9-NEXT: .LBB15_6: ; %endif ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s2, -1 @@ -1722,17 +2243,17 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 -; GFX10-NEXT: s_cbranch_scc0 .LBB13_2 +; GFX10-NEXT: s_cbranch_scc0 .LBB15_2 ; GFX10-NEXT: ; %bb.1: ; %else ; GFX10-NEXT: s_mul_i32 s5, s2, s3 -; GFX10-NEXT: s_branch .LBB13_3 -; GFX10-NEXT: .LBB13_2: +; GFX10-NEXT: s_branch .LBB15_3 +; GFX10-NEXT: .LBB15_2: ; GFX10-NEXT: s_mov_b32 s4, -1 ; GFX10-NEXT: ; implicit-def: $sgpr5 -; GFX10-NEXT: .LBB13_3: ; %Flow +; GFX10-NEXT: .LBB15_3: ; %Flow ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4 -; GFX10-NEXT: s_cbranch_vccnz .LBB13_5 +; GFX10-NEXT: s_cbranch_vccnz .LBB15_5 ; GFX10-NEXT: ; %bb.4: ; %if ; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; GFX10-NEXT: s_mov_b32 s6, -1 @@ -1740,10 +2261,10 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: buffer_load_dword v0, off, s[4:7], 0 -; GFX10-NEXT: s_branch .LBB13_6 -; GFX10-NEXT: .LBB13_5: +; GFX10-NEXT: s_branch .LBB15_6 +; GFX10-NEXT: .LBB15_5: ; GFX10-NEXT: v_mov_b32_e32 v0, s5 -; GFX10-NEXT: .LBB13_6: ; %endif +; GFX10-NEXT: .LBB15_6: ; %endif ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; GFX10-NEXT: s_mov_b32 s2, -1 @@ -1757,17 +2278,17 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_cmp_lg_u32 s2, 0 -; GFX11-NEXT: s_cbranch_scc0 .LBB13_2 +; GFX11-NEXT: s_cbranch_scc0 .LBB15_2 ; GFX11-NEXT: ; %bb.1: ; %else ; GFX11-NEXT: s_mul_i32 s5, s2, s3 -; GFX11-NEXT: s_branch .LBB13_3 -; GFX11-NEXT: .LBB13_2: +; GFX11-NEXT: s_branch .LBB15_3 +; GFX11-NEXT: .LBB15_2: ; GFX11-NEXT: s_mov_b32 s4, -1 ; GFX11-NEXT: ; implicit-def: $sgpr5 -; GFX11-NEXT: .LBB13_3: ; %Flow +; GFX11-NEXT: .LBB15_3: ; %Flow ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 -; GFX11-NEXT: s_cbranch_vccnz .LBB13_5 +; GFX11-NEXT: s_cbranch_vccnz .LBB15_5 ; GFX11-NEXT: ; %bb.4: ; %if ; GFX11-NEXT: s_mov_b32 s7, 0x31016000 ; GFX11-NEXT: s_mov_b32 s6, -1 @@ -1775,10 +2296,10 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_mov_b32 s4, s2 ; GFX11-NEXT: s_mov_b32 s5, s3 ; GFX11-NEXT: buffer_load_b32 v0, off, s[4:7], 0 -; GFX11-NEXT: s_branch .LBB13_6 -; GFX11-NEXT: .LBB13_5: +; GFX11-NEXT: s_branch .LBB15_6 +; GFX11-NEXT: .LBB15_5: ; GFX11-NEXT: v_mov_b32_e32 v0, s5 -; GFX11-NEXT: .LBB13_6: ; %endif +; GFX11-NEXT: .LBB15_6: ; %endif ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; GFX11-NEXT: s_mov_b32 s2, -1 @@ -1788,6 +2309,43 @@ define amdgpu_kernel void @mul32_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: mul32_in_branch: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b64 s[2:3], s[0:1], 0x34 +; GFX12-NEXT: s_mov_b32 s4, 0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_cmp_lg_u32 s2, 0 +; GFX12-NEXT: s_cbranch_scc0 .LBB15_2 +; GFX12-NEXT: ; %bb.1: ; %else +; GFX12-NEXT: s_mul_i32 s5, s2, s3 +; GFX12-NEXT: s_branch .LBB15_3 +; GFX12-NEXT: .LBB15_2: +; GFX12-NEXT: s_mov_b32 s4, -1 +; GFX12-NEXT: ; implicit-def: $sgpr5 +; GFX12-NEXT: .LBB15_3: ; %Flow +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 +; GFX12-NEXT: s_cbranch_vccnz .LBB15_5 +; GFX12-NEXT: ; %bb.4: ; %if +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s4, s2 +; GFX12-NEXT: s_mov_b32 s5, s3 +; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null +; GFX12-NEXT: s_branch .LBB15_6 +; GFX12-NEXT: .LBB15_5: +; GFX12-NEXT: v_mov_b32_e32 v0, s5 +; GFX12-NEXT: .LBB15_6: ; %endif +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s3, 0x31016000 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: mul32_in_branch: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU_PUSH_BEFORE 3, @14, KC0[CB0:0-32], KC1[] @@ -1850,7 +2408,7 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u64_e64 s[10:11], s[4:5], 0 ; SI-NEXT: s_and_b64 vcc, exec, s[10:11] -; SI-NEXT: s_cbranch_vccz .LBB14_4 +; SI-NEXT: s_cbranch_vccz .LBB16_4 ; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mul_hi_u32 v0, s4, v0 @@ -1861,22 +2419,22 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; SI-NEXT: v_add_i32_e32 v1, vcc, s5, v0 ; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: s_andn2_b64 vcc, exec, s[8:9] -; SI-NEXT: s_cbranch_vccnz .LBB14_3 -; SI-NEXT: .LBB14_2: ; %if +; SI-NEXT: s_cbranch_vccnz .LBB16_3 +; SI-NEXT: .LBB16_2: ; %if ; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s4, s2 ; SI-NEXT: s_mov_b32 s5, s3 ; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 -; SI-NEXT: .LBB14_3: ; %endif +; SI-NEXT: .LBB16_3: ; %endif ; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: s_endpgm -; SI-NEXT: .LBB14_4: +; SI-NEXT: .LBB16_4: ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1 -; SI-NEXT: s_branch .LBB14_2 +; SI-NEXT: s_branch .LBB16_2 ; ; VI-LABEL: mul64_in_branch: ; VI: ; %bb.0: ; %entry @@ -1884,7 +2442,7 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; VI-NEXT: s_mov_b64 s[8:9], 0 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 -; VI-NEXT: s_cbranch_scc0 .LBB14_4 +; VI-NEXT: s_cbranch_scc0 .LBB16_4 ; VI-NEXT: ; %bb.1: ; %else ; VI-NEXT: v_mov_b32_e32 v0, s6 ; VI-NEXT: v_mad_u64_u32 v[0:1], s[10:11], s4, v0, 0 @@ -1893,22 +2451,22 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; VI-NEXT: s_mul_i32 s4, s5, s6 ; VI-NEXT: v_add_u32_e32 v1, vcc, s4, v1 ; VI-NEXT: s_andn2_b64 vcc, exec, s[8:9] -; VI-NEXT: s_cbranch_vccnz .LBB14_3 -; VI-NEXT: .LBB14_2: ; %if +; VI-NEXT: s_cbranch_vccnz .LBB16_3 +; VI-NEXT: .LBB16_2: ; %if ; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s4, s2 ; VI-NEXT: s_mov_b32 s5, s3 ; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 -; VI-NEXT: .LBB14_3: ; %endif +; VI-NEXT: .LBB16_3: ; %endif ; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: s_endpgm -; VI-NEXT: .LBB14_4: +; VI-NEXT: .LBB16_4: ; VI-NEXT: ; implicit-def: $vgpr0_vgpr1 -; VI-NEXT: s_branch .LBB14_2 +; VI-NEXT: s_branch .LBB16_2 ; ; GFX9-LABEL: mul64_in_branch: ; GFX9: ; %bb.0: ; %entry @@ -1916,7 +2474,7 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX9-NEXT: s_mov_b64 s[8:9], 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX9-NEXT: s_cbranch_scc0 .LBB14_3 +; GFX9-NEXT: s_cbranch_scc0 .LBB16_3 ; GFX9-NEXT: ; %bb.1: ; %else ; GFX9-NEXT: s_mul_i32 s7, s4, s7 ; GFX9-NEXT: s_mul_hi_u32 s10, s4, s6 @@ -1925,21 +2483,21 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX9-NEXT: s_add_i32 s5, s7, s5 ; GFX9-NEXT: s_mul_i32 s4, s4, s6 ; GFX9-NEXT: s_andn2_b64 vcc, exec, s[8:9] -; GFX9-NEXT: s_cbranch_vccnz .LBB14_4 -; GFX9-NEXT: .LBB14_2: ; %if +; GFX9-NEXT: s_cbranch_vccnz .LBB16_4 +; GFX9-NEXT: .LBB16_2: ; %if ; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 -; GFX9-NEXT: s_branch .LBB14_5 -; GFX9-NEXT: .LBB14_3: +; GFX9-NEXT: s_branch .LBB16_5 +; GFX9-NEXT: .LBB16_3: ; GFX9-NEXT: ; implicit-def: $sgpr4_sgpr5 -; GFX9-NEXT: s_branch .LBB14_2 -; GFX9-NEXT: .LBB14_4: +; GFX9-NEXT: s_branch .LBB16_2 +; GFX9-NEXT: .LBB16_4: ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: .LBB14_5: ; %endif +; GFX9-NEXT: .LBB16_5: ; %endif ; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_waitcnt vmcnt(0) @@ -1951,7 +2509,7 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX10-NEXT: s_cbranch_scc0 .LBB14_3 +; GFX10-NEXT: s_cbranch_scc0 .LBB16_3 ; GFX10-NEXT: ; %bb.1: ; %else ; GFX10-NEXT: s_mul_i32 s7, s4, s7 ; GFX10-NEXT: s_mul_hi_u32 s8, s4, s6 @@ -1960,22 +2518,22 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX10-NEXT: s_mul_i32 s4, s4, s6 ; GFX10-NEXT: s_add_i32 s5, s7, s5 ; GFX10-NEXT: s_mov_b32 s6, 0 -; GFX10-NEXT: s_cbranch_execnz .LBB14_4 -; GFX10-NEXT: .LBB14_2: ; %if +; GFX10-NEXT: s_cbranch_execnz .LBB16_4 +; GFX10-NEXT: .LBB16_2: ; %if ; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; GFX10-NEXT: s_mov_b32 s6, -1 ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 -; GFX10-NEXT: s_branch .LBB14_5 -; GFX10-NEXT: .LBB14_3: +; GFX10-NEXT: s_branch .LBB16_5 +; GFX10-NEXT: .LBB16_3: ; GFX10-NEXT: s_mov_b32 s6, -1 ; GFX10-NEXT: ; implicit-def: $sgpr4_sgpr5 -; GFX10-NEXT: s_branch .LBB14_2 -; GFX10-NEXT: .LBB14_4: +; GFX10-NEXT: s_branch .LBB16_2 +; GFX10-NEXT: .LBB16_4: ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-NEXT: .LBB14_5: ; %endif +; GFX10-NEXT: .LBB16_5: ; %endif ; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; GFX10-NEXT: s_mov_b32 s2, -1 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1987,7 +2545,7 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX11-NEXT: s_cbranch_scc0 .LBB14_3 +; GFX11-NEXT: s_cbranch_scc0 .LBB16_3 ; GFX11-NEXT: ; %bb.1: ; %else ; GFX11-NEXT: s_mul_i32 s7, s4, s7 ; GFX11-NEXT: s_mul_hi_u32 s8, s4, s6 @@ -1996,21 +2554,21 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_mul_i32 s4, s4, s6 ; GFX11-NEXT: s_add_i32 s5, s7, s5 ; GFX11-NEXT: s_mov_b32 s6, 0 -; GFX11-NEXT: s_cbranch_execnz .LBB14_4 -; GFX11-NEXT: .LBB14_2: ; %if +; GFX11-NEXT: s_cbranch_execnz .LBB16_4 +; GFX11-NEXT: .LBB16_2: ; %if ; GFX11-NEXT: s_mov_b32 s7, 0x31016000 ; GFX11-NEXT: s_mov_b32 s6, -1 ; GFX11-NEXT: s_mov_b32 s4, s2 ; GFX11-NEXT: s_mov_b32 s5, s3 ; GFX11-NEXT: buffer_load_b64 v[0:1], off, s[4:7], 0 -; GFX11-NEXT: s_branch .LBB14_5 -; GFX11-NEXT: .LBB14_3: +; GFX11-NEXT: s_branch .LBB16_5 +; GFX11-NEXT: .LBB16_3: ; GFX11-NEXT: s_mov_b32 s6, -1 ; GFX11-NEXT: ; implicit-def: $sgpr4_sgpr5 -; GFX11-NEXT: s_branch .LBB14_2 -; GFX11-NEXT: .LBB14_4: +; GFX11-NEXT: s_branch .LBB16_2 +; GFX11-NEXT: .LBB16_4: ; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 -; GFX11-NEXT: .LBB14_5: ; %endif +; GFX11-NEXT: .LBB16_5: ; %endif ; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; GFX11-NEXT: s_mov_b32 s2, -1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2019,6 +2577,38 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: mul64_in_branch: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX12-NEXT: s_cbranch_scc0 .LBB16_3 +; GFX12-NEXT: ; %bb.1: ; %else +; GFX12-NEXT: s_mul_u64 s[4:5], s[4:5], s[6:7] +; GFX12-NEXT: s_mov_b32 s6, 0 +; GFX12-NEXT: s_cbranch_execnz .LBB16_4 +; GFX12-NEXT: .LBB16_2: ; %if +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s4, s2 +; GFX12-NEXT: s_mov_b32 s5, s3 +; GFX12-NEXT: buffer_load_b64 v[0:1], off, s[4:7], null +; GFX12-NEXT: s_branch .LBB16_5 +; GFX12-NEXT: .LBB16_3: +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: ; implicit-def: $sgpr4_sgpr5 +; GFX12-NEXT: s_branch .LBB16_2 +; GFX12-NEXT: .LBB16_4: +; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX12-NEXT: .LBB16_5: ; %endif +; GFX12-NEXT: s_mov_b32 s3, 0x31016000 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: mul64_in_branch: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU_PUSH_BEFORE 4, @14, KC0[CB0:0-32], KC1[] @@ -2324,6 +2914,51 @@ define amdgpu_kernel void @s_mul_i128(ptr addrspace(1) %out, [8 x i32], i128 %a, ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: s_mul_i128: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x7c +; GFX12-NEXT: s_load_b128 s[8:11], s[0:1], 0x4c +; GFX12-NEXT: s_mov_b32 s3, 0 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: s_mov_b32 s15, s3 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s17, s3 +; GFX12-NEXT: s_mov_b32 s19, s3 +; GFX12-NEXT: s_mov_b32 s24, s3 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_mov_b32 s2, s4 +; GFX12-NEXT: s_mov_b32 s14, s8 +; GFX12-NEXT: s_mov_b32 s12, s9 +; GFX12-NEXT: s_mul_u64 s[22:23], s[14:15], s[2:3] +; GFX12-NEXT: s_mul_u64 s[20:21], s[12:13], s[2:3] +; GFX12-NEXT: s_mov_b32 s2, s23 +; GFX12-NEXT: s_mov_b32 s16, s5 +; GFX12-NEXT: s_mul_u64 s[4:5], s[4:5], s[10:11] +; GFX12-NEXT: s_add_nc_u64 s[10:11], s[20:21], s[2:3] +; GFX12-NEXT: s_mul_u64 s[6:7], s[6:7], s[8:9] +; GFX12-NEXT: s_mul_u64 s[8:9], s[14:15], s[16:17] +; GFX12-NEXT: s_mov_b32 s2, s11 +; GFX12-NEXT: s_mov_b32 s11, s3 +; GFX12-NEXT: s_add_nc_u64 s[4:5], s[6:7], s[4:5] +; GFX12-NEXT: s_add_nc_u64 s[6:7], s[8:9], s[10:11] +; GFX12-NEXT: s_mul_u64 s[12:13], s[12:13], s[16:17] +; GFX12-NEXT: s_mov_b32 s18, s7 +; GFX12-NEXT: s_mov_b32 s23, s3 +; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[18:19] +; GFX12-NEXT: s_mov_b32 s25, s6 +; GFX12-NEXT: s_add_nc_u64 s[2:3], s[12:13], s[2:3] +; GFX12-NEXT: s_or_b64 s[6:7], s[22:23], s[24:25] +; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5] +; GFX12-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 +; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: s_mov_b32 s3, 0x31016000 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: s_mul_i128: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[] @@ -2570,6 +3205,44 @@ define amdgpu_kernel void @v_mul_i128(ptr addrspace(1) %out, ptr addrspace(1) %a ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; +; GFX12-LABEL: v_mul_i128: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x2c +; GFX12-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v15, 4, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: global_load_b128 v[0:3], v15, s[0:1] +; GFX12-NEXT: global_load_b128 v[4:7], v15, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_mad_co_u64_u32 v[8:9], null, v0, v4, 0 +; GFX12-NEXT: v_mul_lo_u32 v14, v5, v2 +; GFX12-NEXT: v_mul_lo_u32 v3, v4, v3 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_u64_u32 v[11:12], null, v1, v4, v[9:10] +; GFX12-NEXT: v_dual_mov_b32 v13, v12 :: v_dual_mov_b32 v12, v10 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_mad_co_u64_u32 v[9:10], null, v0, v5, v[11:12] +; GFX12-NEXT: v_mad_co_u64_u32 v[11:12], null, v4, v2, 0 +; GFX12-NEXT: v_mul_lo_u32 v4, v6, v1 +; GFX12-NEXT: v_mov_b32_e32 v2, v10 +; GFX12-NEXT: v_mul_lo_u32 v10, v7, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_add3_u32 v12, v12, v3, v14 +; GFX12-NEXT: v_add_co_u32 v2, s0, v13, v2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s0 +; GFX12-NEXT: v_mad_co_u64_u32 v[13:14], null, v6, v0, v[11:12] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_mad_co_u64_u32 v[6:7], null, v1, v5, v[2:3] +; GFX12-NEXT: v_add3_u32 v0, v10, v14, v4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_add_co_u32 v10, vcc_lo, v6, v13 +; GFX12-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v7, v0, vcc_lo +; GFX12-NEXT: global_store_b128 v15, v[8:11], s[2:3] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm +; ; EG-LABEL: v_mul_i128: ; EG: ; %bb.0: ; %entry ; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[] @@ -2672,6 +3345,12 @@ define i32 @mul_pow2_plus_1(i32 %val) { ; GFX11-NEXT: v_lshl_add_u32 v0, v0, 3, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: mul_pow2_plus_1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_lshl_add_u32 v0, v0, 3, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; EG-LABEL: mul_pow2_plus_1: ; EG: ; %bb.0: ; EG-NEXT: CF_END -- GitLab From e7655ad605d77e206ec94b2cef59c41a508edba7 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 8 Jan 2024 13:23:38 -0600 Subject: [PATCH 102/652] [Libomptarget] Remove unnecessary CMake definition of endiannness (#77205) Summary: This is needed for some definition in `hsa.h` that requires this to be set for some architectures when it fails at autodetection. We only really build `libomptarget` with `gcc` and `clang` which already provide their own way of detecting this. Remove the unnecessary define and move it into the source. --- .../plugins-nextgen/amdgpu/CMakeLists.txt | 8 -------- .../libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp | 12 ++++++++++++ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt b/openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt index bbf8c0a50f85..68ce63467a6c 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt @@ -35,14 +35,6 @@ add_definitions(-DTARGET_NAME=AMDGPU) # requires changing the original plugins. add_definitions(-DDEBUG_PREFIX="TARGET AMDGPU RTL") -if(CMAKE_SYSTEM_PROCESSOR MATCHES "(ppc64le)|(aarch64)$") - add_definitions(-DLITTLEENDIAN_CPU=1) -endif() - -if(CMAKE_BUILD_TYPE MATCHES Debug) - add_definitions(-DDEBUG) -endif() - set(LIBOMPTARGET_DLOPEN_LIBHSA OFF) option(LIBOMPTARGET_FORCE_DLOPEN_LIBHSA "Build with dlopened libhsa" ${LIBOMPTARGET_DLOPEN_LIBHSA}) diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp index 18076f8082d0..b67642e9e1bc 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp @@ -43,6 +43,18 @@ #include "llvm/Support/Program.h" #include "llvm/Support/raw_ostream.h" +#if !defined(__BYTE_ORDER__) || !defined(__ORDER_LITTLE_ENDIAN__) || \ + !defined(__ORDER_BIG_ENDIAN__) +#error "Missing preprocessor definitions for endianness detection." +#endif + +// The HSA headers require these definitions. +#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) +#define LITTLEENDIAN_CPU +#elif defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) +#define BIGENDIAN_CPU +#endif + #if defined(__has_include) #if __has_include("hsa/hsa.h") #include "hsa/hsa.h" -- GitLab From 7173ae99c0e1b13536a8492335c595f8aaee4267 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Mon, 8 Jan 2024 11:51:20 -0800 Subject: [PATCH 103/652] [llvm-exegesis] Align loop MBB in loop repetitor (#77264) This patch sets the alignment of the loob MBB in the loop repetitor to 16 to avoid instruction fetch/predecoding bottlenecks that can come up with unaligned code. The value of 16 was chosen based on numbers for recent Intel microarchitectures and reccomendations from Agner Fog. Fixes #77259. --- llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp index cc5a045a8be5..1872f550c3f3 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp @@ -10,6 +10,7 @@ #include "Target.h" #include "llvm/ADT/Sequence.h" #include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" namespace llvm { @@ -74,6 +75,11 @@ public: auto Loop = Filler.addBasicBlock(); auto Exit = Filler.addBasicBlock(); + // Align the loop machine basic block to a target-specific boundary + // to promote optimal instruction fetch/predecoding conditions. + Loop.MBB->setAlignment( + Filler.MF.getSubtarget().getTargetLowering()->getPrefLoopAlignment()); + const unsigned LoopUnrollFactor = LoopBodySize <= Instructions.size() ? 1 -- GitLab From eea627e3e3c423149cd2cd46cb6309b8d303e8bd Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Jan 2024 11:52:07 -0800 Subject: [PATCH 104/652] [NFC][msan] Switch allocator interface to use BufferedStackTrace (#77363) We will need it to unwind for fatal errors. --- compiler-rt/lib/msan/msan.h | 23 ++++++++++---------- compiler-rt/lib/msan/msan_allocator.cpp | 29 +++++++++++++------------ 2 files changed, 27 insertions(+), 25 deletions(-) diff --git a/compiler-rt/lib/msan/msan.h b/compiler-rt/lib/msan/msan.h index 25fa2212bdad..753e6b260734 100644 --- a/compiler-rt/lib/msan/msan.h +++ b/compiler-rt/lib/msan/msan.h @@ -255,18 +255,19 @@ char *GetProcSelfMaps(); void InitializeInterceptors(); void MsanAllocatorInit(); -void MsanDeallocate(StackTrace *stack, void *ptr); - -void *msan_malloc(uptr size, StackTrace *stack); -void *msan_calloc(uptr nmemb, uptr size, StackTrace *stack); -void *msan_realloc(void *ptr, uptr size, StackTrace *stack); -void *msan_reallocarray(void *ptr, uptr nmemb, uptr size, StackTrace *stack); -void *msan_valloc(uptr size, StackTrace *stack); -void *msan_pvalloc(uptr size, StackTrace *stack); -void *msan_aligned_alloc(uptr alignment, uptr size, StackTrace *stack); -void *msan_memalign(uptr alignment, uptr size, StackTrace *stack); +void MsanDeallocate(BufferedStackTrace *stack, void *ptr); + +void *msan_malloc(uptr size, BufferedStackTrace *stack); +void *msan_calloc(uptr nmemb, uptr size, BufferedStackTrace *stack); +void *msan_realloc(void *ptr, uptr size, BufferedStackTrace *stack); +void *msan_reallocarray(void *ptr, uptr nmemb, uptr size, + BufferedStackTrace *stack); +void *msan_valloc(uptr size, BufferedStackTrace *stack); +void *msan_pvalloc(uptr size, BufferedStackTrace *stack); +void *msan_aligned_alloc(uptr alignment, uptr size, BufferedStackTrace *stack); +void *msan_memalign(uptr alignment, uptr size, BufferedStackTrace *stack); int msan_posix_memalign(void **memptr, uptr alignment, uptr size, - StackTrace *stack); + BufferedStackTrace *stack); void InstallTrapHandler(); void InstallAtExitHandler(); diff --git a/compiler-rt/lib/msan/msan_allocator.cpp b/compiler-rt/lib/msan/msan_allocator.cpp index 72a7f980d39f..987c894c79d4 100644 --- a/compiler-rt/lib/msan/msan_allocator.cpp +++ b/compiler-rt/lib/msan/msan_allocator.cpp @@ -178,7 +178,7 @@ void MsanThreadLocalMallocStorage::CommitBack() { allocator.DestroyCache(GetAllocatorCache(this)); } -static void *MsanAllocate(StackTrace *stack, uptr size, uptr alignment, +static void *MsanAllocate(BufferedStackTrace *stack, uptr size, uptr alignment, bool zeroise) { if (size > max_malloc_size) { if (AllocatorMayReturnNull()) { @@ -229,7 +229,7 @@ static void *MsanAllocate(StackTrace *stack, uptr size, uptr alignment, return allocated; } -void MsanDeallocate(StackTrace *stack, void *p) { +void MsanDeallocate(BufferedStackTrace *stack, void *p) { CHECK(p); UnpoisonParam(1); RunFreeHooks(p); @@ -259,8 +259,8 @@ void MsanDeallocate(StackTrace *stack, void *p) { } } -static void *MsanReallocate(StackTrace *stack, void *old_p, uptr new_size, - uptr alignment) { +static void *MsanReallocate(BufferedStackTrace *stack, void *old_p, + uptr new_size, uptr alignment) { Metadata *meta = reinterpret_cast(allocator.GetMetaData(old_p)); uptr old_size = meta->requested_size; uptr actually_allocated_size = allocator.GetActuallyAllocatedSize(old_p); @@ -284,7 +284,7 @@ static void *MsanReallocate(StackTrace *stack, void *old_p, uptr new_size, return new_p; } -static void *MsanCalloc(StackTrace *stack, uptr nmemb, uptr size) { +static void *MsanCalloc(BufferedStackTrace *stack, uptr nmemb, uptr size) { if (UNLIKELY(CheckForCallocOverflow(size, nmemb))) { if (AllocatorMayReturnNull()) return nullptr; @@ -320,15 +320,15 @@ static uptr AllocationSizeFast(const void *p) { return reinterpret_cast(allocator.GetMetaData(p))->requested_size; } -void *msan_malloc(uptr size, StackTrace *stack) { +void *msan_malloc(uptr size, BufferedStackTrace *stack) { return SetErrnoOnNull(MsanAllocate(stack, size, sizeof(u64), false)); } -void *msan_calloc(uptr nmemb, uptr size, StackTrace *stack) { +void *msan_calloc(uptr nmemb, uptr size, BufferedStackTrace *stack) { return SetErrnoOnNull(MsanCalloc(stack, nmemb, size)); } -void *msan_realloc(void *ptr, uptr size, StackTrace *stack) { +void *msan_realloc(void *ptr, uptr size, BufferedStackTrace *stack) { if (!ptr) return SetErrnoOnNull(MsanAllocate(stack, size, sizeof(u64), false)); if (size == 0) { @@ -338,7 +338,8 @@ void *msan_realloc(void *ptr, uptr size, StackTrace *stack) { return SetErrnoOnNull(MsanReallocate(stack, ptr, size, sizeof(u64))); } -void *msan_reallocarray(void *ptr, uptr nmemb, uptr size, StackTrace *stack) { +void *msan_reallocarray(void *ptr, uptr nmemb, uptr size, + BufferedStackTrace *stack) { if (UNLIKELY(CheckForCallocOverflow(size, nmemb))) { errno = errno_ENOMEM; if (AllocatorMayReturnNull()) @@ -348,11 +349,11 @@ void *msan_reallocarray(void *ptr, uptr nmemb, uptr size, StackTrace *stack) { return msan_realloc(ptr, nmemb * size, stack); } -void *msan_valloc(uptr size, StackTrace *stack) { +void *msan_valloc(uptr size, BufferedStackTrace *stack) { return SetErrnoOnNull(MsanAllocate(stack, size, GetPageSizeCached(), false)); } -void *msan_pvalloc(uptr size, StackTrace *stack) { +void *msan_pvalloc(uptr size, BufferedStackTrace *stack) { uptr PageSize = GetPageSizeCached(); if (UNLIKELY(CheckForPvallocOverflow(size, PageSize))) { errno = errno_ENOMEM; @@ -365,7 +366,7 @@ void *msan_pvalloc(uptr size, StackTrace *stack) { return SetErrnoOnNull(MsanAllocate(stack, size, PageSize, false)); } -void *msan_aligned_alloc(uptr alignment, uptr size, StackTrace *stack) { +void *msan_aligned_alloc(uptr alignment, uptr size, BufferedStackTrace *stack) { if (UNLIKELY(!CheckAlignedAllocAlignmentAndSize(alignment, size))) { errno = errno_EINVAL; if (AllocatorMayReturnNull()) @@ -375,7 +376,7 @@ void *msan_aligned_alloc(uptr alignment, uptr size, StackTrace *stack) { return SetErrnoOnNull(MsanAllocate(stack, size, alignment, false)); } -void *msan_memalign(uptr alignment, uptr size, StackTrace *stack) { +void *msan_memalign(uptr alignment, uptr size, BufferedStackTrace *stack) { if (UNLIKELY(!IsPowerOfTwo(alignment))) { errno = errno_EINVAL; if (AllocatorMayReturnNull()) @@ -386,7 +387,7 @@ void *msan_memalign(uptr alignment, uptr size, StackTrace *stack) { } int msan_posix_memalign(void **memptr, uptr alignment, uptr size, - StackTrace *stack) { + BufferedStackTrace *stack) { if (UNLIKELY(!CheckPosixMemalignAlignment(alignment))) { if (AllocatorMayReturnNull()) return errno_EINVAL; -- GitLab From e72c71671e044aa30ca35bed9e20da771ae216b5 Mon Sep 17 00:00:00 2001 From: Felipe de Azevedo Piovezan Date: Mon, 8 Jan 2024 17:04:07 -0300 Subject: [PATCH 105/652] [AccelTable][nfc] Add helper function to cast AccelTableData (#77100) Specializations of AccelTableBase are always interested in accessing the derived versions of their data classes (e.g. DWARF5AccelTableData). They do so by sprinkling `static_casts` all over the code. This commit adds a helper function to simplify this process, reducinng the number of casts that have to be made in the middle of code, making it easier to read. --- llvm/include/llvm/CodeGen/AccelTable.h | 15 +++++++++++---- llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp | 11 +++++------ 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/llvm/include/llvm/CodeGen/AccelTable.h b/llvm/include/llvm/CodeGen/AccelTable.h index 6eb09f32f9f9..0638fbffda4f 100644 --- a/llvm/include/llvm/CodeGen/AccelTable.h +++ b/llvm/include/llvm/CodeGen/AccelTable.h @@ -143,6 +143,15 @@ public: std::vector Values; MCSymbol *Sym; + /// Get all AccelTableData cast as a `T`. + template auto getValues() const { + static_assert(std::is_pointer()); + static_assert( + std::is_base_of>()); + return map_range( + Values, [](AccelTableData *Data) { return static_cast(Data); }); + } + #ifndef NDEBUG void print(raw_ostream &OS) const; void dump() const { print(dbgs()); } @@ -319,8 +328,7 @@ public: /// Needs to be called after DIE offsets are computed. void convertDieToOffset() { for (auto &Entry : Entries) { - for (AccelTableData *Value : Entry.second.Values) { - DWARF5AccelTableData *Data = static_cast(Value); + for (auto *Data : Entry.second.getValues()) { // For TU we normalize as each Unit is emitted. // So when this is invoked after CU construction we will be in mixed // state. @@ -332,8 +340,7 @@ public: void addTypeEntries(DWARF5AccelTable &Table) { for (auto &Entry : Table.getEntries()) { - for (AccelTableData *Value : Entry.second.Values) { - DWARF5AccelTableData *Data = static_cast(Value); + for (auto *Data : Entry.second.getValues()) { addName(Entry.second.Name, Data->getDieOffset(), Data->getDieTag(), Data->getUnitID(), true); } diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp index bf580269eca6..b72c17aa6f54 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -342,8 +342,8 @@ void AppleAccelTableWriter::emitData() const { Asm->emitDwarfStringOffset(Hash->Name); Asm->OutStreamer->AddComment("Num DIEs"); Asm->emitInt32(Hash->Values.size()); - for (const auto *V : Hash->Values) - static_cast(V)->emit(Asm); + for (const auto *V : Hash->getValues()) + V->emit(Asm); PrevHash = Hash->HashValue; } // Emit the final end marker for the bucket. @@ -415,11 +415,10 @@ static uint32_t constructAbbreviationTag( void Dwarf5AccelTableWriter::populateAbbrevsMap() { for (auto &Bucket : Contents.getBuckets()) { for (auto *Hash : Bucket) { - for (auto *Value : Hash->Values) { + for (auto *Value : Hash->getValues()) { std::optional EntryRet = - getIndexForEntry(*static_cast(Value)); - unsigned Tag = - static_cast(Value)->getDieTag(); + getIndexForEntry(*Value); + unsigned Tag = Value->getDieTag(); uint32_t AbbrvTag = constructAbbreviationTag(Tag, EntryRet); if (Abbreviations.count(AbbrvTag) == 0) { SmallVector UA; -- GitLab From 87f67c2599410786ea3600d388fd1d2df13e60af Mon Sep 17 00:00:00 2001 From: erichkeane Date: Mon, 8 Jan 2024 10:38:10 -0800 Subject: [PATCH 106/652] [OpenACC] Implement 'self' clause parsing The 'self' clause takes an optional 'condition' expression, same as the non-optional expression taken by the 'if' clause. This patch extracts the 'condition' expression to a separate function, and implements the 'optional parens' infrastructure for clauses, then implements 'self' parsing. --- clang/include/clang/Basic/OpenACCKinds.h | 2 + clang/lib/Parse/ParseOpenACC.cpp | 37 ++++++++--- clang/test/ParserOpenACC/parse-clauses.c | 79 ++++++++++++++++++++++++ 3 files changed, 111 insertions(+), 7 deletions(-) diff --git a/clang/include/clang/Basic/OpenACCKinds.h b/clang/include/clang/Basic/OpenACCKinds.h index f6a628db29cf..b0c157e00236 100644 --- a/clang/include/clang/Basic/OpenACCKinds.h +++ b/clang/include/clang/Basic/OpenACCKinds.h @@ -96,6 +96,8 @@ enum class OpenACCClauseKind { /// 'if' clause, allowed on all the Compute Constructs, Data Constructs, /// Executable Constructs, and Combined Constructs. If, + /// 'self' clause, allowed on Compute and Combined Constructs, plus 'update'. + Self, /// Represents an invalid clause, for the purposes of parsing. Invalid, }; diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 84e994ef0081..c9224d3ae910 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -96,6 +96,7 @@ OpenACCClauseKind getOpenACCClauseKind(Token Tok) { .Case("if_present", OpenACCClauseKind::IfPresent) .Case("independent", OpenACCClauseKind::Independent) .Case("nohost", OpenACCClauseKind::NoHost) + .Case("self", OpenACCClauseKind::Self) .Case("seq", OpenACCClauseKind::Seq) .Case("vector", OpenACCClauseKind::Vector) .Case("worker", OpenACCClauseKind::Worker) @@ -328,10 +329,22 @@ OpenACCDirectiveKind ParseOpenACCDirectiveKind(Parser &P) { return DirKind; } +bool ClauseHasOptionalParens(OpenACCClauseKind Kind) { + return Kind == OpenACCClauseKind::Self; +} + bool ClauseHasRequiredParens(OpenACCClauseKind Kind) { return Kind == OpenACCClauseKind::Default || Kind == OpenACCClauseKind::If; } +ExprResult ParseOpenACCConditionalExpr(Parser &P) { + // FIXME: It isn't clear if the spec saying 'condition' means the same as + // it does in an if/while/etc (See ParseCXXCondition), however as it was + // written with Fortran/C in mind, we're going to assume it just means an + // 'expression evaluating to boolean'. + return P.getActions().CorrectDelayedTyposInExpr(P.ParseExpression()); +} + bool ParseOpenACCClauseParams(Parser &P, OpenACCClauseKind Kind) { BalancedDelimiterTracker Parens(P, tok::l_paren, tok::annot_pragma_openacc_end); @@ -362,12 +375,7 @@ bool ParseOpenACCClauseParams(Parser &P, OpenACCClauseKind Kind) { break; } case OpenACCClauseKind::If: { - // FIXME: It isn't clear if the spec saying 'condition' means the same as - // it does in an if/while/etc (See ParseCXXCondition), however as it was - // written with Fortran/C in mind, we're going to assume it just means an - // 'expression evaluating to boolean'. - ExprResult CondExpr = - P.getActions().CorrectDelayedTyposInExpr(P.ParseExpression()); + ExprResult CondExpr = ParseOpenACCConditionalExpr(P); // An invalid expression can be just about anything, so just give up on // this clause list. if (CondExpr.isInvalid()) @@ -379,8 +387,23 @@ bool ParseOpenACCClauseParams(Parser &P, OpenACCClauseKind Kind) { } return Parens.consumeClose(); + } else if (ClauseHasOptionalParens(Kind)) { + if (!Parens.consumeOpen()) { + switch (Kind) { + case OpenACCClauseKind::Self: { + ExprResult CondExpr = ParseOpenACCConditionalExpr(P); + // An invalid expression can be just about anything, so just give up on + // this clause list. + if (CondExpr.isInvalid()) + return true; + break; + } + default: + llvm_unreachable("Not an optional parens type?"); + } + Parens.consumeClose(); + } } - // FIXME: Handle optional parens return false; } diff --git a/clang/test/ParserOpenACC/parse-clauses.c b/clang/test/ParserOpenACC/parse-clauses.c index b247210ff6c7..11e89d420e6b 100644 --- a/clang/test/ParserOpenACC/parse-clauses.c +++ b/clang/test/ParserOpenACC/parse-clauses.c @@ -236,6 +236,85 @@ void IfClause() { for(;;){} } +void SyncClause() { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self + for(;;){} + + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self, seq + for(;;){} + + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self( + for(;;){} + + // expected-error@+2{{use of undeclared identifier 'seq'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self( seq + for(;;){} + + // expected-error@+3{{expected expression}} + // expected-error@+2{{use of undeclared identifier 'seq'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self(, seq + for(;;){} + + // expected-error@+2{{expected identifier}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self) + for(;;){} + + // expected-error@+2{{expected identifier}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self) seq + for(;;){} + + // expected-error@+2{{expected identifier}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self), seq + for(;;){} + + + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self(), seq + for(;;){} + + // expected-error@+3{{expected expression}} + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self(,), seq + for(;;){} + + // expected-error@+2{{use of undeclared identifier 'invalid_expr'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial loop self(invalid_expr), seq + for(;;){} + + int i, j; + + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial self(i > j + for(;;){} + + // expected-error@+2{{use of undeclared identifier 'seq'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial self(i > j, seq + for(;;){} + + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial self(i > j) + for(;;){} + + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} +#pragma acc serial self(1+5>3), seq + for(;;){} +} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc routine worker, vector, seq, nohost void bar(); -- GitLab From 22a73e7c4616e0405db85598c049a7ca70cca7cc Mon Sep 17 00:00:00 2001 From: carlobertolli Date: Mon, 8 Jan 2024 14:17:28 -0600 Subject: [PATCH 107/652] =?UTF-8?q?[OpenMP][libomptarget]=20Enable=20autom?= =?UTF-8?q?atic=20unified=20shared=20memory=20executi=E2=80=A6=20(#75999)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …on (zero-copy) on MI300A. This patch enables applications that did not request OpenMP unified_shared_memory to run with the same zero-copy behavior, where mapped memory does not result in extra memory allocations and memory copies, but CPU-allocated memory is accessed from the device. The name for this behavior is "automatic zero-copy" and it relies on detecting: that the runtime is running on a MI300A, that the user did not select unified_shared_memory in their program, and that XNACK (unified memory support) is enabled in the current GPU configuration. If all these conditions are met, then automatic zero-copy is triggered. This patch is still missing support for global variables, which will be provided in a subsequent patch. Co-authored-by: Thorsten Blass --- .../libomptarget/include/Shared/PluginAPI.h | 3 + .../libomptarget/include/Shared/PluginAPI.inc | 1 + .../include/Shared/Requirements.h | 15 ++++- openmp/libomptarget/include/device.h | 3 + .../plugins-nextgen/amdgpu/src/rtl.cpp | 47 ++++++++++++++- .../amdgpu/utils/UtilitiesRTL.h | 28 +++++++++ .../common/include/PluginInterface.h | 5 ++ .../common/src/PluginInterface.cpp | 10 ++++ openmp/libomptarget/src/OpenMP/Mapping.cpp | 12 +++- openmp/libomptarget/src/PluginManager.cpp | 14 +++++ openmp/libomptarget/src/device.cpp | 6 ++ .../test/mapping/auto_zero_copy.cpp | 59 +++++++++++++++++++ 12 files changed, 197 insertions(+), 6 deletions(-) create mode 100644 openmp/libomptarget/test/mapping/auto_zero_copy.cpp diff --git a/openmp/libomptarget/include/Shared/PluginAPI.h b/openmp/libomptarget/include/Shared/PluginAPI.h index c6aacf4ce212..aece53d7ee1c 100644 --- a/openmp/libomptarget/include/Shared/PluginAPI.h +++ b/openmp/libomptarget/include/Shared/PluginAPI.h @@ -219,6 +219,9 @@ int32_t __tgt_rtl_initialize_record_replay(int32_t DeviceId, int64_t MemorySize, void *VAddr, bool isRecord, bool SaveOutput, uint64_t &ReqPtrArgOffset); + +// Returns true if the device \p DeviceId suggests to use auto zero-copy. +int32_t __tgt_rtl_use_auto_zero_copy(int32_t DeviceId); } #endif // OMPTARGET_SHARED_PLUGIN_API_H diff --git a/openmp/libomptarget/include/Shared/PluginAPI.inc b/openmp/libomptarget/include/Shared/PluginAPI.inc index 25ebe7d437f9..b842c6eef1d4 100644 --- a/openmp/libomptarget/include/Shared/PluginAPI.inc +++ b/openmp/libomptarget/include/Shared/PluginAPI.inc @@ -47,3 +47,4 @@ PLUGIN_API_HANDLE(data_notify_mapped, false); PLUGIN_API_HANDLE(data_notify_unmapped, false); PLUGIN_API_HANDLE(set_device_offset, false); PLUGIN_API_HANDLE(initialize_record_replay, false); +PLUGIN_API_HANDLE(use_auto_zero_copy, false); diff --git a/openmp/libomptarget/include/Shared/Requirements.h b/openmp/libomptarget/include/Shared/Requirements.h index 19d6b8ffca49..b16a1650f0c4 100644 --- a/openmp/libomptarget/include/Shared/Requirements.h +++ b/openmp/libomptarget/include/Shared/Requirements.h @@ -33,7 +33,12 @@ enum OpenMPOffloadingRequiresDirFlags : int64_t { /// unified_shared_memory clause. OMP_REQ_UNIFIED_SHARED_MEMORY = 0x008, /// dynamic_allocators clause. - OMP_REQ_DYNAMIC_ALLOCATORS = 0x010 + OMP_REQ_DYNAMIC_ALLOCATORS = 0x010, + /// Auto zero-copy extension: + /// when running on an APU, the GPU plugin may decide to + /// run in zero-copy even though the user did not program + /// their application with unified_shared_memory requirement. + OMPX_REQ_AUTO_ZERO_COPY = 0x020 }; class RequirementCollection { @@ -65,6 +70,14 @@ public: return; } + // Auto zero-copy is only valid when no other requirement has been set + // and it is computed at device initialization time, after the requirement + // flag has already been set to OMP_REQ_NONE. + if (SetFlags == OMP_REQ_NONE && NewFlags == OMPX_REQ_AUTO_ZERO_COPY) { + SetFlags = NewFlags; + return; + } + // If multiple compilation units are present enforce // consistency across all of them for require clauses: // - reverse_offload diff --git a/openmp/libomptarget/include/device.h b/openmp/libomptarget/include/device.h index d28d3c508faf..8b4396ac468d 100644 --- a/openmp/libomptarget/include/device.h +++ b/openmp/libomptarget/include/device.h @@ -164,6 +164,9 @@ struct DeviceTy { /// Print all offload entries to stderr. void dumpOffloadEntries(); + /// Ask the device whether the runtime should use auto zero-copy. + bool useAutoZeroCopy(); + private: /// Deinitialize the device (and plugin). void deinit(); diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp index b67642e9e1bc..b5f0baee23dc 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp @@ -1848,8 +1848,9 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { OMPX_StreamBusyWait("LIBOMPTARGET_AMDGPU_STREAM_BUSYWAIT", 2000000), OMPX_UseMultipleSdmaEngines( "LIBOMPTARGET_AMDGPU_USE_MULTIPLE_SDMA_ENGINES", false), - AMDGPUStreamManager(*this, Agent), AMDGPUEventManager(*this), - AMDGPUSignalManager(*this), Agent(Agent), HostDevice(HostDevice) {} + HSAXnackEnv("HSA_XNACK", false), AMDGPUStreamManager(*this, Agent), + AMDGPUEventManager(*this), AMDGPUSignalManager(*this), Agent(Agent), + HostDevice(HostDevice) {} ~AMDGPUDeviceTy() {} @@ -1940,6 +1941,10 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { if (auto Err = AMDGPUSignalManager.init(OMPX_InitialNumSignals)) return Err; + // detect if device is an APU. + if (auto Err = checkIfAPU()) + return Err; + return Plugin::success(); } @@ -2631,6 +2636,14 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::success(); } + /// Returns true if auto zero-copy the best configuration for the current + /// arch. + bool useAutoZeroCopyImpl() override { + // XNACK can be enabled with with kernel boot parameter or with + // environment variable. + return (IsAPU && (HSAXnackEnv || utils::isXnackEnabledViaKernelParam())); + } + /// Getters and setters for stack and heap sizes. Error getDeviceStackSize(uint64_t &Value) override { Value = StackSize; @@ -2728,6 +2741,30 @@ private: return Err; } + /// Detect if current architecture is an APU. + Error checkIfAPU() { + std::string StrGfxName(ComputeUnitKind); + std::transform(std::begin(StrGfxName), std::end(StrGfxName), + std::begin(StrGfxName), + [](char c) { return std::tolower(c); }); + if (StrGfxName == "gfx940") { + IsAPU = true; + return Plugin::success(); + } + if (StrGfxName == "gfx942") { + // can be MI300A or MI300X + uint32_t ChipID = 0; + if (auto Err = getDeviceAttr(HSA_AMD_AGENT_INFO_CHIP_ID, ChipID)) + return Err; + + if (!(ChipID & 0x1)) { + IsAPU = true; + return Plugin::success(); + } + } + return Plugin::success(); + } + /// Envar for controlling the number of HSA queues per device. High number of /// queues may degrade performance. UInt32Envar OMPX_NumQueues; @@ -2764,6 +2801,9 @@ private: /// Use ROCm 5.7 interface for multiple SDMA engines BoolEnvar OMPX_UseMultipleSdmaEngines; + /// Value of HSA_XNACK environment variable. + BoolEnvar HSAXnackEnv; + /// Stream manager for AMDGPU streams. AMDGPUStreamManagerTy AMDGPUStreamManager; @@ -2794,6 +2834,9 @@ private: /// The current size of the stack that will be used in cases where it could /// not be statically determined. uint64_t StackSize = 16 * 1024 /* 16 KB */; + + /// Is the plugin associated with an APU? + bool IsAPU{false}; }; Error AMDGPUDeviceImageTy::loadExecutable(const AMDGPUDeviceTy &Device) { diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h b/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h index 58a3b5df00fa..c5a58f824414 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h @@ -116,6 +116,34 @@ inline bool isImageCompatibleWithEnv(StringRef ImageArch, uint32_t ImageFlags, return true; } +inline bool isXnackEnabledViaKernelParam() { + + ErrorOr> FileOrError = + MemoryBuffer::getFileAsStream("/proc/cmdline"); + + if (std::error_code ErrorCode = FileOrError.getError()) { + FAILURE_MESSAGE("Cannot open /proc/cmdline : %s\n", + ErrorCode.message().c_str()); + return false; + } + + StringRef FileContent = (FileOrError.get())->getBuffer(); + + StringRef RefString("amdgpu.noretry="); + int SizeOfRefString = RefString.size(); + + size_t Pos = FileContent.find_insensitive(RefString); + // Is noretry defined? + if (Pos != StringRef::npos) { + bool NoRetryValue = FileContent[Pos + SizeOfRefString] - '0'; + // is noretry set to 0 + if (!NoRetryValue) + return true; + } + + return false; +} + struct KernelMetaDataTy { uint64_t KernelObject; uint32_t GroupSegmentList; diff --git a/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h b/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h index b85dc146d86d..abe85f43c2e7 100644 --- a/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h +++ b/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h @@ -872,6 +872,11 @@ struct GenericDeviceTy : public DeviceAllocatorTy { virtual Error getDeviceStackSize(uint64_t &V) = 0; + /// Returns true if current plugin architecture is an APU + /// and unified_shared_memory was not requested by the program. + bool useAutoZeroCopy(); + virtual bool useAutoZeroCopyImpl() { return false; } + private: /// Register offload entry for global variable. Error registerGlobalOffloadEntry(DeviceImageTy &DeviceImage, diff --git a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp index 9490e58fc669..e82c2f7bef14 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp @@ -1561,6 +1561,8 @@ Error GenericDeviceTy::syncEvent(void *EventPtr) { return syncEventImpl(EventPtr); } +bool GenericDeviceTy::useAutoZeroCopy() { return useAutoZeroCopyImpl(); } + Error GenericPluginTy::init() { auto NumDevicesOrErr = initImpl(); if (!NumDevicesOrErr) @@ -2073,6 +2075,14 @@ int32_t __tgt_rtl_set_device_offset(int32_t DeviceIdOffset) { return OFFLOAD_SUCCESS; } +int32_t __tgt_rtl_use_auto_zero_copy(int32_t DeviceId) { + // Automatic zero-copy only applies to programs that did + // not request unified_shared_memory and are deployed on an + // APU with XNACK enabled. + if (Plugin::get().getRequiresFlags() & OMP_REQ_UNIFIED_SHARED_MEMORY) + return false; + return Plugin::get().getDevice(DeviceId).useAutoZeroCopy(); +} #ifdef __cplusplus } #endif diff --git a/openmp/libomptarget/src/OpenMP/Mapping.cpp b/openmp/libomptarget/src/OpenMP/Mapping.cpp index a5c24810e0af..87ab70dec2a2 100644 --- a/openmp/libomptarget/src/OpenMP/Mapping.cpp +++ b/openmp/libomptarget/src/OpenMP/Mapping.cpp @@ -252,8 +252,9 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( MESSAGE("device mapping required by 'present' map type modifier does not " "exist for host address " DPxMOD " (%" PRId64 " bytes)", DPxPTR(HstPtrBegin), Size); - } else if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY && - !HasCloseModifier) { + } else if ((PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY && + !HasCloseModifier) || + (PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY)) { // If unified shared memory is active, implicitly mapped variables that are // not privatized use host address. Any explicitly mapped variables also use // host address where correctness is not impeded. In all other cases maps @@ -261,6 +262,10 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( // In addition to the mapping rules above, the close map modifier forces the // mapping of the variable to the device. if (Size) { + INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, + "Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " + "memory\n", + DPxPTR((uintptr_t)HstPtrBegin), Size); DP("Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " "memory\n", DPxPTR((uintptr_t)HstPtrBegin), Size); @@ -415,7 +420,8 @@ TargetPointerResultTy MappingInfoTy::getTgtPtrBegin( LR.TPR.getEntry()->dynRefCountToStr().c_str(), DynRefCountAction, LR.TPR.getEntry()->holdRefCountToStr().c_str(), HoldRefCountAction); LR.TPR.TargetPointer = (void *)TP; - } else if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY) { + } else if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY || + PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY) { // If the value isn't found in the mapping and unified shared memory // is on then it means we have stumbled upon a value which we need to // use directly from the host. diff --git a/openmp/libomptarget/src/PluginManager.cpp b/openmp/libomptarget/src/PluginManager.cpp index da2e08180eea..82b0ecdcd647 100644 --- a/openmp/libomptarget/src/PluginManager.cpp +++ b/openmp/libomptarget/src/PluginManager.cpp @@ -144,19 +144,33 @@ void PluginAdaptorTy::initDevices(PluginManager &PM) { int32_t NumPD = getNumberOfPluginDevices(); ExclusiveDevicesAccessor->reserve(DeviceOffset + NumPD); + // Auto zero-copy is a per-device property. We need to ensure + // that all devices are suggesting to use it. + bool UseAutoZeroCopy = true; + if (NumPD == 0) + UseAutoZeroCopy = false; for (int32_t PDevI = 0, UserDevId = DeviceOffset; PDevI < NumPD; PDevI++) { auto Device = std::make_unique(this, UserDevId, PDevI); + if (auto Err = Device->init()) { DP("Skip plugin known device %d: %s\n", PDevI, toString(std::move(Err)).c_str()); continue; } + UseAutoZeroCopy = UseAutoZeroCopy && Device->useAutoZeroCopy(); ExclusiveDevicesAccessor->push_back(std::move(Device)); ++NumberOfUserDevices; ++UserDevId; } + // Auto Zero-Copy can only be currently triggered when the system is an + // homogeneous APU architecture without attached discrete GPUs. + // If all devices suggest to use it, change requirment flags to trigger + // zero-copy behavior when mapping memory. + if (UseAutoZeroCopy) + PM.addRequirements(OMPX_REQ_AUTO_ZERO_COPY); + DP("Plugin adaptor " DPxMOD " has index %d, exposes %d out of %d devices!\n", DPxPTR(LibraryHandler.get()), DeviceOffset, NumberOfUserDevices, NumberOfPluginDevices); diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index dbad13b92bcc..919c4b55c036 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -340,3 +340,9 @@ void DeviceTy::dumpOffloadEntries() { fprintf(stderr, " %11s: %s\n", Kind, It.second->getNameAsCStr()); } } + +bool DeviceTy::useAutoZeroCopy() { + if (RTL->use_auto_zero_copy) + return RTL->use_auto_zero_copy(RTLDeviceID); + return false; +} diff --git a/openmp/libomptarget/test/mapping/auto_zero_copy.cpp b/openmp/libomptarget/test/mapping/auto_zero_copy.cpp new file mode 100644 index 000000000000..80bb3d24a0c6 --- /dev/null +++ b/openmp/libomptarget/test/mapping/auto_zero_copy.cpp @@ -0,0 +1,59 @@ + +// RUN: %libomptarget-compilexx-generic +// RUN: env HSA_XNACK=1 LIBOMPTARGET_INFO=30 %libomptarget-run-generic 2>&1 \ +// RUN: | %fcheck-generic -check-prefix=INFO_ZERO -check-prefix=CHECK + +// RUN: %libomptarget-compilexx-generic +// RUN: env HSA_XNACK=1 LIBOMPTARGET_INFO=30 USE_USM=1 %libomptarget-run-generic 2>&1 \ +// RUN: | %fcheck-generic -check-prefix=INFO_ZERO -check-prefix=CHECK + +// RUN: %libomptarget-compilexx-generic +// RUN: env HSA_XNACK=0 LIBOMPTARGET_INFO=30 %libomptarget-run-generic 2>&1 \ +// RUN: | %fcheck-generic -check-prefix=INFO_COPY -check-prefix=CHECK + +// UNSUPPORTED: aarch64-unknown-linux-gnu +// UNSUPPORTED: aarch64-unknown-linux-gnu-LTO +// UNSUPPORTED: nvptx64-nvidia-cuda +// UNSUPPORTED: nvptx64-nvidia-cuda-LTO +// UNSUPPORTED: x86_64-pc-linux-gnu +// UNSUPPORTED: x86_64-pc-linux-gnu-LTO + +#include + +#if (USE_USM == 1) +#pragma omp requires unified_shared_memory +#endif + +int main() { + int n = 1024; + + // test various mapping types + int *a = new int[n]; + int k = 3; + int b[n]; + + for (int i = 0; i < n; i++) + b[i] = i; + + // INFO_ZERO: Return HstPtrBegin 0x{{.*}} Size=4096 for unified shared memory + // INFO_ZERO: Return HstPtrBegin 0x{{.*}} Size=4096 for unified shared memory + + // INFO_COPY: Creating new map entry with HstPtrBase=0x{{.*}}, HstPtrBegin=0x{{.*}}, TgtAllocBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, + // INFO_COPY: Creating new map entry with HstPtrBase=0x{{.*}}, HstPtrBegin=0x{{.*}}, TgtAllocBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, + // INFO_COPY: Mapping exists with HstPtrBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, DynRefCount=1 (update suppressed) + // INFO_COPY: Mapping exists with HstPtrBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, DynRefCount=1 (update suppressed) +#pragma omp target teams distribute parallel for map(tofrom : a[ : n]) \ + map(to : b[ : n]) + for (int i = 0; i < n; i++) + a[i] = i + b[i] + k; + + int err = 0; + for (int i = 0; i < n; i++) + if (a[i] != i + b[i] + k) + err++; + + // CHECK: PASS + if (err == 0) + printf("PASS\n"); + return err; +} -- GitLab From 6684a09ca84b44f320052a77cb01cb4216e6511b Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 8 Jan 2024 12:20:17 -0800 Subject: [PATCH 108/652] [Driver] Add the --gcc-triple option (#73214) When --gcc-triple is used, the driver will search for the 'best' gcc installation that has the given triple. This is useful for distributions that want clang to use a specific gcc triple, but do not want to pin to a specific version as would be required by using --gcc-install-dir. Having clang linked to a specific gcc version can cause clang to stop working when the version of gcc installed on the system gets updated. --- clang/include/clang/Driver/Options.td | 2 ++ clang/lib/Driver/ToolChains/Gnu.cpp | 9 +++++++++ .../usr/lib/gcc/x86_64-linux-gnu/13/crtbegin.o | 0 .../usr/lib/gcc/x86_64-linux-gnu/13/crtend.o | 0 .../usr/lib/gcc/x86_64-linux-gnu/13/crti.o | 0 .../usr/lib/gcc/x86_64-linux-gnu/13/crtn.o | 0 .../usr/lib/gcc/x86_64-redhat-linux/13/crtbegin.o | 0 .../usr/lib/gcc/x86_64-redhat-linux/13/crtend.o | 0 .../usr/lib/gcc/x86_64-redhat-linux/13/crti.o | 0 .../usr/lib/gcc/x86_64-redhat-linux/13/crtn.o | 0 clang/test/Driver/gcc-triple.cpp | 14 ++++++++++++++ 11 files changed, 25 insertions(+) create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtbegin.o create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtend.o create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crti.o create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtn.o create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtbegin.o create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtend.o create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crti.o create mode 100644 clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtn.o create mode 100644 clang/test/Driver/gcc-triple.cpp diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 6aff37f13368..bffdddc28aac 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -773,6 +773,8 @@ def gcc_install_dir_EQ : Joined<["--"], "gcc-install-dir=">, def gcc_toolchain : Joined<["--"], "gcc-toolchain=">, Flags<[NoXarchOption]>, HelpText<"Specify a directory where Clang can find 'include' and 'lib{,32,64}/gcc{,-cross}/$triple/$version'. " "Clang will use the GCC installation with the largest version">; +def gcc_triple_EQ : Joined<["--"], "gcc-triple=">, + HelpText<"Search for the GCC installation with the specified triple.">; def CC : Flag<["-"], "CC">, Visibility<[ClangOption, CC1Option]>, Group, HelpText<"Include comments from within macros in preprocessed output">, diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index a610a94a39a2..24681dfdc99c 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -2251,6 +2251,15 @@ void Generic_GCC::GCCInstallationDetector::init( return; } + // If --gcc-triple is specified use this instead of trying to + // auto-detect a triple. + if (const Arg *A = + Args.getLastArg(clang::driver::options::OPT_gcc_triple_EQ)) { + StringRef GCCTriple = A->getValue(); + CandidateTripleAliases.clear(); + CandidateTripleAliases.push_back(GCCTriple); + } + // Compute the set of prefixes for our search. SmallVector Prefixes; StringRef GCCToolchainDir = getGCCToolchainDir(Args, D.SysRoot); diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtbegin.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtbegin.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtend.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtend.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crti.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crti.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtn.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-linux-gnu/13/crtn.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtbegin.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtbegin.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtend.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtend.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crti.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crti.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtn.o b/clang/test/Driver/Inputs/fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13/crtn.o new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/clang/test/Driver/gcc-triple.cpp b/clang/test/Driver/gcc-triple.cpp new file mode 100644 index 000000000000..17f045dae747 --- /dev/null +++ b/clang/test/Driver/gcc-triple.cpp @@ -0,0 +1,14 @@ +// UNSUPPORTED: system-windows + +// RUN: %clang --target=x86_64-redhat-linux-gnu \ +// RUN: --sysroot=%S/Inputs/fedora_39_tree --gcc-triple=x86_64-redhat-linux -v 2>&1 | \ +// RUN: FileCheck %s --check-prefix=TRIPLE_EXISTS + +// TRIPLE_EXISTS: {{^}}Selected GCC installation: +// TRIPLE_EXISTS: fedora_39_tree/usr/lib/gcc/x86_64-redhat-linux/13{{$}} + +// RUN: %clang --target=x86_64-redhat-linux-gnu \ +// RUN: --sysroot=%S/Inputs/fedora_39_tree --gcc-triple=x86_64-gentoo-linux -v 2>&1 | \ +// RUN: FileCheck %s --check-prefix=TRIPLE_DOESNT_EXIST + +// TRIPLE_DOESNT_EXIST-NOT: x86_64-gentoo-linux -- GitLab From ce4144406c94c3b9cf44bcf2997bae80debc6681 Mon Sep 17 00:00:00 2001 From: carlobertolli Date: Mon, 8 Jan 2024 14:38:29 -0600 Subject: [PATCH 109/652] =?UTF-8?q?Revert=20"[OpenMP][libomptarget]=20Enab?= =?UTF-8?q?le=20automatic=20unified=20shared=20memory=20executi=E2=80=A6"?= =?UTF-8?q?=20(#77371)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reverts llvm/llvm-project#75999 lit test is failing. --- .../libomptarget/include/Shared/PluginAPI.h | 3 - .../libomptarget/include/Shared/PluginAPI.inc | 1 - .../include/Shared/Requirements.h | 15 +---- openmp/libomptarget/include/device.h | 3 - .../plugins-nextgen/amdgpu/src/rtl.cpp | 47 +-------------- .../amdgpu/utils/UtilitiesRTL.h | 28 --------- .../common/include/PluginInterface.h | 5 -- .../common/src/PluginInterface.cpp | 10 ---- openmp/libomptarget/src/OpenMP/Mapping.cpp | 12 +--- openmp/libomptarget/src/PluginManager.cpp | 14 ----- openmp/libomptarget/src/device.cpp | 6 -- .../test/mapping/auto_zero_copy.cpp | 59 ------------------- 12 files changed, 6 insertions(+), 197 deletions(-) delete mode 100644 openmp/libomptarget/test/mapping/auto_zero_copy.cpp diff --git a/openmp/libomptarget/include/Shared/PluginAPI.h b/openmp/libomptarget/include/Shared/PluginAPI.h index aece53d7ee1c..c6aacf4ce212 100644 --- a/openmp/libomptarget/include/Shared/PluginAPI.h +++ b/openmp/libomptarget/include/Shared/PluginAPI.h @@ -219,9 +219,6 @@ int32_t __tgt_rtl_initialize_record_replay(int32_t DeviceId, int64_t MemorySize, void *VAddr, bool isRecord, bool SaveOutput, uint64_t &ReqPtrArgOffset); - -// Returns true if the device \p DeviceId suggests to use auto zero-copy. -int32_t __tgt_rtl_use_auto_zero_copy(int32_t DeviceId); } #endif // OMPTARGET_SHARED_PLUGIN_API_H diff --git a/openmp/libomptarget/include/Shared/PluginAPI.inc b/openmp/libomptarget/include/Shared/PluginAPI.inc index b842c6eef1d4..25ebe7d437f9 100644 --- a/openmp/libomptarget/include/Shared/PluginAPI.inc +++ b/openmp/libomptarget/include/Shared/PluginAPI.inc @@ -47,4 +47,3 @@ PLUGIN_API_HANDLE(data_notify_mapped, false); PLUGIN_API_HANDLE(data_notify_unmapped, false); PLUGIN_API_HANDLE(set_device_offset, false); PLUGIN_API_HANDLE(initialize_record_replay, false); -PLUGIN_API_HANDLE(use_auto_zero_copy, false); diff --git a/openmp/libomptarget/include/Shared/Requirements.h b/openmp/libomptarget/include/Shared/Requirements.h index b16a1650f0c4..19d6b8ffca49 100644 --- a/openmp/libomptarget/include/Shared/Requirements.h +++ b/openmp/libomptarget/include/Shared/Requirements.h @@ -33,12 +33,7 @@ enum OpenMPOffloadingRequiresDirFlags : int64_t { /// unified_shared_memory clause. OMP_REQ_UNIFIED_SHARED_MEMORY = 0x008, /// dynamic_allocators clause. - OMP_REQ_DYNAMIC_ALLOCATORS = 0x010, - /// Auto zero-copy extension: - /// when running on an APU, the GPU plugin may decide to - /// run in zero-copy even though the user did not program - /// their application with unified_shared_memory requirement. - OMPX_REQ_AUTO_ZERO_COPY = 0x020 + OMP_REQ_DYNAMIC_ALLOCATORS = 0x010 }; class RequirementCollection { @@ -70,14 +65,6 @@ public: return; } - // Auto zero-copy is only valid when no other requirement has been set - // and it is computed at device initialization time, after the requirement - // flag has already been set to OMP_REQ_NONE. - if (SetFlags == OMP_REQ_NONE && NewFlags == OMPX_REQ_AUTO_ZERO_COPY) { - SetFlags = NewFlags; - return; - } - // If multiple compilation units are present enforce // consistency across all of them for require clauses: // - reverse_offload diff --git a/openmp/libomptarget/include/device.h b/openmp/libomptarget/include/device.h index 8b4396ac468d..d28d3c508faf 100644 --- a/openmp/libomptarget/include/device.h +++ b/openmp/libomptarget/include/device.h @@ -164,9 +164,6 @@ struct DeviceTy { /// Print all offload entries to stderr. void dumpOffloadEntries(); - /// Ask the device whether the runtime should use auto zero-copy. - bool useAutoZeroCopy(); - private: /// Deinitialize the device (and plugin). void deinit(); diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp index b5f0baee23dc..b67642e9e1bc 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp @@ -1848,9 +1848,8 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { OMPX_StreamBusyWait("LIBOMPTARGET_AMDGPU_STREAM_BUSYWAIT", 2000000), OMPX_UseMultipleSdmaEngines( "LIBOMPTARGET_AMDGPU_USE_MULTIPLE_SDMA_ENGINES", false), - HSAXnackEnv("HSA_XNACK", false), AMDGPUStreamManager(*this, Agent), - AMDGPUEventManager(*this), AMDGPUSignalManager(*this), Agent(Agent), - HostDevice(HostDevice) {} + AMDGPUStreamManager(*this, Agent), AMDGPUEventManager(*this), + AMDGPUSignalManager(*this), Agent(Agent), HostDevice(HostDevice) {} ~AMDGPUDeviceTy() {} @@ -1941,10 +1940,6 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { if (auto Err = AMDGPUSignalManager.init(OMPX_InitialNumSignals)) return Err; - // detect if device is an APU. - if (auto Err = checkIfAPU()) - return Err; - return Plugin::success(); } @@ -2636,14 +2631,6 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::success(); } - /// Returns true if auto zero-copy the best configuration for the current - /// arch. - bool useAutoZeroCopyImpl() override { - // XNACK can be enabled with with kernel boot parameter or with - // environment variable. - return (IsAPU && (HSAXnackEnv || utils::isXnackEnabledViaKernelParam())); - } - /// Getters and setters for stack and heap sizes. Error getDeviceStackSize(uint64_t &Value) override { Value = StackSize; @@ -2741,30 +2728,6 @@ private: return Err; } - /// Detect if current architecture is an APU. - Error checkIfAPU() { - std::string StrGfxName(ComputeUnitKind); - std::transform(std::begin(StrGfxName), std::end(StrGfxName), - std::begin(StrGfxName), - [](char c) { return std::tolower(c); }); - if (StrGfxName == "gfx940") { - IsAPU = true; - return Plugin::success(); - } - if (StrGfxName == "gfx942") { - // can be MI300A or MI300X - uint32_t ChipID = 0; - if (auto Err = getDeviceAttr(HSA_AMD_AGENT_INFO_CHIP_ID, ChipID)) - return Err; - - if (!(ChipID & 0x1)) { - IsAPU = true; - return Plugin::success(); - } - } - return Plugin::success(); - } - /// Envar for controlling the number of HSA queues per device. High number of /// queues may degrade performance. UInt32Envar OMPX_NumQueues; @@ -2801,9 +2764,6 @@ private: /// Use ROCm 5.7 interface for multiple SDMA engines BoolEnvar OMPX_UseMultipleSdmaEngines; - /// Value of HSA_XNACK environment variable. - BoolEnvar HSAXnackEnv; - /// Stream manager for AMDGPU streams. AMDGPUStreamManagerTy AMDGPUStreamManager; @@ -2834,9 +2794,6 @@ private: /// The current size of the stack that will be used in cases where it could /// not be statically determined. uint64_t StackSize = 16 * 1024 /* 16 KB */; - - /// Is the plugin associated with an APU? - bool IsAPU{false}; }; Error AMDGPUDeviceImageTy::loadExecutable(const AMDGPUDeviceTy &Device) { diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h b/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h index c5a58f824414..58a3b5df00fa 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h @@ -116,34 +116,6 @@ inline bool isImageCompatibleWithEnv(StringRef ImageArch, uint32_t ImageFlags, return true; } -inline bool isXnackEnabledViaKernelParam() { - - ErrorOr> FileOrError = - MemoryBuffer::getFileAsStream("/proc/cmdline"); - - if (std::error_code ErrorCode = FileOrError.getError()) { - FAILURE_MESSAGE("Cannot open /proc/cmdline : %s\n", - ErrorCode.message().c_str()); - return false; - } - - StringRef FileContent = (FileOrError.get())->getBuffer(); - - StringRef RefString("amdgpu.noretry="); - int SizeOfRefString = RefString.size(); - - size_t Pos = FileContent.find_insensitive(RefString); - // Is noretry defined? - if (Pos != StringRef::npos) { - bool NoRetryValue = FileContent[Pos + SizeOfRefString] - '0'; - // is noretry set to 0 - if (!NoRetryValue) - return true; - } - - return false; -} - struct KernelMetaDataTy { uint64_t KernelObject; uint32_t GroupSegmentList; diff --git a/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h b/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h index abe85f43c2e7..b85dc146d86d 100644 --- a/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h +++ b/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h @@ -872,11 +872,6 @@ struct GenericDeviceTy : public DeviceAllocatorTy { virtual Error getDeviceStackSize(uint64_t &V) = 0; - /// Returns true if current plugin architecture is an APU - /// and unified_shared_memory was not requested by the program. - bool useAutoZeroCopy(); - virtual bool useAutoZeroCopyImpl() { return false; } - private: /// Register offload entry for global variable. Error registerGlobalOffloadEntry(DeviceImageTy &DeviceImage, diff --git a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp index e82c2f7bef14..9490e58fc669 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp @@ -1561,8 +1561,6 @@ Error GenericDeviceTy::syncEvent(void *EventPtr) { return syncEventImpl(EventPtr); } -bool GenericDeviceTy::useAutoZeroCopy() { return useAutoZeroCopyImpl(); } - Error GenericPluginTy::init() { auto NumDevicesOrErr = initImpl(); if (!NumDevicesOrErr) @@ -2075,14 +2073,6 @@ int32_t __tgt_rtl_set_device_offset(int32_t DeviceIdOffset) { return OFFLOAD_SUCCESS; } -int32_t __tgt_rtl_use_auto_zero_copy(int32_t DeviceId) { - // Automatic zero-copy only applies to programs that did - // not request unified_shared_memory and are deployed on an - // APU with XNACK enabled. - if (Plugin::get().getRequiresFlags() & OMP_REQ_UNIFIED_SHARED_MEMORY) - return false; - return Plugin::get().getDevice(DeviceId).useAutoZeroCopy(); -} #ifdef __cplusplus } #endif diff --git a/openmp/libomptarget/src/OpenMP/Mapping.cpp b/openmp/libomptarget/src/OpenMP/Mapping.cpp index 87ab70dec2a2..a5c24810e0af 100644 --- a/openmp/libomptarget/src/OpenMP/Mapping.cpp +++ b/openmp/libomptarget/src/OpenMP/Mapping.cpp @@ -252,9 +252,8 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( MESSAGE("device mapping required by 'present' map type modifier does not " "exist for host address " DPxMOD " (%" PRId64 " bytes)", DPxPTR(HstPtrBegin), Size); - } else if ((PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY && - !HasCloseModifier) || - (PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY)) { + } else if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY && + !HasCloseModifier) { // If unified shared memory is active, implicitly mapped variables that are // not privatized use host address. Any explicitly mapped variables also use // host address where correctness is not impeded. In all other cases maps @@ -262,10 +261,6 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( // In addition to the mapping rules above, the close map modifier forces the // mapping of the variable to the device. if (Size) { - INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, - "Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " - "memory\n", - DPxPTR((uintptr_t)HstPtrBegin), Size); DP("Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " "memory\n", DPxPTR((uintptr_t)HstPtrBegin), Size); @@ -420,8 +415,7 @@ TargetPointerResultTy MappingInfoTy::getTgtPtrBegin( LR.TPR.getEntry()->dynRefCountToStr().c_str(), DynRefCountAction, LR.TPR.getEntry()->holdRefCountToStr().c_str(), HoldRefCountAction); LR.TPR.TargetPointer = (void *)TP; - } else if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY || - PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY) { + } else if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY) { // If the value isn't found in the mapping and unified shared memory // is on then it means we have stumbled upon a value which we need to // use directly from the host. diff --git a/openmp/libomptarget/src/PluginManager.cpp b/openmp/libomptarget/src/PluginManager.cpp index 82b0ecdcd647..da2e08180eea 100644 --- a/openmp/libomptarget/src/PluginManager.cpp +++ b/openmp/libomptarget/src/PluginManager.cpp @@ -144,33 +144,19 @@ void PluginAdaptorTy::initDevices(PluginManager &PM) { int32_t NumPD = getNumberOfPluginDevices(); ExclusiveDevicesAccessor->reserve(DeviceOffset + NumPD); - // Auto zero-copy is a per-device property. We need to ensure - // that all devices are suggesting to use it. - bool UseAutoZeroCopy = true; - if (NumPD == 0) - UseAutoZeroCopy = false; for (int32_t PDevI = 0, UserDevId = DeviceOffset; PDevI < NumPD; PDevI++) { auto Device = std::make_unique(this, UserDevId, PDevI); - if (auto Err = Device->init()) { DP("Skip plugin known device %d: %s\n", PDevI, toString(std::move(Err)).c_str()); continue; } - UseAutoZeroCopy = UseAutoZeroCopy && Device->useAutoZeroCopy(); ExclusiveDevicesAccessor->push_back(std::move(Device)); ++NumberOfUserDevices; ++UserDevId; } - // Auto Zero-Copy can only be currently triggered when the system is an - // homogeneous APU architecture without attached discrete GPUs. - // If all devices suggest to use it, change requirment flags to trigger - // zero-copy behavior when mapping memory. - if (UseAutoZeroCopy) - PM.addRequirements(OMPX_REQ_AUTO_ZERO_COPY); - DP("Plugin adaptor " DPxMOD " has index %d, exposes %d out of %d devices!\n", DPxPTR(LibraryHandler.get()), DeviceOffset, NumberOfUserDevices, NumberOfPluginDevices); diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index 919c4b55c036..dbad13b92bcc 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -340,9 +340,3 @@ void DeviceTy::dumpOffloadEntries() { fprintf(stderr, " %11s: %s\n", Kind, It.second->getNameAsCStr()); } } - -bool DeviceTy::useAutoZeroCopy() { - if (RTL->use_auto_zero_copy) - return RTL->use_auto_zero_copy(RTLDeviceID); - return false; -} diff --git a/openmp/libomptarget/test/mapping/auto_zero_copy.cpp b/openmp/libomptarget/test/mapping/auto_zero_copy.cpp deleted file mode 100644 index 80bb3d24a0c6..000000000000 --- a/openmp/libomptarget/test/mapping/auto_zero_copy.cpp +++ /dev/null @@ -1,59 +0,0 @@ - -// RUN: %libomptarget-compilexx-generic -// RUN: env HSA_XNACK=1 LIBOMPTARGET_INFO=30 %libomptarget-run-generic 2>&1 \ -// RUN: | %fcheck-generic -check-prefix=INFO_ZERO -check-prefix=CHECK - -// RUN: %libomptarget-compilexx-generic -// RUN: env HSA_XNACK=1 LIBOMPTARGET_INFO=30 USE_USM=1 %libomptarget-run-generic 2>&1 \ -// RUN: | %fcheck-generic -check-prefix=INFO_ZERO -check-prefix=CHECK - -// RUN: %libomptarget-compilexx-generic -// RUN: env HSA_XNACK=0 LIBOMPTARGET_INFO=30 %libomptarget-run-generic 2>&1 \ -// RUN: | %fcheck-generic -check-prefix=INFO_COPY -check-prefix=CHECK - -// UNSUPPORTED: aarch64-unknown-linux-gnu -// UNSUPPORTED: aarch64-unknown-linux-gnu-LTO -// UNSUPPORTED: nvptx64-nvidia-cuda -// UNSUPPORTED: nvptx64-nvidia-cuda-LTO -// UNSUPPORTED: x86_64-pc-linux-gnu -// UNSUPPORTED: x86_64-pc-linux-gnu-LTO - -#include - -#if (USE_USM == 1) -#pragma omp requires unified_shared_memory -#endif - -int main() { - int n = 1024; - - // test various mapping types - int *a = new int[n]; - int k = 3; - int b[n]; - - for (int i = 0; i < n; i++) - b[i] = i; - - // INFO_ZERO: Return HstPtrBegin 0x{{.*}} Size=4096 for unified shared memory - // INFO_ZERO: Return HstPtrBegin 0x{{.*}} Size=4096 for unified shared memory - - // INFO_COPY: Creating new map entry with HstPtrBase=0x{{.*}}, HstPtrBegin=0x{{.*}}, TgtAllocBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, - // INFO_COPY: Creating new map entry with HstPtrBase=0x{{.*}}, HstPtrBegin=0x{{.*}}, TgtAllocBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, - // INFO_COPY: Mapping exists with HstPtrBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, DynRefCount=1 (update suppressed) - // INFO_COPY: Mapping exists with HstPtrBegin=0x{{.*}}, TgtPtrBegin=0x{{.*}}, Size=4096, DynRefCount=1 (update suppressed) -#pragma omp target teams distribute parallel for map(tofrom : a[ : n]) \ - map(to : b[ : n]) - for (int i = 0; i < n; i++) - a[i] = i + b[i] + k; - - int err = 0; - for (int i = 0; i < n; i++) - if (a[i] != i + b[i] + k) - err++; - - // CHECK: PASS - if (err == 0) - printf("PASS\n"); - return err; -} -- GitLab From ce1305a3cea42dad8dd6ee5606dd4259e8632953 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 13:09:58 -0800 Subject: [PATCH 110/652] [libc] make off_t 32b for 32b arm (#77350) Fixes the following diagnostic: llvm-project/libc/src/sys/mman/linux/mmap.cpp:44:59: error: implicit conversion loses integer precision: 'off_t' (aka 'long long') to 'long' [-Werror,-Wshorten-64-to-32] size, prot, flags, fd, offset); ^~~~~~ It looks like off_t is a curious types on different platforms. FWICT, it's 32b on arm (at least for arm-linux-gnueabi) but 64b elsewhere (including 32b riscv32-linux-gnu). --- libc/include/llvm-libc-types/off_t.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libc/include/llvm-libc-types/off_t.h b/libc/include/llvm-libc-types/off_t.h index 111b29aa68d8..a0cbe992189d 100644 --- a/libc/include/llvm-libc-types/off_t.h +++ b/libc/include/llvm-libc-types/off_t.h @@ -9,6 +9,10 @@ #ifndef __LLVM_LIBC_TYPES_OFF_T_H__ #define __LLVM_LIBC_TYPES_OFF_T_H__ +#if defined(__LP64__) || defined(__riscv) typedef __INT64_TYPE__ off_t; +#else +typedef __INT32_TYPE__ off_t; +#endif // __LP64__ || __riscv #endif // __LLVM_LIBC_TYPES_OFF_T_H__ -- GitLab From 4435ced94998c00a6589c3500822015b6341c9e3 Mon Sep 17 00:00:00 2001 From: MaheshRavishankar <1663364+MaheshRavishankar@users.noreply.github.com> Date: Mon, 8 Jan 2024 13:26:10 -0800 Subject: [PATCH 111/652] [mlir][TilingInterface] Allow controlling what fusion is done within tile and fuse (#76871) Currently the `tileConsumerAndFuseProducerGreedilyUsingSCFFor` method greedily fuses through all slices that are generated during the tile and fuse flow. That is not the normal use case. Ideally the caller would like to control which slices get fused and which dont. This patch introduces a new field to the `SCFTileAndFuseOptions` to specify this control. The contol function also allows the caller to specify if the replacement for the fused producer needs to be yielded from within the tiled computation. This allows replacing the fused producers in case they have other uses. Without this the original producers still survive negating the utility of the fusion. The change here also means that the name of the function `tileConsumerAndFuseProducerGreedily...` can be updated. Defering that to a later stage to reduce the churn of API changes. --- .../SCF/Transforms/TileUsingInterface.h | 24 +++++ .../SCF/Transforms/TileUsingInterface.cpp | 65 ++++++++---- .../TilingInterface/TestTilingInterface.cpp | 98 +++++++------------ 3 files changed, 105 insertions(+), 82 deletions(-) diff --git a/mlir/include/mlir/Dialect/SCF/Transforms/TileUsingInterface.h b/mlir/include/mlir/Dialect/SCF/Transforms/TileUsingInterface.h index 2f8f337bb805..5d2d78e6e616 100644 --- a/mlir/include/mlir/Dialect/SCF/Transforms/TileUsingInterface.h +++ b/mlir/include/mlir/Dialect/SCF/Transforms/TileUsingInterface.h @@ -97,6 +97,30 @@ struct SCFTileAndFuseOptions { tilingOptions = options; return *this; } + + /// Control function to check if a slice needs to be fused or not, + /// The control function receives + /// 1) the slice along which fusion is to be done, + /// 2) the producer value that is to be fused + /// 3) a boolean value set to `true` if the fusion is from + /// a destination operand. + /// It retuns two booleans + /// - returns `true` if the fusion should be done through the candidate slice + /// - returns `true` if a replacement for the fused producer needs to be + /// yielded from within the tiled loop. Note that it is valid to return + /// `true` only if the slice fused is disjoint across all iterations of the + /// tiled loop. It is up to the caller to ensure that this is true for the + /// fused producers. + using ControlFnTy = std::function( + tensor::ExtractSliceOp candidateSliceOp, OpResult originalProducer, + bool isDestinationOperand)>; + ControlFnTy fusionControlFn = [](tensor::ExtractSliceOp, OpResult, bool) { + return std::make_tuple(true, false); + }; + SCFTileAndFuseOptions &setFusionControlFn(ControlFnTy controlFn) { + fusionControlFn = controlFn; + return *this; + } }; /// Fuse the producer of the source of `candidateSliceOp` by computing the diff --git a/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp b/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp index 1b6b4db9d209..22826cababe7 100644 --- a/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp +++ b/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp @@ -728,32 +728,36 @@ mlir::scf::tileConsumerAndFuseProducerGreedilyUsingSCFForOp( } // 1. First tile the consumer. - SmallVector forLoops; SetVector fusedProducers, tiledAndFusedOps; - DenseMap replacements; - llvm::SmallDenseMap yieldedValueToResultNumber; - { - FailureOr tilingResult = - tileUsingSCFForOp(rewriter, consumer, options.tilingOptions); - if (failed(tilingResult)) - return rewriter.notifyMatchFailure(consumer, "failed to tile consumer"); - for (auto *tiledOp : tilingResult->tiledOps) - tiledAndFusedOps.insert(tiledOp); - forLoops = castToTypedOperations(tilingResult->loops); - for (auto [index, origValue, replacement] : - llvm::enumerate(consumer->getResults(), tilingResult->replacements)) { - replacements[origValue] = replacement; - yieldedValueToResultNumber[tilingResult->tiledOps.back()->getResult( - index)] = index; - } - } + llvm::SmallDenseMap origProducerToLoopResultNum; + FailureOr tilingResult = + tileUsingSCFForOp(rewriter, consumer, options.tilingOptions); + if (failed(tilingResult)) + return rewriter.notifyMatchFailure(consumer, "failed to tile consumer"); + for (auto *tiledOp : tilingResult->tiledOps) + tiledAndFusedOps.insert(tiledOp); + SmallVector forLoops = + castToTypedOperations(tilingResult->loops); // If there are no loops generated, fusion is immaterial. if (forLoops.empty()) { + DenseMap replacements; + for (auto [origVal, replacement] : + llvm::zip_equal(consumer->getResults(), tilingResult->replacements)) { + replacements[origVal] = replacement; + } return scf::SCFTileAndFuseResult{fusedProducers, tiledAndFusedOps, getAsOperations(forLoops), replacements}; } + // To keep track of replacements for now just record the map from the original + // untiled value to the result number of the for loop. Since the loop gets + // potentially replaced during fusion, keeping the value directly wont work. + DenseMap origValToResultNumber; + for (auto [index, result] : llvm::enumerate(consumer->getResults())) { + origValToResultNumber[result] = index; + } + // 2. Typically, the operands of the tiled operation are slices of the // operands of the untiled operation. These are expressed in IR using // `tensor.extract_slice` operations with source being the operands of the @@ -776,6 +780,18 @@ mlir::scf::tileConsumerAndFuseProducerGreedilyUsingSCFForOp( tensor::ExtractSliceOp candidateSliceOp = candidates.front(); candidates.pop_front(); + // Find the original producer of the slice. + auto [fusableProducer, destinationInitArg] = + getUntiledProducerFromSliceSource(&candidateSliceOp.getSourceMutable(), + forLoops); + if (!fusableProducer) + continue; + + auto [fuseSlice, yieldReplacement] = options.fusionControlFn( + candidateSliceOp, fusableProducer, destinationInitArg.has_value()); + if (!fuseSlice) + continue; + // The operands of the fused producer might themselved be slices of // values produced by operations that implement the `TilingInterface`. // Add these operations to the worklist. @@ -784,6 +800,13 @@ mlir::scf::tileConsumerAndFuseProducerGreedilyUsingSCFForOp( if (!fusedResult) continue; + if (yieldReplacement) { + yieldReplacementForFusedProducer(rewriter, candidateSliceOp, + fusedResult.value(), forLoops); + origValToResultNumber[fusableProducer] = + forLoops.front().getNumResults() - 1; + } + if (Operation *tiledAndFusedOp = fusedResult->tiledAndFusedProducer.getDefiningOp()) { fusedProducers.insert(fusedResult->origProducer.getDefiningOp()); @@ -791,6 +814,12 @@ mlir::scf::tileConsumerAndFuseProducerGreedilyUsingSCFForOp( addCandidateSlices(tiledAndFusedOp, candidates); } } + + DenseMap replacements; + for (auto [origVal, resultNumber] : origValToResultNumber) { + replacements[origVal] = forLoops.front()->getResult(resultNumber); + } + return scf::SCFTileAndFuseResult{fusedProducers, tiledAndFusedOps, getAsOperations(forLoops), replacements}; } diff --git a/mlir/test/lib/Interfaces/TilingInterface/TestTilingInterface.cpp b/mlir/test/lib/Interfaces/TilingInterface/TestTilingInterface.cpp index 112ad6cbde85..798293bc1327 100644 --- a/mlir/test/lib/Interfaces/TilingInterface/TestTilingInterface.cpp +++ b/mlir/test/lib/Interfaces/TilingInterface/TestTilingInterface.cpp @@ -311,80 +311,50 @@ struct TestTileConsumerFuseAndYieldProducerUsingSCFForOp // Collect list of operations that can be tiled and fused. llvm::SmallDenseSet tiledAndFusedOps = collectTiledAndFusedOps(rootOp); - auto isIgnoredUser = [&](Operation *user, scf::ForOp outerMostTiledLoop) { - return tiledAndFusedOps.count(user) || isa(user) || - outerMostTiledLoop->isAncestor(user); + llvm::SmallDenseMap yielded; + auto isIgnoredUser = [&](Operation *user) { + return tiledAndFusedOps.count(user) || isa(user); }; - - // The rest of this method is similar to - // scf::tileConsumerAndFuseProducerGreedilyUsingSCFForOp, except that also - // yields replacements for values of the fused producer. - - // 1. Tile the consumer. - SmallVector yieldedValuesToOrigValues; - FailureOr tilingResult = - scf::tileUsingSCFForOp(rewriter, rootOp, options); - if (failed(tilingResult)) { - return rewriter.notifyMatchFailure(rootOp, - "failed to tile base operation"); + for (Operation *op : tiledAndFusedOps) { + yielded[op] = llvm::any_of(op->getUsers(), [&](Operation *user) { + return !isIgnoredUser(user); + }); } - yieldedValuesToOrigValues.append(rootOp->result_begin(), - rootOp->result_end()); - - // 2. Tiling each operation results in generation of slices. The source of - // these slices could be producers that can be fused into the tiled loops by - // computing the slices of these producers in-place. This results in more - // slices created for operands of the "fused producer". This open up more - // opportunities for fusion. Use a worklist to fuse greedily. - auto addCandidateSlices = - [](Operation *fusedOp, std::deque &candidates) { - for (Value operand : fusedOp->getOperands()) - if (auto sliceOp = operand.getDefiningOp()) - candidates.push_back(sliceOp); - }; - std::deque candidates; - addCandidateSlices(tilingResult->tiledOps.back(), candidates); - OpBuilder::InsertionGuard g(rewriter); - auto forLoops = llvm::to_vector(llvm::map_range( - tilingResult->loops, [](auto op) { return cast(op); })); - while (!candidates.empty()) { - // Traverse the slices in BFS fashion. - tensor::ExtractSliceOp candidateSliceOp = candidates.front(); - candidates.pop_front(); - - // Materialize the slice of the producer in place. - std::optional fusedProducer = - tileAndFuseProducerOfSlice(rewriter, candidateSliceOp, forLoops); - if (!fusedProducer) - continue; - - // Check if the fused producer has other uses that require the value - // to be yielded from within the tiled loop. - OpResult untiledProducer = fusedProducer->origProducer; - if (llvm::any_of(untiledProducer.getUsers(), [&](Operation *user) { - return !isIgnoredUser(user, forLoops.front()); - })) { - yieldReplacementForFusedProducer(rewriter, candidateSliceOp, - fusedProducer.value(), forLoops); - yieldedValuesToOrigValues.push_back(untiledProducer); - } + scf::SCFTileAndFuseOptions tileAndFuseOptions; + tileAndFuseOptions.setTilingOptions(options); + scf::SCFTileAndFuseOptions::ControlFnTy controlFn = + [&](tensor::ExtractSliceOp candidateSliceOp, OpResult originalProducer, + bool isDestinationOperand) { + Operation *owner = originalProducer.getOwner(); + return std::make_tuple(true, + yielded.contains(owner) && yielded[owner]); + }; + tileAndFuseOptions.setFusionControlFn(controlFn); - // Add more fusion candidates to the worklist. - if (auto fusedProducerOp = - fusedProducer->tiledAndFusedProducer.getDefiningOp()) - addCandidateSlices(fusedProducerOp, candidates); + FailureOr tileAndFuseResult = + scf::tileConsumerAndFuseProducerGreedilyUsingSCFForOp( + rewriter, rootOp, tileAndFuseOptions); + if (failed(tileAndFuseResult)) { + return rewriter.notifyMatchFailure( + rootOp, "failed to tile and fuse with op as root"); } - scf::ForOp outermostLoop = forLoops.front(); - for (auto [index, origVal] : llvm::enumerate(yieldedValuesToOrigValues)) { - Value replacement = outermostLoop.getResult(index); + for (auto it : tileAndFuseResult->replacements) { + Value origVal = it.first; + Value replacement = it.second; rewriter.replaceUsesWithIf(origVal, replacement, [&](OpOperand &use) { - return !isIgnoredUser(use.getOwner(), outermostLoop); + Operation *user = use.getOwner(); + return !isIgnoredUser(user) && + !tileAndFuseResult->loops.front()->isAncestor(user); }); } + rewriter.eraseOp(rootOp); - filter.replaceTransformationFilter(rewriter, tilingResult->tiledOps.back()); + for (auto tiledAndFusedOp : tileAndFuseResult->tiledAndFusedOps) + if (tiledAndFusedOp->hasAttr(kTransformMarker)) + filter.replaceTransformationFilter(rewriter, tiledAndFusedOp); + return success(); } -- GitLab From 7ab64b3266c580f946b3b65992030c3f68cbe392 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Jan 2024 13:25:38 -0800 Subject: [PATCH 112/652] [RISCV] Remove tab character from RISCVRegisterInfo.td. NFC --- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 840fd149d681..a59d058382fe 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -487,7 +487,7 @@ defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, defvar VM1VTs = [vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, vbfloat16m1_t, vfloat16m1_t, vfloat32m1_t, vfloat64m1_t, vint8mf2_t, vint8mf4_t, vint8mf8_t, - vint16mf2_t, vint16mf4_t, vint32mf2_t, + vint16mf2_t, vint16mf4_t, vint32mf2_t, vfloat16mf4_t, vfloat16mf2_t, vbfloat16mf4_t, vbfloat16mf2_t, vfloat32mf2_t]; -- GitLab From 09e32ab75076a1f2270d37343922c86c12bdd047 Mon Sep 17 00:00:00 2001 From: Alex Langford Date: Mon, 8 Jan 2024 13:30:24 -0800 Subject: [PATCH 113/652] [lldb] Deprecate SBBreakpoint::AddName in favor of AddNameWithErrorHandling (#71228) AddName gives no feedback other than if it succeeded whereas AddNameWithErrorHandling gives you back an SBError object. I would like to mark AddName as deprecated and direct folks to use AddNameWithErorrHandling instead. --------- Co-authored-by: Med Ismail Bennani --- lldb/include/lldb/API/SBBreakpoint.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lldb/include/lldb/API/SBBreakpoint.h b/lldb/include/lldb/API/SBBreakpoint.h index 0bb7c31d74f2..e08df3b6d5ab 100644 --- a/lldb/include/lldb/API/SBBreakpoint.h +++ b/lldb/include/lldb/API/SBBreakpoint.h @@ -112,6 +112,8 @@ public: SBError SetScriptCallbackBody(const char *script_body_text); + LLDB_DEPRECATED_FIXME("Doesn't provide error handling", + "AddNameWithErrorHandling") bool AddName(const char *new_name); SBError AddNameWithErrorHandling(const char *new_name); -- GitLab From 16b8a0dc6885dea0882887a6e642a504fd1e193c Mon Sep 17 00:00:00 2001 From: Alex Langford Date: Mon, 8 Jan 2024 13:31:03 -0800 Subject: [PATCH 114/652] [lldb] Change interface of StructuredData::Array::GetItemAtIndexAsInteger (#71993) This is a follow-up to (#71613) and (#71961). --- lldb/include/lldb/Utility/StructuredData.h | 28 +++++-------------- .../Breakpoint/BreakpointResolverName.cpp | 8 +++--- .../TSan/InstrumentationRuntimeTSan.cpp | 5 ++-- lldb/source/Target/DynamicRegisterInfo.cpp | 15 +++++----- 4 files changed, 21 insertions(+), 35 deletions(-) diff --git a/lldb/include/lldb/Utility/StructuredData.h b/lldb/include/lldb/Utility/StructuredData.h index e7ee12868512..5e63ef92fac3 100644 --- a/lldb/include/lldb/Utility/StructuredData.h +++ b/lldb/include/lldb/Utility/StructuredData.h @@ -221,31 +221,17 @@ public: } template - bool GetItemAtIndexAsInteger(size_t idx, IntType &result) const { - ObjectSP value_sp = GetItemAtIndex(idx); - if (value_sp.get()) { + std::optional GetItemAtIndexAsInteger(size_t idx) const { + if (auto item_sp = GetItemAtIndex(idx)) { if constexpr (std::numeric_limits::is_signed) { - if (auto signed_value = value_sp->GetAsSignedInteger()) { - result = static_cast(signed_value->GetValue()); - return true; - } + if (auto *signed_value = item_sp->GetAsSignedInteger()) + return static_cast(signed_value->GetValue()); } else { - if (auto unsigned_value = value_sp->GetAsUnsignedInteger()) { - result = static_cast(unsigned_value->GetValue()); - return true; - } + if (auto *unsigned_value = item_sp->GetAsUnsignedInteger()) + return static_cast(unsigned_value->GetValue()); } } - return false; - } - - template - bool GetItemAtIndexAsInteger(size_t idx, IntType &result, - IntType default_val) const { - bool success = GetItemAtIndexAsInteger(idx, result); - if (!success) - result = default_val; - return success; + return {}; } std::optional GetItemAtIndexAsString(size_t idx) const { diff --git a/lldb/source/Breakpoint/BreakpointResolverName.cpp b/lldb/source/Breakpoint/BreakpointResolverName.cpp index 82eef43ad6cf..aa86d2a26d11 100644 --- a/lldb/source/Breakpoint/BreakpointResolverName.cpp +++ b/lldb/source/Breakpoint/BreakpointResolverName.cpp @@ -161,14 +161,14 @@ BreakpointResolverSP BreakpointResolverName::CreateFromStructuredData( error.SetErrorString("BRN::CFSD: name entry is not a string."); return nullptr; } - std::underlying_type::type fnt; - success = names_mask_array->GetItemAtIndexAsInteger(i, fnt); - if (!success) { + auto maybe_fnt = names_mask_array->GetItemAtIndexAsInteger< + std::underlying_type::type>(i); + if (!maybe_fnt) { error.SetErrorString("BRN::CFSD: name mask entry is not an integer."); return nullptr; } names.push_back(std::string(*maybe_name)); - name_masks.push_back(static_cast(fnt)); + name_masks.push_back(static_cast(*maybe_fnt)); } std::shared_ptr resolver_sp = diff --git a/lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp b/lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp index 2a35256a6fb0..72293c5331f4 100644 --- a/lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp +++ b/lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp @@ -592,9 +592,10 @@ addr_t InstrumentationRuntimeTSan::GetFirstNonInternalFramePc( if (skip_one_frame && i == 0) continue; - addr_t addr; - if (!trace_array->GetItemAtIndexAsInteger(i, addr)) + auto maybe_addr = trace_array->GetItemAtIndexAsInteger(i); + if (!maybe_addr) continue; + addr_t addr = *maybe_addr; lldb_private::Address so_addr; if (!process_sp->GetTarget().GetSectionLoadList().ResolveLoadAddress( diff --git a/lldb/source/Target/DynamicRegisterInfo.cpp b/lldb/source/Target/DynamicRegisterInfo.cpp index 7469c1d4259a..1a817449fa95 100644 --- a/lldb/source/Target/DynamicRegisterInfo.cpp +++ b/lldb/source/Target/DynamicRegisterInfo.cpp @@ -349,10 +349,8 @@ DynamicRegisterInfo::SetRegisterInfo(const StructuredData::Dictionary &dict, const size_t num_regs = invalidate_reg_list->GetSize(); if (num_regs > 0) { for (uint32_t idx = 0; idx < num_regs; ++idx) { - uint64_t invalidate_reg_num; - std::optional maybe_invalidate_reg_name = - invalidate_reg_list->GetItemAtIndexAsString(idx); - if (maybe_invalidate_reg_name) { + if (auto maybe_invalidate_reg_name = + invalidate_reg_list->GetItemAtIndexAsString(idx)) { const RegisterInfo *invalidate_reg_info = GetRegisterInfo(*maybe_invalidate_reg_name); if (invalidate_reg_info) { @@ -365,10 +363,11 @@ DynamicRegisterInfo::SetRegisterInfo(const StructuredData::Dictionary &dict, "\"%s\" while parsing register \"%s\"\n", maybe_invalidate_reg_name->str().c_str(), reg_info.name); } - } else if (invalidate_reg_list->GetItemAtIndexAsInteger( - idx, invalidate_reg_num)) { - if (invalidate_reg_num != UINT64_MAX) - m_invalidate_regs_map[i].push_back(invalidate_reg_num); + } else if (auto maybe_invalidate_reg_num = + invalidate_reg_list->GetItemAtIndexAsInteger( + idx)) { + if (*maybe_invalidate_reg_num != UINT64_MAX) + m_invalidate_regs_map[i].push_back(*maybe_invalidate_reg_num); else printf("error: 'invalidate-regs' list value wasn't a valid " "integer\n"); -- GitLab From f700d748f0447b6a761eb9d42575b28e0af98708 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 13:57:10 -0800 Subject: [PATCH 115/652] [libc] fix more -Wmissing-brace (#77382) Similar to #77345, the buildbots are observing similar warnings for the sse2 implementation. llvm-project/libc/src/__support/HashTable/sse2/bitmask_impl.inc:36:13: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] return {bitmask}; ^~~~~~~ { } llvm-project/libc/src/__support/HashTable/sse2/bitmask_impl.inc:45:13: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] return {static_cast(~mask_available().word)}; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { } Link: https://lab.llvm.org/buildbot/#/builders/163/builds/49350/steps/8/logs/stdio Link: https://github.com/llvm/llvm-project/pull/74506 --- libc/src/__support/HashTable/sse2/bitmask_impl.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/src/__support/HashTable/sse2/bitmask_impl.inc b/libc/src/__support/HashTable/sse2/bitmask_impl.inc index d65240901ed4..e778c19f284a 100644 --- a/libc/src/__support/HashTable/sse2/bitmask_impl.inc +++ b/libc/src/__support/HashTable/sse2/bitmask_impl.inc @@ -33,7 +33,7 @@ struct Group { LIBC_INLINE IteratableBitMask match_byte(uint8_t byte) const { auto cmp = _mm_cmpeq_epi8(data, _mm_set1_epi8(byte)); auto bitmask = static_cast(_mm_movemask_epi8(cmp)); - return {bitmask}; + return {{bitmask}}; } LIBC_INLINE BitMask mask_available() const { @@ -42,7 +42,7 @@ struct Group { } LIBC_INLINE IteratableBitMask occupied() const { - return {static_cast(~mask_available().word)}; + return {{static_cast(~mask_available().word)}}; } }; } // namespace internal -- GitLab From f84bfa2f92d2aa3329bc06902a12c0f4c54d7297 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Tue, 9 Jan 2024 00:01:21 +0200 Subject: [PATCH 116/652] [LLD] [MinGW] Sync --thinlto-cache-dir option details with ELF (#77010) Disallow using the form with a separate argument, "--thinlto-cache-dir dir", allow only the one with equals, "--thintlo-cache-dir=dir". This is the only form that actually was tested when this was added in f794808bb9ec06966a67fe33d41a13b9601768f8, and matches the ELF side, where only the form with an equals is supported (and this was also the case at the time when this option was added to the MinGW linker). --- lld/MinGW/Options.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lld/MinGW/Options.td b/lld/MinGW/Options.td index d4a49cdbd535..d8471d5a7bc9 100644 --- a/lld/MinGW/Options.td +++ b/lld/MinGW/Options.td @@ -186,8 +186,8 @@ def appcontainer: F<"appcontainer">, HelpText<"Set the appcontainer flag in the defm delayload: Eq<"delayload", "DLL to load only on demand">; defm mllvm: EqNoHelp<"mllvm">; defm pdb: Eq<"pdb", "Output PDB debug info file, chosen implicitly if the argument is empty">; -defm thinlto_cache_dir: EqLong<"thinlto-cache-dir", - "Path to ThinLTO cached object file directory">; +def thinlto_cache_dir: JJ<"thinlto-cache-dir=">, + HelpText<"Path to ThinLTO cached object file directory">; defm Xlink : Eq<"Xlink", "Pass to the COFF linker">, MetaVarName<"">; defm guard_cf : B<"guard-cf", "Enable Control Flow Guard" , "Do not enable Control Flow Guard (default)">; -- GitLab From b2ea9ec7fcf37ca01979c11c5b2b1cab0e1ae212 Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Tue, 9 Jan 2024 05:03:16 +0700 Subject: [PATCH 117/652] [CommandLine] Do not print empty categories with '--help-hidden' (#77043) If a category has no options associated with it, the `--help-hidden` command still shows that category with the annotation "This option category has no options", and this is how it was implemented from the beginning when the categories were introduced, see commit 0537a98878. A feature to hide unrelated options was added later, in https://reviews.llvm.org/D7100. Now, if a tool needs to hide unrelated options that are associated with categories, leaving some of them empty, those categories will still be visible on the `--help-hidden` output, even if they have no use for the tool; see the changes in `llvm/test/tools/llvm-debuginfo-analyzer/cmdline.test` for an example. The patch ensures that only categories with options are shown on both main and hidden help output. --- llvm/docs/CommandLine.rst | 3 +-- llvm/lib/Support/CommandLine.cpp | 9 +------ .../llvm-debuginfo-analyzer/cmdline.test | 4 --- llvm/unittests/Support/CommandLineTest.cpp | 25 +++++++++++++++++++ 4 files changed, 27 insertions(+), 14 deletions(-) diff --git a/llvm/docs/CommandLine.rst b/llvm/docs/CommandLine.rst index 3784db29ed87..00d098745f55 100644 --- a/llvm/docs/CommandLine.rst +++ b/llvm/docs/CommandLine.rst @@ -1521,8 +1521,7 @@ passed to the constructor as ``const char*``. Note that declaring an option category and associating it with an option before parsing options (e.g. statically) will change the output of ``-help`` from uncategorized to categorized. If an option category is declared but not -associated with an option then it will be hidden from the output of ``-help`` -but will be shown in the output of ``-help-hidden``. +associated with an option then it will be hidden from the output of ``-help``. .. _different parser: .. _discussed previously: diff --git a/llvm/lib/Support/CommandLine.cpp b/llvm/lib/Support/CommandLine.cpp index 368dead44914..7360d733d96e 100644 --- a/llvm/lib/Support/CommandLine.cpp +++ b/llvm/lib/Support/CommandLine.cpp @@ -2474,8 +2474,7 @@ protected: for (OptionCategory *Category : SortedCategories) { // Hide empty categories for --help, but show for --help-hidden. const auto &CategoryOptions = CategorizedOptions[Category]; - bool IsEmptyCategory = CategoryOptions.empty(); - if (!ShowHidden && IsEmptyCategory) + if (CategoryOptions.empty()) continue; // Print category information. @@ -2488,12 +2487,6 @@ protected: else outs() << "\n"; - // When using --help-hidden explicitly state if the category has no - // options associated with it. - if (IsEmptyCategory) { - outs() << " This option category has no options.\n"; - continue; - } // Loop over the options in the category and print. for (const Option *Opt : CategoryOptions) Opt->printOptionInfo(MaxArgLen); diff --git a/llvm/test/tools/llvm-debuginfo-analyzer/cmdline.test b/llvm/test/tools/llvm-debuginfo-analyzer/cmdline.test index c9c2dbe9fa3e..15daec0ba593 100644 --- a/llvm/test/tools/llvm-debuginfo-analyzer/cmdline.test +++ b/llvm/test/tools/llvm-debuginfo-analyzer/cmdline.test @@ -70,8 +70,6 @@ HELP-ALL: =system - Display PDB's MS system elements. HELP-ALL: =typename - Include Parameters in templates. HELP-ALL: =underlying - Underlying type for type definitions. HELP-ALL: =zero - Zero line numbers. -HELP-ALL: Color Options: -HELP-ALL: This option category has no options. HELP-ALL: Compare Options: HELP-ALL: These control the view comparison. HELP-ALL: --compare= - Elements to compare. @@ -81,8 +79,6 @@ HELP-ALL: =scopes - Scopes. HELP-ALL: =symbols - Symbols. HELP-ALL: =types - Types. HELP-ALL: --compare-context - Add the view as compare context. -HELP-ALL: General options: -HELP-ALL: This option category has no options. HELP-ALL: Generic Options: HELP-ALL: -h - Alias for --help HELP-ALL: --help - Display available options (--help-hidden for more) diff --git a/llvm/unittests/Support/CommandLineTest.cpp b/llvm/unittests/Support/CommandLineTest.cpp index a9d0790c8fea..99d99c74c128 100644 --- a/llvm/unittests/Support/CommandLineTest.cpp +++ b/llvm/unittests/Support/CommandLineTest.cpp @@ -2301,4 +2301,29 @@ TEST(CommandLineTest, SubCommandGroups) { EXPECT_FALSE(SC3.OptionsMap.contains("opt12")); } +TEST(CommandLineTest, HelpWithEmptyCategory) { + cl::ResetCommandLineParser(); + + cl::OptionCategory Category1("First Category"); + cl::OptionCategory Category2("Second Category"); + StackOption Opt1("opt1", cl::cat(Category1)); + StackOption Opt2("opt2", cl::cat(Category2)); + cl::HideUnrelatedOptions(Category2); + + const char *args[] = {"prog"}; + EXPECT_TRUE(cl::ParseCommandLineOptions(std::size(args), args, StringRef(), + &llvm::nulls())); + auto Output = interceptStdout( + []() { cl::PrintHelpMessage(/*Hidden=*/false, /*Categorized=*/true); }); + EXPECT_EQ(std::string::npos, Output.find("First Category")) + << "An empty category should not be printed"; + + Output = interceptStdout( + []() { cl::PrintHelpMessage(/*Hidden=*/true, /*Categorized=*/true); }); + EXPECT_EQ(std::string::npos, Output.find("First Category")) + << "An empty category should not be printed"; + + cl::ResetCommandLineParser(); +} + } // anonymous namespace -- GitLab From d5f84e6121f0d0cc8984dccc1774ce9ddb7168c4 Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Mon, 8 Jan 2024 22:11:14 +0000 Subject: [PATCH 118/652] [libc++abi] Handle catch null pointer-to-object (#68076) This addresses cases (currently failing) where we throw a null pointer-to-object and fixes #64953. We are trying to satisfy the following bullet from the C++ ABI 15.3: * the handler is of type cv1 T* cv2 and E is a pointer type that can be converted to the type of the handler by either or both of: - a standard pointer conversion (4.10 [conv.ptr]) not involving conversions to private or protected or ambiguous classes. - a qualification conversion. The existing implementation assesses the ambiguity of bases by computing the offsets to them; ambiguous cases are then when the same base appears at different offsets. The computation of offset includes indirecting through the vtables to find the offsets to virtual bases. When the thrown pointer points to a real object, this is quite efficient since, if the base is found, and it is not ambiguous and on a public path, the offset is needed to return the adjusted pointer (and the indirections are not particularly expensive to compute). However, when we throw a null pointer-to-object, this scheme is no longer applicable (and the code currently bypasses the relevant computations, leading to the incorrect catches reported in the issue). ----- The solution proposed here takes a composite approach: 1. When the pointer-to-object points to a real instance (well, at least, it is determined to be non-null), we use the existing scheme. 2. When the pointer-to-object is null: * We note that there is no real object. * When we are processing non-virtual bases, we continue to compute the offsets, but for a notional dummy object based at 0. This is OK, since we never need to access the object content for non-virtual bases. * When we are processing a path with one or more virtual bases, we remember a cookie corresponding to the inner-most virtual base found so far (and set the notional offset to 0). Offsets to inner non-virtual bases are then computed as normal. A base is then ambiguous iff: * There is a recorded virtual base cookie and that is different from the current one or, * The non-virtual base offsets differ. When a handler for a pointer succeeds in catching a base pointer for a thrown null pointer-to-object, we still return a nullptr (so the adjustment to the pointer is not required and need not be computed). Since we noted that there was no object when starting the search for ambiguous bases, we know that we can skip the pointer adjustment. This was originally uploaded as https://reviews.llvm.org/D158769. Fixes #64953 --- libcxxabi/src/private_typeinfo.cpp | 174 +++++++++------- libcxxabi/src/private_typeinfo.h | 7 + ...ch_null_pointer_to_object_pr64953.pass.cpp | 194 ++++++++++++++++++ 3 files changed, 301 insertions(+), 74 deletions(-) create mode 100644 libcxxabi/test/catch_null_pointer_to_object_pr64953.pass.cpp diff --git a/libcxxabi/src/private_typeinfo.cpp b/libcxxabi/src/private_typeinfo.cpp index 82db4bbec1ad..857ae25b7028 100644 --- a/libcxxabi/src/private_typeinfo.cpp +++ b/libcxxabi/src/private_typeinfo.cpp @@ -42,6 +42,7 @@ // is_equal() with use_strcmp=false so the string names are not compared. #include +#include #include #ifdef _LIBCXXABI_FORGIVING_DYNAMIC_CAST @@ -160,15 +161,9 @@ const void* dyn_cast_to_derived(const void* static_ptr, // Fallback to the slow path to check that static_type is a public // base type of dynamic_type. // Using giant short cut. Add that information to info. - __dynamic_cast_info info = { - dst_type, - static_ptr, - static_type, - src2dst_offset, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, // number_of_dst_type - false, false, false - }; + __dynamic_cast_info info = {dst_type, static_ptr, static_type, src2dst_offset, 0, 0, 0, 0, 0, 0, 0, 0, + 1, // number_of_dst_type + false, false, false, true, nullptr}; // Do the search dst_type->search_above_dst(&info, dynamic_ptr, dynamic_ptr, public_path, false); #ifdef _LIBCXXABI_FORGIVING_DYNAMIC_CAST @@ -187,13 +182,8 @@ const void* dyn_cast_to_derived(const void* static_ptr, "should have public visibility. At least one of them is hidden. %s" ", %s.\n", static_type->name(), dst_type->name()); // Redo the search comparing type_info's using strcmp - info = { - dst_type, - static_ptr, - static_type, - src2dst_offset, - 0, 0, 0, 0, 0, 0, 0, 0, 0, false, false, false - }; + info = {dst_type, static_ptr, static_type, src2dst_offset, 0, 0, 0, 0, 0, 0, + 0, 0, 0, false, false, false, true, nullptr}; info.number_of_dst_type = 1; dst_type->search_above_dst(&info, dynamic_ptr, dynamic_ptr, public_path, true); } @@ -232,15 +222,24 @@ const void* dyn_cast_try_downcast(const void* static_ptr, } // Try to search a path from dynamic_type to dst_type. - __dynamic_cast_info dynamic_to_dst_info = { - dynamic_type, - dst_ptr_to_static, - dst_type, - src2dst_offset, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, // number_of_dst_type - false, false, false - }; + __dynamic_cast_info dynamic_to_dst_info = {dynamic_type, + dst_ptr_to_static, + dst_type, + src2dst_offset, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, // number_of_dst_type + false, + false, + false, + true, + nullptr}; dynamic_type->search_above_dst(&dynamic_to_dst_info, dynamic_ptr, dynamic_ptr, public_path, false); if (dynamic_to_dst_info.path_dst_ptr_to_static_ptr != unknown) { // We have found at least one path from dynamic_ptr to dst_ptr. The @@ -261,13 +260,8 @@ const void* dyn_cast_slow(const void* static_ptr, // Not using giant short cut. Do the search // Initialize info struct for this search. - __dynamic_cast_info info = { - dst_type, - static_ptr, - static_type, - src2dst_offset, - 0, 0, 0, 0, 0, 0, 0, 0, 0, false, false, false - }; + __dynamic_cast_info info = {dst_type, static_ptr, static_type, src2dst_offset, 0, 0, 0, 0, 0, 0, + 0, 0, 0, false, false, false, true, nullptr}; dynamic_type->search_below_dst(&info, dynamic_ptr, public_path, false); #ifdef _LIBCXXABI_FORGIVING_DYNAMIC_CAST @@ -287,13 +281,8 @@ const void* dyn_cast_slow(const void* static_ptr, "%s, %s, %s.\n", static_type->name(), dynamic_type->name(), dst_type->name()); // Redo the search comparing type_info's using strcmp - info = { - dst_type, - static_ptr, - static_type, - src2dst_offset, - 0, 0, 0, 0, 0, 0, 0, 0, 0, false, false, false - }; + info = {dst_type, static_ptr, static_type, src2dst_offset, 0, 0, 0, 0, 0, 0, + 0, 0, 0, false, false, false, true, nullptr}; dynamic_type->search_below_dst(&info, dynamic_ptr, public_path, true); } #endif // _LIBCXXABI_FORGIVING_DYNAMIC_CAST @@ -481,7 +470,8 @@ __class_type_info::can_catch(const __shim_type_info* thrown_type, if (thrown_class_type == 0) return false; // bullet 2 - __dynamic_cast_info info = {thrown_class_type, 0, this, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}; + assert(adjustedPtr && "catching a class without an object?"); + __dynamic_cast_info info = {thrown_class_type, 0, this, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, true, nullptr}; info.number_of_dst_type = 1; thrown_class_type->has_unambiguous_public_base(&info, adjustedPtr, public_path); if (info.path_dst_ptr_to_static_ptr == public_path) @@ -496,32 +486,46 @@ __class_type_info::can_catch(const __shim_type_info* thrown_type, #pragma clang diagnostic pop #endif +// When we have an object to inspect - we just pass the pointer to the sub- +// object that matched the static_type we just checked. If that is different +// from any previously recorded pointer to that object type, then we have +// an ambiguous case. + +// When we have no object to inspect, we need to account for virtual bases +// explicitly. +// info->vbase_cookie is a pointer to the name of the innermost virtual base +// type, or nullptr if there is no virtual base on the path so far. +// adjustedPtr points to the subobject we just found. +// If vbase_cookie != any previously recorded (including the case of nullptr +// representing an already-found static sub-object) then we have an ambiguous +// case. Assuming that the vbase_cookie values agree; if then we have a +// different offset (adjustedPtr) from any previously recorded, this indicates +// an ambiguous case within the virtual base. + void __class_type_info::process_found_base_class(__dynamic_cast_info* info, void* adjustedPtr, int path_below) const { - if (info->dst_ptr_leading_to_static_ptr == 0) - { - // First time here - info->dst_ptr_leading_to_static_ptr = adjustedPtr; - info->path_dst_ptr_to_static_ptr = path_below; - info->number_to_static_ptr = 1; - } - else if (info->dst_ptr_leading_to_static_ptr == adjustedPtr) - { - // We've been here before. Update path to "most public" - if (info->path_dst_ptr_to_static_ptr == not_public_path) - info->path_dst_ptr_to_static_ptr = path_below; - } - else - { - // We've detected an ambiguous cast from (thrown_class_type, adjustedPtr) - // to a static_type - info->number_to_static_ptr += 1; - info->path_dst_ptr_to_static_ptr = not_public_path; - info->search_done = true; - } + if (info->number_to_static_ptr == 0) { + // First time we found this base + info->dst_ptr_leading_to_static_ptr = adjustedPtr; + info->path_dst_ptr_to_static_ptr = path_below; + // stash the virtual base cookie. + info->dst_ptr_not_leading_to_static_ptr = info->vbase_cookie; + info->number_to_static_ptr = 1; + } else if (info->dst_ptr_not_leading_to_static_ptr == info->vbase_cookie && + info->dst_ptr_leading_to_static_ptr == adjustedPtr) { + // We've been here before. Update path to "most public" + if (info->path_dst_ptr_to_static_ptr == not_public_path) + info->path_dst_ptr_to_static_ptr = path_below; + } else { + // We've detected an ambiguous cast from (thrown_class_type, adjustedPtr) + // to a static_type. + info->number_to_static_ptr += 1; + info->path_dst_ptr_to_static_ptr = not_public_path; + info->search_done = true; + } } void @@ -549,16 +553,30 @@ __base_class_type_info::has_unambiguous_public_base(__dynamic_cast_info* info, void* adjustedPtr, int path_below) const { - ptrdiff_t offset_to_base = 0; - if (adjustedPtr != nullptr) - { - offset_to_base = __offset_flags >> __offset_shift; - if (__offset_flags & __virtual_mask) - { - const char* vtable = *static_cast(adjustedPtr); - offset_to_base = update_offset_to_base(vtable, offset_to_base); - } + bool is_virtual = __offset_flags & __virtual_mask; + ptrdiff_t offset_to_base = 0; + if (info->have_object) { + /* We have an object to inspect, we can look through its vtables to + find the layout. */ + offset_to_base = __offset_flags >> __offset_shift; + if (is_virtual) { + const char* vtable = *static_cast(adjustedPtr); + offset_to_base = update_offset_to_base(vtable, offset_to_base); } + } else if (!is_virtual) { + /* We have no object; however, for non-virtual bases, (since we do not + need to inspect any content) we can pretend to have an object based + at '0'. */ + offset_to_base = __offset_flags >> __offset_shift; + } else { + /* No object to inspect, and the next base is virtual. + We cannot indirect through the vtable to find the actual object offset. + So, update vbase_cookie to the new innermost virtual base using the + pointer to the typeinfo name as a key. */ + info->vbase_cookie = static_cast(__base_type->name()); + // .. and reset the pointer. + adjustedPtr = nullptr; + } __base_type->has_unambiguous_public_base( info, static_cast(adjustedPtr) + offset_to_base, @@ -679,14 +697,22 @@ __pointer_type_info::can_catch(const __shim_type_info* thrown_type, dynamic_cast(thrown_pointer_type->__pointee); if (thrown_class_type == 0) return false; - __dynamic_cast_info info = {thrown_class_type, 0, catch_class_type, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}; + bool have_object = adjustedPtr != nullptr; + __dynamic_cast_info info = {thrown_class_type, 0, catch_class_type, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + have_object, nullptr}; info.number_of_dst_type = 1; thrown_class_type->has_unambiguous_public_base(&info, adjustedPtr, public_path); if (info.path_dst_ptr_to_static_ptr == public_path) { - if (adjustedPtr != NULL) - adjustedPtr = const_cast(info.dst_ptr_leading_to_static_ptr); - return true; + // In the case of a thrown null pointer, we have no object but we might + // well have computed the offset to where a public sub-object would be. + // However, we do not want to return that offset to the user; we still + // want them to catch a null ptr. + if (have_object) + adjustedPtr = const_cast(info.dst_ptr_leading_to_static_ptr); + else + adjustedPtr = nullptr; + return true; } return false; } diff --git a/libcxxabi/src/private_typeinfo.h b/libcxxabi/src/private_typeinfo.h index 622e09cc2421..328a02edef5c 100644 --- a/libcxxabi/src/private_typeinfo.h +++ b/libcxxabi/src/private_typeinfo.h @@ -110,6 +110,13 @@ struct _LIBCXXABI_HIDDEN __dynamic_cast_info bool found_any_static_type; // Set whenever a search can be stopped bool search_done; + + // Data that modifies the search mechanism. + + // There is no object (seen when we throw a null pointer to object). + bool have_object; + // Virtual base + const void* vbase_cookie; }; // Has no base class diff --git a/libcxxabi/test/catch_null_pointer_to_object_pr64953.pass.cpp b/libcxxabi/test/catch_null_pointer_to_object_pr64953.pass.cpp new file mode 100644 index 000000000000..82ce0c580309 --- /dev/null +++ b/libcxxabi/test/catch_null_pointer_to_object_pr64953.pass.cpp @@ -0,0 +1,194 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This test case checks specifically the cases under bullet 3.3: +// +// C++ ABI 15.3: +// A handler is a match for an exception object of type E if +// * The handler is of type cv T or cv T& and E and T are the same type +// (ignoring the top-level cv-qualifiers), or +// * the handler is of type cv T or cv T& and T is an unambiguous base +// class of E, or +// > * the handler is of type cv1 T* cv2 and E is a pointer type that can < +// > be converted to the type of the handler by either or both of < +// > o a standard pointer conversion (4.10 [conv.ptr]) not involving < +// > conversions to private or protected or ambiguous classes < +// > o a qualification conversion < +// * the handler is a pointer or pointer to member type and E is +// std::nullptr_t +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: no-exceptions +// This test requires the fix to +// https://github.com/llvm/llvm-project/issues/64953, which is in libc++abi.dylib. +// The fix is not contained in older macOS system dylibs, so the test will fail +// there. +// FIXME: In the case that we are testing `natively` with the CI scripts we +// currently pass the newly-built libraries to the execution, this leads to an +// XPASS here so that we have to make these UNSUPPORTED for now (they should be +// XFAILs when tested against current [macOS14] and previous installed libc++abi +// as described above). +// UNSUPPORTED: stdlib=apple-libc++ && target={{.+}}-apple-macosx10.{{9|10|11|12|13|14|15}}{{.*}} +// UNSUPPORTED: stdlib=apple-libc++ && target={{.+}}-apple-macosx{{11|12|13|14}}{{.*}} + +#include +#include +#include +#include + +struct Base { + int b; +}; +struct Base2 { + int b; +}; +struct Derived1 : Base { + int b; +}; +struct Derived2 : Base { + int b; +}; +struct Derived3 : Base2 { + int b; +}; +struct Private : private Base { + int b; +}; +struct Protected : protected Base { + int b; +}; +struct Virtual1 : virtual Base { + int b; +}; +struct Virtual2 : virtual Base { + int b; +}; + +struct Ambiguous1 : Derived1, Derived2 { + int b; +}; +struct Ambiguous2 : Derived1, Private { + int b; +}; +struct Ambiguous3 : Derived1, Protected { + int b; +}; + +struct NoPublic1 : Private, Base2 { + int b; +}; +struct NoPublic2 : Protected, Base2 { + int b; +}; + +struct Catchable1 : Derived3, Derived1 { + int b; +}; +struct Catchable2 : Virtual1, Virtual2 { + int b; +}; +struct Catchable3 : virtual Base, Virtual2 { + int b; +}; + +// Check that, when we have a null pointer-to-object that we catch a nullptr. +template +void assert_catches() { + try { + throw static_cast(0); + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "Statements after throw must be unreachable"); + } catch (T t) { + assert(t == nullptr); + return; + } catch (...) { + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "Should not have entered catch-all"); + } + + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "The catch should have returned"); +} + +template +void assert_cannot_catch() { + try { + throw static_cast(0); + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "Statements after throw must be unreachable"); + } catch (T t) { + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "Should not have entered the catch"); + } catch (...) { + assert(true); + return; + } + + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "The catch-all should have returned"); +} + +// Check that when we have a pointer-to-actual-object we, in fact, get the +// adjusted pointer to the base class. +template +void assert_catches_bp() { + O* o = new (O); + try { + throw o; + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "Statements after throw must be unreachable"); + } catch (T t) { + assert(t == static_cast(o)); + //__builtin_printf("o = %p t = %p\n", o, t); + delete o; + return; + } catch (...) { + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "Should not have entered catch-all"); + } + + printf("%s\n", __PRETTY_FUNCTION__); + assert(false && "The catch should have returned"); +} + +void f1() { + assert_catches(); + assert_catches(); + assert_catches(); +} + +void f2() { + assert_cannot_catch(); + assert_cannot_catch(); + assert_cannot_catch(); + assert_cannot_catch(); + assert_cannot_catch(); +} + +void f3() { + assert_catches_bp(); + assert_catches_bp(); + assert_catches_bp(); +} + +int main(int, char**) { + f1(); + f2(); + f3(); + return 0; +} -- GitLab From 0fe86f9c518fb1296bba8d66ce495f9dfff2c435 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 8 Jan 2024 16:49:33 -0600 Subject: [PATCH 119/652] [Libomptarget] Remove extra cache for offloading entries (#77012) Summary: The offloading entries right now are assumed to be baked into the binary itself, and thus always valid whenever the library is executing. This means that we don't need to copy them to additional storage and can instead simply pass around references to it. This is not likely to change in the expected operation of the OpenMP library. Additionally, the indirection for the offload entry struct is simply two pointers, so moving it by value is trivial. --- openmp/libomptarget/include/DeviceImage.h | 5 +++-- openmp/libomptarget/include/OffloadEntry.h | 8 ++++---- openmp/libomptarget/include/device.h | 4 ++-- openmp/libomptarget/src/DeviceImage.cpp | 4 ---- openmp/libomptarget/src/PluginManager.cpp | 4 ++-- openmp/libomptarget/src/device.cpp | 15 +++++++-------- 6 files changed, 18 insertions(+), 22 deletions(-) diff --git a/openmp/libomptarget/include/DeviceImage.h b/openmp/libomptarget/include/DeviceImage.h index 63b4b6d14e0e..ba46a837f402 100644 --- a/openmp/libomptarget/include/DeviceImage.h +++ b/openmp/libomptarget/include/DeviceImage.h @@ -26,7 +26,6 @@ class DeviceImageTy { std::unique_ptr Binary; - llvm::SmallVector> OffloadEntries; __tgt_bin_desc *BinaryDesc; __tgt_device_image Image; @@ -37,7 +36,9 @@ public: __tgt_device_image &getExecutableImage() { return Image; } __tgt_bin_desc &getBinaryDesc() { return *BinaryDesc; } - auto entries() { return llvm::make_pointee_range(OffloadEntries); } + auto entries() { + return llvm::make_range(Image.EntriesBegin, Image.EntriesEnd); + } }; #endif // OMPTARGET_DEVICE_IMAGE_H diff --git a/openmp/libomptarget/include/OffloadEntry.h b/openmp/libomptarget/include/OffloadEntry.h index f645fe81db2d..5173841f20a4 100644 --- a/openmp/libomptarget/include/OffloadEntry.h +++ b/openmp/libomptarget/include/OffloadEntry.h @@ -36,11 +36,11 @@ public: const char *getNameAsCStr() const { return OffloadEntry.name; } __tgt_bin_desc *getBinaryDescription() const; - bool isCTor() { return hasFlags(OMP_DECLARE_TARGET_CTOR); } - bool isDTor() { return hasFlags(OMP_DECLARE_TARGET_DTOR); } - bool isLink() { return hasFlags(OMP_DECLARE_TARGET_LINK); } + bool isCTor() const { return hasFlags(OMP_DECLARE_TARGET_CTOR); } + bool isDTor() const { return hasFlags(OMP_DECLARE_TARGET_DTOR); } + bool isLink() const { return hasFlags(OMP_DECLARE_TARGET_LINK); } - bool hasFlags(OpenMPOffloadingDeclareTargetFlags Flags) { + bool hasFlags(OpenMPOffloadingDeclareTargetFlags Flags) const { return Flags & OffloadEntry.flags; } }; diff --git a/openmp/libomptarget/include/device.h b/openmp/libomptarget/include/device.h index d28d3c508faf..e94f48891dab 100644 --- a/openmp/libomptarget/include/device.h +++ b/openmp/libomptarget/include/device.h @@ -159,7 +159,7 @@ struct DeviceTy { /// } /// Register \p Entry as an offload entry that is avalable on this device. - void addOffloadEntry(OffloadEntryTy &Entry); + void addOffloadEntry(const OffloadEntryTy &Entry); /// Print all offload entries to stderr. void dumpOffloadEntries(); @@ -170,7 +170,7 @@ private: /// All offload entries available on this device. using DeviceOffloadEntriesMapTy = - llvm::DenseMap; + llvm::DenseMap; ProtectedObj DeviceOffloadEntries; /// Handler to collect and organize host-2-device mapping information. diff --git a/openmp/libomptarget/src/DeviceImage.cpp b/openmp/libomptarget/src/DeviceImage.cpp index 1d39bb9ab8da..e42460b5cca4 100644 --- a/openmp/libomptarget/src/DeviceImage.cpp +++ b/openmp/libomptarget/src/DeviceImage.cpp @@ -27,10 +27,6 @@ DeviceImageTy::DeviceImageTy(__tgt_bin_desc &BinaryDesc, __tgt_device_image &TgtDeviceImage) : BinaryDesc(&BinaryDesc), Image(TgtDeviceImage) { - for (__tgt_offload_entry &Entry : - llvm::make_range(Image.EntriesBegin, Image.EntriesEnd)) - OffloadEntries.emplace_back(std::make_unique(*this, Entry)); - llvm::StringRef ImageStr( static_cast(Image.ImageStart), llvm::omp::target::getPtrDiff(Image.ImageEnd, Image.ImageStart)); diff --git a/openmp/libomptarget/src/PluginManager.cpp b/openmp/libomptarget/src/PluginManager.cpp index da2e08180eea..83bf65f0f0de 100644 --- a/openmp/libomptarget/src/PluginManager.cpp +++ b/openmp/libomptarget/src/PluginManager.cpp @@ -97,8 +97,8 @@ void PluginAdaptorTy::addOffloadEntries(DeviceImageTy &DI) { toString(DeviceOrErr.takeError()).c_str()); DeviceTy &Device = *DeviceOrErr; - for (OffloadEntryTy &Entry : DI.entries()) - Device.addOffloadEntry(Entry); + for (__tgt_offload_entry &Entry : DI.entries()) + Device.addOffloadEntry(OffloadEntryTy(DI, Entry)); } } diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index dbad13b92bcc..fa8932361a51 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -291,10 +291,9 @@ int32_t DeviceTy::destroyEvent(void *Event) { return OFFLOAD_SUCCESS; } -void DeviceTy::addOffloadEntry(OffloadEntryTy &Entry) { +void DeviceTy::addOffloadEntry(const OffloadEntryTy &Entry) { std::lock_guard Lock(PendingGlobalsMtx); - DeviceOffloadEntries.getExclusiveAccessor()->insert( - {Entry.getName(), &Entry}); + DeviceOffloadEntries.getExclusiveAccessor()->insert({Entry.getName(), Entry}); if (Entry.isGlobal()) return; @@ -329,14 +328,14 @@ void DeviceTy::dumpOffloadEntries() { fprintf(stderr, "Device %i offload entries:\n", DeviceID); for (auto &It : *DeviceOffloadEntries.getExclusiveAccessor()) { const char *Kind = "kernel"; - if (It.second->isCTor()) + if (It.second.isCTor()) Kind = "constructor"; - else if (It.second->isDTor()) + else if (It.second.isDTor()) Kind = "destructor"; - else if (It.second->isLink()) + else if (It.second.isLink()) Kind = "link"; - else if (It.second->isGlobal()) + else if (It.second.isGlobal()) Kind = "global var."; - fprintf(stderr, " %11s: %s\n", Kind, It.second->getNameAsCStr()); + fprintf(stderr, " %11s: %s\n", Kind, It.second.getNameAsCStr()); } } -- GitLab From 6e90f13cc9bc9dbc5c2c248d95c6e18a5fb021b4 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Mon, 8 Jan 2024 17:57:52 -0500 Subject: [PATCH 120/652] [mlir][spirv] Drop support for SPV_NV_cooperative_matrix (#76782) This extension has been superseded by SPV_KHR_cooperative_matrix which is supported across major vendors GPU like Nvidia, AMD, and Intel. Given that the KHR version has been supported for nearly half a year, drop the NV-specific extension to reduce the maintenance burden and code duplication. --- .../mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h | 12 +- mlir/include/mlir/Conversion/Passes.td | 4 - .../mlir/Dialect/SPIRV/IR/SPIRVBase.td | 38 +-- .../SPIRV/IR/SPIRVCooperativeMatrixOps.td | 247 ------------------ .../mlir/Dialect/SPIRV/IR/SPIRVTypes.h | 27 -- .../Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp | 12 +- .../Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp | 133 +--------- mlir/lib/Dialect/SPIRV/IR/CastOps.cpp | 2 +- .../Dialect/SPIRV/IR/CooperativeMatrixOps.cpp | 152 ----------- mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp | 46 +--- mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp | 8 +- mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp | 93 +------ .../SPIRV/Deserialization/DeserializeOps.cpp | 1 - .../SPIRV/Deserialization/Deserializer.cpp | 33 --- .../Target/SPIRV/Serialization/Serializer.cpp | 20 -- .../wmma-ops-to-spirv-khr-coop-matrix.mlir | 2 +- .../wmma-ops-to-spirv-nv-coop-matrix.mlir | 194 -------------- mlir/test/Dialect/SPIRV/IR/cast-ops.mlir | 24 -- mlir/test/Dialect/SPIRV/IR/composite-ops.mlir | 39 --- .../SPIRV/IR/khr-cooperative-matrix-ops.mlir | 26 -- mlir/test/Dialect/SPIRV/IR/matrix-ops.mlir | 8 +- .../SPIRV/IR/nv-cooperative-matrix-ops.mlir | 177 ------------- mlir/test/Dialect/SPIRV/IR/structure-ops.mlir | 4 +- mlir/test/Dialect/SPIRV/IR/types.mlir | 19 -- mlir/test/Target/SPIRV/matrix.mlir | 8 +- .../SPIRV/nv-cooperative-matrix-ops.mlir | 102 -------- 26 files changed, 49 insertions(+), 1382 deletions(-) delete mode 100644 mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-nv-coop-matrix.mlir delete mode 100644 mlir/test/Dialect/SPIRV/IR/nv-cooperative-matrix-ops.mlir delete mode 100644 mlir/test/Target/SPIRV/nv-cooperative-matrix-ops.mlir diff --git a/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h b/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h index cd650345f1da..d34549432161 100644 --- a/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h +++ b/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h @@ -31,16 +31,10 @@ void populateGPUToSPIRVPatterns(SPIRVTypeConverter &typeConverter, void populateGpuWMMAToSPIRVCoopMatrixKHRConversionPatterns( SPIRVTypeConverter &typeConverter, RewritePatternSet &patterns); -/// Collect a set of patterns to convert WMMA ops from GPU dialect to SPIRV, -/// using the NV Cooperative Matrix extension. -void populateGpuWMMAToSPIRVCoopMatrixNVConversionPatterns( - SPIRVTypeConverter &typeConverter, RewritePatternSet &patterns); - -/// Adds `MMAMatrixType` conversions to SPIR-V cooperative matrix type -/// conversion to the type converter. Defaults to KHR cooperative matrix types. -/// When `useNVTypes` is `true`, uses the NV cooperative matrix types. +/// Adds `MMAMatrixType` conversions to SPIR-V cooperative matrix KHR type +/// conversion to the type converter. void populateMMAToSPIRVCoopMatrixTypeConversion( - SPIRVTypeConverter &typeConverter, bool useNVTypes = false); + SPIRVTypeConverter &typeConverter); } // namespace mlir #endif // MLIR_CONVERSION_GPUTOSPIRV_GPUTOSPIRV_H diff --git a/mlir/include/mlir/Conversion/Passes.td b/mlir/include/mlir/Conversion/Passes.td index 6193aeb545bc..71be8841ca7c 100644 --- a/mlir/include/mlir/Conversion/Passes.td +++ b/mlir/include/mlir/Conversion/Passes.td @@ -564,10 +564,6 @@ def ConvertGPUToSPIRV : Pass<"convert-gpu-to-spirv", "ModuleOp"> { Option<"use64bitIndex", "use-64bit-index", "bool", /*default=*/"false", "Use 64-bit integers to convert index types">, - Option<"useCoopMatrixNV", "use-coop-matrix-nv", - "bool", /*default=*/"false", - "Use the NV cooperative matrix extension insted of the KHR extension" - " to lower GPU WMMA ops">, ]; } diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td index ee1fbba1e284..6ec97e17c5dc 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td @@ -1253,12 +1253,6 @@ def SPIRV_C_RayTracingProvisionalKHR : I32EnumAttrCase<"RayTr Extension<[SPV_KHR_ray_tracing]> ]; } -def SPIRV_C_CooperativeMatrixNV : I32EnumAttrCase<"CooperativeMatrixNV", 5357> { - list implies = [SPIRV_C_Shader]; - list availability = [ - Extension<[SPV_NV_cooperative_matrix]> - ]; -} def SPIRV_C_FragmentShaderSampleInterlockEXT : I32EnumAttrCase<"FragmentShaderSampleInterlockEXT", 5363> { list implies = [SPIRV_C_Shader]; list availability = [ @@ -1501,7 +1495,7 @@ def SPIRV_CapabilityAttr : SPIRV_C_ShaderNonUniform, SPIRV_C_RuntimeDescriptorArray, SPIRV_C_StorageTexelBufferArrayDynamicIndexing, SPIRV_C_RayTracingNV, SPIRV_C_RayTracingMotionBlurNV, SPIRV_C_PhysicalStorageBufferAddresses, - SPIRV_C_RayTracingProvisionalKHR, SPIRV_C_CooperativeMatrixNV, + SPIRV_C_RayTracingProvisionalKHR, SPIRV_C_FragmentShaderSampleInterlockEXT, SPIRV_C_FragmentShaderShadingRateInterlockEXT, SPIRV_C_ShaderSMBuiltinsNV, SPIRV_C_FragmentShaderPixelInterlockEXT, SPIRV_C_DemoteToHelperInvocation, @@ -4123,8 +4117,6 @@ class SignlessOrUnsignedIntOfWidths widths> : def SPIRV_IsArrayType : CPred<"::llvm::isa<::mlir::spirv::ArrayType>($_self)">; def SPIRV_IsCooperativeMatrixType : CPred<"::llvm::isa<::mlir::spirv::CooperativeMatrixType>($_self)">; -def SPIRV_IsCooperativeMatrixNVType : - CPred<"::llvm::isa<::mlir::spirv::CooperativeMatrixNVType>($_self)">; def SPIRV_IsImageType : CPred<"::llvm::isa<::mlir::spirv::ImageType>($_self)">; def SPIRV_IsJointMatrixType : CPred<"::llvm::isa<::mlir::spirv::JointMatrixINTELType>($_self)">; @@ -4157,9 +4149,6 @@ def SPIRV_AnyArray : DialectType; -def SPIRV_AnyCooperativeMatrixNV : DialectType; def SPIRV_AnyImage : DialectType; def SPIRV_AnyJointMatrix : DialectType; def SPIRV_Aggregate : AnyTypeOf<[SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct]>; def SPIRV_Composite : AnyTypeOf<[SPIRV_Vector, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct, - SPIRV_AnyCooperativeMatrix, SPIRV_AnyCooperativeMatrixNV, - SPIRV_AnyJointMatrix, SPIRV_AnyMatrix]>; + SPIRV_AnyCooperativeMatrix, SPIRV_AnyJointMatrix, SPIRV_AnyMatrix]>; def SPIRV_Type : AnyTypeOf<[ SPIRV_Void, SPIRV_Bool, SPIRV_Integer, SPIRV_Float, SPIRV_Vector, SPIRV_AnyPtr, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct, - SPIRV_AnyCooperativeMatrix, SPIRV_AnyCooperativeMatrixNV, - SPIRV_AnyJointMatrix, SPIRV_AnyMatrix, SPIRV_AnySampledImage + SPIRV_AnyCooperativeMatrix, SPIRV_AnyJointMatrix, SPIRV_AnyMatrix, + SPIRV_AnySampledImage ]>; def SPIRV_SignedInt : SignedIntOfWidths<[8, 16, 32, 64]>; @@ -4195,11 +4183,6 @@ class SPIRV_CoopMatrixOfType allowedTypes> : "::llvm::cast<::mlir::spirv::CooperativeMatrixType>($_self).getElementType()", "Cooperative Matrix">; -class SPIRV_CoopMatrixNVOfType allowedTypes> : - ContainerType, SPIRV_IsCooperativeMatrixNVType, - "::llvm::cast<::mlir::spirv::CooperativeMatrixNVType>($_self).getElementType()", - "Cooperative Matrix NV">; - class SPIRV_JointMatrixOfType allowedTypes> : ContainerType, SPIRV_IsJointMatrixType, "::llvm::cast<::mlir::spirv::JointMatrixINTELType>($_self).getElementType()", @@ -4213,12 +4196,11 @@ class SPIRV_ScalarOrVectorOf : class SPIRV_ScalarOrVectorOrCoopMatrixOf : AnyTypeOf<[type, SPIRV_VectorOf, - SPIRV_CoopMatrixOfType<[type]>, SPIRV_CoopMatrixNVOfType<[type]>]>; + SPIRV_CoopMatrixOfType<[type]>]>; class SPIRV_MatrixOrCoopMatrixOf : AnyTypeOf<[SPIRV_AnyMatrix, - SPIRV_CoopMatrixOfType<[type]>, - SPIRV_CoopMatrixNVOfType<[type]>]>; + SPIRV_CoopMatrixOfType<[type]>]>; def SPIRV_ScalarOrVector : AnyTypeOf<[SPIRV_Scalar, SPIRV_Vector]>; def SPIRV_ScalarOrVectorOrPtr : AnyTypeOf<[SPIRV_ScalarOrVector, SPIRV_AnyPtr]>; @@ -4480,11 +4462,6 @@ def SPIRV_OC_OpCooperativeMatrixLoadKHR : I32EnumAttrCase<"OpCooperativeMatrix def SPIRV_OC_OpCooperativeMatrixStoreKHR : I32EnumAttrCase<"OpCooperativeMatrixStoreKHR", 4458>; def SPIRV_OC_OpCooperativeMatrixMulAddKHR : I32EnumAttrCase<"OpCooperativeMatrixMulAddKHR", 4459>; def SPIRV_OC_OpCooperativeMatrixLengthKHR : I32EnumAttrCase<"OpCooperativeMatrixLengthKHR", 4460>; -def SPIRV_OC_OpTypeCooperativeMatrixNV : I32EnumAttrCase<"OpTypeCooperativeMatrixNV", 5358>; -def SPIRV_OC_OpCooperativeMatrixLoadNV : I32EnumAttrCase<"OpCooperativeMatrixLoadNV", 5359>; -def SPIRV_OC_OpCooperativeMatrixStoreNV : I32EnumAttrCase<"OpCooperativeMatrixStoreNV", 5360>; -def SPIRV_OC_OpCooperativeMatrixMulAddNV : I32EnumAttrCase<"OpCooperativeMatrixMulAddNV", 5361>; -def SPIRV_OC_OpCooperativeMatrixLengthNV : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>; def SPIRV_OC_OpSubgroupBlockReadINTEL : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>; def SPIRV_OC_OpSubgroupBlockWriteINTEL : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>; def SPIRV_OC_OpAssumeTrueKHR : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>; @@ -4585,9 +4562,6 @@ def SPIRV_OpcodeAttr : SPIRV_OC_OpTypeCooperativeMatrixKHR, SPIRV_OC_OpCooperativeMatrixLoadKHR, SPIRV_OC_OpCooperativeMatrixStoreKHR, SPIRV_OC_OpCooperativeMatrixMulAddKHR, SPIRV_OC_OpCooperativeMatrixLengthKHR, - SPIRV_OC_OpTypeCooperativeMatrixNV, SPIRV_OC_OpCooperativeMatrixLoadNV, - SPIRV_OC_OpCooperativeMatrixStoreNV, SPIRV_OC_OpCooperativeMatrixMulAddNV, - SPIRV_OC_OpCooperativeMatrixLengthNV, SPIRV_OC_OpSubgroupBlockReadINTEL, SPIRV_OC_OpSubgroupBlockWriteINTEL, SPIRV_OC_OpAssumeTrueKHR, SPIRV_OC_OpAtomicFAddEXT, SPIRV_OC_OpGroupIMulKHR, SPIRV_OC_OpGroupFMulKHR, diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td index 29ad45bddd55..46732ba19afe 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td @@ -338,253 +338,6 @@ def SPIRV_KHRCooperativeMatrixMulAddOp : SPIRV_KhrVendorOp<"CooperativeMatrixMul ]; } -//===----------------------------------------------------------------------===// -// SPV_NV_cooperative_matrix extension ops. -//===----------------------------------------------------------------------===// - -// ----- - -def SPIRV_NVCooperativeMatrixLengthOp : SPIRV_NvVendorOp<"CooperativeMatrixLength", - [Pure]> { - let summary = "See extension SPV_NV_cooperative_matrix"; - - let description = [{ - Number of components of a cooperative matrix type accessible to each - invocation when treated as a composite. - - Result Type must be an OpTypeInt with 32-bit Width and 0 Signedness. - - Type is a cooperative matrix type. - - #### Example: - - ``` - %0 = spirv.NV.CooperativeMatrixLength : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - ``` - }]; - - let assemblyFormat = "attr-dict `:` $cooperative_matrix_type"; - - let availability = [ - MinVersion, - MaxVersion, - Extension<[SPV_NV_cooperative_matrix]>, - Capability<[SPIRV_C_CooperativeMatrixNV]> - ]; - - let arguments = (ins - TypeAttr:$cooperative_matrix_type - ); - - let results = (outs - SPIRV_Int32:$result - ); -} - -// ----- - -def SPIRV_NVCooperativeMatrixLoadOp : SPIRV_NvVendorOp<"CooperativeMatrixLoad", []> { - let summary = "See extension SPV_NV_cooperative_matrix"; - - let description = [{ - Load a cooperative matrix through a pointer. - - Result Type is the type of the loaded object. It must be a cooperative - matrix type. - - Pointer is a pointer into an array. Its type must be an OpTypePointer whose - Type operand is a scalar or vector type. The storage class of Pointer must - be Workgroup, StorageBuffer, or (if SPV_EXT_physical_storage_buffer is - supported) PhysicalStorageBufferEXT. - - Stride is the number of elements in the array in memory between the first - component of consecutive rows (or columns) in the result. It must be a - scalar integer type. - - ColumnMajor indicates whether the values loaded from memory are arranged in - column-major or row-major order. It must be a boolean constant instruction, - with false indicating row major and true indicating column major. - - Memory Access must be a Memory Access literal. If not present, it is the - same as specifying None. - - If ColumnMajor is false, then elements (row,*) of the result are taken in - order from contiguous locations starting at Pointer[row*Stride]. If - ColumnMajor is true, then elements (*,col) of the result are taken in order - from contiguous locations starting from Pointer[col*Stride]. Any ArrayStride - decoration on Pointer is ignored. - - For a given dynamic instance of this instruction, all operands of this - instruction must be the same for all invocations in a given scope instance - (where the scope is the scope the cooperative matrix type was created with). - All invocations in a given scope instance must be active or all must be - inactive. - - ### Custom assembly form - - ``` {.ebnf} - cooperative-matrixload-op ::= ssa-id `=` `spirv.NV.CooperativeMatrixLoad` - ssa-use `,` ssa-use `,` ssa-use - (`[` memory-access `]`)? ` : ` - pointer-type `as` - cooperative-matrix-type - ``` - - #### Example: - - ``` - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %colMajor - : !spirv.ptr as !spirv.NV.coopmatrix<16x8xi32, Workgroup> - ``` - }]; - - let availability = [ - MinVersion, - MaxVersion, - Extension<[SPV_NV_cooperative_matrix]>, - Capability<[SPIRV_C_CooperativeMatrixNV]> - ]; - - let arguments = (ins - SPIRV_AnyPtr:$pointer, - SPIRV_Integer:$stride, - SPIRV_Bool:$columnmajor, - OptionalAttr:$memory_access - ); - - let results = (outs - SPIRV_AnyCooperativeMatrixNV:$result - ); -} - -// ----- - -def SPIRV_NVCooperativeMatrixMulAddOp : SPIRV_NvVendorOp<"CooperativeMatrixMulAdd", - [Pure, AllTypesMatch<["c", "result"]>]> { - let summary = "See extension SPV_NV_cooperative_matrix"; - - let description = [{ - Linear-algebraic matrix multiply of A by B and then component-wise add C. - The order of the operations is implementation-dependent. The internal - precision of floating-point operations is defined by the client API. - Integer operations are performed at the precision of the Result Type and are - exact unless there is overflow or underflow, in which case the result is - undefined. - - Result Type must be a cooperative matrix type with M rows and N columns. - - A is a cooperative matrix with M rows and K columns. - - B is a cooperative matrix with K rows and N columns. - - C is a cooperative matrix with M rows and N columns. - - The values of M, N, and K must be consistent across the result and operands. - This is referred to as an MxNxK matrix multiply. - - A, B, C, and Result Type must have the same scope, and this defines the - scope of the operation. A, B, C, and Result Type need not necessarily have - the same component type, this is defined by the client API. - - If the Component Type of any matrix operand is an integer type, then its - components are treated as signed if its Component Type has Signedness of 1 - and are treated as unsigned otherwise. - - For a given dynamic instance of this instruction, all invocations in a given - scope instance must be active or all must be inactive (where the scope is - the scope of the operation). - - #### Example: - - ``` - %0 = spirv.NV.CooperativeMatrixMulAdd %arg0, %arg1, %arg2, : - !spirv.NV.coopmatrix<8x16xi32, Subgroup> - ``` - }]; - - let assemblyFormat = [{ - operands attr-dict `:` type($a) `,` type($b) `->` type($c) - }]; - - let availability = [ - MinVersion, - MaxVersion, - Extension<[SPV_NV_cooperative_matrix]>, - Capability<[SPIRV_C_CooperativeMatrixNV]> - ]; - - let arguments = (ins - SPIRV_AnyCooperativeMatrixNV:$a, - SPIRV_AnyCooperativeMatrixNV:$b, - SPIRV_AnyCooperativeMatrixNV:$c - ); - - let results = (outs - SPIRV_AnyCooperativeMatrixNV:$result - ); -} - -// ----- - -def SPIRV_NVCooperativeMatrixStoreOp : SPIRV_NvVendorOp<"CooperativeMatrixStore", []> { - let summary = "See extension SPV_NV_cooperative_matrix"; - - let description = [{ - Store a cooperative matrix through a pointer. - - Pointer is a pointer into an array. Its type must be an OpTypePointer whose - Type operand is a scalar or vector type. The storage class of Pointer must - be Workgroup, StorageBuffer, or (if SPV_EXT_physical_storage_buffer is - supported) PhysicalStorageBufferEXT. - - Object is the object to store. Its type must be an - OpTypeCooperativeMatrixNV. - - Stride is the number of elements in the array in memory between the first - component of consecutive rows (or columns) in the result. It must be a - scalar integer type. - - ColumnMajor indicates whether the values stored to memory are arranged in - column-major or row-major order. It must be a boolean constant instruction, - with false indicating row major and true indicating column major. - - Memory Access must be a Memory Access literal. If not present, it is the - same as specifying None. - - ``` {.ebnf} - coop-matrix-store-op ::= `spirv.NV.CooperativeMatrixStore ` - ssa-use `, ` ssa-use `, ` - ssa-use `, ` ssa-use `, ` - (`[` memory-access `]`)? `:` - pointer-type `,` coop-matrix-type - ``` - - #### Example: - - ``` - spirv.NV.CooperativeMatrixStore %arg0, %arg2, %arg1, %arg3 : - !spirv.ptr, !spirv.NV.coopmatrix<16x8xi32, Workgroup> - ``` - }]; - - let availability = [ - MinVersion, - MaxVersion, - Extension<[SPV_NV_cooperative_matrix]>, - Capability<[SPIRV_C_CooperativeMatrixNV]> - ]; - - let arguments = (ins - SPIRV_AnyPtr:$pointer, - SPIRV_AnyCooperativeMatrixNV:$object, - SPIRV_Integer:$stride, - SPIRV_Bool:$columnmajor, - OptionalAttr:$memory_access - ); - - let results = (outs); -} - // ----- #endif // MLIR_DIALECT_SPIRV_IR_COOPERATIVE_MATRIX_OPS diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h index d946d936d4e6..55f0c787b444 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h @@ -29,7 +29,6 @@ namespace spirv { namespace detail { struct ArrayTypeStorage; struct CooperativeMatrixTypeStorage; -struct CooperativeMatrixNVTypeStorage; struct ImageTypeStorage; struct JointMatrixTypeStorage; struct MatrixTypeStorage; @@ -421,32 +420,6 @@ public: std::optional storage = std::nullopt); }; -// SPIR-V NV cooperative matrix type -class CooperativeMatrixNVType - : public Type::TypeBase { -public: - using Base::Base; - - static constexpr StringLiteral name = "spirv.NV.coopmatrix"; - - static CooperativeMatrixNVType get(Type elementType, Scope scope, - unsigned rows, unsigned columns); - Type getElementType() const; - - /// Returns the scope of the matrix. - Scope getScope() const; - /// Returns the number of rows of the matrix. - unsigned getRows() const; - /// Returns the number of columns of the matrix. - unsigned getColumns() const; - - void getExtensions(SPIRVType::ExtensionArrayRefVector &extensions, - std::optional storage = std::nullopt); - void getCapabilities(SPIRVType::CapabilityArrayRefVector &capabilities, - std::optional storage = std::nullopt); -}; - // SPIR-V joint matrix type class JointMatrixINTELType : public Type::TypeBaseuse64bitIndex; SPIRVTypeConverter typeConverter(targetAttr, options); - populateMMAToSPIRVCoopMatrixTypeConversion(typeConverter, - this->useCoopMatrixNV); + populateMMAToSPIRVCoopMatrixTypeConversion(typeConverter); RewritePatternSet patterns(context); populateGPUToSPIRVPatterns(typeConverter, patterns); - if (this->useCoopMatrixNV) { - populateGpuWMMAToSPIRVCoopMatrixNVConversionPatterns(typeConverter, - patterns); - } else { - populateGpuWMMAToSPIRVCoopMatrixKHRConversionPatterns(typeConverter, - patterns); - } + populateGpuWMMAToSPIRVCoopMatrixKHRConversionPatterns(typeConverter, + patterns); // TODO: Change SPIR-V conversion to be progressive and remove the following // patterns. diff --git a/mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp b/mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp index 4a4281aaaf0d..92cc0eadb978 100644 --- a/mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp +++ b/mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp @@ -32,19 +32,18 @@ namespace mlir { //===----------------------------------------------------------------------===// -// Patterns and helpers used by both the KHR and the NV lowering paths. +// Patterns and helpers. //===----------------------------------------------------------------------===// /// Creates a SPIR-V op to replace the given GPU subgroup mma elementwise op /// when the elementwise op directly supports with cooperative matrix type. /// Returns false if cannot. /// -/// See SPV_NV_cooperative_matrix for supported elementwise ops. +/// See SPV_KHR_cooperative_matrix for supported elementwise ops. static bool createElementwiseOp(ConversionPatternRewriter &builder, gpu::SubgroupMmaElementwiseOp op, Type coopType, ValueRange operands) { - assert((isa( - coopType))); + assert((isa(coopType))); switch (op.getOpType()) { case gpu::MMAElementwiseOp::ADDF: @@ -89,8 +88,7 @@ bool allOperandsHaveSameCoopMatrixType(ValueRange operands) { llvm::map_range(operands, [](Value v) { return v.getType(); }))) return false; - return isa( - operands.front().getType()); + return isa(operands.front().getType()); } namespace { @@ -292,104 +290,6 @@ struct WmmaMmaOpToSPIRVLowering final } // namespace } // namespace khr - -//===----------------------------------------------------------------------===// -// SPV_NV_cooperative_matrix -//===----------------------------------------------------------------------===// - -namespace nv { -namespace { - -/// Converts the GPU MMA loadOp to NVCooperativeMatrixLoad op in the SPIRV -/// dialect. -struct WmmaLoadOpToSPIRVLowering final - : OpConversionPattern { - using OpConversionPattern::OpConversionPattern; - - LogicalResult - matchAndRewrite(gpu::SubgroupMmaLoadMatrixOp subgroupMmaLoadMatrixOp, - OpAdaptor adaptor, - ConversionPatternRewriter &rewriter) const override { - Location loc = subgroupMmaLoadMatrixOp->getLoc(); - auto &typeConverter = *getTypeConverter(); - - gpu::MMAMatrixType retType = - cast(subgroupMmaLoadMatrixOp.getRes().getType()); - auto memrefType = - cast(subgroupMmaLoadMatrixOp.getSrcMemref().getType()); - Value bufferPtr = - spirv::getElementPtr(typeConverter, memrefType, adaptor.getSrcMemref(), - adaptor.getIndices(), loc, rewriter); - auto coopType = - typeConverter.convertType(retType); - if (!coopType) - return rewriter.notifyMatchFailure(subgroupMmaLoadMatrixOp, - "type conversion failed"); - - int64_t stride = subgroupMmaLoadMatrixOp.getLeadDimension().getSExtValue(); - auto i32Type = rewriter.getI32Type(); - auto strideValue = rewriter.create( - loc, i32Type, IntegerAttr::get(i32Type, stride)); - bool isColMajor = static_cast(subgroupMmaLoadMatrixOp.getTranspose()); - auto columnMajor = rewriter.create( - loc, rewriter.getI1Type(), rewriter.getBoolAttr(isColMajor)); - rewriter.replaceOpWithNewOp( - subgroupMmaLoadMatrixOp, coopType, bufferPtr, strideValue, columnMajor, - spirv::MemoryAccessAttr()); - return success(); - } -}; - -/// Converts the GPU MMA StoreOp to NVCooperativeMatrixStore op in the SPIRV -/// dialect. -struct WmmaStoreOpToSPIRVLowering final - : OpConversionPattern { - using OpConversionPattern::OpConversionPattern; - - LogicalResult - matchAndRewrite(gpu::SubgroupMmaStoreMatrixOp subgroupMmaStoreMatrixOp, - OpAdaptor adaptor, - ConversionPatternRewriter &rewriter) const override { - Location loc = subgroupMmaStoreMatrixOp->getLoc(); - auto memrefType = - cast(subgroupMmaStoreMatrixOp.getDstMemref().getType()); - Value bufferPtr = spirv::getElementPtr( - *getTypeConverter(), memrefType, - adaptor.getDstMemref(), adaptor.getIndices(), loc, rewriter); - int64_t stride = subgroupMmaStoreMatrixOp.getLeadDimension().getSExtValue(); - auto i32Type = rewriter.getI32Type(); - auto strideValue = rewriter.create( - loc, i32Type, IntegerAttr::get(i32Type, stride)); - bool useColMajor = - static_cast(subgroupMmaStoreMatrixOp.getTranspose()); - auto columnMajor = rewriter.create( - loc, rewriter.getI1Type(), rewriter.getBoolAttr(useColMajor)); - rewriter.replaceOpWithNewOp( - subgroupMmaStoreMatrixOp, bufferPtr, adaptor.getSrc(), strideValue, - columnMajor, spirv::MemoryAccessAttr()); - return success(); - } -}; - -/// Converts GPU MMA Compute to -/// NVCooperativeMatrixMulAdd op in the SPIRV dialect. -struct WmmaMmaOpToSPIRVLowering final - : OpConversionPattern { - using OpConversionPattern::OpConversionPattern; - - LogicalResult - matchAndRewrite(gpu::SubgroupMmaComputeOp subgroupMmaComputeOp, - OpAdaptor adaptor, - ConversionPatternRewriter &rewriter) const override { - rewriter.replaceOpWithNewOp( - subgroupMmaComputeOp, adaptor.getOpC().getType(), adaptor.getOpA(), - adaptor.getOpB(), adaptor.getOpC()); - return success(); - } -}; - -} // namespace -} // namespace nv } // namespace mlir void mlir::populateGpuWMMAToSPIRVCoopMatrixKHRConversionPatterns( @@ -404,31 +304,8 @@ void mlir::populateGpuWMMAToSPIRVCoopMatrixKHRConversionPatterns( /*benefit=*/2); } -void mlir::populateGpuWMMAToSPIRVCoopMatrixNVConversionPatterns( - SPIRVTypeConverter &converter, RewritePatternSet &patterns) { - using namespace mlir; - MLIRContext *context = patterns.getContext(); - patterns.add(converter, context); - // Give the following patterns higher benefit to prevail over the default one. - patterns.add(converter, context, - /*benefit=*/2); -} - void mlir::populateMMAToSPIRVCoopMatrixTypeConversion( - mlir::SPIRVTypeConverter &typeConverter, bool useNVTypes) { - if (useNVTypes) { - typeConverter.addConversion([](gpu::MMAMatrixType type) { - ArrayRef retTypeShape = type.getShape(); - Type elementType = type.getElementType(); - return spirv::CooperativeMatrixNVType::get( - elementType, spirv::Scope::Subgroup, retTypeShape[0], - retTypeShape[1]); - }); - return; - } - + mlir::SPIRVTypeConverter &typeConverter) { typeConverter.addConversion([](gpu::MMAMatrixType type) { ArrayRef retTypeShape = type.getShape(); Type elementType = type.getElementType(); diff --git a/mlir/lib/Dialect/SPIRV/IR/CastOps.cpp b/mlir/lib/Dialect/SPIRV/IR/CastOps.cpp index f24da2ca5c3f..52b4380ed27f 100644 --- a/mlir/lib/Dialect/SPIRV/IR/CastOps.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/CastOps.cpp @@ -37,7 +37,7 @@ static LogicalResult verifyCastOp(Operation *op, auto [operandElemTy, resultElemTy] = TypeSwitch(operandType) .Case( + spirv::JointMatrixINTELType>( [resultType](auto concreteOperandTy) -> TypePair { if (auto concreteResultTy = dyn_cast(resultType)) { diff --git a/mlir/lib/Dialect/SPIRV/IR/CooperativeMatrixOps.cpp b/mlir/lib/Dialect/SPIRV/IR/CooperativeMatrixOps.cpp index c8b274ceec3e..d532d466334a 100644 --- a/mlir/lib/Dialect/SPIRV/IR/CooperativeMatrixOps.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/CooperativeMatrixOps.cpp @@ -136,156 +136,4 @@ LogicalResult KHRCooperativeMatrixMulAddOp::verify() { return success(); } -//===----------------------------------------------------------------------===// -// spirv.NV.CooperativeMatrixLength -//===----------------------------------------------------------------------===// - -LogicalResult NVCooperativeMatrixLengthOp::verify() { - if (!isa(getCooperativeMatrixType())) { - return emitOpError( - "type attribute must be a '!spirv.NV.coopmatrix' type, found ") - << getCooperativeMatrixType() << " instead"; - } - - return success(); -} - -//===----------------------------------------------------------------------===// -// spirv.NV.CooperativeMatrixLoad -//===----------------------------------------------------------------------===// - -ParseResult NVCooperativeMatrixLoadOp::parse(OpAsmParser &parser, - OperationState &result) { - SmallVector operandInfo; - Type strideType = parser.getBuilder().getIntegerType(32); - Type columnMajorType = parser.getBuilder().getIntegerType(1); - Type ptrType; - Type elementType; - if (parser.parseOperandList(operandInfo, 3) || - parseMemoryAccessAttributes(parser, result) || parser.parseColon() || - parser.parseType(ptrType) || parser.parseKeywordType("as", elementType)) { - return failure(); - } - if (parser.resolveOperands(operandInfo, - {ptrType, strideType, columnMajorType}, - parser.getNameLoc(), result.operands)) { - return failure(); - } - - result.addTypes(elementType); - return success(); -} - -void NVCooperativeMatrixLoadOp::print(OpAsmPrinter &printer) { - printer << " " << getPointer() << ", " << getStride() << ", " - << getColumnmajor(); - // Print optional memory access attribute. - if (auto memAccess = getMemoryAccess()) - printer << " [\"" << stringifyMemoryAccess(*memAccess) << "\"]"; - printer << " : " << getPointer().getType() << " as " << getType(); -} - -static LogicalResult -verifyPointerAndCoopMatrixNVType(Operation *op, Type pointer, Type coopMatrix) { - Type pointeeType = llvm::cast(pointer).getPointeeType(); - if (!llvm::isa(pointeeType) && - !llvm::isa(pointeeType)) - return op->emitError( - "Pointer must point to a scalar or vector type but provided ") - << pointeeType; - StorageClass storage = llvm::cast(pointer).getStorageClass(); - if (storage != StorageClass::Workgroup && - storage != StorageClass::StorageBuffer && - storage != StorageClass::PhysicalStorageBuffer) - return op->emitError( - "Pointer storage class must be Workgroup, StorageBuffer or " - "PhysicalStorageBufferEXT but provided ") - << stringifyStorageClass(storage); - return success(); -} - -LogicalResult NVCooperativeMatrixLoadOp::verify() { - return verifyPointerAndCoopMatrixNVType(*this, getPointer().getType(), - getResult().getType()); -} - -//===----------------------------------------------------------------------===// -// spirv.NV.CooperativeMatrixStore -//===----------------------------------------------------------------------===// - -ParseResult NVCooperativeMatrixStoreOp::parse(OpAsmParser &parser, - OperationState &result) { - SmallVector operandInfo; - Type strideType = parser.getBuilder().getIntegerType(32); - Type columnMajorType = parser.getBuilder().getIntegerType(1); - Type ptrType; - Type elementType; - if (parser.parseOperandList(operandInfo, 4) || - parseMemoryAccessAttributes(parser, result) || parser.parseColon() || - parser.parseType(ptrType) || parser.parseComma() || - parser.parseType(elementType)) { - return failure(); - } - if (parser.resolveOperands( - operandInfo, {ptrType, elementType, strideType, columnMajorType}, - parser.getNameLoc(), result.operands)) { - return failure(); - } - - return success(); -} - -void NVCooperativeMatrixStoreOp::print(OpAsmPrinter &printer) { - printer << " " << getPointer() << ", " << getObject() << ", " << getStride() - << ", " << getColumnmajor(); - // Print optional memory access attribute. - if (auto memAccess = getMemoryAccess()) - printer << " [\"" << stringifyMemoryAccess(*memAccess) << "\"]"; - printer << " : " << getPointer().getType() << ", " << getOperand(1).getType(); -} - -LogicalResult NVCooperativeMatrixStoreOp::verify() { - return verifyPointerAndCoopMatrixNVType(*this, getPointer().getType(), - getObject().getType()); -} - -//===----------------------------------------------------------------------===// -// spirv.NV.CooperativeMatrixMulAdd -//===----------------------------------------------------------------------===// - -static LogicalResult verifyCoopMatrixMulAddNV(NVCooperativeMatrixMulAddOp op) { - if (op.getC().getType() != op.getResult().getType()) - return op.emitOpError("result and third operand must have the same type"); - auto typeA = llvm::cast(op.getA().getType()); - auto typeB = llvm::cast(op.getB().getType()); - auto typeC = llvm::cast(op.getC().getType()); - auto typeR = llvm::cast(op.getResult().getType()); - if (typeA.getRows() != typeR.getRows() || - typeA.getColumns() != typeB.getRows() || - typeB.getColumns() != typeR.getColumns()) - return op.emitOpError("matrix size must match"); - if (typeR.getScope() != typeA.getScope() || - typeR.getScope() != typeB.getScope() || - typeR.getScope() != typeC.getScope()) - return op.emitOpError("matrix scope must match"); - auto elementTypeA = typeA.getElementType(); - auto elementTypeB = typeB.getElementType(); - if (isa(elementTypeA) && isa(elementTypeB)) { - if (llvm::cast(elementTypeA).getWidth() != - llvm::cast(elementTypeB).getWidth()) - return op.emitOpError( - "matrix A and B integer element types must be the same bit width"); - } else if (elementTypeA != elementTypeB) { - return op.emitOpError( - "matrix A and B non-integer element types must match"); - } - if (typeR.getElementType() != typeC.getElementType()) - return op.emitOpError("matrix accumulator element type must match"); - return success(); -} - -LogicalResult NVCooperativeMatrixMulAddOp::verify() { - return verifyCoopMatrixMulAddNV(*this); -} - } // namespace mlir::spirv diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp index d7944d600b0a..db26fa81790d 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp @@ -360,37 +360,6 @@ static Type parseCooperativeMatrixType(SPIRVDialect const &dialect, return CooperativeMatrixType::get(elementTy, dims[0], dims[1], scope, use); } -// nv-cooperative-matrix-type ::= -// `!spirv.NV.coopmatrix` `<` rows `x` columns `x` element-type `,` scope `>` -static Type parseCooperativeMatrixNVType(SPIRVDialect const &dialect, - DialectAsmParser &parser) { - if (parser.parseLess()) - return Type(); - - SmallVector dims; - SMLoc countLoc = parser.getCurrentLocation(); - if (parser.parseDimensionList(dims, /*allowDynamic=*/false)) - return Type(); - - if (dims.size() != 2) { - parser.emitError(countLoc, "expected rows and columns size"); - return Type(); - } - - auto elementTy = parseAndVerifyType(dialect, parser); - if (!elementTy) - return Type(); - - Scope scope; - if (parser.parseComma() || - spirv::parseEnumKeywordAttr(scope, parser, "scope ")) - return Type(); - - if (parser.parseGreater()) - return Type(); - return CooperativeMatrixNVType::get(elementTy, scope, dims[0], dims[1]); -} - // joint-matrix-type ::= `!spirv.jointmatrix` `<`rows `x` columns `x` // element-type // `,` layout `,` scope`>` @@ -810,8 +779,6 @@ Type SPIRVDialect::parseType(DialectAsmParser &parser) const { return parseArrayType(*this, parser); if (keyword == "coopmatrix") return parseCooperativeMatrixType(*this, parser); - if (keyword == "NV.coopmatrix") - return parseCooperativeMatrixNVType(*this, parser); if (keyword == "jointmatrix") return parseJointMatrixType(*this, parser); if (keyword == "image") @@ -917,12 +884,6 @@ static void print(CooperativeMatrixType type, DialectAsmPrinter &os) { << type.getUse() << ">"; } -static void print(CooperativeMatrixNVType type, DialectAsmPrinter &os) { - os << "NV.coopmatrix<" << type.getRows() << "x" << type.getColumns() << "x"; - os << type.getElementType() << ", " << stringifyScope(type.getScope()); - os << ">"; -} - static void print(JointMatrixINTELType type, DialectAsmPrinter &os) { os << "jointmatrix<" << type.getRows() << "x" << type.getColumns() << "x"; os << type.getElementType() << ", " @@ -937,10 +898,9 @@ static void print(MatrixType type, DialectAsmPrinter &os) { void SPIRVDialect::printType(Type type, DialectAsmPrinter &os) const { TypeSwitch(type) - .Case( - [&](auto type) { print(type, os); }) + .Case([&](auto type) { print(type, os); }) .Default([](Type) { llvm_unreachable("unhandled SPIR-V type"); }); } diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp index 3b159030cab7..50035c917137 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp @@ -374,8 +374,7 @@ LogicalResult spirv::CompositeConstructOp::verify() { auto coopElementType = llvm::TypeSwitch(getType()) - .Case( + .Case( [](auto coopType) { return coopType.getElementType(); }) .Default([](Type) { return nullptr; }); @@ -1677,8 +1676,7 @@ LogicalResult spirv::VectorShuffleOp::verify() { LogicalResult spirv::MatrixTimesScalarOp::verify() { Type elementType = llvm::TypeSwitch(getMatrix().getType()) - .Case( + .Case( [](auto matrixType) { return matrixType.getElementType(); }) .Default([](Type) { return nullptr; }); @@ -1817,7 +1815,7 @@ LogicalResult spirv::SpecConstantCompositeOp::verify() { return emitError("result type must be a composite type, but provided ") << getType(); - if (llvm::isa(cType)) + if (llvm::isa(cType)) return emitError("unsupported composite type ") << cType; if (llvm::isa(cType)) return emitError("unsupported composite type ") << cType; diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp index f1bac6490837..3f25696aa5eb 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp @@ -95,9 +95,8 @@ bool CompositeType::classof(Type type) { if (auto vectorType = llvm::dyn_cast(type)) return isValid(vectorType); return llvm::isa(type); + spirv::JointMatrixINTELType, spirv::MatrixType, + spirv::RuntimeArrayType, spirv::StructType>(type); } bool CompositeType::isValid(VectorType type) { @@ -108,8 +107,8 @@ bool CompositeType::isValid(VectorType type) { Type CompositeType::getElementType(unsigned index) const { return TypeSwitch(*this) - .Case( + .Case( [](auto type) { return type.getElementType(); }) .Case([](MatrixType type) { return type.getColumnType(); }) .Case( @@ -127,7 +126,7 @@ unsigned CompositeType::getNumElements() const { return structType.getNumElements(); if (auto vectorType = llvm::dyn_cast(*this)) return vectorType.getNumElements(); - if (llvm::isa(*this)) { + if (llvm::isa(*this)) { llvm_unreachable( "invalid to query number of elements of spirv Cooperative Matrix type"); } @@ -143,16 +142,16 @@ unsigned CompositeType::getNumElements() const { } bool CompositeType::hasCompileTimeKnownNumElements() const { - return !llvm::isa(*this); + return !llvm::isa(*this); } void CompositeType::getExtensions( SPIRVType::ExtensionArrayRefVector &extensions, std::optional storage) { TypeSwitch(*this) - .Case( + .Case( [&](auto type) { type.getExtensions(extensions, storage); }) .Case([&](VectorType type) { return llvm::cast(type.getElementType()) @@ -165,8 +164,8 @@ void CompositeType::getCapabilities( SPIRVType::CapabilityArrayRefVector &capabilities, std::optional storage) { TypeSwitch(*this) - .Case( + .Case( [&](auto type) { type.getCapabilities(capabilities, storage); }) .Case([&](VectorType type) { auto vecSize = getNumElements(); @@ -267,70 +266,6 @@ void CooperativeMatrixType::getCapabilities( capabilities.push_back(caps); } -//===----------------------------------------------------------------------===// -// CooperativeMatrixNVType -//===----------------------------------------------------------------------===// - -struct spirv::detail::CooperativeMatrixNVTypeStorage : public TypeStorage { - using KeyTy = std::tuple; - - static CooperativeMatrixNVTypeStorage * - construct(TypeStorageAllocator &allocator, const KeyTy &key) { - return new (allocator.allocate()) - CooperativeMatrixNVTypeStorage(key); - } - - bool operator==(const KeyTy &key) const { - return key == KeyTy(elementType, scope, rows, columns); - } - - CooperativeMatrixNVTypeStorage(const KeyTy &key) - : elementType(std::get<0>(key)), rows(std::get<2>(key)), - columns(std::get<3>(key)), scope(std::get<1>(key)) {} - - Type elementType; - unsigned rows; - unsigned columns; - Scope scope; -}; - -CooperativeMatrixNVType CooperativeMatrixNVType::get(Type elementType, - Scope scope, unsigned rows, - unsigned columns) { - return Base::get(elementType.getContext(), elementType, scope, rows, columns); -} - -Type CooperativeMatrixNVType::getElementType() const { - return getImpl()->elementType; -} - -Scope CooperativeMatrixNVType::getScope() const { return getImpl()->scope; } - -unsigned CooperativeMatrixNVType::getRows() const { return getImpl()->rows; } - -unsigned CooperativeMatrixNVType::getColumns() const { - return getImpl()->columns; -} - -void CooperativeMatrixNVType::getExtensions( - SPIRVType::ExtensionArrayRefVector &extensions, - std::optional storage) { - llvm::cast(getElementType()).getExtensions(extensions, storage); - static const Extension exts[] = {Extension::SPV_NV_cooperative_matrix}; - ArrayRef ref(exts, std::size(exts)); - extensions.push_back(ref); -} - -void CooperativeMatrixNVType::getCapabilities( - SPIRVType::CapabilityArrayRefVector &capabilities, - std::optional storage) { - llvm::cast(getElementType()) - .getCapabilities(capabilities, storage); - static const Capability caps[] = {Capability::CooperativeMatrixNV}; - ArrayRef ref(caps, std::size(caps)); - capabilities.push_back(ref); -} - //===----------------------------------------------------------------------===// // JointMatrixType //===----------------------------------------------------------------------===// @@ -1312,7 +1247,7 @@ void MatrixType::getCapabilities( //===----------------------------------------------------------------------===// void SPIRVDialect::registerTypes() { - addTypes(); + addTypes(); } diff --git a/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp b/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp index 954aaa98c329..a678124bf483 100644 --- a/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp +++ b/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp @@ -165,7 +165,6 @@ LogicalResult spirv::Deserializer::processInstruction( case spirv::Opcode::OpTypeStruct: case spirv::Opcode::OpTypePointer: case spirv::Opcode::OpTypeCooperativeMatrixKHR: - case spirv::Opcode::OpTypeCooperativeMatrixNV: return processType(opcode, operands); case spirv::Opcode::OpTypeForwardPointer: return processTypeForwardPointer(operands); diff --git a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp index 0c521adb1133..02d03b3a0fae 100644 --- a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp +++ b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp @@ -840,8 +840,6 @@ LogicalResult spirv::Deserializer::processType(spirv::Opcode opcode, return processArrayType(operands); case spirv::Opcode::OpTypeCooperativeMatrixKHR: return processCooperativeMatrixTypeKHR(operands); - case spirv::Opcode::OpTypeCooperativeMatrixNV: - return processCooperativeMatrixTypeNV(operands); case spirv::Opcode::OpTypeFunction: return processFunctionType(operands); case spirv::Opcode::OpTypeJointMatrixINTEL: @@ -1017,37 +1015,6 @@ LogicalResult spirv::Deserializer::processCooperativeMatrixTypeKHR( return success(); } -LogicalResult spirv::Deserializer::processCooperativeMatrixTypeNV( - ArrayRef operands) { - if (operands.size() != 5) { - return emitError(unknownLoc, "OpTypeCooperativeMatrixNV must have element " - "type and row x column parameters"); - } - - Type elementTy = getType(operands[1]); - if (!elementTy) { - return emitError(unknownLoc, - "OpTypeCooperativeMatrixNV references undefined ") - << operands[1]; - } - - std::optional scope = - spirv::symbolizeScope(getConstantInt(operands[2]).getInt()); - if (!scope) { - return emitError( - unknownLoc, - "OpTypeCooperativeMatrixNV references undefined scope ") - << operands[2]; - } - - unsigned rows = getConstantInt(operands[3]).getInt(); - unsigned columns = getConstantInt(operands[4]).getInt(); - - typeMap[operands[0]] = - spirv::CooperativeMatrixNVType::get(elementTy, *scope, rows, columns); - return success(); -} - LogicalResult spirv::Deserializer::processJointMatrixType(ArrayRef operands) { if (operands.size() != 6) { diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp index 1029fb933175..40337e007bbf 100644 --- a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp +++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp @@ -648,26 +648,6 @@ LogicalResult Serializer::prepareBasicType( return success(); } - if (auto cooperativeMatrixType = - dyn_cast(type)) { - uint32_t elementTypeID = 0; - if (failed(processTypeImpl(loc, cooperativeMatrixType.getElementType(), - elementTypeID, serializationCtx))) { - return failure(); - } - typeEnum = spirv::Opcode::OpTypeCooperativeMatrixNV; - auto getConstantOp = [&](uint32_t id) { - auto attr = IntegerAttr::get(IntegerType::get(type.getContext(), 32), id); - return prepareConstantInt(loc, attr); - }; - llvm::append_values( - operands, elementTypeID, - getConstantOp(static_cast(cooperativeMatrixType.getScope())), - getConstantOp(cooperativeMatrixType.getRows()), - getConstantOp(cooperativeMatrixType.getColumns())); - return success(); - } - if (auto jointMatrixType = dyn_cast(type)) { uint32_t elementTypeID = 0; if (failed(processTypeImpl(loc, jointMatrixType.getElementType(), diff --git a/mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-khr-coop-matrix.mlir b/mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-khr-coop-matrix.mlir index f129cc8ce84e..477f344b1ae5 100644 --- a/mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-khr-coop-matrix.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-khr-coop-matrix.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt --convert-gpu-to-spirv="use-coop-matrix-nv=false" --cse \ +// RUN: mlir-opt --convert-gpu-to-spirv --cse \ // RUN: --split-input-file --verify-diagnostics %s | FileCheck %s module attributes { diff --git a/mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-nv-coop-matrix.mlir b/mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-nv-coop-matrix.mlir deleted file mode 100644 index ec7da92704c0..000000000000 --- a/mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-nv-coop-matrix.mlir +++ /dev/null @@ -1,194 +0,0 @@ -// RUN: mlir-opt --convert-gpu-to-spirv="use-coop-matrix-nv=true" \ -// RUN: --split-input-file --verify-diagnostics %s | FileCheck %s - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_load_op - // CHECK-SAME: !spirv.ptr [0])>, StorageBuffer> - gpu.func @gpu_wmma_load_op(%arg0 : memref<32x32xf16, #spirv.storage_class>) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - %i = arith.constant 16 : index - %j = arith.constant 16 : index - // CHECK: %[[COLMAJOR:.*]] = spirv.Constant false - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, %[[COLMAJOR]] : !spirv.ptr as !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %0 = gpu.subgroup_mma_load_matrix %arg0[%i, %j] {leadDimension = 32 : index} : memref<32x32xf16, #spirv.storage_class> -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_load_op_transpose - // CHECK-SAME: {{%.*}}: !spirv.ptr [0])>, StorageBuffer> {spirv.interface_var_abi = #spirv.interface_var_abi<(0, 0)>} - // CHECK-SAME: spirv.entry_point_abi = #spirv.entry_point_abi - gpu.func @gpu_wmma_load_op_transpose(%arg0 : memref<32x32xf16, #spirv.storage_class>) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - %i = arith.constant 16 : index - %j = arith.constant 16 : index - // CHECK: %[[COLMAJOR:.*]] = spirv.Constant true - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, %[[COLMAJOR]] : !spirv.ptr as !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %0 = gpu.subgroup_mma_load_matrix %arg0[%i, %j] {leadDimension = 32 : index, transpose} : memref<32x32xf16, #spirv.storage_class> -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_store_op - // CHECK-SAME: !spirv.ptr [0])>, StorageBuffer> - // CHECK-SAME: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - gpu.func @gpu_wmma_store_op(%arg0 : memref<32x32xf16, #spirv.storage_class>, %arg1 : !gpu.mma_matrix<16x16xf16, "COp">) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - %i = arith.constant 16 : index - %j = arith.constant 16 : index - // CHECK: %[[COLMAJOR:.*]] = spirv.Constant false - // CHECK: spirv.NV.CooperativeMatrixStore {{%.*}}, {{%.*}}, {{%.*}}, %[[COLMAJOR]] : !spirv.ptr, !spirv.NV.coopmatrix<16x16xf16, Subgroup> - gpu.subgroup_mma_store_matrix %arg1, %arg0[%i,%j] {leadDimension= 32 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, #spirv.storage_class> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_store_op_transpose - // CHECK-SAME: {{%.*}}: !spirv.ptr [0])>, StorageBuffer> {spirv.interface_var_abi = #spirv.interface_var_abi<(0, 0)>} - // CHECK-SAME: {{%.*}}: !spirv.NV.coopmatrix<16x16xf16, Subgroup> {spirv.interface_var_abi = #spirv.interface_var_abi<(0, 1)>}) - // CHECK-SAME: spirv.entry_point_abi = #spirv.entry_point_abi - gpu.func @gpu_wmma_store_op_transpose(%arg0 : memref<32x32xf16, #spirv.storage_class>, %arg1 : !gpu.mma_matrix<16x16xf16, "COp">) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - %i = arith.constant 16 : index - %j = arith.constant 16 : index - // CHECK: %[[COLMAJOR:.*]] = spirv.Constant true - // CHECK: spirv.NV.CooperativeMatrixStore {{%.*}}, {{%.*}}, {{%.*}}, %[[COLMAJOR]] : !spirv.ptr, !spirv.NV.coopmatrix<16x16xf16, Subgroup> - gpu.subgroup_mma_store_matrix %arg1, %arg0[%i,%j] {leadDimension= 32 : index, transpose} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, #spirv.storage_class> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_mma_op - // CHECK-SAME: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - // CHECK-SAME: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - // CHECK-SAME: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - gpu.func @gpu_wmma_mma_op(%A : !gpu.mma_matrix<16x16xf16, "AOp">, %B : !gpu.mma_matrix<16x16xf16, "BOp">, %C : !gpu.mma_matrix<16x16xf16, "COp">) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixMulAdd {{%.*}}, {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, !spirv.NV.coopmatrix<16x16xf16, Subgroup> -> !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %D = gpu.subgroup_mma_compute %A, %B, %C : !gpu.mma_matrix<16x16xf16, "AOp">, !gpu.mma_matrix<16x16xf16, "BOp"> -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_constant_op - gpu.func @gpu_wmma_constant_op() kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - // CHECK: {{%.*}} = spirv.Constant - %cst = arith.constant 1.0 : f16 - // CHECK: {{%.*}} = spirv.CompositeConstruct {{%.*}} : (f16) -> !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %C = gpu.subgroup_mma_constant_matrix %cst : !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_elementwise_op_default - // CHECK-SAME: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - // CHECK-SAME: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - gpu.func @gpu_wmma_elementwise_op_default(%A : !gpu.mma_matrix<16x16xf16, "COp">, %B : !gpu.mma_matrix<16x16xf16, "COp">) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - // CHECK: {{%.*}} = spirv.FAdd {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %C = gpu.subgroup_mma_elementwise addf %A, %B : (!gpu.mma_matrix<16x16xf16, "COp">, !gpu.mma_matrix<16x16xf16, "COp">) -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: {{%.*}} = spirv.FNegate {{%.*}} : !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %D = gpu.subgroup_mma_elementwise negatef %C : (!gpu.mma_matrix<16x16xf16, "COp">) -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: {{%.*}} = spirv.FDiv {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %E = gpu.subgroup_mma_elementwise divf %D, %A : (!gpu.mma_matrix<16x16xf16, "COp">, !gpu.mma_matrix<16x16xf16, "COp">) -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: {{%.*}} = spirv.FConvert {{%.*}} : !spirv.NV.coopmatrix<16x16xf16, Subgroup> to !spirv.NV.coopmatrix<16x16xf32, Subgroup> - %F = gpu.subgroup_mma_elementwise extf %E : (!gpu.mma_matrix<16x16xf16, "COp">) -> !gpu.mma_matrix<16x16xf32, "COp"> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_elementwise_op_matrix_times_scalar - // CHECK-SAME: %[[A:.+]]: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - // CHECK-SAME: %[[S:.+]]: f16 - gpu.func @gpu_wmma_elementwise_op_matrix_times_scalar(%A : !gpu.mma_matrix<16x16xf16, "COp">, %scalar : f16) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - %B = gpu.subgroup_mma_constant_matrix %scalar : !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: %{{.+}} = spirv.MatrixTimesScalar %[[A]], %[[S]] : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, f16 - %C = gpu.subgroup_mma_elementwise mulf %A, %B : (!gpu.mma_matrix<16x16xf16, "COp">, !gpu.mma_matrix<16x16xf16, "COp">) -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: %{{.+}} = spirv.MatrixTimesScalar %[[A]], %[[S]] : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, f16 - %D = gpu.subgroup_mma_elementwise mulf %B, %A : (!gpu.mma_matrix<16x16xf16, "COp">, !gpu.mma_matrix<16x16xf16, "COp">) -> !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: spirv.Return - gpu.return - } - } -} - -// ----- - -module attributes { - gpu.container_module, - spirv.target_env = #spirv.target_env<#spirv.vce, #spirv.resource_limits<>>} { - gpu.module @kernels { - // CHECK-LABEL: spirv.func @gpu_wmma_elementwise_op_matrix_plus_scalar - // CHECK-SAME: %[[A:.+]]: !spirv.NV.coopmatrix<16x16xf16, Subgroup> - // CHECK-SAME: %[[S:.+]]: f16 - gpu.func @gpu_wmma_elementwise_op_matrix_plus_scalar(%A : !gpu.mma_matrix<16x16xf16, "COp">, %scalar : f16) kernel - attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { - // CHECK: %[[SM:.+]] = spirv.CompositeConstruct %[[S]] : (f16) -> !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %B = gpu.subgroup_mma_constant_matrix %scalar : !gpu.mma_matrix<16x16xf16, "COp"> - // CHECK: %{{.+}} = spirv.FAdd %[[A]], %[[SM]] : !spirv.NV.coopmatrix<16x16xf16, Subgroup> - %C = gpu.subgroup_mma_elementwise addf %A, %B : (!gpu.mma_matrix<16x16xf16, "COp">, !gpu.mma_matrix<16x16xf16, "COp">) -> !gpu.mma_matrix<16x16xf16, "COp"> - gpu.return - } - } -} diff --git a/mlir/test/Dialect/SPIRV/IR/cast-ops.mlir b/mlir/test/Dialect/SPIRV/IR/cast-ops.mlir index e289dbf28ad2..34d0109e6bb4 100644 --- a/mlir/test/Dialect/SPIRV/IR/cast-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/cast-ops.mlir @@ -146,14 +146,6 @@ func.func @convert_f_to_u.coopmatrix(%arg0 : !spirv.coopmatrix<8x16xf32, Subgrou // ----- -func.func @convert_f_to_u_NV.coopmatrix(%arg0 : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) { - // CHECK: {{%.*}} = spirv.ConvertFToU {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> to !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %0 = spirv.ConvertFToU %arg0 : !spirv.NV.coopmatrix<8x16xf32, Subgroup> to !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// ----- - //===----------------------------------------------------------------------===// // spirv.ConvertSToF //===----------------------------------------------------------------------===// @@ -238,14 +230,6 @@ func.func @f_convert_coop_matrix(%arg0 : !spirv.coopmatrix<8x16xf32, Subgroup, M // ----- -func.func @f_convert_coop_matrix_nv(%arg0 : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) { - // CHECK: {{%.*}} = spirv.FConvert {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> to !spirv.NV.coopmatrix<8x16xf64, Subgroup> - %0 = spirv.FConvert %arg0 : !spirv.NV.coopmatrix<8x16xf32, Subgroup> to !spirv.NV.coopmatrix<8x16xf64, Subgroup> - spirv.Return -} - -// ----- - func.func @f_convert_vector(%arg0 : f32) -> f32 { // expected-error @+1 {{expected the different bit widths for operand type and result type, but provided 'f32' and 'f32'}} %0 = spirv.FConvert %arg0 : f32 to f32 @@ -254,14 +238,6 @@ func.func @f_convert_vector(%arg0 : f32) -> f32 { // ----- -func.func @f_convert_coop_matrix_to_nv_coop_matrix(%arg0 : !spirv.coopmatrix<8x16xf32, Subgroup, MatrixAcc>) { - // expected-error @+1 {{incompatible operand and result types}} - %0 = spirv.FConvert %arg0 : !spirv.coopmatrix<8x16xf32, Subgroup, MatrixAcc> to !spirv.NV.coopmatrix<8x16xf64, Subgroup> - spirv.Return -} - -// ----- - //===----------------------------------------------------------------------===// // spirv.SConvert //===----------------------------------------------------------------------===// diff --git a/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir b/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir index b10677f0f5f9..3fc8dfb2767d 100644 --- a/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir @@ -32,13 +32,6 @@ func.func @composite_construct_coopmatrix_khr(%arg0 : f32) -> !spirv.coopmatrix< return %0: !spirv.coopmatrix<8x16xf32, Subgroup, MatrixA> } -// CHECK-LABEL: func @composite_construct_coopmatrix_nv -func.func @composite_construct_coopmatrix_nv(%arg0 : f32) -> !spirv.NV.coopmatrix<8x16xf32, Subgroup> { - // CHECK: spirv.CompositeConstruct {{%.*}} : (f32) -> !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %0 = spirv.CompositeConstruct %arg0 : (f32) -> !spirv.NV.coopmatrix<8x16xf32, Subgroup> - return %0: !spirv.NV.coopmatrix<8x16xf32, Subgroup> -} - // ----- func.func @composite_construct_invalid_result_type(%arg0: f32, %arg1: f32, %arg2 : f32) -> vector<3xf32> { @@ -75,22 +68,6 @@ func.func @composite_construct_khr_coopmatrix_incorrect_element_type(%arg0 : i32 // ----- -func.func @composite_construct_NV.coopmatrix_incorrect_operand_count(%arg0 : f32, %arg1 : f32) -> !spirv.NV.coopmatrix<8x16xf32, Subgroup> { - // expected-error @+1 {{has incorrect number of operands: expected 1, but provided 2}} - %0 = spirv.CompositeConstruct %arg0, %arg1 : (f32, f32) -> !spirv.NV.coopmatrix<8x16xf32, Subgroup> - return %0: !spirv.NV.coopmatrix<8x16xf32, Subgroup> -} - -// ----- - -func.func @composite_construct_NV.coopmatrix_incorrect_element_type(%arg0 : i32) -> !spirv.NV.coopmatrix<8x16xf32, Subgroup> { - // expected-error @+1 {{operand type mismatch: expected operand type 'f32', but provided 'i32'}} - %0 = spirv.CompositeConstruct %arg0 : (i32) -> !spirv.NV.coopmatrix<8x16xf32, Subgroup> - return %0: !spirv.NV.coopmatrix<8x16xf32, Subgroup> -} - -// ----- - func.func @composite_construct_array(%arg0: f32) -> !spirv.array<4xf32> { // expected-error @+1 {{expected to return a vector or cooperative matrix when the number of constituents is less than what the result needs}} %0 = spirv.CompositeConstruct %arg0 : (f32) -> !spirv.array<4xf32> @@ -143,14 +120,6 @@ func.func @composite_extract_vector(%arg0 : vector<4xf32>) -> f32 { // ----- -func.func @composite_extract_NV.coopmatrix(%arg0 : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) -> f32 { - // CHECK: {{%.*}} = spirv.CompositeExtract {{%.*}}[2 : i32] : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %0 = spirv.CompositeExtract %arg0[2 : i32] : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - return %0 : f32 -} - -// ----- - func.func @composite_extract_no_ssa_operand() -> () { // expected-error @+1 {{expected SSA operand}} %0 = spirv.CompositeExtract [4 : i32, 1 : i32] : !spirv.array<4x!spirv.array<4xf32>> @@ -271,14 +240,6 @@ func.func @composite_insert_struct(%arg0: !spirv.struct<(!spirv.array<4xf32>, f3 // ----- -func.func @composite_insert_NV.coopmatrix(%arg0: !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %arg1: i32) -> !spirv.NV.coopmatrix<8x16xi32, Subgroup> { - // CHECK: {{%.*}} = spirv.CompositeInsert {{%.*}}, {{%.*}}[5 : i32] : i32 into !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %0 = spirv.CompositeInsert %arg1, %arg0[5 : i32] : i32 into !spirv.NV.coopmatrix<8x16xi32, Subgroup> - return %0: !spirv.NV.coopmatrix<8x16xi32, Subgroup> -} - -// ----- - func.func @composite_insert_no_indices(%arg0: !spirv.array<4xf32>, %arg1: f32) -> !spirv.array<4xf32> { // expected-error @+1 {{expected at least one index}} %0 = spirv.CompositeInsert %arg1, %arg0[] : f32 into !spirv.array<4xf32> diff --git a/mlir/test/Dialect/SPIRV/IR/khr-cooperative-matrix-ops.mlir b/mlir/test/Dialect/SPIRV/IR/khr-cooperative-matrix-ops.mlir index 445ab8a48d3c..d3e1dbc229ef 100644 --- a/mlir/test/Dialect/SPIRV/IR/khr-cooperative-matrix-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/khr-cooperative-matrix-ops.mlir @@ -13,14 +13,6 @@ spirv.func @cooperative_matrix_length() -> i32 "None" { // ----- -spirv.func @cooperative_matrix_length_wrong_matrix() -> i32 "None" { - // expected-error @+1 {{'cooperative_matrix_type' failed to satisfy constraint: type attribute of any SPIR-V cooperative matrix type}} - %0 = spirv.KHR.CooperativeMatrixLength : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.ReturnValue %0 : i32 -} - -// ----- - // CHECK-LABEL: @cooperative_matrix_load spirv.func @cooperative_matrix_load(%ptr : !spirv.ptr, %stride : i32) "None" { // CHECK: {{%.*}} = spirv.KHR.CooperativeMatrixLoad {{%.*}}, {{%.*}}, : @@ -118,24 +110,6 @@ spirv.func @cooperative_matrix_load_missing_attr(%ptr : !spirv.ptr, %stride : i32) "None" { - // expected-error @+1 {{expected '<'}} - %0 = spirv.KHR.CooperativeMatrixLoad %ptr, %stride, : - !spirv.ptr, i32 -> !spirv.NV.coopmatrix<8x16xi32, Subgroup, MatrixA> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_load_bad_result(%ptr : !spirv.ptr, %stride : i32) "None" { - // expected-error @+1 {{op result #0 must be any SPIR-V cooperative matrix type}} - %0 = spirv.KHR.CooperativeMatrixLoad %ptr, %stride, : - !spirv.ptr, i32 -> !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// ----- - spirv.func @cooperative_matrix_load_bad_operad(%ptr : !spirv.ptr, %stride : i32) "None" { // expected-error @+1 {{op not compatible with memory operand 'MakePointerAvailable'}} %0 = spirv.KHR.CooperativeMatrixLoad %ptr, %stride, , : diff --git a/mlir/test/Dialect/SPIRV/IR/matrix-ops.mlir b/mlir/test/Dialect/SPIRV/IR/matrix-ops.mlir index f52666af280e..372fcc6e514b 100644 --- a/mlir/test/Dialect/SPIRV/IR/matrix-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/matrix-ops.mlir @@ -9,10 +9,10 @@ spirv.module Logical GLSL450 requires #spirv.vce { } // CHECK-LABEL: @matrix_times_scalar_2 - spirv.func @matrix_times_scalar_2(%arg0 : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, %arg1 : f16) -> !spirv.NV.coopmatrix<16x16xf16, Subgroup> "None" { - // CHECK: {{%.*}} = spirv.MatrixTimesScalar {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, f16 - %result = spirv.MatrixTimesScalar %arg0, %arg1 : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, f16 - spirv.ReturnValue %result : !spirv.NV.coopmatrix<16x16xf16, Subgroup> + spirv.func @matrix_times_scalar_2(%arg0 : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixA>, %arg1 : f16) -> !spirv.coopmatrix<16x16xf16, Subgroup, MatrixA> "None" { + // CHECK: {{%.*}} = spirv.MatrixTimesScalar {{%.*}}, {{%.*}} : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixA>, f16 + %result = spirv.MatrixTimesScalar %arg0, %arg1 : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixA>, f16 + spirv.ReturnValue %result : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixA> } // CHECK-LABEL: @matrix_transpose_1 diff --git a/mlir/test/Dialect/SPIRV/IR/nv-cooperative-matrix-ops.mlir b/mlir/test/Dialect/SPIRV/IR/nv-cooperative-matrix-ops.mlir deleted file mode 100644 index 43cbf61b60ef..000000000000 --- a/mlir/test/Dialect/SPIRV/IR/nv-cooperative-matrix-ops.mlir +++ /dev/null @@ -1,177 +0,0 @@ -// RUN: mlir-opt --split-input-file --verify-diagnostics %s | FileCheck %s - -//===----------------------------------------------------------------------===// -// NV.CooperativeMatrix -//===----------------------------------------------------------------------===// - -// CHECK-LABEL: @cooperative_matrix_load -spirv.func @cooperative_matrix_load(%ptr : !spirv.ptr, %stride : i32, %b : i1) "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, {{%.*}} : !spirv.ptr as !spirv.NV.coopmatrix<16x8xi32, Workgroup> - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b : !spirv.ptr as !spirv.NV.coopmatrix<16x8xi32, Workgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_load_memaccess -spirv.func @cooperative_matrix_load_memaccess(%ptr : !spirv.ptr, %stride : i32, %b : i1) "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, {{%.*}} ["Volatile"] : !spirv.ptr as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b ["Volatile"] : !spirv.ptr as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_load_diff_ptr_type -spirv.func @cooperative_matrix_load_diff_ptr_type(%ptr : !spirv.ptr, StorageBuffer>, %stride : i32, %b : i1) "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, {{%.*}} ["Volatile"] : !spirv.ptr, StorageBuffer> as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b ["Volatile"] : !spirv.ptr, StorageBuffer> as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_store -spirv.func @cooperative_matrix_store(%ptr : !spirv.ptr, %stride : i32, %m : !spirv.NV.coopmatrix<8x16xi32, Workgroup>, %b : i1) "None" { - // CHECK: spirv.NV.CooperativeMatrixStore {{%.*}}, {{%.*}}, {{%.*}} : !spirv.ptr, !spirv.NV.coopmatrix<8x16xi32, Workgroup> - spirv.NV.CooperativeMatrixStore %ptr, %m, %stride, %b : !spirv.ptr, !spirv.NV.coopmatrix<8x16xi32, Workgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_store_memaccess -spirv.func @cooperative_matrix_store_memaccess(%ptr : !spirv.ptr, %m : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %stride : i32, %b : i1) "None" { - // CHECK: spirv.NV.CooperativeMatrixStore {{%.*}}, {{%.*}}, {{%.*}} ["Volatile"] : !spirv.ptr, !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.NV.CooperativeMatrixStore %ptr, %m, %stride, %b ["Volatile"] : !spirv.ptr, !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_length -spirv.func @cooperative_matrix_length() -> i32 "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLength : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %0 = spirv.NV.CooperativeMatrixLength : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.ReturnValue %0 : i32 -} - -// CHECK-LABEL: @cooperative_matrix_muladd -spirv.func @cooperative_matrix_muladd(%a : !spirv.NV.coopmatrix<8x32xi8, Subgroup>, %b : !spirv.NV.coopmatrix<32x8xi8, Subgroup>, %c : !spirv.NV.coopmatrix<8x8xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixMulAdd {{%.*}}, {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x32xi8, Subgroup>, !spirv.NV.coopmatrix<32x8xi8, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - %r = spirv.NV.CooperativeMatrixMulAdd %a, %b, %c : !spirv.NV.coopmatrix<8x32xi8, Subgroup>, !spirv.NV.coopmatrix<32x8xi8, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_add -spirv.func @cooperative_matrix_add(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.IAdd {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.IAdd %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_sub -spirv.func @cooperative_matrix_sub(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.ISub {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.ISub %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_sdiv -spirv.func @cooperative_matrix_sdiv(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.SDiv {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.SDiv %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_udiv -spirv.func @cooperative_matrix_udiv(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.UDiv {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.UDiv %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_fadd -spirv.func @cooperative_matrix_fadd(%a : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.FAdd {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %r = spirv.FAdd %a, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_fsub -spirv.func @cooperative_matrix_fsub(%a : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.FSub {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %r = spirv.FSub %a, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - spirv.Return -} - -// CHECK-LABEL: @cooperative_matrix_fdiv -spirv.func @cooperative_matrix_fdiv(%a : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.FDiv {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %r = spirv.FDiv %a, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - spirv.Return -} - -// ----- - -// CHECK-LABEL: @cooperative_matrix_access_chain -spirv.func @cooperative_matrix_access_chain(%a : !spirv.ptr, Function>) -> !spirv.ptr "None" { - %0 = spirv.Constant 0: i32 - // CHECK: {{%.*}} = spirv.AccessChain {{%.*}}[{{%.*}}] : !spirv.ptr, Function>, i32 - %1 = spirv.AccessChain %a[%0] : !spirv.ptr, Function>, i32 - spirv.ReturnValue %1 : !spirv.ptr -} - -// ----- - -spirv.func @cooperative_matrix_muladd(%a : !spirv.NV.coopmatrix<16x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<16x8xi32, Subgroup>, %c : !spirv.NV.coopmatrix<8x8xi32, Subgroup>) "None" { - // expected-error @+1 {{'spirv.NV.CooperativeMatrixMulAdd' op matrix size must match}} - %r = spirv.NV.CooperativeMatrixMulAdd %a, %b, %c : !spirv.NV.coopmatrix<16x16xi32, Subgroup>, !spirv.NV.coopmatrix<16x8xi32, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_muladd(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x8xi32, Subgroup>, %c : !spirv.NV.coopmatrix<8x8xi32, Subgroup>) "None" { - // expected-error @+1 {{'spirv.NV.CooperativeMatrixMulAdd' op matrix size must match}} - %r = spirv.NV.CooperativeMatrixMulAdd %a, %b, %c : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, !spirv.NV.coopmatrix<8x8xi32, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_muladd(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<16x8xi32, Workgroup>, %c : !spirv.NV.coopmatrix<8x8xi32, Subgroup>) "None" { - // expected-error @+1 {{'spirv.NV.CooperativeMatrixMulAdd' op matrix scope must match}} - %r = spirv.NV.CooperativeMatrixMulAdd %a, %b, %c : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, !spirv.NV.coopmatrix<16x8xi32, Workgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_muladd(%a : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, %b : !spirv.NV.coopmatrix<16x8xi32, Subgroup>, %c : !spirv.NV.coopmatrix<8x8xi32, Subgroup>) "None" { - // expected-error @+1 {{matrix A and B non-integer element types must match}} - %r = spirv.NV.CooperativeMatrixMulAdd %a, %b, %c : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, !spirv.NV.coopmatrix<16x8xi32, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_muladd(%a : !spirv.NV.coopmatrix<8x16xui8, Subgroup>, %b : !spirv.NV.coopmatrix<16x8xsi32, Subgroup>, %c : !spirv.NV.coopmatrix<8x8xi32, Subgroup>) "None" { - // expected-error @+1 {{matrix A and B integer element types must be the same bit width}} - %r = spirv.NV.CooperativeMatrixMulAdd %a, %b, %c : !spirv.NV.coopmatrix<8x16xui8, Subgroup>, !spirv.NV.coopmatrix<16x8xsi32, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_load_memaccess(%ptr : !spirv.ptr, StorageBuffer>, %stride : i32, %b : i1) "None" { - // expected-error @+1 {{Pointer must point to a scalar or vector type}} - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b : !spirv.ptr, StorageBuffer> as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_load_memaccess(%ptr : !spirv.ptr, %stride : i32, %b : i1) "None" { - // expected-error @+1 {{Pointer storage class must be Workgroup, StorageBuffer or PhysicalStorageBufferEXT}} - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b : !spirv.ptr as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return -} - -// ----- - -spirv.func @cooperative_matrix_length_wrong_matrix() -> i32 "None" { - // expected-error @+1 {{'spirv.NV.CooperativeMatrixLength' op type attribute must be a '!spirv.NV.coopmatrix'}} - %0 = spirv.NV.CooperativeMatrixLength : !spirv.coopmatrix<8x16xi32, Subgroup, MatrixB> - spirv.ReturnValue %0 : i32 -} diff --git a/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir b/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir index 77b605050e14..6e4c8688666a 100644 --- a/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir @@ -810,7 +810,7 @@ spirv.module Logical GLSL450 { } //===----------------------------------------------------------------------===// -// spirv.SpecConstantComposite (spirv.NV.coopmatrix) +// spirv.SpecConstantComposite (spirv.KHR.coopmatrix) //===----------------------------------------------------------------------===// // ----- @@ -818,7 +818,7 @@ spirv.module Logical GLSL450 { spirv.module Logical GLSL450 { spirv.SpecConstant @sc1 = 1.5 : f32 // expected-error @+1 {{unsupported composite type}} - spirv.SpecConstantComposite @scc (@sc1) : !spirv.NV.coopmatrix<8x16xf32, Device> + spirv.SpecConstantComposite @scc (@sc1) : !spirv.coopmatrix<8x16xf32, Device, MatrixA> } //===----------------------------------------------------------------------===// diff --git a/mlir/test/Dialect/SPIRV/IR/types.mlir b/mlir/test/Dialect/SPIRV/IR/types.mlir index e10a6fc77e85..05ab91b6db6b 100644 --- a/mlir/test/Dialect/SPIRV/IR/types.mlir +++ b/mlir/test/Dialect/SPIRV/IR/types.mlir @@ -479,25 +479,6 @@ func.func private @use_not_integer(!spirv.coopmatrix<8x8xi32, Subgroup, Subgroup // ----- -//===----------------------------------------------------------------------===// -// NV.CooperativeMatrix -//===----------------------------------------------------------------------===// - -// CHECK: func private @nv_coop_matrix_type(!spirv.NV.coopmatrix<8x16xi32, Subgroup>, !spirv.NV.coopmatrix<8x8xf32, Workgroup>) -func.func private @nv_coop_matrix_type(!spirv.NV.coopmatrix<8x16xi32, Subgroup>, !spirv.NV.coopmatrix<8x8xf32, Workgroup>) -> () - -// ----- - -// expected-error @+1 {{expected ','}} -func.func private @missing_scope(!spirv.NV.coopmatrix<8x16xi32>) -> () - -// ----- - -// expected-error @+1 {{expected rows and columns size}} -func.func private @missing_count(!spirv.NV.coopmatrix<8xi32, Subgroup>) -> () - -// ----- - //===----------------------------------------------------------------------===// // Matrix //===----------------------------------------------------------------------===// diff --git a/mlir/test/Target/SPIRV/matrix.mlir b/mlir/test/Target/SPIRV/matrix.mlir index af8f41a30d24..b52c3f4aa2f1 100644 --- a/mlir/test/Target/SPIRV/matrix.mlir +++ b/mlir/test/Target/SPIRV/matrix.mlir @@ -23,10 +23,10 @@ spirv.module Logical GLSL450 requires #spirv.vce { } // CHECK-LABEL: @matrix_times_scalar_3 - spirv.func @matrix_times_scalar_3(%arg0 : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, %arg1 : f16) -> !spirv.NV.coopmatrix<16x16xf16, Subgroup> "None" { - // CHECK: {{%.*}} = spirv.MatrixTimesScalar {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, f16 - %result = spirv.MatrixTimesScalar %arg0, %arg1 : !spirv.NV.coopmatrix<16x16xf16, Subgroup>, f16 - spirv.ReturnValue %result : !spirv.NV.coopmatrix<16x16xf16, Subgroup> + spirv.func @matrix_times_scalar_3(%arg0 : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixAcc>, %arg1 : f16) -> !spirv.coopmatrix<16x16xf16, Subgroup, MatrixAcc> "None" { + // CHECK: {{%.*}} = spirv.MatrixTimesScalar {{%.*}}, {{%.*}} : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixAcc>, f16 + %result = spirv.MatrixTimesScalar %arg0, %arg1 : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixAcc>, f16 + spirv.ReturnValue %result : !spirv.coopmatrix<16x16xf16, Subgroup, MatrixAcc> } // CHECK-LABEL: @matrix_transpose_1 diff --git a/mlir/test/Target/SPIRV/nv-cooperative-matrix-ops.mlir b/mlir/test/Target/SPIRV/nv-cooperative-matrix-ops.mlir deleted file mode 100644 index 2eec99f72691..000000000000 --- a/mlir/test/Target/SPIRV/nv-cooperative-matrix-ops.mlir +++ /dev/null @@ -1,102 +0,0 @@ -// RUN: mlir-translate -no-implicit-module -test-spirv-roundtrip -split-input-file %s | FileCheck %s - -spirv.module Logical GLSL450 requires #spirv.vce { - // CHECK-LABEL: @cooperative_matrix_load - spirv.func @cooperative_matrix_load(%ptr : !spirv.ptr, %stride : i32, %b : i1) "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, {{%.*}} : !spirv.ptr as !spirv.NV.coopmatrix<16x8xi32, Workgroup> - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b : !spirv.ptr as !spirv.NV.coopmatrix<16x8xi32, Workgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_load_memaccess - spirv.func @cooperative_matrix_load_memaccess(%ptr : !spirv.ptr, %stride : i32, %b : i1) "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, {{%.*}} ["Volatile"] : !spirv.ptr as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b ["Volatile"] : !spirv.ptr as !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_store - spirv.func @cooperative_matrix_store(%ptr : !spirv.ptr, %stride : i32, %m : !spirv.NV.coopmatrix<16x8xi32, Workgroup>, %b : i1) "None" { - // CHECK: spirv.NV.CooperativeMatrixStore {{%.*}}, {{%.*}}, {{%.*}} : !spirv.ptr, !spirv.NV.coopmatrix<16x8xi32, Workgroup> - spirv.NV.CooperativeMatrixStore %ptr, %m, %stride, %b : !spirv.ptr, !spirv.NV.coopmatrix<16x8xi32, Workgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_store_memaccess - spirv.func @cooperative_matrix_store_memaccess(%ptr : !spirv.ptr, %m : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %stride : i32, %b : i1) "None" { - // CHECK: spirv.NV.CooperativeMatrixStore {{%.*}}, {{%.*}}, {{%.*}} ["Volatile"] : !spirv.ptr, !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.NV.CooperativeMatrixStore %ptr, %m, %stride, %b ["Volatile"] : !spirv.ptr, !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_length - spirv.func @cooperative_matrix_length() -> i32 "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLength : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %0 = spirv.NV.CooperativeMatrixLength : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.ReturnValue %0 : i32 - } - - // CHECK-LABEL: @cooperative_matrix_muladd - spirv.func @cooperative_matrix_muladd(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<16x8xi32, Subgroup>, %c : !spirv.NV.coopmatrix<8x8xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixMulAdd {{%.*}}, {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, !spirv.NV.coopmatrix<16x8xi32, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - %r = spirv.NV.CooperativeMatrixMulAdd %a, %b, %c : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, !spirv.NV.coopmatrix<16x8xi32, Subgroup> -> !spirv.NV.coopmatrix<8x8xi32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_add - spirv.func @cooperative_matrix_add(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.IAdd {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.IAdd %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_sub - spirv.func @cooperative_matrix_sub(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.ISub {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.ISub %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_sdiv - spirv.func @cooperative_matrix_sdiv(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.SDiv {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.SDiv %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_udiv - spirv.func @cooperative_matrix_udiv(%a : !spirv.NV.coopmatrix<8x16xi32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.UDiv {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - %r = spirv.UDiv %a, %b : !spirv.NV.coopmatrix<8x16xi32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_fadd - spirv.func @cooperative_matrix_fadd(%a : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.FAdd {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %r = spirv.FAdd %a, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_fsub - spirv.func @cooperative_matrix_fsub(%a : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.FSub {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %r = spirv.FSub %a, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_fdiv - spirv.func @cooperative_matrix_fdiv(%a : !spirv.NV.coopmatrix<8x16xf32, Subgroup>, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup>) "None" { - // CHECK: {{%.*}} = spirv.FDiv {{%.*}}, {{%.*}} : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - %r = spirv.FDiv %a, %b : !spirv.NV.coopmatrix<8x16xf32, Subgroup> - spirv.Return - } - - // CHECK-LABEL: @cooperative_matrix_access_chain - spirv.func @cooperative_matrix_access_chain(%a : !spirv.ptr, Function>) -> !spirv.ptr "None" { - %0 = spirv.Constant 0: i32 - // CHECK: {{%.*}} = spirv.AccessChain {{%.*}}[{{%.*}}] : !spirv.ptr, Function>, i32 - %1 = spirv.AccessChain %a[%0] : !spirv.ptr, Function>, i32 - spirv.ReturnValue %1 : !spirv.ptr - } -} -- GitLab From 6eab9dd7f01e6cad9f1a93bd52e4c6e7b4c3c1fa Mon Sep 17 00:00:00 2001 From: Alex MacLean Date: Mon, 8 Jan 2024 15:17:00 -0800 Subject: [PATCH 121/652] [NVPTX] remove incorrect NVPTX intrinsic transformations (#76870) `nvvm_fabs_f` `nvvm_fabs_ftz_f` Unfortunately, llvm fabs is not equivalent to these intrinsics since llvm fabs is defined to only set the sign bit to zero while these can also flush subnormal inputs and modify NaNs. `nvvm_round_d` `nvvm_round_f` `nvvm_round_ftz_f` llvm.nvvm.round uses RNI, while llvm.round codegens to RZI. LLVM defines llvm.round to use the same rounding as libm `round[f]()`, which is not necessary the same as how we define llvm.nvvm.round. `nvvm_sqrt_rn_f` `nvvm_sqrt_rn_ftz_f` sqrt may be lowered to a less precise version of sqrt, such as sqrt.approx in NVPTX depending on factors such as the value of -nvptx-prec-sqrtf32. These intrinsics should always become the corresponding NVPTX instructions. `nvvm_add_rn_d` `nvvm_add_rn_f` `nvvm_add_rn_ftz_f` `nvvm_mul_rn_d` `nvvm_mul_rn_f` `nvvm_mul_rn_ftz_f` These nvvm intrinsics have an explicitly specified rounding mode (.rn). They should always be lowered to a PTX instruction with the same explicit rounding mode. Converting to fmul and fadd instructions result in the PTX instructions without rounding modes specified. This can cause issue because: > An add [or mul] instruction with no rounding modifier defaults to round-to-nearest-even and may be optimized aggressively by the code optimizer. In particular, mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. `nvvm_div_rn_f` `nvvm_div_rn_ftz_f` `nvvm_rcp_rn_f` `nvvm_rcp_rn_ftz_f` fdiv may be lowered to a less precise version of div, such as div.full in NVPTX depending on factors such as the value of -nvptx-prec-divf32. These intrinsics should always become the corresponding NVPTX instructions. --- .../Target/NVPTX/NVPTXTargetTransformInfo.cpp | 34 ------------- .../InstCombine/NVPTX/nvvm-intrins.ll | 48 +++++++------------ 2 files changed, 17 insertions(+), 65 deletions(-) diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp index c73721da46e3..7aa63f9fc0c9 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp @@ -180,10 +180,6 @@ static Instruction *simplifyNvvmIntrinsic(IntrinsicInst *II, InstCombiner &IC) { return {Intrinsic::ceil, FTZ_MustBeOn}; case Intrinsic::nvvm_fabs_d: return {Intrinsic::fabs, FTZ_Any}; - case Intrinsic::nvvm_fabs_f: - return {Intrinsic::fabs, FTZ_MustBeOff}; - case Intrinsic::nvvm_fabs_ftz_f: - return {Intrinsic::fabs, FTZ_MustBeOn}; case Intrinsic::nvvm_floor_d: return {Intrinsic::floor, FTZ_Any}; case Intrinsic::nvvm_floor_f: @@ -264,12 +260,6 @@ static Instruction *simplifyNvvmIntrinsic(IntrinsicInst *II, InstCombiner &IC) { return {Intrinsic::minimum, FTZ_MustBeOff, true}; case Intrinsic::nvvm_fmin_ftz_nan_f16x2: return {Intrinsic::minimum, FTZ_MustBeOn, true}; - case Intrinsic::nvvm_round_d: - return {Intrinsic::round, FTZ_Any}; - case Intrinsic::nvvm_round_f: - return {Intrinsic::round, FTZ_MustBeOff}; - case Intrinsic::nvvm_round_ftz_f: - return {Intrinsic::round, FTZ_MustBeOn}; case Intrinsic::nvvm_sqrt_rn_d: return {Intrinsic::sqrt, FTZ_Any}; case Intrinsic::nvvm_sqrt_f: @@ -278,10 +268,6 @@ static Instruction *simplifyNvvmIntrinsic(IntrinsicInst *II, InstCombiner &IC) { // the ftz-ness of the surrounding code. sqrt_rn_f and sqrt_rn_ftz_f are // the versions with explicit ftz-ness. return {Intrinsic::sqrt, FTZ_Any}; - case Intrinsic::nvvm_sqrt_rn_f: - return {Intrinsic::sqrt, FTZ_MustBeOff}; - case Intrinsic::nvvm_sqrt_rn_ftz_f: - return {Intrinsic::sqrt, FTZ_MustBeOn}; case Intrinsic::nvvm_trunc_d: return {Intrinsic::trunc, FTZ_Any}; case Intrinsic::nvvm_trunc_f: @@ -316,24 +302,8 @@ static Instruction *simplifyNvvmIntrinsic(IntrinsicInst *II, InstCombiner &IC) { return {Instruction::UIToFP}; // NVVM intrinsics that map to LLVM binary ops. - case Intrinsic::nvvm_add_rn_d: - return {Instruction::FAdd, FTZ_Any}; - case Intrinsic::nvvm_add_rn_f: - return {Instruction::FAdd, FTZ_MustBeOff}; - case Intrinsic::nvvm_add_rn_ftz_f: - return {Instruction::FAdd, FTZ_MustBeOn}; - case Intrinsic::nvvm_mul_rn_d: - return {Instruction::FMul, FTZ_Any}; - case Intrinsic::nvvm_mul_rn_f: - return {Instruction::FMul, FTZ_MustBeOff}; - case Intrinsic::nvvm_mul_rn_ftz_f: - return {Instruction::FMul, FTZ_MustBeOn}; case Intrinsic::nvvm_div_rn_d: return {Instruction::FDiv, FTZ_Any}; - case Intrinsic::nvvm_div_rn_f: - return {Instruction::FDiv, FTZ_MustBeOff}; - case Intrinsic::nvvm_div_rn_ftz_f: - return {Instruction::FDiv, FTZ_MustBeOn}; // The remainder of cases are NVVM intrinsics that map to LLVM idioms, but // need special handling. @@ -342,10 +312,6 @@ static Instruction *simplifyNvvmIntrinsic(IntrinsicInst *II, InstCombiner &IC) { // as well. case Intrinsic::nvvm_rcp_rn_d: return {SPC_Reciprocal, FTZ_Any}; - case Intrinsic::nvvm_rcp_rn_f: - return {SPC_Reciprocal, FTZ_MustBeOff}; - case Intrinsic::nvvm_rcp_rn_ftz_f: - return {SPC_Reciprocal, FTZ_MustBeOn}; // We do not currently simplify intrinsics that give an approximate // answer. These include: diff --git a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll index ca1a5237f905..633aa43c4fc8 100644 --- a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll +++ b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll @@ -49,15 +49,13 @@ define double @fabs_double(double %a) #0 { } ; CHECK-LABEL: @fabs_float define float @fabs_float(float %a) #0 { -; NOFTZ: call float @llvm.fabs.f32 -; FTZ: call float @llvm.nvvm.fabs.f +; CHECK: call float @llvm.nvvm.fabs.f %ret = call float @llvm.nvvm.fabs.f(float %a) ret float %ret } ; CHECK-LABEL: @fabs_float_ftz define float @fabs_float_ftz(float %a) #0 { -; NOFTZ: call float @llvm.nvvm.fabs.ftz.f -; FTZ: call float @llvm.fabs.f32 +; CHECK: call float @llvm.nvvm.fabs.ftz.f %ret = call float @llvm.nvvm.fabs.ftz.f(float %a) ret float %ret } @@ -148,21 +146,19 @@ define float @fmin_float_ftz(float %a, float %b) #0 { ; CHECK-LABEL: @round_double define double @round_double(double %a) #0 { -; CHECK: call double @llvm.round.f64 +; CHECK: call double @llvm.nvvm.round.d %ret = call double @llvm.nvvm.round.d(double %a) ret double %ret } ; CHECK-LABEL: @round_float define float @round_float(float %a) #0 { -; NOFTZ: call float @llvm.round.f32 -; FTZ: call float @llvm.nvvm.round.f +; CHECK: call float @llvm.nvvm.round.f %ret = call float @llvm.nvvm.round.f(float %a) ret float %ret } ; CHECK-LABEL: @round_float_ftz define float @round_float_ftz(float %a) #0 { -; NOFTZ: call float @llvm.nvvm.round.ftz.f -; FTZ: call float @llvm.round.f32 +; CHECK: call float @llvm.nvvm.round.ftz.f %ret = call float @llvm.nvvm.round.ftz.f(float %a) ret float %ret } @@ -292,42 +288,38 @@ define float @test_ull2f(i64 %a) #0 { ; CHECK-LABEL: @test_add_rn_d define double @test_add_rn_d(double %a, double %b) #0 { -; CHECK: fadd +; CHECK: call double @llvm.nvvm.add.rn.d %ret = call double @llvm.nvvm.add.rn.d(double %a, double %b) ret double %ret } ; CHECK-LABEL: @test_add_rn_f define float @test_add_rn_f(float %a, float %b) #0 { -; NOFTZ: fadd -; FTZ: call float @llvm.nvvm.add.rn.f +; CHECK: call float @llvm.nvvm.add.rn.f %ret = call float @llvm.nvvm.add.rn.f(float %a, float %b) ret float %ret } ; CHECK-LABEL: @test_add_rn_f_ftz define float @test_add_rn_f_ftz(float %a, float %b) #0 { -; NOFTZ: call float @llvm.nvvm.add.rn.f -; FTZ: fadd +; CHECK: call float @llvm.nvvm.add.rn.ftz.f(float %a, float %b) %ret = call float @llvm.nvvm.add.rn.ftz.f(float %a, float %b) ret float %ret } ; CHECK-LABEL: @test_mul_rn_d define double @test_mul_rn_d(double %a, double %b) #0 { -; CHECK: fmul +; CHECK: call double @llvm.nvvm.mul.rn.d %ret = call double @llvm.nvvm.mul.rn.d(double %a, double %b) ret double %ret } ; CHECK-LABEL: @test_mul_rn_f define float @test_mul_rn_f(float %a, float %b) #0 { -; NOFTZ: fmul -; FTZ: call float @llvm.nvvm.mul.rn.f +; CHECK: call float @llvm.nvvm.mul.rn.f %ret = call float @llvm.nvvm.mul.rn.f(float %a, float %b) ret float %ret } ; CHECK-LABEL: @test_mul_rn_f_ftz define float @test_mul_rn_f_ftz(float %a, float %b) #0 { -; NOFTZ: call float @llvm.nvvm.mul.rn.f -; FTZ: fmul +; CHECK: call float @llvm.nvvm.mul.rn.ftz.f(float %a, float %b) %ret = call float @llvm.nvvm.mul.rn.ftz.f(float %a, float %b) ret float %ret } @@ -340,15 +332,13 @@ define double @test_div_rn_d(double %a, double %b) #0 { } ; CHECK-LABEL: @test_div_rn_f define float @test_div_rn_f(float %a, float %b) #0 { -; NOFTZ: fdiv -; FTZ: call float @llvm.nvvm.div.rn.f +; CHECK: call float @llvm.nvvm.div.rn.f %ret = call float @llvm.nvvm.div.rn.f(float %a, float %b) ret float %ret } ; CHECK-LABEL: @test_div_rn_f_ftz define float @test_div_rn_f_ftz(float %a, float %b) #0 { -; NOFTZ: call float @llvm.nvvm.div.rn.f -; FTZ: fdiv +; CHECK: call float @llvm.nvvm.div.rn.ftz.f(float %a, float %b) %ret = call float @llvm.nvvm.div.rn.ftz.f(float %a, float %b) ret float %ret } @@ -357,15 +347,13 @@ define float @test_div_rn_f_ftz(float %a, float %b) #0 { ; CHECK-LABEL: @test_rcp_rn_f define float @test_rcp_rn_f(float %a) #0 { -; NOFTZ: fdiv float 1.0{{.*}} %a -; FTZ: call float @llvm.nvvm.rcp.rn.f +; CHECK: call float @llvm.nvvm.rcp.rn.f %ret = call float @llvm.nvvm.rcp.rn.f(float %a) ret float %ret } ; CHECK-LABEL: @test_rcp_rn_f_ftz define float @test_rcp_rn_f_ftz(float %a) #0 { -; NOFTZ: call float @llvm.nvvm.rcp.rn.f -; FTZ: fdiv float 1.0{{.*}} %a +; CHECK: call float @llvm.nvvm.rcp.rn.ftz.f(float %a) %ret = call float @llvm.nvvm.rcp.rn.ftz.f(float %a) ret float %ret } @@ -385,15 +373,13 @@ define float @test_sqrt_f(float %a) #0 { } ; CHECK-LABEL: @test_sqrt_rn_f define float @test_sqrt_rn_f(float %a) #0 { -; NOFTZ: call float @llvm.sqrt.f32(float %a) -; FTZ: call float @llvm.nvvm.sqrt.rn.f +; CHECK: call float @llvm.nvvm.sqrt.rn.f %ret = call float @llvm.nvvm.sqrt.rn.f(float %a) ret float %ret } ; CHECK-LABEL: @test_sqrt_rn_f_ftz define float @test_sqrt_rn_f_ftz(float %a) #0 { -; NOFTZ: call float @llvm.nvvm.sqrt.rn.f -; FTZ: call float @llvm.sqrt.f32(float %a) +; CHECK: call float @llvm.nvvm.sqrt.rn.ftz.f(float %a) %ret = call float @llvm.nvvm.sqrt.rn.ftz.f(float %a) ret float %ret } -- GitLab From f5145f4dc819d73ff8bebcfba3779533b150884e Mon Sep 17 00:00:00 2001 From: Krystian Stasiowski Date: Mon, 8 Jan 2024 18:21:16 -0500 Subject: [PATCH 122/652] [Clang][NFC] Fix out-of-bounds access (#77193) The changes to tablegen made by https://github.com/llvm/llvm-project/pull/76825 result in `StmtClass::lastStmtConstant` changing from `StmtClass::WhileStmtClass` to `StmtClass::GCCAsmStmtClass`. Since `CFG::BuildOptions::alwaysAdd` is never called with a `WhileStmt`, this has flown under the radar until now. Once such test in which an out-of-bounds access occurs is `test/Sema/inline-asm-validate.c`, among many others. --- clang/include/clang/Analysis/CFG.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Analysis/CFG.h b/clang/include/clang/Analysis/CFG.h index 67383bb316d3..9f776ca6cc26 100644 --- a/clang/include/clang/Analysis/CFG.h +++ b/clang/include/clang/Analysis/CFG.h @@ -1215,7 +1215,9 @@ public: //===--------------------------------------------------------------------===// class BuildOptions { - std::bitset alwaysAddMask; + // Stmt::lastStmtConstant has the same value as the last Stmt kind, + // so make sure we add one to account for this! + std::bitset alwaysAddMask; public: using ForcedBlkExprs = llvm::DenseMap; -- GitLab From faa326de97bf6119dcc42806b07f3523c521ae96 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Jan 2024 15:23:26 -0800 Subject: [PATCH 123/652] [RISCV] Add branch+c.mv macrofusion for sifive-p450. (#76169) sifive-p450 supports a very restricted version of the short forward branch optimization from the sifive-7-series. For sifive-p450, a branch over a single c.mv can be macrofused as a conditional move operation. Due to encoding restrictions on c.mv, we can't conditionally move from X0. That would require c.li instead. --- .../Target/RISCV/RISCVExpandPseudoInsts.cpp | 4 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 6 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 + llvm/lib/Target/RISCV/RISCVInstrInfo.td | 20 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 3 +- llvm/lib/Target/RISCV/RISCVSubtarget.h | 7 + llvm/test/CodeGen/RISCV/cmov-branch-opt.ll | 461 ++++++++++++++++++ 8 files changed, 505 insertions(+), 8 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/cmov-branch-opt.ll diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp index 24a13f93af88..a39f0671a6dc 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -109,6 +109,7 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB, return expandRV32ZdinxStore(MBB, MBBI); case RISCV::PseudoRV32ZdinxLD: return expandRV32ZdinxLoad(MBB, MBBI); + case RISCV::PseudoCCMOVGPRNoX0: case RISCV::PseudoCCMOVGPR: case RISCV::PseudoCCADD: case RISCV::PseudoCCSUB: @@ -191,7 +192,8 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB, Register DestReg = MI.getOperand(0).getReg(); assert(MI.getOperand(4).getReg() == DestReg); - if (MI.getOpcode() == RISCV::PseudoCCMOVGPR) { + if (MI.getOpcode() == RISCV::PseudoCCMOVGPR || + MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) { // Add MV. BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg) .add(MI.getOperand(5)) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 59b202606dad..bb7a3291085d 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1021,6 +1021,12 @@ def TuneShortForwardBranchOpt def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; +def TuneConditionalCompressedMoveFusion + : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion", + "true", "Enable branch+c.mv fusion">; +def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; +def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; + def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors", [TuneNoDefaultUnroll, diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 79c16cf4c4c3..135b41c7a085 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -6920,7 +6920,7 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG, MVT VT = N->getSimpleValueType(0); SDLoc DL(N); - if (!Subtarget.hasShortForwardBranchOpt()) { + if (!Subtarget.hasConditionalMoveFusion()) { // (select c, -1, y) -> -c | y if (isAllOnesConstant(TrueV)) { SDValue Neg = DAG.getNegative(CondV, DL, VT); @@ -7084,7 +7084,7 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { // (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c)) // Unless we have the short forward branch optimization. - if (!Subtarget.hasShortForwardBranchOpt()) + if (!Subtarget.hasConditionalMoveFusion()) return DAG.getNode( ISD::OR, DL, VT, DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV), @@ -12209,7 +12209,7 @@ static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, if (VT.isVector()) return SDValue(); - if (!Subtarget.hasShortForwardBranchOpt()) { + if (!Subtarget.hasConditionalMoveFusion()) { // (select cond, x, (and x, c)) has custom lowering with Zicond. if ((!Subtarget.hasStdExtZicond() && !Subtarget.hasVendorXVentanaCondOps()) || @@ -14440,7 +14440,7 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, if (SDValue V = useInversedSetcc(N, DAG, Subtarget)) return V; - if (Subtarget.hasShortForwardBranchOpt()) + if (Subtarget.hasConditionalMoveFusion()) return SDValue(); SDValue TrueVal = N->getOperand(1); @@ -15178,7 +15178,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0), {LHS, RHS, CC, TrueV, FalseV}); - if (!Subtarget.hasShortForwardBranchOpt()) { + if (!Subtarget.hasConditionalMoveFusion()) { // (select c, -1, y) -> -c | y if (isAllOnesConstant(TrueV)) { SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, CCVal); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 7f6a045a7d04..a24e8b2d18cb 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2650,6 +2650,7 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI, case RISCV::TH_MULSH: // Operands 2 and 3 are commutable. return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3); + case RISCV::PseudoCCMOVGPRNoX0: case RISCV::PseudoCCMOVGPR: // Operands 4 and 5 are commutable. return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 4, 5); @@ -2806,6 +2807,7 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1, OpIdx2); } + case RISCV::PseudoCCMOVGPRNoX0: case RISCV::PseudoCCMOVGPR: { // CCMOV can be commuted by inverting the condition. auto CC = static_cast(MI.getOperand(3).getImm()); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 2f4744529469..e274e9f3898f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1371,6 +1371,24 @@ def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst), ReadSFBALU, ReadSFBALU]>; } +// This should always expand to a branch+c.mv so the size is 6 or 4 if the +// branch is compressible. +let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt], + Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in { +// This instruction moves $truev to $dst when the condition is true. It will +// be expanded to control flow in RISCVExpandPseudoInsts. +// We use GPRNoX0 because c.mv cannot encode X0. +def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPRNoX0:$falsev, GPRNoX0:$truev), + [(set GPRNoX0:$dst, + (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), + (XLenVT GPR:$rhs), + cond, (XLenVT GPRNoX0:$truev), + (XLenVT GPRNoX0:$falsev)))]>, + Sched<[]>; +} + // Conditional binops, that updates update $dst to (op rs1, rs2) when condition // is true. Returns $falsev otherwise. Selected by optimizeSelect. // TODO: Can we use DefaultOperands on the regular binop to accomplish this more @@ -1519,7 +1537,7 @@ multiclass SelectCC_GPR_rrirr { (IntCCtoRISCVCC $cc), valty:$truev, valty:$falsev)>; } -let Predicates = [NoShortForwardBranchOpt] in +let Predicates = [NoConditionalMoveFusion] in defm Select_GPR : SelectCC_GPR_rrirr; class SelectCompressOpt diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index ba8996e710ed..52800f086129 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -232,7 +232,8 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel, FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs, - FeatureStdExtZfhmin]>; + FeatureStdExtZfhmin], + [TuneConditionalCompressedMoveFusion]>; def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 26320b05d9be..2ba93764facd 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -150,6 +150,13 @@ public: bool hasHalfFPLoadStoreMove() const { return HasStdExtZfhmin || HasStdExtZfbfmin; } + + bool hasConditionalMoveFusion() const { + // Do we support fusing a branch+mv or branch+c.mv as a conditional move. + return (hasConditionalCompressedMoveFusion() && hasStdExtCOrZca()) || + hasShortForwardBranchOpt(); + } + bool is64Bit() const { return IsRV64; } MVT getXLenVT() const { return is64Bit() ? MVT::i64 : MVT::i32; diff --git a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll new file mode 100644 index 000000000000..6ad529ea477c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll @@ -0,0 +1,461 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=NOCMOV %s +; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=CMOV,CMOV-NOZICOND %s +; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+experimental-zicond -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=CMOV,CMOV-ZICOND %s +; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s +; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+c -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s +; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+experimental-zicond -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-ZICOND %s + +; The conditional move optimization in sifive-p450 requires that only a +; single c.mv instruction appears in the branch shadow. + +; The sifive-7-series can predicate an xor. + +define signext i32 @test1(i32 signext %x, i32 signext %y, i32 signext %z) { +; NOCMOV-LABEL: test1: +; NOCMOV: # %bb.0: +; NOCMOV-NEXT: snez a2, a2 +; NOCMOV-NEXT: addi a2, a2, -1 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: xor a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: test1: +; CMOV: # %bb.0: +; CMOV-NEXT: xor a1, a1, a0 +; CMOV-NEXT: bnez a2, .LBB0_2 +; CMOV-NEXT: # %bb.1: +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB0_2: +; CMOV-NEXT: ret +; +; SHORT_FORWARD-LABEL: test1: +; SHORT_FORWARD: # %bb.0: +; SHORT_FORWARD-NEXT: bnez a2, .LBB0_2 +; SHORT_FORWARD-NEXT: # %bb.1: +; SHORT_FORWARD-NEXT: xor a0, a0, a1 +; SHORT_FORWARD-NEXT: .LBB0_2: +; SHORT_FORWARD-NEXT: ret + %c = icmp eq i32 %z, 0 + %a = xor i32 %x, %y + %b = select i1 %c, i32 %a, i32 %x + ret i32 %b +} + +define signext i32 @test2(i32 signext %x, i32 signext %y, i32 signext %z) { +; NOCMOV-LABEL: test2: +; NOCMOV: # %bb.0: +; NOCMOV-NEXT: seqz a2, a2 +; NOCMOV-NEXT: addi a2, a2, -1 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: xor a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: test2: +; CMOV: # %bb.0: +; CMOV-NEXT: xor a1, a1, a0 +; CMOV-NEXT: beqz a2, .LBB1_2 +; CMOV-NEXT: # %bb.1: +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB1_2: +; CMOV-NEXT: ret +; +; SHORT_FORWARD-LABEL: test2: +; SHORT_FORWARD: # %bb.0: +; SHORT_FORWARD-NEXT: beqz a2, .LBB1_2 +; SHORT_FORWARD-NEXT: # %bb.1: +; SHORT_FORWARD-NEXT: xor a0, a0, a1 +; SHORT_FORWARD-NEXT: .LBB1_2: +; SHORT_FORWARD-NEXT: ret + %c = icmp eq i32 %z, 0 + %a = xor i32 %x, %y + %b = select i1 %c, i32 %x, i32 %a + ret i32 %b +} + +; Make sure we don't share the same basic block for two selects with the same +; condition. +define signext i32 @test3(i32 signext %v, i32 signext %w, i32 signext %x, i32 signext %y, i32 signext %z) { +; NOCMOV-LABEL: test3: +; NOCMOV: # %bb.0: +; NOCMOV-NEXT: seqz a4, a4 +; NOCMOV-NEXT: addi a4, a4, -1 +; NOCMOV-NEXT: and a1, a1, a4 +; NOCMOV-NEXT: xor a0, a0, a1 +; NOCMOV-NEXT: and a3, a3, a4 +; NOCMOV-NEXT: xor a2, a2, a3 +; NOCMOV-NEXT: addw a0, a0, a2 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: test3: +; CMOV: # %bb.0: +; CMOV-NEXT: xor a1, a1, a0 +; CMOV-NEXT: bnez a4, .LBB2_2 +; CMOV-NEXT: # %bb.1: +; CMOV-NEXT: mv a1, a0 +; CMOV-NEXT: .LBB2_2: +; CMOV-NEXT: xor a0, a2, a3 +; CMOV-NEXT: bnez a4, .LBB2_4 +; CMOV-NEXT: # %bb.3: +; CMOV-NEXT: mv a0, a2 +; CMOV-NEXT: .LBB2_4: +; CMOV-NEXT: addw a0, a0, a1 +; CMOV-NEXT: ret +; +; SHORT_FORWARD-LABEL: test3: +; SHORT_FORWARD: # %bb.0: +; SHORT_FORWARD-NEXT: beqz a4, .LBB2_2 +; SHORT_FORWARD-NEXT: # %bb.1: +; SHORT_FORWARD-NEXT: xor a0, a0, a1 +; SHORT_FORWARD-NEXT: .LBB2_2: +; SHORT_FORWARD-NEXT: beqz a4, .LBB2_4 +; SHORT_FORWARD-NEXT: # %bb.3: +; SHORT_FORWARD-NEXT: xor a2, a2, a3 +; SHORT_FORWARD-NEXT: .LBB2_4: +; SHORT_FORWARD-NEXT: addw a0, a0, a2 +; SHORT_FORWARD-NEXT: ret + %c = icmp eq i32 %z, 0 + %a = xor i32 %v, %w + %b = select i1 %c, i32 %v, i32 %a + %d = xor i32 %x, %y + %e = select i1 %c, i32 %x, i32 %d + %f = add i32 %b, %e + ret i32 %f +} + +define signext i32 @test4(i32 signext %x, i32 signext %y, i32 signext %z) { +; NOCMOV-LABEL: test4: +; NOCMOV: # %bb.0: +; NOCMOV-NEXT: snez a0, a2 +; NOCMOV-NEXT: addi a0, a0, -1 +; NOCMOV-NEXT: andi a0, a0, 3 +; NOCMOV-NEXT: ret +; +; CMOV-NOZICOND-LABEL: test4: +; CMOV-NOZICOND: # %bb.0: +; CMOV-NOZICOND-NEXT: li a1, 0 +; CMOV-NOZICOND-NEXT: li a0, 3 +; CMOV-NOZICOND-NEXT: beqz a2, .LBB3_2 +; CMOV-NOZICOND-NEXT: # %bb.1: +; CMOV-NOZICOND-NEXT: mv a0, a1 +; CMOV-NOZICOND-NEXT: .LBB3_2: +; CMOV-NOZICOND-NEXT: ret +; +; CMOV-ZICOND-LABEL: test4: +; CMOV-ZICOND: # %bb.0: +; CMOV-ZICOND-NEXT: li a0, 3 +; CMOV-ZICOND-NEXT: czero.nez a0, a0, a2 +; CMOV-ZICOND-NEXT: ret +; +; SFB-NOZICOND-LABEL: test4: +; SFB-NOZICOND: # %bb.0: +; SFB-NOZICOND-NEXT: li a0, 3 +; SFB-NOZICOND-NEXT: beqz a2, .LBB3_2 +; SFB-NOZICOND-NEXT: # %bb.1: +; SFB-NOZICOND-NEXT: li a0, 0 +; SFB-NOZICOND-NEXT: .LBB3_2: +; SFB-NOZICOND-NEXT: ret +; +; SFB-ZICOND-LABEL: test4: +; SFB-ZICOND: # %bb.0: +; SFB-ZICOND-NEXT: li a0, 3 +; SFB-ZICOND-NEXT: czero.nez a0, a0, a2 +; SFB-ZICOND-NEXT: ret + %c = icmp eq i32 %z, 0 + %a = select i1 %c, i32 3, i32 0 + ret i32 %a +} + +define i16 @select_xor_1(i16 %A, i8 %cond) { +; NOCMOV-LABEL: select_xor_1: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a1, a1, 63 +; NOCMOV-NEXT: srai a1, a1, 63 +; NOCMOV-NEXT: andi a1, a1, 43 +; NOCMOV-NEXT: xor a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_xor_1: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a1, a1, 1 +; CMOV-NEXT: xori a2, a0, 43 +; CMOV-NEXT: beqz a1, .LBB4_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a2 +; CMOV-NEXT: .LBB4_2: # %entry +; CMOV-NEXT: ret +; +; SHORT_FORWARD-LABEL: select_xor_1: +; SHORT_FORWARD: # %bb.0: # %entry +; SHORT_FORWARD-NEXT: andi a1, a1, 1 +; SHORT_FORWARD-NEXT: beqz a1, .LBB4_2 +; SHORT_FORWARD-NEXT: # %bb.1: # %entry +; SHORT_FORWARD-NEXT: xori a0, a0, 43 +; SHORT_FORWARD-NEXT: .LBB4_2: # %entry +; SHORT_FORWARD-NEXT: ret +entry: + %and = and i8 %cond, 1 + %cmp10 = icmp eq i8 %and, 0 + %0 = xor i16 %A, 43 + %1 = select i1 %cmp10, i16 %A, i16 %0 + ret i16 %1 +} + +; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of +; icmp eq (and %cond, 1), 0 +define i16 @select_xor_1b(i16 %A, i8 %cond) { +; NOCMOV-LABEL: select_xor_1b: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a1, a1, 63 +; NOCMOV-NEXT: srai a1, a1, 63 +; NOCMOV-NEXT: andi a1, a1, 43 +; NOCMOV-NEXT: xor a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_xor_1b: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a1, a1, 1 +; CMOV-NEXT: xori a2, a0, 43 +; CMOV-NEXT: beqz a1, .LBB5_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a2 +; CMOV-NEXT: .LBB5_2: # %entry +; CMOV-NEXT: ret +; +; SHORT_FORWARD-LABEL: select_xor_1b: +; SHORT_FORWARD: # %bb.0: # %entry +; SHORT_FORWARD-NEXT: andi a1, a1, 1 +; SHORT_FORWARD-NEXT: beqz a1, .LBB5_2 +; SHORT_FORWARD-NEXT: # %bb.1: # %entry +; SHORT_FORWARD-NEXT: xori a0, a0, 43 +; SHORT_FORWARD-NEXT: .LBB5_2: # %entry +; SHORT_FORWARD-NEXT: ret +entry: + %and = and i8 %cond, 1 + %cmp10 = icmp ne i8 %and, 1 + %0 = xor i16 %A, 43 + %1 = select i1 %cmp10, i16 %A, i16 %0 + ret i16 %1 +} + +define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) { +; NOCMOV-LABEL: select_xor_2: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a2, a2, 63 +; NOCMOV-NEXT: srai a2, a2, 63 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: xor a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_xor_2: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a2, a2, 1 +; CMOV-NEXT: xor a1, a1, a0 +; CMOV-NEXT: beqz a2, .LBB6_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB6_2: # %entry +; CMOV-NEXT: ret +; +; SFB-ZICOND-LABEL: select_xor_2: +; SFB-ZICOND: # %bb.0: # %entry +; SFB-ZICOND-NEXT: andi a2, a2, 1 +; SFB-ZICOND-NEXT: beqz a2, .LBB6_2 +; SFB-ZICOND-NEXT: # %bb.1: # %entry +; SFB-ZICOND-NEXT: xor a0, a1, a0 +; SFB-ZICOND-NEXT: .LBB6_2: # %entry +; SFB-ZICOND-NEXT: ret +entry: + %and = and i8 %cond, 1 + %cmp10 = icmp eq i8 %and, 0 + %0 = xor i32 %B, %A + %1 = select i1 %cmp10, i32 %A, i32 %0 + ret i32 %1 +} + +; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of +; icmp eq (and %cond, 1), 0 +define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) { +; NOCMOV-LABEL: select_xor_2b: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a2, a2, 63 +; NOCMOV-NEXT: srai a2, a2, 63 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: xor a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_xor_2b: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a2, a2, 1 +; CMOV-NEXT: xor a1, a1, a0 +; CMOV-NEXT: beqz a2, .LBB7_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB7_2: # %entry +; CMOV-NEXT: ret +; +; SFB-ZICOND-LABEL: select_xor_2b: +; SFB-ZICOND: # %bb.0: # %entry +; SFB-ZICOND-NEXT: andi a2, a2, 1 +; SFB-ZICOND-NEXT: beqz a2, .LBB7_2 +; SFB-ZICOND-NEXT: # %bb.1: # %entry +; SFB-ZICOND-NEXT: xor a0, a1, a0 +; SFB-ZICOND-NEXT: .LBB7_2: # %entry +; SFB-ZICOND-NEXT: ret +entry: + %and = and i8 %cond, 1 + %cmp10 = icmp ne i8 %and, 1 + %0 = xor i32 %B, %A + %1 = select i1 %cmp10, i32 %A, i32 %0 + ret i32 %1 +} + +define i32 @select_or(i32 %A, i32 %B, i8 %cond) { +; NOCMOV-LABEL: select_or: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a2, a2, 63 +; NOCMOV-NEXT: srai a2, a2, 63 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: or a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_or: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a2, a2, 1 +; CMOV-NEXT: or a1, a1, a0 +; CMOV-NEXT: beqz a2, .LBB8_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB8_2: # %entry +; CMOV-NEXT: ret +; +; SFB-ZICOND-LABEL: select_or: +; SFB-ZICOND: # %bb.0: # %entry +; SFB-ZICOND-NEXT: andi a2, a2, 1 +; SFB-ZICOND-NEXT: beqz a2, .LBB8_2 +; SFB-ZICOND-NEXT: # %bb.1: # %entry +; SFB-ZICOND-NEXT: or a0, a1, a0 +; SFB-ZICOND-NEXT: .LBB8_2: # %entry +; SFB-ZICOND-NEXT: ret +entry: + %and = and i8 %cond, 1 + %cmp10 = icmp eq i8 %and, 0 + %0 = or i32 %B, %A + %1 = select i1 %cmp10, i32 %A, i32 %0 + ret i32 %1 +} + +; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of +; icmp eq (and %cond, 1), 0 +define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) { +; NOCMOV-LABEL: select_or_b: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a2, a2, 63 +; NOCMOV-NEXT: srai a2, a2, 63 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: or a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_or_b: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a2, a2, 1 +; CMOV-NEXT: or a1, a1, a0 +; CMOV-NEXT: beqz a2, .LBB9_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB9_2: # %entry +; CMOV-NEXT: ret +; +; SFB-ZICOND-LABEL: select_or_b: +; SFB-ZICOND: # %bb.0: # %entry +; SFB-ZICOND-NEXT: andi a2, a2, 1 +; SFB-ZICOND-NEXT: beqz a2, .LBB9_2 +; SFB-ZICOND-NEXT: # %bb.1: # %entry +; SFB-ZICOND-NEXT: or a0, a1, a0 +; SFB-ZICOND-NEXT: .LBB9_2: # %entry +; SFB-ZICOND-NEXT: ret +entry: + %and = and i8 %cond, 1 + %cmp10 = icmp ne i8 %and, 1 + %0 = or i32 %B, %A + %1 = select i1 %cmp10, i32 %A, i32 %0 + ret i32 %1 +} + +define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) { +; NOCMOV-LABEL: select_or_1: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a2, a2, 63 +; NOCMOV-NEXT: srai a2, a2, 63 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: or a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_or_1: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a2, a2, 1 +; CMOV-NEXT: or a1, a1, a0 +; CMOV-NEXT: beqz a2, .LBB10_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB10_2: # %entry +; CMOV-NEXT: ret +; +; SFB-ZICOND-LABEL: select_or_1: +; SFB-ZICOND: # %bb.0: # %entry +; SFB-ZICOND-NEXT: andi a2, a2, 1 +; SFB-ZICOND-NEXT: beqz a2, .LBB10_2 +; SFB-ZICOND-NEXT: # %bb.1: # %entry +; SFB-ZICOND-NEXT: or a0, a1, a0 +; SFB-ZICOND-NEXT: .LBB10_2: # %entry +; SFB-ZICOND-NEXT: ret +entry: + %and = and i32 %cond, 1 + %cmp10 = icmp eq i32 %and, 0 + %0 = or i32 %B, %A + %1 = select i1 %cmp10, i32 %A, i32 %0 + ret i32 %1 +} + +; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of +; icmp eq (and %cond, 1), 0 +define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) { +; NOCMOV-LABEL: select_or_1b: +; NOCMOV: # %bb.0: # %entry +; NOCMOV-NEXT: slli a2, a2, 63 +; NOCMOV-NEXT: srai a2, a2, 63 +; NOCMOV-NEXT: and a1, a1, a2 +; NOCMOV-NEXT: or a0, a0, a1 +; NOCMOV-NEXT: ret +; +; CMOV-LABEL: select_or_1b: +; CMOV: # %bb.0: # %entry +; CMOV-NEXT: andi a2, a2, 1 +; CMOV-NEXT: or a1, a1, a0 +; CMOV-NEXT: beqz a2, .LBB11_2 +; CMOV-NEXT: # %bb.1: # %entry +; CMOV-NEXT: mv a0, a1 +; CMOV-NEXT: .LBB11_2: # %entry +; CMOV-NEXT: ret +; +; SFB-ZICOND-LABEL: select_or_1b: +; SFB-ZICOND: # %bb.0: # %entry +; SFB-ZICOND-NEXT: andi a2, a2, 1 +; SFB-ZICOND-NEXT: beqz a2, .LBB11_2 +; SFB-ZICOND-NEXT: # %bb.1: # %entry +; SFB-ZICOND-NEXT: or a0, a1, a0 +; SFB-ZICOND-NEXT: .LBB11_2: # %entry +; SFB-ZICOND-NEXT: ret +entry: + %and = and i32 %cond, 1 + %cmp10 = icmp ne i32 %and, 1 + %0 = or i32 %B, %A + %1 = select i1 %cmp10, i32 %A, i32 %0 + ret i32 %1 +} -- GitLab From 1ea7a56057492d9da1124787a9855cc2edca7df9 Mon Sep 17 00:00:00 2001 From: Advenam Tacet Date: Tue, 9 Jan 2024 00:45:34 +0100 Subject: [PATCH 124/652] Revert "[ASan][libc++] String annotations optimizations fix with lambda (#76200)" This reverts commit c68a9d25e99a096f6862fc4b57dd380a21245d31. --- libcxx/include/string | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/include/string b/libcxx/include/string index e2be53eaee24..c676182fba8b 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -922,7 +922,7 @@ public: // Turning off ASan instrumentation for variable initialization with _LIBCPP_STRING_INTERNAL_MEMORY_ACCESS // does not work consistently during initialization of __r_, so we instead unpoison __str's memory manually first. // __str's memory needs to be unpoisoned only in the case where it's a short string. - : __r_([](basic_string &__s){ if(!__s.__is_long()) __s.__annotate_delete(); return std::move(__s.__r_); }(__str)) { + : __r_(((__str.__is_long() ? 0 : (__str.__annotate_delete(), 0)), std::move(__str.__r_))) { __str.__r_.first() = __rep(); __str.__annotate_new(0); if (!__is_long()) -- GitLab From ac8b4f874945f83eec8c8f56d9fc80093e02a7b2 Mon Sep 17 00:00:00 2001 From: Usman Nadeem Date: Mon, 8 Jan 2024 15:51:33 -0800 Subject: [PATCH 125/652] [AArch64][SVE2] Add pattern for BCAX (#77159) Bitwise clear and exclusive or Add pattern for: xor x, (and y, not(z)) -> bcax x, y, z --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 5 +- llvm/test/CodeGen/AArch64/sve2-bcax.ll | 143 ++++++++++++++++++ 2 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AArch64/sve2-bcax.ll diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 344a15389063..ee10a7d1c706 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -453,6 +453,9 @@ def AArch64msb_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3), def AArch64eor3 : PatFrags<(ops node:$op1, node:$op2, node:$op3), [(int_aarch64_sve_eor3 node:$op1, node:$op2, node:$op3), (xor node:$op1, (xor node:$op2, node:$op3))]>; +def AArch64bcax : PatFrags<(ops node:$op1, node:$op2, node:$op3), + [(int_aarch64_sve_bcax node:$op1, node:$op2, node:$op3), + (xor node:$op1, (and node:$op2, (vnot node:$op3)))]>; def AArch64fmla_m1 : PatFrags<(ops node:$pg, node:$za, node:$zn, node:$zm), [(int_aarch64_sve_fmla node:$pg, node:$za, node:$zn, node:$zm), @@ -3714,7 +3717,7 @@ let Predicates = [HasSVE2orSME] in { // SVE2 bitwise ternary operations defm EOR3_ZZZZ : sve2_int_bitwise_ternary_op<0b000, "eor3", AArch64eor3>; - defm BCAX_ZZZZ : sve2_int_bitwise_ternary_op<0b010, "bcax", int_aarch64_sve_bcax>; + defm BCAX_ZZZZ : sve2_int_bitwise_ternary_op<0b010, "bcax", AArch64bcax>; defm BSL_ZZZZ : sve2_int_bitwise_ternary_op<0b001, "bsl", int_aarch64_sve_bsl, AArch64bsp>; defm BSL1N_ZZZZ : sve2_int_bitwise_ternary_op<0b011, "bsl1n", int_aarch64_sve_bsl1n>; defm BSL2N_ZZZZ : sve2_int_bitwise_ternary_op<0b101, "bsl2n", int_aarch64_sve_bsl2n>; diff --git a/llvm/test/CodeGen/AArch64/sve2-bcax.ll b/llvm/test/CodeGen/AArch64/sve2-bcax.ll new file mode 100644 index 000000000000..c4a82e69a05a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve2-bcax.ll @@ -0,0 +1,143 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefix=SVE %s +; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefix=SVE2 %s + +define @bcax_nxv2i64_1( %0, %1, %2) { +; SVE-LABEL: bcax_nxv2i64_1: +; SVE: // %bb.0: +; SVE-NEXT: bic z1.d, z2.d, z1.d +; SVE-NEXT: eor z0.d, z1.d, z0.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv2i64_1: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i64 -1) + %5 = and %4, %2 + %6 = xor %5, %0 + ret %6 +} + +define @bcax_nxv2i64_2( %0, %1, %2) { +; SVE-LABEL: bcax_nxv2i64_2: +; SVE: // %bb.0: +; SVE-NEXT: bic z0.d, z0.d, z1.d +; SVE-NEXT: eor z0.d, z0.d, z2.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv2i64_2: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d +; SVE2-NEXT: mov z0.d, z2.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i64 -1) + %5 = and %4, %0 + %6 = xor %5, %2 + ret %6 +} + +define @bcax_nxv4i32_1( %0, %1, %2) { +; SVE-LABEL: bcax_nxv4i32_1: +; SVE: // %bb.0: +; SVE-NEXT: bic z1.d, z2.d, z1.d +; SVE-NEXT: eor z0.d, z1.d, z0.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv4i32_1: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i32 -1) + %5 = and %4, %2 + %6 = xor %5, %0 + ret %6 +} + +define @bcax_nxv4i32_2( %0, %1, %2) { +; SVE-LABEL: bcax_nxv4i32_2: +; SVE: // %bb.0: +; SVE-NEXT: bic z0.d, z0.d, z1.d +; SVE-NEXT: eor z0.d, z0.d, z2.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv4i32_2: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d +; SVE2-NEXT: mov z0.d, z2.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i32 -1) + %5 = and %4, %0 + %6 = xor %5, %2 + ret %6 +} + +define @bcax_nxv8i16_1( %0, %1, %2) { +; SVE-LABEL: bcax_nxv8i16_1: +; SVE: // %bb.0: +; SVE-NEXT: bic z1.d, z2.d, z1.d +; SVE-NEXT: eor z0.d, z1.d, z0.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv8i16_1: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i16 -1) + %5 = and %4, %2 + %6 = xor %5, %0 + ret %6 +} + +define @bcax_nxv8i16_2( %0, %1, %2) { +; SVE-LABEL: bcax_nxv8i16_2: +; SVE: // %bb.0: +; SVE-NEXT: bic z0.d, z0.d, z1.d +; SVE-NEXT: eor z0.d, z0.d, z2.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv8i16_2: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d +; SVE2-NEXT: mov z0.d, z2.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i16 -1) + %5 = and %4, %0 + %6 = xor %5, %2 + ret %6 +} + +define @bcax_nxv16i8_1( %0, %1, %2) { +; SVE-LABEL: bcax_nxv16i8_1: +; SVE: // %bb.0: +; SVE-NEXT: bic z1.d, z2.d, z1.d +; SVE-NEXT: eor z0.d, z1.d, z0.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv16i8_1: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i8 -1) + %5 = and %4, %2 + %6 = xor %5, %0 + ret %6 +} + +define @bcax_nxv16i8_2( %0, %1, %2) { +; SVE-LABEL: bcax_nxv16i8_2: +; SVE: // %bb.0: +; SVE-NEXT: bic z0.d, z0.d, z1.d +; SVE-NEXT: eor z0.d, z0.d, z2.d +; SVE-NEXT: ret +; +; SVE2-LABEL: bcax_nxv16i8_2: +; SVE2: // %bb.0: +; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d +; SVE2-NEXT: mov z0.d, z2.d +; SVE2-NEXT: ret + %4 = xor %1, splat (i8 -1) + %5 = and %4, %0 + %6 = xor %5, %2 + ret %6 +} -- GitLab From a0ae5258065a856d5f8d9f8dcb12e9d8394f789f Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Tue, 9 Jan 2024 08:01:57 +0800 Subject: [PATCH 126/652] [clang-tidy]unused using decls only check cpp files (#77335) --- clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.h | 3 +++ clang-tools-extra/docs/ReleaseNotes.rst | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.h b/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.h index fa2a8799d098..498b3ffd2678 100644 --- a/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.h +++ b/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.h @@ -26,6 +26,9 @@ public: void registerMatchers(ast_matchers::MatchFinder *Finder) override; void check(const ast_matchers::MatchFinder::MatchResult &Result) override; void onEndOfTranslationUnit() override; + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { + return LangOpts.CPlusPlus; + } private: void removeFromFoundDecls(const Decl *D); diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 1bd5a72126c1..d7f46cede037 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -382,7 +382,7 @@ Changes in existing checks - Improved :doc:`misc-unused-using-decls ` check to avoid false positive when - using in elaborated type. + using in elaborated type and only check cpp files. - Improved :doc:`modernize-avoid-bind ` check to -- GitLab From 6958986f77bdbedd6ba571af7b546018f9108067 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 16:08:22 -0800 Subject: [PATCH 127/652] [libc] fix -Wconversion (#77384) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following from GCC: llvm-project/libc/src/string/memory_utils/op_x86.h:236:24: error: conversion from ‘long unsigned int’ to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion] 236 | return (xored >> 32) | (xored & 0xFFFFFFFF); | ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~ Link: https://lab.llvm.org/buildbot/#/builders/250/builds/16236/steps/8/logs/stdio Link: https://github.com/llvm/llvm-project/pull/74506 --- libc/src/string/memory_utils/op_x86.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libc/src/string/memory_utils/op_x86.h b/libc/src/string/memory_utils/op_x86.h index 1a20659c178c..3d2eb13fa302 100644 --- a/libc/src/string/memory_utils/op_x86.h +++ b/libc/src/string/memory_utils/op_x86.h @@ -233,7 +233,8 @@ template <> LIBC_INLINE uint32_t neq<__m512i>(CPtr p1, CPtr p2, size_t offset) { const auto a = load<__m512i>(p1, offset); const auto b = load<__m512i>(p2, offset); const uint64_t xored = _mm512_cmpneq_epi8_mask(a, b); - return (xored >> 32) | (xored & 0xFFFFFFFF); + return static_cast(xored >> 32) | + static_cast(xored & 0xFFFFFFFF)); } template <> LIBC_INLINE MemcmpReturnType cmp_neq<__m512i>(CPtr p1, CPtr p2, size_t offset) { -- GitLab From 7c89b20e02ff079ec84fc54880dbc6c063d8c915 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 8 Jan 2024 16:12:49 -0800 Subject: [PATCH 128/652] [ELF] OVERLAY: support optional start address and LMA https://reviews.llvm.org/D44780 implemented rudimentary support for OVERLAY. The start address and `AT(ldaddr)` in `OVERLAY [start] : [NOCROSSREFS] [AT ( ldaddr )]` are not optional. In addition, there are two issues: * When the start address is `.`, subsequent sections don't share the address of the first overlay section. * When the first overlay section is empty and discardable, `p_paddr` is incorrectly zero. This is because a discarded section has a zero address, causing `prev->getLMA() + prev->size` where `prev` refers to the first section to evaluate to zero. This patch supports optional start address and LMA and fix the issues. Close #77265 Pull Request: https://github.com/llvm/llvm-project/pull/77272 --- lld/ELF/ScriptParser.cpp | 27 +++++++++++++++++--------- lld/test/ELF/linkerscript/overlay.test | 19 ++++++++++-------- 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/lld/ELF/ScriptParser.cpp b/lld/ELF/ScriptParser.cpp index 55b10f0c59b5..4fdb8c7075a6 100644 --- a/lld/ELF/ScriptParser.cpp +++ b/lld/ELF/ScriptParser.cpp @@ -531,13 +531,17 @@ void ScriptParser::readSearchDir() { // linker's sections sanity check failures. // https://sourceware.org/binutils/docs/ld/Overlay-Description.html#Overlay-Description SmallVector ScriptParser::readOverlay() { - // VA and LMA expressions are optional, though for simplicity of - // implementation we assume they are not. That is what OVERLAY was designed - // for first of all: to allow sections with overlapping VAs at different LMAs. - Expr addrExpr = readExpr(); - expect(":"); - expect("AT"); - Expr lmaExpr = readParenExpr(); + Expr addrExpr; + if (consume(":")) { + addrExpr = [] { return script->getDot(); }; + } else { + addrExpr = readExpr(); + expect(":"); + } + // When AT is omitted, LMA should equal VMA. script->getDot() when evaluating + // lmaExpr will ensure this, even if the start address is specified. + Expr lmaExpr = + consume("AT") ? readParenExpr() : [] { return script->getDot(); }; expect("{"); SmallVector v; @@ -547,10 +551,15 @@ SmallVector ScriptParser::readOverlay() { // starting from the base load address specified. OutputDesc *osd = readOverlaySectionDescription(); osd->osec.addrExpr = addrExpr; - if (prev) + if (prev) { osd->osec.lmaExpr = [=] { return prev->getLMA() + prev->size; }; - else + } else { osd->osec.lmaExpr = lmaExpr; + // Use first section address for subsequent sections as initial addrExpr + // can be DOT. Ensure the first section, even if empty, is not discarded. + osd->osec.usedInExpression = true; + addrExpr = [=]() -> ExprValue { return {&osd->osec, false, 0, ""}; }; + } v.push_back(osd); prev = &osd->osec; } diff --git a/lld/test/ELF/linkerscript/overlay.test b/lld/test/ELF/linkerscript/overlay.test index 942e0a2971be..b939ee4c4095 100644 --- a/lld/test/ELF/linkerscript/overlay.test +++ b/lld/test/ELF/linkerscript/overlay.test @@ -16,9 +16,10 @@ # CHECK-NEXT: .small1 PROGBITS 0000000000001000 002000 000004 # CHECK-NEXT: .small2 PROGBITS 0000000000001008 002008 000004 # CHECK-NEXT: .big2 PROGBITS 0000000000001008 003008 000008 +# CHECK-NEXT: .empty3 PROGBITS 0000000000001010 003010 000000 # CHECK-NEXT: .small3 PROGBITS 0000000000001010 003010 000004 -# CHECK-NEXT: .big3 PROGBITS 0000000000001014 003014 000008 -# CHECK-NEXT: .text PROGBITS 0000000000001024 003024 000001 +# CHECK-NEXT: .big3 PROGBITS 0000000000001010 004010 000008 +# CHECK-NEXT: .text PROGBITS 0000000000001018 004018 000001 # CHECK: Program Headers: # CHECK: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align @@ -26,10 +27,9 @@ # CHECK-NEXT: LOAD 0x002000 0x0000000000001000 0x0000000000001008 0x000004 0x000004 R 0x1000 # CHECK-NEXT: LOAD 0x002008 0x0000000000001008 0x0000000000002008 0x000004 0x000004 R 0x1000 # CHECK-NEXT: LOAD 0x003008 0x0000000000001008 0x000000000000200c 0x000008 0x000008 R 0x1000 -## FIXME Fix p_paddr when the first section in an overlay is empty and discarded. -# CHECK-NEXT: LOAD 0x003010 0x0000000000001010 0x0000000000000000 0x000004 0x000004 R 0x1000 -# CHECK-NEXT: LOAD 0x003014 0x0000000000001014 0x0000000000000004 0x000008 0x000008 R 0x1000 -# CHECK-NEXT: LOAD 0x003024 0x0000000000001024 0x0000000000000014 0x000001 0x000001 R E 0x1000 +# CHECK-NEXT: LOAD 0x003010 0x0000000000001010 0x0000000000002014 0x000004 0x000004 R 0x1000 +# CHECK-NEXT: LOAD 0x004010 0x0000000000001010 0x0000000000002018 0x000008 0x000008 R 0x1000 +# CHECK-NEXT: LOAD 0x004018 0x0000000000001018 0x0000000000002020 0x000001 0x000001 R E 0x1000 # RUN: not ld.lld a.o -T err1.t 2>&1 | FileCheck %s --check-prefix=ERR1 --match-full-lines --strict-whitespace # ERR1:{{.*}}error: err1.t:3: { expected, but got 0x3000 @@ -57,14 +57,17 @@ _start: #--- a.t SECTIONS { - OVERLAY 0x1000 : AT( 0x1000 ) { +## LMA defaults to VMA + OVERLAY 0x1000 : { .big1 { *(.big1) } .small1 { *(.small1) } } - OVERLAY 0x1008 : AT (0x2008) { +## .big2 starts at ADDR(.small2) + OVERLAY : AT (0x2008) { .small2 { *(.small2) } .big2 { *(.big2) } } +## .empty3 is not discarded. .small3 and .big3 share its address. OVERLAY . : AT (0x2014) { .empty3 { *(.empty3) } .small3 { *(.small3) } -- GitLab From 1689bbea17683129f41246110af1ebd32b98362f Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 16:18:11 -0800 Subject: [PATCH 129/652] [libc] fix up #77384 --- libc/src/string/memory_utils/op_x86.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libc/src/string/memory_utils/op_x86.h b/libc/src/string/memory_utils/op_x86.h index 3d2eb13fa302..1d2ae5cd1540 100644 --- a/libc/src/string/memory_utils/op_x86.h +++ b/libc/src/string/memory_utils/op_x86.h @@ -234,7 +234,7 @@ template <> LIBC_INLINE uint32_t neq<__m512i>(CPtr p1, CPtr p2, size_t offset) { const auto b = load<__m512i>(p2, offset); const uint64_t xored = _mm512_cmpneq_epi8_mask(a, b); return static_cast(xored >> 32) | - static_cast(xored & 0xFFFFFFFF)); + static_cast(xored & 0xFFFFFFFF); } template <> LIBC_INLINE MemcmpReturnType cmp_neq<__m512i>(CPtr p1, CPtr p2, size_t offset) { -- GitLab From 70cea91e0fc93db618069588e6a06314b2b0e2d3 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Jan 2024 16:21:49 -0800 Subject: [PATCH 130/652] [libc] temporarily set -Wno-shorten-64-to-32 (#77396) This is still broken after #77350. Disable the warning for now, and fix properly once the buildbot it back to green. Link: https://github.com/llvm/llvm-project/issues/77395 --- libc/src/sys/mman/linux/CMakeLists.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libc/src/sys/mman/linux/CMakeLists.txt b/libc/src/sys/mman/linux/CMakeLists.txt index 163e7dead888..08694ec48be3 100644 --- a/libc/src/sys/mman/linux/CMakeLists.txt +++ b/libc/src/sys/mman/linux/CMakeLists.txt @@ -22,6 +22,9 @@ add_entrypoint_object( libc.include.sys_syscall libc.src.__support.OSUtil.osutil libc.src.errno.errno + COMPILE_OPTIONS + # TODO: https://github.com/llvm/llvm-project/issues/77395 + -Wno-shorten-64-to-32 ) add_entrypoint_object( -- GitLab From eee71ed3f7d0abe40f7c54166421421362a8ac46 Mon Sep 17 00:00:00 2001 From: Kai Sasaki Date: Tue, 9 Jan 2024 09:29:27 +0900 Subject: [PATCH 131/652] [mlir][complex] Support Fastmath flag for complex.mulf (#74554) Support fast math flag in the conversion of `complex.mulf` op to standard dialect. See: https://discourse.llvm.org/t/rfc-fastmath-flags-support-in-complex-dialect/71981 --- .../ComplexToStandard/ComplexToStandard.cpp | 66 ++++++---- .../convert-to-standard.mlir | 120 ++++++++++++++++++ 2 files changed, 158 insertions(+), 28 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index bf753c7062f3..4c9dad9e2c17 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -569,29 +569,39 @@ struct MulOpConversion : public OpConversionPattern { mlir::ImplicitLocOpBuilder b(op.getLoc(), rewriter); auto type = cast(adaptor.getLhs().getType()); auto elementType = cast(type.getElementType()); + arith::FastMathFlagsAttr fmf = op.getFastMathFlagsAttr(); + auto fmfValue = fmf.getValue(); Value lhsReal = b.create(elementType, adaptor.getLhs()); - Value lhsRealAbs = b.create(lhsReal); + Value lhsRealAbs = b.create(lhsReal, fmfValue); Value lhsImag = b.create(elementType, adaptor.getLhs()); - Value lhsImagAbs = b.create(lhsImag); + Value lhsImagAbs = b.create(lhsImag, fmfValue); Value rhsReal = b.create(elementType, adaptor.getRhs()); - Value rhsRealAbs = b.create(rhsReal); + Value rhsRealAbs = b.create(rhsReal, fmfValue); Value rhsImag = b.create(elementType, adaptor.getRhs()); - Value rhsImagAbs = b.create(rhsImag); - - Value lhsRealTimesRhsReal = b.create(lhsReal, rhsReal); - Value lhsRealTimesRhsRealAbs = b.create(lhsRealTimesRhsReal); - Value lhsImagTimesRhsImag = b.create(lhsImag, rhsImag); - Value lhsImagTimesRhsImagAbs = b.create(lhsImagTimesRhsImag); - Value real = - b.create(lhsRealTimesRhsReal, lhsImagTimesRhsImag); - - Value lhsImagTimesRhsReal = b.create(lhsImag, rhsReal); - Value lhsImagTimesRhsRealAbs = b.create(lhsImagTimesRhsReal); - Value lhsRealTimesRhsImag = b.create(lhsReal, rhsImag); - Value lhsRealTimesRhsImagAbs = b.create(lhsRealTimesRhsImag); - Value imag = - b.create(lhsImagTimesRhsReal, lhsRealTimesRhsImag); + Value rhsImagAbs = b.create(rhsImag, fmfValue); + + Value lhsRealTimesRhsReal = + b.create(lhsReal, rhsReal, fmfValue); + Value lhsRealTimesRhsRealAbs = + b.create(lhsRealTimesRhsReal, fmfValue); + Value lhsImagTimesRhsImag = + b.create(lhsImag, rhsImag, fmfValue); + Value lhsImagTimesRhsImagAbs = + b.create(lhsImagTimesRhsImag, fmfValue); + Value real = b.create(lhsRealTimesRhsReal, + lhsImagTimesRhsImag, fmfValue); + + Value lhsImagTimesRhsReal = + b.create(lhsImag, rhsReal, fmfValue); + Value lhsImagTimesRhsRealAbs = + b.create(lhsImagTimesRhsReal, fmfValue); + Value lhsRealTimesRhsImag = + b.create(lhsReal, rhsImag, fmfValue); + Value lhsRealTimesRhsImagAbs = + b.create(lhsRealTimesRhsImag, fmfValue); + Value imag = b.create(lhsImagTimesRhsReal, + lhsRealTimesRhsImag, fmfValue); // Handle cases where the "naive" calculation results in NaN values. Value realIsNan = @@ -717,20 +727,20 @@ struct MulOpConversion : public OpConversionPattern { recalc = b.create(isNan, recalc); // Recalculate real part. - lhsRealTimesRhsReal = b.create(lhsReal, rhsReal); - lhsImagTimesRhsImag = b.create(lhsImag, rhsImag); - Value newReal = - b.create(lhsRealTimesRhsReal, lhsImagTimesRhsImag); + lhsRealTimesRhsReal = b.create(lhsReal, rhsReal, fmfValue); + lhsImagTimesRhsImag = b.create(lhsImag, rhsImag, fmfValue); + Value newReal = b.create(lhsRealTimesRhsReal, + lhsImagTimesRhsImag, fmfValue); real = b.create( - recalc, b.create(inf, newReal), real); + recalc, b.create(inf, newReal, fmfValue), real); // Recalculate imag part. - lhsImagTimesRhsReal = b.create(lhsImag, rhsReal); - lhsRealTimesRhsImag = b.create(lhsReal, rhsImag); - Value newImag = - b.create(lhsImagTimesRhsReal, lhsRealTimesRhsImag); + lhsImagTimesRhsReal = b.create(lhsImag, rhsReal, fmfValue); + lhsRealTimesRhsImag = b.create(lhsReal, rhsImag, fmfValue); + Value newImag = b.create(lhsImagTimesRhsReal, + lhsRealTimesRhsImag, fmfValue); imag = b.create( - recalc, b.create(inf, newImag), imag); + recalc, b.create(inf, newImag, fmfValue), imag); rewriter.replaceOpWithNewOp(op, type, real, imag); return success(); diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index 3af28150fd5c..8fa29ea43854 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -845,3 +845,123 @@ func.func @complex_log1p_with_fmf(%arg: complex) -> complex { // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] fastmath : f32 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] : complex + +// ----- + +// CHECK-LABEL: func @complex_mul_with_fmf +// CHECK-SAME: (%[[LHS:.*]]: complex, %[[RHS:.*]]: complex) +func.func @complex_mul_with_fmf(%lhs: complex, %rhs: complex) -> complex { + %mul = complex.mul %lhs, %rhs fastmath : complex + return %mul : complex +} +// CHECK: %[[LHS_REAL:.*]] = complex.re %[[LHS]] : complex +// CHECK: %[[LHS_REAL_ABS:.*]] = math.absf %[[LHS_REAL]] fastmath : f32 +// CHECK: %[[LHS_IMAG:.*]] = complex.im %[[LHS]] : complex +// CHECK: %[[LHS_IMAG_ABS:.*]] = math.absf %[[LHS_IMAG]] fastmath : f32 +// CHECK: %[[RHS_REAL:.*]] = complex.re %[[RHS]] : complex +// CHECK: %[[RHS_REAL_ABS:.*]] = math.absf %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[RHS_IMAG:.*]] = complex.im %[[RHS]] : complex +// CHECK: %[[RHS_IMAG_ABS:.*]] = math.absf %[[RHS_IMAG]] fastmath : f32 + +// CHECK: %[[LHS_REAL_TIMES_RHS_REAL:.*]] = arith.mulf %[[LHS_REAL]], %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[LHS_REAL_TIMES_RHS_REAL_ABS:.*]] = math.absf %[[LHS_REAL_TIMES_RHS_REAL]] fastmath : f32 +// CHECK: %[[LHS_IMAG_TIMES_RHS_IMAG:.*]] = arith.mulf %[[LHS_IMAG]], %[[RHS_IMAG]] fastmath : f32 +// CHECK: %[[LHS_IMAG_TIMES_RHS_IMAG_ABS:.*]] = math.absf %[[LHS_IMAG_TIMES_RHS_IMAG]] fastmath : f32 +// CHECK: %[[REAL:.*]] = arith.subf %[[LHS_REAL_TIMES_RHS_REAL]], %[[LHS_IMAG_TIMES_RHS_IMAG]] fastmath : f32 + +// CHECK: %[[LHS_IMAG_TIMES_RHS_REAL:.*]] = arith.mulf %[[LHS_IMAG]], %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[LHS_IMAG_TIMES_RHS_REAL_ABS:.*]] = math.absf %[[LHS_IMAG_TIMES_RHS_REAL]] fastmath : f32 +// CHECK: %[[LHS_REAL_TIMES_RHS_IMAG:.*]] = arith.mulf %[[LHS_REAL]], %[[RHS_IMAG]] fastmath : f32 +// CHECK: %[[LHS_REAL_TIMES_RHS_IMAG_ABS:.*]] = math.absf %[[LHS_REAL_TIMES_RHS_IMAG]] fastmath : f32 +// CHECK: %[[IMAG:.*]] = arith.addf %[[LHS_IMAG_TIMES_RHS_REAL]], %[[LHS_REAL_TIMES_RHS_IMAG]] fastmath : f32 + +// Handle cases where the "naive" calculation results in NaN values. +// CHECK: %[[REAL_IS_NAN:.*]] = arith.cmpf uno, %[[REAL]], %[[REAL]] : f32 +// CHECK: %[[IMAG_IS_NAN:.*]] = arith.cmpf uno, %[[IMAG]], %[[IMAG]] : f32 +// CHECK: %[[IS_NAN:.*]] = arith.andi %[[REAL_IS_NAN]], %[[IMAG_IS_NAN]] : i1 +// CHECK: %[[INF:.*]] = arith.constant 0x7F800000 : f32 + +// Case 1. LHS_REAL or LHS_IMAG are infinite. +// CHECK: %[[LHS_REAL_IS_INF:.*]] = arith.cmpf oeq, %[[LHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[LHS_IMAG_IS_INF:.*]] = arith.cmpf oeq, %[[LHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[LHS_IS_INF:.*]] = arith.ori %[[LHS_REAL_IS_INF]], %[[LHS_IMAG_IS_INF]] : i1 +// CHECK: %[[RHS_REAL_IS_NAN:.*]] = arith.cmpf uno, %[[RHS_REAL]], %[[RHS_REAL]] : f32 +// CHECK: %[[RHS_IMAG_IS_NAN:.*]] = arith.cmpf uno, %[[RHS_IMAG]], %[[RHS_IMAG]] : f32 +// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[LHS_REAL_IS_INF_FLOAT:.*]] = arith.select %[[LHS_REAL_IS_INF]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[TMP:.*]] = math.copysign %[[LHS_REAL_IS_INF_FLOAT]], %[[LHS_REAL]] : f32 +// CHECK: %[[LHS_REAL1:.*]] = arith.select %[[LHS_IS_INF]], %[[TMP]], %[[LHS_REAL]] : f32 +// CHECK: %[[LHS_IMAG_IS_INF_FLOAT:.*]] = arith.select %[[LHS_IMAG_IS_INF]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[TMP:.*]] = math.copysign %[[LHS_IMAG_IS_INF_FLOAT]], %[[LHS_IMAG]] : f32 +// CHECK: %[[LHS_IMAG1:.*]] = arith.select %[[LHS_IS_INF]], %[[TMP]], %[[LHS_IMAG]] : f32 +// CHECK: %[[LHS_IS_INF_AND_RHS_REAL_IS_NAN:.*]] = arith.andi %[[LHS_IS_INF]], %[[RHS_REAL_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[RHS_REAL]] : f32 +// CHECK: %[[RHS_REAL1:.*]] = arith.select %[[LHS_IS_INF_AND_RHS_REAL_IS_NAN]], %[[TMP]], %[[RHS_REAL]] : f32 +// CHECK: %[[LHS_IS_INF_AND_RHS_IMAG_IS_NAN:.*]] = arith.andi %[[LHS_IS_INF]], %[[RHS_IMAG_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[RHS_IMAG]] : f32 +// CHECK: %[[RHS_IMAG1:.*]] = arith.select %[[LHS_IS_INF_AND_RHS_IMAG_IS_NAN]], %[[TMP]], %[[RHS_IMAG]] : f32 + +// Case 2. RHS_REAL or RHS_IMAG are infinite. +// CHECK: %[[RHS_REAL_IS_INF:.*]] = arith.cmpf oeq, %[[RHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[RHS_IMAG_IS_INF:.*]] = arith.cmpf oeq, %[[RHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[RHS_IS_INF:.*]] = arith.ori %[[RHS_REAL_IS_INF]], %[[RHS_IMAG_IS_INF]] : i1 +// CHECK: %[[LHS_REAL_IS_NAN:.*]] = arith.cmpf uno, %[[LHS_REAL1]], %[[LHS_REAL1]] : f32 +// CHECK: %[[LHS_IMAG_IS_NAN:.*]] = arith.cmpf uno, %[[LHS_IMAG1]], %[[LHS_IMAG1]] : f32 +// CHECK: %[[RHS_REAL_IS_INF_FLOAT:.*]] = arith.select %[[RHS_REAL_IS_INF]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[TMP:.*]] = math.copysign %[[RHS_REAL_IS_INF_FLOAT]], %[[RHS_REAL1]] : f32 +// CHECK: %[[RHS_REAL2:.*]] = arith.select %[[RHS_IS_INF]], %[[TMP]], %[[RHS_REAL1]] : f32 +// CHECK: %[[RHS_IMAG_IS_INF_FLOAT:.*]] = arith.select %[[RHS_IMAG_IS_INF]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[TMP:.*]] = math.copysign %[[RHS_IMAG_IS_INF_FLOAT]], %[[RHS_IMAG1]] : f32 +// CHECK: %[[RHS_IMAG2:.*]] = arith.select %[[RHS_IS_INF]], %[[TMP]], %[[RHS_IMAG1]] : f32 +// CHECK: %[[RHS_IS_INF_AND_LHS_REAL_IS_NAN:.*]] = arith.andi %[[RHS_IS_INF]], %[[LHS_REAL_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[LHS_REAL1]] : f32 +// CHECK: %[[LHS_REAL2:.*]] = arith.select %[[RHS_IS_INF_AND_LHS_REAL_IS_NAN]], %[[TMP]], %[[LHS_REAL1]] : f32 +// CHECK: %[[RHS_IS_INF_AND_LHS_IMAG_IS_NAN:.*]] = arith.andi %[[RHS_IS_INF]], %[[LHS_IMAG_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[LHS_IMAG1]] : f32 +// CHECK: %[[LHS_IMAG2:.*]] = arith.select %[[RHS_IS_INF_AND_LHS_IMAG_IS_NAN]], %[[TMP]], %[[LHS_IMAG1]] : f32 +// CHECK: %[[RECALC:.*]] = arith.ori %[[LHS_IS_INF]], %[[RHS_IS_INF]] : i1 + +// Case 3. One of the pairwise products of left hand side with right hand side +// is infinite. +// CHECK: %[[LHS_REAL_TIMES_RHS_REAL_IS_INF:.*]] = arith.cmpf oeq, %[[LHS_REAL_TIMES_RHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[LHS_IMAG_TIMES_RHS_IMAG_IS_INF:.*]] = arith.cmpf oeq, %[[LHS_IMAG_TIMES_RHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[IS_SPECIAL_CASE:.*]] = arith.ori %[[LHS_REAL_TIMES_RHS_REAL_IS_INF]], %[[LHS_IMAG_TIMES_RHS_IMAG_IS_INF]] : i1 +// CHECK: %[[LHS_REAL_TIMES_RHS_IMAG_IS_INF:.*]] = arith.cmpf oeq, %[[LHS_REAL_TIMES_RHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[IS_SPECIAL_CASE1:.*]] = arith.ori %[[IS_SPECIAL_CASE]], %[[LHS_REAL_TIMES_RHS_IMAG_IS_INF]] : i1 +// CHECK: %[[LHS_IMAG_TIMES_RHS_REAL_IS_INF:.*]] = arith.cmpf oeq, %[[LHS_IMAG_TIMES_RHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[IS_SPECIAL_CASE2:.*]] = arith.ori %[[IS_SPECIAL_CASE1]], %[[LHS_IMAG_TIMES_RHS_REAL_IS_INF]] : i1 +// CHECK: %[[TRUE:.*]] = arith.constant true +// CHECK: %[[NOT_RECALC:.*]] = arith.xori %[[RECALC]], %[[TRUE]] : i1 +// CHECK: %[[IS_SPECIAL_CASE3:.*]] = arith.andi %[[IS_SPECIAL_CASE2]], %[[NOT_RECALC]] : i1 +// CHECK: %[[IS_SPECIAL_CASE_AND_LHS_REAL_IS_NAN:.*]] = arith.andi %[[IS_SPECIAL_CASE3]], %[[LHS_REAL_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[LHS_REAL2]] : f32 +// CHECK: %[[LHS_REAL3:.*]] = arith.select %[[IS_SPECIAL_CASE_AND_LHS_REAL_IS_NAN]], %[[TMP]], %[[LHS_REAL2]] : f32 +// CHECK: %[[IS_SPECIAL_CASE_AND_LHS_IMAG_IS_NAN:.*]] = arith.andi %[[IS_SPECIAL_CASE3]], %[[LHS_IMAG_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[LHS_IMAG2]] : f32 +// CHECK: %[[LHS_IMAG3:.*]] = arith.select %[[IS_SPECIAL_CASE_AND_LHS_IMAG_IS_NAN]], %[[TMP]], %[[LHS_IMAG2]] : f32 +// CHECK: %[[IS_SPECIAL_CASE_AND_RHS_REAL_IS_NAN:.*]] = arith.andi %[[IS_SPECIAL_CASE3]], %[[RHS_REAL_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[RHS_REAL2]] : f32 +// CHECK: %[[RHS_REAL3:.*]] = arith.select %[[IS_SPECIAL_CASE_AND_RHS_REAL_IS_NAN]], %[[TMP]], %[[RHS_REAL2]] : f32 +// CHECK: %[[IS_SPECIAL_CASE_AND_RHS_IMAG_IS_NAN:.*]] = arith.andi %[[IS_SPECIAL_CASE3]], %[[RHS_IMAG_IS_NAN]] : i1 +// CHECK: %[[TMP:.*]] = math.copysign %[[ZERO]], %[[RHS_IMAG2]] : f32 +// CHECK: %[[RHS_IMAG3:.*]] = arith.select %[[IS_SPECIAL_CASE_AND_RHS_IMAG_IS_NAN]], %[[TMP]], %[[RHS_IMAG2]] : f32 +// CHECK: %[[RECALC2:.*]] = arith.ori %[[RECALC]], %[[IS_SPECIAL_CASE3]] : i1 +// CHECK: %[[RECALC3:.*]] = arith.andi %[[IS_NAN]], %[[RECALC2]] : i1 + + // Recalculate real part. +// CHECK: %[[LHS_REAL_TIMES_RHS_REAL:.*]] = arith.mulf %[[LHS_REAL3]], %[[RHS_REAL3]] fastmath : f32 +// CHECK: %[[LHS_IMAG_TIMES_RHS_IMAG:.*]] = arith.mulf %[[LHS_IMAG3]], %[[RHS_IMAG3]] fastmath : f32 +// CHECK: %[[NEW_REAL:.*]] = arith.subf %[[LHS_REAL_TIMES_RHS_REAL]], %[[LHS_IMAG_TIMES_RHS_IMAG]] fastmath : f32 +// CHECK: %[[NEW_REAL_TIMES_INF:.*]] = arith.mulf %[[INF]], %[[NEW_REAL]] fastmath : f32 +// CHECK: %[[FINAL_REAL:.*]] = arith.select %[[RECALC3]], %[[NEW_REAL_TIMES_INF]], %[[REAL]] : f32 + +// Recalculate imag part. +// CHECK: %[[LHS_IMAG_TIMES_RHS_REAL:.*]] = arith.mulf %[[LHS_IMAG3]], %[[RHS_REAL3]] fastmath : f32 +// CHECK: %[[LHS_REAL_TIMES_RHS_IMAG:.*]] = arith.mulf %[[LHS_REAL3]], %[[RHS_IMAG3]] fastmath : f32 +// CHECK: %[[NEW_IMAG:.*]] = arith.addf %[[LHS_IMAG_TIMES_RHS_REAL]], %[[LHS_REAL_TIMES_RHS_IMAG]] fastmath : f32 +// CHECK: %[[NEW_IMAG_TIMES_INF:.*]] = arith.mulf %[[INF]], %[[NEW_IMAG]] fastmath : f32 +// CHECK: %[[FINAL_IMAG:.*]] = arith.select %[[RECALC3]], %[[NEW_IMAG_TIMES_INF]], %[[IMAG]] : f32 + +// CHECK: %[[RESULT:.*]] = complex.create %[[FINAL_REAL]], %[[FINAL_IMAG]] : complex +// CHECK: return %[[RESULT]] : complex \ No newline at end of file -- GitLab From 4147b72301bf77ad63793e1dcefefe8d37e69a37 Mon Sep 17 00:00:00 2001 From: HaohaiWen Date: Tue, 9 Jan 2024 09:05:11 +0800 Subject: [PATCH 132/652] [CostModel][X86] Fix fpext conversion cost for 16 elements (#76278) The fpext conversion cost for 16 elements should be 4 from Znver4. --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 1 + llvm/test/Analysis/CostModel/X86/cast.ll | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 49631f38017a..cd40b1d3b093 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -2232,6 +2232,7 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, + { ISD::FP_EXTEND, MVT::v16f64, MVT::v16f32, 4 }, // 2*vcvtps2pd+vextractf64x4 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd diff --git a/llvm/test/Analysis/CostModel/X86/cast.ll b/llvm/test/Analysis/CostModel/X86/cast.ll index e0173e9df4dc..64ed9bed13f3 100644 --- a/llvm/test/Analysis/CostModel/X86/cast.ll +++ b/llvm/test/Analysis/CostModel/X86/cast.ll @@ -632,7 +632,7 @@ define void @fp_conv(<8 x float> %a, <16 x float>%b, <4 x float> %c) { ; AVX512-LABEL: 'fp_conv' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %A1 = fpext <4 x float> %c to <4 x double> ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %A2 = fpext <8 x float> %a to <8 x double> -; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %A3 = fpext <16 x float> %b to <16 x double> +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %A3 = fpext <16 x float> %b to <16 x double> ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %A4 = fptrunc <4 x double> undef to <4 x float> ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %A5 = fptrunc <8 x double> undef to <8 x float> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -- GitLab From 8d982e509bf61fab1df58eaf3582138fc3c331b2 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Jan 2024 17:09:34 -0800 Subject: [PATCH 133/652] [test][hwasan] Test function name in summaries #77391 (#77397) Push #77391 into the main. --- .../TestCases/Linux/aligned_alloc-alignment.cpp | 2 +- .../hwasan/TestCases/Linux/pvalloc-overflow.cpp | 2 +- .../TestCases/Posix/posix_memalign-alignment.cpp | 2 +- .../hwasan/TestCases/allocator_returns_null.cpp | 16 ++++++++-------- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp b/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp index 429760ba0e19..ad5b7616e8a7 100644 --- a/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp +++ b/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp @@ -14,7 +14,7 @@ int main() { // CHECK: ERROR: HWAddressSanitizer: invalid alignment requested in aligned_alloc: 17 // CHECK: {{#0 0x.* in .*}}{{aligned_alloc|memalign}} // CHECK: {{#1 0x.* in main .*aligned_alloc-alignment.cpp:}}[[@LINE-3]] - // CHECK: SUMMARY: HWAddressSanitizer: invalid-aligned-alloc-alignment + // CHECK: SUMMARY: HWAddressSanitizer: invalid-aligned-alloc-alignment {{.*}} in aligned_alloc printf("pointer after failed aligned_alloc: %zd\n", (size_t)p); // CHECK-NULL: pointer after failed aligned_alloc: 0 diff --git a/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp b/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp index b0b1ed3b798c..bd9f34a0dac9 100644 --- a/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp +++ b/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp @@ -39,6 +39,6 @@ int main(int argc, char *argv[]) { // CHECK: {{ERROR: HWAddressSanitizer: pvalloc parameters overflow: size .* rounded up to system page size .* cannot be represented in type size_t}} // CHECK: {{#0 0x.* in .*pvalloc}} // CHECK: {{#1 0x.* in main .*pvalloc-overflow.cpp:}} -// CHECK: SUMMARY: HWAddressSanitizer: pvalloc-overflow +// CHECK: SUMMARY: HWAddressSanitizer: pvalloc-overflow {{.*}} in pvalloc // CHECK-NULL: errno: 12 diff --git a/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp b/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp index eb9355f6da72..029e086f99ad 100644 --- a/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp +++ b/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp @@ -11,7 +11,7 @@ int main() { // CHECK: ERROR: HWAddressSanitizer: invalid alignment requested in posix_memalign: 17 // CHECK: {{#0 0x.* in .*posix_memalign}} // CHECK: {{#1 0x.* in main .*posix_memalign-alignment.cpp:}}[[@LINE-3]] - // CHECK: SUMMARY: HWAddressSanitizer: invalid-posix-memalign-alignment + // CHECK: SUMMARY: HWAddressSanitizer: invalid-posix-memalign-alignment {{.*}} in posix_memalign printf("pointer after failed posix_memalign: %zd\n", (size_t)p); // CHECK-NULL: pointer after failed posix_memalign: 42 diff --git a/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp b/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp index aa98076bf91e..18ee9406d146 100644 --- a/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp +++ b/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp @@ -87,21 +87,21 @@ int main(int argc, char **argv) { } // CHECK-mCRASH: malloc: -// CHECK-mCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big +// CHECK-mCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in malloc // CHECK-cCRASH: calloc: -// CHECK-cCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big +// CHECK-cCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in calloc // CHECK-coCRASH: calloc-overflow: -// CHECK-coCRASH: SUMMARY: HWAddressSanitizer: calloc-overflow +// CHECK-coCRASH: SUMMARY: HWAddressSanitizer: calloc-overflow {{.*}} in calloc // CHECK-rCRASH: realloc: -// CHECK-rCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big +// CHECK-rCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in realloc // CHECK-mrCRASH: realloc-after-malloc: -// CHECK-mrCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big +// CHECK-mrCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in realloc // CHECK-nCRASH: new: -// CHECK-nCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big +// CHECK-nCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in operator new // CHECK-nCRASH-OOM: new: -// CHECK-nCRASH-OOM: SUMMARY: HWAddressSanitizer: out-of-memory +// CHECK-nCRASH-OOM: SUMMARY: HWAddressSanitizer: out-of-memory {{.*}} in operator new // CHECK-nnCRASH: new-nothrow: -// CHECK-nnCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big +// CHECK-nnCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in operator new // CHECK-mNULL: malloc: // CHECK-mNULL: errno: 12 -- GitLab From c54a8ac35ab0fe3b7d204dc9867bf05fcb1775cd Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Mon, 8 Jan 2024 17:12:26 -0800 Subject: [PATCH 134/652] [Sema] Use StringRef::ltrim (NFC) --- clang/lib/Sema/SemaChecking.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index f13164dc0638..74f8f626fb16 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -18376,7 +18376,7 @@ static bool isSetterLikeSelector(Selector sel) { if (sel.isUnarySelector()) return false; StringRef str = sel.getNameForSlot(0); - while (!str.empty() && str.front() == '_') str = str.substr(1); + str = str.ltrim('_'); if (str.starts_with("set")) str = str.substr(3); else if (str.starts_with("add")) { -- GitLab From 898093638043e465a9099829e32614f38cf3e1a8 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Jan 2024 17:15:16 -0800 Subject: [PATCH 135/652] [msan] Unwind stack before fatal reports (#77168) Msan does not unwind stack in malloc without origins, but we still need trace for fatal errors. --- compiler-rt/lib/msan/msan.h | 11 ++++++++ compiler-rt/lib/msan/msan_allocator.cpp | 11 +++++++- compiler-rt/lib/msan/msan_new_delete.cpp | 26 ++++++++++++------- .../TestCases/max_allocation_size.cpp | 10 ++++++- 4 files changed, 46 insertions(+), 12 deletions(-) diff --git a/compiler-rt/lib/msan/msan.h b/compiler-rt/lib/msan/msan.h index 753e6b260734..710447a3e1a3 100644 --- a/compiler-rt/lib/msan/msan.h +++ b/compiler-rt/lib/msan/msan.h @@ -322,6 +322,17 @@ const int STACK_TRACE_TAG_VPTR = STACK_TRACE_TAG_FIELDS + 1; stack.Unwind(pc, bp, nullptr, common_flags()->fast_unwind_on_fatal); \ } +#define GET_FATAL_STACK_TRACE \ + GET_FATAL_STACK_TRACE_PC_BP(StackTrace::GetCurrentPc(), GET_CURRENT_FRAME()) + +// Unwind the stack for fatal error, as the parameter `stack` is +// empty without origins. +#define GET_FATAL_STACK_TRACE_IF_EMPTY(STACK) \ + if (msan_inited && (STACK)->size == 0) { \ + (STACK)->Unwind(StackTrace::GetCurrentPc(), GET_CURRENT_FRAME(), nullptr, \ + common_flags()->fast_unwind_on_fatal); \ + } + class ScopedThreadLocalStateBackup { public: ScopedThreadLocalStateBackup() { Backup(); } diff --git a/compiler-rt/lib/msan/msan_allocator.cpp b/compiler-rt/lib/msan/msan_allocator.cpp index 987c894c79d4..0b2dd2b2f188 100644 --- a/compiler-rt/lib/msan/msan_allocator.cpp +++ b/compiler-rt/lib/msan/msan_allocator.cpp @@ -180,16 +180,18 @@ void MsanThreadLocalMallocStorage::CommitBack() { static void *MsanAllocate(BufferedStackTrace *stack, uptr size, uptr alignment, bool zeroise) { - if (size > max_malloc_size) { + if (UNLIKELY(size > max_malloc_size)) { if (AllocatorMayReturnNull()) { Report("WARNING: MemorySanitizer failed to allocate 0x%zx bytes\n", size); return nullptr; } + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportAllocationSizeTooBig(size, max_malloc_size, stack); } if (UNLIKELY(IsRssLimitExceeded())) { if (AllocatorMayReturnNull()) return nullptr; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportRssLimitExceeded(stack); } MsanThread *t = GetCurrentThread(); @@ -206,6 +208,7 @@ static void *MsanAllocate(BufferedStackTrace *stack, uptr size, uptr alignment, SetAllocatorOutOfMemory(); if (AllocatorMayReturnNull()) return nullptr; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportOutOfMemory(size, stack); } Metadata *meta = @@ -288,6 +291,7 @@ static void *MsanCalloc(BufferedStackTrace *stack, uptr nmemb, uptr size) { if (UNLIKELY(CheckForCallocOverflow(size, nmemb))) { if (AllocatorMayReturnNull()) return nullptr; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportCallocOverflow(nmemb, size, stack); } return MsanAllocate(stack, nmemb * size, sizeof(u64), true); @@ -344,6 +348,7 @@ void *msan_reallocarray(void *ptr, uptr nmemb, uptr size, errno = errno_ENOMEM; if (AllocatorMayReturnNull()) return nullptr; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportReallocArrayOverflow(nmemb, size, stack); } return msan_realloc(ptr, nmemb * size, stack); @@ -359,6 +364,7 @@ void *msan_pvalloc(uptr size, BufferedStackTrace *stack) { errno = errno_ENOMEM; if (AllocatorMayReturnNull()) return nullptr; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportPvallocOverflow(size, stack); } // pvalloc(0) should allocate one page. @@ -371,6 +377,7 @@ void *msan_aligned_alloc(uptr alignment, uptr size, BufferedStackTrace *stack) { errno = errno_EINVAL; if (AllocatorMayReturnNull()) return nullptr; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportInvalidAlignedAllocAlignment(size, alignment, stack); } return SetErrnoOnNull(MsanAllocate(stack, size, alignment, false)); @@ -381,6 +388,7 @@ void *msan_memalign(uptr alignment, uptr size, BufferedStackTrace *stack) { errno = errno_EINVAL; if (AllocatorMayReturnNull()) return nullptr; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportInvalidAllocationAlignment(alignment, stack); } return SetErrnoOnNull(MsanAllocate(stack, size, alignment, false)); @@ -391,6 +399,7 @@ int msan_posix_memalign(void **memptr, uptr alignment, uptr size, if (UNLIKELY(!CheckPosixMemalignAlignment(alignment))) { if (AllocatorMayReturnNull()) return errno_EINVAL; + GET_FATAL_STACK_TRACE_IF_EMPTY(stack); ReportInvalidPosixMemalignAlignment(alignment, stack); } void *ptr = MsanAllocate(stack, size, alignment, false); diff --git a/compiler-rt/lib/msan/msan_new_delete.cpp b/compiler-rt/lib/msan/msan_new_delete.cpp index d4e95c0f6513..7daa55474b7d 100644 --- a/compiler-rt/lib/msan/msan_new_delete.cpp +++ b/compiler-rt/lib/msan/msan_new_delete.cpp @@ -30,16 +30,22 @@ namespace std { // TODO(alekseys): throw std::bad_alloc instead of dying on OOM. -#define OPERATOR_NEW_BODY(nothrow) \ - GET_MALLOC_STACK_TRACE; \ - void *res = msan_malloc(size, &stack);\ - if (!nothrow && UNLIKELY(!res)) ReportOutOfMemory(size, &stack);\ - return res -#define OPERATOR_NEW_BODY_ALIGN(nothrow) \ - GET_MALLOC_STACK_TRACE;\ - void *res = msan_memalign((uptr)align, size, &stack);\ - if (!nothrow && UNLIKELY(!res)) ReportOutOfMemory(size, &stack);\ - return res; +# define OPERATOR_NEW_BODY(nothrow) \ + GET_MALLOC_STACK_TRACE; \ + void *res = msan_malloc(size, &stack); \ + if (!nothrow && UNLIKELY(!res)) { \ + GET_FATAL_STACK_TRACE_IF_EMPTY(&stack); \ + ReportOutOfMemory(size, &stack); \ + } \ + return res +# define OPERATOR_NEW_BODY_ALIGN(nothrow) \ + GET_MALLOC_STACK_TRACE; \ + void *res = msan_memalign((uptr)align, size, &stack); \ + if (!nothrow && UNLIKELY(!res)) { \ + GET_FATAL_STACK_TRACE_IF_EMPTY(&stack); \ + ReportOutOfMemory(size, &stack); \ + } \ + return res; INTERCEPTOR_ATTRIBUTE void *operator new(size_t size) { OPERATOR_NEW_BODY(false /*nothrow*/); } diff --git a/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp b/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp index ace28965f3c1..c74f241c32b7 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp @@ -35,7 +35,7 @@ // RUN: | FileCheck %s --check-prefix=CHECK-nnCRASH // RUN: %env_tool_opts=max_allocation_size_mb=2:allocator_may_return_null=1 \ // RUN: %run %t new-nothrow 2>&1 | FileCheck %s --check-prefix=CHECK-NULL -// RUN: %env_tool_opts=max_allocation_size_mb=2:allocator_may_return_null=0 \ +// RUN: %env_tool_opts=max_allocation_size_mb=2:allocator_may_return_null=0:fast_unwind_on_malloc=0 \ // RUN: not %run %t strndup 2>&1 | FileCheck %s --check-prefix=CHECK-sCRASH // RUN: %env_tool_opts=max_allocation_size_mb=2:allocator_may_return_null=1 \ // RUN: %run %t strndup 2>&1 | FileCheck %s --check-prefix=CHECK-NULL @@ -123,20 +123,28 @@ int main(int Argc, char **Argv) { } // CHECK-mCRASH: malloc: +// CHECK-mCRASH: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-mCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} // CHECK-cCRASH: calloc: +// CHECK-cCRASH: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-cCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} // CHECK-rCRASH: realloc: +// CHECK-rCRASH: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-rCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} // CHECK-mrCRASH: realloc-after-malloc: +// CHECK-mrCRASH: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-mrCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} // CHECK-nCRASH: new: +// CHECK-nCRASH: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-nCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} // CHECK-nCRASH-OOM: new: +// CHECK-nCRASH-OOM: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-nCRASH-OOM: {{SUMMARY: .*Sanitizer: out-of-memory}} // CHECK-nnCRASH: new-nothrow: +// CHECK-nnCRASH: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-nnCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} // CHECK-sCRASH: strndup: +// CHECK-sCRASH: #{{[0-9]+.*}}max_allocation_size.cpp // CHECK-sCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} // CHECK-NULL: {{malloc|calloc|calloc-overflow|realloc|realloc-after-malloc|new-nothrow|strndup}} -- GitLab From 2b3baffb4720d4ddc7ddd7080f5ea624230b9324 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Mon, 8 Jan 2024 17:24:47 -0800 Subject: [PATCH 136/652] [Analysis] Use StringRef::rtrim (NFC) --- clang/lib/Analysis/PathDiagnostic.cpp | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/clang/lib/Analysis/PathDiagnostic.cpp b/clang/lib/Analysis/PathDiagnostic.cpp index 0cb03943c547..79f337a91ec8 100644 --- a/clang/lib/Analysis/PathDiagnostic.cpp +++ b/clang/lib/Analysis/PathDiagnostic.cpp @@ -50,12 +50,7 @@ using namespace clang; using namespace ento; -static StringRef StripTrailingDots(StringRef s) { - for (StringRef::size_type i = s.size(); i != 0; --i) - if (s[i - 1] != '.') - return s.substr(0, i); - return {}; -} +static StringRef StripTrailingDots(StringRef s) { return s.rtrim('.'); } PathDiagnosticPiece::PathDiagnosticPiece(StringRef s, Kind k, DisplayHint hint) -- GitLab From 7dd20637c801b429f2dd1040941d00141459d64e Mon Sep 17 00:00:00 2001 From: Ben Shi <2283975856@qq.com> Date: Tue, 9 Jan 2024 09:27:57 +0800 Subject: [PATCH 137/652] Improve modeling of 'getcwd' in the StdLibraryFunctionsChecker (#77040) 1. Improve the 'errno' modeling. 2. Improve constraints of the arguments. --- clang/docs/ReleaseNotes.rst | 5 +++-- .../Checkers/StdLibraryFunctionsChecker.cpp | 13 ++++++++++++- clang/test/Analysis/errno-stdlibraryfunctions.c | 15 +++++++++++++++ 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index c9b577bd549b..803eb2f7c74c 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1150,9 +1150,10 @@ Improvements ^^^^^^^^^^^^ - Improved the ``unix.StdCLibraryFunctions`` checker by modeling more - functions like ``send``, ``recv``, ``readlink``, ``fflush``, ``mkdtemp`` and - ``errno`` behavior. + functions like ``send``, ``recv``, ``readlink``, ``fflush``, ``mkdtemp``, + ``getcwd`` and ``errno`` behavior. (`52ac71f92d38 `_, + `#77040 `_, `#76671 `_, `#71373 `_, `#76557 `_, diff --git a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp index 20068653d530..034825d88a44 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp @@ -2516,10 +2516,21 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( .ArgConstraint(NotNull(ArgNo(0)))); // char *getcwd(char *buf, size_t size); - // FIXME: Improve for errno modeling. addToFunctionSummaryMap( "getcwd", Signature(ArgTypes{CharPtrTy, SizeTy}, RetType{CharPtrTy}), Summary(NoEvalCall) + .Case({ArgumentCondition(1, WithinRange, Range(1, SizeMax)), + ReturnValueCondition(BO_EQ, ArgNo(0))}, + ErrnoMustNotBeChecked, GenericSuccessMsg) + .Case({ArgumentCondition(1, WithinRange, SingleValue(0)), + IsNull(Ret)}, + ErrnoNEZeroIrrelevant, "Assuming that argument 'size' is 0") + .Case({ArgumentCondition(1, WithinRange, Range(1, SizeMax)), + IsNull(Ret)}, + ErrnoNEZeroIrrelevant, GenericFailureMsg) + .ArgConstraint(NotNull(ArgNo(0))) + .ArgConstraint( + BufferSize(/*Buffer*/ ArgNo(0), /*BufSize*/ ArgNo(1))) .ArgConstraint( ArgumentCondition(1, WithinRange, Range(0, SizeMax)))); diff --git a/clang/test/Analysis/errno-stdlibraryfunctions.c b/clang/test/Analysis/errno-stdlibraryfunctions.c index 80e14c4e2923..9e3d07e7aa88 100644 --- a/clang/test/Analysis/errno-stdlibraryfunctions.c +++ b/clang/test/Analysis/errno-stdlibraryfunctions.c @@ -74,3 +74,18 @@ void errno_mkdtemp(char *template) { if (errno) {} // expected-warning{{An undefined value may be read from 'errno'}} } } + +void errno_getcwd(char *Buf, size_t Sz) { + char *Path = getcwd(Buf, Sz); + if (Sz == 0) { + clang_analyzer_eval(errno != 0); // expected-warning{{TRUE}} + clang_analyzer_eval(Path == NULL); // expected-warning{{TRUE}} + if (errno) {} // no warning + } else if (Path == NULL) { + clang_analyzer_eval(errno != 0); // expected-warning{{TRUE}} + if (errno) {} // no warning + } else { + clang_analyzer_eval(Path == Buf); // expected-warning{{TRUE}} + if (errno) {} // expected-warning{{An undefined value may be read from 'errno'}} + } +} -- GitLab From af1fdcc343d1c850d73f7dd47493ffb9a18d596b Mon Sep 17 00:00:00 2001 From: wangpc Date: Tue, 9 Jan 2024 11:06:33 +0800 Subject: [PATCH 138/652] [doc][StackMaps] Fix typo --- llvm/docs/StackMaps.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/StackMaps.rst b/llvm/docs/StackMaps.rst index 826393bd2918..d94274138eb2 100644 --- a/llvm/docs/StackMaps.rst +++ b/llvm/docs/StackMaps.rst @@ -514,4 +514,4 @@ Supported Architectures Support for StackMap generation and the related intrinsics requires some code for each backend. Today, only a subset of LLVM's backends are supported. The currently supported architectures are X86_64, -PowerPC, Aarch64 and SystemZ. +PowerPC, AArch64 and SystemZ. -- GitLab From 96c4f1034cc3a93dafa9f8541548249deb813b78 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Tue, 9 Jan 2024 11:12:44 +0800 Subject: [PATCH 139/652] [RISCV] Add support predicating for ANDN/ORN/XNOR with short-forward-branch-opt. (#77077) ANDN/ORN/XNOR are like other ALU instructions. It should be able to be predicated by the cpu that supports short-forward-branch. --- .../Target/RISCV/RISCVExpandPseudoInsts.cpp | 6 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 + llvm/lib/Target/RISCV/RISCVInstrInfo.td | 17 ++ .../CodeGen/RISCV/short-forward-branch-opt.ll | 162 ++++++++++++++++-- 4 files changed, 179 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp index a39f0671a6dc..103a2e2da7b9 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -135,6 +135,9 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB, case RISCV::PseudoCCSLLIW: case RISCV::PseudoCCSRLIW: case RISCV::PseudoCCSRAIW: + case RISCV::PseudoCCANDN: + case RISCV::PseudoCCORN: + case RISCV::PseudoCCXNOR: return expandCCOp(MBB, MBBI, NextMBBI); case RISCV::PseudoVSETVLI: case RISCV::PseudoVSETVLIX0: @@ -227,6 +230,9 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB, case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break; case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break; case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break; + case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break; + case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break; + case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break; } BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg) .add(MI.getOperand(5)) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index a24e8b2d18cb..351f48c1708e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1346,6 +1346,10 @@ unsigned getPredicatedOpcode(unsigned Opcode) { case RISCV::SLLIW: return RISCV::PseudoCCSLLIW; break; case RISCV::SRLIW: return RISCV::PseudoCCSRLIW; break; case RISCV::SRAIW: return RISCV::PseudoCCSRAIW; break; + + case RISCV::ANDN: return RISCV::PseudoCCANDN; break; + case RISCV::ORN: return RISCV::PseudoCCORN; break; + case RISCV::XNOR: return RISCV::PseudoCCXNOR; break; } return RISCV::INSTRUCTION_LIST_END; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index e274e9f3898f..792e0bbdf581 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1519,6 +1519,23 @@ def PseudoCCSRAIW : Pseudo<(outs GPR:$dst), GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; + +// Zbb/Zbkb instructions +def PseudoCCANDN : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCORN : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCXNOR : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; } multiclass SelectCC_GPR_rrirr { diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll index d007c245d21b..d2ddbe99000e 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+c,+zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=NOSFB %s -; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV64SFB %s -; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond \ +; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond,+zbb \ ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=SFB,ZICOND %s -; RUN: llc -mtriple=riscv32 -mcpu=sifive-e76 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mcpu=sifive-e76 -mattr=+zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV32SFB %s ; The sifive-7-series can predicate a mv. @@ -1462,9 +1462,8 @@ entry: define signext i32 @abs_i32(i32 signext %x) { ; NOSFB-LABEL: abs_i32: ; NOSFB: # %bb.0: -; NOSFB-NEXT: sraiw a1, a0, 31 -; NOSFB-NEXT: xor a0, a0, a1 -; NOSFB-NEXT: subw a0, a0, a1 +; NOSFB-NEXT: negw a1, a0 +; NOSFB-NEXT: max a0, a0, a1 ; NOSFB-NEXT: ret ; ; RV64SFB-LABEL: abs_i32: @@ -1498,9 +1497,8 @@ declare i32 @llvm.abs.i32(i32, i1) define i64 @abs_i64(i64 %x) { ; NOSFB-LABEL: abs_i64: ; NOSFB: # %bb.0: -; NOSFB-NEXT: srai a1, a0, 63 -; NOSFB-NEXT: xor a0, a0, a1 -; NOSFB-NEXT: sub a0, a0, a1 +; NOSFB-NEXT: neg a1, a0 +; NOSFB-NEXT: max a0, a0, a1 ; NOSFB-NEXT: ret ; ; RV64SFB-LABEL: abs_i64: @@ -1536,3 +1534,147 @@ define i64 @abs_i64(i64 %x) { ret i64 %a } declare i64 @llvm.abs.i64(i64, i1) + +define i64 @select_andn(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) { +; NOSFB-LABEL: select_andn: +; NOSFB: # %bb.0: # %entry +; NOSFB-NEXT: bnez a3, .LBB36_2 +; NOSFB-NEXT: # %bb.1: # %entry +; NOSFB-NEXT: andn a2, a0, a1 +; NOSFB-NEXT: .LBB36_2: # %entry +; NOSFB-NEXT: mv a0, a2 +; NOSFB-NEXT: ret +; +; RV64SFB-LABEL: select_andn: +; RV64SFB: # %bb.0: # %entry +; RV64SFB-NEXT: bnez a3, .LBB36_2 +; RV64SFB-NEXT: # %bb.1: # %entry +; RV64SFB-NEXT: andn a2, a0, a1 +; RV64SFB-NEXT: .LBB36_2: # %entry +; RV64SFB-NEXT: mv a0, a2 +; RV64SFB-NEXT: ret +; +; ZICOND-LABEL: select_andn: +; ZICOND: # %bb.0: # %entry +; ZICOND-NEXT: bnez a3, .LBB36_2 +; ZICOND-NEXT: # %bb.1: # %entry +; ZICOND-NEXT: andn a2, a0, a1 +; ZICOND-NEXT: .LBB36_2: # %entry +; ZICOND-NEXT: mv a0, a2 +; ZICOND-NEXT: ret +; +; RV32SFB-LABEL: select_andn: +; RV32SFB: # %bb.0: # %entry +; RV32SFB-NEXT: bnez a6, .LBB36_2 +; RV32SFB-NEXT: # %bb.1: # %entry +; RV32SFB-NEXT: andn a4, a0, a2 +; RV32SFB-NEXT: .LBB36_2: # %entry +; RV32SFB-NEXT: bnez a6, .LBB36_4 +; RV32SFB-NEXT: # %bb.3: # %entry +; RV32SFB-NEXT: andn a5, a1, a3 +; RV32SFB-NEXT: .LBB36_4: # %entry +; RV32SFB-NEXT: mv a0, a4 +; RV32SFB-NEXT: mv a1, a5 +; RV32SFB-NEXT: ret +entry: + %0 = xor i64 %B, -1 + %1 = and i64 %A, %0 + %2 = select i1 %cond, i64 %C, i64 %1 + ret i64 %2 +} + +define i64 @select_orn(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) { +; NOSFB-LABEL: select_orn: +; NOSFB: # %bb.0: # %entry +; NOSFB-NEXT: bnez a3, .LBB37_2 +; NOSFB-NEXT: # %bb.1: # %entry +; NOSFB-NEXT: orn a2, a0, a1 +; NOSFB-NEXT: .LBB37_2: # %entry +; NOSFB-NEXT: mv a0, a2 +; NOSFB-NEXT: ret +; +; RV64SFB-LABEL: select_orn: +; RV64SFB: # %bb.0: # %entry +; RV64SFB-NEXT: bnez a3, .LBB37_2 +; RV64SFB-NEXT: # %bb.1: # %entry +; RV64SFB-NEXT: orn a2, a0, a1 +; RV64SFB-NEXT: .LBB37_2: # %entry +; RV64SFB-NEXT: mv a0, a2 +; RV64SFB-NEXT: ret +; +; ZICOND-LABEL: select_orn: +; ZICOND: # %bb.0: # %entry +; ZICOND-NEXT: bnez a3, .LBB37_2 +; ZICOND-NEXT: # %bb.1: # %entry +; ZICOND-NEXT: orn a2, a0, a1 +; ZICOND-NEXT: .LBB37_2: # %entry +; ZICOND-NEXT: mv a0, a2 +; ZICOND-NEXT: ret +; +; RV32SFB-LABEL: select_orn: +; RV32SFB: # %bb.0: # %entry +; RV32SFB-NEXT: bnez a6, .LBB37_2 +; RV32SFB-NEXT: # %bb.1: # %entry +; RV32SFB-NEXT: orn a4, a0, a2 +; RV32SFB-NEXT: .LBB37_2: # %entry +; RV32SFB-NEXT: bnez a6, .LBB37_4 +; RV32SFB-NEXT: # %bb.3: # %entry +; RV32SFB-NEXT: orn a5, a1, a3 +; RV32SFB-NEXT: .LBB37_4: # %entry +; RV32SFB-NEXT: mv a0, a4 +; RV32SFB-NEXT: mv a1, a5 +; RV32SFB-NEXT: ret +entry: + %0 = xor i64 %B, -1 + %1 = or i64 %A, %0 + %2 = select i1 %cond, i64 %C, i64 %1 + ret i64 %2 +} + +define i64 @select_xnor(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) { +; NOSFB-LABEL: select_xnor: +; NOSFB: # %bb.0: # %entry +; NOSFB-NEXT: bnez a3, .LBB38_2 +; NOSFB-NEXT: # %bb.1: # %entry +; NOSFB-NEXT: xnor a2, a0, a1 +; NOSFB-NEXT: .LBB38_2: # %entry +; NOSFB-NEXT: mv a0, a2 +; NOSFB-NEXT: ret +; +; RV64SFB-LABEL: select_xnor: +; RV64SFB: # %bb.0: # %entry +; RV64SFB-NEXT: bnez a3, .LBB38_2 +; RV64SFB-NEXT: # %bb.1: # %entry +; RV64SFB-NEXT: xnor a2, a0, a1 +; RV64SFB-NEXT: .LBB38_2: # %entry +; RV64SFB-NEXT: mv a0, a2 +; RV64SFB-NEXT: ret +; +; ZICOND-LABEL: select_xnor: +; ZICOND: # %bb.0: # %entry +; ZICOND-NEXT: bnez a3, .LBB38_2 +; ZICOND-NEXT: # %bb.1: # %entry +; ZICOND-NEXT: xnor a2, a0, a1 +; ZICOND-NEXT: .LBB38_2: # %entry +; ZICOND-NEXT: mv a0, a2 +; ZICOND-NEXT: ret +; +; RV32SFB-LABEL: select_xnor: +; RV32SFB: # %bb.0: # %entry +; RV32SFB-NEXT: bnez a6, .LBB38_2 +; RV32SFB-NEXT: # %bb.1: # %entry +; RV32SFB-NEXT: xnor a4, a0, a2 +; RV32SFB-NEXT: .LBB38_2: # %entry +; RV32SFB-NEXT: bnez a6, .LBB38_4 +; RV32SFB-NEXT: # %bb.3: # %entry +; RV32SFB-NEXT: xnor a5, a1, a3 +; RV32SFB-NEXT: .LBB38_4: # %entry +; RV32SFB-NEXT: mv a0, a4 +; RV32SFB-NEXT: mv a1, a5 +; RV32SFB-NEXT: ret +entry: + %0 = xor i64 %A, %B + %1 = xor i64 %0, -1 + %2 = select i1 %cond, i64 %C, i64 %1 + ret i64 %2 +} -- GitLab From b856e77b2df212d740bfedc984572d812d07ecc8 Mon Sep 17 00:00:00 2001 From: James Y Knight Date: Mon, 8 Jan 2024 22:34:28 -0500 Subject: [PATCH 140/652] Set MaxAtomicSizeInBitsSupported for remaining targets. (#75703) Targets affected: - NVPTX and BPF: set to 64 bits. - ARC, Lanai, and MSP430: set to 0 (they don't implement atomics). Those which didn't yet add AtomicExpandPass to their pass pipeline now do so. This will result in larger atomic operations getting expanded to `__atomic_*` libcalls via AtomicExpandPass. On all these targets, this now matches what Clang already does in the frontend. The only targets which do not configure AtomicExpandPass now are: - DirectX and SPIRV: they aren't normal backends. - AVR: a single-cpu architecture with no privileged/user divide, which could implement all atomics by disabling/enabling interrupts, regardless of size/alignment. Will be addressed by future work. --- llvm/lib/Target/ARC/ARCISelLowering.cpp | 2 + llvm/lib/Target/ARC/ARCTargetMachine.cpp | 7 +++ llvm/lib/Target/BPF/BPFISelLowering.cpp | 1 + llvm/lib/Target/BPF/BPFTargetMachine.cpp | 2 + llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 2 + llvm/lib/Target/Lanai/LanaiTargetMachine.cpp | 7 +++ llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 1 + .../lib/Target/MSP430/MSP430TargetMachine.cpp | 7 +++ llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 1 + llvm/test/CodeGen/ARC/atomic-oversize.ll | 11 +++++ llvm/test/CodeGen/BPF/atomic-oversize.ll | 12 +++++ llvm/test/CodeGen/Lanai/atomic-oversize.ll | 11 +++++ llvm/test/CodeGen/MSP430/atomic-oversize.ll | 11 +++++ llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll | 48 ++++++++++--------- 14 files changed, 101 insertions(+), 22 deletions(-) create mode 100644 llvm/test/CodeGen/ARC/atomic-oversize.ll create mode 100644 llvm/test/CodeGen/BPF/atomic-oversize.ll create mode 100644 llvm/test/CodeGen/Lanai/atomic-oversize.ll create mode 100644 llvm/test/CodeGen/MSP430/atomic-oversize.ll diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp index 2265f5db6737..5dd343d97b80 100644 --- a/llvm/lib/Target/ARC/ARCISelLowering.cpp +++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp @@ -174,6 +174,8 @@ ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM, setOperationAction(ISD::READCYCLECOUNTER, MVT::i32, Legal); setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isTypeLegal(MVT::i64) ? Legal : Custom); + + setMaxAtomicSizeInBitsSupported(0); } const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const { diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index d4ae3255b32a..4f612ae623b9 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -57,6 +57,7 @@ public: return getTM(); } + void addIRPasses() override; bool addInstSelector() override; void addPreEmitPass() override; void addPreRegAlloc() override; @@ -68,6 +69,12 @@ TargetPassConfig *ARCTargetMachine::createPassConfig(PassManagerBase &PM) { return new ARCPassConfig(*this, PM); } +void ARCPassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); + + TargetPassConfig::addIRPasses(); +} + bool ARCPassConfig::addInstSelector() { addPass(createARCISelDag(getARCTargetMachine(), getOptLevel())); return false; diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index 2fe86e75ddae..4d8ace7c1ece 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -151,6 +151,7 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, } setBooleanContents(ZeroOrOneBooleanContent); + setMaxAtomicSizeInBitsSupported(64); // Function alignments setMinFunctionAlignment(Align(8)); diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 897368417163..8a6e7ae3663e 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -149,7 +149,9 @@ void BPFTargetMachine::registerPassBuilderCallbacks( } void BPFPassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); addPass(createBPFCheckAndAdjustIR()); + TargetPassConfig::addIRPasses(); } diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index 17d7ffb586f4..06de2ff1ae3e 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -166,6 +166,8 @@ LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM, // Booleans always contain 0 or 1. setBooleanContents(ZeroOrOneBooleanContent); + + setMaxAtomicSizeInBitsSupported(0); } SDValue LanaiTargetLowering::LowerOperation(SDValue Op, diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index 039182b3ffe6..33479720183b 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -93,6 +93,7 @@ public: return getTM(); } + void addIRPasses() override; bool addInstSelector() override; void addPreSched2() override; void addPreEmitPass() override; @@ -104,6 +105,12 @@ LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) { return new LanaiPassConfig(*this, &PassManager); } +void LanaiPassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); + + TargetPassConfig::addIRPasses(); +} + // Install an instruction selector pass. bool LanaiPassConfig::addInstSelector() { addPass(createLanaiISelDag(getLanaiTargetMachine())); diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index d3b59138a5a9..1ed19f9381ec 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -333,6 +333,7 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM, setMinFunctionAlignment(Align(2)); setPrefFunctionAlignment(Align(2)); + setMaxAtomicSizeInBitsSupported(0); } SDValue MSP430TargetLowering::LowerOperation(SDValue Op, diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index 39e0658eb70d..283de46e57d5 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -65,6 +65,7 @@ public: return getTM(); } + void addIRPasses() override; bool addInstSelector() override; void addPreEmitPass() override; }; @@ -81,6 +82,12 @@ MachineFunctionInfo *MSP430TargetMachine::createMachineFunctionInfo( F, STI); } +void MSP430PassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); + + TargetPassConfig::addIRPasses(); +} + bool MSP430PassConfig::addInstSelector() { // Install an instruction selector. addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel())); diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index e8f36bf50a1b..de6de3214521 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -854,6 +854,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, computeRegisterProperties(STI.getRegisterInfo()); setMinCmpXchgSizeInBits(32); + setMaxAtomicSizeInBitsSupported(64); } const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const { diff --git a/llvm/test/CodeGen/ARC/atomic-oversize.ll b/llvm/test/CodeGen/ARC/atomic-oversize.ll new file mode 100644 index 000000000000..678c1ae649c6 --- /dev/null +++ b/llvm/test/CodeGen/ARC/atomic-oversize.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=arc < %s | FileCheck %s + +; Native atomics are unsupported, so all are oversize. +define void @test(ptr %a) nounwind { +; CHECK-LABEL: test: +; CHECK: bl @__atomic_load_1 +; CHECK: bl @__atomic_store_1 + %1 = load atomic i8, ptr %a seq_cst, align 16 + store atomic i8 %1, ptr %a seq_cst, align 16 + ret void +} diff --git a/llvm/test/CodeGen/BPF/atomic-oversize.ll b/llvm/test/CodeGen/BPF/atomic-oversize.ll new file mode 100644 index 000000000000..187f0964d4fb --- /dev/null +++ b/llvm/test/CodeGen/BPF/atomic-oversize.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple=bpf < %s | FileCheck %s +; XFAIL: * +; Doesn't currently build, with error 'only small returns supported'. + +define void @test(ptr %a) nounwind { +; CHECK-LABEL: test: +; CHECK: call __atomic_load_16 +; CHECK: call __atomic_store_16 + %1 = load atomic i128, ptr %a monotonic, align 16 + store atomic i128 %1, ptr %a monotonic, align 16 + ret void +} diff --git a/llvm/test/CodeGen/Lanai/atomic-oversize.ll b/llvm/test/CodeGen/Lanai/atomic-oversize.ll new file mode 100644 index 000000000000..93307ac8184d --- /dev/null +++ b/llvm/test/CodeGen/Lanai/atomic-oversize.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=lanai < %s | FileCheck %s + +; Native atomics are unsupported, so all are oversize. +define void @test(ptr %a) nounwind { +; CHECK-LABEL: test: +; CHECK: bt __atomic_load_1 +; CHECK: bt __atomic_store_1 + %1 = load atomic i8, ptr %a monotonic, align 16 + store atomic i8 %1, ptr %a monotonic, align 16 + ret void +} diff --git a/llvm/test/CodeGen/MSP430/atomic-oversize.ll b/llvm/test/CodeGen/MSP430/atomic-oversize.ll new file mode 100644 index 000000000000..53b668ab25b5 --- /dev/null +++ b/llvm/test/CodeGen/MSP430/atomic-oversize.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=msp430 < %s | FileCheck %s + +; Native atomics are unsupported, so all are oversize. +define void @test(ptr %a) nounwind { +; CHECK-LABEL: test: +; CHECK: call #__atomic_load_1 +; CHECK: call #__atomic_store_1 + %1 = load atomic i8, ptr %a monotonic, align 16 + store atomic i8 %1, ptr %a monotonic, align 16 + ret void +} diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll index d4fd62059204..b65c281092dd 100644 --- a/llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll +++ b/llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll @@ -140,26 +140,30 @@ entry: ret void } -; TODO: We might still want to test other types, such as i128. Currently the -; backend doesn't support them. Atomic expand only supports expansion to cas of -; the same bitwidth, which means even after expansion, the back end still -; doesn't support the instruction. Here we still put the tests. Remove the -; comment once we have proper support, either from atomic expand or backend. - -; define void @bitwise_i128(ptr %0, i128 %1) { -; entry: -; %2 = atomicrmw and ptr %0, i128 %1 monotonic, align 16 -; %3 = atomicrmw or ptr %0, i128 %1 monotonic, align 16 -; %4 = atomicrmw xor ptr %0, i128 %1 monotonic, align 16 -; %5 = atomicrmw xchg ptr %0, i128 %1 monotonic, align 16 -; ret void -; } +; CHECK-LABEL: bitwise_i128 +define void @bitwise_i128(ptr %0, i128 %1) { +entry: + ; ALL: __atomic_fetch_and_16 + %2 = atomicrmw and ptr %0, i128 %1 monotonic, align 16 + ; ALL: __atomic_fetch_or_16 + %3 = atomicrmw or ptr %0, i128 %1 monotonic, align 16 + ; ALL: __atomic_fetch_xor_16 + %4 = atomicrmw xor ptr %0, i128 %1 monotonic, align 16 + ; ALL: __atomic_exchange_16 + %5 = atomicrmw xchg ptr %0, i128 %1 monotonic, align 16 + ret void +} -; define void @minmax_i128(ptr %0, i128 %1) { -; entry: -; %2 = atomicrmw min ptr %0, i128 %1 monotonic, align 16 -; %3 = atomicrmw max ptr %0, i128 %1 monotonic, align 16 -; %4 = atomicrmw umin ptr %0, i128 %1 monotonic, align 16 -; %5 = atomicrmw umax ptr %0, i128 %1 monotonic, align 16 -; ret void -; } +; CHECK-LABEL: minmax_i128 +define void @minmax_i128(ptr %0, i128 %1) { +entry: + ; ALL: __atomic_compare_exchange_16 + %2 = atomicrmw min ptr %0, i128 %1 monotonic, align 16 + ; ALL: __atomic_compare_exchange_16 + %3 = atomicrmw max ptr %0, i128 %1 monotonic, align 16 + ; ALL: __atomic_compare_exchange_16 + %4 = atomicrmw umin ptr %0, i128 %1 monotonic, align 16 + ; ALL: __atomic_compare_exchange_16 + %5 = atomicrmw umax ptr %0, i128 %1 monotonic, align 16 + ret void +} -- GitLab From a8e9dceb49a9824b9326a16acedd19dbb29add2f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Jan 2024 19:36:15 -0800 Subject: [PATCH 141/652] [RISCV] Use getELen() instead of hardcoded 64 in lowerBUILD_VECTOR. (#77355) This is needed to properly support Zve32x. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +- .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 448 +++++++++++++----- 2 files changed, 320 insertions(+), 132 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 135b41c7a085..a5d49dcece3c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -3657,10 +3657,10 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG, // would require bit-manipulation instructions to construct the splat value. SmallVector Sequence; const auto *BV = cast(Op); - if (VT.isInteger() && EltBitSize < 64 && + if (VT.isInteger() && EltBitSize < Subtarget.getELen() && ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) && BV->getRepeatedSequence(Sequence) && - (Sequence.size() * EltBitSize) <= 64) { + (Sequence.size() * EltBitSize) <= Subtarget.getELen()) { unsigned SeqLen = Sequence.size(); MVT ViaIntVT = MVT::getIntegerVT(EltBitSize * SeqLen); assert((ViaIntVT == MVT::i16 || ViaIntVT == MVT::i32 || diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 5dfa3835cad0..faeca5ef801a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V +; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32 define void @buildvec_vid_v16i8(ptr %x) { ; CHECK-LABEL: buildvec_vid_v16i8: @@ -296,11 +297,22 @@ define <4 x i64> @buildvec_vid_step1_add0_v4i64() { ; RV32-NEXT: vsext.vf4 v8, v10 ; RV32-NEXT: ret ; -; RV64-LABEL: buildvec_vid_step1_add0_v4i64: -; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; RV64-NEXT: vid.v v8 -; RV64-NEXT: ret +; RV64V-LABEL: buildvec_vid_step1_add0_v4i64: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; RV64V-NEXT: vid.v v8 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_vid_step1_add0_v4i64: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: li a1, 3 +; RV64ZVE32-NEXT: sd a1, 24(a0) +; RV64ZVE32-NEXT: li a1, 2 +; RV64ZVE32-NEXT: sd a1, 16(a0) +; RV64ZVE32-NEXT: li a1, 1 +; RV64ZVE32-NEXT: sd a1, 8(a0) +; RV64ZVE32-NEXT: sd zero, 0(a0) +; RV64ZVE32-NEXT: ret ret <4 x i64> } @@ -314,12 +326,23 @@ define <4 x i64> @buildvec_vid_step2_add0_v4i64() { ; RV32-NEXT: vsext.vf4 v8, v10 ; RV32-NEXT: ret ; -; RV64-LABEL: buildvec_vid_step2_add0_v4i64: -; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; RV64-NEXT: vid.v v8 -; RV64-NEXT: vadd.vv v8, v8, v8 -; RV64-NEXT: ret +; RV64V-LABEL: buildvec_vid_step2_add0_v4i64: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; RV64V-NEXT: vid.v v8 +; RV64V-NEXT: vadd.vv v8, v8, v8 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_vid_step2_add0_v4i64: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: li a1, 6 +; RV64ZVE32-NEXT: sd a1, 24(a0) +; RV64ZVE32-NEXT: li a1, 4 +; RV64ZVE32-NEXT: sd a1, 16(a0) +; RV64ZVE32-NEXT: li a1, 2 +; RV64ZVE32-NEXT: sd a1, 8(a0) +; RV64ZVE32-NEXT: sd zero, 0(a0) +; RV64ZVE32-NEXT: ret ret <4 x i64> } @@ -420,21 +443,47 @@ define <2 x i8> @buildvec_dominant0_v2i8() { } define <2 x i8> @buildvec_dominant1_v2i8() { -; CHECK-LABEL: buildvec_dominant1_v2i8: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-NEXT: vmv.v.i v8, -1 -; CHECK-NEXT: ret +; RV32-LABEL: buildvec_dominant1_v2i8: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV32-NEXT: vmv.v.i v8, -1 +; RV32-NEXT: ret +; +; RV64V-LABEL: buildvec_dominant1_v2i8: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV64V-NEXT: vmv.v.i v8, -1 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_dominant1_v2i8: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma +; RV64ZVE32-NEXT: vmv.v.i v8, -1 +; RV64ZVE32-NEXT: ret ret <2 x i8> } define <2 x i8> @buildvec_dominant2_v2i8() { -; CHECK-LABEL: buildvec_dominant2_v2i8: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-NEXT: vid.v v8 -; CHECK-NEXT: vrsub.vi v8, v8, 0 -; CHECK-NEXT: ret +; RV32-LABEL: buildvec_dominant2_v2i8: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV32-NEXT: vid.v v8 +; RV32-NEXT: vrsub.vi v8, v8, 0 +; RV32-NEXT: ret +; +; RV64V-LABEL: buildvec_dominant2_v2i8: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV64V-NEXT: vid.v v8 +; RV64V-NEXT: vrsub.vi v8, v8, 0 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_dominant2_v2i8: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma +; RV64ZVE32-NEXT: vid.v v8 +; RV64ZVE32-NEXT: vrsub.vi v8, v8, 0 +; RV64ZVE32-NEXT: ret ret <2 x i8> } @@ -448,16 +497,25 @@ define void @buildvec_dominant0_v2i32(ptr %x) { ; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; -; RV64-LABEL: buildvec_dominant0_v2i32: -; RV64: # %bb.0: -; RV64-NEXT: lui a1, %hi(.LCPI38_0) -; RV64-NEXT: ld a1, %lo(.LCPI38_0)(a1) -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vmv.v.i v8, -1 -; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma -; RV64-NEXT: vmv.s.x v8, a1 -; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: ret +; RV64V-LABEL: buildvec_dominant0_v2i32: +; RV64V: # %bb.0: +; RV64V-NEXT: lui a1, %hi(.LCPI38_0) +; RV64V-NEXT: ld a1, %lo(.LCPI38_0)(a1) +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vmv.v.i v8, -1 +; RV64V-NEXT: vsetvli zero, zero, e64, m1, tu, ma +; RV64V-NEXT: vmv.s.x v8, a1 +; RV64V-NEXT: vse64.v v8, (a0) +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_dominant0_v2i32: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: lui a1, %hi(.LCPI38_0) +; RV64ZVE32-NEXT: ld a1, %lo(.LCPI38_0)(a1) +; RV64ZVE32-NEXT: li a2, -1 +; RV64ZVE32-NEXT: sd a2, 8(a0) +; RV64ZVE32-NEXT: sd a1, 0(a0) +; RV64ZVE32-NEXT: ret store <2 x i64> , ptr %x ret void } @@ -472,14 +530,23 @@ define void @buildvec_dominant1_optsize_v2i32(ptr %x) optsize { ; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; -; RV64-LABEL: buildvec_dominant1_optsize_v2i32: -; RV64: # %bb.0: -; RV64-NEXT: lui a1, %hi(.LCPI39_0) -; RV64-NEXT: addi a1, a1, %lo(.LCPI39_0) -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vle64.v v8, (a1) -; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: ret +; RV64V-LABEL: buildvec_dominant1_optsize_v2i32: +; RV64V: # %bb.0: +; RV64V-NEXT: lui a1, %hi(.LCPI39_0) +; RV64V-NEXT: addi a1, a1, %lo(.LCPI39_0) +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vle64.v v8, (a1) +; RV64V-NEXT: vse64.v v8, (a0) +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_dominant1_optsize_v2i32: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: lui a1, %hi(.LCPI39_0) +; RV64ZVE32-NEXT: ld a1, %lo(.LCPI39_0)(a1) +; RV64ZVE32-NEXT: li a2, -1 +; RV64ZVE32-NEXT: sd a2, 8(a0) +; RV64ZVE32-NEXT: sd a1, 0(a0) +; RV64ZVE32-NEXT: ret store <2 x i64> , ptr %x ret void } @@ -497,15 +564,35 @@ define void @buildvec_seq_v8i8_v4i16(ptr %x) { } define void @buildvec_seq_v8i8_v2i32(ptr %x) { -; CHECK-LABEL: buildvec_seq_v8i8_v2i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a1, 48 -; CHECK-NEXT: addi a1, a1, 513 -; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-NEXT: vmv.v.x v8, a1 -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-NEXT: vse8.v v8, (a0) -; CHECK-NEXT: ret +; RV32-LABEL: buildvec_seq_v8i8_v2i32: +; RV32: # %bb.0: +; RV32-NEXT: lui a1, 48 +; RV32-NEXT: addi a1, a1, 513 +; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; RV32-NEXT: vmv.v.x v8, a1 +; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV32-NEXT: vse8.v v8, (a0) +; RV32-NEXT: ret +; +; RV64V-LABEL: buildvec_seq_v8i8_v2i32: +; RV64V: # %bb.0: +; RV64V-NEXT: lui a1, 48 +; RV64V-NEXT: addi a1, a1, 513 +; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; RV64V-NEXT: vmv.v.x v8, a1 +; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64V-NEXT: vse8.v v8, (a0) +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_seq_v8i8_v2i32: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: lui a1, 48 +; RV64ZVE32-NEXT: addi a1, a1, 513 +; RV64ZVE32-NEXT: vsetivli zero, 2, e32, m1, ta, ma +; RV64ZVE32-NEXT: vmv.v.x v8, a1 +; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64ZVE32-NEXT: vse8.v v8, (a0) +; RV64ZVE32-NEXT: ret store <8 x i8> , ptr %x ret void } @@ -520,15 +607,24 @@ define void @buildvec_seq_v16i8_v2i64(ptr %x) { ; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; -; RV64-LABEL: buildvec_seq_v16i8_v2i64: -; RV64: # %bb.0: -; RV64-NEXT: lui a1, %hi(.LCPI42_0) -; RV64-NEXT: addi a1, a1, %lo(.LCPI42_0) -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vlse64.v v8, (a1), zero -; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; RV64-NEXT: vse8.v v8, (a0) -; RV64-NEXT: ret +; RV64V-LABEL: buildvec_seq_v16i8_v2i64: +; RV64V: # %bb.0: +; RV64V-NEXT: lui a1, %hi(.LCPI42_0) +; RV64V-NEXT: addi a1, a1, %lo(.LCPI42_0) +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vlse64.v v8, (a1), zero +; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; RV64V-NEXT: vse8.v v8, (a0) +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_seq_v16i8_v2i64: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: lui a1, %hi(.LCPI42_0) +; RV64ZVE32-NEXT: addi a1, a1, %lo(.LCPI42_0) +; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; RV64ZVE32-NEXT: vle8.v v8, (a1) +; RV64ZVE32-NEXT: vse8.v v8, (a0) +; RV64ZVE32-NEXT: ret store <16 x i8> , ptr %x ret void } @@ -544,36 +640,79 @@ define void @buildvec_seq2_v16i8_v2i64(ptr %x) { ; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; -; RV64-LABEL: buildvec_seq2_v16i8_v2i64: -; RV64: # %bb.0: -; RV64-NEXT: lui a1, 528432 -; RV64-NEXT: addiw a1, a1, 513 -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vmv.v.x v8, a1 -; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; RV64-NEXT: vse8.v v8, (a0) -; RV64-NEXT: ret +; RV64V-LABEL: buildvec_seq2_v16i8_v2i64: +; RV64V: # %bb.0: +; RV64V-NEXT: lui a1, 528432 +; RV64V-NEXT: addiw a1, a1, 513 +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vmv.v.x v8, a1 +; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; RV64V-NEXT: vse8.v v8, (a0) +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_seq2_v16i8_v2i64: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: lui a1, %hi(.LCPI43_0) +; RV64ZVE32-NEXT: addi a1, a1, %lo(.LCPI43_0) +; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; RV64ZVE32-NEXT: vle8.v v8, (a1) +; RV64ZVE32-NEXT: vse8.v v8, (a0) +; RV64ZVE32-NEXT: ret store <16 x i8> , ptr %x ret void } define void @buildvec_seq_v9i8(ptr %x) { -; CHECK-LABEL: buildvec_seq_v9i8: -; CHECK: # %bb.0: -; CHECK-NEXT: li a1, 73 -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-NEXT: vmv.s.x v0, a1 -; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-NEXT: vmv.v.i v8, 3 -; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: li a1, 146 -; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; CHECK-NEXT: vmv.s.x v0, a1 -; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma -; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 -; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma -; CHECK-NEXT: vse8.v v8, (a0) -; CHECK-NEXT: ret +; RV32-LABEL: buildvec_seq_v9i8: +; RV32: # %bb.0: +; RV32-NEXT: li a1, 73 +; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; RV32-NEXT: vmv.s.x v0, a1 +; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; RV32-NEXT: vmv.v.i v8, 3 +; RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; RV32-NEXT: li a1, 146 +; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV32-NEXT: vmv.s.x v0, a1 +; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; RV32-NEXT: vmerge.vim v8, v8, 2, v0 +; RV32-NEXT: vsetivli zero, 9, e8, m1, ta, ma +; RV32-NEXT: vse8.v v8, (a0) +; RV32-NEXT: ret +; +; RV64V-LABEL: buildvec_seq_v9i8: +; RV64V: # %bb.0: +; RV64V-NEXT: li a1, 73 +; RV64V-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; RV64V-NEXT: vmv.s.x v0, a1 +; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; RV64V-NEXT: vmv.v.i v8, 3 +; RV64V-NEXT: vmerge.vim v8, v8, 1, v0 +; RV64V-NEXT: li a1, 146 +; RV64V-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV64V-NEXT: vmv.s.x v0, a1 +; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; RV64V-NEXT: vmerge.vim v8, v8, 2, v0 +; RV64V-NEXT: vsetivli zero, 9, e8, m1, ta, ma +; RV64V-NEXT: vse8.v v8, (a0) +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: buildvec_seq_v9i8: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: li a1, 73 +; RV64ZVE32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma +; RV64ZVE32-NEXT: vmv.s.x v0, a1 +; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; RV64ZVE32-NEXT: vmv.v.i v8, 3 +; RV64ZVE32-NEXT: vmerge.vim v8, v8, 1, v0 +; RV64ZVE32-NEXT: li a1, 146 +; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV64ZVE32-NEXT: vmv.s.x v0, a1 +; RV64ZVE32-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; RV64ZVE32-NEXT: vmerge.vim v8, v8, 2, v0 +; RV64ZVE32-NEXT: vsetivli zero, 9, e8, m1, ta, ma +; RV64ZVE32-NEXT: vse8.v v8, (a0) +; RV64ZVE32-NEXT: ret store <9 x i8> , ptr %x ret void } @@ -863,14 +1002,22 @@ define <4 x i64> @v4xi64_exact(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) ; RV32-NEXT: vslide1down.vx v8, v8, a3 ; RV32-NEXT: ret ; -; RV64-LABEL: v4xi64_exact: -; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vmv.v.x v8, a2 -; RV64-NEXT: vslide1down.vx v9, v8, a3 -; RV64-NEXT: vmv.v.x v8, a0 -; RV64-NEXT: vslide1down.vx v8, v8, a1 -; RV64-NEXT: ret +; RV64V-LABEL: v4xi64_exact: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vmv.v.x v8, a2 +; RV64V-NEXT: vslide1down.vx v9, v8, a3 +; RV64V-NEXT: vmv.v.x v8, a0 +; RV64V-NEXT: vslide1down.vx v8, v8, a1 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: v4xi64_exact: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: sd a4, 24(a0) +; RV64ZVE32-NEXT: sd a3, 16(a0) +; RV64ZVE32-NEXT: sd a2, 8(a0) +; RV64ZVE32-NEXT: sd a1, 0(a0) +; RV64ZVE32-NEXT: ret %v1 = insertelement <4 x i64> poison, i64 %a, i32 0 %v2 = insertelement <4 x i64> %v1, i64 %b, i32 1 %v3 = insertelement <4 x i64> %v2, i64 %c, i32 2 @@ -907,18 +1054,31 @@ define <8 x i64> @v8xi64_exact(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i ; RV32-NEXT: vslide1down.vx v11, v11, t0 ; RV32-NEXT: ret ; -; RV64-LABEL: v8xi64_exact: -; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vmv.v.x v8, a2 -; RV64-NEXT: vslide1down.vx v9, v8, a3 -; RV64-NEXT: vmv.v.x v8, a0 -; RV64-NEXT: vslide1down.vx v8, v8, a1 -; RV64-NEXT: vmv.v.x v10, a4 -; RV64-NEXT: vslide1down.vx v10, v10, a5 -; RV64-NEXT: vmv.v.x v11, a6 -; RV64-NEXT: vslide1down.vx v11, v11, a7 -; RV64-NEXT: ret +; RV64V-LABEL: v8xi64_exact: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vmv.v.x v8, a2 +; RV64V-NEXT: vslide1down.vx v9, v8, a3 +; RV64V-NEXT: vmv.v.x v8, a0 +; RV64V-NEXT: vslide1down.vx v8, v8, a1 +; RV64V-NEXT: vmv.v.x v10, a4 +; RV64V-NEXT: vslide1down.vx v10, v10, a5 +; RV64V-NEXT: vmv.v.x v11, a6 +; RV64V-NEXT: vslide1down.vx v11, v11, a7 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: v8xi64_exact: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: ld t0, 0(sp) +; RV64ZVE32-NEXT: sd t0, 56(a0) +; RV64ZVE32-NEXT: sd a7, 48(a0) +; RV64ZVE32-NEXT: sd a6, 40(a0) +; RV64ZVE32-NEXT: sd a5, 32(a0) +; RV64ZVE32-NEXT: sd a4, 24(a0) +; RV64ZVE32-NEXT: sd a3, 16(a0) +; RV64ZVE32-NEXT: sd a2, 8(a0) +; RV64ZVE32-NEXT: sd a1, 0(a0) +; RV64ZVE32-NEXT: ret %v1 = insertelement <8 x i64> poison, i64 %a, i32 0 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 1 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 2 @@ -946,16 +1106,28 @@ define <8 x i64> @v8xi64_exact_equal_halves(i64 %a, i64 %b, i64 %c, i64 %d) vsca ; RV32-NEXT: vmv.v.v v11, v9 ; RV32-NEXT: ret ; -; RV64-LABEL: v8xi64_exact_equal_halves: -; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vmv.v.x v8, a2 -; RV64-NEXT: vslide1down.vx v9, v8, a3 -; RV64-NEXT: vmv.v.x v8, a0 -; RV64-NEXT: vslide1down.vx v8, v8, a1 -; RV64-NEXT: vmv.v.v v10, v8 -; RV64-NEXT: vmv.v.v v11, v9 -; RV64-NEXT: ret +; RV64V-LABEL: v8xi64_exact_equal_halves: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vmv.v.x v8, a2 +; RV64V-NEXT: vslide1down.vx v9, v8, a3 +; RV64V-NEXT: vmv.v.x v8, a0 +; RV64V-NEXT: vslide1down.vx v8, v8, a1 +; RV64V-NEXT: vmv.v.v v10, v8 +; RV64V-NEXT: vmv.v.v v11, v9 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: v8xi64_exact_equal_halves: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: sd a4, 56(a0) +; RV64ZVE32-NEXT: sd a3, 48(a0) +; RV64ZVE32-NEXT: sd a2, 40(a0) +; RV64ZVE32-NEXT: sd a1, 32(a0) +; RV64ZVE32-NEXT: sd a4, 24(a0) +; RV64ZVE32-NEXT: sd a3, 16(a0) +; RV64ZVE32-NEXT: sd a2, 8(a0) +; RV64ZVE32-NEXT: sd a1, 0(a0) +; RV64ZVE32-NEXT: ret %v1 = insertelement <8 x i64> poison, i64 %a, i32 0 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 1 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 2 @@ -981,14 +1153,22 @@ define <8 x i64> @v8xi64_exact_undef_suffix(i64 %a, i64 %b, i64 %c, i64 %d) vsca ; RV32-NEXT: vslide1down.vx v8, v8, a3 ; RV32-NEXT: ret ; -; RV64-LABEL: v8xi64_exact_undef_suffix: -; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vmv.v.x v8, a2 -; RV64-NEXT: vslide1down.vx v9, v8, a3 -; RV64-NEXT: vmv.v.x v8, a0 -; RV64-NEXT: vslide1down.vx v8, v8, a1 -; RV64-NEXT: ret +; RV64V-LABEL: v8xi64_exact_undef_suffix: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vmv.v.x v8, a2 +; RV64V-NEXT: vslide1down.vx v9, v8, a3 +; RV64V-NEXT: vmv.v.x v8, a0 +; RV64V-NEXT: vslide1down.vx v8, v8, a1 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: v8xi64_exact_undef_suffix: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: sd a4, 24(a0) +; RV64ZVE32-NEXT: sd a3, 16(a0) +; RV64ZVE32-NEXT: sd a2, 8(a0) +; RV64ZVE32-NEXT: sd a1, 0(a0) +; RV64ZVE32-NEXT: ret %v1 = insertelement <8 x i64> poison, i64 %a, i32 0 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 1 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 2 @@ -1010,14 +1190,22 @@ define <8 x i64> @v8xi64_exact_undef_prefix(i64 %a, i64 %b, i64 %c, i64 %d) vsca ; RV32-NEXT: vslide1down.vx v10, v8, a3 ; RV32-NEXT: ret ; -; RV64-LABEL: v8xi64_exact_undef_prefix: -; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RV64-NEXT: vmv.v.x v8, a2 -; RV64-NEXT: vslide1down.vx v11, v8, a3 -; RV64-NEXT: vmv.v.x v8, a0 -; RV64-NEXT: vslide1down.vx v10, v8, a1 -; RV64-NEXT: ret +; RV64V-LABEL: v8xi64_exact_undef_prefix: +; RV64V: # %bb.0: +; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; RV64V-NEXT: vmv.v.x v8, a2 +; RV64V-NEXT: vslide1down.vx v11, v8, a3 +; RV64V-NEXT: vmv.v.x v8, a0 +; RV64V-NEXT: vslide1down.vx v10, v8, a1 +; RV64V-NEXT: ret +; +; RV64ZVE32-LABEL: v8xi64_exact_undef_prefix: +; RV64ZVE32: # %bb.0: +; RV64ZVE32-NEXT: sd a4, 56(a0) +; RV64ZVE32-NEXT: sd a3, 48(a0) +; RV64ZVE32-NEXT: sd a2, 40(a0) +; RV64ZVE32-NEXT: sd a1, 32(a0) +; RV64ZVE32-NEXT: ret %v1 = insertelement <8 x i64> poison, i64 %a, i32 4 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 5 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 6 -- GitLab From 700a1928bbc2bac557384e20efa56bc61ee64b86 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Jan 2024 19:40:27 -0800 Subject: [PATCH 142/652] [test][sanitizer] Check summary function and a single stack frame --- .../TestCases/allocator_returns_null.cpp | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp b/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp index e9d4601a8ac8..9f8e12ff6aa0 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp @@ -94,21 +94,29 @@ int main(int argc, char **argv) { } // CHECK-mCRASH: malloc: -// CHECK-mCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-mCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-mCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc // CHECK-cCRASH: calloc: -// CHECK-cCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-cCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-cCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc // CHECK-coCRASH: calloc-overflow: -// CHECK-coCRASH: {{SUMMARY: .*Sanitizer: calloc-overflow}} +// CHECK-coCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-coCRASH: {{SUMMARY: .*Sanitizer: calloc-overflow.*}} in {{.*}}lloc // CHECK-rCRASH: realloc: -// CHECK-rCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-rCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-rCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc // CHECK-mrCRASH: realloc-after-malloc: -// CHECK-mrCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-mrCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-mrCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc // CHECK-nCRASH: new: -// CHECK-nCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-nCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-nCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{operator new|.*lloc}} // CHECK-nCRASH-OOM: new: -// CHECK-nCRASH-OOM: {{SUMMARY: .*Sanitizer: out-of-memory}} +// CHECK-nCRASH-O#{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-nCRASH-OOM: {{SUMMARY: .*Sanitizer: out-of-memory.*}} in {{operator new|.*lloc}} // CHECK-nnCRASH: new-nothrow: -// CHECK-nnCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-nnCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp +// CHECK-nnCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{operator new|.*lloc}} // CHECK-NULL: {{malloc|calloc|calloc-overflow|realloc|realloc-after-malloc|new-nothrow}} // CHECK-NULL: errno: 12, x: 0 -- GitLab From b43c50490c5964b3b1aa1b95a9025a5b5942a46e Mon Sep 17 00:00:00 2001 From: Justin Fargnoli <34139864+justinfargnoli@users.noreply.github.com> Date: Mon, 8 Jan 2024 20:19:18 -0800 Subject: [PATCH 143/652] [mlir] Declare promised interfaces for the ConvertToLLVM extension (#76341) This PR adds promised interface declarations for `ConvertToLLVMPatternInterface` in all the dialects that support the `ConvertToLLVM` dialect extension. Promised interfaces allow a dialect to declare that it will have an implementation of a particular interface, crashing the program if one isn't provided when the interface is used. --- mlir/lib/Dialect/Arith/IR/ArithDialect.cpp | 2 ++ mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp | 2 ++ mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp | 2 ++ mlir/lib/Dialect/Func/IR/FuncOps.cpp | 2 ++ mlir/lib/Dialect/Index/IR/IndexDialect.cpp | 2 ++ mlir/lib/Dialect/Math/IR/MathDialect.cpp | 2 ++ mlir/lib/Dialect/MemRef/IR/MemRefDialect.cpp | 2 ++ mlir/lib/Dialect/UB/IR/UBOps.cpp | 2 ++ 8 files changed, 16 insertions(+) diff --git a/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp b/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp index ed4b91cbe516..745c5706a838 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp +++ b/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" #include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/Dialect/UB/IR/UBOps.h" #include "mlir/IR/Builders.h" @@ -44,6 +45,7 @@ void arith::ArithDialect::initialize() { #include "mlir/Dialect/Arith/IR/ArithOpsAttributes.cpp.inc" >(); addInterfaces(); + declarePromisedInterface(); } /// Materialize an integer or floating point constant. diff --git a/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp b/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp index da57d254676e..e54b3a71bbc3 100644 --- a/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp +++ b/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" #include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/Dialect/Complex/IR/Complex.h" #include "mlir/IR/Builders.h" @@ -26,6 +27,7 @@ void complex::ComplexDialect::initialize() { #define GET_ATTRDEF_LIST #include "mlir/Dialect/Complex/IR/ComplexAttributes.cpp.inc" >(); + declarePromisedInterface(); } Operation *complex::ComplexDialect::materializeConstant(OpBuilder &builder, diff --git a/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp b/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp index fab6f3416999..999c04e48ee1 100644 --- a/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp +++ b/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp @@ -8,6 +8,7 @@ #include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h" +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" #include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/IR/AffineExpr.h" #include "mlir/IR/AffineMap.h" @@ -67,6 +68,7 @@ void ControlFlowDialect::initialize() { #include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.cpp.inc" >(); addInterfaces(); + declarePromisedInterface(); } //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/Func/IR/FuncOps.cpp b/mlir/lib/Dialect/Func/IR/FuncOps.cpp index ca9b19c66595..d18ec279e85c 100644 --- a/mlir/lib/Dialect/Func/IR/FuncOps.cpp +++ b/mlir/lib/Dialect/Func/IR/FuncOps.cpp @@ -8,6 +8,7 @@ #include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" #include "mlir/IR/BuiltinOps.h" #include "mlir/IR/BuiltinTypes.h" #include "mlir/IR/IRMapping.h" @@ -41,6 +42,7 @@ void FuncDialect::initialize() { #include "mlir/Dialect/Func/IR/FuncOps.cpp.inc" >(); declarePromisedInterface(); + declarePromisedInterface(); } /// Materialize a single constant operation from a given attribute value with diff --git a/mlir/lib/Dialect/Index/IR/IndexDialect.cpp b/mlir/lib/Dialect/Index/IR/IndexDialect.cpp index 130157f35781..d631afa63b9a 100644 --- a/mlir/lib/Dialect/Index/IR/IndexDialect.cpp +++ b/mlir/lib/Dialect/Index/IR/IndexDialect.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "mlir/Dialect/Index/IR/IndexDialect.h" +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" using namespace mlir; using namespace mlir::index; @@ -18,6 +19,7 @@ using namespace mlir::index; void IndexDialect::initialize() { registerAttributes(); registerOperations(); + declarePromisedInterface(); } //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/Math/IR/MathDialect.cpp b/mlir/lib/Dialect/Math/IR/MathDialect.cpp index 9cf47ac71306..a71b24cb1b97 100644 --- a/mlir/lib/Dialect/Math/IR/MathDialect.cpp +++ b/mlir/lib/Dialect/Math/IR/MathDialect.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" #include "mlir/Dialect/Math/IR/Math.h" #include "mlir/Dialect/UB/IR/UBOps.h" #include "mlir/Transforms/InliningUtils.h" @@ -34,4 +35,5 @@ void mlir::math::MathDialect::initialize() { #include "mlir/Dialect/Math/IR/MathOps.cpp.inc" >(); addInterfaces(); + declarePromisedInterface(); } diff --git a/mlir/lib/Dialect/MemRef/IR/MemRefDialect.cpp b/mlir/lib/Dialect/MemRef/IR/MemRefDialect.cpp index 8304000bbcfd..d71669a274b8 100644 --- a/mlir/lib/Dialect/MemRef/IR/MemRefDialect.cpp +++ b/mlir/lib/Dialect/MemRef/IR/MemRefDialect.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" #include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Interfaces/SideEffectInterfaces.h" @@ -41,6 +42,7 @@ void mlir::memref::MemRefDialect::initialize() { #include "mlir/Dialect/MemRef/IR/MemRefOps.cpp.inc" >(); addInterfaces(); + declarePromisedInterface(); } /// Finds the unique dealloc operation (if one exists) for `allocValue`. diff --git a/mlir/lib/Dialect/UB/IR/UBOps.cpp b/mlir/lib/Dialect/UB/IR/UBOps.cpp index e0cd5dafcfa6..3a2010cdcb5c 100644 --- a/mlir/lib/Dialect/UB/IR/UBOps.cpp +++ b/mlir/lib/Dialect/UB/IR/UBOps.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "mlir/Dialect/UB/IR/UBOps.h" +#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" #include "mlir/Transforms/InliningUtils.h" #include "mlir/IR/Builders.h" @@ -45,6 +46,7 @@ void UBDialect::initialize() { #include "mlir/Dialect/UB/IR/UBOpsAttributes.cpp.inc" >(); addInterfaces(); + declarePromisedInterface(); } Operation *UBDialect::materializeConstant(OpBuilder &builder, Attribute value, -- GitLab From 3fa17954dedd59bfad9cef1778719fb6312a5949 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 8 Jan 2024 20:24:00 -0800 Subject: [PATCH 144/652] [ELF] Support R_RISCV_SET_ULEB128/R_RISCV_SUB_ULEB128 in SHF_ALLOC sections (#77261) Complement #72610 (non-SHF_ALLOC sections). GCC-generated .gcc_exception_table has the SHF_ALLOC flag and may contain R_RISCV_SET_ULEB128/R_RISCV_SUB_ULEB128 relocations. --- lld/ELF/Arch/RISCV.cpp | 42 ++++++++++++++++ lld/ELF/InputSection.cpp | 11 +---- lld/ELF/Relocations.cpp | 4 +- lld/ELF/Target.h | 10 ++++ lld/test/ELF/riscv-reloc-leb128.s | 80 ++++++++++++++++++++++++++----- 5 files changed, 124 insertions(+), 23 deletions(-) diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 898e3e45b9e7..1d3d179e5d6f 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -43,6 +43,7 @@ public: const uint8_t *loc) const override; void relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const override; + void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override; bool relaxOnce(int pass) const override; }; @@ -307,6 +308,7 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s, case R_RISCV_RELAX: return config->relax ? R_RELAX_HINT : R_NONE; case R_RISCV_SET_ULEB128: + case R_RISCV_SUB_ULEB128: return R_RISCV_LEB128; default: error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + @@ -515,6 +517,46 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { } } +void RISCV::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const { + uint64_t secAddr = sec.getOutputSection()->addr; + if (auto *s = dyn_cast(&sec)) + secAddr += s->outSecOff; + else if (auto *ehIn = dyn_cast(&sec)) + secAddr += ehIn->getParent()->outSecOff; + for (size_t i = 0, size = sec.relocs().size(); i != size; ++i) { + const Relocation &rel = sec.relocs()[i]; + uint8_t *loc = buf + rel.offset; + const uint64_t val = + sec.getRelocTargetVA(sec.file, rel.type, rel.addend, + secAddr + rel.offset, *rel.sym, rel.expr); + + switch (rel.expr) { + case R_RELAX_HINT: + break; + case R_RISCV_LEB128: + if (i + 1 < size) { + const Relocation &rel1 = sec.relocs()[i + 1]; + if (rel.type == R_RISCV_SET_ULEB128 && + rel1.type == R_RISCV_SUB_ULEB128 && rel.offset == rel1.offset) { + auto val = rel.sym->getVA(rel.addend) - rel1.sym->getVA(rel1.addend); + if (overwriteULEB128(loc, val) >= 0x80) + errorOrWarn(sec.getLocation(rel.offset) + ": ULEB128 value " + + Twine(val) + " exceeds available space; references '" + + lld::toString(*rel.sym) + "'"); + ++i; + continue; + } + } + errorOrWarn(sec.getLocation(rel.offset) + + ": R_RISCV_SET_ULEB128 not paired with R_RISCV_SUB_SET128"); + return; + default: + relocate(loc, rel, val); + break; + } + } +} + namespace { struct SymbolAnchor { uint64_t offset; diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index 5dfb57fda432..53b496bd0842 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -671,6 +671,7 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, case R_RELAX_TLS_LD_TO_LE_ABS: case R_RELAX_GOT_PC_NOPIC: case R_RISCV_ADD: + case R_RISCV_LEB128: return sym.getVA(a); case R_ADDEND: return a; @@ -875,16 +876,6 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, } } -// Overwrite a ULEB128 value and keep the original length. -static uint64_t overwriteULEB128(uint8_t *bufLoc, uint64_t val) { - while (*bufLoc & 0x80) { - *bufLoc++ = 0x80 | (val & 0x7f); - val >>= 7; - } - *bufLoc = val; - return val; -} - // This function applies relocations to sections without SHF_ALLOC bit. // Such sections are never mapped to memory at runtime. Debug sections are // an example. Relocations in non-alloc sections are much easier to diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp index 210b4d1eb1a7..9eb2e82542d3 100644 --- a/lld/ELF/Relocations.cpp +++ b/lld/ELF/Relocations.cpp @@ -988,8 +988,8 @@ bool RelocationScanner::isStaticLinkTimeConstant(RelExpr e, RelType type, if (!config->isPic) return true; - // The size of a non preemptible symbol is a constant. - if (e == R_SIZE) + // Constant when referencing a non-preemptible symbol. + if (e == R_SIZE || e == R_RISCV_LEB128) return true; // For the target and the relocation, we want to know if they are diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h index 6264ab1a3da7..af7aaff8a4c0 100644 --- a/lld/ELF/Target.h +++ b/lld/ELF/Target.h @@ -301,6 +301,16 @@ inline void write32(void *p, uint32_t v) { inline void write64(void *p, uint64_t v) { llvm::support::endian::write64(p, v, config->endianness); } + +// Overwrite a ULEB128 value and keep the original length. +inline uint64_t overwriteULEB128(uint8_t *bufLoc, uint64_t val) { + while (*bufLoc & 0x80) { + *bufLoc++ = 0x80 | (val & 0x7f); + val >>= 7; + } + *bufLoc = val; + return val; +} } // namespace elf } // namespace lld diff --git a/lld/test/ELF/riscv-reloc-leb128.s b/lld/test/ELF/riscv-reloc-leb128.s index 8198819686c3..0bdc1eb18269 100644 --- a/lld/test/ELF/riscv-reloc-leb128.s +++ b/lld/test/ELF/riscv-reloc-leb128.s @@ -1,13 +1,13 @@ # REQUIRES: riscv # RUN: rm -rf %t && split-file %s %t && cd %t # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax a.s -o a.o -# RUN: llvm-readobj -r -x .debug_rnglists -x .debug_loclists a.o | FileCheck %s --check-prefix=REL -# RUN: ld.lld -shared --gc-sections a.o -o a.so -# RUN: llvm-readelf -x .debug_rnglists -x .debug_loclists a.so | FileCheck %s +# RUN: llvm-readobj -r -x .gcc_except_table -x .debug_rnglists -x .debug_loclists a.o | FileCheck %s --check-prefix=REL +# RUN: ld.lld -shared --gc-sections --noinhibit-exec a.o -o a.so +# RUN: llvm-readelf -x .gcc_except_table -x .debug_rnglists -x .debug_loclists a.so | FileCheck %s # REL: .rela.debug_rnglists { -# REL-NEXT: 0x0 R_RISCV_SET_ULEB128 w1 0x83 -# REL-NEXT: 0x0 R_RISCV_SUB_ULEB128 w2 0x0 +# REL-NEXT: 0x0 R_RISCV_SET_ULEB128 w1 0x82 +# REL-NEXT: 0x0 R_RISCV_SUB_ULEB128 w2 0xFFFFFFFFFFFFFFFF # REL-NEXT: 0x1 R_RISCV_SET_ULEB128 w2 0x78 # REL-NEXT: 0x1 R_RISCV_SUB_ULEB128 w1 0x0 # REL-NEXT: 0x3 R_RISCV_SET_ULEB128 w1 0x89 @@ -28,12 +28,18 @@ # REL-NEXT: 0x1 R_RISCV_SUB_ULEB128 x1 0x0 # REL-NEXT: } +# REL: Hex dump of section '.gcc_except_table': +# REL-NEXT: 0x00000000 7b800181 01808001 81800180 80800181 { +# REL-NEXT: 0x00000010 808001 . # REL: Hex dump of section '.debug_rnglists': # REL-NEXT: 0x00000000 7b800181 01808001 81800180 80800181 { # REL-NEXT: 0x00000010 808001 . # REL: Hex dump of section '.debug_loclists': # REL-NEXT: 0x00000000 0008 . +# CHECK: Hex dump of section '.gcc_except_table': +# CHECK-NEXT: 0x[[#%x,]] 7ffc0085 01fcff00 858001fc ffff0085 . +# CHECK-NEXT: 0x[[#%x,]] 808001 . # CHECK: Hex dump of section '.debug_rnglists': # CHECK-NEXT: 0x00000000 7ffc0085 01fcff00 858001fc ffff0085 . # CHECK-NEXT: 0x00000010 808001 . @@ -50,21 +56,32 @@ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax sub.s -o sub.o # RUN: not ld.lld -shared sub.o 2>&1 | FileCheck %s --check-prefix=SUB -# SUB: error: sub.o:(.debug_rnglists+0x8): unknown relocation (61) against symbol w2 +# SUB: error: sub.o:(.debug_rnglists+0x8): has non-ABS relocation R_RISCV_SUB_ULEB128 against symbol 'w2' # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax unpaired1.s -o unpaired1.o -# RUN: not ld.lld -shared unpaired1.o 2>&1 | FileCheck %s --check-prefix=UNPAIRED +# RUN: not ld.lld -shared --threads=1 unpaired1.o 2>&1 | FileCheck %s --check-prefix=UNPAIRED # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax unpaired2.s -o unpaired2.o -# RUN: not ld.lld -shared unpaired2.o 2>&1 | FileCheck %s --check-prefix=UNPAIRED +# RUN: not ld.lld -shared --threads=1 unpaired2.o 2>&1 | FileCheck %s --check-prefix=UNPAIRED # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax unpaired3.s -o unpaired3.o -# RUN: not ld.lld -shared unpaired3.o 2>&1 | FileCheck %s --check-prefix=UNPAIRED +# RUN: not ld.lld -shared --threads=1 unpaired3.o 2>&1 | FileCheck %s --check-prefix=UNPAIRED +# UNPAIRED: error: {{.*}}.o:(.alloc+0x8): R_RISCV_SET_ULEB128 not paired with R_RISCV_SUB_SET128 # UNPAIRED: error: {{.*}}.o:(.debug_rnglists+0x8): R_RISCV_SET_ULEB128 not paired with R_RISCV_SUB_SET128 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax overflow.s -o overflow.o -# RUN: not ld.lld -shared overflow.o 2>&1 | FileCheck %s --check-prefix=OVERFLOW +# RUN: not ld.lld -shared --threads=1 overflow.o 2>&1 | FileCheck %s --check-prefix=OVERFLOW +# OVERFLOW: error: overflow.o:(.alloc+0x8): ULEB128 value 128 exceeds available space; references 'w2' # OVERFLOW: error: overflow.o:(.debug_rnglists+0x8): ULEB128 value 128 exceeds available space; references 'w2' +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax preemptable.s -o preemptable.o +# RUN: not ld.lld -shared --threads=1 preemptable.o 2>&1 | FileCheck %s --check-prefix=PREEMPTABLE --implicit-check-not=error: +# PREEMPTABLE: error: relocation R_RISCV_SET_ULEB128 cannot be used against symbol 'w2'; recompile with -fPIC +# PREEMPTABLE: error: relocation R_RISCV_SUB_ULEB128 cannot be used against symbol 'w1'; recompile with -fPIC + #--- a.s +.cfi_startproc +.cfi_lsda 0x1b,.LLSDA0 +.cfi_endproc + .section .text.w,"axR" w1: call foo # 4 bytes after relaxation @@ -75,8 +92,22 @@ x1: call foo # 4 bytes after relaxation x2: +.section .gcc_except_table,"a" +.LLSDA0: +.reloc ., R_RISCV_SET_ULEB128, w1+130 +.reloc ., R_RISCV_SUB_ULEB128, w2-1 # non-zero addend for SUB +.byte 0x7b +.uleb128 w2-w1+120 # initial value: 0x0180 +.uleb128 w1-w2+137 # initial value: 0x0181 +.uleb128 w2-w1+16376 # initial value: 0x018080 +.uleb128 w1-w2+16393 # initial value: 0x018081 +.uleb128 w2-w1+2097144 # initial value: 0x01808080 +.uleb128 w1-w2+2097161 # initial value: 0x01808081 + .section .debug_rnglists -.uleb128 w1-w2+131 # initial value: 0x7b +.reloc ., R_RISCV_SET_ULEB128, w1+130 +.reloc ., R_RISCV_SUB_ULEB128, w2-1 # non-zero addend for SUB +.byte 0x7b .uleb128 w2-w1+120 # initial value: 0x0180 .uleb128 w1-w2+137 # initial value: 0x0181 .uleb128 w2-w1+16376 # initial value: 0x018080 @@ -99,6 +130,10 @@ w1: call foo; w2: #--- unpaired1.s w1: call foo; w2: +.section .alloc,"a" +.quad 0 +.reloc ., R_RISCV_SET_ULEB128, w2+120 +.byte 0x7f .section .debug_rnglists .quad 0; .reloc ., R_RISCV_SET_ULEB128, w2+120 @@ -106,6 +141,11 @@ w1: call foo; w2: #--- unpaired2.s w1: call foo; w2: +.section .alloc,"a" +.quad 0 +.reloc ., R_RISCV_SET_ULEB128, w2+120 +.reloc .+1, R_RISCV_SUB_ULEB128, w1 +.byte 0x7f .section .debug_rnglists .quad 0 .reloc ., R_RISCV_SET_ULEB128, w2+120 @@ -114,6 +154,11 @@ w1: call foo; w2: #--- unpaired3.s w1: call foo; w2: +.section .alloc,"a" +.quad 0 +.reloc ., R_RISCV_SET_ULEB128, w2+120 +.reloc ., R_RISCV_SUB64, w1 +.byte 0x7f .section .debug_rnglists .quad 0 .reloc ., R_RISCV_SET_ULEB128, w2+120 @@ -122,8 +167,21 @@ w1: call foo; w2: #--- overflow.s w1: call foo; w2: +.section .alloc,"a" +.quad 0 +.reloc ., R_RISCV_SET_ULEB128, w2+124 +.reloc ., R_RISCV_SUB_ULEB128, w1 +.byte 0x7f .section .debug_rnglists .quad 0 .reloc ., R_RISCV_SET_ULEB128, w2+124 .reloc ., R_RISCV_SUB_ULEB128, w1 .byte 0x7f + +#--- preemptable.s +.globl w1, w2 +w1: call foo; w2: +.section .alloc,"a" +.uleb128 w2-w1 +.section .debug_rnglists +.uleb128 w2-w1 -- GitLab From 49c35f69ac6884a07f07e7c09ca7b79282707f49 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Mon, 8 Jan 2024 23:28:04 -0500 Subject: [PATCH 145/652] [CMake] Add support for building on illumos (#74930) illumos has an older version of the Solaris linker that does not support the GNU version script compat nor version scripts and does not support -Bsymbolic-functions. Treat illumos linker separately. The libclang/CMakeLists part lifted from NetBSD's pkgsrc. Build tested on Solaris 11.4 and OpenIndiana 2023.10. /usr/bin/ld --version ld: Software Generation Utilities - Solaris Link Editors: 5.11-1.3260 ld: Software Generation Utilities - Solaris Link Editors: 5.11-1.1790 (illumos) --- clang/tools/clang-shlib/CMakeLists.txt | 2 +- clang/tools/libclang/CMakeLists.txt | 19 +++++++++++++++---- llvm/cmake/modules/AddLLVM.cmake | 6 ++++++ llvm/tools/llvm-shlib/CMakeLists.txt | 2 +- 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/clang/tools/clang-shlib/CMakeLists.txt b/clang/tools/clang-shlib/CMakeLists.txt index aa7fcd1efed4..298d3a9d18fe 100644 --- a/clang/tools/clang-shlib/CMakeLists.txt +++ b/clang/tools/clang-shlib/CMakeLists.txt @@ -50,7 +50,7 @@ add_clang_library(clang-cpp ${_DEPS}) # Optimize function calls for default visibility definitions to avoid PLT and # reduce dynamic relocations. -if (NOT APPLE AND NOT MINGW) +if (NOT APPLE AND NOT MINGW AND NOT LLVM_LINKER_IS_SOLARISLD_ILLUMOS) target_link_options(clang-cpp PRIVATE LINKER:-Bsymbolic-functions) endif() if (MINGW OR CYGWIN) diff --git a/clang/tools/libclang/CMakeLists.txt b/clang/tools/libclang/CMakeLists.txt index 4f23065a2472..1cfc46eb1a52 100644 --- a/clang/tools/libclang/CMakeLists.txt +++ b/clang/tools/libclang/CMakeLists.txt @@ -185,11 +185,22 @@ if(ENABLE_SHARED) endif() endif() if (USE_VERSION_SCRIPT) - target_link_options(libclang PRIVATE "-Wl,--version-script,${CMAKE_CURRENT_SOURCE_DIR}/libclang.map") - # The Solaris 11.4 linker supports a subset of GNU ld version scripts, - # but requires a special option to enable it. if (${CMAKE_SYSTEM_NAME} MATCHES "SunOS") - target_link_options(libclang PRIVATE "-Wl,-z,gnu-version-script-compat") + include(CheckLinkerFlag) + # The Solaris 11.4 linker supports a subset of GNU ld version scripts, + # but requires a special option to enable it. + llvm_check_linker_flag(CXX "-Wl,-z,gnu-version-script-compat" + LINKER_SUPPORTS_Z_GNU_VERSION_SCRIPT_COMPAT) + # Older Solaris (and illumos) linker does not support GNU ld version scripts + # and does not support GNU version script compat. + if (LINKER_SUPPORTS_Z_GNU_VERSION_SCRIPT_COMPAT) + target_link_options(libclang PRIVATE "-Wl,--version-script,${CMAKE_CURRENT_SOURCE_DIR}/libclang.map") + target_link_options(libclang PRIVATE "-Wl,-z,gnu-version-script-compat") + else() + target_link_options(libclang PRIVATE "-Wl,-M,${CMAKE_CURRENT_SOURCE_DIR}/libclang.map") + endif() + else() + target_link_options(libclang PRIVATE "-Wl,--version-script,${CMAKE_CURRENT_SOURCE_DIR}/libclang.map") endif() # Ensure that libclang.so gets rebuilt when the linker script changes. set_property(SOURCE ARCMigrate.cpp APPEND PROPERTY diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake index c9bca30c8f33..14c0837c3596 100644 --- a/llvm/cmake/modules/AddLLVM.cmake +++ b/llvm/cmake/modules/AddLLVM.cmake @@ -241,6 +241,12 @@ if (NOT DEFINED LLVM_LINKER_DETECTED AND NOT WIN32) set(LLVM_LINKER_DETECTED YES CACHE INTERNAL "") set(LLVM_LINKER_IS_GNULD YES CACHE INTERNAL "") message(STATUS "Linker detection: GNU ld") + elseif("${stderr}" MATCHES "(illumos)" OR + "${stdout}" MATCHES "(illumos)") + set(LLVM_LINKER_DETECTED YES CACHE INTERNAL "") + set(LLVM_LINKER_IS_SOLARISLD YES CACHE INTERNAL "") + set(LLVM_LINKER_IS_SOLARISLD_ILLUMOS YES CACHE INTERNAL "") + message(STATUS "Linker detection: Solaris ld (illumos)") elseif("${stderr}" MATCHES "Solaris Link Editors" OR "${stdout}" MATCHES "Solaris Link Editors") set(LLVM_LINKER_DETECTED YES CACHE INTERNAL "") diff --git a/llvm/tools/llvm-shlib/CMakeLists.txt b/llvm/tools/llvm-shlib/CMakeLists.txt index 64d6f631ffad..a47a0ec84c62 100644 --- a/llvm/tools/llvm-shlib/CMakeLists.txt +++ b/llvm/tools/llvm-shlib/CMakeLists.txt @@ -49,7 +49,7 @@ if(LLVM_BUILD_LLVM_DYLIB) # Solaris ld does not accept global: *; so there is no way to version *all* global symbols set(LIB_NAMES -Wl,--version-script,${LLVM_LIBRARY_DIR}/tools/llvm-shlib/simple_version_script.map ${LIB_NAMES}) endif() - if (NOT MINGW) + if (NOT MINGW AND NOT LLVM_LINKER_IS_SOLARISLD_ILLUMOS) # Optimize function calls for default visibility definitions to avoid PLT and # reduce dynamic relocations. # Note: for -fno-pic default, the address of a function may be different from -- GitLab From f6dbd4cc5f52b6d40f98cf09af22b276b8e1f289 Mon Sep 17 00:00:00 2001 From: ZijunZhaoCCK <88353225+ZijunZhaoCCK@users.noreply.github.com> Date: Mon, 8 Jan 2024 20:46:05 -0800 Subject: [PATCH 146/652] Make clang report invalid target versions. (#75373) Clang always silently ignores garbage target versions and this makes debug harder. So clang will report when target versions are invalid. --- .../include/clang/Basic/DiagnosticDriverKinds.td | 3 +++ clang/lib/Driver/Driver.cpp | 11 +++++++++++ .../test/CodeGen/aarch64-fix-cortex-a53-835769.c | 6 +++--- .../test/Driver/aarch64-fix-cortex-a53-835769.c | 2 +- clang/test/Driver/android-version.cpp | 16 ++++++++++++++++ llvm/include/llvm/TargetParser/Triple.h | 6 ++++++ llvm/lib/TargetParser/Triple.cpp | 7 +++++-- 7 files changed, 45 insertions(+), 6 deletions(-) create mode 100644 clang/test/Driver/android-version.cpp diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 676f1a62b49d..0a8a77fadbeb 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -786,4 +786,7 @@ def warn_android_unversioned_fallback : Warning< " directories will not be used in Clang 19. Provide a versioned directory" " for the target version or lower instead.">, InGroup>; + +def err_drv_triple_version_invalid : Error< + "version '%0' in target triple '%1' is invalid">; } diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 9b2f2a374809..1889ea28079d 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -1430,6 +1430,17 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) { const ToolChain &TC = getToolChain( *UArgs, computeTargetTriple(*this, TargetTriple, *UArgs)); + if (TC.getTriple().isAndroid()) { + llvm::Triple Triple = TC.getTriple(); + StringRef TripleVersionName = Triple.getEnvironmentVersionString(); + + if (Triple.getEnvironmentVersion().empty() && TripleVersionName != "") { + Diags.Report(diag::err_drv_triple_version_invalid) + << TripleVersionName << TC.getTripleString(); + ContainsError = true; + } + } + // Report warning when arm64EC option is overridden by specified target if ((TC.getTriple().getArch() != llvm::Triple::aarch64 || TC.getTriple().getSubArch() != llvm::Triple::AArch64SubArch_arm64ec) && diff --git a/clang/test/CodeGen/aarch64-fix-cortex-a53-835769.c b/clang/test/CodeGen/aarch64-fix-cortex-a53-835769.c index 3d1a2c7aceb1..e5d70564d57b 100644 --- a/clang/test/CodeGen/aarch64-fix-cortex-a53-835769.c +++ b/clang/test/CodeGen/aarch64-fix-cortex-a53-835769.c @@ -5,13 +5,13 @@ // RUN: %clang -O3 -target aarch64-linux-eabi -mno-fix-cortex-a53-835769 %s -S -o- 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NO --check-prefix=CHECK %s -// RUN: %clang -O3 -target aarch64-android-eabi %s -S -o- \ +// RUN: %clang -O3 --target=aarch64-linux-androideabi %s -S -o- \ // RUN: | FileCheck --check-prefix=CHECK-YES --check-prefix=CHECK %s // RUN: %clang -O3 -target aarch64-linux-ohos %s -S -o- \ // RUN: | FileCheck --check-prefix=CHECK-YES --check-prefix=CHECK %s -// RUN: %clang -O3 -target aarch64-android-eabi -mfix-cortex-a53-835769 %s -S -o- \ +// RUN: %clang -O3 --target=aarch64-linux-androideabi -mfix-cortex-a53-835769 %s -S -o- \ // RUN: | FileCheck --check-prefix=CHECK-YES --check-prefix=CHECK %s -// RUN: %clang -O3 -target aarch64-android-eabi -mno-fix-cortex-a53-835769 %s -S -o- \ +// RUN: %clang -O3 --target=aarch64-linux-androideabi -mno-fix-cortex-a53-835769 %s -S -o- \ // RUN: | FileCheck --check-prefix=CHECK-NO --check-prefix=CHECK %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/Driver/aarch64-fix-cortex-a53-835769.c b/clang/test/Driver/aarch64-fix-cortex-a53-835769.c index a854920f3e6e..d7a2ad911261 100644 --- a/clang/test/Driver/aarch64-fix-cortex-a53-835769.c +++ b/clang/test/Driver/aarch64-fix-cortex-a53-835769.c @@ -5,7 +5,7 @@ // RUN: %clang --target=aarch64-linux-eabi -mno-fix-cortex-a53-835769 %s -### 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NO %s -// RUN: %clang --target=aarch64-android-eabi %s -### 2>&1 \ +// RUN: %clang --target=aarch64-linux-androideabi %s -### 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-YES %s // RUN: %clang --target=aarch64-fuchsia %s -### 2>&1 \ diff --git a/clang/test/Driver/android-version.cpp b/clang/test/Driver/android-version.cpp new file mode 100644 index 000000000000..d365b701c022 --- /dev/null +++ b/clang/test/Driver/android-version.cpp @@ -0,0 +1,16 @@ +// Check that we get the right Android version. + +// RUN: not %clang --target=aarch64-linux-androidS -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-ERROR %s + +// CHECK-ERROR: error: version 'S' in target triple 'aarch64-unknown-linux-androidS' is invalid + +// RUN: not %clang --target=armv7-linux-androideabiS -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-ERROR1 %s + +// CHECK-ERROR1: error: version 'S' in target triple 'armv7-unknown-linux-androidS' is invalid + +// RUN: %clang --target=aarch64-linux-android31 -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-TARGET %s + +// CHECK-TARGET: "aarch64-unknown-linux-android31" diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 47904621c096..95014a546f72 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -434,6 +434,12 @@ public: /// string (separated by a '-' if the environment component is present). StringRef getOSAndEnvironmentName() const; + /// Get the version component of the environment component as a single + /// string (the version after the environment). + /// + /// For example, "fooos1.2.3" would return "1.2.3". + StringRef getEnvironmentVersionString() const; + /// @} /// @name Convenience Predicates /// @{ diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index e93502187b54..b9971c25af71 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -1206,11 +1206,14 @@ static VersionTuple parseVersionFromName(StringRef Name) { } VersionTuple Triple::getEnvironmentVersion() const { + return parseVersionFromName(getEnvironmentVersionString()); +} + +StringRef Triple::getEnvironmentVersionString() const { StringRef EnvironmentName = getEnvironmentName(); StringRef EnvironmentTypeName = getEnvironmentTypeName(getEnvironment()); EnvironmentName.consume_front(EnvironmentTypeName); - - return parseVersionFromName(EnvironmentName); + return EnvironmentName; } VersionTuple Triple::getOSVersion() const { -- GitLab From b2b4ffbc9bdda617977cbece015b8ea5ac44c531 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Mon, 8 Jan 2024 21:05:57 -0800 Subject: [PATCH 147/652] [Instrumentation] Remove -pgo-instr-old-cfg-hashing (#77357) It's been more than 3 years since -pgo-instr-old-cfg-hashing was introduced by: commit 120e66b3418b37b95fc1dbbb23e296a602a24fa8 Author: Hiroshi Yamauchi Date: Tue Jul 28 10:09:49 2020 -0700 I don't think anyone really cares about the ability to use the old CFG hashing at this point. --- .../Instrumentation/PGOInstrumentation.cpp | 51 +++++++------------ .../Inputs/multiple_hash_profile.proftext | 29 ----------- .../PGOProfile/multiple_hash_profile.ll | 4 -- 3 files changed, 18 insertions(+), 66 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp index 3a57709c4e8b..6b95c7028d93 100644 --- a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp +++ b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp @@ -330,10 +330,6 @@ extern cl::opt ViewBlockFreqFuncName; extern cl::opt ProfileCorrelate; } // namespace llvm -static cl::opt - PGOOldCFGHashing("pgo-instr-old-cfg-hashing", cl::init(false), cl::Hidden, - cl::desc("Use the old CFG function hashing")); - // Return a string describing the branch condition that can be // used in static branch probability heuristics: static std::string getBranchCondString(Instruction *TI) { @@ -635,34 +631,25 @@ void FuncPGOInstrumentation::computeCFGHash() { JC.update(Indexes); JamCRC JCH; - if (PGOOldCFGHashing) { - // Hash format for context sensitive profile. Reserve 4 bits for other - // information. - FunctionHash = (uint64_t)SIVisitor.getNumOfSelectInsts() << 56 | - (uint64_t)ValueSites[IPVK_IndirectCallTarget].size() << 48 | - //(uint64_t)ValueSites[IPVK_MemOPSize].size() << 40 | - (uint64_t)MST.numEdges() << 32 | JC.getCRC(); + // The higher 32 bits. + auto updateJCH = [&JCH](uint64_t Num) { + uint8_t Data[8]; + support::endian::write64le(Data, Num); + JCH.update(Data); + }; + updateJCH((uint64_t)SIVisitor.getNumOfSelectInsts()); + updateJCH((uint64_t)ValueSites[IPVK_IndirectCallTarget].size()); + updateJCH((uint64_t)ValueSites[IPVK_MemOPSize].size()); + if (BCI) { + updateJCH(BCI->getInstrumentedBlocksHash()); } else { - // The higher 32 bits. - auto updateJCH = [&JCH](uint64_t Num) { - uint8_t Data[8]; - support::endian::write64le(Data, Num); - JCH.update(Data); - }; - updateJCH((uint64_t)SIVisitor.getNumOfSelectInsts()); - updateJCH((uint64_t)ValueSites[IPVK_IndirectCallTarget].size()); - updateJCH((uint64_t)ValueSites[IPVK_MemOPSize].size()); - if (BCI) { - updateJCH(BCI->getInstrumentedBlocksHash()); - } else { - updateJCH((uint64_t)MST.numEdges()); - } - - // Hash format for context sensitive profile. Reserve 4 bits for other - // information. - FunctionHash = (((uint64_t)JCH.getCRC()) << 28) + JC.getCRC(); + updateJCH((uint64_t)MST.numEdges()); } + // Hash format for context sensitive profile. Reserve 4 bits for other + // information. + FunctionHash = (((uint64_t)JCH.getCRC()) << 28) + JC.getCRC(); + // Reserve bit 60-63 for other information purpose. FunctionHash &= 0x0FFFFFFFFFFFFFFF; if (IsCS) @@ -672,10 +659,8 @@ void FuncPGOInstrumentation::computeCFGHash() { << ", Selects = " << SIVisitor.getNumOfSelectInsts() << ", Edges = " << MST.numEdges() << ", ICSites = " << ValueSites[IPVK_IndirectCallTarget].size()); - if (!PGOOldCFGHashing) { - LLVM_DEBUG(dbgs() << ", Memops = " << ValueSites[IPVK_MemOPSize].size() - << ", High32 CRC = " << JCH.getCRC()); - } + LLVM_DEBUG(dbgs() << ", Memops = " << ValueSites[IPVK_MemOPSize].size() + << ", High32 CRC = " << JCH.getCRC()); LLVM_DEBUG(dbgs() << ", Hash = " << FunctionHash << "\n";); if (PGOTraceFuncHash != "-" && F.getName().contains(PGOTraceFuncHash)) diff --git a/llvm/test/Transforms/PGOProfile/Inputs/multiple_hash_profile.proftext b/llvm/test/Transforms/PGOProfile/Inputs/multiple_hash_profile.proftext index 77f8d5a5ade3..1db6cfb445c2 100644 --- a/llvm/test/Transforms/PGOProfile/Inputs/multiple_hash_profile.proftext +++ b/llvm/test/Transforms/PGOProfile/Inputs/multiple_hash_profile.proftext @@ -9,16 +9,6 @@ _Z3fooi 18 12 -# For -pgo-instr-old-cfg-hashing=true -_Z3fooi -# Func Hash: -72057606922829823 -# Num Counters: -2 -# Counter Values: -18 -6 - _Z3fooi # Func Hash: 12884901887 @@ -36,16 +26,6 @@ _Z3bari 0 0 -# For -pgo-instr-old-cfg-hashing=true -_Z3bari -# Func Hash: -72057606922829823 -# Num Counters: -2 -# Counter Values: -0 -0 - _Z4m2f1v # Func Hash: 742261418966908927 @@ -53,12 +33,3 @@ _Z4m2f1v 1 # Counter Values: 1 - -# For -pgo-instr-old-cfg-hashing=true -_Z4m2f1v -# Func Hash: -12884901887 -# Num Counters: -1 -# Counter Values: -1 diff --git a/llvm/test/Transforms/PGOProfile/multiple_hash_profile.ll b/llvm/test/Transforms/PGOProfile/multiple_hash_profile.ll index 6a7838080b1d..768412603a84 100644 --- a/llvm/test/Transforms/PGOProfile/multiple_hash_profile.ll +++ b/llvm/test/Transforms/PGOProfile/multiple_hash_profile.ll @@ -1,6 +1,5 @@ ; RUN: llvm-profdata merge %S/Inputs/multiple_hash_profile.proftext -o %t.profdata ; RUN: opt < %s -passes=pgo-instr-use -pgo-test-profile-file=%t.profdata -S | FileCheck %s -; RUN: opt < %s -passes=pgo-instr-use -pgo-test-profile-file=%t.profdata -pgo-instr-old-cfg-hashing=true -S | FileCheck -check-prefix=CHECKOLDHASH %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -29,9 +28,6 @@ entry: ; CHECK: %mul.i = select i1 %cmp.i, i32 1, i32 %i ; CHECK-SAME: !prof ![[BW:[0-9]+]] ; CHECK: ![[BW]] = !{!"branch_weights", i32 12, i32 6} -; CHECKOLDHASH: %mul.i = select i1 %cmp.i, i32 1, i32 %i -; CHECKOLDHASH-SAME: !prof ![[BW:[0-9]+]] -; CHECKOLDHASH: ![[BW]] = !{!"branch_weights", i32 6, i32 12} %retval.0.i = mul nsw i32 %mul.i, %i ret i32 %retval.0.i } -- GitLab From 0930f62cf600d9e2e9a45fef1b3a422d50be89d5 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 8 Jan 2024 21:13:27 -0800 Subject: [PATCH 148/652] [ELF] -r: fix crash when SHF_LINK_ORDER linked-to section has a larger index Fixes: b8dface221f4490933b0d39deb769e97ca134e5f ThinLTO asan build may place `asan_globals` before the associated `.bss.xxx` section. `rel->getOutputSection()` is nullptr because `rel->parent` hasn't been set, leading to a crash. Simplify return `s->name` in this case. --- lld/ELF/LinkerScript.cpp | 4 +++ lld/test/ELF/linkorder-group.test | 58 +++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 lld/test/ELF/linkorder-group.test diff --git a/lld/ELF/LinkerScript.cpp b/lld/ELF/LinkerScript.cpp index 28ae4b854306..03aec187668a 100644 --- a/lld/ELF/LinkerScript.cpp +++ b/lld/ELF/LinkerScript.cpp @@ -57,6 +57,10 @@ static StringRef getOutputSectionName(const InputSectionBase *s) { if (auto *isec = dyn_cast(s)) { if (InputSectionBase *rel = isec->getRelocatedSection()) { OutputSection *out = rel->getOutputSection(); + if (!out) { + assert(config->relocatable && (rel->flags & SHF_LINK_ORDER)); + return s->name; + } if (s->type == SHT_RELA) return saver().save(".rela" + out->name); return saver().save(".rel" + out->name); diff --git a/lld/test/ELF/linkorder-group.test b/lld/test/ELF/linkorder-group.test new file mode 100644 index 000000000000..988f793cf632 --- /dev/null +++ b/lld/test/ELF/linkorder-group.test @@ -0,0 +1,58 @@ +# REQUIRES: x86 +## Test SHF_LINK_ORDER when the linked-to section has a larger index. +# RUN: yaml2obj %s -o %t.o +# RUN: ld.lld -r %t.o -o %t.ro +# RUN: llvm-readelf -x asan_globals %t.ro | FileCheck %s + +# CHECK: Hex dump of section 'asan_globals': +# CHECK-NEXT: 0x00000000 00 . + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_X86_64 + SectionHeaderStringTable: .strtab +Sections: + - Name: .text + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + - Name: .bss + Type: SHT_NOBITS + Flags: [ SHF_WRITE, SHF_ALLOC, SHF_GROUP ] + Size: 0x1 + - Name: asan_globals + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_LINK_ORDER, SHF_GROUP ] + Link: .bss + Content: '00' + - Name: .group + Type: SHT_GROUP + Link: .symtab + Info: foo + Members: + - SectionOrType: GRP_COMDAT + - SectionOrType: .bss + - SectionOrType: asan_globals + - SectionOrType: .relaasan_globals + - Name: .relaasan_globals + Type: SHT_RELA + Flags: [ SHF_GROUP ] + Link: .symtab + Info: asan_globals + Relocations: + - Type: R_X86_64_NONE + - Type: SectionHeaderTable + Sections: + - Name: .strtab + - Name: .text + - Name: .group + - Name: asan_globals + - Name: .relaasan_globals + - Name: .bss + - Name: .symtab +Symbols: + - Name: foo + Section: .bss + Binding: STB_WEAK -- GitLab From 782c5250077cf472941f0ab7555f87ff22d6e724 Mon Sep 17 00:00:00 2001 From: SunilKuravinakop <98882378+SunilKuravinakop@users.noreply.github.com> Date: Tue, 9 Jan 2024 11:14:56 +0530 Subject: [PATCH 149/652] [OpenMP] Patch for Support to loop bind clause : Checking Parent Region (#76938) Changes uploaded to the phabricator on Dec 16th are lost because the phabricator is down. Hence re-uploading it to the github.com. Changes to be committed: modified: clang/include/clang/Sema/Sema.h modified: clang/lib/Sema/SemaOpenMP.cpp modified: clang/test/OpenMP/generic_loop_ast_print.cpp modified: clang/test/OpenMP/loop_bind_messages.cpp modified: clang/test/PCH/pragma-loop.cpp --------- Co-authored-by: Sunil Kuravinakop --- clang/include/clang/Sema/Sema.h | 7 +- clang/lib/Sema/SemaOpenMP.cpp | 56 +++++-- clang/test/OpenMP/loop_bind_messages.cpp | 191 ++++++++++++++++++++--- clang/test/PCH/pragma-loop.cpp | 8 +- 4 files changed, 225 insertions(+), 37 deletions(-) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 8f44adef3815..4c464a1ae4c6 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -11346,9 +11346,12 @@ private: /// rigorous semantic checking in the new mapped directives. bool mapLoopConstruct(llvm::SmallVector &ClausesWithoutBind, ArrayRef Clauses, - OpenMPBindClauseKind BindKind, + OpenMPBindClauseKind &BindKind, OpenMPDirectiveKind &Kind, - OpenMPDirectiveKind &PrevMappedDirective); + OpenMPDirectiveKind &PrevMappedDirective, + SourceLocation StartLoc, SourceLocation EndLoc, + const DeclarationNameInfo &DirName, + OpenMPDirectiveKind CancelRegion); public: /// The declarator \p D defines a function in the scope \p S which is nested diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index f34d2959dc61..365032c96421 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -5072,6 +5072,18 @@ static bool checkNestingOfRegions(Sema &SemaRef, const DSAStackTy *Stack, CurrentRegion != OMPD_cancellation_point && CurrentRegion != OMPD_cancel && CurrentRegion != OMPD_scan) return false; + // Checks needed for mapping "loop" construct. Please check mapLoopConstruct + // for a detailed explanation + if (SemaRef.LangOpts.OpenMP >= 50 && CurrentRegion == OMPD_loop && + (BindKind == OMPC_BIND_parallel || BindKind == OMPC_BIND_teams) && + (isOpenMPWorksharingDirective(ParentRegion) || + ParentRegion == OMPD_loop)) { + int ErrorMsgNumber = (BindKind == OMPC_BIND_parallel) ? 1 : 4; + SemaRef.Diag(StartLoc, diag::err_omp_prohibited_region) + << true << getOpenMPDirectiveName(ParentRegion) << ErrorMsgNumber + << getOpenMPDirectiveName(CurrentRegion); + return true; + } if (CurrentRegion == OMPD_cancellation_point || CurrentRegion == OMPD_cancel) { // OpenMP [2.16, Nesting of Regions] @@ -6124,21 +6136,25 @@ processImplicitMapsWithDefaultMappers(Sema &S, DSAStackTy *Stack, bool Sema::mapLoopConstruct(llvm::SmallVector &ClausesWithoutBind, ArrayRef Clauses, - OpenMPBindClauseKind BindKind, + OpenMPBindClauseKind &BindKind, OpenMPDirectiveKind &Kind, - OpenMPDirectiveKind &PrevMappedDirective) { + OpenMPDirectiveKind &PrevMappedDirective, + SourceLocation StartLoc, SourceLocation EndLoc, + const DeclarationNameInfo &DirName, + OpenMPDirectiveKind CancelRegion) { bool UseClausesWithoutBind = false; // Restricting to "#pragma omp loop bind" if (getLangOpts().OpenMP >= 50 && Kind == OMPD_loop) { + + const OpenMPDirectiveKind ParentDirective = DSAStack->getParentDirective(); + if (BindKind == OMPC_BIND_unknown) { // Setting the enclosing teams or parallel construct for the loop // directive without bind clause. BindKind = OMPC_BIND_thread; // Default bind(thread) if binding is unknown - const OpenMPDirectiveKind ParentDirective = - DSAStack->getParentDirective(); if (ParentDirective == OMPD_unknown) { Diag(DSAStack->getDefaultDSALocation(), diag::err_omp_bind_required_on_loop); @@ -6150,9 +6166,10 @@ bool Sema::mapLoopConstruct(llvm::SmallVector &ClausesWithoutBind, BindKind = OMPC_BIND_teams; } } else { - // bind clause is present, so we should set flag indicating to only - // use the clauses that aren't the bind clause for the new directive that - // loop is lowered to. + // bind clause is present in loop directive. When the loop directive is + // changed to a new directive the bind clause is not used. So, we should + // set flag indicating to only use the clauses that aren't the + // bind clause. UseClausesWithoutBind = true; } @@ -6213,26 +6230,35 @@ StmtResult Sema::ActOnOpenMPExecutableDirective( OpenMPDirectiveKind PrevMappedDirective) { StmtResult Res = StmtError(); OpenMPBindClauseKind BindKind = OMPC_BIND_unknown; + llvm::SmallVector ClausesWithoutBind; + bool UseClausesWithoutBind = false; + if (const OMPBindClause *BC = OMPExecutableDirective::getSingleClause(Clauses)) BindKind = BC->getBindKind(); + + // Variable used to note down the DirectiveKind because mapLoopConstruct may + // change "Kind" variable, due to mapping of "omp loop" to other directives. + OpenMPDirectiveKind DK = Kind; + if (Kind == OMPD_loop || PrevMappedDirective == OMPD_loop) { + UseClausesWithoutBind = mapLoopConstruct( + ClausesWithoutBind, Clauses, BindKind, Kind, PrevMappedDirective, + StartLoc, EndLoc, DirName, CancelRegion); + DK = OMPD_loop; + } + // First check CancelRegion which is then used in checkNestingOfRegions. if (checkCancelRegion(*this, Kind, CancelRegion, StartLoc) || - checkNestingOfRegions(*this, DSAStack, Kind, DirName, CancelRegion, - BindKind, StartLoc)) + checkNestingOfRegions(*this, DSAStack, DK, DirName, CancelRegion, + BindKind, StartLoc)) { return StmtError(); + } // Report affected OpenMP target offloading behavior when in HIP lang-mode. if (getLangOpts().HIP && (isOpenMPTargetExecutionDirective(Kind) || isOpenMPTargetDataManagementDirective(Kind))) Diag(StartLoc, diag::warn_hip_omp_target_directives); - llvm::SmallVector ClausesWithoutBind; - bool UseClausesWithoutBind = false; - - UseClausesWithoutBind = mapLoopConstruct(ClausesWithoutBind, Clauses, - BindKind, Kind, PrevMappedDirective); - llvm::SmallVector ClausesWithImplicit; VarsWithInheritedDSAType VarsWithInheritedDSA; bool ErrorFound = false; diff --git a/clang/test/OpenMP/loop_bind_messages.cpp b/clang/test/OpenMP/loop_bind_messages.cpp index f7fdf2897143..becd1f40c0c0 100644 --- a/clang/test/OpenMP/loop_bind_messages.cpp +++ b/clang/test/OpenMP/loop_bind_messages.cpp @@ -4,6 +4,7 @@ #define NNN 50 int aaa[NNN]; +int aaa2[NNN][NNN]; void parallel_loop() { #pragma omp parallel @@ -13,10 +14,82 @@ void parallel_loop() { aaa[j] = j*NNN; } } + + #pragma omp parallel for + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(parallel) // expected-error{{region cannot be closely nested inside 'parallel for' region; perhaps you forget to enclose 'omp loop' directive into a parallel region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } + } + + #pragma omp parallel + #pragma omp for nowait + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(parallel) // expected-error{{region cannot be closely nested inside 'for' region; perhaps you forget to enclose 'omp loop' directive into a parallel region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } + } + + #pragma omp parallel for + for (int i = 0 ; i < NNN ; i++) { + #pragma omp nothing + #pragma omp loop + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } + } + + #pragma omp target teams distribute parallel for + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(parallel) // expected-error{{region cannot be closely nested inside 'target teams distribute parallel for' region; perhaps you forget to enclose 'omp loop' directive into a parallel region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } + } + + #pragma omp target parallel + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(parallel) + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } + } + + #pragma omp parallel for + for (int i = 0; i < 100; ++i) { + #pragma omp loop bind(parallel) // expected-error{{region cannot be closely nested inside 'parallel for' region; perhaps you forget to enclose 'omp loop' directive into a parallel region?}} + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(parallel) // expected-error{{region cannot be closely nested inside 'loop' region; perhaps you forget to enclose 'omp loop' directive into a parallel region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa[j] = j*NNN; + } + } + } + + #pragma omp parallel + { + #pragma omp sections + { + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(parallel) // expected-error{{region cannot be closely nested inside 'sections' region; perhaps you forget to enclose 'omp loop' directive into a parallel region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } + } + + #pragma omp section + { + aaa[NNN-1] = NNN; + } + } + } } void teams_loop() { - int var1, var2; + int var1; + int total = 0; #pragma omp teams { @@ -32,24 +105,22 @@ void teams_loop() { } } } -} -void orphan_loop_with_bind() { - #pragma omp loop bind(parallel) - for (int j = 0 ; j < NNN ; j++) { - aaa[j] = j*NNN; + #pragma omp target teams + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(teams) + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } } -} -void orphan_loop_no_bind() { - #pragma omp loop // expected-error{{expected 'bind' clause for 'loop' construct without an enclosing OpenMP construct}} - for (int j = 0 ; j < NNN ; j++) { - aaa[j] = j*NNN; + #pragma omp target teams distribute parallel for + for (int i = 0 ; i < NNN ; i++) { + #pragma omp loop bind(teams) // expected-error{{region cannot be closely nested inside 'target teams distribute parallel for' region; perhaps you forget to enclose 'omp loop' directive into a teams region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa2[i][j] = i+j; + } } -} - -void teams_loop_reduction() { - int total = 0; #pragma omp teams { @@ -63,14 +134,98 @@ void teams_loop_reduction() { total+=aaa[j]; } } + + #pragma omp teams num_teams(8) thread_limit(256) + #pragma omp distribute parallel for dist_schedule(static, 1024) \ + schedule(static, 64) + for (int i = 0; i < NNN; i++) { + #pragma omp loop bind(teams) // expected-error{{'distribute parallel for' region; perhaps you forget to enclose 'omp loop' directive into a teams region?}} + for (int j = 0; j < NNN; j++) { + aaa2[i][j] = i+j; + } + } + + #pragma omp teams + for (int i = 0; i < NNN; i++) { + #pragma omp loop bind(thread) + for (int j = 0 ; j < NNN ; j++) { + aaa[i] = i+i*NNN; + } + } + + #pragma omp teams loop + for (int i = 0; i < NNN; i++) { + #pragma omp loop + for (int j = 0 ; j < NNN ; j++) { + aaa[i] = i+i*NNN; + } + } + + #pragma omp teams loop + for (int i = 0; i < NNN; i++) { + #pragma omp loop bind(teams) // expected-error{{region cannot be closely nested inside 'teams loop' region; perhaps you forget to enclose 'omp loop' directive into a teams region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa[i] = i+i*NNN; + } + } +} + +void thread_loop() { + #pragma omp parallel + for (int i = 0; i < NNN; i++) { + #pragma omp loop bind(thread) + for (int j = 0 ; j < NNN ; j++) { + aaa[i] = i+i*NNN; + } + } + + #pragma omp teams + for (int i = 0; i < NNN; i++) { + #pragma omp loop bind(thread) + for (int j = 0 ; j < NNN ; j++) { + aaa[i] = i+i*NNN; + } + } +} + +void parallel_for_with_loop_teams_bind(){ + #pragma omp parallel for + for (int i = 0; i < NNN; i++) { + #pragma omp loop bind(teams) // expected-error{{region cannot be closely nested inside 'parallel for' region; perhaps you forget to enclose 'omp loop' directive into a teams region?}} + for (int j = 0 ; j < NNN ; j++) { + aaa[i] = i+i*NNN; + } + } +} + +void orphan_loops() { + #pragma omp loop // expected-error{{expected 'bind' clause for 'loop' construct without an enclosing OpenMP construct}} + for (int j = 0 ; j < NNN ; j++) { + aaa[j] = j*NNN; + } + + #pragma omp loop bind(parallel) + for (int j = 0 ; j < NNN ; j++) { + aaa[j] = j*NNN; + } + + #pragma omp loop bind(teams) + for (int i = 0; i < NNN; i++) { + aaa[i] = i+i*NNN; + } + + #pragma omp loop bind(thread) + for (int i = 0; i < NNN; i++) { + aaa[i] = i+i*NNN; + } } int main(int argc, char *argv[]) { parallel_loop(); teams_loop(); - orphan_loop_with_bind(); - orphan_loop_no_bind(); - teams_loop_reduction(); + thread_loop(); + parallel_for_with_loop_teams_bind(); + orphan_loops(); } #endif diff --git a/clang/test/PCH/pragma-loop.cpp b/clang/test/PCH/pragma-loop.cpp index f5de630ffc91..a3c6871041c0 100644 --- a/clang/test/PCH/pragma-loop.cpp +++ b/clang/test/PCH/pragma-loop.cpp @@ -116,9 +116,13 @@ public: inline void run10(int *List, int Length) { int i = 0; -#pragma omp loop bind(teams) + int j = 0; + #pragma omp teams for (int i = 0; i < Length; i++) { - List[i] = i; + #pragma omp loop bind(teams) + for (int j = 0; j < Length; j++) { + List[i] = i+j; + } } } -- GitLab From abaa79b25dde740d5b54adab463432bee2840c85 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Mon, 8 Jan 2024 21:49:32 -0800 Subject: [PATCH 150/652] [mlir] Use StringRef::ltrim (NFC) --- mlir/lib/Query/Matcher/Parser.cpp | 5 +---- mlir/lib/Query/QueryParser.cpp | 9 +++------ mlir/lib/TableGen/Class.cpp | 2 +- mlir/lib/Tools/lsp-server-support/SourceMgrUtils.cpp | 2 +- 4 files changed, 6 insertions(+), 12 deletions(-) diff --git a/mlir/lib/Query/Matcher/Parser.cpp b/mlir/lib/Query/Matcher/Parser.cpp index 6585b5d740f6..30eb4801fc03 100644 --- a/mlir/lib/Query/Matcher/Parser.cpp +++ b/mlir/lib/Query/Matcher/Parser.cpp @@ -201,10 +201,7 @@ private: } // Consume all leading whitespace from code, except newlines - void consumeWhitespace() { - code = code.drop_while( - [](char c) { return llvm::StringRef(" \t\v\f\r").contains(c); }); - } + void consumeWhitespace() { code = code.ltrim(" \t\v\f\r"); } // Returns the current location in the source code SourceLocation currentLocation() { diff --git a/mlir/lib/Query/QueryParser.cpp b/mlir/lib/Query/QueryParser.cpp index f43a28569f00..595055a42965 100644 --- a/mlir/lib/Query/QueryParser.cpp +++ b/mlir/lib/Query/QueryParser.cpp @@ -16,10 +16,8 @@ namespace mlir::query { // is found before end, return StringRef(). begin is adjusted to exclude the // lexed region. llvm::StringRef QueryParser::lexWord() { - line = line.drop_while([](char c) { - // Don't trim newlines. - return llvm::StringRef(" \t\v\f\r").contains(c); - }); + // Don't trim newlines. + line = line.ltrim(" \t\v\f\r"); if (line.empty()) // Even though the line is empty, it contains a pointer and @@ -91,8 +89,7 @@ struct QueryParser::LexOrCompleteWord { QueryRef QueryParser::endQuery(QueryRef queryRef) { llvm::StringRef extra = line; - llvm::StringRef extraTrimmed = extra.drop_while( - [](char c) { return llvm::StringRef(" \t\v\f\r").contains(c); }); + llvm::StringRef extraTrimmed = extra.ltrim(" \t\v\f\r"); if ((!extraTrimmed.empty() && extraTrimmed[0] == '\n') || (extraTrimmed.size() >= 2 && extraTrimmed[0] == '\r' && diff --git a/mlir/lib/TableGen/Class.cpp b/mlir/lib/TableGen/Class.cpp index f71d7e07ed49..9092adcc627c 100644 --- a/mlir/lib/TableGen/Class.cpp +++ b/mlir/lib/TableGen/Class.cpp @@ -113,7 +113,7 @@ MethodBody::MethodBody(bool declOnly) : declOnly(declOnly), stringOs(body), os(stringOs) {} void MethodBody::writeTo(raw_indented_ostream &os) const { - auto bodyRef = StringRef(body).drop_while([](char c) { return c == '\n'; }); + auto bodyRef = StringRef(body).ltrim('\n'); os << bodyRef; if (bodyRef.empty()) return; diff --git a/mlir/lib/Tools/lsp-server-support/SourceMgrUtils.cpp b/mlir/lib/Tools/lsp-server-support/SourceMgrUtils.cpp index f8d348aba5a3..f1a362385f28 100644 --- a/mlir/lib/Tools/lsp-server-support/SourceMgrUtils.cpp +++ b/mlir/lib/Tools/lsp-server-support/SourceMgrUtils.cpp @@ -103,7 +103,7 @@ lsp::extractSourceDocComment(llvm::SourceMgr &sourceMgr, SMLoc loc) { break; // Extract the document string from the comment. - commentLines.push_back(line->drop_while([](char c) { return c == '/'; })); + commentLines.push_back(line->ltrim('/')); } if (commentLines.empty()) -- GitLab From ee78e038667d89f5dcd5ed25a36659b3653095d0 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 9 Jan 2024 13:10:36 +0700 Subject: [PATCH 151/652] AMDGPU: Avoid instantiating PatFrag with null_frag (#77271) This makes it possible to pass null_frag to the MAIInst multiclass. null_frag does not work as you may hope if used as the input to a PatFrag, which is what happens when it's passed through to *MAIFrag. Avoid this by checking for null_frag. It might be possible to hack up tablegen to allow consuming PatFrag inputs. --- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index 985b77be1d88..e9d6f67aee16 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -623,12 +623,12 @@ multiclass MAIInst("VOPProfileMAI_" # P), - !if(NoDstOverlap, null_frag, AgprMAIFrag)>, + !if(!or(NoDstOverlap, !eq(node, null_frag)), null_frag, AgprMAIFrag)>, MFMATable<0, NAME # "_e64">; let SubtargetPredicate = isGFX90APlus, Mnemonic = OpName in def _vgprcd_e64 : MAIInst("VOPProfileMAI_" # P # "_VCD"), - !if(NoDstOverlap, null_frag, VgprMAIFrag)>, + !if(!or(NoDstOverlap, !eq(node, null_frag)), null_frag, VgprMAIFrag)>, MFMATable<0, NAME # "_vgprcd_e64">; } @@ -636,12 +636,13 @@ multiclass MAIInst("VOPProfileMAI_" # P), AgprMAIFrag>, + def "_mac_e64" : MAIInst("VOPProfileMAI_" # P), + !if(!eq(node, null_frag), null_frag, AgprMAIFrag)>, MFMATable<1, NAME # "_e64">; let SubtargetPredicate = isGFX90APlus in def _mac_vgprcd_e64 : MAIInst("VOPProfileMAI_" # P # "_VCD"), - VgprMAIFrag>, + !if(!eq(node, null_frag), null_frag, VgprMAIFrag)>, MFMATable<1, NAME # "_vgprcd_e64">; } } -- GitLab From 0c24c175f262b1043752c67798cd83f79188e9d2 Mon Sep 17 00:00:00 2001 From: Chia Date: Tue, 9 Jan 2024 15:17:38 +0900 Subject: [PATCH 152/652] [RISCV][ISel] Use vaaddu with rounding mode rdn for ISD::AVGFLOORU. (#76550) This patch aims to use `vaaddu` with rounding mode rdn (i.e `vxrm[1:0] = 0b10`) for `ISD::AVGFLOORU`. ### Source code ``` define <8 x i8> @vaaddu_auto(ptr %x, ptr %y, ptr %z) { %xv = load <8 x i8>, ptr %x, align 2 %yv = load <8 x i8>, ptr %y, align 2 %xzv = zext <8 x i8> %xv to <8 x i16> %yzv = zext <8 x i8> %yv to <8 x i16> %add = add nuw nsw <8 x i16> %xzv, %yzv %div = lshr <8 x i16> %add, %ret = trunc <8 x i16> %div to <8 x i8> ret <8 x i8> %ret } ``` ### Before this patch ``` vaaddu_auto: vsetivli zero, 8, e8, mf2, ta, ma vle8.v v8, (a0) vle8.v v9, (a1) vwaddu.vv v10, v8, v9 vnsrl.wi v8, v10, 1 ret ``` ### After this patch ``` vaaddu_auto: vsetivli zero, 8, e8, mf2, ta, ma vle8.v v8, (a0) vle8.v v9, (a1) csrwi vxrm, 2 vaaddu.vv v8, v8, v9 ret ``` ### Note on signed averaging addition Based on the rvv spec, there is also a variant for signed averaging addition called `vaadd`. But AFAIU, no matter in which rounding mode, we cannot achieve the semantic of signed averaging addition through `vaadd`. Thus this patch only introduces `vaaddu`. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 18 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 + .../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 16 ++ .../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 19 ++ .../CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll | 220 ++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll | 212 +++++++++++++++++ 6 files changed, 482 insertions(+), 7 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a5d49dcece3c..a5b33e8e293a 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -814,8 +814,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, Custom); setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); - setOperationAction( - {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Legal); + setOperationAction({ISD::AVGFLOORU, ISD::SADDSAT, ISD::UADDSAT, + ISD::SSUBSAT, ISD::USUBSAT}, + VT, Legal); // Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR_VL" // nodes which truncate by one power of two at a time. @@ -1184,9 +1185,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, if (VT.getVectorElementType() != MVT::i64 || Subtarget.hasStdExtV()) setOperationAction({ISD::MULHS, ISD::MULHU}, VT, Custom); - setOperationAction( - {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, - Custom); + setOperationAction({ISD::AVGFLOORU, ISD::SADDSAT, ISD::UADDSAT, + ISD::SSUBSAT, ISD::USUBSAT}, + VT, Custom); setOperationAction(ISD::VSELECT, VT, Custom); setOperationAction(ISD::SELECT_CC, VT, Expand); @@ -5465,6 +5466,7 @@ static unsigned getRISCVVLOp(SDValue Op) { OP_CASE(UADDSAT) OP_CASE(SSUBSAT) OP_CASE(USUBSAT) + OP_CASE(AVGFLOORU) OP_CASE(FADD) OP_CASE(FSUB) OP_CASE(FMUL) @@ -5569,7 +5571,7 @@ static bool hasMergeOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 124 && + 125 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -5595,7 +5597,7 @@ static bool hasMaskOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 124 && + 125 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -6459,6 +6461,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, !Subtarget.hasVInstructionsF16())) return SplitVectorOp(Op, DAG); [[fallthrough]]; + case ISD::AVGFLOORU: case ISD::SADDSAT: case ISD::UADDSAT: case ISD::SSUBSAT: @@ -18595,6 +18598,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(UDIV_VL) NODE_NAME_CASE(UREM_VL) NODE_NAME_CASE(XOR_VL) + NODE_NAME_CASE(AVGFLOORU_VL) NODE_NAME_CASE(SADDSAT_VL) NODE_NAME_CASE(UADDSAT_VL) NODE_NAME_CASE(SSUBSAT_VL) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 18f580575581..5d51fe168b04 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -253,6 +253,9 @@ enum NodeType : unsigned { SSUBSAT_VL, USUBSAT_VL, + // Averaging adds of unsigned integers. + AVGFLOORU_VL, + MULHS_VL, MULHU_VL, FADD_VL, @@ -902,6 +905,7 @@ private: SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, SelectionDAG &DAG) const; SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerUnsignedAvgFloor(SDValue Op, SelectionDAG &DAG) const; SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const; SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const; SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index b7c845703794..4f87c36506e5 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -1131,6 +1131,22 @@ defm : VPatBinarySDNode_VV_VX_VI; defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; +// 12.2. Vector Single-Width Averaging Add and Subtract +foreach vti = AllIntegerVectors in { + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(avgflooru (vti.Vector vti.RegClass:$rs1), + (vti.Vector vti.RegClass:$rs2)), + (!cast("PseudoVAADDU_VV_"#vti.LMul.MX) + (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs2, + 0b10, vti.AVL, vti.Log2SEW, TA_MA)>; + def : Pat<(avgflooru (vti.Vector vti.RegClass:$rs1), + (vti.Vector (SplatPat (XLenVT GPR:$rs2)))), + (!cast("PseudoVAADDU_VX_"#vti.LMul.MX) + (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, + 0b10, vti.AVL, vti.Log2SEW, TA_MA)>; + } +} + // 15. Vector Mask Instructions // 15.1. Vector Mask-Register Logical Instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index ca9e37b9144b..d60ff4b5fab0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -111,6 +111,7 @@ def riscv_ctlz_vl : SDNode<"RISCVISD::CTLZ_VL", SDT_RISCVIntUnOp_VL> def riscv_cttz_vl : SDNode<"RISCVISD::CTTZ_VL", SDT_RISCVIntUnOp_VL>; def riscv_ctpop_vl : SDNode<"RISCVISD::CTPOP_VL", SDT_RISCVIntUnOp_VL>; +def riscv_avgflooru_vl : SDNode<"RISCVISD::AVGFLOORU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; @@ -2306,6 +2307,24 @@ defm : VPatBinaryVL_VV_VX_VI; defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; +// 12.2. Vector Single-Width Averaging Add and Subtract +foreach vti = AllIntegerVectors in { + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(riscv_avgflooru_vl (vti.Vector vti.RegClass:$rs1), + (vti.Vector vti.RegClass:$rs2), + vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), + (!cast("PseudoVAADDU_VV_"#vti.LMul.MX#"_MASK") + vti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs2, + (vti.Mask V0), 0b10, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(riscv_avgflooru_vl (vti.Vector vti.RegClass:$rs1), + (vti.Vector (SplatPat (XLenVT GPR:$rs2))), + vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), + (!cast("PseudoVAADDU_VX_"#vti.LMul.MX#"_MASK") + vti.RegClass:$merge, vti.RegClass:$rs1, GPR:$rs2, + (vti.Mask V0), 0b10, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; + } +} + // 12.5. Vector Narrowing Fixed-Point Clip Instructions class VPatTruncSatClipMaxMinBase @vaaddu_vv_v8i8(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i16> + %yzv = zext <8 x i8> %y to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %div = lshr <8 x i16> %add, + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vx_v8i8(<8 x i8> %x, i8 %y) { +; CHECK-LABEL: vaaddu_vx_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i16> + %yhead = insertelement <8 x i8> poison, i8 %y, i32 0 + %ysplat = shufflevector <8 x i8> %yhead, <8 x i8> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i8> %ysplat to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %one = insertelement <8 x i16> poison, i16 1, i32 0 + %splat = shufflevector <8 x i16> %one, <8 x i16> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i16> %add, %splat + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + + +define <8 x i8> @vaaddu_vv_v8i8_sexti16(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_sexti16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9 +; CHECK-NEXT: vnsrl.wi v8, v10, 1 +; CHECK-NEXT: ret + %xzv = sext <8 x i8> %x to <8 x i16> + %yzv = sext <8 x i8> %y to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %div = lshr <8 x i16> %add, + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vv_v8i8_zexti32(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_zexti32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i32> + %yzv = zext <8 x i8> %y to <8 x i32> + %add = add nuw nsw <8 x i32> %xzv, %yzv + %div = lshr <8 x i32> %add, + %ret = trunc <8 x i32> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vv_v8i8_lshr2(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_lshr2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9 +; CHECK-NEXT: vnsrl.wi v8, v10, 2 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i16> + %yzv = zext <8 x i8> %y to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %div = lshr <8 x i16> %add, + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i16> @vaaddu_vv_v8i16(<8 x i16> %x, <8 x i16> %y) { +; CHECK-LABEL: vaaddu_vv_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext <8 x i16> %x to <8 x i32> + %yzv = zext <8 x i16> %y to <8 x i32> + %add = add nuw nsw <8 x i32> %xzv, %yzv + %div = lshr <8 x i32> %add, + %ret = trunc <8 x i32> %div to <8 x i16> + ret <8 x i16> %ret +} + +define <8 x i16> @vaaddu_vx_v8i16(<8 x i16> %x, i16 %y) { +; CHECK-LABEL: vaaddu_vx_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext <8 x i16> %x to <8 x i32> + %yhead = insertelement <8 x i16> poison, i16 %y, i16 0 + %ysplat = shufflevector <8 x i16> %yhead, <8 x i16> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i16> %ysplat to <8 x i32> + %add = add nuw nsw <8 x i32> %xzv, %yzv + %one = insertelement <8 x i32> poison, i32 1, i32 0 + %splat = shufflevector <8 x i32> %one, <8 x i32> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i32> %add, %splat + %ret = trunc <8 x i32> %div to <8 x i16> + ret <8 x i16> %ret +} + +define <8 x i32> @vaaddu_vv_v8i32(<8 x i32> %x, <8 x i32> %y) { +; CHECK-LABEL: vaaddu_vv_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: ret + %xzv = zext <8 x i32> %x to <8 x i64> + %yzv = zext <8 x i32> %y to <8 x i64> + %add = add nuw nsw <8 x i64> %xzv, %yzv + %div = lshr <8 x i64> %add, + %ret = trunc <8 x i64> %div to <8 x i32> + ret <8 x i32> %ret +} + +define <8 x i32> @vaaddu_vx_v8i32(<8 x i32> %x, i32 %y) { +; CHECK-LABEL: vaaddu_vx_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext <8 x i32> %x to <8 x i64> + %yhead = insertelement <8 x i32> poison, i32 %y, i32 0 + %ysplat = shufflevector <8 x i32> %yhead, <8 x i32> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i32> %ysplat to <8 x i64> + %add = add nuw nsw <8 x i64> %xzv, %yzv + %one = insertelement <8 x i64> poison, i64 1, i64 0 + %splat = shufflevector <8 x i64> %one, <8 x i64> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i64> %add, %splat + %ret = trunc <8 x i64> %div to <8 x i32> + ret <8 x i32> %ret +} + +define <8 x i64> @vaaddu_vv_v8i64(<8 x i64> %x, <8 x i64> %y) { +; CHECK-LABEL: vaaddu_vv_v8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: ret + %xzv = zext <8 x i64> %x to <8 x i128> + %yzv = zext <8 x i64> %y to <8 x i128> + %add = add nuw nsw <8 x i128> %xzv, %yzv + %div = lshr <8 x i128> %add, + %ret = trunc <8 x i128> %div to <8 x i64> + ret <8 x i64> %ret +} + +define <8 x i1> @vaaddu_vv_v8i1(<8 x i1> %x, <8 x i1> %y) { +; CHECK-LABEL: vaaddu_vv_v8i1: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v10, v8 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: ret + %xzv = zext <8 x i1> %x to <8 x i8> + %yzv = zext <8 x i1> %y to <8 x i8> + %add = add nuw nsw <8 x i8> %xzv, %yzv + %div = lshr <8 x i8> %add, + %ret = trunc <8 x i8> %div to <8 x i1> + ret <8 x i1> %ret +} + +define <8 x i64> @vaaddu_vx_v8i64(<8 x i64> %x, i64 %y) { +; RV32-LABEL: vaaddu_vx_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: csrwi vxrm, 2 +; RV32-NEXT: vaaddu.vv v8, v8, v12 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vaaddu_vx_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; RV64-NEXT: csrwi vxrm, 2 +; RV64-NEXT: vaaddu.vx v8, v8, a0 +; RV64-NEXT: ret + %xzv = zext <8 x i64> %x to <8 x i128> + %yhead = insertelement <8 x i64> poison, i64 %y, i64 0 + %ysplat = shufflevector <8 x i64> %yhead, <8 x i64> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i64> %ysplat to <8 x i128> + %add = add nuw nsw <8 x i128> %xzv, %yzv + %one = insertelement <8 x i128> poison, i128 1, i128 0 + %splat = shufflevector <8 x i128> %one, <8 x i128> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i128> %add, %splat + %ret = trunc <8 x i128> %div to <8 x i64> + ret <8 x i64> %ret +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll new file mode 100644 index 000000000000..883d605e77e2 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll @@ -0,0 +1,212 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 + +define @vaaddu_vv_nxv8i8( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i8( %x, i8 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i8 %y, i32 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i8_sexti16( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_sexti16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9 +; CHECK-NEXT: vnsrl.wi v8, v10, 1 +; CHECK-NEXT: ret + %xzv = sext %x to + %yzv = sext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i8_zexti32( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_zexti32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i32 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i8_lshr2( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_lshr2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9 +; CHECK-NEXT: vnsrl.wi v8, v10, 2 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 2, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i16( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i32 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i16( %x, i16 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i16 %y, i16 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i32 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i32( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i64 1, i64 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i32( %x, i32 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i32 %y, i32 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i64 1, i64 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i64( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i128 1, i128 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i64( %x, i64 %y) { +; RV32-LABEL: vaaddu_vx_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: csrwi vxrm, 2 +; RV32-NEXT: vaaddu.vv v8, v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vaaddu_vx_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV64-NEXT: csrwi vxrm, 2 +; RV64-NEXT: vaaddu.vx v8, v8, a0 +; RV64-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i64 %y, i64 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i128 1, i128 0 + %splat = shufflevector %one, poison, zeroinitializer + %div = lshr %add, %splat + %ret = trunc %div to + ret %ret +} -- GitLab From 38ce770ef13131dce92a76ff80e6d5caba2d8422 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Tue, 9 Jan 2024 14:24:28 +0800 Subject: [PATCH 153/652] [X86][test] Add test to check ah is not allocatable for register class gr8_norex2 This test should be added after #73529 --- llvm/test/CodeGen/X86/apx/gr8_norex2.ll | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 llvm/test/CodeGen/X86/apx/gr8_norex2.ll diff --git a/llvm/test/CodeGen/X86/apx/gr8_norex2.ll b/llvm/test/CodeGen/X86/apx/gr8_norex2.ll new file mode 100644 index 000000000000..afa62f72abbe --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/gr8_norex2.ll @@ -0,0 +1,9 @@ +; Check ah is not allocatable for register class gr8_norex2 +; RUN: not llc < %s -mtriple=x86_64-unknown-unknown 2>&1 | FileCheck %s + +define void @gr8_norex2() { +; CHECK: error: inline assembly requires more registers than available + %1 = tail call i8 asm sideeffect "movb %r14b, $0", "=r,~{al},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{rbp},~{rsp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"() + ret void +} + -- GitLab From f1ec0d12bb0843f0deab83ef2b5cf1339cbc4f0b Mon Sep 17 00:00:00 2001 From: Nick Anderson Date: Mon, 8 Jan 2024 22:32:59 -0800 Subject: [PATCH 154/652] =?UTF-8?q?Port=20CodeGenPrepare=20to=20new=20pass?= =?UTF-8?q?=20manager=20(and=20BasicBlockSectionsProfil=E2=80=A6=20(#77182?= =?UTF-8?q?)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port CodeGenPrepare to new pass manager and dependency BasicBlockSectionsProfileReader Fixes: #75380 Co-authored-by: Krishna-13-cyber <84722531+Krishna-13-cyber@users.noreply.github.com> --- .../CodeGen/BasicBlockSectionsProfileReader.h | 83 +++++++++--- llvm/include/llvm/CodeGen/CodeGenPrepare.h | 35 +++++ llvm/include/llvm/CodeGen/Passes.h | 4 +- llvm/include/llvm/InitializePasses.h | 4 +- llvm/include/llvm/LinkAllPasses.h | 2 +- llvm/lib/CodeGen/BasicBlockPathCloning.cpp | 11 +- llvm/lib/CodeGen/BasicBlockSections.cpp | 8 +- .../BasicBlockSectionsProfileReader.cpp | 52 ++++++-- llvm/lib/CodeGen/CodeGen.cpp | 2 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 125 ++++++++++++------ llvm/lib/CodeGen/TargetPassConfig.cpp | 4 +- llvm/lib/Passes/PassBuilder.cpp | 2 + llvm/lib/Passes/PassRegistry.def | 2 + .../AArch64/aarch64-codegen-prepare-atp.ll | 2 +- llvm/test/CodeGen/AArch64/and-sink.ll | 4 +- .../CodeGen/AArch64/arm64-bitfield-extract.ll | 2 +- .../AArch64/arm64-codegen-prepare-extload.ll | 6 +- .../test/CodeGen/AArch64/arm64_32-gep-sink.ll | 2 +- .../CodeGen/AArch64/cgp-trivial-phi-node.ll | 2 +- llvm/test/CodeGen/AArch64/convertphitype.ll | 2 +- .../AArch64/scalable-vector-promotion.ll | 2 +- llvm/test/CodeGen/AArch64/sve-vscale.ll | 2 +- .../CodeGen/AArch64/sve2-vscale-sinking.ll | 2 +- .../AMDGPU/cgp-addressing-modes-flat.ll | 8 +- .../AMDGPU/cgp-addressing-modes-gfx1030.ll | 2 +- .../AMDGPU/cgp-addressing-modes-gfx908.ll | 2 +- .../CodeGen/AMDGPU/cgp-addressing-modes.ll | 8 +- llvm/test/CodeGen/ARM/vector-promotion.ll | 4 +- .../Generic/addr-sink-call-multi-arg.ll | 2 +- llvm/test/CodeGen/Generic/addr-use-count.ll | 2 +- .../test/CodeGen/X86/callbr-codegenprepare.ll | 2 +- .../X86/codegen-prepare-addrmode-sext.ll | 2 +- .../CodeGen/X86/codegen-prepare-extload.ll | 6 +- llvm/test/CodeGen/X86/convertphitype.ll | 2 +- .../CodeGen/X86/indirect-br-gep-unmerge.ll | 2 +- llvm/test/CodeGen/X86/pr58538.ll | 4 +- llvm/test/CodeGen/X86/tailcall-cgp-dup.ll | 2 +- llvm/test/CodeGen/X86/tailcall-extract.ll | 2 +- llvm/test/DebugInfo/ARM/salvage-debug-info.ll | 2 +- llvm/test/DebugInfo/X86/zextload.ll | 2 +- llvm/test/Other/codegenprepare-and-debug.ll | 2 +- .../AArch64/combine-address-mode.ll | 2 +- .../CodeGenPrepare/AArch64/free-zext.ll | 2 +- .../gather-scatter-opt-inseltpoison.ll | 2 +- .../AArch64/gather-scatter-opt.ll | 2 +- .../AArch64/overflow-intrinsics.ll | 6 +- .../AArch64/sink-gather-scatter-addressing.ll | 2 +- .../AArch64/trunc-weird-user.ll | 2 +- .../CodeGenPrepare/AArch64/zext-to-shuffle.ll | 2 +- .../CodeGenPrepare/AMDGPU/addressing-modes.ll | 2 +- .../AMDGPU/no-sink-addrspacecast.ll | 2 +- .../AMDGPU/sink-addrspacecast.ll | 2 +- .../CodeGenPrepare/ARM/branch-on-zero.ll | 2 +- .../Transforms/CodeGenPrepare/ARM/dead-gep.ll | 2 +- .../CodeGenPrepare/ARM/memory-intrinsics.ll | 2 +- .../CodeGenPrepare/ARM/overflow-intrinsics.ll | 2 +- .../CodeGenPrepare/ARM/sink-addrmode.ll | 2 +- .../Transforms/CodeGenPrepare/ARM/splitgep.ll | 2 +- .../CodeGenPrepare/ARM/tailcall-dup.ll | 2 +- .../bypass-slow-div-constant-numerator.ll | 2 +- .../NVPTX/bypass-slow-div-not-exact.ll | 2 +- .../NVPTX/bypass-slow-div-special-cases.ll | 2 +- .../CodeGenPrepare/NVPTX/bypass-slow-div.ll | 2 +- .../NVPTX/dont-introduce-addrspacecast.ll | 2 +- .../NVPTX/dont-sink-nop-addrspacecast.ll | 2 +- .../PowerPC/split-store-alignment.ll | 4 +- .../CodeGenPrepare/RISCV/and-mask-sink.ll | 8 +- .../CodeGenPrepare/RISCV/cttz-ctlz.ll | 2 +- .../SPARC/overflow-intrinsics.ll | 6 +- .../CodeGenPrepare/X86/catchpad-phi-cast.ll | 4 +- .../X86/cgp_shuffle_crash-inseltpoison.ll | 2 +- .../CodeGenPrepare/X86/cgp_shuffle_crash.ll | 2 +- .../CodeGenPrepare/X86/computedgoto.ll | 2 +- .../CodeGenPrepare/X86/cttz-ctlz.ll | 10 +- .../X86/delete-assume-dead-code.ll | 2 +- .../CodeGenPrepare/X86/extend-sink-hoist.ll | 2 +- .../CodeGenPrepare/X86/freeze-brcond.ll | 2 +- .../X86/gather-scatter-opt-inseltpoison.ll | 4 +- .../CodeGenPrepare/X86/gather-scatter-opt.ll | 2 +- .../CodeGenPrepare/X86/gep-unmerging.ll | 2 +- .../CodeGenPrepare/X86/invariant.group.ll | 2 +- .../X86/masked-gather-struct-gep.ll | 2 +- .../CodeGenPrepare/X86/nonintegral.ll | 4 +- .../CodeGenPrepare/X86/optimizeSelect-DT.ll | 2 +- .../CodeGenPrepare/X86/overflow-intrinsics.ll | 6 +- .../Transforms/CodeGenPrepare/X86/pr27536.ll | 2 +- .../Transforms/CodeGenPrepare/X86/pr35658.ll | 2 +- .../Transforms/CodeGenPrepare/X86/pr72046.ll | 2 +- .../recursively-delete-dead-instructions.ll | 2 +- .../CodeGenPrepare/X86/remove-assume-block.ll | 2 +- .../Transforms/CodeGenPrepare/X86/select.ll | 6 +- .../CodeGenPrepare/X86/sink-addrmode-base.ll | 4 +- .../X86/sink-addrmode-inseltpoison.ll | 2 +- .../X86/sink-addrmode-select.ll | 2 +- .../X86/sink-addrmode-two-phi.ll | 2 +- .../CodeGenPrepare/X86/sink-addrmode.ll | 2 +- .../CodeGenPrepare/X86/sink-addrspacecast.ll | 2 +- .../CodeGenPrepare/X86/split-indirect-loop.ll | 2 +- .../X86/split-store-alignment.ll | 2 +- .../CodeGenPrepare/X86/statepoint-relocate.ll | 2 +- .../CodeGenPrepare/X86/tailcall-assume-xbb.ll | 2 +- .../X86/vec-shift-inseltpoison.ll | 14 +- .../CodeGenPrepare/X86/vec-shift.ll | 14 +- .../CodeGenPrepare/X86/widenable-condition.ll | 2 +- .../X86/x86-shuffle-sink-inseltpoison.ll | 8 +- .../CodeGenPrepare/X86/x86-shuffle-sink.ll | 8 +- .../CodeGenPrepare/dead-allocation.ll | 2 +- .../CodeGenPrepare/skip-merging-case-block.ll | 2 +- .../Transforms/HotColdSplit/coldentrycount.ll | 2 +- .../codegenprepare-produced-address-math.ll | 2 +- .../section-accurate-samplepgo.ll | 6 +- llvm/tools/opt/opt.cpp | 2 +- 112 files changed, 400 insertions(+), 238 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/CodeGenPrepare.h diff --git a/llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h b/llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h index dfb8d5d9f2f5..bba675f1d3eb 100644 --- a/llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h +++ b/llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h @@ -21,11 +21,14 @@ #include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/IR/Module.h" +#include "llvm/IR/PassManager.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" #include "llvm/Support/Error.h" #include "llvm/Support/LineIterator.h" #include "llvm/Support/MemoryBuffer.h" +#include "llvm/Target/TargetMachine.h" + using namespace llvm; namespace llvm { @@ -72,25 +75,13 @@ template <> struct DenseMapInfo { } }; -class BasicBlockSectionsProfileReader : public ImmutablePass { +class BasicBlockSectionsProfileReader { public: - static char ID; - + friend class BasicBlockSectionsProfileReaderWrapperPass; BasicBlockSectionsProfileReader(const MemoryBuffer *Buf) - : ImmutablePass(ID), MBuf(Buf), - LineIt(*Buf, /*SkipBlanks=*/true, /*CommentMarker=*/'#') { - initializeBasicBlockSectionsProfileReaderPass( - *PassRegistry::getPassRegistry()); - }; + : MBuf(Buf), LineIt(*Buf, /*SkipBlanks=*/true, /*CommentMarker=*/'#'){}; - BasicBlockSectionsProfileReader() : ImmutablePass(ID) { - initializeBasicBlockSectionsProfileReaderPass( - *PassRegistry::getPassRegistry()); - } - - StringRef getPassName() const override { - return "Basic Block Sections Profile Reader"; - } + BasicBlockSectionsProfileReader(){}; // Returns true if basic block sections profile exist for function \p // FuncName. @@ -109,10 +100,6 @@ public: SmallVector> getClonePathsForFunction(StringRef FuncName) const; - // Initializes the FunctionNameToDIFilename map for the current module and - // then reads the profile for the matching functions. - bool doInitialization(Module &M) override; - private: StringRef getAliasName(StringRef FuncName) const { auto R = FuncAliasMap.find(FuncName); @@ -170,7 +157,61 @@ private: // sections profile. \p Buf is a memory buffer that contains the list of // functions and basic block ids to selectively enable basic block sections. ImmutablePass * -createBasicBlockSectionsProfileReaderPass(const MemoryBuffer *Buf); +createBasicBlockSectionsProfileReaderWrapperPass(const MemoryBuffer *Buf); + +/// Analysis pass providing the \c BasicBlockSectionsProfileReader. +/// +/// Note that this pass's result cannot be invalidated, it is immutable for the +/// life of the module. +class BasicBlockSectionsProfileReaderAnalysis + : public AnalysisInfoMixin { + +public: + static AnalysisKey Key; + typedef BasicBlockSectionsProfileReader Result; + BasicBlockSectionsProfileReaderAnalysis(const TargetMachine *TM) : TM(TM) {} + + Result run(Function &F, FunctionAnalysisManager &AM); + +private: + const TargetMachine *TM; +}; + +class BasicBlockSectionsProfileReaderWrapperPass : public ImmutablePass { +public: + static char ID; + BasicBlockSectionsProfileReader BBSPR; + + BasicBlockSectionsProfileReaderWrapperPass(const MemoryBuffer *Buf) + : ImmutablePass(ID), BBSPR(BasicBlockSectionsProfileReader(Buf)) { + initializeBasicBlockSectionsProfileReaderWrapperPassPass( + *PassRegistry::getPassRegistry()); + }; + + BasicBlockSectionsProfileReaderWrapperPass() + : ImmutablePass(ID), BBSPR(BasicBlockSectionsProfileReader()) { + initializeBasicBlockSectionsProfileReaderWrapperPassPass( + *PassRegistry::getPassRegistry()); + } + + StringRef getPassName() const override { + return "Basic Block Sections Profile Reader"; + } + + bool isFunctionHot(StringRef FuncName) const; + + std::pair> + getClusterInfoForFunction(StringRef FuncName) const; + + SmallVector> + getClonePathsForFunction(StringRef FuncName) const; + + // Initializes the FunctionNameToDIFilename map for the current module and + // then reads the profile for the matching functions. + bool doInitialization(Module &M) override; + + BasicBlockSectionsProfileReader &getBBSPR(); +}; } // namespace llvm #endif // LLVM_CODEGEN_BASICBLOCKSECTIONSPROFILEREADER_H diff --git a/llvm/include/llvm/CodeGen/CodeGenPrepare.h b/llvm/include/llvm/CodeGen/CodeGenPrepare.h new file mode 100644 index 000000000000..dee3a9ee53d7 --- /dev/null +++ b/llvm/include/llvm/CodeGen/CodeGenPrepare.h @@ -0,0 +1,35 @@ +//===- CodeGenPrepare.h -----------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// +/// Defines an IR pass for CodeGen Prepare. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_PREPARE_H +#define LLVM_CODEGEN_PREPARE_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { + +class Function; +class TargetMachine; + +class CodeGenPreparePass : public PassInfoMixin { +private: + const TargetMachine *TM; + +public: + CodeGenPreparePass(const TargetMachine *TM) : TM(TM) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); +}; + +} // end namespace llvm + +#endif // LLVM_CODEGEN_PREPARE_H diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index ca9fbb1def76..bbfb8a0dbe26 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -93,9 +93,9 @@ namespace llvm { MachineFunctionPass *createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel); - /// createCodeGenPreparePass - Transform the code to expose more pattern + /// createCodeGenPrepareLegacyPass - Transform the code to expose more pattern /// matching during instruction selection. - FunctionPass *createCodeGenPreparePass(); + FunctionPass *createCodeGenPrepareLegacyPass(); /// This pass implements generation of target-specific intrinsics to support /// handling of complex number arithmetic diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 46b1e95c3c15..3db639a68724 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -54,7 +54,7 @@ void initializeAssignmentTrackingAnalysisPass(PassRegistry &); void initializeAssumptionCacheTrackerPass(PassRegistry&); void initializeAtomicExpandPass(PassRegistry&); void initializeBasicBlockPathCloningPass(PassRegistry &); -void initializeBasicBlockSectionsProfileReaderPass(PassRegistry &); +void initializeBasicBlockSectionsProfileReaderWrapperPassPass(PassRegistry &); void initializeBasicBlockSectionsPass(PassRegistry &); void initializeBarrierNoopPass(PassRegistry&); void initializeBasicAAWrapperPassPass(PassRegistry&); @@ -75,7 +75,7 @@ void initializeCallGraphDOTPrinterPass(PassRegistry&); void initializeCallGraphViewerPass(PassRegistry&); void initializeCallGraphWrapperPassPass(PassRegistry&); void initializeCheckDebugMachineModulePass(PassRegistry &); -void initializeCodeGenPreparePass(PassRegistry&); +void initializeCodeGenPrepareLegacyPassPass(PassRegistry &); void initializeComplexDeinterleavingLegacyPassPass(PassRegistry&); void initializeConstantHoistingLegacyPassPass(PassRegistry&); void initializeCycleInfoWrapperPassPass(PassRegistry &); diff --git a/llvm/include/llvm/LinkAllPasses.h b/llvm/include/llvm/LinkAllPasses.h index 7a21876e565a..fe7fedad18bc 100644 --- a/llvm/include/llvm/LinkAllPasses.h +++ b/llvm/include/llvm/LinkAllPasses.h @@ -113,7 +113,7 @@ namespace { (void) llvm::createTailCallEliminationPass(); (void)llvm::createTLSVariableHoistPass(); (void) llvm::createConstantHoistingPass(); - (void) llvm::createCodeGenPreparePass(); + (void)llvm::createCodeGenPrepareLegacyPass(); (void) llvm::createEarlyCSEPass(); (void) llvm::createGVNPass(); (void) llvm::createPostDomTree(); diff --git a/llvm/lib/CodeGen/BasicBlockPathCloning.cpp b/llvm/lib/CodeGen/BasicBlockPathCloning.cpp index 5d5f3c3da481..901542e8507b 100644 --- a/llvm/lib/CodeGen/BasicBlockPathCloning.cpp +++ b/llvm/lib/CodeGen/BasicBlockPathCloning.cpp @@ -196,7 +196,7 @@ class BasicBlockPathCloning : public MachineFunctionPass { public: static char ID; - BasicBlockSectionsProfileReader *BBSectionsProfileReader = nullptr; + BasicBlockSectionsProfileReaderWrapperPass *BBSectionsProfileReader = nullptr; BasicBlockPathCloning() : MachineFunctionPass(ID) { initializeBasicBlockPathCloningPass(*PassRegistry::getPassRegistry()); @@ -218,7 +218,7 @@ INITIALIZE_PASS_BEGIN( BasicBlockPathCloning, "bb-path-cloning", "Applies path clonings for the -basic-block-sections=list option", false, false) -INITIALIZE_PASS_DEPENDENCY(BasicBlockSectionsProfileReader) +INITIALIZE_PASS_DEPENDENCY(BasicBlockSectionsProfileReaderWrapperPass) INITIALIZE_PASS_END( BasicBlockPathCloning, "bb-path-cloning", "Applies path clonings for the -basic-block-sections=list option", false, @@ -230,13 +230,14 @@ bool BasicBlockPathCloning::runOnMachineFunction(MachineFunction &MF) { if (hasInstrProfHashMismatch(MF)) return false; - return ApplyCloning(MF, getAnalysis() - .getClonePathsForFunction(MF.getName())); + return ApplyCloning(MF, + getAnalysis() + .getClonePathsForFunction(MF.getName())); } void BasicBlockPathCloning::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/CodeGen/BasicBlockSections.cpp b/llvm/lib/CodeGen/BasicBlockSections.cpp index 42997d2287d6..94b5a503fbd0 100644 --- a/llvm/lib/CodeGen/BasicBlockSections.cpp +++ b/llvm/lib/CodeGen/BasicBlockSections.cpp @@ -103,7 +103,7 @@ class BasicBlockSections : public MachineFunctionPass { public: static char ID; - BasicBlockSectionsProfileReader *BBSectionsProfileReader = nullptr; + BasicBlockSectionsProfileReaderWrapperPass *BBSectionsProfileReader = nullptr; BasicBlockSections() : MachineFunctionPass(ID) { initializeBasicBlockSectionsPass(*PassRegistry::getPassRegistry()); @@ -128,7 +128,7 @@ INITIALIZE_PASS_BEGIN( "Prepares for basic block sections, by splitting functions " "into clusters of basic blocks.", false, false) -INITIALIZE_PASS_DEPENDENCY(BasicBlockSectionsProfileReader) +INITIALIZE_PASS_DEPENDENCY(BasicBlockSectionsProfileReaderWrapperPass) INITIALIZE_PASS_END(BasicBlockSections, "bbsections-prepare", "Prepares for basic block sections, by splitting functions " "into clusters of basic blocks.", @@ -306,7 +306,7 @@ bool BasicBlockSections::runOnMachineFunction(MachineFunction &MF) { DenseMap FuncClusterInfo; if (BBSectionsType == BasicBlockSection::List) { auto [HasProfile, ClusterInfo] = - getAnalysis() + getAnalysis() .getClusterInfoForFunction(MF.getName()); if (!HasProfile) return false; @@ -362,7 +362,7 @@ bool BasicBlockSections::runOnMachineFunction(MachineFunction &MF) { void BasicBlockSections::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp b/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp index 15b6f63e8632..79e42d9304df 100644 --- a/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp +++ b/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp @@ -30,8 +30,9 @@ using namespace llvm; -char BasicBlockSectionsProfileReader::ID = 0; -INITIALIZE_PASS(BasicBlockSectionsProfileReader, "bbsections-profile-reader", +char BasicBlockSectionsProfileReaderWrapperPass::ID = 0; +INITIALIZE_PASS(BasicBlockSectionsProfileReaderWrapperPass, + "bbsections-profile-reader", "Reads and parses a basic block sections profile.", false, false) @@ -395,11 +396,11 @@ Error BasicBlockSectionsProfileReader::ReadProfile() { } } -bool BasicBlockSectionsProfileReader::doInitialization(Module &M) { - if (!MBuf) +bool BasicBlockSectionsProfileReaderWrapperPass::doInitialization(Module &M) { + if (!BBSPR.MBuf) return false; // Get the function name to debug info filename mapping. - FunctionNameToDIFilename.clear(); + BBSPR.FunctionNameToDIFilename.clear(); for (const Function &F : M) { SmallString<128> DIFilename; if (F.isDeclaration()) @@ -411,15 +412,46 @@ bool BasicBlockSectionsProfileReader::doInitialization(Module &M) { DIFilename = sys::path::remove_leading_dotslash(CU->getFilename()); } [[maybe_unused]] bool inserted = - FunctionNameToDIFilename.try_emplace(F.getName(), DIFilename).second; + BBSPR.FunctionNameToDIFilename.try_emplace(F.getName(), DIFilename) + .second; assert(inserted); } - if (auto Err = ReadProfile()) + if (auto Err = BBSPR.ReadProfile()) report_fatal_error(std::move(Err)); return false; } -ImmutablePass * -llvm::createBasicBlockSectionsProfileReaderPass(const MemoryBuffer *Buf) { - return new BasicBlockSectionsProfileReader(Buf); +AnalysisKey BasicBlockSectionsProfileReaderAnalysis::Key; + +BasicBlockSectionsProfileReader +BasicBlockSectionsProfileReaderAnalysis::run(Function &F, + FunctionAnalysisManager &AM) { + return BasicBlockSectionsProfileReader(TM->getBBSectionsFuncListBuf()); +} + +bool BasicBlockSectionsProfileReaderWrapperPass::isFunctionHot( + StringRef FuncName) const { + return BBSPR.isFunctionHot(FuncName); +} + +std::pair> +BasicBlockSectionsProfileReaderWrapperPass::getClusterInfoForFunction( + StringRef FuncName) const { + return BBSPR.getClusterInfoForFunction(FuncName); +} + +SmallVector> +BasicBlockSectionsProfileReaderWrapperPass::getClonePathsForFunction( + StringRef FuncName) const { + return BBSPR.getClonePathsForFunction(FuncName); +} + +BasicBlockSectionsProfileReader & +BasicBlockSectionsProfileReaderWrapperPass::getBBSPR() { + return BBSPR; +} + +ImmutablePass *llvm::createBasicBlockSectionsProfileReaderWrapperPass( + const MemoryBuffer *Buf) { + return new BasicBlockSectionsProfileReaderWrapperPass(Buf); } diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 7b73a7b11ddf..418066452c17 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -30,7 +30,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeCFIFixupPass(Registry); initializeCFIInstrInserterPass(Registry); initializeCheckDebugMachineModulePass(Registry); - initializeCodeGenPreparePass(Registry); + initializeCodeGenPrepareLegacyPassPass(Registry); initializeDeadMachineInstructionElimPass(Registry); initializeDebugifyMachineModulePass(Registry); initializeDetectDeadLanesPass(Registry); diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 5bd4c6b067d7..b8bfb9742bfb 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -12,6 +12,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/CodeGenPrepare.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" @@ -301,7 +302,8 @@ using ValueToSExts = MapVector; class TypePromotionTransaction; -class CodeGenPrepare : public FunctionPass { +class CodeGenPrepare { + friend class CodeGenPrepareLegacyPass; const TargetMachine *TM = nullptr; const TargetSubtargetInfo *SubtargetInfo = nullptr; const TargetLowering *TLI = nullptr; @@ -365,6 +367,8 @@ class CodeGenPrepare : public FunctionPass { std::unique_ptr DT; public: + CodeGenPrepare(){}; + CodeGenPrepare(const TargetMachine *TM) : TM(TM){}; /// If encounter huge function, we need to limit the build time. bool IsHugeFunc = false; @@ -374,15 +378,7 @@ public: /// to insert such BB into FreshBBs for huge function. SmallSet FreshBBs; - static char ID; // Pass identification, replacement for typeid - - CodeGenPrepare() : FunctionPass(ID) { - initializeCodeGenPreparePass(*PassRegistry::getPassRegistry()); - } - - bool runOnFunction(Function &F) override; - - void releaseMemory() override { + void releaseMemory() { // Clear per function information. InsertedInsts.clear(); PromotedInsts.clear(); @@ -391,17 +387,7 @@ public: BFI.reset(); } - StringRef getPassName() const override { return "CodeGen Prepare"; } - - void getAnalysisUsage(AnalysisUsage &AU) const override { - // FIXME: When we can selectively preserve passes, preserve the domtree. - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); - AU.addUsedIfAvailable(); - } + bool run(Function &F, FunctionAnalysisManager &AM); private: template @@ -488,45 +474,108 @@ private: bool combineToUSubWithOverflow(CmpInst *Cmp, ModifyDT &ModifiedDT); bool combineToUAddWithOverflow(CmpInst *Cmp, ModifyDT &ModifiedDT); void verifyBFIUpdates(Function &F); + bool _run(Function &F); +}; + +class CodeGenPrepareLegacyPass : public FunctionPass { +public: + static char ID; // Pass identification, replacement for typeid + + CodeGenPrepareLegacyPass() : FunctionPass(ID) { + initializeCodeGenPrepareLegacyPassPass(*PassRegistry::getPassRegistry()); + } + + bool runOnFunction(Function &F) override; + + StringRef getPassName() const override { return "CodeGen Prepare"; } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + // FIXME: When we can selectively preserve passes, preserve the domtree. + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addUsedIfAvailable(); + } }; } // end anonymous namespace -char CodeGenPrepare::ID = 0; +char CodeGenPrepareLegacyPass::ID = 0; -INITIALIZE_PASS_BEGIN(CodeGenPrepare, DEBUG_TYPE, +bool CodeGenPrepareLegacyPass::runOnFunction(Function &F) { + if (skipFunction(F)) + return false; + auto TM = &getAnalysis().getTM(); + CodeGenPrepare CGP(TM); + CGP.DL = &F.getParent()->getDataLayout(); + CGP.SubtargetInfo = TM->getSubtargetImpl(F); + CGP.TLI = CGP.SubtargetInfo->getTargetLowering(); + CGP.TRI = CGP.SubtargetInfo->getRegisterInfo(); + CGP.TLInfo = &getAnalysis().getTLI(F); + CGP.TTI = &getAnalysis().getTTI(F); + CGP.LI = &getAnalysis().getLoopInfo(); + CGP.BPI.reset(new BranchProbabilityInfo(F, *CGP.LI)); + CGP.BFI.reset(new BlockFrequencyInfo(F, *CGP.BPI, *CGP.LI)); + CGP.PSI = &getAnalysis().getPSI(); + auto BBSPRWP = + getAnalysisIfAvailable(); + CGP.BBSectionsProfileReader = BBSPRWP ? &BBSPRWP->getBBSPR() : nullptr; + + return CGP._run(F); +} + +INITIALIZE_PASS_BEGIN(CodeGenPrepareLegacyPass, DEBUG_TYPE, "Optimize for code generation", false, false) -INITIALIZE_PASS_DEPENDENCY(BasicBlockSectionsProfileReader) +INITIALIZE_PASS_DEPENDENCY(BasicBlockSectionsProfileReaderWrapperPass) INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass) -INITIALIZE_PASS_END(CodeGenPrepare, DEBUG_TYPE, "Optimize for code generation", - false, false) +INITIALIZE_PASS_END(CodeGenPrepareLegacyPass, DEBUG_TYPE, + "Optimize for code generation", false, false) -FunctionPass *llvm::createCodeGenPreparePass() { return new CodeGenPrepare(); } +FunctionPass *llvm::createCodeGenPrepareLegacyPass() { + return new CodeGenPrepareLegacyPass(); +} -bool CodeGenPrepare::runOnFunction(Function &F) { - if (skipFunction(F)) - return false; +PreservedAnalyses CodeGenPreparePass::run(Function &F, + FunctionAnalysisManager &AM) { + CodeGenPrepare CGP(TM); - DL = &F.getParent()->getDataLayout(); + bool Changed = CGP.run(F, AM); + if (!Changed) + return PreservedAnalyses::all(); - bool EverMadeChange = false; + PreservedAnalyses PA; + PA.preserve(); + PA.preserve(); + PA.preserve(); + return PA; +} - TM = &getAnalysis().getTM(); +bool CodeGenPrepare::run(Function &F, FunctionAnalysisManager &AM) { + DL = &F.getParent()->getDataLayout(); SubtargetInfo = TM->getSubtargetImpl(F); TLI = SubtargetInfo->getTargetLowering(); TRI = SubtargetInfo->getRegisterInfo(); - TLInfo = &getAnalysis().getTLI(F); - TTI = &getAnalysis().getTTI(F); - LI = &getAnalysis().getLoopInfo(); + TLInfo = &AM.getResult(F); + TTI = &AM.getResult(F); + LI = &AM.getResult(F); BPI.reset(new BranchProbabilityInfo(F, *LI)); BFI.reset(new BlockFrequencyInfo(F, *BPI, *LI)); - PSI = &getAnalysis().getPSI(); + auto &MAMProxy = AM.getResult(F); + PSI = MAMProxy.getCachedResult(*F.getParent()); BBSectionsProfileReader = - getAnalysisIfAvailable(); + AM.getCachedResult(F); + return _run(F); +} + +bool CodeGenPrepare::_run(Function &F) { + bool EverMadeChange = false; + OptSize = F.hasOptSize(); // Use the basic-block-sections profile to promote hot functions to .text.hot // if requested. diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 4003a08a5422..3bbc792f4cbf 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -978,7 +978,7 @@ void TargetPassConfig::addPassesToHandleExceptions() { /// before exception handling preparation passes. void TargetPassConfig::addCodeGenPrepare() { if (getOptLevel() != CodeGenOptLevel::None && !DisableCGP) - addPass(createCodeGenPreparePass()); + addPass(createCodeGenPrepareLegacyPass()); } /// Add common passes that perform LLVM IR to IR transforms in preparation for @@ -1271,7 +1271,7 @@ void TargetPassConfig::addMachinePasses() { // together. Update this check once we have addressed any issues. if (TM->getBBSectionsType() != llvm::BasicBlockSection::None) { if (TM->getBBSectionsType() == llvm::BasicBlockSection::List) { - addPass(llvm::createBasicBlockSectionsProfileReaderPass( + addPass(llvm::createBasicBlockSectionsProfileReaderWrapperPass( TM->getBBSectionsFuncListBuf())); addPass(llvm::createBasicBlockPathCloningPass()); } diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 649451edc0e2..b4a48e713d05 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -72,7 +72,9 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" #include "llvm/Analysis/UniformityAnalysis.h" +#include "llvm/CodeGen/BasicBlockSectionsProfileReader.h" #include "llvm/CodeGen/CallBrPrepare.h" +#include "llvm/CodeGen/CodeGenPrepare.h" #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandLargeFpConvert.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index eaa7c3fc8924..1b6c0e4dd3bb 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -230,6 +230,7 @@ CGSCC_PASS_WITH_PARAMS( FUNCTION_ANALYSIS("aa", AAManager()) FUNCTION_ANALYSIS("access-info", LoopAccessAnalysis()) FUNCTION_ANALYSIS("assumptions", AssumptionAnalysis()) +FUNCTION_ANALYSIS("bb-sections-profile-reader", BasicBlockSectionsProfileReaderAnalysis(TM)) FUNCTION_ANALYSIS("block-freq", BlockFrequencyAnalysis()) FUNCTION_ANALYSIS("branch-prob", BranchProbabilityAnalysis()) FUNCTION_ANALYSIS("cycles", CycleAnalysis()) @@ -291,6 +292,7 @@ FUNCTION_PASS("break-crit-edges", BreakCriticalEdgesPass()) FUNCTION_PASS("callbrprepare", CallBrPreparePass()) FUNCTION_PASS("callsite-splitting", CallSiteSplittingPass()) FUNCTION_PASS("chr", ControlHeightReductionPass()) +FUNCTION_PASS("codegenprepare", CodeGenPreparePass(TM)) FUNCTION_PASS("consthoist", ConstantHoistingPass()) FUNCTION_PASS("constraint-elimination", ConstraintEliminationPass()) FUNCTION_PASS("coro-elide", CoroElidePass()) diff --git a/llvm/test/CodeGen/AArch64/aarch64-codegen-prepare-atp.ll b/llvm/test/CodeGen/AArch64/aarch64-codegen-prepare-atp.ll index 92f29dac13fa..10b594978bee 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-codegen-prepare-atp.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-codegen-prepare-atp.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare < %s -S | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' < %s -S | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-gnu" diff --git a/llvm/test/CodeGen/AArch64/and-sink.ll b/llvm/test/CodeGen/AArch64/and-sink.ll index f4e9551259e4..4d085869de24 100644 --- a/llvm/test/CodeGen/AArch64/and-sink.ll +++ b/llvm/test/CodeGen/AArch64/and-sink.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s -; RUN: opt -S -codegenprepare -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s -; RUN: opt -S -codegenprepare -cgpp-huge-func=0 -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s +; RUN: opt -S -passes='require,function(codegenprepare)' -cgpp-huge-func=0 -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s @A = dso_local global i32 zeroinitializer @B = dso_local global i32 zeroinitializer diff --git a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll index 6041904dc0f3..2b42a3f29a72 100644 --- a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll +++ b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck --check-prefix=LLC %s %struct.X = type { i8, i8, [2 x i8] } diff --git a/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll b/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll index 23cbad0d15b4..78a0bb4982b6 100644 --- a/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll +++ b/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll @@ -1,6 +1,6 @@ -; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS -; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS -; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=DISABLE +; RUN: opt -passes='require,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS +; RUN: opt -passes='require,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS +; RUN: opt -passes='require,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=DISABLE ; CodeGenPrepare should move the zext into the block with the load ; so that SelectionDAG can select it with the load. diff --git a/llvm/test/CodeGen/AArch64/arm64_32-gep-sink.ll b/llvm/test/CodeGen/AArch64/arm64_32-gep-sink.ll index 964c669439d4..c33159163901 100644 --- a/llvm/test/CodeGen/AArch64/arm64_32-gep-sink.ll +++ b/llvm/test/CodeGen/AArch64/arm64_32-gep-sink.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -codegenprepare -mtriple=arm64_32-apple-ios %s -S -o - | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=arm64_32-apple-ios %s -S -o - | FileCheck %s define void @test_simple_sink(ptr %base, i64 %offset) { ; CHECK-LABEL: define void @test_simple_sink( diff --git a/llvm/test/CodeGen/AArch64/cgp-trivial-phi-node.ll b/llvm/test/CodeGen/AArch64/cgp-trivial-phi-node.ll index 98b820709e82..dfcedc8dd984 100644 --- a/llvm/test/CodeGen/AArch64/cgp-trivial-phi-node.ll +++ b/llvm/test/CodeGen/AArch64/cgp-trivial-phi-node.ll @@ -1,5 +1,5 @@ ; Checks that case when GEP is bound to trivial PHI node is correctly handled. -; RUN: opt %s -mtriple=aarch64-linux-gnu -codegenprepare -S -o - | FileCheck %s +; RUN: opt %s -mtriple=aarch64-linux-gnu -passes='require,function(codegenprepare)' -S -o - | FileCheck %s ; CHECK: define void @crash(ptr %s, i32 %n) { ; CHECK-NEXT: entry: diff --git a/llvm/test/CodeGen/AArch64/convertphitype.ll b/llvm/test/CodeGen/AArch64/convertphitype.ll index a5fc46d2abca..b723b470266a 100644 --- a/llvm/test/CodeGen/AArch64/convertphitype.ll +++ b/llvm/test/CodeGen/AArch64/convertphitype.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -cgp-optimize-phi-types %s -S | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -cgp-optimize-phi-types %s -S | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-gnu" diff --git a/llvm/test/CodeGen/AArch64/scalable-vector-promotion.ll b/llvm/test/CodeGen/AArch64/scalable-vector-promotion.ll index e6ab52dc9e61..a45f3733dbda 100644 --- a/llvm/test/CodeGen/AArch64/scalable-vector-promotion.ll +++ b/llvm/test/CodeGen/AArch64/scalable-vector-promotion.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=aarch64 -codegenprepare -S < %s | FileCheck %s +; RUN: opt -mtriple=aarch64 -passes='require,function(codegenprepare)' -S < %s | FileCheck %s ; This test intends to check vector promotion for scalable vector. Current target lowering ; rejects scalable vector before reaching getConstantVector() in CodeGenPrepare. This test diff --git a/llvm/test/CodeGen/AArch64/sve-vscale.ll b/llvm/test/CodeGen/AArch64/sve-vscale.ll index fa48808ff7f8..7214c98cc318 100644 --- a/llvm/test/CodeGen/AArch64/sve-vscale.ll +++ b/llvm/test/CodeGen/AArch64/sve-vscale.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple aarch64 -mattr=+sve -asm-verbose=0 < %s | FileCheck %s -; RUN: opt -mtriple=aarch64 -codegenprepare -S < %s | llc -mtriple=aarch64 -mattr=+sve -asm-verbose=0 | FileCheck %s +; RUN: opt -mtriple=aarch64 -passes='require,function(codegenprepare)' -S < %s | llc -mtriple=aarch64 -mattr=+sve -asm-verbose=0 | FileCheck %s ; ; RDVL diff --git a/llvm/test/CodeGen/AArch64/sve2-vscale-sinking.ll b/llvm/test/CodeGen/AArch64/sve2-vscale-sinking.ll index c80aa82ef9a8..bf3082d99c66 100644 --- a/llvm/test/CodeGen/AArch64/sve2-vscale-sinking.ll +++ b/llvm/test/CodeGen/AArch64/sve2-vscale-sinking.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 -; RUN: opt -codegenprepare -S -o - %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -o - %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll index 3005b17e0524..88a8e7cc4220 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck --check-prefixes=OPT,OPT-GFX7 %s -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga < %s | FileCheck --check-prefixes=OPT,OPT-GFX8 %s -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 < %s | FileCheck --check-prefixes=OPT,OPT-GFX9 %s -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx1030 < %s | FileCheck --check-prefixes=OPT,OPT-GFX10 %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck --check-prefixes=OPT,OPT-GFX7 %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=tonga < %s | FileCheck --check-prefixes=OPT,OPT-GFX8 %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 < %s | FileCheck --check-prefixes=OPT,OPT-GFX9 %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=gfx1030 < %s | FileCheck --check-prefixes=OPT,OPT-GFX10 %s ; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=GFX7 %s ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll index aee6f0e82d25..1588dde19cfb 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s ; Make sure we match the addressing mode offset of csub intrinsics across blocks. diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll index 494b4b5c48ba..ac50fb86c96f 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=GCN %s ; Make sure we match the addressing mode offset of globla.atomic.fadd intrinsics across blocks. diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll index 0e61547c27b4..65a604c98c4b 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll @@ -1,7 +1,7 @@ -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tahiti < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-SI -check-prefix=OPT-SICIVI %s -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-SICIVI %s -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-SICIVI %s -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=tahiti < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-SI -check-prefix=OPT-SICIVI %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-SICIVI %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-SICIVI %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s ; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=SICIVI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-scalarize-global-loads=false -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s diff --git a/llvm/test/CodeGen/ARM/vector-promotion.ll b/llvm/test/CodeGen/ARM/vector-promotion.ll index 3e314306ff08..f4a2a4a4521e 100644 --- a/llvm/test/CodeGen/ARM/vector-promotion.ll +++ b/llvm/test/CodeGen/ARM/vector-promotion.ll @@ -1,5 +1,5 @@ -; RUN: opt -codegenprepare -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon -S | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-NORMAL %s -; RUN: opt -codegenprepare -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon -S -stress-cgp-store-extract | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-STRESS %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon -S | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-NORMAL %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon -S -stress-cgp-store-extract | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-STRESS %s ; RUN: llc -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon | FileCheck --check-prefix=ASM %s ; IR-BOTH-LABEL: @simpleOneInstructionPromotion diff --git a/llvm/test/CodeGen/Generic/addr-sink-call-multi-arg.ll b/llvm/test/CodeGen/Generic/addr-sink-call-multi-arg.ll index b02bdc3b5724..2a8d05c4f26e 100644 --- a/llvm/test/CodeGen/Generic/addr-sink-call-multi-arg.ll +++ b/llvm/test/CodeGen/Generic/addr-sink-call-multi-arg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s ; REQUIRES: aarch64-registered-target ; Check that we don't give up if unable to sink the first argument. diff --git a/llvm/test/CodeGen/Generic/addr-use-count.ll b/llvm/test/CodeGen/Generic/addr-use-count.ll index 00943b5a58e2..5c4c0c618794 100644 --- a/llvm/test/CodeGen/Generic/addr-use-count.ll +++ b/llvm/test/CodeGen/Generic/addr-use-count.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s ; REQUIRES: aarch64-registered-target ; Test that `%addr` is sunk, after we've increased limit on the number of the memory uses to scan. diff --git a/llvm/test/CodeGen/X86/callbr-codegenprepare.ll b/llvm/test/CodeGen/X86/callbr-codegenprepare.ll index 854cc4bf7a9c..d2380a730b5b 100644 --- a/llvm/test/CodeGen/X86/callbr-codegenprepare.ll +++ b/llvm/test/CodeGen/X86/callbr-codegenprepare.ll @@ -1,4 +1,4 @@ -;; RUN: opt -S -codegenprepare < %s | FileCheck %s +;; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s ;; Ensure that codegenprepare (via InstSimplify) doesn't eliminate the ;; phi here (which would cause a module verification error). diff --git a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll index 6e95c91e7398..c611e89f2786 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll +++ b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare %s -o - | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' %s -o - | FileCheck %s ; This file tests the different cases what are involved when codegen prepare ; tries to get sign/zero extension out of the way of addressing mode. ; This tests require an actual target as addressing mode decisions depends diff --git a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll index ff0ac5bfd6a7..ce87985fb3a0 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll +++ b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-win64 | FileCheck %s -; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS -; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS -; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE +; RUN: opt -passes='require,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS +; RUN: opt -passes='require,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS +; RUN: opt -passes='require,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE ; rdar://7304838 ; CodeGenPrepare should move the zext into the block with the load diff --git a/llvm/test/CodeGen/X86/convertphitype.ll b/llvm/test/CodeGen/X86/convertphitype.ll index df01612252bf..6c77236fc698 100644 --- a/llvm/test/CodeGen/X86/convertphitype.ll +++ b/llvm/test/CodeGen/X86/convertphitype.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -cgp-optimize-phi-types=true %s -S | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -cgp-optimize-phi-types=true %s -S | FileCheck %s target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/indirect-br-gep-unmerge.ll b/llvm/test/CodeGen/X86/indirect-br-gep-unmerge.ll index 6b953e300425..ac23de49d3bd 100644 --- a/llvm/test/CodeGen/X86/indirect-br-gep-unmerge.ll +++ b/llvm/test/CodeGen/X86/indirect-br-gep-unmerge.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -S -codegenprepare %s -o - | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' %s -o - | FileCheck %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/pr58538.ll b/llvm/test/CodeGen/X86/pr58538.ll index 6c4103718950..7bae2594fc02 100644 --- a/llvm/test/CodeGen/X86/pr58538.ll +++ b/llvm/test/CodeGen/X86/pr58538.ll @@ -1,5 +1,5 @@ -; RUN: opt -codegenprepare -mtriple=x86_64 %s -S -o - | FileCheck %s -; RUN: opt -codegenprepare -mtriple=i386 %s -S -o - | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64 %s -S -o - | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=i386 %s -S -o - | FileCheck %s define i32 @f(i32 %0) { ; CHECK-LABEL: @f diff --git a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll index 48440558283d..75bbae1050d6 100644 --- a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll +++ b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -; RUN: opt -S -codegenprepare %s -mtriple=x86_64-apple-darwin -o - | FileCheck %s --check-prefix OPT +; RUN: opt -S -passes='require,function(codegenprepare)' %s -mtriple=x86_64-apple-darwin -o - | FileCheck %s --check-prefix OPT ; Teach CGP to dup returns to enable tail call optimization. ; rdar://9147433 diff --git a/llvm/test/CodeGen/X86/tailcall-extract.ll b/llvm/test/CodeGen/X86/tailcall-extract.ll index c3597a8e5b99..7a6c75c44ca7 100644 --- a/llvm/test/CodeGen/X86/tailcall-extract.ll +++ b/llvm/test/CodeGen/X86/tailcall-extract.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s -; RUN: opt -codegenprepare -S -mtriple=x86_64-linux < %s | FileCheck %s --check-prefix OPT +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64-linux < %s | FileCheck %s --check-prefix OPT ; The exit block containing extractvalue can be duplicated into the BB diff --git a/llvm/test/DebugInfo/ARM/salvage-debug-info.ll b/llvm/test/DebugInfo/ARM/salvage-debug-info.ll index 3717abada42e..1564a80ded0e 100644 --- a/llvm/test/DebugInfo/ARM/salvage-debug-info.ll +++ b/llvm/test/DebugInfo/ARM/salvage-debug-info.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S %s -o - | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S %s -o - | FileCheck %s ; typedef struct info { ; unsigned long long size; ; } info_t; diff --git a/llvm/test/DebugInfo/X86/zextload.ll b/llvm/test/DebugInfo/X86/zextload.ll index 888e230c258d..05d92b09c20c 100644 --- a/llvm/test/DebugInfo/X86/zextload.ll +++ b/llvm/test/DebugInfo/X86/zextload.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s ; ; This test case was generated from the following source code: ; diff --git a/llvm/test/Other/codegenprepare-and-debug.ll b/llvm/test/Other/codegenprepare-and-debug.ll index 9023e8f21997..95f48c630efb 100644 --- a/llvm/test/Other/codegenprepare-and-debug.ll +++ b/llvm/test/Other/codegenprepare-and-debug.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s ; RUN: opt -strip-debug -codegenprepare -S < %s | FileCheck %s ; REQUIRES: x86-registered-target diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll index 91194864c013..25d4492f4c16 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s @_MergedGlobals = external dso_local global <{ i32, i32 }>, align 4 diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll index adb13f1a4c9f..de7eeada6024 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -mtriple=aarch64-linux %s | FileCheck -enable-var-scope %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=aarch64-linux %s | FileCheck -enable-var-scope %s ; Test for CodeGenPrepare::optimizeLoadExt(): simple case: two loads ; feeding a phi that zext's each loaded value. diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll index 0114d7f9f409..469d818af28f 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll index e4c5b4ceee54..6444f6adcdcc 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/overflow-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/overflow-intrinsics.ll index 4caf6d0dc893..f72679f55e11 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/overflow-intrinsics.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/overflow-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S < %s | FileCheck %s -; RUN: opt -enable-debugify -codegenprepare -S < %s 2>&1 | FileCheck %s -check-prefix=DEBUG +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s +; RUN: opt -enable-debugify -passes='require,function(codegenprepare)' -S < %s 2>&1 | FileCheck %s -check-prefix=DEBUG ; Subset of tests from llvm/tests/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll ; to test shouldFormOverflowOp on SPARC, where it is not profitable to create @@ -167,5 +167,5 @@ define i1 @usubo_ult_i64_math_overflow_used(i64 %x, i64 %y, ptr %p) { ret i1 %ov } -; Check that every instruction inserted by -codegenprepare has a debug location. +; Check that every instruction inserted by -passes='require,function(codegenprepare)' has a debug location. ; DEBUG: CheckModuleDebugify: PASS diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/sink-gather-scatter-addressing.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/sink-gather-scatter-addressing.ll index 73322836d1b8..f170c8ff18c1 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/sink-gather-scatter-addressing.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/sink-gather-scatter-addressing.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -S --codegenprepare < %s | FileCheck %s +; RUN: opt -S --passes='require,function(codegenprepare)' < %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/trunc-weird-user.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/trunc-weird-user.ll index 6a8b5733889e..fa53d536fa38 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/trunc-weird-user.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/trunc-weird-user.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -mtriple=arm64-apple-ios7.0 %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=arm64-apple-ios7.0 %s | FileCheck %s %foo = type { i8 } diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/zext-to-shuffle.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/zext-to-shuffle.ll index 60b1e81e3dcd..8999e8d901ad 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/zext-to-shuffle.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/zext-to-shuffle.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S %s | FileCheck %s target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "arm64-apple-ios" diff --git a/llvm/test/Transforms/CodeGenPrepare/AMDGPU/addressing-modes.ll b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/addressing-modes.ll index acd40d744f71..20a5a9ededac 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AMDGPU/addressing-modes.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/addressing-modes.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare -mtriple=amdgcn--amdhsa < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn--amdhsa < %s | FileCheck %s define amdgpu_kernel void @test_sink_as999_small_max_mubuf_offset(ptr addrspace(999) %out, ptr addrspace(999) %in) { ; CHECK-LABEL: @test_sink_as999_small_max_mubuf_offset( diff --git a/llvm/test/Transforms/CodeGenPrepare/AMDGPU/no-sink-addrspacecast.ll b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/no-sink-addrspacecast.ll index 63098ab098a2..c64d5a357f3a 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AMDGPU/no-sink-addrspacecast.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/no-sink-addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown < %s | FileCheck -check-prefix=ASC -check-prefix=COMMON %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-unknown-unknown < %s | FileCheck -check-prefix=ASC -check-prefix=COMMON %s ; COMMON-LABEL: @test_sink_ptrtoint_asc( ; ASC: addrspacecast diff --git a/llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll index 7e6020629df8..77e79a902f3b 100644 --- a/llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -S -codegenprepare -mtriple=amdgcn--amdhsa < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn--amdhsa < %s | FileCheck %s define i64 @no_sink_local_to_flat(i1 %pred, ptr addrspace(3) %ptr) { ; CHECK-LABEL: define i64 @no_sink_local_to_flat( diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll index 996cab1d1d2c..ff5cef7e781f 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main-none-eabi" diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/dead-gep.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/dead-gep.ll index 52c06fd52b7b..f84491933b25 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/dead-gep.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/dead-gep.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S %s -o - | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S %s -o - | FileCheck %s target triple = "thumbv7-apple-ios7.0.0" diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll index ae76dbda4aa1..9bec9b53ed0c 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -mtriple=arm7-unknown-unknown -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=arm7-unknown-unknown -S < %s | FileCheck %s declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1) nounwind declare void @llvm.memmove.p0.p0.i32(ptr, ptr, i32, i1) nounwind diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/overflow-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/overflow-intrinsics.ll index 3fbc21331410..2f32ef94f82c 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/overflow-intrinsics.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/overflow-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8m.main-arm-none-eabi" diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll index 838486aa2486..49cffe286a54 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -mtriple=thumbv7m -disable-complex-addr-modes=false -addr-sink-new-select=true -addr-sink-new-phis=true < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=thumbv7m -disable-complex-addr-modes=false -addr-sink-new-select=true -addr-sink-new-phis=true < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/splitgep.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/splitgep.ll index cd2087d94149..69c8b92a3558 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/splitgep.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/splitgep.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv6m-arm-none-eabi" diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/tailcall-dup.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/tailcall-dup.ll index 76b119fe36aa..3f113e6ea163 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/tailcall-dup.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/tailcall-dup.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s target triple = "armv8m.main-none-eabi" diff --git a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-constant-numerator.ll b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-constant-numerator.ll index 94adf1970938..b8a45e847afc 100644 --- a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-constant-numerator.ll +++ b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-constant-numerator.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-nvidia-cuda" diff --git a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-not-exact.ll b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-not-exact.ll index c571da4411e7..d46aaf51a59c 100644 --- a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-not-exact.ll +++ b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-not-exact.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-nvidia-cuda" diff --git a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-special-cases.ll b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-special-cases.ll index 21e47c614ad0..9ec533c2e653 100644 --- a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-special-cases.ll +++ b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-special-cases.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-nvidia-cuda" diff --git a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div.ll b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div.ll index 424f7c3b0271..463fa0d487a7 100644 --- a/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div.ll +++ b/llvm/test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-nvidia-cuda" diff --git a/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-introduce-addrspacecast.ll b/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-introduce-addrspacecast.ll index 17b0dbf81ac2..af9b5ccd7287 100644 --- a/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-introduce-addrspacecast.ll +++ b/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-introduce-addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-nvidia-cuda" diff --git a/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-sink-nop-addrspacecast.ll b/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-sink-nop-addrspacecast.ll index 374f30dba508..7ee7f0550318 100644 --- a/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-sink-nop-addrspacecast.ll +++ b/llvm/test/Transforms/CodeGenPrepare/NVPTX/dont-sink-nop-addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-nvidia-cuda" diff --git a/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll index 79aebb9c247a..65177d5ae3d7 100644 --- a/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll +++ b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare -mtriple=powerpc64-unknown-linux-gnu -data-layout="E-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefix=BE %s -; RUN: opt -S -codegenprepare -mtriple=powerpc64le-unknown-linux-gnu -data-layout="e-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefix=LE %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=powerpc64-unknown-linux-gnu -data-layout="E-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefix=BE %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=powerpc64le-unknown-linux-gnu -data-layout="e-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefix=LE %s define void @split_store_align1(float %x, ptr %p) { ; BE-LABEL: @split_store_align1( diff --git a/llvm/test/Transforms/CodeGenPrepare/RISCV/and-mask-sink.ll b/llvm/test/Transforms/CodeGenPrepare/RISCV/and-mask-sink.ll index 130401d78171..863b0b4ad26f 100644 --- a/llvm/test/Transforms/CodeGenPrepare/RISCV/and-mask-sink.ll +++ b/llvm/test/Transforms/CodeGenPrepare/RISCV/and-mask-sink.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare -mtriple=riscv32 %s \ +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=riscv32 %s \ ; RUN: | FileCheck --check-prefixes=CHECK,NOZBS %s -; RUN: opt -S -codegenprepare -mtriple=riscv32 -mattr=+zbs %s \ +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=riscv32 -mattr=+zbs %s \ ; RUN: | FileCheck --check-prefixes=CHECK,ZBS %s -; RUN: opt -S -codegenprepare -mtriple=riscv64 %s \ +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=riscv64 %s \ ; RUN: | FileCheck --check-prefixes=CHECK,NOZBS %s -; RUN: opt -S -codegenprepare -mtriple=riscv64 -mattr=zbs %s \ +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=riscv64 -mattr=zbs %s \ ; RUN: | FileCheck --check-prefixes=CHECK,ZBS %s @A = global i32 zeroinitializer diff --git a/llvm/test/Transforms/CodeGenPrepare/RISCV/cttz-ctlz.ll b/llvm/test/Transforms/CodeGenPrepare/RISCV/cttz-ctlz.ll index c70112e91ebd..00ad32e96748 100644 --- a/llvm/test/Transforms/CodeGenPrepare/RISCV/cttz-ctlz.ll +++ b/llvm/test/Transforms/CodeGenPrepare/RISCV/cttz-ctlz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target triple = "riscv64-unknown-unknown" diff --git a/llvm/test/Transforms/CodeGenPrepare/SPARC/overflow-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/SPARC/overflow-intrinsics.ll index 7525ae14fa35..ec60238cbf92 100644 --- a/llvm/test/Transforms/CodeGenPrepare/SPARC/overflow-intrinsics.ll +++ b/llvm/test/Transforms/CodeGenPrepare/SPARC/overflow-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S < %s | FileCheck %s -; RUN: opt -enable-debugify -codegenprepare -S < %s 2>&1 | FileCheck %s -check-prefix=DEBUG +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s +; RUN: opt -enable-debugify -passes='require,function(codegenprepare)' -S < %s 2>&1 | FileCheck %s -check-prefix=DEBUG ; Subset of tests from llvm/tests/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll ; to test shouldFormOverflowOp on SPARC, where it is not profitable to create @@ -119,5 +119,5 @@ define i1 @usubo_ult_i64_math_overflow_used(i64 %x, i64 %y, ptr %p) { ret i1 %ov } -; Check that every instruction inserted by -codegenprepare has a debug location. +; Check that every instruction inserted by -passes='require,function(codegenprepare)' has a debug location. ; DEBUG: CheckModuleDebugify: PASS diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/catchpad-phi-cast.ll b/llvm/test/Transforms/CodeGenPrepare/X86/catchpad-phi-cast.ll index 614e80e3e89c..cb617671827e 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/catchpad-phi-cast.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/catchpad-phi-cast.ll @@ -1,5 +1,5 @@ -; RUN: opt -codegenprepare -S < %s | FileCheck %s -; RUN: opt -codegenprepare -S < %s --try-experimental-debuginfo-iterators | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S < %s --try-experimental-debuginfo-iterators | FileCheck %s ; The following target lines are needed for the test to exercise what it should. ; Without these lines, CodeGenPrepare does not try to sink the bitcasts. diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash-inseltpoison.ll index 9eede8cf361b..bcb7edd6e91b 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash-inseltpoison.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash-inseltpoison.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S %s | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash.ll b/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash.ll index 7433ff74bab5..9ce830c39477 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S %s | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/computedgoto.ll b/llvm/test/Transforms/CodeGenPrepare/X86/computedgoto.ll index fbf294128163..c1b919d31e07 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/computedgoto.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/computedgoto.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/cttz-ctlz.ll b/llvm/test/Transforms/CodeGenPrepare/X86/cttz-ctlz.ll index 5f368faf46ee..3a3a5327da8d 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/cttz-ctlz.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/cttz-ctlz.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s --check-prefix=SLOW -; RUN: opt -S -codegenprepare -mattr=+bmi < %s | FileCheck %s --check-prefix=FAST_TZ -; RUN: opt -S -codegenprepare -mattr=+lzcnt < %s | FileCheck %s --check-prefix=FAST_LZ +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s --check-prefix=SLOW +; RUN: opt -S -passes='require,function(codegenprepare)' -mattr=+bmi < %s | FileCheck %s --check-prefix=FAST_TZ +; RUN: opt -S -passes='require,function(codegenprepare)' -mattr=+lzcnt < %s | FileCheck %s --check-prefix=FAST_LZ -; RUN: opt -S -debugify -codegenprepare < %s | FileCheck %s --check-prefix=DEBUGINFO -; RUN: opt -S -debugify -codegenprepare --try-experimental-debuginfo-iterators < %s | FileCheck %s --check-prefix=DEBUGINFO +; RUN: opt -S -enable-debugify -passes='require,function(codegenprepare)' < %s | FileCheck %s --check-prefix=DEBUGINFO +; RUN: opt -S -enable-debugify -passes='require,function(codegenprepare)' --try-experimental-debuginfo-iterators < %s | FileCheck %s --check-prefix=DEBUGINFO target triple = "x86_64-unknown-unknown" target datalayout = "e-n32:64" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/delete-assume-dead-code.ll b/llvm/test/Transforms/CodeGenPrepare/X86/delete-assume-dead-code.ll index abdf54c6e542..e1d99fd932fb 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/delete-assume-dead-code.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/delete-assume-dead-code.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S -mtriple=x86_64-linux < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64-linux < %s | FileCheck %s define i32 @test1(ptr %d) nounwind { ; CHECK-LABEL: @test1( diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll b/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll index a0814e0a5f20..5349afc18d84 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -disable-cgp-branch-opts -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -disable-cgp-branch-opts -S < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll b/llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll index c37227f5fa82..e9ecfd1615d4 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll index 41b1ac2c05fc..e62ba5d5a7f5 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s -; RUN: opt -S -codegenprepare -cgpp-huge-func=0 < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -cgpp-huge-func=0 < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll index 2cf98491acb9..7899477afdb2 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/gep-unmerging.ll b/llvm/test/Transforms/CodeGenPrepare/X86/gep-unmerging.ll index d2eae6954c5d..a2ea3f7e36a0 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/gep-unmerging.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/gep-unmerging.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S -mtriple=x86_64 < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64 < %s | FileCheck %s @exit_addr = constant ptr blockaddress(@gep_unmerging, %exit) @op1_addr = constant ptr blockaddress(@gep_unmerging, %op1) diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/invariant.group.ll b/llvm/test/Transforms/CodeGenPrepare/X86/invariant.group.ll index 3c81a4beb834..a0bac01d1165 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/invariant.group.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/invariant.group.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S -mtriple=x86_64 < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64 < %s | FileCheck %s @tmp = global i8 0 diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/masked-gather-struct-gep.ll b/llvm/test/Transforms/CodeGenPrepare/X86/masked-gather-struct-gep.ll index ea07a5fe9bc5..dbd5e87f2c28 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/masked-gather-struct-gep.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/masked-gather-struct-gep.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s ; REQUIRES: x86-registered-target target triple = "x86_64-pc-linux" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll b/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll index 2f42ad889b42..9d53855ada79 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s -; RUN: opt -S -codegenprepare -addr-sink-using-gep=false < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -addr-sink-using-gep=false < %s | FileCheck %s ; This target data layout is modified to have a non-integral addrspace(1), ; in order to verify that codegenprepare does not try to introduce illegal diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/optimizeSelect-DT.ll b/llvm/test/Transforms/CodeGenPrepare/X86/optimizeSelect-DT.ll index be651d7eb004..aaf3df093468 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/optimizeSelect-DT.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/optimizeSelect-DT.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll index a324f6f44e5c..653f34635648 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S < %s | FileCheck %s -; RUN: opt -enable-debugify -codegenprepare -S < %s 2>&1 | FileCheck %s -check-prefix=DEBUG +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s +; RUN: opt -enable-debugify -passes='require,function(codegenprepare)' -S < %s 2>&1 | FileCheck %s -check-prefix=DEBUG target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" @@ -636,6 +636,6 @@ exit: ret void } -; Check that every instruction inserted by -codegenprepare has a debug location. +; Check that every instruction inserted by -passes='require,function(codegenprepare)' has a debug location. ; DEBUG: CheckModuleDebugify: PASS diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/pr27536.ll b/llvm/test/Transforms/CodeGenPrepare/X86/pr27536.ll index 3ef27c7c950f..51fba2229f3c 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/pr27536.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/pr27536.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll b/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll index eec9475a1c48..e9d0806235c9 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -disable-complex-addr-modes=false -addr-sink-new-phis=true -addr-sink-new-select=true %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-phis=true -addr-sink-new-select=true %s | FileCheck %s target triple = "x86_64-unknown-linux-gnu" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/pr72046.ll b/llvm/test/Transforms/CodeGenPrepare/X86/pr72046.ll index d75e5632ebb2..b6296871f575 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/pr72046.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/pr72046.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -S -codegenprepare -mtriple=x86_64-unknown-unknown < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=x86_64-unknown-unknown < %s | FileCheck %s ; Make sure the nneg flag is dropped when lshr and zext are interchanged. define i8 @get(ptr %box, i32 %in) { diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/recursively-delete-dead-instructions.ll b/llvm/test/Transforms/CodeGenPrepare/X86/recursively-delete-dead-instructions.ll index 0366b7d7e6d2..eff88bba3773 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/recursively-delete-dead-instructions.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/recursively-delete-dead-instructions.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S -mtriple=x86_64-linux < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64-linux < %s | FileCheck %s declare void @llvm.assume(i1 noundef) nounwind willreturn diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/remove-assume-block.ll b/llvm/test/Transforms/CodeGenPrepare/X86/remove-assume-block.ll index 1d5e6ea0978a..6b7a122b3e26 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/remove-assume-block.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/remove-assume-block.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -mtriple=x86_64-linux < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=x86_64-linux < %s | FileCheck %s ; ; Ensure that blocks that only contain @llvm.assume are removed completely ; during CodeGenPrepare. diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/select.ll b/llvm/test/Transforms/CodeGenPrepare/X86/select.ll index a0f34a882d30..08dd77e9e4c3 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/select.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/select.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S < %s | FileCheck %s -; RUN: opt -debugify -codegenprepare -S < %s | FileCheck %s -check-prefix=DEBUG -; RUN: opt -debugify -codegenprepare -S < %s --try-experimental-debuginfo-iterators | FileCheck %s -check-prefix=DEBUG +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s +; RUN: opt -enable-debugify -passes='require,function(codegenprepare)' -S < %s | FileCheck %s -check-prefix=DEBUG +; RUN: opt -enable-debugify -passes='require,function(codegenprepare)' -S < %s --try-experimental-debuginfo-iterators | FileCheck %s -check-prefix=DEBUG target triple = "x86_64-unknown-unknown" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll index 45ddbe76c8f1..08e822f7e211 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -codegenprepare -disable-complex-addr-modes=false -addr-sink-new-phis=true -addr-sink-new-select=true -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-YES -; RUN: opt -S -codegenprepare -disable-complex-addr-modes=false -addr-sink-new-phis=false -addr-sink-new-select=true -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NO +; RUN: opt -S -passes='require,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-phis=true -addr-sink-new-select=true -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-YES +; RUN: opt -S -passes='require,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-phis=false -addr-sink-new-select=true -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NO target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll index d5e69b9d802e..7660ee47fdbd 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll index 336421e4c500..076915028aef 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -disable-complex-addr-modes=false -addr-sink-new-select=true %s | FileCheck %s --check-prefix=CHECK +; RUN: opt -S -passes='require,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-select=true %s | FileCheck %s --check-prefix=CHECK target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll index 611ef908d706..6a6b029b67b5 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare -disable-complex-addr-modes=false -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK +; RUN: opt -S -passes='require,function(codegenprepare)' -disable-complex-addr-modes=false -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll index 97b11a2e1f1c..f75af606eff0 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll index f2e82212d0fa..a760f56b151f 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s -check-prefix=CHECK -check-prefix=GEP +; RUN: opt -S -passes='require,function(codegenprepare)' < %s | FileCheck %s -check-prefix=CHECK -check-prefix=GEP target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/split-indirect-loop.ll b/llvm/test/Transforms/CodeGenPrepare/X86/split-indirect-loop.ll index c5d18ff50309..7f7f80910b48 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/split-indirect-loop.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/split-indirect-loop.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S -mtriple=x86_64 < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64 < %s | FileCheck %s ; Test that an invalid CFG is not created by splitIndirectCriticalEdges ; transformation when the 'target' block is a loop to itself. diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll index 3bced480f31a..0335da94ea50 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -mtriple=x86_64-unknown-unknown -force-split-store -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-unknown-unknown -force-split-store -S < %s | FileCheck %s target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-w64-windows-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/statepoint-relocate.ll b/llvm/test/Transforms/CodeGenPrepare/X86/statepoint-relocate.ll index a8a6f7baf9b4..babaa08a959b 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/statepoint-relocate.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/statepoint-relocate.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S < %s | FileCheck %s target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-linux-gnu" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/tailcall-assume-xbb.ll b/llvm/test/Transforms/CodeGenPrepare/X86/tailcall-assume-xbb.ll index 9dc88a100daa..dd47d5eb6cc4 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/tailcall-assume-xbb.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/tailcall-assume-xbb.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -S -mtriple=x86_64-linux < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64-linux < %s | FileCheck %s ; The ret instruction can be duplicated into BB case2 even though there is an ; intermediate BB exit1 and call to llvm.assume. diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll index 557974fcfe54..db7d960899ca 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx -S < %s | FileCheck %s --check-prefixes=AVX1 -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx2 -S < %s | FileCheck %s --check-prefixes=AVX2 -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx512bw -S < %s | FileCheck %s --check-prefixes=AVX512BW -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx,+xop -S < %s | FileCheck %s --check-prefixes=XOP -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx2,+xop -S < %s | FileCheck %s --check-prefixes=XOP -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx -S -enable-debugify < %s 2>&1 | FileCheck %s -check-prefix=DEBUG +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx -S < %s | FileCheck %s --check-prefixes=AVX1 +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx2 -S < %s | FileCheck %s --check-prefixes=AVX2 +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx512bw -S < %s | FileCheck %s --check-prefixes=AVX512BW +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx,+xop -S < %s | FileCheck %s --check-prefixes=XOP +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx2,+xop -S < %s | FileCheck %s --check-prefixes=XOP +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx -S -enable-debugify < %s 2>&1 | FileCheck %s -check-prefix=DEBUG define <4 x i32> @vector_variable_shift_right_v4i32(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { ; AVX1-LABEL: @vector_variable_shift_right_v4i32( @@ -409,5 +409,5 @@ exit: declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>) #1 -; Check that every instruction inserted by -codegenprepare has a debug location. +; Check that every instruction inserted by -passes='require,function(codegenprepare)' has a debug location. ; DEBUG: CheckModuleDebugify: PASS diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift.ll b/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift.ll index 482e822ea3d8..e0f04f77efa0 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx -S < %s | FileCheck %s --check-prefixes=AVX1 -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx2 -S < %s | FileCheck %s --check-prefixes=AVX2 -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx512bw -S < %s | FileCheck %s --check-prefixes=AVX512BW -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx,+xop -S < %s | FileCheck %s --check-prefixes=XOP -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx2,+xop -S < %s | FileCheck %s --check-prefixes=XOP -; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx -S -enable-debugify < %s 2>&1 | FileCheck %s -check-prefix=DEBUG +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx -S < %s | FileCheck %s --check-prefixes=AVX1 +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx2 -S < %s | FileCheck %s --check-prefixes=AVX2 +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx512bw -S < %s | FileCheck %s --check-prefixes=AVX512BW +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx,+xop -S < %s | FileCheck %s --check-prefixes=XOP +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx2,+xop -S < %s | FileCheck %s --check-prefixes=XOP +; RUN: opt -passes='require,function(codegenprepare)' -mtriple=x86_64-- -mattr=+avx -S -enable-debugify < %s 2>&1 | FileCheck %s -check-prefix=DEBUG define <4 x i32> @vector_variable_shift_right_v4i32(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { ; AVX1-LABEL: @vector_variable_shift_right_v4i32( @@ -409,5 +409,5 @@ exit: declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>) #1 -; Check that every instruction inserted by -codegenprepare has a debug location. +; Check that every instruction inserted by -passes='require,function(codegenprepare)' has a debug location. ; DEBUG: CheckModuleDebugify: PASS diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/widenable-condition.ll b/llvm/test/Transforms/CodeGenPrepare/X86/widenable-condition.ll index b26876e0e1e2..12230ec689cf 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/widenable-condition.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/widenable-condition.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -codegenprepare -S -mtriple=x86_64 < %s | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -S -mtriple=x86_64 < %s | FileCheck %s ; Check the idiomatic guard pattern to ensure it's lowered correctly. define void @test_guard(i1 %cond_0) { diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll index 72d1672eb4f7..ce1b6bd5ae63 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare -mcpu=corei7 %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2 -; RUN: opt -S -codegenprepare -mcpu=bdver2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP -; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2 -; RUN: opt -S -codegenprepare -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=corei7 %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2 +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=bdver2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2 +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-darwin10.9.0" diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll index c14918a6956f..9e82844dfc2f 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -codegenprepare -mcpu=corei7 %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2 -; RUN: opt -S -codegenprepare -mcpu=bdver2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP -; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2 -; RUN: opt -S -codegenprepare -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=corei7 %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2 +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=bdver2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2 +; RUN: opt -S -passes='require,function(codegenprepare)' -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-darwin10.9.0" diff --git a/llvm/test/Transforms/CodeGenPrepare/dead-allocation.ll b/llvm/test/Transforms/CodeGenPrepare/dead-allocation.ll index 637040a0d56d..9550e748da6d 100644 --- a/llvm/test/Transforms/CodeGenPrepare/dead-allocation.ll +++ b/llvm/test/Transforms/CodeGenPrepare/dead-allocation.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; Eliminate the dead allocation instruction ; REQUIRES: arm-registered-target -; RUN: opt -codegenprepare < %s -S | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' < %s -S | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv7--linux-gnueabihf" diff --git a/llvm/test/Transforms/CodeGenPrepare/skip-merging-case-block.ll b/llvm/test/Transforms/CodeGenPrepare/skip-merging-case-block.ll index 608ad4c0a32f..d25b9c91aff6 100644 --- a/llvm/test/Transforms/CodeGenPrepare/skip-merging-case-block.ll +++ b/llvm/test/Transforms/CodeGenPrepare/skip-merging-case-block.ll @@ -1,5 +1,5 @@ ; REQUIRES: aarch64-registered-target -; RUN: opt -codegenprepare < %s -mtriple=aarch64-none-linux-gnu -S | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' < %s -mtriple=aarch64-none-linux-gnu -S | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-gnu" diff --git a/llvm/test/Transforms/HotColdSplit/coldentrycount.ll b/llvm/test/Transforms/HotColdSplit/coldentrycount.ll index 1a113ff16188..6e5ef1aa2539 100644 --- a/llvm/test/Transforms/HotColdSplit/coldentrycount.ll +++ b/llvm/test/Transforms/HotColdSplit/coldentrycount.ll @@ -1,5 +1,5 @@ ; REQUIRES: x86-registered-target -; RUN: opt -passes=hotcoldsplit -hotcoldsplit-threshold=0 < %s | opt -codegenprepare -S | FileCheck %s +; RUN: opt -passes=hotcoldsplit -hotcoldsplit-threshold=0 < %s | opt -passes='require,function(codegenprepare)' -S | FileCheck %s ; Test to ensure that split cold function gets 0 entry count profile ; metadata when compiling with pgo. diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/codegenprepare-produced-address-math.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/codegenprepare-produced-address-math.ll index ff8a804beeb5..a56efe8dd3f3 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/X86/codegenprepare-produced-address-math.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/codegenprepare-produced-address-math.ll @@ -1,4 +1,4 @@ -; RUN: opt -codegenprepare -load-store-vectorizer %s -S -o - | FileCheck %s +; RUN: opt -passes='require,function(codegenprepare)' -passes=load-store-vectorizer %s -S -o - | FileCheck %s ; RUN: opt -passes=load-store-vectorizer %s -S -o - | FileCheck %s ; RUN: opt -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' %s -S -o - | FileCheck %s diff --git a/llvm/test/Transforms/SampleProfile/section-accurate-samplepgo.ll b/llvm/test/Transforms/SampleProfile/section-accurate-samplepgo.ll index a404220056c8..ef2ddbc33cee 100644 --- a/llvm/test/Transforms/SampleProfile/section-accurate-samplepgo.ll +++ b/llvm/test/Transforms/SampleProfile/section-accurate-samplepgo.ll @@ -1,7 +1,7 @@ ; REQUIRES: x86-registered-target -; RUN: opt -S %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline.prof | opt -S -codegenprepare | FileCheck %s -; RUN: opt -S %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline.prof | opt -S -codegenprepare -profile-unknown-in-special-section -partial-profile | FileCheck %s --check-prefix=UNKNOWN -; RUN: opt -S %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline.prof -profile-sample-accurate -S | opt -S -codegenprepare | FileCheck %s --check-prefix=ACCURATE +; RUN: opt -S %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline.prof | opt -S -passes='require,function(codegenprepare)' | FileCheck %s +; RUN: opt -S %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline.prof | opt -S -passes='require,function(codegenprepare)' -profile-unknown-in-special-section -partial-profile | FileCheck %s --check-prefix=UNKNOWN +; RUN: opt -S %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline.prof -profile-sample-accurate -S | opt -S -passes='require,function(codegenprepare)' | FileCheck %s --check-prefix=ACCURATE target triple = "x86_64-pc-linux-gnu" diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp index b6068513d230..c649e6ecddc0 100644 --- a/llvm/tools/opt/opt.cpp +++ b/llvm/tools/opt/opt.cpp @@ -426,7 +426,7 @@ int main(int argc, char **argv) { initializeScalarizeMaskedMemIntrinLegacyPassPass(Registry); initializeSelectOptimizePass(Registry); initializeCallBrPreparePass(Registry); - initializeCodeGenPreparePass(Registry); + initializeCodeGenPrepareLegacyPassPass(Registry); initializeAtomicExpandPass(Registry); initializeWinEHPreparePass(Registry); initializeDwarfEHPrepareLegacyPassPass(Registry); -- GitLab From cf6e9c4b2711fa4450c537aa381a1d693e130740 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Mon, 8 Jan 2024 22:33:08 -0800 Subject: [PATCH 155/652] [RISCV] Add documentation in the LangRef on GHC CC (#72762) The GHC CC got added to RISCV in a8dc2110cd4dd69212a204bc1074729f95d5402a but it never got documented in the LangRef. This adds documentation in the LangRef noting that RISCV is supports the GHC calling convention and notes the specific limitations of the GHC CC on RISCV. --- llvm/docs/LangRef.rst | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 15abeb1c984c..c90b6becae52 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -317,8 +317,8 @@ added in the future: not be used lightly but only for specific situations such as an alternative to the *register pinning* performance technique often used when implementing functional programming languages. At the - moment only X86 and AArch64 support this convention. The following - limitations exist: + moment only X86, AArch64, and RISCV support this convention. The + following limitations exist: - On *X86-32* only up to 4 bit type parameters are supported. No floating-point types are supported. @@ -327,6 +327,9 @@ added in the future: - On *AArch64* only up to 4 32-bit floating-point parameters, 4 64-bit floating-point parameters, and 10 bit type parameters are supported. + - *RISCV64* only supports up to 11 bit type parameters, 4 + 32-bit floating-point parameters, and 4 64-bit floating-point + parameters. This calling convention supports `tail call optimization `_ but requires -- GitLab From 4a5ebc7f6538dbebe9d671346de6138de657cb7d Mon Sep 17 00:00:00 2001 From: Lu Weining Date: Tue, 9 Jan 2024 14:58:09 +0800 Subject: [PATCH 156/652] [BinaryFormat][LoongArch] Define psABI v2.30 relocs (#77039) --- .../llvm/BinaryFormat/ELFRelocs/LoongArch.def | 23 ++++++++++++ .../ELF/reloc-types-loongarch64.test | 36 +++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def index df3a342151fb..4859057abcbb 100644 --- a/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def +++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def @@ -126,3 +126,26 @@ ELF_RELOC(R_LARCH_64_PCREL, 109) // // Spec addition: https://github.com/loongson/la-abi-specs/pull/4 ELF_RELOC(R_LARCH_CALL36, 110) + +// Relocs added in ELF for the LoongArch™ Architecture v20231219, part of the +// v2.30 LoongArch ABI specs. +// +// Spec addition: https://github.com/loongson/la-abi-specs/pull/5 +ELF_RELOC(R_LARCH_TLS_DESC32, 13) +ELF_RELOC(R_LARCH_TLS_DESC64, 14) +ELF_RELOC(R_LARCH_TLS_DESC_PC_HI20, 111) +ELF_RELOC(R_LARCH_TLS_DESC_PC_LO12, 112) +ELF_RELOC(R_LARCH_TLS_DESC64_PC_LO20, 113) +ELF_RELOC(R_LARCH_TLS_DESC64_PC_HI12, 114) +ELF_RELOC(R_LARCH_TLS_DESC_HI20, 115) +ELF_RELOC(R_LARCH_TLS_DESC_LO12, 116) +ELF_RELOC(R_LARCH_TLS_DESC64_LO20, 117) +ELF_RELOC(R_LARCH_TLS_DESC64_HI12, 118) +ELF_RELOC(R_LARCH_TLS_DESC_LD, 119) +ELF_RELOC(R_LARCH_TLS_DESC_CALL, 120) +ELF_RELOC(R_LARCH_TLS_LE_HI20_R, 121) +ELF_RELOC(R_LARCH_TLS_LE_ADD_R, 122) +ELF_RELOC(R_LARCH_TLS_LE_LO12_R, 123) +ELF_RELOC(R_LARCH_TLS_LD_PCREL20_S2, 124) +ELF_RELOC(R_LARCH_TLS_GD_PCREL20_S2, 125) +ELF_RELOC(R_LARCH_TLS_DESC_PCREL20_S2, 126) diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test index 55a3e645b883..26c4e8f5ca84 100644 --- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test +++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test @@ -17,6 +17,8 @@ # CHECK: Type: R_LARCH_TLS_TPREL32 (10) # CHECK: Type: R_LARCH_TLS_TPREL64 (11) # CHECK: Type: R_LARCH_IRELATIVE (12) +# CHECK: Type: R_LARCH_TLS_DESC32 (13) +# CHECK: Type: R_LARCH_TLS_DESC64 (14) # CHECK: Type: R_LARCH_MARK_LA (20) # CHECK: Type: R_LARCH_MARK_PCREL (21) # CHECK: Type: R_LARCH_SOP_PUSH_PCREL (22) @@ -101,6 +103,22 @@ # CHECK: Type: R_LARCH_SUB_ULEB128 (108) # CHECK: Type: R_LARCH_64_PCREL (109) # CHECK: Type: R_LARCH_CALL36 (110) +# CHECK: Type: R_LARCH_TLS_DESC_PC_HI20 (111) +# CHECK: Type: R_LARCH_TLS_DESC_PC_LO12 (112) +# CHECK: Type: R_LARCH_TLS_DESC64_PC_LO20 (113) +# CHECK: Type: R_LARCH_TLS_DESC64_PC_HI12 (114) +# CHECK: Type: R_LARCH_TLS_DESC_HI20 (115) +# CHECK: Type: R_LARCH_TLS_DESC_LO12 (116) +# CHECK: Type: R_LARCH_TLS_DESC64_LO20 (117) +# CHECK: Type: R_LARCH_TLS_DESC64_HI12 (118) +# CHECK: Type: R_LARCH_TLS_DESC_LD (119) +# CHECK: Type: R_LARCH_TLS_DESC_CALL (120) +# CHECK: Type: R_LARCH_TLS_LE_HI20_R (121) +# CHECK: Type: R_LARCH_TLS_LE_ADD_R (122) +# CHECK: Type: R_LARCH_TLS_LE_LO12_R (123) +# CHECK: Type: R_LARCH_TLS_LD_PCREL20_S2 (124) +# CHECK: Type: R_LARCH_TLS_GD_PCREL20_S2 (125) +# CHECK: Type: R_LARCH_TLS_DESC_PCREL20_S2 (126) --- !ELF FileHeader: @@ -125,6 +143,8 @@ Sections: - Type: R_LARCH_TLS_TPREL32 - Type: R_LARCH_TLS_TPREL64 - Type: R_LARCH_IRELATIVE + - Type: R_LARCH_TLS_DESC32 + - Type: R_LARCH_TLS_DESC64 - Type: R_LARCH_MARK_LA - Type: R_LARCH_MARK_PCREL - Type: R_LARCH_SOP_PUSH_PCREL @@ -209,3 +229,19 @@ Sections: - Type: R_LARCH_SUB_ULEB128 - Type: R_LARCH_64_PCREL - Type: R_LARCH_CALL36 + - Type: R_LARCH_TLS_DESC_PC_HI20 + - Type: R_LARCH_TLS_DESC_PC_LO12 + - Type: R_LARCH_TLS_DESC64_PC_LO20 + - Type: R_LARCH_TLS_DESC64_PC_HI12 + - Type: R_LARCH_TLS_DESC_HI20 + - Type: R_LARCH_TLS_DESC_LO12 + - Type: R_LARCH_TLS_DESC64_LO20 + - Type: R_LARCH_TLS_DESC64_HI12 + - Type: R_LARCH_TLS_DESC_LD + - Type: R_LARCH_TLS_DESC_CALL + - Type: R_LARCH_TLS_LE_HI20_R + - Type: R_LARCH_TLS_LE_ADD_R + - Type: R_LARCH_TLS_LE_LO12_R + - Type: R_LARCH_TLS_LD_PCREL20_S2 + - Type: R_LARCH_TLS_GD_PCREL20_S2 + - Type: R_LARCH_TLS_DESC_PCREL20_S2 -- GitLab From dad614cc606333fa614e696dbdd22263096dadb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Hana=20Dus=C3=ADkov=C3=A1?= Date: Tue, 9 Jan 2024 08:00:20 +0100 Subject: [PATCH 157/652] [Documentation] fix invalid links in documentation (#76502) --- llvm/docs/SphinxQuickstartTemplate.rst | 2 +- llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/docs/SphinxQuickstartTemplate.rst b/llvm/docs/SphinxQuickstartTemplate.rst index 956adabce78c..8d21b43c050d 100644 --- a/llvm/docs/SphinxQuickstartTemplate.rst +++ b/llvm/docs/SphinxQuickstartTemplate.rst @@ -170,7 +170,7 @@ Generating the documentation You can generate the HTML documentation from the sources locally if you want to see what they would look like. In addition to the normal -`build tools `_ +`build tools `_ you need to install `Sphinx`_ and the necessary extensions using the following command inside the ``llvm-project`` checkout: diff --git a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst index 17bf8a47c84c..2e3d4ed0a308 100644 --- a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst +++ b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst @@ -122,7 +122,7 @@ Configuring the Module We're now ready to configure our module, to specify the target and data layout. This isn't strictly necessary, but the `frontend -performance guide <../Frontend/PerformanceTips.html>`_ recommends +performance guide <../../Frontend/PerformanceTips.html>`_ recommends this. Optimizations benefit from knowing about the target and data layout. -- GitLab From b57159cb19cdc06ec5733f93f0975aa6f40595cb Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Tue, 9 Jan 2024 15:14:54 +0800 Subject: [PATCH 158/652] [LoongArch] Support R_LARCH_{ADD,SUB}_ULEB128 for .uleb128 and force relocs when sym is not in section (#76433) 1, Follow RISCV 1df5ea29 to support generates relocs for .uleb128 which can not be folded. Unlike RISCV, the located content of LoongArch should be zero. LoongArch fixup uleb128 value by in-place addition and subtraction reloc types named R_LARCH_{ADD,SUB}_ULEB128. The located content can affect the result and R_LARCH_ADD_ULEB128 has enough info to represent the first symbol value, so it needs to be set to zero. 2, Force relocs if sym is not in section so that it can emit relocs for external symbol. Fixes: https://github.com/llvm/llvm-project/pull/72960#issuecomment-1866844679 --- llvm/include/llvm/MC/MCAsmBackend.h | 6 +- llvm/lib/MC/MCAssembler.cpp | 6 +- .../MCTargetDesc/LoongArchAsmBackend.cpp | 69 ++++++++++++++---- .../MCTargetDesc/LoongArchAsmBackend.h | 3 + .../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 9 +-- .../RISCV/MCTargetDesc/RISCVAsmBackend.h | 4 +- llvm/test/MC/LoongArch/Relocations/leb128.s | 72 +++++++++++++++++++ .../MC/LoongArch/Relocations/relax-addsub.s | 57 +++++++++++---- 8 files changed, 187 insertions(+), 39 deletions(-) create mode 100644 llvm/test/MC/LoongArch/Relocations/leb128.s diff --git a/llvm/include/llvm/MC/MCAsmBackend.h b/llvm/include/llvm/MC/MCAsmBackend.h index 8931e8cab2fa..01a64fb425a9 100644 --- a/llvm/include/llvm/MC/MCAsmBackend.h +++ b/llvm/include/llvm/MC/MCAsmBackend.h @@ -198,9 +198,9 @@ public: // Defined by linker relaxation targets to possibly emit LEB128 relocations // and set Value at the relocated location. - virtual bool relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, - int64_t &Value) const { - return false; + virtual std::pair + relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, int64_t &Value) const { + return std::make_pair(false, false); } /// @} diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp index def13044dfcc..ad30b5ce9e63 100644 --- a/llvm/lib/MC/MCAssembler.cpp +++ b/llvm/lib/MC/MCAssembler.cpp @@ -1026,7 +1026,9 @@ bool MCAssembler::relaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) { ? LF.getValue().evaluateKnownAbsolute(Value, Layout) : LF.getValue().evaluateAsAbsolute(Value, Layout); if (!Abs) { - if (!getBackend().relaxLEB128(LF, Layout, Value)) { + bool Relaxed, UseZeroPad; + std::tie(Relaxed, UseZeroPad) = getBackend().relaxLEB128(LF, Layout, Value); + if (!Relaxed) { getContext().reportError(LF.getValue().getLoc(), Twine(LF.isSigned() ? ".s" : ".u") + "leb128 expression is not absolute"); @@ -1034,6 +1036,8 @@ bool MCAssembler::relaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) { } uint8_t Tmp[10]; // maximum size: ceil(64/7) PadTo = std::max(PadTo, encodeULEB128(uint64_t(Value), Tmp)); + if (UseZeroPad) + Value = 0; } Data.clear(); raw_svector_ostream OSE(Data); diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp index 6d8ef1bf96cb..518f6b10edab 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp @@ -91,6 +91,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case FK_Data_2: case FK_Data_4: case FK_Data_8: + case FK_Data_leb128: return Value; case LoongArch::fixup_loongarch_b16: { if (!isInt<18>(Value)) @@ -128,6 +129,15 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, } } +static void fixupLeb128(MCContext &Ctx, const MCFixup &Fixup, + MutableArrayRef Data, uint64_t Value) { + unsigned I; + for (I = 0; I != Data.size() && Value; ++I, Value >>= 7) + Data[I] |= uint8_t(Value & 0x7f); + if (Value) + Ctx.reportError(Fixup.getLoc(), "Invalid uleb128 value!"); +} + void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, @@ -143,6 +153,10 @@ void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm, MCFixupKindInfo Info = getFixupKindInfo(Kind); MCContext &Ctx = Asm.getContext(); + // Fixup leb128 separately. + if (Fixup.getTargetKind() == FK_Data_leb128) + return fixupLeb128(Ctx, Fixup, Data, Value); + // Apply any target-specific value adjustments. Value = adjustFixupValue(Fixup, Value, Ctx); @@ -173,6 +187,7 @@ bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm, case FK_Data_2: case FK_Data_4: case FK_Data_8: + case FK_Data_leb128: return !Target.isAbsolute(); } } @@ -202,9 +217,24 @@ getRelocPairForSize(unsigned Size) { return std::make_pair( MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD64), MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB64)); + case 128: + return std::make_pair( + MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD_ULEB128), + MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB_ULEB128)); } } +std::pair LoongArchAsmBackend::relaxLEB128(MCLEBFragment &LF, + MCAsmLayout &Layout, + int64_t &Value) const { + const MCExpr &Expr = LF.getValue(); + if (LF.isSigned() || !Expr.evaluateKnownAbsolute(Value, Layout)) + return std::make_pair(false, false); + LF.getFixups().push_back( + MCFixup::create(0, &Expr, FK_Data_leb128, Expr.getLoc())); + return std::make_pair(true, true); +} + bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const { // We mostly follow binutils' convention here: align to 4-byte boundary with a @@ -226,21 +256,27 @@ bool LoongArchAsmBackend::handleAddSubRelocations(const MCAsmLayout &Layout, uint64_t &FixedValue) const { std::pair FK; uint64_t FixedValueA, FixedValueB; - const MCSection &SecA = Target.getSymA()->getSymbol().getSection(); - const MCSection &SecB = Target.getSymB()->getSymbol().getSection(); - - // We need record relocation if SecA != SecB. Usually SecB is same as the - // section of Fixup, which will be record the relocation as PCRel. If SecB - // is not same as the section of Fixup, it will report error. Just return - // false and then this work can be finished by handleFixup. - if (&SecA != &SecB) - return false; - - // In SecA == SecB case. If the linker relaxation is enabled, we need record - // the ADD, SUB relocations. Otherwise the FixedValue has already been - // calculated out in evaluateFixup, return true and avoid record relocations. - if (!STI.hasFeature(LoongArch::FeatureRelax)) - return true; + const MCSymbol &SA = Target.getSymA()->getSymbol(); + const MCSymbol &SB = Target.getSymB()->getSymbol(); + + bool force = !SA.isInSection() || !SB.isInSection(); + if (!force) { + const MCSection &SecA = SA.getSection(); + const MCSection &SecB = SB.getSection(); + + // We need record relocation if SecA != SecB. Usually SecB is same as the + // section of Fixup, which will be record the relocation as PCRel. If SecB + // is not same as the section of Fixup, it will report error. Just return + // false and then this work can be finished by handleFixup. + if (&SecA != &SecB) + return false; + + // In SecA == SecB case. If the linker relaxation is enabled, we need record + // the ADD, SUB relocations. Otherwise the FixedValue has already been calc- + // ulated out in evaluateFixup, return true and avoid record relocations. + if (!STI.hasFeature(LoongArch::FeatureRelax)) + return true; + } switch (Fixup.getKind()) { case llvm::FK_Data_1: @@ -255,6 +291,9 @@ bool LoongArchAsmBackend::handleAddSubRelocations(const MCAsmLayout &Layout, case llvm::FK_Data_8: FK = getRelocPairForSize(64); break; + case llvm::FK_Data_leb128: + FK = getRelocPairForSize(128); + break; default: llvm_unreachable("unsupported fixup size"); } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h index fef0e84600a7..71977217f59b 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h @@ -66,6 +66,9 @@ public: void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override {} + std::pair relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, + int64_t &Value) const override; + bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 716fb67c5824..7ce08eabdeb6 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -329,16 +329,17 @@ bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF, return true; } -bool RISCVAsmBackend::relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, - int64_t &Value) const { +std::pair RISCVAsmBackend::relaxLEB128(MCLEBFragment &LF, + MCAsmLayout &Layout, + int64_t &Value) const { if (LF.isSigned()) - return false; + return std::make_pair(false, false); const MCExpr &Expr = LF.getValue(); if (ULEB128Reloc) { LF.getFixups().push_back( MCFixup::create(0, &Expr, FK_Data_leb128, Expr.getLoc())); } - return Expr.evaluateKnownAbsolute(Value, Layout); + return std::make_pair(Expr.evaluateKnownAbsolute(Value, Layout), false); } // Given a compressed control flow instruction this function returns diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h index 2ad6534ac8bc..902b44bba70f 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h @@ -100,8 +100,8 @@ public: bool &WasRelaxed) const override; bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override; - bool relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, - int64_t &Value) const override; + std::pair relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, + int64_t &Value) const override; bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override; diff --git a/llvm/test/MC/LoongArch/Relocations/leb128.s b/llvm/test/MC/LoongArch/Relocations/leb128.s new file mode 100644 index 000000000000..7a96ec551b76 --- /dev/null +++ b/llvm/test/MC/LoongArch/Relocations/leb128.s @@ -0,0 +1,72 @@ +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s -o %t +# RUN: llvm-readobj -r -x .alloc_w %t | FileCheck --check-prefixes=CHECK,NORELAX %s +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.relax +# RUN: llvm-readobj -r -x .alloc_w %t.relax | FileCheck --check-prefixes=CHECK,RELAX %s + +# RUN: not llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax --defsym ERR=1 %s -o /dev/null 2>&1 | \ +# RUN: FileCheck %s --check-prefix=ERR +# RUN: not llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax --defsym ERR=1 %s -o /dev/null 2>&1 | \ +# RUN: FileCheck %s --check-prefix=ERR + +# CHECK: Relocations [ +# CHECK-NEXT: .rela.alloc_w { +# RELAX-NEXT: 0x0 R_LARCH_ADD_ULEB128 w1 0x0 +# RELAX-NEXT: 0x0 R_LARCH_SUB_ULEB128 w 0x0 +# RELAX-NEXT: 0x1 R_LARCH_ADD_ULEB128 w2 0x0 +# RELAX-NEXT: 0x1 R_LARCH_SUB_ULEB128 w1 0x0 +# CHECK-NEXT: 0x2 R_LARCH_PCALA_HI20 foo 0x0 +# RELAX-NEXT: 0x2 R_LARCH_RELAX - 0x0 +# CHECK-NEXT: 0x6 R_LARCH_PCALA_LO12 foo 0x0 +# RELAX-NEXT: 0x6 R_LARCH_RELAX - 0x0 +# RELAX-NEXT: 0xA R_LARCH_ADD_ULEB128 w2 0x0 +# RELAX-NEXT: 0xA R_LARCH_SUB_ULEB128 w1 0x0 +# RELAX-NEXT: 0xB R_LARCH_ADD_ULEB128 w2 0x78 +# RELAX-NEXT: 0xB R_LARCH_SUB_ULEB128 w1 0x0 +# RELAX-NEXT: 0xD R_LARCH_ADD_ULEB128 w1 0x0 +# RELAX-NEXT: 0xD R_LARCH_SUB_ULEB128 w2 0x0 +# RELAX-NEXT: 0x17 R_LARCH_ADD_ULEB128 w3 0x6F +# RELAX-NEXT: 0x17 R_LARCH_SUB_ULEB128 w2 0x0 +# RELAX-NEXT: 0x18 R_LARCH_ADD_ULEB128 w3 0x71 +# RELAX-NEXT: 0x18 R_LARCH_SUB_ULEB128 w2 0x0 +# CHECK-NEXT: } +# CHECK-NEXT: ] + +# CHECK: Hex dump of section '.alloc_w': +# NORELAX-NEXT: 0x00000000 02080c00 001a8c01 c0020880 01f8ffff +# NORELAX-NEXT: 0x00000010 ffffffff ffff017f 8101 +# RELAX-NEXT: 0x00000000 00000c00 001a8c01 c0020080 00808080 +# RELAX-NEXT: 0x00000010 80808080 80800000 8000 + +.section .alloc_w,"ax",@progbits; w: +.uleb128 w1-w # w1 is later defined in the same section +.uleb128 w2-w1 # w1 and w2 are separated by a linker relaxable instruction +w1: + la.pcrel $t0, foo +w2: +.uleb128 w2-w1 # 0x08 +.uleb128 w2-w1+120 # 0x0180 +.uleb128 -(w2-w1) # 0x01fffffffffffffffff8 +.uleb128 w3-w2+111 # 0x7f +.uleb128 w3-w2+113 # 0x0181 +w3: + +.ifdef ERR +# ERR: :[[#@LINE+1]]:16: error: .uleb128 expression is not absolute +.uleb128 extern-w # extern is undefined +# ERR: :[[#@LINE+1]]:11: error: .uleb128 expression is not absolute +.uleb128 w-extern +# ERR: :[[#@LINE+1]]:11: error: .uleb128 expression is not absolute +.uleb128 x-w # x is later defined in another section + +.section .alloc_x,"aw",@progbits; x: +# ERR: :[[#@LINE+1]]:11: error: .uleb128 expression is not absolute +.uleb128 y-x +.section .alloc_y,"aw",@progbits; y: +# ERR: :[[#@LINE+1]]:11: error: .uleb128 expression is not absolute +.uleb128 x-y + +# ERR: :[[#@LINE+1]]:10: error: .uleb128 expression is not absolute +.uleb128 extern +# ERR: :[[#@LINE+1]]:10: error: .uleb128 expression is not absolute +.uleb128 y +.endif diff --git a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s index 14922657ae89..cd01332afd0b 100644 --- a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s +++ b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s @@ -8,12 +8,23 @@ # NORELAX-NEXT: 0x10 R_LARCH_PCALA_HI20 .text 0x0 # NORELAX-NEXT: 0x14 R_LARCH_PCALA_LO12 .text 0x0 # NORELAX-NEXT: } +# NORELAX-NEXT: Section ({{.*}}) .rela.data { +# NORELAX-NEXT: 0x30 R_LARCH_ADD8 foo 0x0 +# NORELAX-NEXT: 0x30 R_LARCH_SUB8 .text 0x10 +# NORELAX-NEXT: 0x31 R_LARCH_ADD16 foo 0x0 +# NORELAX-NEXT: 0x31 R_LARCH_SUB16 .text 0x10 +# NORELAX-NEXT: 0x33 R_LARCH_ADD32 foo 0x0 +# NORELAX-NEXT: 0x33 R_LARCH_SUB32 .text 0x10 +# NORELAX-NEXT: 0x37 R_LARCH_ADD64 foo 0x0 +# NORELAX-NEXT: 0x37 R_LARCH_SUB64 .text 0x10 +# NORELAX-NEXT: } # NORELAX-NEXT: ] # NORELAX: Hex dump of section '.data': -# NORELAX-NEXT: 0x00000000 04040004 00000004 00000000 0000000c -# NORELAX-NEXT: 0x00000010 0c000c00 00000c00 00000000 00000808 -# NORELAX-NEXT: 0x00000020 00080000 00080000 00000000 00 +# NORELAX-NEXT: 0x00000000 04040004 00000004 00000000 00000004 +# NORELAX-NEXT: 0x00000010 0c0c000c 0000000c 00000000 0000000c +# NORELAX-NEXT: 0x00000020 08080008 00000008 00000000 00000008 +# NORELAX-NEXT: 0x00000030 00000000 00000000 00000000 000000 # RELAX: Relocations [ # RELAX-NEXT: Section ({{.*}}) .rela.text { @@ -23,21 +34,32 @@ # RELAX-NEXT: 0x14 R_LARCH_RELAX - 0x0 # RELAX-NEXT: } # RELAX-NEXT: Section ({{.*}}) .rela.data { -# RELAX-NEXT: 0x1E R_LARCH_ADD8 .L4 0x0 -# RELAX-NEXT: 0x1E R_LARCH_SUB8 .L3 0x0 -# RELAX-NEXT: 0x1F R_LARCH_ADD16 .L4 0x0 -# RELAX-NEXT: 0x1F R_LARCH_SUB16 .L3 0x0 -# RELAX-NEXT: 0x21 R_LARCH_ADD32 .L4 0x0 -# RELAX-NEXT: 0x21 R_LARCH_SUB32 .L3 0x0 -# RELAX-NEXT: 0x25 R_LARCH_ADD64 .L4 0x0 -# RELAX-NEXT: 0x25 R_LARCH_SUB64 .L3 0x0 +# RELAX-NEXT: 0x20 R_LARCH_ADD8 .L4 0x0 +# RELAX-NEXT: 0x20 R_LARCH_SUB8 .L3 0x0 +# RELAX-NEXT: 0x21 R_LARCH_ADD16 .L4 0x0 +# RELAX-NEXT: 0x21 R_LARCH_SUB16 .L3 0x0 +# RELAX-NEXT: 0x23 R_LARCH_ADD32 .L4 0x0 +# RELAX-NEXT: 0x23 R_LARCH_SUB32 .L3 0x0 +# RELAX-NEXT: 0x27 R_LARCH_ADD64 .L4 0x0 +# RELAX-NEXT: 0x27 R_LARCH_SUB64 .L3 0x0 +# RELAX-NEXT: 0x2F R_LARCH_ADD_ULEB128 .L4 0x0 +# RELAX-NEXT: 0x2F R_LARCH_SUB_ULEB128 .L3 0x0 +# RELAX-NEXT: 0x30 R_LARCH_ADD8 foo 0x0 +# RELAX-NEXT: 0x30 R_LARCH_SUB8 .L3 0x0 +# RELAX-NEXT: 0x31 R_LARCH_ADD16 foo 0x0 +# RELAX-NEXT: 0x31 R_LARCH_SUB16 .L3 0x0 +# RELAX-NEXT: 0x33 R_LARCH_ADD32 foo 0x0 +# RELAX-NEXT: 0x33 R_LARCH_SUB32 .L3 0x0 +# RELAX-NEXT: 0x37 R_LARCH_ADD64 foo 0x0 +# RELAX-NEXT: 0x37 R_LARCH_SUB64 .L3 0x0 # RELAX-NEXT: } # RELAX-NEXT: ] # RELAX: Hex dump of section '.data': -# RELAX-NEXT: 0x00000000 04040004 00000004 00000000 0000000c -# RELAX-NEXT: 0x00000010 0c000c00 00000c00 00000000 00000000 -# RELAX-NEXT: 0x00000020 00000000 00000000 00000000 00 +# RELAX-NEXT: 0x00000000 04040004 00000004 00000000 00000004 +# RELAX-NEXT: 0x00000010 0c0c000c 0000000c 00000000 0000000c +# RELAX-NEXT: 0x00000020 00000000 00000000 00000000 00000000 +# RELAX-NEXT: 0x00000030 00000000 00000000 00000000 000000 .text .L1: @@ -55,13 +77,20 @@ .short .L2 - .L1 .word .L2 - .L1 .dword .L2 - .L1 +.uleb128 .L2 - .L1 ## TODO Handle alignment directive. .byte .L3 - .L2 .short .L3 - .L2 .word .L3 - .L2 .dword .L3 - .L2 +.uleb128 .L3 - .L2 ## With relaxation, emit relocs because the la.pcrel makes the diff variable. .byte .L4 - .L3 .short .L4 - .L3 .word .L4 - .L3 .dword .L4 - .L3 +.uleb128 .L4 - .L3 +.byte foo - .L3 +.short foo - .L3 +.word foo - .L3 +.dword foo - .L3 -- GitLab From 7b45c549670a8e8b6fe90f4382b0699dd20707d3 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Tue, 9 Jan 2024 15:21:41 +0800 Subject: [PATCH 159/652] [MC][RISCV] Check hasEmitNops before call shouldInsertExtraNopBytesForCodeAlign (#77236) The shouldInsertExtraNopBytesForCodeAlign() need STI to check whether relax is enabled or not. It is initialized when call setEmitNops. The setEmitNops may not be called in a section which has instructions but is not executable. In this case uninitialized STI will cause problems. Thus, check hasEmitNops before call it. Fixes: https://github.com/llvm/llvm-project/pull/76552#issuecomment-1878952480 --- llvm/lib/MC/MCExpr.cpp | 2 +- llvm/test/MC/RISCV/align-non-executable.s | 25 +++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 llvm/test/MC/RISCV/align-non-executable.s diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp index 9dae026535cc..80def6dfc24b 100644 --- a/llvm/lib/MC/MCExpr.cpp +++ b/llvm/lib/MC/MCExpr.cpp @@ -708,7 +708,7 @@ static void AttemptToFoldSymbolOffsetDifference( if (DF) { Displacement += DF->getContents().size(); } else if (auto *AF = dyn_cast(FI); - AF && Layout && + AF && Layout && AF->hasEmitNops() && !Asm->getBackend().shouldInsertExtraNopBytesForCodeAlign( *AF, Count)) { Displacement += Asm->computeFragmentSize(*Layout, *AF); diff --git a/llvm/test/MC/RISCV/align-non-executable.s b/llvm/test/MC/RISCV/align-non-executable.s new file mode 100644 index 000000000000..95f91d93369f --- /dev/null +++ b/llvm/test/MC/RISCV/align-non-executable.s @@ -0,0 +1,25 @@ +## A label difference separated by an alignment directive, when the +## referenced symbols are in a non-executable section with instructions, +## should generate ADD/SUB relocations. +## https://github.com/llvm/llvm-project/pull/76552 + +# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=+relax %s \ +# RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK,RELAX %s +# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=-relax %s \ +# RUN: | llvm-readobj -r - | FileCheck %s + +.section ".dummy", "a" +.L1: + call func +.p2align 3 +.L2: +.dword .L2 - .L1 + +# CHECK: Relocations [ +# CHECK-NEXT: Section ({{.*}}) .rela.dummy { +# CHECK-NEXT: 0x0 R_RISCV_CALL_PLT func 0x0 +# RELAX-NEXT: 0x0 R_RISCV_RELAX - 0x0 +# CHECK-NEXT: 0x8 R_RISCV_ADD64 .L2 0x0 +# CHECK-NEXT: 0x8 R_RISCV_SUB64 .L1 0x0 +# CHECK-NEXT: } +# CHECK-NEXT: ] -- GitLab From 3d688d4e3db58c68f090c3e118e7e052c9c25593 Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Tue, 9 Jan 2024 07:45:18 +0000 Subject: [PATCH 160/652] [mlir][Bazel] Adjust BUILD.bazel file for b43c50490c5964b3b1aa1b95a9025a5b5942a46e --- .../llvm-project-overlay/mlir/BUILD.bazel | 52 +++++++++++++------ 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 7a4495e28cae..6822a49ef0fc 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -3957,7 +3957,7 @@ cc_library( ":ArithDialect", ":AsyncDialect", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":FuncDialect", ":FuncToLLVM", ":FuncTransforms", @@ -4447,6 +4447,7 @@ cc_library( ":CommonFolders", ":ControlFlowInterfaces", ":ControlFlowOpsIncGen", + ":ConvertToLLVMInterface", ":IR", ":SideEffectInterfaces", ":Support", @@ -4493,6 +4494,7 @@ cc_library( ":CommonFolders", ":ControlFlowDialect", ":ControlFlowInterfaces", + ":ConvertToLLVMInterface", ":FuncIncGen", ":FunctionInterfaces", ":IR", @@ -5811,6 +5813,7 @@ cc_library( ":ControlFlowToLLVM", ":ConversionPassIncGen", ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":FuncToLLVM", ":GPUDialect", ":GPUTransforms", @@ -6049,7 +6052,7 @@ cc_library( includes = ["include"], deps = [ ":BasicPtxBuilderInterface", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":DialectUtils", ":GPUDialect", ":IR", @@ -6269,7 +6272,7 @@ cc_library( includes = ["include"], deps = [ ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":FuncDialect", ":GPUDialect", ":IR", @@ -7802,13 +7805,26 @@ cc_library( ], ) +cc_library( + name = "ConvertToLLVMInterface", + srcs = ["lib/Conversion/ConvertToLLVM/ToLLVMInterface.cpp"], + hdrs = ["include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h"], + includes = ["include"], + deps = [ + ":IR", + ":Support", + "//llvm:Support", + ], +) + cc_library( name = "ConvertToLLVM", - srcs = glob(["lib/Conversion/ConvertToLLVM/*.cpp"]), - hdrs = glob(["include/mlir/Conversion/ConvertToLLVM/*.h"]), + srcs = ["lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp"], + hdrs = ["include/mlir/Conversion/ConvertToLLVM/ToLLVMPass.h"], includes = ["include"], deps = [ ":ConversionPassIncGen", + ":ConvertToLLVMInterface", ":IR", ":LLVMCommonConversion", ":LLVMDialect", @@ -7835,7 +7851,7 @@ cc_library( ":ArithToLLVM", ":ControlFlowToLLVM", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":DataLayoutInterfaces", ":DialectUtils", ":FuncDialect", @@ -7894,7 +7910,7 @@ cc_library( ":ArithToLLVM", ":ControlFlowDialect", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":DataLayoutInterfaces", ":DialectUtils", ":IR", @@ -7941,7 +7957,7 @@ cc_library( ":Analysis", ":ArithDialect", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":DataLayoutInterfaces", ":FuncDialect", ":IR", @@ -8005,7 +8021,7 @@ cc_library( ":AMDGPUDialect", ":ArithDialect", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":IR", ":LLVMDialect", ":Pass", @@ -8025,7 +8041,7 @@ cc_library( ":ArithAttrToLLVMConversion", ":ArithDialect", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":IR", ":LLVMCommonConversion", ":LLVMDialect", @@ -8064,7 +8080,7 @@ cc_library( ":Analysis", ":ArithAttrToLLVMConversion", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":DataLayoutInterfaces", ":IR", ":LLVMCommonConversion", @@ -10159,7 +10175,7 @@ cc_library( deps = [ ":Analysis", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":IR", ":IndexDialect", ":LLVMCommonConversion", @@ -10204,6 +10220,7 @@ cc_library( includes = ["include"], deps = [ ":CastInterfaces", + ":ConvertToLLVMInterface", ":IR", ":IndexEnumsIncGen", ":IndexOpsIncGen", @@ -11660,7 +11677,7 @@ cc_library( ":CallOpInterfaces", ":CastInterfaces", ":ControlFlowInterfaces", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":FunctionInterfaces", ":IR", ":LLVMCommonConversion", @@ -11921,6 +11938,7 @@ cc_library( ":ComplexAttributesIncGen", ":ComplexBaseIncGen", ":ComplexOpsIncGen", + ":ConvertToLLVMInterface", ":IR", ":InferTypeOpInterface", ":SideEffectInterfaces", @@ -11943,7 +11961,7 @@ cc_library( ":ArithDialect", ":ComplexDialect", ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":FuncDialect", ":IR", ":LLVMCommonConversion", @@ -12184,6 +12202,7 @@ cc_library( ":ArithOpsInterfacesIncGen", ":CastInterfaces", ":CommonFolders", + ":ConvertToLLVMInterface", ":IR", ":InferIntRangeCommon", ":InferIntRangeInterface", @@ -12346,6 +12365,7 @@ cc_library( deps = [ ":ArithDialect", ":CommonFolders", + ":ConvertToLLVMInterface", ":IR", ":InferTypeOpInterface", ":MathBaseIncGen", @@ -12491,6 +12511,7 @@ cc_library( ":CastInterfaces", ":ComplexDialect", ":ControlFlowInterfaces", + ":ConvertToLLVMInterface", ":CopyOpInterface", ":DialectUtils", ":IR", @@ -13398,6 +13419,7 @@ cc_library( hdrs = ["include/mlir/Dialect/UB/IR/UBOps.h"], includes = ["include"], deps = [ + ":ConvertToLLVMInterface", ":IR", ":SideEffectInterfaces", ":UBOpsIncGen", @@ -13418,7 +13440,7 @@ cc_library( includes = ["include"], deps = [ ":ConversionPassIncGen", - ":ConvertToLLVM", + ":ConvertToLLVMInterface", ":IR", ":LLVMCommonConversion", ":LLVMDialect", -- GitLab From 81df51fb318f2a83de3414c6f9f6770fa6ccda38 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Tue, 9 Jan 2024 08:13:31 +0000 Subject: [PATCH 161/652] [mlir][vector] Don't treat memrefs with empty stride as non-contiguous (#76848) As per the docs [1]: ``` In absence of an explicit layout, a memref is considered to have a multi-dimensional identity affine map layout. ``` This patch makes sure that MemRefs with no strides (i.e. no explicit layout) are treated as contiguous when checking whether a particular vector is a contiguous slice of the given MemRef. [1] https://mlir.llvm.org/docs/Dialects/Builtin/#layout Follow-up for #76428. --- mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp | 27 ++++++----- .../Vector/vector-transfer-flatten.mlir | 48 +++++++++++++------ 2 files changed, 49 insertions(+), 26 deletions(-) diff --git a/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp b/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp index c1c0f5483a6a..377f3d8c5574 100644 --- a/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp +++ b/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp @@ -264,26 +264,31 @@ bool vector::isContiguousSlice(MemRefType memrefType, VectorType vectorType) { if (!succeeded(getStridesAndOffset(memrefType, stridesFull, offset))) return false; auto strides = ArrayRef(stridesFull).take_back(vecRank); + memrefType.getLayout().isIdentity(); // TODO: Add support for memref with trailing dynamic shapes. Memrefs // with leading dynamic dimensions are already supported. if (ShapedType::isDynamicShape(memrefShape)) return false; - // Cond 1: A contiguous memref will always have a unit trailing stride. - if (strides.empty() || strides.back() != 1) - return false; + // Cond 1: Check whether `memrefType` is contiguous. + if (!strides.empty()) { + // Cond 1.1: A contiguous memref will always have a unit trailing stride. + if (strides.back() != 1) + return false; - // Cond 2: Strides of a contiguous memref have to match the flattened dims. - strides = strides.drop_back(1); - SmallVector flattenedDims; - for (size_t i = 1; i < memrefShape.size(); i++) - flattenedDims.push_back(mlir::computeProduct(memrefShape.take_back(i))); + // Cond 1.2: Strides of a contiguous memref have to match the flattened + // dims. + strides = strides.drop_back(1); + SmallVector flattenedDims; + for (size_t i = 1; i < memrefShape.size(); i++) + flattenedDims.push_back(mlir::computeProduct(memrefShape.take_back(i))); - if (!llvm::equal(strides, llvm::reverse(flattenedDims))) - return false; + if (!llvm::equal(strides, llvm::reverse(flattenedDims))) + return false; + } - // Cond 3: Compare the dims of `vectorType` against `memrefType` (in reverse). + // Cond 2: Compare the dims of `vectorType` against `memrefType` (in reverse). // In the most basic case, all dims will match. auto firstNonMatchingDim = std::mismatch(vectorShape.rbegin(), vectorShape.rend(), diff --git a/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir b/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir index ae457ea81ec5..9976048a3320 100644 --- a/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir +++ b/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir @@ -18,6 +18,24 @@ func.func @transfer_read_dims_match_contiguous( // ----- +func.func @transfer_read_dims_match_contiguous_empty_stride( + %arg : memref<5x4x3x2xi8>) -> vector<5x4x3x2xi8> { + %c0 = arith.constant 0 : index + %cst = arith.constant 0 : i8 + %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst : + memref<5x4x3x2xi8>, vector<5x4x3x2xi8> + return %v : vector<5x4x3x2xi8> +} + +// CHECK-LABEL: func @transfer_read_dims_match_contiguous_empty_stride +// CHECK-SAME: %[[ARG:[0-9a-zA-Z]+]]: memref<5x4x3x2xi8 +// CHECK: %[[COLLAPSED:.+]] = memref.collapse_shape %[[ARG]] {{.}}[0, 1, 2, 3] +// CHECK: %[[READ1D:.+]] = vector.transfer_read %[[COLLAPSED]] +// CHECK: %[[VEC2D:.+]] = vector.shape_cast %[[READ1D]] : vector<120xi8> to vector<5x4x3x2xi8> +// CHECK: return %[[VEC2D]] + +// ----- + // The shape of the memref and the vector don't match, but the vector is a // contiguous subset of the memref, so "flattenable". @@ -114,6 +132,21 @@ func.func @transfer_read_dims_mismatch_non_contiguous( // ----- +func.func @transfer_read_dims_mismatch_non_contiguous_empty_stride( + %arg : memref<5x4x3x2xi8>) -> vector<2x1x2x2xi8> { + %c0 = arith.constant 0 : index + %cst = arith.constant 0 : i8 + %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst : + memref<5x4x3x2xi8>, vector<2x1x2x2xi8> + return %v : vector<2x1x2x2xi8> +} + +// CHECK-LABEL: func.func @transfer_read_dims_mismatch_non_contiguous_empty_stride +// CHECK-NOT: memref.collapse_shape +// CHECK-NOT: vector.shape_cast + +// ----- + func.func @transfer_write_dims_match_contiguous( %arg : memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>, %vec : vector<5x4x3x2xi8>) { %c0 = arith.constant 0 : index @@ -356,18 +389,3 @@ func.func @fold_unit_dims_entirely(%arg0 : vector<8xi32>, // CHECK: %[[VAL_3:.*]] = arith.muli %[[VAL_0]], %[[VAL_1]] : vector<8xi32> // CHECK: %[[VAL_4:.*]] = arith.addi %[[VAL_3]], %[[VAL_2]] : vector<8xi32> // CHECK: return %[[VAL_4]] : vector<8xi32> - -// ----- - -// This test is to make sure there is no crash for empty stride. -func.func @stride_empty_test(%1: memref) -> vector<32x256xi16> { - %c0_i16 = arith.constant 0 : i16 - %3 = vector.transfer_read %1[], %c0_i16 {permutation_map = affine_map<() -> (0, 0)>} : memref, vector<32x256xi16> - return %3 : vector<32x256xi16> - - // CHECK-LABEL: func.func @stride_empty_test - // CHECK: %[[VAL:.*]] = arith.constant 0 : i16 - // CHECK: %[[RET:.*]] = vector.transfer_read {{.*}} vector<32x256xi16> - // CHECK: return %[[RET]] - // CHECK-NOT: empty() -} -- GitLab From daecc303bb719ed63566fcb343afec169826f82c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 9 Jan 2024 15:13:58 +0700 Subject: [PATCH 162/652] AMDGPU: Replace sqrt OpenCL libcalls with llvm.sqrt (#74197) The library implementation is just a wrapper around a call to the intrinsic, but loses metadata. Swap out the call site to the intrinsic so that the lowering can see the !fpmath metadata and fast math flags. Since d56e0d07cc5ee8e334fd1ad403eef0b1a771384f, clang started placing !fpmath on OpenCL library sqrt calls. Also don't bother emitting native_sqrt anymore, it's just another wrapper around llvm.sqrt. --- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 32 +------- .../AMDGPU/amdgpu-simplify-libcall-sqrt.ll | 76 +++++++++---------- llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll | 5 +- 3 files changed, 43 insertions(+), 70 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp index f03e6b8915b1..1b2f74cf153b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp @@ -87,9 +87,6 @@ private: Constant *copr0, Constant *copr1); bool evaluateCall(CallInst *aCI, const FuncInfo &FInfo); - // sqrt - bool fold_sqrt(FPMathOperator *FPOp, IRBuilder<> &B, const FuncInfo &FInfo); - /// Insert a value to sincos function \p Fsincos. Returns (value of sin, value /// of cos, sincos call). std::tuple insertSinCos(Value *Arg, @@ -672,8 +669,6 @@ bool AMDGPULibCalls::fold(CallInst *CI) { // Specialized optimizations for each function call. // - // TODO: Handle other simple intrinsic wrappers. Sqrt. - // // TODO: Handle native functions switch (FInfo.getId()) { case AMDGPULibFunc::EI_EXP: @@ -794,7 +789,9 @@ bool AMDGPULibCalls::fold(CallInst *CI) { case AMDGPULibFunc::EI_ROOTN: return fold_rootn(FPOp, B, FInfo); case AMDGPULibFunc::EI_SQRT: - return fold_sqrt(FPOp, B, FInfo); + // TODO: Allow with strictfp + constrained intrinsic + return tryReplaceLibcallWithSimpleIntrinsic( + B, CI, Intrinsic::sqrt, true, true, /*AllowStrictFP=*/false); case AMDGPULibFunc::EI_COS: case AMDGPULibFunc::EI_SIN: return fold_sincos(FPOp, B, FInfo); @@ -1273,29 +1270,6 @@ bool AMDGPULibCalls::tryReplaceLibcallWithSimpleIntrinsic( return true; } -// fold sqrt -> native_sqrt (x) -bool AMDGPULibCalls::fold_sqrt(FPMathOperator *FPOp, IRBuilder<> &B, - const FuncInfo &FInfo) { - if (!isUnsafeMath(FPOp)) - return false; - - if (getArgType(FInfo) == AMDGPULibFunc::F32 && (getVecSize(FInfo) == 1) && - (FInfo.getPrefix() != AMDGPULibFunc::NATIVE)) { - Module *M = B.GetInsertBlock()->getModule(); - - if (FunctionCallee FPExpr = getNativeFunction( - M, AMDGPULibFunc(AMDGPULibFunc::EI_SQRT, FInfo))) { - Value *opr0 = FPOp->getOperand(0); - LLVM_DEBUG(errs() << "AMDIC: " << *FPOp << " ---> " - << "sqrt(" << *opr0 << ")\n"); - Value *nval = CreateCallEx(B,FPExpr, opr0, "__sqrt"); - replaceCall(FPOp, nval); - return true; - } - } - return false; -} - std::tuple AMDGPULibCalls::insertSinCos(Value *Arg, FastMathFlags FMF, IRBuilder<> &B, FunctionCallee Fsincos) { diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sqrt.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sqrt.ll index 5b57778d5fdc..72f809b3e060 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sqrt.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sqrt.ll @@ -27,7 +27,7 @@ declare <16 x half> @_Z4sqrtDv16_Dh(<16 x half>) define float @test_sqrt_f32(float %arg) { ; CHECK-LABEL: define float @test_sqrt_f32 ; CHECK-SAME: (float [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]), !fpmath [[META0:![0-9]+]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call float @llvm.sqrt.f32(float [[ARG]]), !fpmath [[META0:![0-9]+]] ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call float @_Z4sqrtf(float %arg), !fpmath !0 @@ -37,7 +37,7 @@ define float @test_sqrt_f32(float %arg) { define <2 x float> @test_sqrt_v2f32(<2 x float> %arg) { ; CHECK-LABEL: define <2 x float> @test_sqrt_v2f32 ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]), !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[ARG]]), !fpmath [[META0]] ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg), !fpmath !0 @@ -47,7 +47,7 @@ define <2 x float> @test_sqrt_v2f32(<2 x float> %arg) { define <3 x float> @test_sqrt_v3f32(<3 x float> %arg) { ; CHECK-LABEL: define <3 x float> @test_sqrt_v3f32 ; CHECK-SAME: (<3 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x float> @_Z4sqrtDv3_f(<3 x float> [[ARG]]), !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x float> @llvm.sqrt.v3f32(<3 x float> [[ARG]]), !fpmath [[META0]] ; CHECK-NEXT: ret <3 x float> [[SQRT]] ; %sqrt = tail call <3 x float> @_Z4sqrtDv3_f(<3 x float> %arg), !fpmath !0 @@ -57,7 +57,7 @@ define <3 x float> @test_sqrt_v3f32(<3 x float> %arg) { define <4 x float> @test_sqrt_v4f32(<4 x float> %arg) { ; CHECK-LABEL: define <4 x float> @test_sqrt_v4f32 ; CHECK-SAME: (<4 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x float> @_Z4sqrtDv4_f(<4 x float> [[ARG]]), !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META0]] ; CHECK-NEXT: ret <4 x float> [[SQRT]] ; %sqrt = tail call <4 x float> @_Z4sqrtDv4_f(<4 x float> %arg), !fpmath !0 @@ -67,7 +67,7 @@ define <4 x float> @test_sqrt_v4f32(<4 x float> %arg) { define <8 x float> @test_sqrt_v8f32(<8 x float> %arg) { ; CHECK-LABEL: define <8 x float> @test_sqrt_v8f32 ; CHECK-SAME: (<8 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x float> @_Z4sqrtDv8_f(<8 x float> [[ARG]]), !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> [[ARG]]), !fpmath [[META0]] ; CHECK-NEXT: ret <8 x float> [[SQRT]] ; %sqrt = tail call <8 x float> @_Z4sqrtDv8_f(<8 x float> %arg), !fpmath !0 @@ -77,7 +77,7 @@ define <8 x float> @test_sqrt_v8f32(<8 x float> %arg) { define <16 x float> @test_sqrt_v16f32(<16 x float> %arg) { ; CHECK-LABEL: define <16 x float> @test_sqrt_v16f32 ; CHECK-SAME: (<16 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x float> @_Z4sqrtDv16_f(<16 x float> [[ARG]]), !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x float> @llvm.sqrt.v16f32(<16 x float> [[ARG]]), !fpmath [[META0]] ; CHECK-NEXT: ret <16 x float> [[SQRT]] ; %sqrt = tail call <16 x float> @_Z4sqrtDv16_f(<16 x float> %arg), !fpmath !0 @@ -87,7 +87,7 @@ define <16 x float> @test_sqrt_v16f32(<16 x float> %arg) { define float @test_sqrt_cr_f32(float %arg) { ; CHECK-LABEL: define float @test_sqrt_cr_f32 ; CHECK-SAME: (float [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call float @llvm.sqrt.f32(float [[ARG]]) ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call float @_Z4sqrtf(float %arg) @@ -97,7 +97,7 @@ define float @test_sqrt_cr_f32(float %arg) { define <2 x float> @test_sqrt_cr_v2f32(<2 x float> %arg) { ; CHECK-LABEL: define <2 x float> @test_sqrt_cr_v2f32 ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[ARG]]) ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg) @@ -107,7 +107,7 @@ define <2 x float> @test_sqrt_cr_v2f32(<2 x float> %arg) { define <3 x float> @test_sqrt_cr_v3f32(<3 x float> %arg) { ; CHECK-LABEL: define <3 x float> @test_sqrt_cr_v3f32 ; CHECK-SAME: (<3 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x float> @_Z4sqrtDv3_f(<3 x float> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x float> @llvm.sqrt.v3f32(<3 x float> [[ARG]]) ; CHECK-NEXT: ret <3 x float> [[SQRT]] ; %sqrt = tail call <3 x float> @_Z4sqrtDv3_f(<3 x float> %arg) @@ -117,7 +117,7 @@ define <3 x float> @test_sqrt_cr_v3f32(<3 x float> %arg) { define <4 x float> @test_sqrt_cr_v4f32(<4 x float> %arg) { ; CHECK-LABEL: define <4 x float> @test_sqrt_cr_v4f32 ; CHECK-SAME: (<4 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x float> @_Z4sqrtDv4_f(<4 x float> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]) ; CHECK-NEXT: ret <4 x float> [[SQRT]] ; %sqrt = tail call <4 x float> @_Z4sqrtDv4_f(<4 x float> %arg) @@ -127,7 +127,7 @@ define <4 x float> @test_sqrt_cr_v4f32(<4 x float> %arg) { define <8 x float> @test_sqrt_cr_v8f32(<8 x float> %arg) { ; CHECK-LABEL: define <8 x float> @test_sqrt_cr_v8f32 ; CHECK-SAME: (<8 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x float> @_Z4sqrtDv8_f(<8 x float> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> [[ARG]]) ; CHECK-NEXT: ret <8 x float> [[SQRT]] ; %sqrt = tail call <8 x float> @_Z4sqrtDv8_f(<8 x float> %arg) @@ -137,7 +137,7 @@ define <8 x float> @test_sqrt_cr_v8f32(<8 x float> %arg) { define <16 x float> @test_sqrt_cr_v16f32(<16 x float> %arg) { ; CHECK-LABEL: define <16 x float> @test_sqrt_cr_v16f32 ; CHECK-SAME: (<16 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x float> @_Z4sqrtDv16_f(<16 x float> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x float> @llvm.sqrt.v16f32(<16 x float> [[ARG]]) ; CHECK-NEXT: ret <16 x float> [[SQRT]] ; %sqrt = tail call <16 x float> @_Z4sqrtDv16_f(<16 x float> %arg) @@ -147,7 +147,7 @@ define <16 x float> @test_sqrt_cr_v16f32(<16 x float> %arg) { define double @test_sqrt_f64(double %arg) { ; CHECK-LABEL: define double @test_sqrt_f64 ; CHECK-SAME: (double [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call double @_Z4sqrtd(double [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call double @llvm.sqrt.f64(double [[ARG]]) ; CHECK-NEXT: ret double [[SQRT]] ; %sqrt = tail call double @_Z4sqrtd(double %arg) @@ -157,7 +157,7 @@ define double @test_sqrt_f64(double %arg) { define <2 x double> @test_sqrt_v2f64(<2 x double> %arg) { ; CHECK-LABEL: define <2 x double> @test_sqrt_v2f64 ; CHECK-SAME: (<2 x double> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x double> @_Z4sqrtDv2_d(<2 x double> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x double> @llvm.sqrt.v2f64(<2 x double> [[ARG]]) ; CHECK-NEXT: ret <2 x double> [[SQRT]] ; %sqrt = tail call <2 x double> @_Z4sqrtDv2_d(<2 x double> %arg) @@ -167,7 +167,7 @@ define <2 x double> @test_sqrt_v2f64(<2 x double> %arg) { define <3 x double> @test_sqrt_v3f64(<3 x double> %arg) { ; CHECK-LABEL: define <3 x double> @test_sqrt_v3f64 ; CHECK-SAME: (<3 x double> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x double> @_Z4sqrtDv3_d(<3 x double> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x double> @llvm.sqrt.v3f64(<3 x double> [[ARG]]) ; CHECK-NEXT: ret <3 x double> [[SQRT]] ; %sqrt = tail call <3 x double> @_Z4sqrtDv3_d(<3 x double> %arg) @@ -177,7 +177,7 @@ define <3 x double> @test_sqrt_v3f64(<3 x double> %arg) { define <4 x double> @test_sqrt_v4f64(<4 x double> %arg) { ; CHECK-LABEL: define <4 x double> @test_sqrt_v4f64 ; CHECK-SAME: (<4 x double> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x double> @_Z4sqrtDv4_d(<4 x double> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x double> @llvm.sqrt.v4f64(<4 x double> [[ARG]]) ; CHECK-NEXT: ret <4 x double> [[SQRT]] ; %sqrt = tail call <4 x double> @_Z4sqrtDv4_d(<4 x double> %arg) @@ -187,7 +187,7 @@ define <4 x double> @test_sqrt_v4f64(<4 x double> %arg) { define <8 x double> @test_sqrt_v8f64(<8 x double> %arg) { ; CHECK-LABEL: define <8 x double> @test_sqrt_v8f64 ; CHECK-SAME: (<8 x double> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x double> @_Z4sqrtDv8_d(<8 x double> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x double> @llvm.sqrt.v8f64(<8 x double> [[ARG]]) ; CHECK-NEXT: ret <8 x double> [[SQRT]] ; %sqrt = tail call <8 x double> @_Z4sqrtDv8_d(<8 x double> %arg) @@ -197,7 +197,7 @@ define <8 x double> @test_sqrt_v8f64(<8 x double> %arg) { define <16 x double> @test_sqrt_v16f64(<16 x double> %arg) { ; CHECK-LABEL: define <16 x double> @test_sqrt_v16f64 ; CHECK-SAME: (<16 x double> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x double> @_Z4sqrtDv16_d(<16 x double> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x double> @llvm.sqrt.v16f64(<16 x double> [[ARG]]) ; CHECK-NEXT: ret <16 x double> [[SQRT]] ; %sqrt = tail call <16 x double> @_Z4sqrtDv16_d(<16 x double> %arg) @@ -207,7 +207,7 @@ define <16 x double> @test_sqrt_v16f64(<16 x double> %arg) { define half @test_sqrt_f16(half %arg) { ; CHECK-LABEL: define half @test_sqrt_f16 ; CHECK-SAME: (half [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call half @_Z4sqrtDh(half [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call half @llvm.sqrt.f16(half [[ARG]]) ; CHECK-NEXT: ret half [[SQRT]] ; %sqrt = tail call half @_Z4sqrtDh(half %arg) @@ -217,7 +217,7 @@ define half @test_sqrt_f16(half %arg) { define <2 x half> @test_sqrt_v2f16(<2 x half> %arg) { ; CHECK-LABEL: define <2 x half> @test_sqrt_v2f16 ; CHECK-SAME: (<2 x half> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x half> @_Z4sqrtDv2_Dh(<2 x half> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x half> @llvm.sqrt.v2f16(<2 x half> [[ARG]]) ; CHECK-NEXT: ret <2 x half> [[SQRT]] ; %sqrt = tail call <2 x half> @_Z4sqrtDv2_Dh(<2 x half> %arg) @@ -227,7 +227,7 @@ define <2 x half> @test_sqrt_v2f16(<2 x half> %arg) { define <3 x half> @test_sqrt_v3f16(<3 x half> %arg) { ; CHECK-LABEL: define <3 x half> @test_sqrt_v3f16 ; CHECK-SAME: (<3 x half> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x half> @_Z4sqrtDv3_Dh(<3 x half> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <3 x half> @llvm.sqrt.v3f16(<3 x half> [[ARG]]) ; CHECK-NEXT: ret <3 x half> [[SQRT]] ; %sqrt = tail call <3 x half> @_Z4sqrtDv3_Dh(<3 x half> %arg) @@ -237,7 +237,7 @@ define <3 x half> @test_sqrt_v3f16(<3 x half> %arg) { define <4 x half> @test_sqrt_v4f16(<4 x half> %arg) { ; CHECK-LABEL: define <4 x half> @test_sqrt_v4f16 ; CHECK-SAME: (<4 x half> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x half> @_Z4sqrtDv4_Dh(<4 x half> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <4 x half> @llvm.sqrt.v4f16(<4 x half> [[ARG]]) ; CHECK-NEXT: ret <4 x half> [[SQRT]] ; %sqrt = tail call <4 x half> @_Z4sqrtDv4_Dh(<4 x half> %arg) @@ -247,7 +247,7 @@ define <4 x half> @test_sqrt_v4f16(<4 x half> %arg) { define <8 x half> @test_sqrt_v8f16(<8 x half> %arg) { ; CHECK-LABEL: define <8 x half> @test_sqrt_v8f16 ; CHECK-SAME: (<8 x half> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x half> @_Z4sqrtDv8_Dh(<8 x half> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <8 x half> @llvm.sqrt.v8f16(<8 x half> [[ARG]]) ; CHECK-NEXT: ret <8 x half> [[SQRT]] ; %sqrt = tail call <8 x half> @_Z4sqrtDv8_Dh(<8 x half> %arg) @@ -257,7 +257,7 @@ define <8 x half> @test_sqrt_v8f16(<8 x half> %arg) { define <16 x half> @test_sqrt_v16f16(<16 x half> %arg) { ; CHECK-LABEL: define <16 x half> @test_sqrt_v16f16 ; CHECK-SAME: (<16 x half> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x half> @_Z4sqrtDv16_Dh(<16 x half> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call <16 x half> @llvm.sqrt.v16f16(<16 x half> [[ARG]]) ; CHECK-NEXT: ret <16 x half> [[SQRT]] ; %sqrt = tail call <16 x half> @_Z4sqrtDv16_Dh(<16 x half> %arg) @@ -267,7 +267,7 @@ define <16 x half> @test_sqrt_v16f16(<16 x half> %arg) { define float @test_sqrt_f32_nobuiltin_callsite(float %arg) { ; CHECK-LABEL: define float @test_sqrt_f32_nobuiltin_callsite ; CHECK-SAME: (float [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR2:[0-9]+]], !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR3:[0-9]+]], !fpmath [[META0]] ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call float @_Z4sqrtf(float %arg) #0, !fpmath !0 @@ -277,7 +277,7 @@ define float @test_sqrt_f32_nobuiltin_callsite(float %arg) { define <2 x float> @test_sqrt_v2f32_nobuiltin_callsite(<2 x float> %arg) { ; CHECK-LABEL: define <2 x float> @test_sqrt_v2f32_nobuiltin_callsite ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR2]], !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR3]], !fpmath [[META0]] ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg) #0, !fpmath !0 @@ -287,7 +287,7 @@ define <2 x float> @test_sqrt_v2f32_nobuiltin_callsite(<2 x float> %arg) { define float @test_sqrt_cr_f32_nobuiltin_callsite(float %arg) { ; CHECK-LABEL: define float @test_sqrt_cr_f32_nobuiltin_callsite ; CHECK-SAME: (float [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR2]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR3]] ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call float @_Z4sqrtf(float %arg) #0 @@ -297,7 +297,7 @@ define float @test_sqrt_cr_f32_nobuiltin_callsite(float %arg) { define <2 x float> @test_sqrt_cr_v2f32_nobuiltin_callsite(<2 x float> %arg) { ; CHECK-LABEL: define <2 x float> @test_sqrt_cr_v2f32_nobuiltin_callsite ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR2]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR3]] ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg) #0 @@ -308,7 +308,7 @@ define <2 x float> @test_sqrt_cr_v2f32_nobuiltin_callsite(<2 x float> %arg) { define float @test_sqrt_f32_nobuiltins(float %arg) #1 { ; CHECK-LABEL: define float @test_sqrt_f32_nobuiltins ; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR2]], !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR3]], !fpmath [[META0]] ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call float @_Z4sqrtf(float %arg) #0, !fpmath !0 @@ -318,7 +318,7 @@ define float @test_sqrt_f32_nobuiltins(float %arg) #1 { define <2 x float> @test_sqrt_v2f32_nobuiltins(<2 x float> %arg) #1 { ; CHECK-LABEL: define <2 x float> @test_sqrt_v2f32_nobuiltins ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR2]], !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR3]], !fpmath [[META0]] ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg) #0, !fpmath !0 @@ -328,7 +328,7 @@ define <2 x float> @test_sqrt_v2f32_nobuiltins(<2 x float> %arg) #1 { define float @test_sqrt_cr_f32_nobuiltins(float %arg) #1 { ; CHECK-LABEL: define float @test_sqrt_cr_f32_nobuiltins ; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR2]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call float @_Z4sqrtf(float [[ARG]]) #[[ATTR3]] ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call float @_Z4sqrtf(float %arg) #0 @@ -338,7 +338,7 @@ define float @test_sqrt_cr_f32_nobuiltins(float %arg) #1 { define <2 x float> @test_sqrt_cr_v2f32_nobuiltins(<2 x float> %arg) #1 { ; CHECK-LABEL: define <2 x float> @test_sqrt_cr_v2f32_nobuiltins ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR2]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) #[[ATTR3]] ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg) #0 @@ -348,7 +348,7 @@ define <2 x float> @test_sqrt_cr_v2f32_nobuiltins(<2 x float> %arg) #1 { define float @test_sqrt_f32_preserve_flags(float %arg) { ; CHECK-LABEL: define float @test_sqrt_f32_preserve_flags ; CHECK-SAME: (float [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan ninf float @_Z4sqrtf(float [[ARG]]), !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan ninf float @llvm.sqrt.f32(float [[ARG]]), !fpmath [[META0]] ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call nnan ninf float @_Z4sqrtf(float %arg), !fpmath !0 @@ -358,7 +358,7 @@ define float @test_sqrt_f32_preserve_flags(float %arg) { define <2 x float> @test_sqrt_v2f32_preserve_flags(<2 x float> %arg) { ; CHECK-LABEL: define <2 x float> @test_sqrt_v2f32_preserve_flags ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan nsz contract <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]), !fpmath [[META0]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan nsz contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[ARG]]), !fpmath [[META0]] ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call contract nsz nnan <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg), !fpmath !0 @@ -368,7 +368,7 @@ define <2 x float> @test_sqrt_v2f32_preserve_flags(<2 x float> %arg) { define float @test_sqrt_f32_preserve_flags_md(float %arg) { ; CHECK-LABEL: define float @test_sqrt_f32_preserve_flags_md ; CHECK-SAME: (float [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan ninf float @_Z4sqrtf(float [[ARG]]), !fpmath [[META0]], !foo [[META1:![0-9]+]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan ninf float @llvm.sqrt.f32(float [[ARG]]), !fpmath [[META0]], !foo [[META1:![0-9]+]] ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call nnan ninf float @_Z4sqrtf(float %arg), !fpmath !0, !foo !1 @@ -378,7 +378,7 @@ define float @test_sqrt_f32_preserve_flags_md(float %arg) { define <2 x float> @test_sqrt_v2f32_preserve_flags_md(<2 x float> %arg) { ; CHECK-LABEL: define <2 x float> @test_sqrt_v2f32_preserve_flags_md ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan nsz contract <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]), !fpmath [[META0]], !foo [[META1]] +; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan nsz contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[ARG]]), !fpmath [[META0]], !foo [[META1]] ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call contract nsz nnan <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg), !fpmath !0, !foo !1 @@ -388,7 +388,7 @@ define <2 x float> @test_sqrt_v2f32_preserve_flags_md(<2 x float> %arg) { define float @test_sqrt_cr_f32_preserve_flags(float %arg) { ; CHECK-LABEL: define float @test_sqrt_cr_f32_preserve_flags ; CHECK-SAME: (float [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call ninf contract float @_Z4sqrtf(float [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call ninf contract float @llvm.sqrt.f32(float [[ARG]]) ; CHECK-NEXT: ret float [[SQRT]] ; %sqrt = tail call ninf contract float @_Z4sqrtf(float %arg) @@ -398,7 +398,7 @@ define float @test_sqrt_cr_f32_preserve_flags(float %arg) { define <2 x float> @test_sqrt_cr_v2f32_preserve_flags(<2 x float> %arg) { ; CHECK-LABEL: define <2 x float> @test_sqrt_cr_v2f32_preserve_flags ; CHECK-SAME: (<2 x float> [[ARG:%.*]]) { -; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan nsz <2 x float> @_Z4sqrtDv2_f(<2 x float> [[ARG]]) +; CHECK-NEXT: [[SQRT:%.*]] = tail call nnan nsz <2 x float> @llvm.sqrt.v2f32(<2 x float> [[ARG]]) ; CHECK-NEXT: ret <2 x float> [[SQRT]] ; %sqrt = tail call nnan nsz <2 x float> @_Z4sqrtDv2_f(<2 x float> %arg) diff --git a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll index 87f69065c9fd..731a88278e51 100644 --- a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll +++ b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll @@ -694,7 +694,7 @@ entry: } ; GCN-LABEL: {{^}}define amdgpu_kernel void @test_use_native_sqrt -; GCN-NATIVE: call fast float @_Z11native_sqrtf(float %tmp) +; GCN-NATIVE: call fast float @llvm.sqrt.f32(float %tmp) define amdgpu_kernel void @test_use_native_sqrt(ptr addrspace(1) nocapture %a) { entry: %tmp = load float, ptr addrspace(1) %a, align 4 @@ -704,7 +704,7 @@ entry: } ; GCN-LABEL: {{^}}define amdgpu_kernel void @test_dont_use_native_sqrt_fast_f64 -; GCN: call fast double @_Z4sqrtd(double %tmp) +; GCN: call fast double @llvm.sqrt.f64(double %tmp) define amdgpu_kernel void @test_dont_use_native_sqrt_fast_f64(ptr addrspace(1) nocapture %a) { entry: %tmp = load double, ptr addrspace(1) %a, align 8 @@ -836,7 +836,6 @@ entry: } ; GCN-PRELINK: declare float @_Z4cbrtf(float) local_unnamed_addr #[[$NOUNWIND_READONLY:[0-9]+]] -; GCN-PRELINK: declare float @_Z11native_sqrtf(float) local_unnamed_addr #[[$NOUNWIND_READONLY]] ; GCN-PRELINK-DAG: attributes #[[$NOUNWIND]] = { nounwind } ; GCN-PRELINK-DAG: attributes #[[$NOUNWIND_READONLY]] = { nofree nounwind memory(read) } -- GitLab From c6bb89f308c6715edf3f35fb7c6257713ecfc614 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 9 Jan 2024 09:18:07 +0100 Subject: [PATCH 163/652] [clang] Fix assertion failure when initializing union with FAM (#77298) When initializing a union that constrain a struct with a flexible array member, and the initializer list is empty, we currently trigger an assertion failure. This happens because getFlexibleArrayInitChars() assumes that the initializer list is non-empty. Fixes https://github.com/llvm/llvm-project/issues/77085. --- clang/docs/ReleaseNotes.rst | 3 +++ clang/lib/AST/Decl.cpp | 2 +- clang/test/CodeGen/flexible-array-init.c | 8 ++++++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 803eb2f7c74c..980be4fe0ef7 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -696,6 +696,9 @@ Bug Fixes in This Version - Clang now accepts recursive non-dependent calls to functions with deduced return type. Fixes (`#71015 `_) +- Fix assertion failure when initializing union containing struct with + flexible array member using empty initializer list. + Fixes (`#77085 `_) Bug Fixes to Compiler Builtins diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp index 12e0a6faa4c3..e1440e5183a4 100644 --- a/clang/lib/AST/Decl.cpp +++ b/clang/lib/AST/Decl.cpp @@ -2835,7 +2835,7 @@ CharUnits VarDecl::getFlexibleArrayInitChars(const ASTContext &Ctx) const { if (!Ty || !Ty->getDecl()->hasFlexibleArrayMember()) return CharUnits::Zero(); auto *List = dyn_cast(getInit()->IgnoreParens()); - if (!List) + if (!List || List->getNumInits() == 0) return CharUnits::Zero(); const Expr *FlexibleInit = List->getInit(List->getNumInits() - 1); auto InitTy = Ctx.getAsConstantArrayType(FlexibleInit->getType()); diff --git a/clang/test/CodeGen/flexible-array-init.c b/clang/test/CodeGen/flexible-array-init.c index b2cf959f7e12..bae926da5feb 100644 --- a/clang/test/CodeGen/flexible-array-init.c +++ b/clang/test/CodeGen/flexible-array-init.c @@ -20,3 +20,11 @@ struct __attribute((packed, aligned(4))) { char a; int x; char z[]; } e = { 1, 2 struct { int x; char y[]; } f = { 1, { 13, 15 } }; // CHECK: @f ={{.*}} global <{ i32, [2 x i8] }> <{ i32 1, [2 x i8] c"\0D\0F" }> + +union { + struct { + int a; + char b[]; + } x; +} in_union = {}; +// CHECK: @in_union ={{.*}} global %union.anon zeroinitializer -- GitLab From 4cb1d914ff7b36be06137a8357da0afbf8d628c9 Mon Sep 17 00:00:00 2001 From: jeanPerier Date: Tue, 9 Jan 2024 09:28:44 +0100 Subject: [PATCH 164/652] [flang] add folding support for quad bessels (#77314) This is done using libquadmath and the mappings are only available if libquadmath was found by cmake. Support for non quad bessels is already available on POSIX platform using libm extensions. --- flang/lib/Evaluate/intrinsics-library.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/flang/lib/Evaluate/intrinsics-library.cpp b/flang/lib/Evaluate/intrinsics-library.cpp index 892b8d0b6a06..e68c5ed3f6a8 100644 --- a/flang/lib/Evaluate/intrinsics-library.cpp +++ b/flang/lib/Evaluate/intrinsics-library.cpp @@ -321,6 +321,7 @@ template <> struct HostRuntimeLibrary { template <> struct HostRuntimeLibrary<__float128, LibraryVersion::Libm> { using F = FuncPointer<__float128, __float128>; using F2 = FuncPointer<__float128, __float128, __float128>; + using FN = FuncPointer<__float128, int, __float128>; static constexpr HostRuntimeFunction table[]{ FolderFactory::Create("acos"), FolderFactory::Create("acosh"), @@ -329,6 +330,12 @@ template <> struct HostRuntimeLibrary<__float128, LibraryVersion::Libm> { FolderFactory::Create("atan"), FolderFactory::Create("atan2"), FolderFactory::Create("atanh"), + FolderFactory::Create("bessel_j0"), + FolderFactory::Create("bessel_j1"), + FolderFactory::Create("bessel_jn"), + FolderFactory::Create("bessel_y0"), + FolderFactory::Create("bessel_y1"), + FolderFactory::Create("bessel_yn"), FolderFactory::Create("cos"), FolderFactory::Create("cosh"), FolderFactory::Create("erf"), -- GitLab From 2357e899cb11e05312c54b689ebd0355487be6bc Mon Sep 17 00:00:00 2001 From: avl-llvm <55248412+avl-llvm@users.noreply.github.com> Date: Tue, 9 Jan 2024 11:32:08 +0300 Subject: [PATCH 165/652] [DWARFLinker][DWARFLinkerParallel][NFC] Refactor DWARFLinker&DWARFLinkerParallel to have a common library. Part 1. (#75925) This patch creates DWARFLinkerBase library, places DWARFLinker code into DWARFLinker\Classic, places DWARFLinkerParallel into DWARFLinker\Parallel. updates BOLT to use new library. This patch is NFC. --- bolt/lib/Rewrite/CMakeLists.txt | 1 + bolt/lib/Rewrite/DWARFRewriter.cpp | 11 +- .../AddressesMap.h | 10 +- .../DWARFLinker/{ => Classic}/DWARFLinker.h | 216 +++++------------- .../{ => Classic}/DWARFLinkerCompileUnit.h | 12 +- .../{ => Classic}/DWARFLinkerDeclContext.h | 12 +- .../DWARFLinker/{ => Classic}/DWARFStreamer.h | 28 ++- .../DWARFFile.h | 17 +- .../llvm/DWARFLinker/DWARFLinkerBase.h | 100 ++++++++ .../Parallel}/DWARFLinker.h | 108 +-------- .../StringPool.h | 25 +- .../llvm/DebugInfo/DWARF/DWARFDebugMacro.h | 9 +- llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h | 6 +- llvm/lib/CMakeLists.txt | 1 - llvm/lib/DWARFLinker/CMakeLists.txt | 15 +- llvm/lib/DWARFLinker/Classic/CMakeLists.txt | 24 ++ .../DWARFLinker/{ => Classic}/DWARFLinker.cpp | 66 +++--- .../{ => Classic}/DWARFLinkerCompileUnit.cpp | 7 +- .../{ => Classic}/DWARFLinkerDeclContext.cpp | 7 +- .../{ => Classic}/DWARFStreamer.cpp | 10 +- .../Parallel}/AcceleratorRecordsSaver.cpp | 8 +- .../Parallel}/AcceleratorRecordsSaver.h | 14 +- .../Parallel}/ArrayList.h | 18 +- .../Parallel}/CMakeLists.txt | 3 +- .../Parallel}/DIEAttributeCloner.cpp | 8 +- .../Parallel}/DIEAttributeCloner.h | 14 +- .../Parallel}/DIEGenerator.h | 14 +- .../Parallel}/DWARFEmitterImpl.cpp | 10 +- .../Parallel}/DWARFEmitterImpl.h | 16 +- .../Parallel}/DWARFLinker.cpp | 12 +- .../Parallel}/DWARFLinkerCompileUnit.cpp | 5 +- .../Parallel}/DWARFLinkerCompileUnit.h | 16 +- .../Parallel}/DWARFLinkerGlobalData.h | 24 +- .../Parallel}/DWARFLinkerImpl.cpp | 207 ++++++++--------- .../Parallel}/DWARFLinkerImpl.h | 20 +- .../Parallel}/DWARFLinkerTypeUnit.cpp | 7 +- .../Parallel}/DWARFLinkerTypeUnit.h | 14 +- .../Parallel}/DWARFLinkerUnit.cpp | 8 +- .../Parallel}/DWARFLinkerUnit.h | 18 +- .../Parallel}/DebugLineSectionEmitter.h | 18 +- .../Parallel}/DependencyTracker.cpp | 8 +- .../Parallel}/DependencyTracker.h | 14 +- .../Parallel}/IndexedValuesMap.h | 14 +- .../Parallel}/OutputSections.cpp | 23 +- .../Parallel}/OutputSections.h | 32 ++- .../StringEntryToDwarfStringPoolEntryMap.h | 16 +- .../Parallel}/SyntheticTypeNameBuilder.cpp | 8 +- .../Parallel}/SyntheticTypeNameBuilder.h | 14 +- .../Parallel}/TypePool.h | 35 +-- .../Parallel}/Utils.h | 14 +- .../StringPool.cpp => DWARFLinker/Utils.cpp} | 4 +- llvm/lib/DWARFLinkerParallel/DWARFFile.cpp | 17 -- llvm/tools/dsymutil/CMakeLists.txt | 1 + llvm/tools/dsymutil/DwarfLinkerForBinary.cpp | 161 +++++-------- llvm/tools/dsymutil/DwarfLinkerForBinary.h | 26 +-- llvm/tools/dsymutil/LinkUtils.h | 7 +- llvm/tools/dsymutil/dsymutil.cpp | 3 +- llvm/tools/llvm-dwarfutil/CMakeLists.txt | 1 + llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp | 32 ++- .../DWARFLinkerParallel/StringPoolTest.cpp | 4 +- 60 files changed, 742 insertions(+), 831 deletions(-) rename llvm/include/llvm/{DWARFLinkerParallel => DWARFLinker}/AddressesMap.h (97%) rename llvm/include/llvm/DWARFLinker/{ => Classic}/DWARFLinker.h (81%) rename llvm/include/llvm/DWARFLinker/{ => Classic}/DWARFLinkerCompileUnit.h (97%) rename llvm/include/llvm/DWARFLinker/{ => Classic}/DWARFLinkerDeclContext.h (95%) rename llvm/include/llvm/DWARFLinker/{ => Classic}/DWARFStreamer.h (95%) rename llvm/include/llvm/{DWARFLinkerParallel => DWARFLinker}/DWARFFile.h (79%) create mode 100644 llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h rename llvm/include/llvm/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinker.h (58%) rename llvm/include/llvm/{DWARFLinkerParallel => DWARFLinker}/StringPool.h (75%) create mode 100644 llvm/lib/DWARFLinker/Classic/CMakeLists.txt rename llvm/lib/DWARFLinker/{ => Classic}/DWARFLinker.cpp (98%) rename llvm/lib/DWARFLinker/{ => Classic}/DWARFLinkerCompileUnit.cpp (97%) rename llvm/lib/DWARFLinker/{ => Classic}/DWARFLinkerDeclContext.cpp (97%) rename llvm/lib/DWARFLinker/{ => Classic}/DWARFStreamer.cpp (99%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/AcceleratorRecordsSaver.cpp (98%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/AcceleratorRecordsSaver.h (88%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/ArrayList.h (91%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/CMakeLists.txt (94%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DIEAttributeCloner.cpp (99%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DIEAttributeCloner.h (95%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DIEGenerator.h (95%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFEmitterImpl.cpp (98%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFEmitterImpl.h (93%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinker.cpp (65%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerCompileUnit.cpp (99%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerCompileUnit.h (98%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerGlobalData.h (88%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerImpl.cpp (91%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerImpl.h (96%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerTypeUnit.cpp (99%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerTypeUnit.h (93%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerUnit.cpp (98%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DWARFLinkerUnit.h (94%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DebugLineSectionEmitter.h (97%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DependencyTracker.cpp (99%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/DependencyTracker.h (96%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/IndexedValuesMap.h (78%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/OutputSections.cpp (95%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/OutputSections.h (94%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/StringEntryToDwarfStringPoolEntryMap.h (84%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/SyntheticTypeNameBuilder.cpp (99%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/SyntheticTypeNameBuilder.h (94%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/TypePool.h (84%) rename llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/Utils.h (81%) rename llvm/lib/{DWARFLinkerParallel/StringPool.cpp => DWARFLinker/Utils.cpp} (68%) delete mode 100644 llvm/lib/DWARFLinkerParallel/DWARFFile.cpp diff --git a/bolt/lib/Rewrite/CMakeLists.txt b/bolt/lib/Rewrite/CMakeLists.txt index b0e2b7f46bef..fb21c13c654b 100644 --- a/bolt/lib/Rewrite/CMakeLists.txt +++ b/bolt/lib/Rewrite/CMakeLists.txt @@ -5,6 +5,7 @@ set(LLVM_LINK_COMPONENTS MC Object Support + DWARFLinkerBase DWARFLinker AsmPrinter TargetParser diff --git a/bolt/lib/Rewrite/DWARFRewriter.cpp b/bolt/lib/Rewrite/DWARFRewriter.cpp index 05fb3e8fafe2..8e20306925fe 100644 --- a/bolt/lib/Rewrite/DWARFRewriter.cpp +++ b/bolt/lib/Rewrite/DWARFRewriter.cpp @@ -21,7 +21,7 @@ #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DIE.h" -#include "llvm/DWARFLinker/DWARFStreamer.h" +#include "llvm/DWARFLinker/Classic/DWARFStreamer.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFDebugAbbrev.h" #include "llvm/DebugInfo/DWARF/DWARFDebugLoc.h" @@ -178,6 +178,9 @@ translateInputToOutputLocationList(const BinaryFunction &BF, return MergedLL; } +using namespace dwarf_linker; +using namespace dwarf_linker::classic; + namespace llvm { namespace bolt { /// Emits debug information into .debug_info or .debug_types section. @@ -278,10 +281,10 @@ private: public: DIEStreamer(DIEBuilder *DIEBldr, DWARFRewriter &Rewriter, - DWARFLinker::OutputFileType OutFileType, + DWARFLinkerBase::OutputFileType OutFileType, raw_pwrite_stream &OutFile, std::function Translator, - DWARFLinker::messageHandler Warning) + DWARFLinkerBase::MessageHandlerTy Warning) : DwarfStreamer(OutFileType, OutFile, Translator, Warning), DIEBldr(DIEBldr), Rewriter(Rewriter){}; @@ -457,7 +460,7 @@ createDIEStreamer(const Triple &TheTriple, raw_pwrite_stream &OutFile, DWARFRewriter &Rewriter) { std::unique_ptr Streamer = std::make_unique( - &DIEBldr, Rewriter, llvm::DWARFLinker::OutputFileType::Object, OutFile, + &DIEBldr, Rewriter, DWARFLinkerBase::OutputFileType::Object, OutFile, [](StringRef Input) -> StringRef { return Input; }, [&](const Twine &Warning, StringRef Context, const DWARFDie *) {}); Error Err = Streamer->init(TheTriple, Swift5ReflectionSegmentName); diff --git a/llvm/include/llvm/DWARFLinkerParallel/AddressesMap.h b/llvm/include/llvm/DWARFLinker/AddressesMap.h similarity index 97% rename from llvm/include/llvm/DWARFLinkerParallel/AddressesMap.h rename to llvm/include/llvm/DWARFLinker/AddressesMap.h index b451fee4e0b7..d8b3b4407471 100644 --- a/llvm/include/llvm/DWARFLinkerParallel/AddressesMap.h +++ b/llvm/include/llvm/DWARFLinker/AddressesMap.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKERPARALLEL_ADDRESSESMAP_H -#define LLVM_DWARFLINKERPARALLEL_ADDRESSESMAP_H +#ifndef LLVM_DWARFLINKER_ADDRESSESMAP_H +#define LLVM_DWARFLINKER_ADDRESSESMAP_H #include "llvm/ADT/AddressRanges.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" @@ -17,7 +17,7 @@ #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { /// Mapped value in the address map is the offset to apply to the /// linked address. @@ -186,7 +186,7 @@ protected: } }; -} // end of namespace dwarflinker_parallel +} // namespace dwarf_linker } // end namespace llvm -#endif // LLVM_DWARFLINKERPARALLEL_ADDRESSESMAP_H +#endif // LLVM_DWARFLINKER_ADDRESSESMAP_H diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinker.h b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h similarity index 81% rename from llvm/include/llvm/DWARFLinker/DWARFLinker.h rename to llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h index 2bd85e30d3b1..d3aaa3baadc4 100644 --- a/llvm/include/llvm/DWARFLinker/DWARFLinker.h +++ b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h @@ -6,14 +6,15 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKER_DWARFLINKER_H -#define LLVM_DWARFLINKER_DWARFLINKER_H +#ifndef LLVM_DWARFLINKER_CLASSIC_DWARFLINKER_H +#define LLVM_DWARFLINKER_CLASSIC_DWARFLINKER_H #include "llvm/ADT/AddressRanges.h" #include "llvm/ADT/DenseMap.h" #include "llvm/CodeGen/AccelTable.h" #include "llvm/CodeGen/NonRelocatableStringpool.h" -#include "llvm/DWARFLinker/DWARFLinkerCompileUnit.h" +#include "llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h" +#include "llvm/DWARFLinker/DWARFLinkerBase.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFDebugLine.h" #include "llvm/DebugInfo/DWARF/DWARFDebugRangeList.h" @@ -25,73 +26,11 @@ namespace llvm { class DWARFExpression; class DWARFUnit; class DataExtractor; -class DeclContextTree; template class SmallVectorImpl; -enum class DwarfLinkerClient { Dsymutil, LLD, General }; - -/// AddressesMap represents information about valid addresses used -/// by debug information. Valid addresses are those which points to -/// live code sections. i.e. relocations for these addresses point -/// into sections which would be/are placed into resulting binary. -class AddressesMap { -public: - virtual ~AddressesMap(); - - /// Checks that there are valid relocations against a .debug_info - /// section. - virtual bool hasValidRelocs() = 0; - - /// Checks that the specified DWARF expression operand \p Op references live - /// code section and returns the relocation adjustment value (to get the - /// linked address this value might be added to the source expression operand - /// address). - /// \returns relocation adjustment value or std::nullopt if there is no - /// corresponding live address. - virtual std::optional - getExprOpAddressRelocAdjustment(DWARFUnit &U, - const DWARFExpression::Operation &Op, - uint64_t StartOffset, uint64_t EndOffset) = 0; - - /// Checks that the specified subprogram \p DIE references the live code - /// section and returns the relocation adjustment value (to get the linked - /// address this value might be added to the source subprogram address). - /// Allowed kinds of input DIE: DW_TAG_subprogram, DW_TAG_label. - /// \returns relocation adjustment value or std::nullopt if there is no - /// corresponding live address. - virtual std::optional - getSubprogramRelocAdjustment(const DWARFDie &DIE) = 0; - - /// Returns the file name associated to the AddessesMap - virtual std::optional getLibraryInstallName() = 0; - - /// Apply the valid relocations to the buffer \p Data, taking into - /// account that Data is at \p BaseOffset in the .debug_info section. - /// - /// \returns true whether any reloc has been applied. - virtual bool applyValidRelocs(MutableArrayRef Data, uint64_t BaseOffset, - bool IsLittleEndian) = 0; - - /// Check if the linker needs to gather and save relocation info. - virtual bool needToSaveValidRelocs() = 0; - - /// Update and save original relocations located in between StartOffset and - /// EndOffset. LinkedOffset is the value which should be added to the original - /// relocation offset to get new relocation offset in linked binary. - virtual void updateAndSaveValidRelocs(bool IsDWARF5, - uint64_t OriginalUnitOffset, - int64_t LinkedOffset, - uint64_t StartOffset, - uint64_t EndOffset) = 0; - - /// Update the valid relocations that used OriginalUnitOffset as the compile - /// unit offset, and update their values to reflect OutputUnitOffset. - virtual void updateRelocationsWithUnitOffset(uint64_t OriginalUnitOffset, - uint64_t OutputUnitOffset) = 0; - - /// Erases all data. - virtual void clear() = 0; -}; +namespace dwarf_linker { +namespace classic { +class DeclContextTree; using Offset2UnitMap = DenseMap; @@ -117,7 +56,7 @@ struct DebugDieValuePool { /// DwarfEmitter presents interface to generate all debug info tables. class DwarfEmitter { public: - virtual ~DwarfEmitter(); + virtual ~DwarfEmitter() = default; /// Emit section named SecName with data SecData. virtual void emitSectionContents(StringRef SecData, StringRef SecName) = 0; @@ -282,44 +221,6 @@ public: class DwarfStreamer; using UnitListTy = std::vector>; -/// This class represents DWARF information for source file -/// and its address map. -class DWARFFile { -public: - using UnloadCallbackTy = std::function; - DWARFFile(StringRef Name, std::unique_ptr Dwarf, - std::unique_ptr Addresses, - UnloadCallbackTy UnloadFunc = nullptr) - : FileName(Name), Dwarf(std::move(Dwarf)), - Addresses(std::move(Addresses)), UnloadFunc(UnloadFunc) {} - - /// The object file name. - StringRef FileName; - - /// The source DWARF information. - std::unique_ptr Dwarf; - - /// Helpful address information(list of valid address ranges, relocations). - std::unique_ptr Addresses; - - /// Callback to the module keeping object file to unload. - UnloadCallbackTy UnloadFunc; - - /// Unloads object file and corresponding AddressesMap and Dwarf Context. - void unload() { - Addresses.reset(); - Dwarf.reset(); - - if (UnloadFunc) - UnloadFunc(FileName); - } -}; - -typedef std::map swiftInterfacesMap; -typedef std::map objectPrefixMap; - -typedef function_ref CompileUnitHandler; - /// The core of the Dwarf linking logic. /// /// The generation of the dwarf information from the object files will be @@ -334,41 +235,20 @@ typedef function_ref CompileUnitHandler; /// a variable). These relocations are called ValidRelocs in the /// AddressesInfo and are gathered as a very first step when we start /// processing a object file. -class DWARFLinker { +class DWARFLinker : public DWARFLinkerBase { public: - typedef std::function - messageHandler; - DWARFLinker(messageHandler ErrorHandler, messageHandler WarningHandler, + DWARFLinker(MessageHandlerTy ErrorHandler, MessageHandlerTy WarningHandler, std::function StringsTranslator) - : DwarfLinkerClientID(DwarfLinkerClient::Dsymutil), - StringsTranslator(StringsTranslator), ErrorHandler(ErrorHandler), + : StringsTranslator(StringsTranslator), ErrorHandler(ErrorHandler), WarningHandler(WarningHandler) {} static std::unique_ptr createLinker( - messageHandler ErrorHandler, messageHandler WarningHandler, + MessageHandlerTy ErrorHandler, MessageHandlerTy WarningHandler, std::function StringsTranslator = nullptr) { return std::make_unique(ErrorHandler, WarningHandler, StringsTranslator); } - /// Type of output file. - enum class OutputFileType { - Object, - Assembly, - }; - - /// The kind of accelerator tables we should emit. - enum class AccelTableKind : uint8_t { - Apple, ///< .apple_names, .apple_namespaces, .apple_types, .apple_objc. - Pub, ///< .debug_pubnames, .debug_pubtypes - DebugNames ///< .debug_names. - }; - typedef std::function inputVerificationHandler; - typedef std::function(StringRef ContainerName, - StringRef Path)> - objFileLoader; - Error createEmitter(const Triple &TheTriple, OutputFileType FileType, raw_pwrite_stream &OutFile); @@ -381,73 +261,82 @@ public: /// /// \pre NoODR, Update options should be set before call to addObjectFile. void addObjectFile( - DWARFFile &File, objFileLoader Loader = nullptr, - CompileUnitHandler OnCUDieLoaded = [](const DWARFUnit &) {}); + DWARFFile &File, ObjFileLoaderTy Loader = nullptr, + CompileUnitHandlerTy OnCUDieLoaded = [](const DWARFUnit &) {}) override; /// Link debug info for added objFiles. Object files are linked all together. - Error link(); + Error link() override; /// A number of methods setting various linking options: /// Allows to generate log of linking process to the standard output. - void setVerbosity(bool Verbose) { Options.Verbose = Verbose; } + void setVerbosity(bool Verbose) override { Options.Verbose = Verbose; } /// Print statistics to standard output. - void setStatistics(bool Statistics) { Options.Statistics = Statistics; } + void setStatistics(bool Statistics) override { + Options.Statistics = Statistics; + } /// Verify the input DWARF. - void setVerifyInputDWARF(bool Verify) { Options.VerifyInputDWARF = Verify; } + void setVerifyInputDWARF(bool Verify) override { + Options.VerifyInputDWARF = Verify; + } /// Do not unique types according to ODR. - void setNoODR(bool NoODR) { Options.NoODR = NoODR; } + void setNoODR(bool NoODR) override { Options.NoODR = NoODR; } /// Update index tables only(do not modify rest of DWARF). - void setUpdateIndexTablesOnly(bool Update) { Options.Update = Update; } + void setUpdateIndexTablesOnly(bool Update) override { + Options.Update = Update; + } /// Allow generating valid, but non-deterministic output. - void setAllowNonDeterministicOutput(bool) { /* Nothing to do. */ + void setAllowNonDeterministicOutput(bool) override { /* Nothing to do. */ } /// Set whether to keep the enclosing function for a static variable. - void setKeepFunctionForStatic(bool KeepFunctionForStatic) { + void setKeepFunctionForStatic(bool KeepFunctionForStatic) override { Options.KeepFunctionForStatic = KeepFunctionForStatic; } /// Use specified number of threads for parallel files linking. - void setNumThreads(unsigned NumThreads) { Options.Threads = NumThreads; } + void setNumThreads(unsigned NumThreads) override { + Options.Threads = NumThreads; + } /// Add kind of accelerator tables to be generated. - void addAccelTableKind(AccelTableKind Kind) { + void addAccelTableKind(AccelTableKind Kind) override { assert(!llvm::is_contained(Options.AccelTables, Kind)); Options.AccelTables.emplace_back(Kind); } /// Set prepend path for clang modules. - void setPrependPath(const std::string &Ppath) { Options.PrependPath = Ppath; } + void setPrependPath(StringRef Ppath) override { Options.PrependPath = Ppath; } /// Set estimated objects files amount, for preliminary data allocation. - void setEstimatedObjfilesAmount(unsigned ObjFilesNum) { + void setEstimatedObjfilesAmount(unsigned ObjFilesNum) override { ObjectContexts.reserve(ObjFilesNum); } /// Set verification handler which would be used to report verification /// errors. - void setInputVerificationHandler(inputVerificationHandler Handler) { + void + setInputVerificationHandler(InputVerificationHandlerTy Handler) override { Options.InputVerificationHandler = Handler; } /// Set map for Swift interfaces. - void setSwiftInterfacesMap(swiftInterfacesMap *Map) { + void setSwiftInterfacesMap(SwiftInterfacesMapTy *Map) override { Options.ParseableSwiftInterfaces = Map; } /// Set prefix map for objects. - void setObjectPrefixMap(objectPrefixMap *Map) { + void setObjectPrefixMap(ObjectPrefixMapTy *Map) override { Options.ObjectPrefixMap = Map; } /// Set target DWARF version. - Error setTargetDWARFVersion(uint16_t TargetDWARFVersion) { + Error setTargetDWARFVersion(uint16_t TargetDWARFVersion) override { if ((TargetDWARFVersion < 1) || (TargetDWARFVersion > 5)) return createStringError(std::errc::invalid_argument, "unsupported DWARF version: %d", @@ -619,16 +508,17 @@ private: /// pointing to the module, and a DW_AT_gnu_dwo_id with the module /// hash. bool registerModuleReference(const DWARFDie &CUDie, LinkContext &Context, - objFileLoader Loader, - CompileUnitHandler OnCUDieLoaded, + ObjFileLoaderTy Loader, + CompileUnitHandlerTy OnCUDieLoaded, unsigned Indent = 0); /// Recursively add the debug info in this clang module .pcm /// file (and all the modules imported by it in a bottom-up fashion) /// to ModuleUnits. - Error loadClangModule(objFileLoader Loader, const DWARFDie &CUDie, + Error loadClangModule(ObjFileLoaderTy Loader, const DWARFDie &CUDie, const std::string &PCMFile, LinkContext &Context, - CompileUnitHandler OnCUDieLoaded, unsigned Indent = 0); + CompileUnitHandlerTy OnCUDieLoaded, + unsigned Indent = 0); /// Clone specified Clang module unit \p Unit. Error cloneModuleUnit(LinkContext &Context, RefModuleUnit &Unit, @@ -911,18 +801,16 @@ private: /// Mapping the PCM filename to the DwoId. StringMap ClangModules; - DwarfLinkerClient DwarfLinkerClientID; - std::function StringsTranslator = nullptr; /// A unique ID that identifies each compile unit. unsigned UniqueUnitID = 0; // error handler - messageHandler ErrorHandler = nullptr; + MessageHandlerTy ErrorHandler = nullptr; // warning handler - messageHandler WarningHandler = nullptr; + MessageHandlerTy WarningHandler = nullptr; /// linking options struct DWARFLinkerOptions { @@ -958,20 +846,22 @@ private: std::string PrependPath; // input verification handler - inputVerificationHandler InputVerificationHandler = nullptr; + InputVerificationHandlerTy InputVerificationHandler = nullptr; /// A list of all .swiftinterface files referenced by the debug /// info, mapping Module name to path on disk. The entries need to /// be uniqued and sorted and there are only few entries expected /// per compile unit, which is why this is a std::map. /// this is dsymutil specific fag. - swiftInterfacesMap *ParseableSwiftInterfaces = nullptr; + SwiftInterfacesMapTy *ParseableSwiftInterfaces = nullptr; /// A list of remappings to apply to file paths. - objectPrefixMap *ObjectPrefixMap = nullptr; + ObjectPrefixMapTy *ObjectPrefixMap = nullptr; } Options; }; -} // end namespace llvm +} // end of namespace classic +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_DWARFLINKER_DWARFLINKER_H +#endif // LLVM_DWARFLINKER_CLASSIC_DWARFLINKER_H diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinkerCompileUnit.h b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h similarity index 97% rename from llvm/include/llvm/DWARFLinker/DWARFLinkerCompileUnit.h rename to llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h index 08ebd4bc70bc..bfe544946fd9 100644 --- a/llvm/include/llvm/DWARFLinker/DWARFLinkerCompileUnit.h +++ b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKER_DWARFLINKERCOMPILEUNIT_H -#define LLVM_DWARFLINKER_DWARFLINKERCOMPILEUNIT_H +#ifndef LLVM_DWARFLINKER_CLASSIC_DWARFLINKERCOMPILEUNIT_H +#define LLVM_DWARFLINKER_CLASSIC_DWARFLINKERCOMPILEUNIT_H #include "llvm/ADT/AddressRanges.h" #include "llvm/ADT/DenseMap.h" @@ -16,6 +16,8 @@ #include namespace llvm { +namespace dwarf_linker { +namespace classic { class DeclContext; @@ -327,6 +329,8 @@ private: std::string ClangModuleName; }; -} // end namespace llvm +} // end of namespace classic +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_DWARFLINKER_DWARFLINKERCOMPILEUNIT_H +#endif // LLVM_DWARFLINKER_CLASSIC_DWARFLINKERCOMPILEUNIT_H diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinkerDeclContext.h b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h similarity index 95% rename from llvm/include/llvm/DWARFLinker/DWARFLinkerDeclContext.h rename to llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h index fb02b0fc1b4d..b00f68c3be84 100644 --- a/llvm/include/llvm/DWARFLinker/DWARFLinkerDeclContext.h +++ b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKER_DWARFLINKERDECLCONTEXT_H -#define LLVM_DWARFLINKER_DWARFLINKERDECLCONTEXT_H +#ifndef LLVM_DWARFLINKER_CLASSIC_DWARFLINKERDECLCONTEXT_H +#define LLVM_DWARFLINKER_CLASSIC_DWARFLINKERDECLCONTEXT_H #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMapInfo.h" @@ -21,6 +21,8 @@ #include namespace llvm { +namespace dwarf_linker { +namespace classic { class CompileUnit; struct DeclMapInfo; @@ -184,6 +186,8 @@ struct DeclMapInfo : private DenseMapInfo { } }; -} // end namespace llvm +} // end of namespace classic +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_DWARFLINKER_DWARFLINKERDECLCONTEXT_H +#endif // LLVM_DWARFLINKER_CLASSIC_DWARFLINKERDECLCONTEXT_H diff --git a/llvm/include/llvm/DWARFLinker/DWARFStreamer.h b/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h similarity index 95% rename from llvm/include/llvm/DWARFLinker/DWARFStreamer.h rename to llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h index 18eb7277bfa2..f010c348f121 100644 --- a/llvm/include/llvm/DWARFLinker/DWARFStreamer.h +++ b/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKER_DWARFSTREAMER_H -#define LLVM_DWARFLINKER_DWARFSTREAMER_H +#ifndef LLVM_DWARFLINKER_CLASSIC_DWARFSTREAMER_H +#define LLVM_DWARFLINKER_CLASSIC_DWARFSTREAMER_H +#include "DWARFLinker.h" #include "llvm/BinaryFormat/Swift.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/DWARFLinker/DWARFLinker.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInstrInfo.h" @@ -23,6 +23,12 @@ namespace llvm { template class AccelTable; +class MCCodeEmitter; +class DWARFDebugMacro; + +namespace dwarf_linker { +namespace classic { + /// User of DwarfStreamer should call initialization code /// for AsmPrinter: /// @@ -31,21 +37,19 @@ template class AccelTable; /// InitializeAllTargets(); /// InitializeAllAsmPrinters(); -class MCCodeEmitter; -class DWARFDebugMacro; - /// The Dwarf streaming logic. /// /// All interactions with the MC layer that is used to build the debug /// information binary representation are handled in this class. class DwarfStreamer : public DwarfEmitter { public: - DwarfStreamer(DWARFLinker::OutputFileType OutFileType, + DwarfStreamer(DWARFLinkerBase::OutputFileType OutFileType, raw_pwrite_stream &OutFile, std::function Translator, - DWARFLinker::messageHandler Warning) + DWARFLinkerBase::MessageHandlerTy Warning) : OutFile(OutFile), OutFileType(OutFileType), Translator(Translator), WarningHandler(Warning) {} + virtual ~DwarfStreamer() = default; Error init(Triple TheTriple, StringRef Swift5ReflectionSegmentName); @@ -310,9 +314,11 @@ private: const CompileUnit &Unit, const std::vector &Names); - DWARFLinker::messageHandler WarningHandler = nullptr; + DWARFLinkerBase::MessageHandlerTy WarningHandler = nullptr; }; -} // end namespace llvm +} // end of namespace classic +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_DWARFLINKER_DWARFSTREAMER_H +#endif // LLVM_DWARFLINKER_CLASSIC_DWARFSTREAMER_H diff --git a/llvm/include/llvm/DWARFLinkerParallel/DWARFFile.h b/llvm/include/llvm/DWARFLinker/DWARFFile.h similarity index 79% rename from llvm/include/llvm/DWARFLinkerParallel/DWARFFile.h rename to llvm/include/llvm/DWARFLinker/DWARFFile.h index c320530569bb..c1d0fd87c7d7 100644 --- a/llvm/include/llvm/DWARFLinkerParallel/DWARFFile.h +++ b/llvm/include/llvm/DWARFLinker/DWARFFile.h @@ -6,18 +6,17 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKERPARALLEL_DWARFFILE_H -#define LLVM_DWARFLINKERPARALLEL_DWARFFILE_H +#ifndef LLVM_DWARFLINKER_DWARFFILE_H +#define LLVM_DWARFLINKER_DWARFFILE_H +#include "AddressesMap.h" #include "llvm/ADT/StringRef.h" -#include "llvm/DWARFLinkerParallel/AddressesMap.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" -#include "llvm/Support/Endian.h" #include #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { /// This class represents DWARF information for source file /// and it's address map. @@ -29,7 +28,9 @@ public: DWARFFile(StringRef Name, std::unique_ptr Dwarf, std::unique_ptr Addresses, - UnloadCallbackTy UnloadFunc = nullptr); + UnloadCallbackTy UnloadFunc = nullptr) + : FileName(Name), Dwarf(std::move(Dwarf)), + Addresses(std::move(Addresses)), UnloadFunc(UnloadFunc) {} /// Object file name. StringRef FileName; @@ -53,7 +54,7 @@ public: } }; -} // end namespace dwarflinker_parallel +} // namespace dwarf_linker } // end namespace llvm -#endif // LLVM_DWARFLINKERPARALLEL_DWARFFILE_H +#endif // LLVM_DWARFLINKER_DWARFFILE_H diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h b/llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h new file mode 100644 index 000000000000..626fb53d90f9 --- /dev/null +++ b/llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h @@ -0,0 +1,100 @@ +//===- DWARFLinkerBase.h ----------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_DWARFLINKER_DWARFLINKERBASE_H +#define LLVM_DWARFLINKER_DWARFLINKERBASE_H +#include "AddressesMap.h" +#include "DWARFFile.h" +#include "llvm/ADT/AddressRanges.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/DebugInfo/DWARF/DWARFContext.h" +#include "llvm/DebugInfo/DWARF/DWARFDebugLine.h" +#include "llvm/DebugInfo/DWARF/DWARFDebugRangeList.h" +#include "llvm/DebugInfo/DWARF/DWARFDie.h" +#include "llvm/DebugInfo/DWARF/DWARFExpression.h" +#include +namespace llvm { +class DWARFUnit; + +namespace dwarf_linker { + +/// The base interface for DWARFLinker implementations. +class DWARFLinkerBase { +public: + virtual ~DWARFLinkerBase() = default; + using MessageHandlerTy = std::function; + using ObjFileLoaderTy = std::function( + StringRef ContainerName, StringRef Path)>; + using InputVerificationHandlerTy = + std::function; + using ObjectPrefixMapTy = std::map; + using CompileUnitHandlerTy = function_ref; + using TranslatorFuncTy = std::function; + using SwiftInterfacesMapTy = std::map; + /// Type of output file. + enum class OutputFileType : uint8_t { + Object, + Assembly, + }; + /// The kind of accelerator tables to be emitted. + enum class AccelTableKind : uint8_t { + Apple, ///< .apple_names, .apple_namespaces, .apple_types, .apple_objc. + Pub, ///< .debug_pubnames, .debug_pubtypes + DebugNames ///< .debug_names. + }; + /// Add an object file to be linked. Pre-load compile unit die. Call + /// \p OnCUDieLoaded for each compile unit die. If \p File has reference to + /// a Clang module and UpdateIndexTablesOnly == false then the module is be + /// pre-loaded by \p Loader. + /// + /// \pre a call to setNoODR(true) and/or setUpdateIndexTablesOnly(bool Update) + /// must be made when required. + virtual void addObjectFile( + DWARFFile &File, ObjFileLoaderTy Loader = nullptr, + CompileUnitHandlerTy OnCUDieLoaded = [](const DWARFUnit &) {}) = 0; + /// Link the debug info for all object files added through calls to + /// addObjectFile. + virtual Error link() = 0; + /// A number of methods setting various linking options: + /// Enable logging to standard output. + virtual void setVerbosity(bool Verbose) = 0; + /// Print statistics to standard output. + virtual void setStatistics(bool Statistics) = 0; + /// Verify the input DWARF. + virtual void setVerifyInputDWARF(bool Verify) = 0; + /// Do not unique types according to ODR. + virtual void setNoODR(bool NoODR) = 0; + /// Update index tables only (do not modify rest of DWARF). + virtual void setUpdateIndexTablesOnly(bool Update) = 0; + /// Allows generating non-deterministic output in exchange for more + /// parallelism. + virtual void setAllowNonDeterministicOutput(bool) = 0; + /// Set whether to keep the enclosing function for a static variable. + virtual void setKeepFunctionForStatic(bool KeepFunctionForStatic) = 0; + /// Use specified number of threads for parallel files linking. + virtual void setNumThreads(unsigned NumThreads) = 0; + /// Add kind of accelerator tables to be generated. + virtual void addAccelTableKind(AccelTableKind Kind) = 0; + /// Set prepend path for clang modules. + virtual void setPrependPath(StringRef Ppath) = 0; + /// Set estimated objects files amount, for preliminary data allocation. + virtual void setEstimatedObjfilesAmount(unsigned ObjFilesNum) = 0; + /// Set verification handler used to report verification errors. + virtual void + setInputVerificationHandler(InputVerificationHandlerTy Handler) = 0; + /// Set map for Swift interfaces. + virtual void setSwiftInterfacesMap(SwiftInterfacesMapTy *Map) = 0; + /// Set prefix map for objects. + virtual void setObjectPrefixMap(ObjectPrefixMapTy *Map) = 0; + /// Set target DWARF version. + virtual Error setTargetDWARFVersion(uint16_t TargetDWARFVersion) = 0; +}; +} // end namespace dwarf_linker +} // end namespace llvm +#endif // LLVM_DWARFLINKER_DWARFLINKERBASE_H diff --git a/llvm/include/llvm/DWARFLinkerParallel/DWARFLinker.h b/llvm/include/llvm/DWARFLinker/Parallel/DWARFLinker.h similarity index 58% rename from llvm/include/llvm/DWARFLinkerParallel/DWARFLinker.h rename to llvm/include/llvm/DWARFLinker/Parallel/DWARFLinker.h index c16c94d65c2f..c38a9906940e 100644 --- a/llvm/include/llvm/DWARFLinkerParallel/DWARFLinker.h +++ b/llvm/include/llvm/DWARFLinker/Parallel/DWARFLinker.h @@ -6,11 +6,12 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKERPARALLEL_DWARFLINKER_H -#define LLVM_DWARFLINKERPARALLEL_DWARFLINKER_H +#ifndef LLVM_DWARFLINKER_PARALLEL_DWARFLINKER_H +#define LLVM_DWARFLINKER_PARALLEL_DWARFLINKER_H #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/DWARFLinkerParallel/DWARFFile.h" +#include "llvm/DWARFLinker/DWARFFile.h" +#include "llvm/DWARFLinker/DWARFLinkerBase.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFDie.h" #include "llvm/MC/MCDwarf.h" @@ -85,7 +86,8 @@ /// namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// ExtraDwarfEmitter allows adding extra data to the DWARFLinker output. /// The finish() method should be called after all extra data are emitted. @@ -111,31 +113,8 @@ public: virtual AsmPrinter &getAsmPrinter() const = 0; }; -class DWARFLinker { +class DWARFLinker : public DWARFLinkerBase { public: - /// Type of output file. - enum class OutputFileType { - Object, - Assembly, - }; - - /// The kind of accelerator tables we should emit. - enum class AccelTableKind : uint8_t { - Apple, ///< .apple_names, .apple_namespaces, .apple_types, .apple_objc. - Pub, ///< .debug_pubnames, .debug_pubtypes - DebugNames ///< .debug_names. - }; - - using MessageHandlerTy = std::function; - using ObjFileLoaderTy = std::function( - StringRef ContainerName, StringRef Path)>; - using InputVerificationHandlerTy = std::function; - using ObjectPrefixMapTy = std::map; - using CompileUnitHandlerTy = function_ref; - using TranslatorFuncTy = std::function; - using SwiftInterfacesMapTy = std::map; - virtual ~DWARFLinker() = default; /// Creates dwarf linker instance. @@ -149,75 +128,10 @@ public: /// Returns previously created dwarf emitter. May be nullptr. virtual ExtraDwarfEmitter *getEmitter() = 0; - - /// Add object file to be linked. Pre-load compile unit die. Call - /// \p OnCUDieLoaded for each compile unit die. If specified \p File - /// has reference to the Clang module then such module would be - /// pre-loaded by \p Loader for !Update case. - /// - /// \pre NoODR, Update options should be set before call to addObjectFile. - virtual void addObjectFile( - DWARFFile &File, ObjFileLoaderTy Loader = nullptr, - CompileUnitHandlerTy OnCUDieLoaded = [](const DWARFUnit &) {}) = 0; - - /// Link debug info for added files. - virtual Error link() = 0; - - /// \defgroup Methods setting various linking options: - /// - /// @{ - - /// Allows to generate log of linking process to the standard output. - virtual void setVerbosity(bool Verbose) = 0; - - /// Print statistics to standard output. - virtual void setStatistics(bool Statistics) = 0; - - /// Verify the input DWARF. - virtual void setVerifyInputDWARF(bool Verify) = 0; - - /// Do not unique types according to ODR. - virtual void setNoODR(bool NoODR) = 0; - - /// Update index tables only(do not modify rest of DWARF). - virtual void setUpdateIndexTablesOnly(bool UpdateIndexTablesOnly) = 0; - - /// Allow generating valid, but non-deterministic output. - virtual void - setAllowNonDeterministicOutput(bool AllowNonDeterministicOutput) = 0; - - /// Set to keep the enclosing function for a static variable. - virtual void setKeepFunctionForStatic(bool KeepFunctionForStatic) = 0; - - /// Use specified number of threads for parallel files linking. - virtual void setNumThreads(unsigned NumThreads) = 0; - - /// Add kind of accelerator tables to be generated. - virtual void addAccelTableKind(AccelTableKind Kind) = 0; - - /// Set prepend path for clang modules. - virtual void setPrependPath(const std::string &Ppath) = 0; - - /// Set estimated objects files amount, for preliminary data allocation. - virtual void setEstimatedObjfilesAmount(unsigned ObjFilesNum) = 0; - - /// Set verification handler which would be used to report verification - /// errors. - virtual void - setInputVerificationHandler(InputVerificationHandlerTy Handler) = 0; - - /// Set map for Swift interfaces. - virtual void setSwiftInterfacesMap(SwiftInterfacesMapTy *Map) = 0; - - /// Set prefix map for objects. - virtual void setObjectPrefixMap(ObjectPrefixMapTy *Map) = 0; - - /// Set target DWARF version. - virtual Error setTargetDWARFVersion(uint16_t TargetDWARFVersion) = 0; - /// @} }; -} // end namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_DWARFLINKERPARALLEL_DWARFLINKER_H +#endif // LLVM_DWARFLINKER_PARALLEL_DWARFLINKER_H diff --git a/llvm/include/llvm/DWARFLinkerParallel/StringPool.h b/llvm/include/llvm/DWARFLinker/StringPool.h similarity index 75% rename from llvm/include/llvm/DWARFLinkerParallel/StringPool.h rename to llvm/include/llvm/DWARFLinker/StringPool.h index e55909f34311..d0f4e211fac3 100644 --- a/llvm/include/llvm/DWARFLinkerParallel/StringPool.h +++ b/llvm/include/llvm/DWARFLinker/StringPool.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKERPARALLEL_STRINGPOOL_H -#define LLVM_DWARFLINKERPARALLEL_STRINGPOOL_H +#ifndef LLVM_DWARFLINKER_STRINGPOOL_H +#define LLVM_DWARFLINKER_STRINGPOOL_H #include "llvm/ADT/ConcurrentHashtable.h" #include "llvm/CodeGen/DwarfStringPoolEntry.h" @@ -16,7 +16,7 @@ #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { /// StringEntry keeps data of the string: the length, external offset /// and a string body which is placed right after StringEntry. @@ -41,35 +41,38 @@ public: /// \returns newly created object of KeyDataTy type. static inline StringEntry * - create(const StringRef &Key, parallel::PerThreadBumpPtrAllocator &Allocator) { + create(const StringRef &Key, + llvm::parallel::PerThreadBumpPtrAllocator &Allocator) { return StringEntry::create(Key, Allocator); } }; class StringPool : public ConcurrentHashTableByPtr { public: StringPool() : ConcurrentHashTableByPtr(Allocator) {} StringPool(size_t InitialSize) : ConcurrentHashTableByPtr(Allocator, InitialSize) {} - parallel::PerThreadBumpPtrAllocator &getAllocatorRef() { return Allocator; } + llvm::parallel::PerThreadBumpPtrAllocator &getAllocatorRef() { + return Allocator; + } void clear() { Allocator.Reset(); } private: - parallel::PerThreadBumpPtrAllocator Allocator; + llvm::parallel::PerThreadBumpPtrAllocator Allocator; }; -} // end of namespace dwarflinker_parallel +} // namespace dwarf_linker } // end namespace llvm -#endif // LLVM_DWARFLINKERPARALLEL_STRINGPOOL_H +#endif // LLVM_DWARFLINKER_STRINGPOOL_H diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugMacro.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugMacro.h index 6b1b2ae6d7e0..df862f60cb2f 100644 --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugMacro.h +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugMacro.h @@ -18,11 +18,16 @@ namespace llvm { class raw_ostream; + +namespace dwarf_linker { +namespace classic { class DwarfStreamer; +} +} // namespace dwarf_linker class DWARFDebugMacro { - friend DwarfStreamer; - friend dwarflinker_parallel::CompileUnit; + friend dwarf_linker::classic::DwarfStreamer; + friend dwarf_linker::parallel::CompileUnit; /// DWARFv5 section 6.3.1 Macro Information Header. enum HeaderFlagMask { diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h index 7084081ce61a..f20e71781f46 100644 --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h @@ -43,9 +43,11 @@ class DWARFObject; class raw_ostream; struct DIDumpOptions; struct DWARFSection; -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { class CompileUnit; } +} // namespace dwarf_linker /// Base class describing the header of any kind of "unit." Some information /// is specific to certain unit types. We separate this class out so we can @@ -256,7 +258,7 @@ class DWARFUnit { std::shared_ptr DWO; protected: - friend dwarflinker_parallel::CompileUnit; + friend dwarf_linker::parallel::CompileUnit; /// Return the index of a \p Die entry inside the unit's DIE vector. /// diff --git a/llvm/lib/CMakeLists.txt b/llvm/lib/CMakeLists.txt index 283baa6090eb..ea22ff21820a 100644 --- a/llvm/lib/CMakeLists.txt +++ b/llvm/lib/CMakeLists.txt @@ -14,7 +14,6 @@ add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) -add_subdirectory(DWARFLinkerParallel) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) diff --git a/llvm/lib/DWARFLinker/CMakeLists.txt b/llvm/lib/DWARFLinker/CMakeLists.txt index f720c5e844b3..73055a96d4a9 100644 --- a/llvm/lib/DWARFLinker/CMakeLists.txt +++ b/llvm/lib/DWARFLinker/CMakeLists.txt @@ -1,23 +1,18 @@ -add_llvm_component_library(LLVMDWARFLinker - DWARFLinkerCompileUnit.cpp - DWARFLinkerDeclContext.cpp - DWARFLinker.cpp - DWARFStreamer.cpp +add_llvm_component_library(LLVMDWARFLinkerBase + Utils.cpp ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/DWARFLinker - DEPENDS intrinsics_gen LINK_COMPONENTS - AsmPrinter BinaryFormat CodeGen - CodeGenTypes DebugInfoDWARF - MC Object Support - TargetParser ) + +add_subdirectory(Classic) +add_subdirectory(Parallel) diff --git a/llvm/lib/DWARFLinker/Classic/CMakeLists.txt b/llvm/lib/DWARFLinker/Classic/CMakeLists.txt new file mode 100644 index 000000000000..b173d42eb015 --- /dev/null +++ b/llvm/lib/DWARFLinker/Classic/CMakeLists.txt @@ -0,0 +1,24 @@ +add_llvm_component_library(LLVMDWARFLinker + DWARFLinkerCompileUnit.cpp + DWARFLinkerDeclContext.cpp + DWARFLinker.cpp + DWARFStreamer.cpp + + ADDITIONAL_HEADER_DIRS + ${LLVM_MAIN_INCLUDE_DIR}/llvm/DWARFLinker + + DEPENDS + intrinsics_gen + + LINK_COMPONENTS + AsmPrinter + BinaryFormat + CodeGen + CodeGenTypes + DebugInfoDWARF + DWARFLinkerBase + MC + Object + Support + TargetParser + ) diff --git a/llvm/lib/DWARFLinker/DWARFLinker.cpp b/llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp similarity index 98% rename from llvm/lib/DWARFLinker/DWARFLinker.cpp rename to llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp index 10967123a562..8d76c3bcf672 100644 --- a/llvm/lib/DWARFLinker/DWARFLinker.cpp +++ b/llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// -#include "llvm/DWARFLinker/DWARFLinker.h" +#include "llvm/DWARFLinker/Classic/DWARFLinker.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/CodeGen/NonRelocatableStringpool.h" -#include "llvm/DWARFLinker/DWARFLinkerDeclContext.h" -#include "llvm/DWARFLinker/DWARFStreamer.h" +#include "llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h" +#include "llvm/DWARFLinker/Classic/DWARFStreamer.h" #include "llvm/DebugInfo/DWARF/DWARFAbbreviationDeclaration.h" #include "llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" @@ -39,6 +39,9 @@ namespace llvm { +using namespace dwarf_linker; +using namespace dwarf_linker::classic; + /// Hold the input and output of the debug info size in bytes. struct DebugInfoSize { uint64_t Input; @@ -137,10 +140,6 @@ static bool isTypeTag(uint16_t Tag) { return false; } -AddressesMap::~AddressesMap() = default; - -DwarfEmitter::~DwarfEmitter() = default; - bool DWARFLinker::DIECloner::getDIENames(const DWARFDie &Die, AttributesInfo &Info, OffsetsStringPool &StringPool, @@ -195,7 +194,7 @@ static SmallString<128> guessToolchainBaseDir(StringRef SysRoot) { /// DW_TAG_module blocks. static void analyzeImportedModule( const DWARFDie &DIE, CompileUnit &CU, - swiftInterfacesMap *ParseableSwiftInterfaces, + DWARFLinkerBase::SwiftInterfacesMapTy *ParseableSwiftInterfaces, std::function ReportWarning) { if (CU.getLanguage() != dwarf::DW_LANG_Swift) return; @@ -307,7 +306,8 @@ static void updateChildPruning(const DWARFDie &Die, CompileUnit &CU, static void analyzeContextInfo( const DWARFDie &DIE, unsigned ParentIdx, CompileUnit &CU, DeclContext *CurrentDeclContext, DeclContextTree &Contexts, - uint64_t ModulesEndOffset, swiftInterfacesMap *ParseableSwiftInterfaces, + uint64_t ModulesEndOffset, + DWARFLinkerBase::SwiftInterfacesMapTy *ParseableSwiftInterfaces, std::function ReportWarning) { // LIFO work list. std::vector Worklist; @@ -1357,9 +1357,9 @@ unsigned DWARFLinker::DIECloner::cloneAddressAttribute( // independently by the linker). // - If address relocated in an inline_subprogram that happens at the // beginning of its inlining function. - // To avoid above cases and to not apply relocation twice (in applyValidRelocs - // and here), read address attribute from InputDIE and apply Info.PCOffset - // here. + // To avoid above cases and to not apply relocation twice (in + // applyValidRelocs and here), read address attribute from InputDIE and apply + // Info.PCOffset here. std::optional AddrAttribute = InputDIE.find(AttrSpec.Attr); if (!AddrAttribute) @@ -1411,7 +1411,7 @@ unsigned DWARFLinker::DIECloner::cloneScalarAttribute( // need to remove the attribute. if (AttrSpec.Attr == dwarf::DW_AT_macro_info) { if (std::optional Offset = Val.getAsSectionOffset()) { - const DWARFDebugMacro *Macro = File.Dwarf->getDebugMacinfo(); + const llvm::DWARFDebugMacro *Macro = File.Dwarf->getDebugMacinfo(); if (Macro == nullptr || !Macro->hasEntryForOffset(*Offset)) return 0; } @@ -1419,7 +1419,7 @@ unsigned DWARFLinker::DIECloner::cloneScalarAttribute( if (AttrSpec.Attr == dwarf::DW_AT_macros) { if (std::optional Offset = Val.getAsSectionOffset()) { - const DWARFDebugMacro *Macro = File.Dwarf->getDebugMacro(); + const llvm::DWARFDebugMacro *Macro = File.Dwarf->getDebugMacro(); if (Macro == nullptr || !Macro->hasEntryForOffset(*Offset)) return 0; } @@ -2040,8 +2040,7 @@ static void patchAddrBase(DIE &Die, DIEInteger Offset) { } void DWARFLinker::DIECloner::emitDebugAddrSection( - CompileUnit &Unit, - const uint16_t DwarfVersion) const { + CompileUnit &Unit, const uint16_t DwarfVersion) const { if (LLVM_UNLIKELY(Linker.Options.Update)) return; @@ -2407,8 +2406,9 @@ static uint64_t getDwoId(const DWARFDie &CUDie) { return 0; } -static std::string remapPath(StringRef Path, - const objectPrefixMap &ObjectPrefixMap) { +static std::string +remapPath(StringRef Path, + const DWARFLinkerBase::ObjectPrefixMapTy &ObjectPrefixMap) { if (ObjectPrefixMap.empty()) return Path.str(); @@ -2419,8 +2419,9 @@ static std::string remapPath(StringRef Path, return p.str().str(); } -static std::string getPCMFile(const DWARFDie &CUDie, - objectPrefixMap *ObjectPrefixMap) { +static std::string +getPCMFile(const DWARFDie &CUDie, + const DWARFLinkerBase::ObjectPrefixMapTy *ObjectPrefixMap) { std::string PCMFile = dwarf::toString( CUDie.find({dwarf::DW_AT_dwo_name, dwarf::DW_AT_GNU_dwo_name}), ""); @@ -2477,8 +2478,8 @@ std::pair DWARFLinker::isClangModuleRef(const DWARFDie &CUDie, bool DWARFLinker::registerModuleReference(const DWARFDie &CUDie, LinkContext &Context, - objFileLoader Loader, - CompileUnitHandler OnCUDieLoaded, + ObjFileLoaderTy Loader, + CompileUnitHandlerTy OnCUDieLoaded, unsigned Indent) { std::string PCMFile = getPCMFile(CUDie, Options.ObjectPrefixMap); std::pair IsClangModuleRef = @@ -2505,11 +2506,9 @@ bool DWARFLinker::registerModuleReference(const DWARFDie &CUDie, return true; } -Error DWARFLinker::loadClangModule(objFileLoader Loader, const DWARFDie &CUDie, - const std::string &PCMFile, - LinkContext &Context, - CompileUnitHandler OnCUDieLoaded, - unsigned Indent) { +Error DWARFLinker::loadClangModule( + ObjFileLoaderTy Loader, const DWARFDie &CUDie, const std::string &PCMFile, + LinkContext &Context, CompileUnitHandlerTy OnCUDieLoaded, unsigned Indent) { uint64_t DwoId = getDwoId(CUDie); std::string ModuleName = dwarf::toString(CUDie.find(dwarf::DW_AT_name), ""); @@ -2673,8 +2672,8 @@ void DWARFLinker::copyInvariantDebugSection(DWARFContext &Dwarf) { Dwarf.getDWARFObj().getLoclistsSection().Data, "debug_loclists"); } -void DWARFLinker::addObjectFile(DWARFFile &File, objFileLoader Loader, - CompileUnitHandler OnCUDieLoaded) { +void DWARFLinker::addObjectFile(DWARFFile &File, ObjFileLoaderTy Loader, + CompileUnitHandlerTy OnCUDieLoaded) { ObjectContexts.emplace_back(LinkContext(File)); if (ObjectContexts.back().File.Dwarf) { @@ -2713,12 +2712,8 @@ Error DWARFLinker::link() { DeclContextTree ODRContexts; for (LinkContext &OptContext : ObjectContexts) { - if (Options.Verbose) { - if (DwarfLinkerClientID == DwarfLinkerClient::Dsymutil) - outs() << "DEBUG MAP OBJECT: " << OptContext.File.FileName << "\n"; - else - outs() << "OBJECT FILE: " << OptContext.File.FileName << "\n"; - } + if (Options.Verbose) + outs() << "DEBUG MAP OBJECT: " << OptContext.File.FileName << "\n"; if (!OptContext.File.Dwarf) continue; @@ -3039,7 +3034,6 @@ Error DWARFLinker::cloneModuleUnit(LinkContext &Context, RefModuleUnit &Unit, void DWARFLinker::verifyInput(const DWARFFile &File) { assert(File.Dwarf); - std::string Buffer; raw_string_ostream OS(Buffer); DIDumpOptions DumpOpts; diff --git a/llvm/lib/DWARFLinker/DWARFLinkerCompileUnit.cpp b/llvm/lib/DWARFLinker/Classic/DWARFLinkerCompileUnit.cpp similarity index 97% rename from llvm/lib/DWARFLinker/DWARFLinkerCompileUnit.cpp rename to llvm/lib/DWARFLinker/Classic/DWARFLinkerCompileUnit.cpp index 06559bc38c86..1eb3a70a5513 100644 --- a/llvm/lib/DWARFLinker/DWARFLinkerCompileUnit.cpp +++ b/llvm/lib/DWARFLinker/Classic/DWARFLinkerCompileUnit.cpp @@ -6,15 +6,18 @@ // //===----------------------------------------------------------------------===// -#include "llvm/DWARFLinker/DWARFLinkerCompileUnit.h" +#include "llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/DWARFLinker/DWARFLinkerDeclContext.h" +#include "llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFExpression.h" #include "llvm/Support/FormatVariadic.h" namespace llvm { +using namespace dwarf_linker; +using namespace dwarf_linker::classic; + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void CompileUnit::DIEInfo::dump() { llvm::errs() << "{\n"; diff --git a/llvm/lib/DWARFLinker/DWARFLinkerDeclContext.cpp b/llvm/lib/DWARFLinker/Classic/DWARFLinkerDeclContext.cpp similarity index 97% rename from llvm/lib/DWARFLinker/DWARFLinkerDeclContext.cpp rename to llvm/lib/DWARFLinker/Classic/DWARFLinkerDeclContext.cpp index 015a4f9e8ac6..c9c8dddce9c4 100644 --- a/llvm/lib/DWARFLinker/DWARFLinkerDeclContext.cpp +++ b/llvm/lib/DWARFLinker/Classic/DWARFLinkerDeclContext.cpp @@ -6,14 +6,17 @@ // //===----------------------------------------------------------------------===// -#include "llvm/DWARFLinker/DWARFLinkerDeclContext.h" -#include "llvm/DWARFLinker/DWARFLinkerCompileUnit.h" +#include "llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h" +#include "llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFDie.h" #include "llvm/DebugInfo/DWARF/DWARFUnit.h" namespace llvm { +using namespace dwarf_linker; +using namespace dwarf_linker::classic; + /// Set the last DIE/CU a context was seen in and, possibly invalidate the /// context if it is ambiguous. /// diff --git a/llvm/lib/DWARFLinker/DWARFStreamer.cpp b/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp similarity index 99% rename from llvm/lib/DWARFLinker/DWARFStreamer.cpp rename to llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp index 3ec082f4ea0c..020bbb06449d 100644 --- a/llvm/lib/DWARFLinker/DWARFStreamer.cpp +++ b/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp @@ -6,9 +6,9 @@ // //===----------------------------------------------------------------------===// -#include "llvm/DWARFLinker/DWARFStreamer.h" +#include "llvm/DWARFLinker/Classic/DWARFStreamer.h" #include "llvm/CodeGen/NonRelocatableStringpool.h" -#include "llvm/DWARFLinker/DWARFLinkerCompileUnit.h" +#include "llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFDebugMacro.h" #include "llvm/MC/MCAsmBackend.h" @@ -26,7 +26,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/TargetParser/Triple.h" -namespace llvm { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::classic; Error DwarfStreamer::init(Triple TheTriple, StringRef Swift5ReflectionSegmentName) { @@ -1426,5 +1428,3 @@ void DwarfStreamer::emitMacroTableImpl(const DWARFDebugMacro *MacroTable, } } } - -} // namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/AcceleratorRecordsSaver.cpp b/llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.cpp similarity index 98% rename from llvm/lib/DWARFLinkerParallel/AcceleratorRecordsSaver.cpp rename to llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.cpp index 5ec25cfe5fd2..3af574c70561 100644 --- a/llvm/lib/DWARFLinkerParallel/AcceleratorRecordsSaver.cpp +++ b/llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.cpp @@ -11,8 +11,9 @@ #include "llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h" #include "llvm/Support/DJB.h" -namespace llvm { -namespace dwarflinker_parallel { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; static uint32_t hashFullyQualifiedName(CompileUnit &InputCU, DWARFDie &InputDIE, int ChildRecurseDepth = 0) { @@ -290,6 +291,3 @@ void AcceleratorRecordsSaver::saveTypeRecord(StringEntry *Name, DIE *OutDIE, Info.TypeEntryBodyPtr = TypeEntry->getValue().load(); OutUnit.getAsTypeUnit()->saveAcceleratorInfo(Info); } - -} // end of namespace dwarflinker_parallel -} // namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/AcceleratorRecordsSaver.h b/llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.h similarity index 88% rename from llvm/lib/DWARFLinkerParallel/AcceleratorRecordsSaver.h rename to llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.h index 5e7f4d0c3166..bc3ea8669ece 100644 --- a/llvm/lib/DWARFLinkerParallel/AcceleratorRecordsSaver.h +++ b/llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_ACCELERATORRECORDSSAVER_H -#define LLVM_LIB_DWARFLINKERPARALLEL_ACCELERATORRECORDSSAVER_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_ACCELERATORRECORDSSAVER_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_ACCELERATORRECORDSSAVER_H #include "DIEAttributeCloner.h" #include "DWARFLinkerCompileUnit.h" @@ -15,7 +15,8 @@ #include "DWARFLinkerTypeUnit.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This class helps to store information for accelerator entries. /// It prepares accelerator info for the certain DIE and store it inside @@ -64,7 +65,8 @@ protected: CompileUnit::OutputUnitVariantPtr OutUnit; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_ACCELERATORRECORDSSAVER_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_ACCELERATORRECORDSSAVER_H diff --git a/llvm/lib/DWARFLinkerParallel/ArrayList.h b/llvm/lib/DWARFLinker/Parallel/ArrayList.h similarity index 91% rename from llvm/lib/DWARFLinkerParallel/ArrayList.h rename to llvm/lib/DWARFLinker/Parallel/ArrayList.h index def83f91bc6f..c48f828609be 100644 --- a/llvm/lib/DWARFLinkerParallel/ArrayList.h +++ b/llvm/lib/DWARFLinker/Parallel/ArrayList.h @@ -6,14 +6,15 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_ARRAYLIST_H -#define LLVM_LIB_DWARFLINKERPARALLEL_ARRAYLIST_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_ARRAYLIST_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_ARRAYLIST_H #include "llvm/Support/PerThreadBumpPtrAllocator.h" #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This class is a simple list of T structures. It keeps elements as /// pre-allocated groups to save memory for each element's next pointer. @@ -21,7 +22,7 @@ namespace dwarflinker_parallel { /// Method add() can be called asynchronously. template class ArrayList { public: - ArrayList(parallel::PerThreadBumpPtrAllocator *Allocator) + ArrayList(llvm::parallel::PerThreadBumpPtrAllocator *Allocator) : Allocator(Allocator) {} /// Add specified \p Item to the list. @@ -156,10 +157,11 @@ protected: std::atomic GroupsHead = nullptr; std::atomic LastGroup = nullptr; - parallel::PerThreadBumpPtrAllocator *Allocator = nullptr; + llvm::parallel::PerThreadBumpPtrAllocator *Allocator = nullptr; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_ARRAYLIST_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_ARRAYLIST_H diff --git a/llvm/lib/DWARFLinkerParallel/CMakeLists.txt b/llvm/lib/DWARFLinker/Parallel/CMakeLists.txt similarity index 94% rename from llvm/lib/DWARFLinkerParallel/CMakeLists.txt rename to llvm/lib/DWARFLinker/Parallel/CMakeLists.txt index b0f0b3910e58..5d3806297513 100644 --- a/llvm/lib/DWARFLinkerParallel/CMakeLists.txt +++ b/llvm/lib/DWARFLinker/Parallel/CMakeLists.txt @@ -3,14 +3,12 @@ add_llvm_component_library(LLVMDWARFLinkerParallel DependencyTracker.cpp DIEAttributeCloner.cpp DWARFEmitterImpl.cpp - DWARFFile.cpp DWARFLinker.cpp DWARFLinkerCompileUnit.cpp DWARFLinkerTypeUnit.cpp DWARFLinkerImpl.cpp DWARFLinkerUnit.cpp OutputSections.cpp - StringPool.cpp SyntheticTypeNameBuilder.cpp ADDITIONAL_HEADER_DIRS @@ -24,6 +22,7 @@ add_llvm_component_library(LLVMDWARFLinkerParallel BinaryFormat CodeGen DebugInfoDWARF + DWARFLinkerBase MC Object Support diff --git a/llvm/lib/DWARFLinkerParallel/DIEAttributeCloner.cpp b/llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.cpp similarity index 99% rename from llvm/lib/DWARFLinkerParallel/DIEAttributeCloner.cpp rename to llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.cpp index 81fc57f7cabb..07ebd55e2c46 100644 --- a/llvm/lib/DWARFLinkerParallel/DIEAttributeCloner.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.cpp @@ -9,8 +9,9 @@ #include "DIEAttributeCloner.h" #include "llvm/DebugInfo/DWARF/DWARFDebugMacro.h" -namespace llvm { -namespace dwarflinker_parallel { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; void DIEAttributeCloner::clone() { // Extract and clone every attribute. @@ -650,6 +651,3 @@ unsigned DIEAttributeCloner::finalizeAbbreviations(bool HasChildrenToClone) { return AttrOutOffset; } - -} // end of namespace dwarflinker_parallel -} // namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/DIEAttributeCloner.h b/llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.h similarity index 95% rename from llvm/lib/DWARFLinkerParallel/DIEAttributeCloner.h rename to llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.h index e18c0a15cefc..6a6bd08570d7 100644 --- a/llvm/lib/DWARFLinkerParallel/DIEAttributeCloner.h +++ b/llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DIEATTRIBUTECLONER_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DIEATTRIBUTECLONER_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DIEATTRIBUTECLONER_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DIEATTRIBUTECLONER_H #include "ArrayList.h" #include "DIEGenerator.h" @@ -16,7 +16,8 @@ #include "DWARFLinkerTypeUnit.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// Information gathered and exchanged between the various /// clone*Attr helpers about the attributes of a particular DIE. @@ -178,7 +179,8 @@ protected: bool Use_DW_FORM_strp = false; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DIEATTRIBUTECLONER_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DIEATTRIBUTECLONER_H diff --git a/llvm/lib/DWARFLinkerParallel/DIEGenerator.h b/llvm/lib/DWARFLinker/Parallel/DIEGenerator.h similarity index 95% rename from llvm/lib/DWARFLinkerParallel/DIEGenerator.h rename to llvm/lib/DWARFLinker/Parallel/DIEGenerator.h index 42bf00f55ff1..2341dbaa8c76 100644 --- a/llvm/lib/DWARFLinkerParallel/DIEGenerator.h +++ b/llvm/lib/DWARFLinker/Parallel/DIEGenerator.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DIEGENERATOR_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DIEGENERATOR_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DIEGENERATOR_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DIEGENERATOR_H #include "DWARFLinkerGlobalData.h" #include "DWARFLinkerUnit.h" @@ -15,7 +15,8 @@ #include "llvm/Support/LEB128.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This class is a helper to create output DIE tree. class DIEGenerator { @@ -174,7 +175,8 @@ protected: DIE *OutputDIE = nullptr; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DIEGENERATOR_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DIEGENERATOR_H diff --git a/llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp similarity index 98% rename from llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.cpp rename to llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp index 355cfae3a646..115167f0c7dc 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "DWARFEmitterImpl.h" -#include "llvm/DWARFLinker/DWARFLinkerCompileUnit.h" +#include "DWARFLinkerCompileUnit.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCObjectWriter.h" @@ -17,8 +17,9 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/FormattedStream.h" -namespace llvm { -namespace dwarflinker_parallel { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; Error DwarfEmitterImpl::init(Triple TheTriple, StringRef Swift5ReflectionSegmentName) { @@ -276,6 +277,3 @@ void DwarfEmitterImpl::emitAppleTypes( Asm->OutStreamer->emitLabel(SectionBegin); emitAppleAccelTable(Asm.get(), Table, "types", SectionBegin); } - -} // end of namespace dwarflinker_parallel -} // namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.h b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h similarity index 93% rename from llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.h rename to llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h index d03336c1c11a..89a33fe94191 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DWARFEMITTERIMPL_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DWARFEMITTERIMPL_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DWARFEMITTERIMPL_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DWARFEMITTERIMPL_H #include "DWARFLinkerCompileUnit.h" #include "llvm/BinaryFormat/Swift.h" #include "llvm/CodeGen/AccelTable.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/DWARFLinkerParallel/DWARFLinker.h" +#include "llvm/DWARFLinker/Parallel/DWARFLinker.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInstrInfo.h" @@ -36,7 +36,8 @@ namespace llvm { template class AccelTable; class MCCodeEmitter; -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { using DebugNamesUnitsOffsets = std::vector>; using CompUnitIDToIdx = DenseMap; @@ -139,7 +140,8 @@ private: uint64_t DebugInfoSectionSize = 0; }; -} // end namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DWARFEMITTERIMPL_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DWARFEMITTERIMPL_H diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinker.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFLinker.cpp similarity index 65% rename from llvm/lib/DWARFLinkerParallel/DWARFLinker.cpp rename to llvm/lib/DWARFLinker/Parallel/DWARFLinker.cpp index 269f24b1a13b..ad8d28a64317 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinker.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinker.cpp @@ -9,10 +9,14 @@ #include "DWARFLinkerImpl.h" #include "DependencyTracker.h" -std::unique_ptr -llvm::dwarflinker_parallel::DWARFLinker::createLinker( - MessageHandlerTy ErrorHandler, MessageHandlerTy WarningHandler, - TranslatorFuncTy StringsTranslator) { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; + +std::unique_ptr +DWARFLinker::createLinker(MessageHandlerTy ErrorHandler, + MessageHandlerTy WarningHandler, + TranslatorFuncTy StringsTranslator) { return std::make_unique(ErrorHandler, WarningHandler, StringsTranslator); } diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp similarity index 99% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.cpp rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp index 3f0e75690272..ffcf9f365aec 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp @@ -21,7 +21,8 @@ #include using namespace llvm; -using namespace llvm::dwarflinker_parallel; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; CompileUnit::CompileUnit(LinkingGlobalData &GlobalData, unsigned ID, StringRef ClangModuleName, DWARFFile &File, @@ -1870,7 +1871,7 @@ void CompileUnit::verifyDependencies() { Dependencies.get()->verifyKeepChain(); } -ArrayRef llvm::dwarflinker_parallel::getODRAttributes() { +ArrayRef dwarf_linker::parallel::getODRAttributes() { static dwarf::Attribute ODRAttributes[] = { dwarf::DW_AT_type, dwarf::DW_AT_specification, dwarf::DW_AT_abstract_origin, dwarf::DW_AT_import}; diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.h similarity index 98% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.h rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.h index 28fcc34d867d..abd978e7c0e4 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.h @@ -6,15 +6,16 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERCOMPILEUNIT_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERCOMPILEUNIT_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERCOMPILEUNIT_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERCOMPILEUNIT_H #include "DWARFLinkerUnit.h" -#include "llvm/DWARFLinkerParallel/DWARFFile.h" +#include "llvm/DWARFLinker/DWARFFile.h" #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { using OffsetToUnitTy = function_ref; @@ -730,7 +731,8 @@ private: /// infinite recursion. ArrayRef getODRAttributes(); -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERCOMPILEUNIT_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERCOMPILEUNIT_H diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerGlobalData.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerGlobalData.h similarity index 88% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerGlobalData.h rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerGlobalData.h index 31724770093d..b641343ac808 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerGlobalData.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerGlobalData.h @@ -6,19 +6,20 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERGLOBALDATA_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERGLOBALDATA_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERGLOBALDATA_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERGLOBALDATA_H #include "TypePool.h" -#include "llvm/DWARFLinkerParallel/DWARFLinker.h" -#include "llvm/DWARFLinkerParallel/StringPool.h" +#include "llvm/DWARFLinker/Parallel/DWARFLinker.h" +#include "llvm/DWARFLinker/StringPool.h" #include "llvm/Support/PerThreadBumpPtrAllocator.h" namespace llvm { class DWARFDie; -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { using TranslatorFuncTy = std::function; using MessageHandlerTy = std::function( GlobalData, UniqueUnitID++, Language, GlobalFormat, GlobalEndianness); @@ -191,9 +192,10 @@ Error DWARFLinkerImpl::link() { // Set parallel options. if (GlobalData.getOptions().Threads == 0) - parallel::strategy = optimal_concurrency(OverallNumberOfCU); + llvm::parallel::strategy = optimal_concurrency(OverallNumberOfCU); else - parallel::strategy = hardware_concurrency(GlobalData.getOptions().Threads); + llvm::parallel::strategy = + hardware_concurrency(GlobalData.getOptions().Threads); // Link object files. if (GlobalData.getOptions().Threads == 1) { @@ -205,7 +207,7 @@ Error DWARFLinkerImpl::link() { Context->InputDWARFFile.unload(); } } else { - ThreadPool Pool(parallel::strategy); + ThreadPool Pool(llvm::parallel::strategy); for (std::unique_ptr &Context : ObjectContexts) Pool.async([&]() { // Link object file. @@ -486,108 +488,104 @@ Error DWARFLinkerImpl::LinkContext::link(TypeUnit *ArtificialTypeUnit) { return Error::success(); } - OriginalDebugInfoSize = getInputDebugInfoSize(); - - // Create CompileUnit structures to keep information about source - // DWARFUnit`s, load line tables. - for (const auto &OrigCU : InputDWARFFile.Dwarf->compile_units()) { - // Load only unit DIE at this stage. - auto CUDie = OrigCU->getUnitDIE(); - std::string PCMFile = - getPCMFile(CUDie, GlobalData.getOptions().ObjectPrefixMap); - - // The !isClangModuleRef condition effectively skips over fully resolved - // skeleton units. - if (!CUDie || GlobalData.getOptions().UpdateIndexTablesOnly || - !isClangModuleRef(CUDie, PCMFile, 0, true).first) { - CompileUnits.emplace_back(std::make_unique( - GlobalData, *OrigCU, UniqueUnitID.fetch_add(1), "", InputDWARFFile, - getUnitForOffset, OrigCU->getFormParams(), getEndianness())); - - // Preload line table, as it can't be loaded asynchronously. - CompileUnits.back()->loadLineTable(); - } - }; + OriginalDebugInfoSize = getInputDebugInfoSize(); + + // Create CompileUnit structures to keep information about source + // DWARFUnit`s, load line tables. + for (const auto &OrigCU : InputDWARFFile.Dwarf->compile_units()) { + // Load only unit DIE at this stage. + auto CUDie = OrigCU->getUnitDIE(); + std::string PCMFile = + getPCMFile(CUDie, GlobalData.getOptions().ObjectPrefixMap); + + // The !isClangModuleRef condition effectively skips over fully resolved + // skeleton units. + if (!CUDie || GlobalData.getOptions().UpdateIndexTablesOnly || + !isClangModuleRef(CUDie, PCMFile, 0, true).first) { + CompileUnits.emplace_back(std::make_unique( + GlobalData, *OrigCU, UniqueUnitID.fetch_add(1), "", InputDWARFFile, + getUnitForOffset, OrigCU->getFormParams(), getEndianness())); + + // Preload line table, as it can't be loaded asynchronously. + CompileUnits.back()->loadLineTable(); + } + }; - HasNewInterconnectedCUs = false; + HasNewInterconnectedCUs = false; - // Link self-sufficient compile units and discover inter-connected compile - // units. - parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { - linkSingleCompileUnit(*CU, ArtificialTypeUnit); - }); + // Link self-sufficient compile units and discover inter-connected compile + // units. + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + linkSingleCompileUnit(*CU, ArtificialTypeUnit); + }); + + // Link all inter-connected units. + if (HasNewInterconnectedCUs) { + InterCUProcessingStarted = true; - // Link all inter-connected units. - if (HasNewInterconnectedCUs) { - InterCUProcessingStarted = true; - - if (Error Err = finiteLoop([&]() -> Expected { - HasNewInterconnectedCUs = false; - - // Load inter-connected units. - parallelForEach( - CompileUnits, [&](std::unique_ptr &CU) { - if (CU->isInterconnectedCU()) { - CU->maybeResetToLoadedStage(); - linkSingleCompileUnit(*CU, ArtificialTypeUnit, - CompileUnit::Stage::Loaded); - } - }); - - // Do liveness analysis for inter-connected units. - parallelForEach(CompileUnits, - [&](std::unique_ptr &CU) { - linkSingleCompileUnit( - *CU, ArtificialTypeUnit, + if (Error Err = finiteLoop([&]() -> Expected { + HasNewInterconnectedCUs = false; + + // Load inter-connected units. + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + if (CU->isInterconnectedCU()) { + CU->maybeResetToLoadedStage(); + linkSingleCompileUnit(*CU, ArtificialTypeUnit, + CompileUnit::Stage::Loaded); + } + }); + + // Do liveness analysis for inter-connected units. + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + linkSingleCompileUnit(*CU, ArtificialTypeUnit, CompileUnit::Stage::LivenessAnalysisDone); - }); - - return HasNewInterconnectedCUs.load(); - })) - return Err; - - // Update dependencies. - if (Error Err = finiteLoop([&]() -> Expected { - HasNewGlobalDependency = false; - parallelForEach( - CompileUnits, [&](std::unique_ptr &CU) { - linkSingleCompileUnit( - *CU, ArtificialTypeUnit, - CompileUnit::Stage::UpdateDependenciesCompleteness); - }); - return HasNewGlobalDependency.load(); - })) - return Err; - parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { - if (CU->isInterconnectedCU() && - CU->getStage() == CompileUnit::Stage::LivenessAnalysisDone) - CU->setStage(CompileUnit::Stage::UpdateDependenciesCompleteness); - }); + }); - // Assign type names. - parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { - linkSingleCompileUnit(*CU, ArtificialTypeUnit, - CompileUnit::Stage::TypeNamesAssigned); - }); + return HasNewInterconnectedCUs.load(); + })) + return Err; - // Clone inter-connected units. - parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { - linkSingleCompileUnit(*CU, ArtificialTypeUnit, - CompileUnit::Stage::Cloned); - }); + // Update dependencies. + if (Error Err = finiteLoop([&]() -> Expected { + HasNewGlobalDependency = false; + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + linkSingleCompileUnit( + *CU, ArtificialTypeUnit, + CompileUnit::Stage::UpdateDependenciesCompleteness); + }); + return HasNewGlobalDependency.load(); + })) + return Err; + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + if (CU->isInterconnectedCU() && + CU->getStage() == CompileUnit::Stage::LivenessAnalysisDone) + CU->setStage(CompileUnit::Stage::UpdateDependenciesCompleteness); + }); - // Update patches for inter-connected units. - parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { - linkSingleCompileUnit(*CU, ArtificialTypeUnit, - CompileUnit::Stage::PatchesUpdated); - }); + // Assign type names. + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + linkSingleCompileUnit(*CU, ArtificialTypeUnit, + CompileUnit::Stage::TypeNamesAssigned); + }); - // Release data. - parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { - linkSingleCompileUnit(*CU, ArtificialTypeUnit, - CompileUnit::Stage::Cleaned); - }); - } + // Clone inter-connected units. + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + linkSingleCompileUnit(*CU, ArtificialTypeUnit, + CompileUnit::Stage::Cloned); + }); + + // Update patches for inter-connected units. + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + linkSingleCompileUnit(*CU, ArtificialTypeUnit, + CompileUnit::Stage::PatchesUpdated); + }); + + // Release data. + parallelForEach(CompileUnits, [&](std::unique_ptr &CU) { + linkSingleCompileUnit(*CU, ArtificialTypeUnit, + CompileUnit::Stage::Cleaned); + }); + } if (GlobalData.getOptions().UpdateIndexTablesOnly) { // Emit Invariant sections. @@ -598,7 +596,7 @@ Error DWARFLinkerImpl::LinkContext::link(TypeUnit *ArtificialTypeUnit) { // Emit .debug_frame section. Error ResultErr = Error::success(); - parallel::TaskGroup TGroup; + llvm::parallel::TaskGroup TGroup; // We use task group here as PerThreadBumpPtrAllocator should be called from // the threads created by ThreadPoolExecutor. TGroup.spawn([&]() { @@ -965,7 +963,7 @@ void DWARFLinkerImpl::printStatistic() { } void DWARFLinkerImpl::assignOffsets() { - parallel::TaskGroup TGroup; + llvm::parallel::TaskGroup TGroup; TGroup.spawn([&]() { assignOffsetsToStrings(); }); TGroup.spawn([&]() { assignOffsetsToSections(); }); } @@ -1134,7 +1132,7 @@ void DWARFLinkerImpl::patchOffsetsAndSizes() { } void DWARFLinkerImpl::emitCommonSectionsAndWriteCompileUnitsToTheOutput() { - parallel::TaskGroup TG; + llvm::parallel::TaskGroup TG; // Create section descriptors ahead if they are not exist at the moment. // SectionDescriptors container is not thread safe. Thus we should be sure @@ -1451,6 +1449,3 @@ void DWARFLinkerImpl::writeCommonSectionsToTheOutput() { OutSection.clearSectionContent(); }); } - -} // end of namespace dwarflinker_parallel -} // namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerImpl.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h similarity index 96% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerImpl.h rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h index 60018eea121f..b4331df5e323 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerImpl.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERIMPL_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERIMPL_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERIMPL_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERIMPL_H #include "DWARFEmitterImpl.h" #include "DWARFLinkerCompileUnit.h" @@ -15,11 +15,12 @@ #include "StringEntryToDwarfStringPoolEntryMap.h" #include "llvm/ADT/AddressRanges.h" #include "llvm/CodeGen/AccelTable.h" -#include "llvm/DWARFLinkerParallel/DWARFLinker.h" -#include "llvm/DWARFLinkerParallel/StringPool.h" +#include "llvm/DWARFLinker/Parallel/DWARFLinker.h" +#include "llvm/DWARFLinker/StringPool.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This class links debug info. class DWARFLinkerImpl : public DWARFLinker { @@ -100,7 +101,7 @@ public: } /// Set prepend path for clang modules. - void setPrependPath(const std::string &Ppath) override { + void setPrependPath(StringRef Ppath) override { GlobalData.Options.PrependPath = Ppath; } @@ -374,7 +375,8 @@ protected: /// @} }; -} // end namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERIMPL_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERIMPL_H diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerTypeUnit.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp similarity index 99% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerTypeUnit.cpp rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp index 9d5c213085c2..397411895a8e 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerTypeUnit.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp @@ -12,7 +12,8 @@ #include "llvm/Support/LEB128.h" using namespace llvm; -using namespace llvm::dwarflinker_parallel; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; TypeUnit::TypeUnit(LinkingGlobalData &GlobalData, unsigned ID, std::optional Language, dwarf::FormParams Format, @@ -43,7 +44,7 @@ void TypeUnit::createDIETree(BumpPtrAllocator &Allocator) { // TaskGroup is created here as internal code has calls to // PerThreadBumpPtrAllocator which should be called from the task group task. - parallel::TaskGroup TG; + llvm::parallel::TaskGroup TG; TG.spawn([&]() { SectionDescriptor &DebugInfoSection = getOrCreateSectionDescriptor(DebugSectionKind::DebugInfo); @@ -134,7 +135,7 @@ void TypeUnit::prepareDataForTreeCreation() { // Type unit data created parallelly. So the order of data is not // deterministic. Order data here if we need deterministic output. - parallel::TaskGroup TG; + llvm::parallel::TaskGroup TG; if (!GlobalData.getOptions().AllowNonDeterministicOutput) { TG.spawn([&]() { diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerTypeUnit.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.h similarity index 93% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerTypeUnit.h rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.h index 97e620eee0c4..0944de8d1315 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerTypeUnit.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKERPARALLEL_DWARFLINKERTYPEUNIT_H -#define LLVM_DWARFLINKERPARALLEL_DWARFLINKERTYPEUNIT_H +#ifndef LLVM_DWARFLINKER_PARALLEL_DWARFLINKERTYPEUNIT_H +#define LLVM_DWARFLINKER_PARALLEL_DWARFLINKERTYPEUNIT_H #include "DWARFLinkerUnit.h" #include "llvm/CodeGen/DIE.h" @@ -15,7 +15,8 @@ #include "llvm/DebugInfo/DWARF/DWARFUnit.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// Type Unit is used to represent an artificial compilation unit /// which keeps all type information. This type information is referenced @@ -132,7 +133,8 @@ private: std::mutex DebugStringIndexMapMutex; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_DWARFLINKERPARALLEL_DWARFLINKERTYPEUNIT_H +#endif // LLVM_DWARFLINKER_PARALLEL_DWARFLINKERTYPEUNIT_H diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerUnit.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.cpp similarity index 98% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerUnit.cpp rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.cpp index b1da1900d65e..93def34aa4fd 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerUnit.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.cpp @@ -10,8 +10,9 @@ #include "DWARFEmitterImpl.h" #include "DebugLineSectionEmitter.h" -namespace llvm { -namespace dwarflinker_parallel { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; void DwarfUnit::assignAbbrev(DIEAbbrev &Abbrev) { // Check the set for priors. @@ -245,6 +246,3 @@ void DwarfUnit::emitPubAccelerators() { OutSection.OS.tell() - *TypesLengthOffset); } } - -} // end of namespace dwarflinker_parallel -} // end of namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerUnit.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h similarity index 94% rename from llvm/lib/DWARFLinkerParallel/DWARFLinkerUnit.h rename to llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h index 9640a8ee711e..36c24372e494 100644 --- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerUnit.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h @@ -6,20 +6,21 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERUNIT_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERUNIT_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERUNIT_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERUNIT_H #include "DWARFLinkerGlobalData.h" #include "IndexedValuesMap.h" #include "OutputSections.h" #include "llvm/CodeGen/DIE.h" -#include "llvm/DWARFLinkerParallel/DWARFLinker.h" -#include "llvm/DWARFLinkerParallel/StringPool.h" +#include "llvm/DWARFLinker/Parallel/DWARFLinker.h" +#include "llvm/DWARFLinker/StringPool.h" #include "llvm/DebugInfo/DWARF/DWARFUnit.h" #include "llvm/Support/LEB128.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { class DwarfUnit; using MacroOffset2UnitMapTy = DenseMap; @@ -215,7 +216,8 @@ inline bool isODRLanguage(uint16_t Language) { return false; } -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DWARFLINKERUNIT_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERUNIT_H diff --git a/llvm/lib/DWARFLinkerParallel/DebugLineSectionEmitter.h b/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h similarity index 97% rename from llvm/lib/DWARFLinkerParallel/DebugLineSectionEmitter.h rename to llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h index 27c63fad712f..545d04cfbe43 100644 --- a/llvm/lib/DWARFLinkerParallel/DebugLineSectionEmitter.h +++ b/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h @@ -6,18 +6,19 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DEBUGLINESECTIONEMITTER_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DEBUGLINESECTIONEMITTER_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DEBUGLINESECTIONEMITTER_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DEBUGLINESECTIONEMITTER_H #include "DWARFEmitterImpl.h" -#include "llvm/DWARFLinkerParallel/AddressesMap.h" -#include "llvm/DWARFLinkerParallel/DWARFLinker.h" +#include "llvm/DWARFLinker/AddressesMap.h" +#include "llvm/DWARFLinker/Parallel/DWARFLinker.h" #include "llvm/DebugInfo/DWARF/DWARFObject.h" #include "llvm/MC/MCTargetOptionsCommandFlags.h" #include "llvm/MC/TargetRegistry.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This class emits specified line table into the .debug_line section. class DebugLineSectionEmitter { @@ -389,7 +390,8 @@ private: std::unique_ptr MSTI; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DEBUGLINESECTIONEMITTER_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DEBUGLINESECTIONEMITTER_H diff --git a/llvm/lib/DWARFLinkerParallel/DependencyTracker.cpp b/llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp similarity index 99% rename from llvm/lib/DWARFLinkerParallel/DependencyTracker.cpp rename to llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp index 052eb6cf57d4..04152e7f9f2b 100644 --- a/llvm/lib/DWARFLinkerParallel/DependencyTracker.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp @@ -9,8 +9,9 @@ #include "DependencyTracker.h" #include "llvm/Support/FormatVariadic.h" -namespace llvm { -namespace dwarflinker_parallel { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; /// A broken link in the keep chain. By recording both the parent and the child /// we can show only broken links for DIEs with multiple children. @@ -834,6 +835,3 @@ bool DependencyTracker::isLiveSubprogramEntry(const UnitEntryPairTy &Entry) { Entry.CU->addFunctionRange(*LowPc, *HighPc, *RelocAdjustment); return true; } - -} // end of namespace dwarflinker_parallel -} // namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/DependencyTracker.h b/llvm/lib/DWARFLinker/Parallel/DependencyTracker.h similarity index 96% rename from llvm/lib/DWARFLinkerParallel/DependencyTracker.h rename to llvm/lib/DWARFLinker/Parallel/DependencyTracker.h index b0b6ad3a1e8c..4a0d985c8aaa 100644 --- a/llvm/lib/DWARFLinkerParallel/DependencyTracker.h +++ b/llvm/lib/DWARFLinker/Parallel/DependencyTracker.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_DEPENDENCYTRACKER_H -#define LLVM_LIB_DWARFLINKERPARALLEL_DEPENDENCYTRACKER_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_DEPENDENCYTRACKER_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_DEPENDENCYTRACKER_H #include "DWARFLinkerCompileUnit.h" #include "llvm/ADT/PointerIntPair.h" @@ -17,7 +17,8 @@ namespace llvm { class DWARFDebugInfoEntry; class DWARFDie; -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This class discovers DIEs dependencies: marks "live" DIEs, marks DIE /// locations (whether DIE should be cloned as regular DIE or it should be put @@ -266,7 +267,8 @@ protected: RootEntriesListTy Dependencies; }; -} // end namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_DEPENDENCYTRACKER_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_DEPENDENCYTRACKER_H diff --git a/llvm/lib/DWARFLinkerParallel/IndexedValuesMap.h b/llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h similarity index 78% rename from llvm/lib/DWARFLinkerParallel/IndexedValuesMap.h rename to llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h index 0dc8de860a42..b592ce37937b 100644 --- a/llvm/lib/DWARFLinkerParallel/IndexedValuesMap.h +++ b/llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_INDEXEDVALUESMAP_H -#define LLVM_LIB_DWARFLINKERPARALLEL_INDEXEDVALUESMAP_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_INDEXEDVALUESMAP_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_INDEXEDVALUESMAP_H #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" @@ -15,7 +15,8 @@ #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { template class IndexedValuesMap { public: @@ -43,7 +44,8 @@ protected: SmallVector Values; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_INDEXEDVALUESMAP_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_INDEXEDVALUESMAP_H diff --git a/llvm/lib/DWARFLinkerParallel/OutputSections.cpp b/llvm/lib/DWARFLinker/Parallel/OutputSections.cpp similarity index 95% rename from llvm/lib/DWARFLinkerParallel/OutputSections.cpp rename to llvm/lib/DWARFLinker/Parallel/OutputSections.cpp index 730ae0f83d7b..cd1205b60f85 100644 --- a/llvm/lib/DWARFLinkerParallel/OutputSections.cpp +++ b/llvm/lib/DWARFLinker/Parallel/OutputSections.cpp @@ -11,22 +11,12 @@ #include "DWARFLinkerTypeUnit.h" #include "llvm/ADT/StringSwitch.h" -namespace llvm { -namespace dwarflinker_parallel { - -static constexpr StringLiteral SectionNames[SectionKindsNum] = { - "debug_info", "debug_line", "debug_frame", "debug_ranges", - "debug_rnglists", "debug_loc", "debug_loclists", "debug_aranges", - "debug_abbrev", "debug_macinfo", "debug_macro", "debug_addr", - "debug_str", "debug_line_str", "debug_str_offsets", "debug_pubnames", - "debug_pubtypes", "debug_names", "apple_names", "apple_namespac", - "apple_objc", "apple_types"}; - -const StringLiteral &getSectionName(DebugSectionKind SectionKind) { - return SectionNames[static_cast(SectionKind)]; -} +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; -std::optional parseDebugTableName(llvm::StringRef SecName) { +std::optional +dwarf_linker::parallel::parseDebugTableName(llvm::StringRef SecName) { return llvm::StringSwitch>( SecName.substr(SecName.find_first_not_of("._"))) .Case(getSectionName(DebugSectionKind::DebugInfo), @@ -531,6 +521,3 @@ void OutputSections::applyPatches( Section.apply(Patch.PatchOffset, dwarf::DW_FORM_sec_offset, FinalValue); }); } - -} // end of namespace dwarflinker_parallel -} // end of namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/OutputSections.h b/llvm/lib/DWARFLinker/Parallel/OutputSections.h similarity index 94% rename from llvm/lib/DWARFLinkerParallel/OutputSections.h rename to llvm/lib/DWARFLinker/Parallel/OutputSections.h index 0f394b0810ea..b9df2228920a 100644 --- a/llvm/lib/DWARFLinkerParallel/OutputSections.h +++ b/llvm/lib/DWARFLinker/Parallel/OutputSections.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_OUTPUTSECTIONS_H -#define LLVM_LIB_DWARFLINKERPARALLEL_OUTPUTSECTIONS_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_OUTPUTSECTIONS_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_OUTPUTSECTIONS_H #include "ArrayList.h" #include "StringEntryToDwarfStringPoolEntryMap.h" @@ -15,7 +15,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/DwarfStringPoolEntry.h" -#include "llvm/DWARFLinkerParallel/StringPool.h" +#include "llvm/DWARFLinker/StringPool.h" #include "llvm/DebugInfo/DWARF/DWARFFormValue.h" #include "llvm/DebugInfo/DWARF/DWARFObject.h" #include "llvm/Object/ObjectFile.h" @@ -29,7 +29,8 @@ #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { class TypeUnit; @@ -62,12 +63,22 @@ enum class DebugSectionKind : uint8_t { constexpr static size_t SectionKindsNum = static_cast(DebugSectionKind::NumberOfEnumEntries); +static constexpr StringLiteral SectionNames[SectionKindsNum] = { + "debug_info", "debug_line", "debug_frame", "debug_ranges", + "debug_rnglists", "debug_loc", "debug_loclists", "debug_aranges", + "debug_abbrev", "debug_macinfo", "debug_macro", "debug_addr", + "debug_str", "debug_line_str", "debug_str_offsets", "debug_pubnames", + "debug_pubtypes", "debug_names", "apple_names", "apple_namespac", + "apple_objc", "apple_types"}; + +static constexpr const StringLiteral & +getSectionName(DebugSectionKind SectionKind) { + return SectionNames[static_cast(SectionKind)]; +} + /// Recognise the table name and match it with the DebugSectionKind. std::optional parseDebugTableName(StringRef Name); -/// Return the name of the section. -const StringLiteral &getSectionName(DebugSectionKind SectionKind); - /// There are fields(sizes, offsets) which should be updated after /// sections are generated. To remember offsets and related data /// the descendants of SectionPatch structure should be used. @@ -498,7 +509,8 @@ protected: SectionsSetTy SectionDescriptors; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_OUTPUTSECTIONS_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_OUTPUTSECTIONS_H diff --git a/llvm/lib/DWARFLinkerParallel/StringEntryToDwarfStringPoolEntryMap.h b/llvm/lib/DWARFLinker/Parallel/StringEntryToDwarfStringPoolEntryMap.h similarity index 84% rename from llvm/lib/DWARFLinkerParallel/StringEntryToDwarfStringPoolEntryMap.h rename to llvm/lib/DWARFLinker/Parallel/StringEntryToDwarfStringPoolEntryMap.h index b4c74d0adba9..858f224777db 100644 --- a/llvm/lib/DWARFLinkerParallel/StringEntryToDwarfStringPoolEntryMap.h +++ b/llvm/lib/DWARFLinker/Parallel/StringEntryToDwarfStringPoolEntryMap.h @@ -6,15 +6,16 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_STRINGENTRYTODWARFSTRINGPOOLENTRYMAP_H -#define LLVM_LIB_DWARFLINKERPARALLEL_STRINGENTRYTODWARFSTRINGPOOLENTRYMAP_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_STRINGENTRYTODWARFSTRINGPOOLENTRYMAP_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_STRINGENTRYTODWARFSTRINGPOOLENTRYMAP_H #include "DWARFLinkerGlobalData.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/DWARFLinkerParallel/StringPool.h" +#include "llvm/DWARFLinker/StringPool.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This class creates a DwarfStringPoolEntry for the corresponding StringEntry. class StringEntryToDwarfStringPoolEntryMap { @@ -66,7 +67,8 @@ protected: LinkingGlobalData &GlobalData; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_STRINGENTRYTODWARFSTRINGPOOLENTRYMAP_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_STRINGENTRYTODWARFSTRINGPOOLENTRYMAP_H diff --git a/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.cpp b/llvm/lib/DWARFLinker/Parallel/SyntheticTypeNameBuilder.cpp similarity index 99% rename from llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.cpp rename to llvm/lib/DWARFLinker/Parallel/SyntheticTypeNameBuilder.cpp index a9b4478e33c4..1554946c2c04 100644 --- a/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.cpp +++ b/llvm/lib/DWARFLinker/Parallel/SyntheticTypeNameBuilder.cpp @@ -12,8 +12,9 @@ #include "llvm/DebugInfo/DWARF/DWARFDebugInfoEntry.h" #include "llvm/Support/ScopedPrinter.h" -namespace llvm { -namespace dwarflinker_parallel { +using namespace llvm; +using namespace dwarf_linker; +using namespace dwarf_linker::parallel; Error SyntheticTypeNameBuilder::assignName( UnitEntryPairTy InputUnitEntryPair, @@ -762,6 +763,3 @@ OrderedChildrenIndexAssigner::getChildIndex( OrderedChildIdxs[*ArrayIndex]++; return Result; } - -} // end of namespace dwarflinker_parallel -} // namespace llvm diff --git a/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.h b/llvm/lib/DWARFLinker/Parallel/SyntheticTypeNameBuilder.h similarity index 94% rename from llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.h rename to llvm/lib/DWARFLinker/Parallel/SyntheticTypeNameBuilder.h index c9dce4e94fb0..8465c0d77b9c 100644 --- a/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.h +++ b/llvm/lib/DWARFLinker/Parallel/SyntheticTypeNameBuilder.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===/ -#ifndef LLVM_LIB_DWARFLINKERNEXT_SYNTHETICTYPENAMEBUILDER_H -#define LLVM_LIB_DWARFLINKERNEXT_SYNTHETICTYPENAMEBUILDER_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_SYNTHETICTYPENAMEBUILDER_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_SYNTHETICTYPENAMEBUILDER_H #include "DWARFLinkerCompileUnit.h" #include "DWARFLinkerGlobalData.h" @@ -17,7 +17,8 @@ namespace llvm { class DWARFDebugInfoEntry; -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { struct LinkContext; class TypeTableUnit; class CompileUnit; @@ -149,7 +150,8 @@ protected: OrderedChildrenIndexesArrayTy ChildIndexesWidth = {0}; }; -} // end namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERNEXT_SYNTHETICTYPENAMEBUILDER_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_SYNTHETICTYPENAMEBUILDER_H diff --git a/llvm/lib/DWARFLinkerParallel/TypePool.h b/llvm/lib/DWARFLinker/Parallel/TypePool.h similarity index 84% rename from llvm/lib/DWARFLinkerParallel/TypePool.h rename to llvm/lib/DWARFLinker/Parallel/TypePool.h index bbb3261027ce..547532977262 100644 --- a/llvm/lib/DWARFLinkerParallel/TypePool.h +++ b/llvm/lib/DWARFLinker/Parallel/TypePool.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DWARFLINKERPARALLEL_TYPEPOOL_H -#define LLVM_DWARFLINKERPARALLEL_TYPEPOOL_H +#ifndef LLVM_DWARFLINKER_PARALLEL_TYPEPOOL_H +#define LLVM_DWARFLINKER_PARALLEL_TYPEPOOL_H #include "ArrayList.h" #include "llvm/ADT/ConcurrentHashtable.h" @@ -17,7 +17,8 @@ #include namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { class TypePool; class CompileUnit; @@ -41,7 +42,8 @@ public: bool hasOnlyDeclaration() const { return Die == nullptr; } /// Creates type DIE for the specified name. - static TypeEntryBody *create(parallel::PerThreadBumpPtrAllocator &Allocator) { + static TypeEntryBody * + create(llvm::parallel::PerThreadBumpPtrAllocator &Allocator) { TypeEntryBody *Result = Allocator.Allocate(); new (Result) TypeEntryBody(Allocator); return Result; @@ -72,7 +74,7 @@ protected: TypeEntryBody &operator=(const TypeEntryBody &RHS) = delete; TypeEntryBody &operator=(const TypeEntryBody &&RHS) = delete; - TypeEntryBody(parallel::PerThreadBumpPtrAllocator &Allocator) + TypeEntryBody(llvm::parallel::PerThreadBumpPtrAllocator &Allocator) : Children(&Allocator) {} }; @@ -95,20 +97,22 @@ public: /// \returns newly created object of KeyDataTy type. static inline TypeEntry * - create(const StringRef &Key, parallel::PerThreadBumpPtrAllocator &Allocator) { + create(const StringRef &Key, + llvm::parallel::PerThreadBumpPtrAllocator &Allocator) { return TypeEntry::create(Key, Allocator); } }; /// TypePool keeps type descriptors which contain partially cloned DIE /// correspinding to each type. Types are identified by names. -class TypePool : ConcurrentHashTableByPtr { +class TypePool + : ConcurrentHashTableByPtr { public: TypePool() : ConcurrentHashTableByPtr(Allocator) { Root = TypeEntry::create("", Allocator); Root->getValue().store(TypeEntryBody::create(Allocator)); @@ -116,7 +120,7 @@ public: TypeEntry *insert(StringRef Name) { return ConcurrentHashTableByPtr::insert(Name) .first; } @@ -168,10 +172,11 @@ protected: TypeEntry *Root = nullptr; private: - parallel::PerThreadBumpPtrAllocator Allocator; + llvm::parallel::PerThreadBumpPtrAllocator Allocator; }; -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_DWARFLINKERPARALLEL_TYPEPOOL_H +#endif // LLVM_DWARFLINKER_PARALLEL_TYPEPOOL_H diff --git a/llvm/lib/DWARFLinkerParallel/Utils.h b/llvm/lib/DWARFLinker/Parallel/Utils.h similarity index 81% rename from llvm/lib/DWARFLinkerParallel/Utils.h rename to llvm/lib/DWARFLinker/Parallel/Utils.h index 91f9dca46a82..3c05b2ea173d 100644 --- a/llvm/lib/DWARFLinkerParallel/Utils.h +++ b/llvm/lib/DWARFLinker/Parallel/Utils.h @@ -6,13 +6,14 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKERPARALLEL_UTILS_H -#define LLVM_LIB_DWARFLINKERPARALLEL_UTILS_H +#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_UTILS_H +#define LLVM_LIB_DWARFLINKER_PARALLEL_UTILS_H #include "llvm/Support/Error.h" namespace llvm { -namespace dwarflinker_parallel { +namespace dwarf_linker { +namespace parallel { /// This function calls \p Iteration() until it returns false. /// If number of iterations exceeds \p MaxCounter then an Error is returned. @@ -34,7 +35,8 @@ inline Error finiteLoop(function_ref()> Iteration, return createStringError(std::errc::invalid_argument, "Infinite recursion"); } -} // end of namespace dwarflinker_parallel -} // end namespace llvm +} // end of namespace parallel +} // end of namespace dwarf_linker +} // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKERPARALLEL_UTILS_H +#endif // LLVM_LIB_DWARFLINKER_PARALLEL_UTILS_H diff --git a/llvm/lib/DWARFLinkerParallel/StringPool.cpp b/llvm/lib/DWARFLinker/Utils.cpp similarity index 68% rename from llvm/lib/DWARFLinkerParallel/StringPool.cpp rename to llvm/lib/DWARFLinker/Utils.cpp index fbff6b05e3a5..e8b0fe303aae 100644 --- a/llvm/lib/DWARFLinkerParallel/StringPool.cpp +++ b/llvm/lib/DWARFLinker/Utils.cpp @@ -1,9 +1,7 @@ -//=== StringPool.cpp ------------------------------------------------------===// +//===- Utils.cpp ------------------------------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// - -#include "llvm/DWARFLinkerParallel/StringPool.h" diff --git a/llvm/lib/DWARFLinkerParallel/DWARFFile.cpp b/llvm/lib/DWARFLinkerParallel/DWARFFile.cpp deleted file mode 100644 index 5a3486e6398d..000000000000 --- a/llvm/lib/DWARFLinkerParallel/DWARFFile.cpp +++ /dev/null @@ -1,17 +0,0 @@ -//=== DWARFFile.cpp -------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "llvm/DWARFLinkerParallel/DWARFFile.h" -#include "DWARFLinkerGlobalData.h" - -llvm::dwarflinker_parallel::DWARFFile::DWARFFile( - StringRef Name, std::unique_ptr Dwarf, - std::unique_ptr Addresses, - DWARFFile::UnloadCallbackTy UnloadFunc) - : FileName(Name), Dwarf(std::move(Dwarf)), Addresses(std::move(Addresses)), - UnloadFunc(UnloadFunc) {} diff --git a/llvm/tools/dsymutil/CMakeLists.txt b/llvm/tools/dsymutil/CMakeLists.txt index c612bfd9150c..0e407f6fa1db 100644 --- a/llvm/tools/dsymutil/CMakeLists.txt +++ b/llvm/tools/dsymutil/CMakeLists.txt @@ -9,6 +9,7 @@ set(LLVM_LINK_COMPONENTS AsmPrinter CodeGen CodeGenTypes + DWARFLinkerBase DWARFLinker DWARFLinkerParallel DebugInfoDWARF diff --git a/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp b/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp index 33d053c745b0..89a15e5916e2 100644 --- a/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp +++ b/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp @@ -27,8 +27,9 @@ #include "llvm/CodeGen/DIE.h" #include "llvm/CodeGen/NonRelocatableStringpool.h" #include "llvm/Config/config.h" -#include "llvm/DWARFLinker/DWARFLinkerDeclContext.h" -#include "llvm/DWARFLinkerParallel/DWARFLinker.h" +#include "llvm/DWARFLinker/Classic/DWARFLinker.h" +#include "llvm/DWARFLinker/Classic/DWARFStreamer.h" +#include "llvm/DWARFLinker/Parallel/DWARFLinker.h" #include "llvm/DebugInfo/DIContext.h" #include "llvm/DebugInfo/DWARF/DWARFAbbreviationDeclaration.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" @@ -100,6 +101,8 @@ namespace llvm { static mc::RegisterMCTargetOptionsFlags MOF; +using namespace dwarf_linker; + namespace dsymutil { static void dumpDIE(const DWARFDie *DIE, bool Verbose) { @@ -185,10 +188,8 @@ static Error remarksErrorHandler(const DebugMapObject &DMO, return createFileError(FE->getFileName(), std::move(NewE)); } -template Error DwarfLinkerForBinary::emitRelocations( - const DebugMap &DM, - std::vector> &ObjectsForLinking) { + const DebugMap &DM, std::vector &ObjectsForLinking) { // Return early if the "Resources" directory is not being written to. if (!Options.ResourceDir) return Error::success(); @@ -262,13 +263,12 @@ static Error emitRemarks(const LinkOptions &Options, StringRef BinaryPath, return Error::success(); } -template -ErrorOr> DwarfLinkerForBinary::loadObject( +ErrorOr> DwarfLinkerForBinary::loadObject( const DebugMapObject &Obj, const DebugMap &DebugMap, remarks::RemarkLinker &RL, std::shared_ptr DLBRM) { auto ErrorOrObj = loadObject(Obj, DebugMap.getTriple()); - std::unique_ptr Res; + std::unique_ptr Res; if (ErrorOrObj) { auto Context = DWARFContext::create( @@ -285,9 +285,9 @@ ErrorOr> DwarfLinkerForBinary::loadObject( }); }); DLBRM->init(*Context); - Res = std::make_unique( + Res = std::make_unique( Obj.getObjectFilename(), std::move(Context), - std::make_unique(*this, *ErrorOrObj, Obj, DLBRM), + std::make_unique(*this, *ErrorOrObj, Obj, DLBRM), [&](StringRef FileName) { BinHolder.eraseObjectEntry(FileName); }); Error E = RL.link(*ErrorOrObj); @@ -309,7 +309,7 @@ static bool binaryHasStrippableSwiftReflectionSections( // need to copy them to the .dSYM. Only copy them for binaries where the // linker omitted the reflection metadata. if (!Map.getBinaryPath().empty() && - Options.FileType == DWARFLinker::OutputFileType::Object) { + Options.FileType == DWARFLinkerBase::OutputFileType::Object) { auto ObjectEntry = BinHolder.getObjectEntry(Map.getBinaryPath()); // If ObjectEntry or Object has an error, no binary exists, therefore no @@ -593,28 +593,10 @@ void DwarfLinkerForBinary::copySwiftReflectionMetadata( } bool DwarfLinkerForBinary::link(const DebugMap &Map) { - if (Options.DWARFLinkerType == DsymutilDWARFLinkerType::LLVM) { - dwarflinker_parallel::DWARFLinker::OutputFileType DWARFLinkerOutputType; - switch (Options.FileType) { - case DWARFLinker::OutputFileType::Object: - DWARFLinkerOutputType = - dwarflinker_parallel::DWARFLinker::OutputFileType::Object; - break; - - case DWARFLinker::OutputFileType::Assembly: - DWARFLinkerOutputType = - dwarflinker_parallel::DWARFLinker::OutputFileType::Assembly; - break; - } - - return linkImpl>( - Map, DWARFLinkerOutputType); - } + if (Options.DWARFLinkerType == DsymutilDWARFLinkerType::LLVM) + return linkImpl(Map, Options.FileType); - return linkImpl>( - Map, Options.FileType); + return linkImpl(Map, Options.FileType); } template @@ -645,11 +627,11 @@ void setAcceleratorTables(Linker &GeneralLinker, llvm_unreachable("All cases handled above!"); } -template +template bool DwarfLinkerForBinary::linkImpl( const DebugMap &Map, typename Linker::OutputFileType ObjectType) { - std::vector> ObjectsForLinking; + std::vector ObjectsForLinking; DebugMap DebugMap(Map.getTriple(), Map.getBinaryPath()); @@ -691,22 +673,22 @@ bool DwarfLinkerForBinary::linkImpl( GeneralLinker->setNumThreads(Options.Threads); GeneralLinker->setPrependPath(Options.PrependPath); GeneralLinker->setKeepFunctionForStatic(Options.KeepFunctionForStatic); - GeneralLinker->setInputVerificationHandler([&](const OutDwarfFile &File, llvm::StringRef Output) { - std::lock_guard Guard(ErrorHandlerMutex); - if (Options.Verbose) - errs() << Output; - warn("input verification failed", File.FileName); - HasVerificationErrors = true; - }); + GeneralLinker->setInputVerificationHandler( + [&](const DWARFFile &File, llvm::StringRef Output) { + std::lock_guard Guard(ErrorHandlerMutex); + if (Options.Verbose) + errs() << Output; + warn("input verification failed", File.FileName); + HasVerificationErrors = true; + }); auto Loader = [&](StringRef ContainerName, - StringRef Path) -> ErrorOr { + StringRef Path) -> ErrorOr { auto &Obj = DebugMap.addDebugMapObject( Path, sys::TimePoint(), MachO::N_OSO); auto DLBRelocMap = std::make_shared(); - if (ErrorOr> ErrorOrObj = - loadObject(Obj, DebugMap, RL, - DLBRelocMap)) { + if (ErrorOr> ErrorOrObj = + loadObject(Obj, DebugMap, RL, DLBRelocMap)) { ObjectsForLinking.emplace_back(std::move(*ErrorOrObj), DLBRelocMap); return *ObjectsForLinking.back().Object; } else { @@ -820,15 +802,15 @@ bool DwarfLinkerForBinary::linkImpl( } auto DLBRelocMap = std::make_shared(); - if (ErrorOr> ErrorOrObj = - loadObject(*Obj, Map, RL, DLBRelocMap)) { + if (ErrorOr> ErrorOrObj = + loadObject(*Obj, Map, RL, DLBRelocMap)) { ObjectsForLinking.emplace_back(std::move(*ErrorOrObj), DLBRelocMap); GeneralLinker->addObjectFile(*ObjectsForLinking.back().Object, Loader, OnCUDieLoaded); } else { ObjectsForLinking.push_back( - {std::make_unique(Obj->getObjectFilename(), nullptr, - nullptr), + {std::make_unique(Obj->getObjectFilename(), nullptr, + nullptr), DLBRelocMap}); GeneralLinker->addObjectFile(*ObjectsForLinking.back().Object); } @@ -855,8 +837,7 @@ bool DwarfLinkerForBinary::linkImpl( if (Options.NoOutput) return true; - if (Error E = - emitRelocations(Map, ObjectsForLinking)) + if (Error E = emitRelocations(Map, ObjectsForLinking)) return error(toString(std::move(E))); if (Options.ResourceDir && !ParseableSwiftInterfaces.empty()) { @@ -879,12 +860,9 @@ bool DwarfLinkerForBinary::linkImpl( /// Iterate over the relocations of the given \p Section and /// store the ones that correspond to debug map entries into the /// ValidRelocs array. -template -void DwarfLinkerForBinary::AddressManager:: - findValidRelocsMachO(const object::SectionRef &Section, - const object::MachOObjectFile &Obj, - const DebugMapObject &DMO, - std::vector &ValidRelocs) { +void DwarfLinkerForBinary::AddressManager::findValidRelocsMachO( + const object::SectionRef &Section, const object::MachOObjectFile &Obj, + const DebugMapObject &DMO, std::vector &ValidRelocs) { Expected ContentsOrErr = Section.getContents(); if (!ContentsOrErr) { consumeError(ContentsOrErr.takeError()); @@ -961,8 +939,7 @@ void DwarfLinkerForBinary::AddressManager:: /// Dispatch the valid relocation finding logic to the /// appropriate handler depending on the object file format. -template -bool DwarfLinkerForBinary::AddressManager::findValidRelocs( +bool DwarfLinkerForBinary::AddressManager::findValidRelocs( const object::SectionRef &Section, const object::ObjectFile &Obj, const DebugMapObject &DMO, std::vector &Relocs) { // Dispatch to the right handler depending on the file type. @@ -987,10 +964,8 @@ bool DwarfLinkerForBinary::AddressManager::findValidRelocs( /// entries in the debug map. These relocations will drive the Dwarf link by /// indicating which DIEs refer to symbols present in the linked binary. /// \returns whether there are any valid relocations in the debug info. -template -bool DwarfLinkerForBinary::AddressManager:: - findValidRelocsInDebugSections(const object::ObjectFile &Obj, - const DebugMapObject &DMO) { +bool DwarfLinkerForBinary::AddressManager::findValidRelocsInDebugSections( + const object::ObjectFile &Obj, const DebugMapObject &DMO) { // Find the debug_info section. bool FoundValidRelocs = false; for (const object::SectionRef &Section : Obj.sections()) { @@ -1011,9 +986,7 @@ bool DwarfLinkerForBinary::AddressManager:: return FoundValidRelocs; } -template -std::vector -DwarfLinkerForBinary::AddressManager::getRelocations( +std::vector DwarfLinkerForBinary::AddressManager::getRelocations( const std::vector &Relocs, uint64_t StartPos, uint64_t EndPos) { std::vector Res; @@ -1030,9 +1003,7 @@ DwarfLinkerForBinary::AddressManager::getRelocations( return Res; } -template -void DwarfLinkerForBinary::AddressManager::printReloc( - const ValidReloc &Reloc) { +void DwarfLinkerForBinary::AddressManager::printReloc(const ValidReloc &Reloc) { const auto &Mapping = Reloc.SymbolMapping; const uint64_t ObjectAddress = Mapping.ObjectAddress ? uint64_t(*Mapping.ObjectAddress) @@ -1043,18 +1014,16 @@ void DwarfLinkerForBinary::AddressManager::printReloc( uint64_t(Mapping.BinaryAddress)); } -template -int64_t DwarfLinkerForBinary::AddressManager::getRelocValue( - const ValidReloc &Reloc) { +int64_t +DwarfLinkerForBinary::AddressManager::getRelocValue(const ValidReloc &Reloc) { int64_t AddrAdjust = relocate(Reloc); if (Reloc.SymbolMapping.ObjectAddress) AddrAdjust -= uint64_t(*Reloc.SymbolMapping.ObjectAddress); return AddrAdjust; } -template std::optional -DwarfLinkerForBinary::AddressManager::hasValidRelocationAt( +DwarfLinkerForBinary::AddressManager::hasValidRelocationAt( const std::vector &AllRelocs, uint64_t StartOffset, uint64_t EndOffset) { std::vector Relocs = @@ -1089,11 +1058,10 @@ getAttributeOffsets(const DWARFAbbreviationDeclaration *Abbrev, unsigned Idx, return std::make_pair(Offset, End); } -template -std::optional DwarfLinkerForBinary::AddressManager:: - getExprOpAddressRelocAdjustment(DWARFUnit &U, - const DWARFExpression::Operation &Op, - uint64_t StartOffset, uint64_t EndOffset) { +std::optional +DwarfLinkerForBinary::AddressManager::getExprOpAddressRelocAdjustment( + DWARFUnit &U, const DWARFExpression::Operation &Op, uint64_t StartOffset, + uint64_t EndOffset) { switch (Op.getCode()) { default: { assert(false && "Specified operation does not have address operand"); @@ -1116,9 +1084,9 @@ std::optional DwarfLinkerForBinary::AddressManager:: return std::nullopt; } -template -std::optional DwarfLinkerForBinary::AddressManager< - AddressesMapBase>::getSubprogramRelocAdjustment(const DWARFDie &DIE) { +std::optional +DwarfLinkerForBinary::AddressManager::getSubprogramRelocAdjustment( + const DWARFDie &DIE) { const auto *Abbrev = DIE.getAbbreviationDeclarationPtr(); std::optional LowPcIdx = @@ -1158,25 +1126,19 @@ std::optional DwarfLinkerForBinary::AddressManager< } } -template -std::optional DwarfLinkerForBinary::AddressManager< - AddressesMapBase>::getLibraryInstallName() { +std::optional +DwarfLinkerForBinary::AddressManager::getLibraryInstallName() { return LibInstallName; } -template -uint64_t DwarfLinkerForBinary::AddressManager::relocate( - const ValidReloc &Reloc) const { +uint64_t +DwarfLinkerForBinary::AddressManager::relocate(const ValidReloc &Reloc) const { return Reloc.SymbolMapping.BinaryAddress + Reloc.Addend; } -template -void DwarfLinkerForBinary::AddressManager< - AddressesMapBase>::updateAndSaveValidRelocs(bool IsDWARF5, - uint64_t OriginalUnitOffset, - int64_t LinkedOffset, - uint64_t StartOffset, - uint64_t EndOffset) { +void DwarfLinkerForBinary::AddressManager::updateAndSaveValidRelocs( + bool IsDWARF5, uint64_t OriginalUnitOffset, int64_t LinkedOffset, + uint64_t StartOffset, uint64_t EndOffset) { std::vector InRelocs = getRelocations(ValidDebugInfoRelocs, StartOffset, EndOffset); if (IsDWARF5) @@ -1185,10 +1147,8 @@ void DwarfLinkerForBinary::AddressManager< IsDWARF5, InRelocs, OriginalUnitOffset, LinkedOffset); } -template -void DwarfLinkerForBinary::AddressManager:: - updateRelocationsWithUnitOffset(uint64_t OriginalUnitOffset, - uint64_t OutputUnitOffset) { +void DwarfLinkerForBinary::AddressManager::updateRelocationsWithUnitOffset( + uint64_t OriginalUnitOffset, uint64_t OutputUnitOffset) { DwarfLinkerRelocMap->updateRelocationsWithUnitOffset(OriginalUnitOffset, OutputUnitOffset); } @@ -1200,8 +1160,7 @@ void DwarfLinkerForBinary::AddressManager:: /// monotonic \p BaseOffset values. /// /// \returns whether any reloc has been applied. -template -bool DwarfLinkerForBinary::AddressManager::applyValidRelocs( +bool DwarfLinkerForBinary::AddressManager::applyValidRelocs( MutableArrayRef Data, uint64_t BaseOffset, bool IsLittleEndian) { std::vector Relocs = getRelocations( diff --git a/llvm/tools/dsymutil/DwarfLinkerForBinary.h b/llvm/tools/dsymutil/DwarfLinkerForBinary.h index 328cd9197d0d..052c6a899fd7 100644 --- a/llvm/tools/dsymutil/DwarfLinkerForBinary.h +++ b/llvm/tools/dsymutil/DwarfLinkerForBinary.h @@ -14,10 +14,6 @@ #include "LinkUtils.h" #include "MachOUtils.h" #include "RelocationMap.h" -#include "llvm/DWARFLinker/DWARFLinker.h" -#include "llvm/DWARFLinker/DWARFLinkerCompileUnit.h" -#include "llvm/DWARFLinker/DWARFLinkerDeclContext.h" -#include "llvm/DWARFLinker/DWARFStreamer.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/Remarks/RemarkFormat.h" #include "llvm/Remarks/RemarkLinker.h" @@ -25,6 +21,8 @@ #include namespace llvm { +using namespace dwarf_linker; + namespace dsymutil { /// DwarfLinkerForBinaryRelocationMap contains the logic to handle the @@ -55,12 +53,12 @@ public: DwarfLinkerForBinaryRelocationMap() = default; }; -template struct ObjectWithRelocMap { +struct ObjectWithRelocMap { ObjectWithRelocMap( - std::unique_ptr Object, + std::unique_ptr Object, std::shared_ptr OutRelocs) : Object(std::move(Object)), OutRelocs(OutRelocs) {} - std::unique_ptr Object; + std::unique_ptr Object; std::shared_ptr OutRelocs; }; @@ -104,8 +102,7 @@ public: private: /// Keeps track of relocations. - template - class AddressManager : public AddressesMapBase { + class AddressManager : public dwarf_linker::AddressesMap { const DwarfLinkerForBinary &Linker; @@ -241,8 +238,7 @@ private: /// Attempt to load a debug object from disk. ErrorOr loadObject(const DebugMapObject &Obj, const Triple &triple); - template - ErrorOr> + ErrorOr> loadObject(const DebugMapObject &Obj, const DebugMap &DebugMap, remarks::RemarkLinker &RL, std::shared_ptr DLBRM); @@ -264,14 +260,12 @@ private: std::vector &RelocationsToApply); - template + template bool linkImpl(const DebugMap &Map, typename Linker::OutputFileType ObjectType); - template - Error emitRelocations( - const DebugMap &DM, - std::vector> &ObjectsForLinking); + Error emitRelocations(const DebugMap &DM, + std::vector &ObjectsForLinking); raw_fd_ostream &OutFile; BinaryHolder &BinHolder; diff --git a/llvm/tools/dsymutil/LinkUtils.h b/llvm/tools/dsymutil/LinkUtils.h index 0bf6d9aac1a3..97785dd872f5 100644 --- a/llvm/tools/dsymutil/LinkUtils.h +++ b/llvm/tools/dsymutil/LinkUtils.h @@ -16,8 +16,8 @@ #include "llvm/Support/VirtualFileSystem.h" #include "llvm/Support/WithColor.h" -#include "llvm/DWARFLinker/DWARFLinker.h" -#include "llvm/DWARFLinker/DWARFStreamer.h" +#include "llvm/DWARFLinker/Classic/DWARFLinker.h" +#include "llvm/DWARFLinker/Classic/DWARFStreamer.h" #include namespace llvm { @@ -72,7 +72,8 @@ struct LinkOptions { unsigned Threads = 1; // Output file type. - DWARFLinker::OutputFileType FileType = DWARFLinker::OutputFileType::Object; + dwarf_linker::DWARFLinkerBase::OutputFileType FileType = + dwarf_linker::DWARFLinkerBase::OutputFileType::Object; /// The accelerator table kind DsymutilAccelTableKind TheAccelTableKind; diff --git a/llvm/tools/dsymutil/dsymutil.cpp b/llvm/tools/dsymutil/dsymutil.cpp index 2dd123318e00..a461d9e20a21 100644 --- a/llvm/tools/dsymutil/dsymutil.cpp +++ b/llvm/tools/dsymutil/dsymutil.cpp @@ -55,6 +55,7 @@ using namespace llvm; using namespace llvm::dsymutil; using namespace object; +using namespace llvm::dwarf_linker; namespace { enum ID { @@ -373,7 +374,7 @@ static Expected getOptions(opt::InputArgList &Args) { Options.Toolchain = Toolchain->getValue(); if (Args.hasArg(OPT_assembly)) - Options.LinkOpts.FileType = DWARFLinker::OutputFileType::Assembly; + Options.LinkOpts.FileType = DWARFLinkerBase::OutputFileType::Assembly; if (opt::Arg *NumThreads = Args.getLastArg(OPT_threads)) Options.LinkOpts.Threads = atoi(NumThreads->getValue()); diff --git a/llvm/tools/llvm-dwarfutil/CMakeLists.txt b/llvm/tools/llvm-dwarfutil/CMakeLists.txt index b2585799b10c..91b25207b4f7 100644 --- a/llvm/tools/llvm-dwarfutil/CMakeLists.txt +++ b/llvm/tools/llvm-dwarfutil/CMakeLists.txt @@ -7,6 +7,7 @@ set(LLVM_LINK_COMPONENTS AllTargetsDescs AllTargetsInfos CodeGenTypes + DWARFLinkerBase DWARFLinker DWARFLinkerParallel DebugInfoDWARF diff --git a/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp b/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp index 02a94596ec76..d6504992b56e 100644 --- a/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp +++ b/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp @@ -9,9 +9,9 @@ #include "DebugInfoLinker.h" #include "Error.h" #include "llvm/ADT/StringSwitch.h" -#include "llvm/DWARFLinker/DWARFLinker.h" -#include "llvm/DWARFLinker/DWARFStreamer.h" -#include "llvm/DWARFLinkerParallel/DWARFLinker.h" +#include "llvm/DWARFLinker/Classic/DWARFLinker.h" +#include "llvm/DWARFLinker/Classic/DWARFStreamer.h" +#include "llvm/DWARFLinker/Parallel/DWARFLinker.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFExpression.h" #include "llvm/Object/ObjectFile.h" @@ -19,6 +19,8 @@ #include namespace llvm { +using namespace dwarf_linker; + namespace dwarfutil { // ObjFileAddressMap allows to check whether specified DIE referencing @@ -37,8 +39,7 @@ namespace dwarfutil { // exec: [LowPC, HighPC] is not inside address ranges of .text sections // // universal: maxpc and bfd -template -class ObjFileAddressMap : public AddressMapBase { +class ObjFileAddressMap : public AddressesMap { public: ObjFileAddressMap(DWARFContext &Context, const Options &Options, object::ObjectFile &ObjFile) @@ -298,7 +299,7 @@ static std::string getMessageForDeletedAcceleratorTables( return Message; } -template +template Error linkDebugInfoImpl(object::ObjectFile &File, const Options &Options, raw_pwrite_stream &OutStream) { std::mutex ErrorHandlerMutex; @@ -345,7 +346,7 @@ Error linkDebugInfoImpl(object::ObjectFile &File, const Options &Options, DebugInfoLinker->setVerbosity(Options.Verbose); DebugInfoLinker->setUpdateIndexTablesOnly(!Options.DoGarbageCollection); - std::vector> ObjectsForLinking(1); + std::vector> ObjectsForLinking(1); // Add object files to the DWARFLinker. std::unique_ptr Context = DWARFContext::create( @@ -360,11 +361,10 @@ Error linkDebugInfoImpl(object::ObjectFile &File, const Options &Options, ReportWarn(Info.message(), "", nullptr); }); }); - std::unique_ptr> AddressesMap( - std::make_unique>(*Context, Options, - File)); + std::unique_ptr AddressesMap( + std::make_unique(*Context, Options, File)); - ObjectsForLinking[0] = std::make_unique( + ObjectsForLinking[0] = std::make_unique( File.getFileName(), std::move(Context), std::move(AddressesMap)); uint16_t MaxDWARFVersion = 0; @@ -400,7 +400,7 @@ Error linkDebugInfoImpl(object::ObjectFile &File, const Options &Options, for (typename Linker::AccelTableKind Table : AccelTables) DebugInfoLinker->addAccelTableKind(Table); - for (std::unique_ptr &CurFile : ObjectsForLinking) { + for (std::unique_ptr &CurFile : ObjectsForLinking) { SmallVector AccelTableNamesToReplace; SmallVector AccelTableNamesToDelete; @@ -452,13 +452,9 @@ Error linkDebugInfoImpl(object::ObjectFile &File, const Options &Options, Error linkDebugInfo(object::ObjectFile &File, const Options &Options, raw_pwrite_stream &OutStream) { if (Options.UseLLVMDWARFLinker) - return linkDebugInfoImpl(File, Options, - OutStream); + return linkDebugInfoImpl(File, Options, OutStream); else - return linkDebugInfoImpl( - File, Options, OutStream); + return linkDebugInfoImpl(File, Options, OutStream); } } // end of namespace dwarfutil diff --git a/llvm/unittests/DWARFLinkerParallel/StringPoolTest.cpp b/llvm/unittests/DWARFLinkerParallel/StringPoolTest.cpp index 84199f696a59..2612e763648b 100644 --- a/llvm/unittests/DWARFLinkerParallel/StringPoolTest.cpp +++ b/llvm/unittests/DWARFLinkerParallel/StringPoolTest.cpp @@ -6,13 +6,13 @@ // //===----------------------------------------------------------------------===// -#include "llvm/DWARFLinkerParallel/StringPool.h" +#include "llvm/DWARFLinker/StringPool.h" #include "llvm/Support/Parallel.h" #include "gtest/gtest.h" #include using namespace llvm; -using namespace dwarflinker_parallel; +using namespace dwarf_linker; namespace { -- GitLab From db78c30ba772af1466bb0d0c1d376c8e642ee4a9 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 9 Jan 2024 15:33:51 +0700 Subject: [PATCH 166/652] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (#76942) toFeatures and toFeatureVector both output a list of target feature flags, just with a slightly different interface. toFeatures keeps any unsupported extensions, and also provides a way to append negative extensions (AddAllExtensions=true). This patch combines them into one function, so that a later patch will be be able to get a std::vector of features that includes all the negative extensions, which was previously only possible through the StrAlloc interface. --- clang/lib/Basic/Targets/RISCV.cpp | 4 +- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 +-- llvm/include/llvm/Support/RISCVISAInfo.h | 6 +-- llvm/lib/Object/ELFObjectFile.cpp | 2 +- llvm/lib/Support/RISCVISAInfo.cpp | 41 +++++++-------------- llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 ++++++++++++--- 6 files changed, 47 insertions(+), 42 deletions(-) diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 59ae12eed940..daaa8639ae83 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -296,7 +296,7 @@ bool RISCVTargetInfo::initFeatureMap( } // RISCVISAInfo makes implications for ISA features - std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector(); + std::vector ImpliedFeatures = (*ParseResult)->toFeatures(); // parseFeatures normalizes the feature set by dropping any explicit // negatives, and non-extension features. We need to preserve the later @@ -413,7 +413,7 @@ static void handleFullArchString(StringRef FullArchStr, // Forward the invalid FullArchStr. Features.push_back("+" + FullArchStr.str()); } else { - std::vector FeatStrings = (*RII)->toFeatureVector(); + std::vector FeatStrings = (*RII)->toFeatures(); Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end()); } } diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 0717e3b813e1..16a8b3cc42ba 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch, return false; } - (*ISAInfo)->toFeatures( - Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); }, - /*AddAllExtensions=*/true); + for (const std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true, + /*IgnoreUnknown=*/false)) + Features.push_back(Args.MakeArgString(Str)); if (EnableExperimentalExtensions) Features.push_back(Args.MakeArgString("+experimental")); diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h index 09c4edd6df60..c539448683d3 100644 --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/Support/RISCVISAInfo.h @@ -68,9 +68,8 @@ public: parseFeatures(unsigned XLen, const std::vector &Features); /// Convert RISC-V ISA info to a feature vector. - void toFeatures(std::vector &Features, - llvm::function_ref StrAlloc, - bool AddAllExtensions) const; + std::vector toFeatures(bool AddAllExtensions = false, + bool IgnoreUnknown = true) const; const OrderedExtensionMap &getExtensions() const { return Exts; }; @@ -83,7 +82,6 @@ public: bool hasExtension(StringRef Ext) const; std::string toString() const; - std::vector toFeatureVector() const; StringRef computeDefaultABI() const; static bool isSupportedExtensionFeature(StringRef Ext); diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index 95c4f9f8545d..ae21b81c10c8 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -315,7 +315,7 @@ Expected ELFObjectFileBase::getRISCVFeatures() const { else llvm_unreachable("XLEN should be 32 or 64."); - Features.addFeaturesVector(ISAInfo->toFeatureVector()); + Features.addFeaturesVector(ISAInfo->toFeatures()); } return Features; diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index a9b7e209915a..70f531e40b90 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -466,35 +466,38 @@ bool RISCVISAInfo::compareExtension(const std::string &LHS, return LHS < RHS; } -void RISCVISAInfo::toFeatures( - std::vector &Features, - llvm::function_ref StrAlloc, - bool AddAllExtensions) const { - for (auto const &Ext : Exts) { - StringRef ExtName = Ext.first; - +std::vector RISCVISAInfo::toFeatures(bool AddAllExtensions, + bool IgnoreUnknown) const { + std::vector Features; + for (const auto &[ExtName, _] : Exts) { + // i is a base instruction set, not an extension (see + // https://github.com/riscv/riscv-isa-manual/blob/main/src/naming.adoc#base-integer-isa) + // and is not recognized in clang -cc1 if (ExtName == "i") continue; + if (IgnoreUnknown && !isSupportedExtension(ExtName)) + continue; if (isExperimentalExtension(ExtName)) { - Features.push_back(StrAlloc("+experimental-" + ExtName)); + Features.push_back((llvm::Twine("+experimental-") + ExtName).str()); } else { - Features.push_back(StrAlloc("+" + ExtName)); + Features.push_back((llvm::Twine("+") + ExtName).str()); } } if (AddAllExtensions) { for (const RISCVSupportedExtension &Ext : SupportedExtensions) { if (Exts.count(Ext.Name)) continue; - Features.push_back(StrAlloc(Twine("-") + Ext.Name)); + Features.push_back((llvm::Twine("-") + Ext.Name).str()); } for (const RISCVSupportedExtension &Ext : SupportedExperimentalExtensions) { if (Exts.count(Ext.Name)) continue; - Features.push_back(StrAlloc(Twine("-experimental-") + Ext.Name)); + Features.push_back((llvm::Twine("-experimental-") + Ext.Name).str()); } } + return Features; } // Extensions may have a version number, and may be separated by @@ -1269,22 +1272,6 @@ std::string RISCVISAInfo::toString() const { return Arch.str(); } -std::vector RISCVISAInfo::toFeatureVector() const { - std::vector FeatureVector; - for (auto const &Ext : Exts) { - std::string ExtName = Ext.first; - if (ExtName == "i") // i is not recognized in clang -cc1 - continue; - if (!isSupportedExtension(ExtName)) - continue; - std::string Feature = isExperimentalExtension(ExtName) - ? "+experimental-" + ExtName - : "+" + ExtName; - FeatureVector.push_back(Feature); - } - return FeatureVector; -} - llvm::Expected> RISCVISAInfo::postProcessAndChecking(std::unique_ptr &&ISAInfo) { ISAInfo->updateImplication(); diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 7463824b5b52..42759f30fd1b 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -477,25 +477,45 @@ TEST(ParseArchString, RejectsConflictingExtensions) { } } -TEST(ToFeatureVector, IIsDroppedAndExperimentalExtensionsArePrefixed) { +TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) { auto MaybeISAInfo1 = RISCVISAInfo::parseArchString("rv64im_zicond", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded()); - EXPECT_THAT((*MaybeISAInfo1)->toFeatureVector(), + EXPECT_THAT((*MaybeISAInfo1)->toFeatures(), ElementsAre("+m", "+experimental-zicond")); auto MaybeISAInfo2 = RISCVISAInfo::parseArchString( "rv32e_zicond_xventanacondops", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); - EXPECT_THAT((*MaybeISAInfo2)->toFeatureVector(), + EXPECT_THAT((*MaybeISAInfo2)->toFeatures(), ElementsAre("+e", "+experimental-zicond", "+xventanacondops")); } -TEST(ToFeatureVector, UnsupportedExtensionsAreDropped) { +TEST(ToFeatures, UnsupportedExtensionsAreDropped) { auto MaybeISAInfo = RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0_xmadeup1p0"); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - EXPECT_THAT((*MaybeISAInfo)->toFeatureVector(), ElementsAre("+m")); + EXPECT_THAT((*MaybeISAInfo)->toFeatures(), ElementsAre("+m")); +} + +TEST(ToFeatures, UnsupportedExtensionsAreKeptIfIgnoreUnknownIsFalse) { + auto MaybeISAInfo = + RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0_xmadeup1p0"); + ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); + EXPECT_THAT((*MaybeISAInfo)->toFeatures(false, false), + ElementsAre("+m", "+xmadeup")); +} + +TEST(ToFeatures, AddAllExtensionsAddsNegativeExtensions) { + auto MaybeISAInfo = RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0"); + ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); + + auto Features = (*MaybeISAInfo)->toFeatures(true); + EXPECT_GT(Features.size(), 1UL); + EXPECT_EQ(Features.front(), "+m"); + // Every feature after should be a negative feature + for (auto &NegativeExt : llvm::drop_begin(Features)) + EXPECT_TRUE(NegativeExt.substr(0, 1) == "-"); } TEST(OrderedExtensionMap, ExtensionsAreCorrectlyOrdered) { -- GitLab From ae5575db1561c0606582346d5f0cbc799c1c02f3 Mon Sep 17 00:00:00 2001 From: Benjamin Maxwell Date: Tue, 9 Jan 2024 09:05:31 +0000 Subject: [PATCH 167/652] [mlir][ArmSME] Add `arm_sme.intr.cnts(b|h|w|d)` intrinsics (#77319) This adds MLIR versions of the Arm streaming vector length intrinsics. These allow reading the streaming vector length regardless of the streaming mode. --- .../mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td | 13 +++++++++++++ mlir/test/Target/LLVMIR/arm-sme-invalid.mlir | 8 ++++++++ mlir/test/Target/LLVMIR/arm-sme.mlir | 14 ++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td index 4d96e04c886f..d85ef963ae5d 100644 --- a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td +++ b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td @@ -187,4 +187,17 @@ def LLVM_aarch64_sme_write_vert : LLVM_aarch64_sme_write<"vert">; def LLVM_aarch64_sme_read_horiz : LLVM_aarch64_sme_read<"horiz">; def LLVM_aarch64_sme_read_vert : LLVM_aarch64_sme_read<"vert">; +class ArmSME_IntrCountOp + : ArmSME_IntrOp>], + /*numResults=*/1, /*overloadedResults=*/[]>; + +def LLVM_aarch64_sme_cntsb : ArmSME_IntrCountOp<"cntsb">; +def LLVM_aarch64_sme_cntsh : ArmSME_IntrCountOp<"cntsh">; +def LLVM_aarch64_sme_cntsw : ArmSME_IntrCountOp<"cntsw">; +def LLVM_aarch64_sme_cntsd : ArmSME_IntrCountOp<"cntsd">; + #endif // ARMSME_INTRINSIC_OPS diff --git a/mlir/test/Target/LLVMIR/arm-sme-invalid.mlir b/mlir/test/Target/LLVMIR/arm-sme-invalid.mlir index 7c9976bed912..14821da83872 100644 --- a/mlir/test/Target/LLVMIR/arm-sme-invalid.mlir +++ b/mlir/test/Target/LLVMIR/arm-sme-invalid.mlir @@ -31,3 +31,11 @@ llvm.func @arm_sme_tile_slice_to_vector_invalid_element_types( (vector<[4]xf32>, vector<[4]xi1>, i32) -> vector<[4]xi32> llvm.return %res : vector<[4]xi32> } + +// ----- + +llvm.func @arm_sme_streaming_vl_invalid_return_type() -> i32 { + // expected-error @+1 {{failed to verify that `res` is i64}} + %res = "arm_sme.intr.cntsb"() : () -> i32 + llvm.return %res : i32 +} diff --git a/mlir/test/Target/LLVMIR/arm-sme.mlir b/mlir/test/Target/LLVMIR/arm-sme.mlir index edc1f7491304..7a42033dc04b 100644 --- a/mlir/test/Target/LLVMIR/arm-sme.mlir +++ b/mlir/test/Target/LLVMIR/arm-sme.mlir @@ -403,3 +403,17 @@ llvm.func @arm_sme_tile_slice_to_vector_vert(%tileslice : i32, : (vector<[2]xf64>, vector<[2]xi1>, i32) -> vector<[2]xf64> llvm.return } + +// ----- + +llvm.func @arm_sme_streaming_vl() { + // CHECK: call i64 @llvm.aarch64.sme.cntsb() + %svl_b = "arm_sme.intr.cntsb"() : () -> i64 + // CHECK: call i64 @llvm.aarch64.sme.cntsh() + %svl_h = "arm_sme.intr.cntsh"() : () -> i64 + // CHECK: call i64 @llvm.aarch64.sme.cntsw() + %svl_w = "arm_sme.intr.cntsw"() : () -> i64 + // CHECK: call i64 @llvm.aarch64.sme.cntsd() + %svl_d = "arm_sme.intr.cntsd"() : () -> i64 + llvm.return +} -- GitLab From b59b8d418279f20275ece99bb6c31b1417a7bd80 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 9 Jan 2024 09:05:48 +0000 Subject: [PATCH 168/652] [AMDGPU] Add GFX12 S_WAIT_* instructions (#77336) GFX12 has separate wait instructions per counter e.g. S_WAIT_LOADCNT. S_WAITCNT still exists but is deprecated and codegen should stop using it. S_WAITCNT_* (e.g. S_WAITCNT_VSCNT) are removed. This patch adds/removes MC layer support for these instructions. --- llvm/lib/Target/AMDGPU/SOPInstructions.td | 42 ++++++++++++--- llvm/test/MC/AMDGPU/gfx11_asm_err.s | 5 ++ llvm/test/MC/AMDGPU/gfx12_asm_sopp.s | 54 +++++++++++++++++++ llvm/test/MC/AMDGPU/gfx12_unsupported.s | 12 +++++ .../MC/Disassembler/AMDGPU/decode-err.txt | 4 ++ .../Disassembler/AMDGPU/gfx12_dasm_sopp.txt | 54 +++++++++++++++++++ 6 files changed, 164 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 5f021307e18e..46fa3d57a21c 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1196,14 +1196,12 @@ let SubtargetPredicate = isGFX10Plus in { let SubtargetPredicate = isGFX10GFX11 in { def S_SUBVECTOR_LOOP_BEGIN : SOPK_32_BR<"s_subvector_loop_begin">; def S_SUBVECTOR_LOOP_END : SOPK_32_BR<"s_subvector_loop_end">; -} // End SubtargetPredicate = isGFX10GFX11 -let SubtargetPredicate = isGFX10Plus in { def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">; def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">; def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">; def S_WAITCNT_LGKMCNT : SOPK_WAITCNT<"s_waitcnt_lgkmcnt">; -} // End SubtargetPredicate = isGFX10Plus +} // End SubtargetPredicate = isGFX10GFX11 //===----------------------------------------------------------------------===// // SOPC Instructions @@ -1712,6 +1710,27 @@ let SubtargetPredicate = HasVGPRSingleUseHintInsts in { SOPP_Pseudo<"s_singleuse_vdst", (ins s16imm:$simm16), "$simm16">; } // End SubtargetPredicate = HasVGPRSingeUseHintInsts +let SubtargetPredicate = isGFX12Plus, hasSideEffects = 1 in { + def S_WAIT_LOADCNT : + SOPP_Pseudo<"s_wait_loadcnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_LOADCNT_DSCNT : + SOPP_Pseudo<"s_wait_loadcnt_dscnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_STORECNT : + SOPP_Pseudo<"s_wait_storecnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_STORECNT_DSCNT : + SOPP_Pseudo<"s_wait_storecnt_dscnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_SAMPLECNT : + SOPP_Pseudo<"s_wait_samplecnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_BVHCNT : + SOPP_Pseudo<"s_wait_bvhcnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_EXPCNT : + SOPP_Pseudo<"s_wait_expcnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_DSCNT : + SOPP_Pseudo<"s_wait_dscnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_KMCNT : + SOPP_Pseudo<"s_wait_kmcnt", (ins s16imm:$simm16), "$simm16">; +} // End SubtargetPredicate = isGFX12Plus, hasSideEffects = 1 + //===----------------------------------------------------------------------===// // SOP1 Patterns //===----------------------------------------------------------------------===// @@ -2421,10 +2440,10 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>; defm S_CALL_B64 : SOPK_Real32_gfx11_gfx12<0x014>; defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>; defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx11<0x017>; -defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11_gfx12<0x018>; -defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11_gfx12<0x019>; -defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11_gfx12<0x01a>; -defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11_gfx12<0x01b>; +defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11<0x018>; +defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11<0x019>; +defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11<0x01a>; +defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>; //===----------------------------------------------------------------------===// // SOPK - GFX10. @@ -2526,6 +2545,15 @@ multiclass SOPP_Real_32_Renamed_gfx12 op, SOPP_Pseudo backing_pseudo, st defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR, "s_wait_alu">; defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>; defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>; +defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12<0x040>; +defm S_WAIT_STORECNT : SOPP_Real_32_gfx12<0x041>; +defm S_WAIT_SAMPLECNT : SOPP_Real_32_gfx12<0x042>; +defm S_WAIT_BVHCNT : SOPP_Real_32_gfx12<0x043>; +defm S_WAIT_EXPCNT : SOPP_Real_32_gfx12<0x044>; +defm S_WAIT_DSCNT : SOPP_Real_32_gfx12<0x046>; +defm S_WAIT_KMCNT : SOPP_Real_32_gfx12<0x047>; +defm S_WAIT_LOADCNT_DSCNT : SOPP_Real_32_gfx12<0x048>; +defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>; //===----------------------------------------------------------------------===// // SOPP - GFX11, GFX12. diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_err.s index 088ee416692b..916d6f05dab5 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_err.s @@ -36,6 +36,11 @@ v_interp_p2_f32 v0, -v1, v2, v3 wait_exp global_atomic_cmpswap_x2 v[1:4], v3, v[5:8], off offset:2047 glc // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// s_waitcnt_depctr is called s_wait_alu on GFX12, but its semantics and +// encoding are identical. Even so, the new name should be rejected on GFX11 +s_wait_alu 0xfffe +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + v_cubesc_f32_e64_dpp v5, v1, v2, 12345678 row_shr:4 row_mask:0xf bank_mask:0xf // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s index cf78b87a4761..41ed4de6be8a 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s @@ -1,5 +1,59 @@ // RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s +s_wait_loadcnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc0,0xbf] + +s_wait_loadcnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc0,0xbf] + +s_wait_storecnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc1,0xbf] + +s_wait_storecnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc1,0xbf] + +s_wait_samplecnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc2,0xbf] + +s_wait_samplecnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc2,0xbf] + +s_wait_bvhcnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc3,0xbf] + +s_wait_bvhcnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc3,0xbf] + +s_wait_expcnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc4,0xbf] + +s_wait_expcnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc4,0xbf] + +s_wait_dscnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc6,0xbf] + +s_wait_dscnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc6,0xbf] + +s_wait_kmcnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc7,0xbf] + +s_wait_kmcnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc7,0xbf] + +s_wait_loadcnt_dscnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc8,0xbf] + +s_wait_loadcnt_dscnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc8,0xbf] + +s_wait_storecnt_dscnt 0x1234 +// GFX12: encoding: [0x34,0x12,0xc9,0xbf] + +s_wait_storecnt_dscnt 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0xc9,0xbf] + s_wait_alu 0xfffe // GFX12: encoding: [0xfe,0xff,0x88,0xbf] diff --git a/llvm/test/MC/AMDGPU/gfx12_unsupported.s b/llvm/test/MC/AMDGPU/gfx12_unsupported.s index 44c85b8545c5..aabaf526dc2a 100644 --- a/llvm/test/MC/AMDGPU/gfx12_unsupported.s +++ b/llvm/test/MC/AMDGPU/gfx12_unsupported.s @@ -4,6 +4,18 @@ // Unsupported instructions. //===----------------------------------------------------------------------===// +s_waitcnt_expcnt exec_hi, 0x1234 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +s_waitcnt_lgkmcnt exec_hi, 0x1234 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +s_waitcnt_vmcnt exec_hi, 0x1234 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +s_waitcnt_vscnt exec_hi, 0x1234 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + s_subvector_loop_begin s0, 0x1234 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU diff --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt index e1bb7ad51171..d7417929a8e1 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt @@ -10,6 +10,10 @@ # GFX11: [[@LINE+1]]:1: warning: invalid instruction encoding 0x34,0x12,0x93,0xbf +# this is s_waitcnt_vscnt exec_hi, 0x1234, which is valid on gfx11, but not on gfx12 +# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding +0x34,0x12,0x7f,0xbc + # W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf] # W64: [[@LINE+1]]:1: warning: invalid instruction encoding 0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt index 13ded15998fb..6f4dc2423487 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt @@ -6,6 +6,60 @@ # GFX12: s_wait_alu 0xfffe ; encoding: [0xfe,0xff,0x88,0xbf] 0xfe,0xff,0x88,0xbf +# GFX12: s_wait_loadcnt 0x1234 ; encoding: [0x34,0x12,0xc0,0xbf] +0x34,0x12,0xc0,0xbf + +# GFX12: s_wait_loadcnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc0,0xbf] +0xd1,0xc1,0xc0,0xbf + +# GFX12: s_wait_storecnt 0x1234 ; encoding: [0x34,0x12,0xc1,0xbf] +0x34,0x12,0xc1,0xbf + +# GFX12: s_wait_storecnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc1,0xbf] +0xd1,0xc1,0xc1,0xbf + +# GFX12: s_wait_samplecnt 0x1234 ; encoding: [0x34,0x12,0xc2,0xbf] +0x34,0x12,0xc2,0xbf + +# GFX12: s_wait_samplecnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc2,0xbf] +0xd1,0xc1,0xc2,0xbf + +# GFX12: s_wait_bvhcnt 0x1234 ; encoding: [0x34,0x12,0xc3,0xbf] +0x34,0x12,0xc3,0xbf + +# GFX12: s_wait_bvhcnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc3,0xbf] +0xd1,0xc1,0xc3,0xbf + +# GFX12: s_wait_expcnt 0x1234 ; encoding: [0x34,0x12,0xc4,0xbf] +0x34,0x12,0xc4,0xbf + +# GFX12: s_wait_expcnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc4,0xbf] +0xd1,0xc1,0xc4,0xbf + +# GFX12: s_wait_dscnt 0x1234 ; encoding: [0x34,0x12,0xc6,0xbf] +0x34,0x12,0xc6,0xbf + +# GFX12: s_wait_dscnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc6,0xbf] +0xd1,0xc1,0xc6,0xbf + +# GFX12: s_wait_kmcnt 0x1234 ; encoding: [0x34,0x12,0xc7,0xbf] +0x34,0x12,0xc7,0xbf + +# GFX12: s_wait_kmcnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc7,0xbf] +0xd1,0xc1,0xc7,0xbf + +# GFX12: s_wait_loadcnt_dscnt 0x1234 ; encoding: [0x34,0x12,0xc8,0xbf] +0x34,0x12,0xc8,0xbf + +# GFX12: s_wait_loadcnt_dscnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc8,0xbf] +0xd1,0xc1,0xc8,0xbf + +# GFX12: s_wait_storecnt_dscnt 0x1234 ; encoding: [0x34,0x12,0xc9,0xbf] +0x34,0x12,0xc9,0xbf + +# GFX12: s_wait_storecnt_dscnt 0xc1d1 ; encoding: [0xd1,0xc1,0xc9,0xbf] +0xd1,0xc1,0xc9,0xbf + # GFX12: s_singleuse_vdst 0x0 ; encoding: [0x00,0x00,0x93,0xbf] 0x00,0x00,0x93,0xbf -- GitLab From b399c8407351a8fce7313d6ecd6510cb04e94d8f Mon Sep 17 00:00:00 2001 From: Mitch Phillips <31459023+hctim@users.noreply.github.com> Date: Tue, 9 Jan 2024 10:06:21 +0100 Subject: [PATCH 169/652] [NFC] [lld] [MTE] Rename MemtagDescriptors to MemtagGlobalDescriptors (#77300) Requested in https://github.com/llvm/llvm-project/pull/77078, I agree that we may as well be unambiguous. --- lld/ELF/Relocations.cpp | 2 +- lld/ELF/SyntheticSections.cpp | 22 ++++++++++++---------- lld/ELF/SyntheticSections.h | 6 +++--- lld/ELF/Writer.cpp | 9 +++++---- 4 files changed, 21 insertions(+), 18 deletions(-) diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp index 9eb2e82542d3..20eb02b87984 100644 --- a/lld/ELF/Relocations.cpp +++ b/lld/ELF/Relocations.cpp @@ -1669,7 +1669,7 @@ void elf::postScanRelocations() { return; if (sym.isTagged() && sym.isDefined()) - mainPart->memtagDescriptors->addSymbol(sym); + mainPart->memtagGlobalDescriptors->addSymbol(sym); if (!sym.needsDynReloc()) return; diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index 19fced5aff92..1c1b0ee2f9c8 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -1454,9 +1454,10 @@ DynamicSection::computeContents() { addInt(DT_AARCH64_MEMTAG_MODE, config->androidMemtagMode == NT_MEMTAG_LEVEL_ASYNC); addInt(DT_AARCH64_MEMTAG_HEAP, config->androidMemtagHeap); addInt(DT_AARCH64_MEMTAG_STACK, config->androidMemtagStack); - if (mainPart->memtagDescriptors->isNeeded()) { - addInSec(DT_AARCH64_MEMTAG_GLOBALS, *mainPart->memtagDescriptors); - addInt(DT_AARCH64_MEMTAG_GLOBALSSZ, mainPart->memtagDescriptors->getSize()); + if (mainPart->memtagGlobalDescriptors->isNeeded()) { + addInSec(DT_AARCH64_MEMTAG_GLOBALS, *mainPart->memtagGlobalDescriptors); + addInt(DT_AARCH64_MEMTAG_GLOBALSSZ, + mainPart->memtagGlobalDescriptors->getSize()); } } } @@ -3919,8 +3920,9 @@ static size_t computeOrWriteULEB128(uint64_t v, uint8_t *buf, size_t offset) { // https://github.com/ARM-software/abi-aa/blob/main/memtagabielf64/memtagabielf64.rst#83encoding-of-sht_aarch64_memtag_globals_dynamic constexpr uint64_t kMemtagStepSizeBits = 3; constexpr uint64_t kMemtagGranuleSize = 16; -static size_t createMemtagDescriptors(const SmallVector &symbols, - uint8_t *buf = nullptr) { +static size_t +createMemtagGlobalDescriptors(const SmallVector &symbols, + uint8_t *buf = nullptr) { size_t sectionSize = 0; uint64_t lastGlobalEnd = 0; @@ -3961,7 +3963,7 @@ static size_t createMemtagDescriptors(const SmallVector &symb return sectionSize; } -bool MemtagDescriptors::updateAllocSize() { +bool MemtagGlobalDescriptors::updateAllocSize() { size_t oldSize = getSize(); std::stable_sort(symbols.begin(), symbols.end(), [](const Symbol *s1, const Symbol *s2) { @@ -3970,12 +3972,12 @@ bool MemtagDescriptors::updateAllocSize() { return oldSize != getSize(); } -void MemtagDescriptors::writeTo(uint8_t *buf) { - createMemtagDescriptors(symbols, buf); +void MemtagGlobalDescriptors::writeTo(uint8_t *buf) { + createMemtagGlobalDescriptors(symbols, buf); } -size_t MemtagDescriptors::getSize() const { - return createMemtagDescriptors(symbols); +size_t MemtagGlobalDescriptors::getSize() const { + return createMemtagGlobalDescriptors(symbols); } InStruct elf::in; diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h index 3a9f4ba886f6..7882ad87c241 100644 --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -1257,9 +1257,9 @@ public: size_t getSize() const override; }; -class MemtagDescriptors final : public SyntheticSection { +class MemtagGlobalDescriptors final : public SyntheticSection { public: - MemtagDescriptors() + MemtagGlobalDescriptors() : SyntheticSection(llvm::ELF::SHF_ALLOC, llvm::ELF::SHT_AARCH64_MEMTAG_GLOBALS_DYNAMIC, /*alignment=*/4, ".memtag.globals.dynamic") {} @@ -1315,7 +1315,7 @@ struct Partition { std::unique_ptr gnuHashTab; std::unique_ptr hashTab; std::unique_ptr memtagAndroidNote; - std::unique_ptr memtagDescriptors; + std::unique_ptr memtagGlobalDescriptors; std::unique_ptr packageMetadataNote; std::unique_ptr relaDyn; std::unique_ptr relrDyn; diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 7b9880a034bc..dfec5e07301a 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -405,8 +405,9 @@ template void elf::createSyntheticSections() { part.memtagAndroidNote = std::make_unique(); add(*part.memtagAndroidNote); if (canHaveMemtagGlobals()) { - part.memtagDescriptors = std::make_unique(); - add(*part.memtagDescriptors); + part.memtagGlobalDescriptors = + std::make_unique(); + add(*part.memtagGlobalDescriptors); } } @@ -1731,8 +1732,8 @@ template void Writer::finalizeAddressDependentContent() { changed |= part.relaDyn->updateAllocSize(); if (part.relrDyn) changed |= part.relrDyn->updateAllocSize(); - if (part.memtagDescriptors) - changed |= part.memtagDescriptors->updateAllocSize(); + if (part.memtagGlobalDescriptors) + changed |= part.memtagGlobalDescriptors->updateAllocSize(); } const Defined *changedSym = script->assignAddresses(); -- GitLab From b81ba52e15d95c3353489d4ce2f61c3771714c28 Mon Sep 17 00:00:00 2001 From: Frederik Carlier Date: Tue, 9 Jan 2024 10:15:01 +0100 Subject: [PATCH 170/652] Set dllstorage on ObjectiveC ivar offsets (#77385) Mark instance variable offset symbols with `dllexport`/`dllimport` if they are not hidden and the interface declaration is marked with `dllexport`/`dllimport`, when using the GNUstep 2.x ABI. /cc @davidchisnall --- clang/lib/CodeGen/CGObjCGNU.cpp | 2 ++ clang/test/CodeGenObjC/dllstorage.m | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/clang/lib/CodeGen/CGObjCGNU.cpp b/clang/lib/CodeGen/CGObjCGNU.cpp index 4ca1a8cce64d..9443fecf9b79 100644 --- a/clang/lib/CodeGen/CGObjCGNU.cpp +++ b/clang/lib/CodeGen/CGObjCGNU.cpp @@ -1851,6 +1851,8 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { llvm::GlobalValue::HiddenVisibility : llvm::GlobalValue::DefaultVisibility; OffsetVar->setVisibility(ivarVisibility); + if (ivarVisibility != llvm::GlobalValue::HiddenVisibility) + CGM.setGVProperties(OffsetVar, OID->getClassInterface()); ivarBuilder.add(OffsetVar); // Ivar size ivarBuilder.addInt(Int32Ty, diff --git a/clang/test/CodeGenObjC/dllstorage.m b/clang/test/CodeGenObjC/dllstorage.m index 64ba21f9769a..0dbf1881caa9 100644 --- a/clang/test/CodeGenObjC/dllstorage.m +++ b/clang/test/CodeGenObjC/dllstorage.m @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -triple x86_64-unknown-windows-msvc -fdeclspec -fobjc-runtime=ios -fobjc-exceptions -S -emit-llvm -o - %s | FileCheck -allow-deprecated-dag-overlap -check-prefix CHECK-IR %s +// RUN: %clang_cc1 -triple x86_64-unknown-windows-msvc -fdeclspec -fobjc-runtime=gnustep-2.0 -fobjc-exceptions -S -emit-llvm -o - %s | FileCheck -allow-deprecated-dag-overlap -check-prefix CHECK-NF %s // RUN: %clang_cc1 -triple i686-windows-itanium -fms-extensions -fobjc-runtime=macosx -fdeclspec -fobjc-exceptions -S -emit-llvm -o - %s | FileCheck -allow-deprecated-dag-overlap -check-prefix CHECK-IR %s // RUN: %clang_cc1 -triple i686-windows-itanium -fms-extensions -fobjc-runtime=objfw -fdeclspec -fobjc-exceptions -S -emit-llvm -o - %s | FileCheck -allow-deprecated-dag-overlap -check-prefix CHECK-FW %s @@ -12,6 +13,8 @@ __declspec(dllimport) // CHECK-IR-DAG: @"OBJC_METACLASS_$_I" = external dllimport global %struct._class_t // CHECK-IR-DAG: @"OBJC_CLASS_$_I" = external dllimport global %struct._class_t +// CHECK-NF-DAG: @"$_OBJC_CLASS_I" = external dllimport global ptr + __declspec(dllexport) @interface J : I @end @@ -22,6 +25,9 @@ __declspec(dllexport) // CHECK-FW-DAG: @_OBJC_METACLASS_J = dso_local dllexport global // CHECK-FW-DAG: @_OBJC_CLASS_J = dso_local dllexport global +// CHECK-NF-DAG: @"$_OBJC_METACLASS_J" = internal global +// CHECK-NF-DAG: @"$_OBJC_CLASS_J" = dllexport global + @implementation J { id _ivar; } @@ -29,6 +35,8 @@ __declspec(dllexport) // CHECK-IR-DAG: @"OBJC_IVAR_$_J._ivar" = global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_J._ivar.\01" = hidden global i32 + @interface K : J @end @@ -38,6 +46,9 @@ __declspec(dllexport) // CHECK-FW-DAG: @_OBJC_METACLASS_K = dso_local global // CHECK-FW-DAG: @_OBJC_CLASS_K = dso_local global +// CHECK-NF-DAG: @"$_OBJC_METACLASS_K" = internal global +// CHECK-NF-DAG: @"$_OBJC_CLASS_K" = global + @implementation K { id _ivar; } @@ -45,6 +56,8 @@ __declspec(dllexport) // CHECK-IR-DAG: @"OBJC_IVAR_$_K._ivar" = global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_K._ivar.\01" = hidden global i32 + __declspec(dllexport) @interface L : K @end @@ -55,6 +68,9 @@ __declspec(dllexport) // CHECK-FW-DAG: @_OBJC_METACLASS_L = dso_local dllexport global // CHECK-FW-DAG: @_OBJC_CLASS_L = dso_local dllexport global +// CHECK-NF-DAG: @"$_OBJC_METACLASS_L" = internal global +// CHECK-NF-DAG: @"$_OBJC_CLASS_L" = dllexport global + @implementation L { id _none; @@ -78,6 +94,12 @@ __declspec(dllexport) // CHECK-IR-DAG: @"OBJC_IVAR_$_L._package" = global i32 // CHECK-IR-DAG: @"OBJC_IVAR_$_L._private" = global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_L._none.\01" = hidden global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_L._public.\01" = dso_local dllexport global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_L._protected.\01" = dso_local dllexport global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_L._package.\01" = hidden global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_L._private.\01" = hidden global i32 + __declspec(dllimport) @interface M : I { @public @@ -89,6 +111,9 @@ __declspec(dllimport) // CHECK-IR-DAG: @"OBJC_IVAR_$_M._ivar" = external dllimport global i32 +// CHECK-NF-DAG: @"$_OBJC_REF_CLASS_M" = external dllimport global ptr +// CHECK-NF-DAG: @"__objc_ivar_offset_M._ivar.\01" = external global i32 + __declspec(dllexport) __attribute__((__objc_exception__)) @interface N : I @@ -97,6 +122,8 @@ __attribute__((__objc_exception__)) // CHECK-FW-DAG: @_OBJC_METACLASS_N = dso_local dllexport global // CHECK-FW-DAG: @_OBJC_CLASS_N = dso_local dllexport global +// CHECK-NF-DAG: @"$_OBJC_CLASS_N" = dllexport global + @implementation N : I @end @@ -124,6 +151,8 @@ id f(Q *q) { // CHECK-IR-DAG: @"OBJC_IVAR_$_M._ivar" = external dllimport global i32 +// CHECK-NF-DAG: @"__objc_ivar_offset_M._ivar.\01" = external global i32 + int g(void) { @autoreleasepool { M *mi = [M new]; -- GitLab From 243a5822f68d784f5d8b12db5d50353a37a2f0f4 Mon Sep 17 00:00:00 2001 From: Mikhail Goncharov Date: Tue, 9 Jan 2024 10:24:32 +0100 Subject: [PATCH 171/652] [bazel] update build for 2357e899cb11e05312c54b689ebd0355487be6bc --- .../llvm-project-overlay/llvm/BUILD.bazel | 32 +++++++++++++++---- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index 1110daa62a1c..efa2b8f47f6a 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -2887,10 +2887,10 @@ cc_library( cc_library( name = "DWARFLinker", srcs = glob([ - "lib/DWARFLinker/*.cpp", - "lib/DWARFLinker/*.h", + "lib/DWARFLinker/Classic/*.cpp", + "lib/DWARFLinker/Classic/*.h", ]), - hdrs = glob(["include/llvm/DWARFLinker/*.h"]), + hdrs = glob(["include/llvm/DWARFLinker/Classic/*.h"]), copts = llvm_copts, deps = [ ":BinaryFormat", @@ -2901,21 +2901,39 @@ cc_library( ":Support", ":Target", ":TargetParser", + ":DWARFLinkerBase", + ], +) + +cc_library( + name = "DWARFLinkerBase", + srcs = glob([ + "lib/DWARFLinker/*.cpp", + "lib/DWARFLinker/*.h", + ]), + hdrs = glob(["include/llvm/DWARFLinker/*.h"]), + copts = llvm_copts, + deps = [ + ":BinaryFormat", + ":CodeGen", + ":DebugInfoDWARF", + ":Support", + ":Target", ], ) cc_library( name = "DWARFLinkerParallel", srcs = glob([ - "lib/DWARFLinkerParallel/*.cpp", - "lib/DWARFLinkerParallel/*.h", + "lib/DWARFLinker/Parallel/*.cpp", + "lib/DWARFLinker/Parallel/*.h", ]), - hdrs = glob(["include/llvm/DWARFLinkerParallel/*.h"]), + hdrs = glob(["include/llvm/DWARFLinker/Parallel/*.h"]), copts = llvm_copts, deps = [ ":BinaryFormat", ":CodeGen", - ":DWARFLinker", + ":DWARFLinkerBase", ":DebugInfoDWARF", ":MC", ":Object", -- GitLab From 414ea3a77181ef01d2cc2ad34950fc1c03ce0d41 Mon Sep 17 00:00:00 2001 From: Haojian Wu Date: Tue, 9 Jan 2024 10:32:06 +0100 Subject: [PATCH 172/652] [AST] Teach TextNodeDumper to print the "implicit" bit for coroutine AST nodes (#77311) --- clang/include/clang/AST/TextNodeDumper.h | 2 + clang/lib/AST/TextNodeDumper.cpp | 10 ++++ clang/test/AST/ast-dump-coroutine.cpp | 69 ++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 clang/test/AST/ast-dump-coroutine.cpp diff --git a/clang/include/clang/AST/TextNodeDumper.h b/clang/include/clang/AST/TextNodeDumper.h index 2f4ed082a0c7..732749ad305e 100644 --- a/clang/include/clang/AST/TextNodeDumper.h +++ b/clang/include/clang/AST/TextNodeDumper.h @@ -252,6 +252,8 @@ public: void VisitGotoStmt(const GotoStmt *Node); void VisitCaseStmt(const CaseStmt *Node); void VisitReturnStmt(const ReturnStmt *Node); + void VisitCoawaitExpr(const CoawaitExpr *Node); + void VisitCoreturnStmt(const CoreturnStmt *Node); void VisitCompoundStmt(const CompoundStmt *Node); void VisitConstantExpr(const ConstantExpr *Node); void VisitCallExpr(const CallExpr *Node); diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index e8274fcd5cfe..369ff66ac4db 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -1094,6 +1094,16 @@ void clang::TextNodeDumper::VisitReturnStmt(const ReturnStmt *Node) { } } +void clang::TextNodeDumper::VisitCoawaitExpr(const CoawaitExpr *Node) { + if (Node->isImplicit()) + OS << " implicit"; +} + +void clang::TextNodeDumper::VisitCoreturnStmt(const CoreturnStmt *Node) { + if (Node->isImplicit()) + OS << " implicit"; +} + void TextNodeDumper::VisitConstantExpr(const ConstantExpr *Node) { if (Node->hasAPValueResult()) AddChild("value", diff --git a/clang/test/AST/ast-dump-coroutine.cpp b/clang/test/AST/ast-dump-coroutine.cpp new file mode 100644 index 000000000000..5e7736300f9f --- /dev/null +++ b/clang/test/AST/ast-dump-coroutine.cpp @@ -0,0 +1,69 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -std=c++20 \ +// RUN: -fsyntax-only -ast-dump -ast-dump-filter test | FileCheck %s + +#include "Inputs/std-coroutine.h" + +using namespace std; + +struct Task { + struct promise_type { + std::suspend_always initial_suspend() { return {}; } + Task get_return_object() { + return std::coroutine_handle::from_promise(*this); + } + std::suspend_always final_suspend() noexcept { return {}; } + std::suspend_always return_void() { return {}; } + void unhandled_exception() {} + + auto await_transform(int s) { + struct awaiter { + promise_type *promise; + bool await_ready() { return true; } + int await_resume() { return 1; } + void await_suspend(std::coroutine_handle<>) {} + }; + + return awaiter{this}; + } + }; + + Task(std::coroutine_handle promise); + + std::coroutine_handle handle; +}; + +Task test() { + co_await 1; +// Writen souce code, verify no implicit bit for the co_await expr. +// CHECK: CompoundStmt {{.*}} +// CHECK-NEXT: | `-ExprWithCleanups {{.*}} 'int' +// CHECK-NEXT: | `-CoawaitExpr {{.*}} 'int'{{$}} +// CHECK-NEXT: | |-IntegerLiteral {{.*}} 'int' 1 +// CHECK-NEXT: | |-MaterializeTemporaryExpr {{.*}} 'awaiter' +// CHECK-NEXT: | | `-CXXMemberCallExpr {{.*}} 'awaiter' +// CHECK-NEXT: | | |-MemberExpr {{.*}} .await_transform +} +// Verify the implicit AST nodes for coroutines. +// CHECK: |-DeclStmt {{.*}} +// CHECK-NEXT: | `-VarDecl {{.*}} implicit used __promise +// CHECK-NEXT: | `-CXXConstructExpr {{.*}} +// CHECK-NEXT: |-ExprWithCleanups {{.*}} 'void' +// CHECK-NEXT: | `-CoawaitExpr {{.*}} 'void' implicit +// CHECK-NEXT: |-CXXMemberCallExpr {{.*}} 'std::suspend_always' +// CHECK-NEXT: | | `-MemberExpr {{.*}} .initial_suspend +// ... +// FIXME: the CoreturnStmt should be marked as implicit +// CHECK: CoreturnStmt {{.*}} {{$}} + +Task test2() { +// Writen souce code, verify no implicit bit for the co_return expr. +// CHECK: CompoundStmt {{.*}} +// CHECK-NEXT: | `-CoreturnStmt {{.*}} {{$}} + co_return; +} +// Verify the implicit AST nodes for coroutines. +// CHECK: |-DeclStmt {{.*}} +// CHECK-NEXT: | `-VarDecl {{.*}} implicit used __promise +// ... +// FIXME: the CoreturnStmt should be marked as implicit +// CHECK: CoreturnStmt {{.*}} {{$}} -- GitLab From 25e0dc92a1df906d6e42c66a32f1fa764f1acabd Mon Sep 17 00:00:00 2001 From: paperchalice Date: Tue, 9 Jan 2024 17:42:09 +0800 Subject: [PATCH 173/652] [CodeGen] Port `GCLowering` to new pass manager (#75305) --- .../include/llvm/CodeGen/CodeGenPassBuilder.h | 1 + llvm/include/llvm/CodeGen/GCMetadata.h | 11 +++++++ .../llvm/CodeGen/MachinePassRegistry.def | 2 +- llvm/lib/CodeGen/GCRootLowering.cpp | 33 +++++++++++++------ llvm/lib/Passes/PassRegistry.def | 1 + 5 files changed, 37 insertions(+), 11 deletions(-) diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index 2100c30aad11..c52bd41086e1 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -488,6 +488,7 @@ Error CodeGenPassBuilder::buildPipeline( AddIRPass addIRPass(MPM, Opt.DebugPM); // `ProfileSummaryInfo` is always valid. addIRPass(RequireAnalysisPass()); + addIRPass(RequireAnalysisPass()); addISelPasses(addIRPass); AddMachinePass addPass(MFPM); diff --git a/llvm/include/llvm/CodeGen/GCMetadata.h b/llvm/include/llvm/CodeGen/GCMetadata.h index 9e4e8342ea29..ca6a511185c7 100644 --- a/llvm/include/llvm/CodeGen/GCMetadata.h +++ b/llvm/include/llvm/CodeGen/GCMetadata.h @@ -186,6 +186,17 @@ public: Result run(Function &F, FunctionAnalysisManager &FAM); }; +/// LowerIntrinsics - This pass rewrites calls to the llvm.gcread or +/// llvm.gcwrite intrinsics, replacing them with simple loads and stores as +/// directed by the GCStrategy. It also performs automatic root initialization +/// and custom intrinsic lowering. +/// +/// This pass requires `CollectorMetadataAnalysis`. +class GCLoweringPass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + /// An analysis pass which caches information about the entire Module. /// Records both the function level information used by GCRoots and a /// cache of the 'active' gc strategy objects for the current Module. diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index b1b8ee8df29d..4ddbb2419abc 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -51,6 +51,7 @@ FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, (TM)) FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass, (TM)) FUNCTION_PASS("expand-reductions", ExpandReductionsPass, ()) FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ()) +FUNCTION_PASS("gc-lowering", GCLoweringPass, ()) FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, (TM)) FUNCTION_PASS("interleaved-access", InterleavedAccessPass, (TM)) FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass, (TM)) @@ -133,7 +134,6 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, #endif DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ()) -DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ()) DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ()) #undef DUMMY_FUNCTION_PASS diff --git a/llvm/lib/CodeGen/GCRootLowering.cpp b/llvm/lib/CodeGen/GCRootLowering.cpp index c0ce37091933..894ab9a0486a 100644 --- a/llvm/lib/CodeGen/GCRootLowering.cpp +++ b/llvm/lib/CodeGen/GCRootLowering.cpp @@ -27,6 +27,15 @@ using namespace llvm; +/// Lower barriers out of existence (if the associated GCStrategy hasn't +/// already done so...), and insert initializing stores to roots as a defensive +/// measure. Given we're going to report all roots live at all safepoints, we +/// need to be able to ensure each root has been initialized by the point the +/// first safepoint is reached. This really should have been done by the +/// frontend, but the old API made this non-obvious, so we do a potentially +/// redundant store just in case. +static bool DoLowering(Function &F, GCStrategy &S); + namespace { /// LowerIntrinsics - This pass rewrites calls to the llvm.gcread or @@ -34,8 +43,6 @@ namespace { /// directed by the GCStrategy. It also performs automatic root initialization /// and custom intrinsic lowering. class LowerIntrinsics : public FunctionPass { - bool DoLowering(Function &F, GCStrategy &S); - public: static char ID; @@ -72,6 +79,19 @@ public: }; } +PreservedAnalyses GCLoweringPass::run(Function &F, + FunctionAnalysisManager &FAM) { + auto &Info = FAM.getResult(F); + + bool Changed = DoLowering(F, Info.getStrategy()); + + if (!Changed) + return PreservedAnalyses::all(); + PreservedAnalyses PA; + PA.preserve(); + return PA; +} + // ----------------------------------------------------------------------------- INITIALIZE_PASS_BEGIN(LowerIntrinsics, "gc-lowering", "GC Lowering", false, @@ -178,14 +198,7 @@ bool LowerIntrinsics::runOnFunction(Function &F) { return DoLowering(F, S); } -/// Lower barriers out of existance (if the associated GCStrategy hasn't -/// already done so...), and insert initializing stores to roots as a defensive -/// measure. Given we're going to report all roots live at all safepoints, we -/// need to be able to ensure each root has been initialized by the point the -/// first safepoint is reached. This really should have been done by the -/// frontend, but the old API made this non-obvious, so we do a potentially -/// redundant store just in case. -bool LowerIntrinsics::DoLowering(Function &F, GCStrategy &S) { +bool DoLowering(Function &F, GCStrategy &S) { SmallVector Roots; bool MadeChange = false; diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 1b6c0e4dd3bb..bceac8374ba9 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -316,6 +316,7 @@ FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flattencfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) +FUNCTION_PASS("gc-lowering", GCLoweringPass()) FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) FUNCTION_PASS("gvn-sink", GVNSinkPass()) -- GitLab From f9fec402896a90f3b09cea359c330f65a0908649 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 9 Jan 2024 17:02:27 +0700 Subject: [PATCH 174/652] AMDGPU: Make v32bf16 a legal type (#76679) Depends #76678 --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 ++++ llvm/lib/Target/AMDGPU/SIInstructions.td | 32 +++++++++++++++++++++++ llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 4 +-- 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 209debb3a105..975178b313ae 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -173,6 +173,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, addRegisterClass(MVT::v16bf16, &AMDGPU::SGPR_256RegClass); addRegisterClass(MVT::v32i16, &AMDGPU::SGPR_512RegClass); addRegisterClass(MVT::v32f16, &AMDGPU::SGPR_512RegClass); + addRegisterClass(MVT::v32bf16, &AMDGPU::SGPR_512RegClass); } addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass); @@ -719,11 +720,15 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, AddPromotedToType(ISD::LOAD, MVT::v32i16, MVT::v16i32); setOperationAction(ISD::LOAD, MVT::v32f16, Promote); AddPromotedToType(ISD::LOAD, MVT::v32f16, MVT::v16i32); + setOperationAction(ISD::LOAD, MVT::v32bf16, Promote); + AddPromotedToType(ISD::LOAD, MVT::v32bf16, MVT::v16i32); setOperationAction(ISD::STORE, MVT::v32i16, Promote); AddPromotedToType(ISD::STORE, MVT::v32i16, MVT::v16i32); setOperationAction(ISD::STORE, MVT::v32f16, Promote); AddPromotedToType(ISD::STORE, MVT::v32f16, MVT::v16i32); + setOperationAction(ISD::STORE, MVT::v32bf16, Promote); + AddPromotedToType(ISD::STORE, MVT::v32bf16, MVT::v16i32); setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, MVT::v2i32, Expand); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 1cd8a37c3aa9..e28b3d412e48 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1801,6 +1801,38 @@ def : BitConvert ; def : BitConvert ; def : BitConvert ; + + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + // 1024-bit bitcast def : BitConvert ; def : BitConvert ; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 1d197dc08ac2..f42af89cf5e6 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -916,7 +916,7 @@ defm "" : SRegClass<11, [v11i32, v11f32], SGPR_352Regs, TTMP_352Regs>; defm "" : SRegClass<12, [v12i32, v12f32], SGPR_384Regs, TTMP_384Regs>; let GlobalPriority = true in { -defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16], SGPR_512Regs, TTMP_512Regs>; +defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], SGPR_512Regs, TTMP_512Regs>; defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>; } @@ -970,7 +970,7 @@ defm VReg_352 : VRegClass<11, [v11i32, v11f32], (add VGPR_352)>; defm VReg_384 : VRegClass<12, [v12i32, v12f32], (add VGPR_384)>; let GlobalPriority = true in { -defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16], (add VGPR_512)>; +defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], (add VGPR_512)>; defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>; } -- GitLab From 7a2596344045565f24dd08486a36a30d8966d27e Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 9 Jan 2024 10:20:32 +0000 Subject: [PATCH 175/652] [AMDGPU] Flip the default value of maybeAtomic. NFCI. (#75220) In practice maybeAtomic = 0 is used to prevent SIMemoryLegalizer from interfering with instructions that are mayLoad or mayStore but lack MachineMemOperands. These instructions should be the exception not the rule, so this patch sets maybeAtomic = 1 by default and only overrides it to 0 where necessary. --- llvm/lib/Target/AMDGPU/BUFInstructions.td | 4 ---- llvm/lib/Target/AMDGPU/DSDIRInstructions.td | 1 + llvm/lib/Target/AMDGPU/DSInstructions.td | 1 - llvm/lib/Target/AMDGPU/EXPInstructions.td | 1 + llvm/lib/Target/AMDGPU/FLATInstructions.td | 7 ------- llvm/lib/Target/AMDGPU/SIInstrFormats.td | 2 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +- llvm/lib/Target/AMDGPU/SMInstructions.td | 1 + 8 files changed, 5 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 15a54856cb2e..9e99d382ed9b 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -503,7 +503,6 @@ class MUBUF_Load_Pseudo .ret; let mayLoad = 0; let mayStore = 1; - let maybeAtomic = 1; let elements = getMUBUFElements.ret; let tfe = isTFE; } @@ -671,7 +669,6 @@ class MUBUF_Pseudo_Store_Lds let LGKM_CNT = 1; let mayLoad = 1; let mayStore = 1; - let maybeAtomic = 1; let has_vdata = 0; let has_vaddr = 0; @@ -735,7 +732,6 @@ class MUBUF_Atomic_Pseudo : let hasSideEffects = 0; let mayLoad = 1; let mayStore = 0; + let maybeAtomic = 0; string Mnemonic = opName; let UseNamedOperandTable = 1; diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index bc9049b4ef33..3cccd8c50e66 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -19,7 +19,6 @@ class DS_Pseudo patt // Most instruction load and store data, so set this as the default. let mayLoad = 1; let mayStore = 1; - let maybeAtomic = 1; let hasSideEffects = 0; let SchedRW = [WriteLDS]; diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td index ff1d661ef6fe..4cfee7d013ef 100644 --- a/llvm/lib/Target/AMDGPU/EXPInstructions.td +++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td @@ -20,6 +20,7 @@ class EXPCommon : InstSI< let EXP_CNT = 1; let mayLoad = done; let mayStore = 1; + let maybeAtomic = 0; let UseNamedOperandTable = 1; let Uses = !if(row, [EXEC, M0], [EXEC]); let SchedRW = [WriteExport]; diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 345564c06af1..16a8b770e057 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -215,7 +215,6 @@ class FLAT_Load_Pseudo { @@ -263,7 +261,6 @@ class FLAT_Global_Load_AddTid_Pseudo { @@ -520,7 +514,6 @@ class FLAT_AtomicNoRet_Pseudo { let hasSideEffects = 1; - let maybeAtomic = 1; } let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in { @@ -563,6 +562,7 @@ def SI_MASKED_UNREACHABLE : SPseudoInstSI <(outs), (ins), let hasNoSchedulingInfo = 1; let FixedSize = 1; let isMeta = 1; + let maybeAtomic = 0; } // Used as an isel pseudo to directly emit initialization with an diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index 087ee65aa03f..fc29ce8d71f2 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -29,6 +29,7 @@ class SM_Pseudo patt let mayStore = 0; let mayLoad = 1; let hasSideEffects = 0; + let maybeAtomic = 0; let UseNamedOperandTable = 1; let SchedRW = [WriteSMEM]; -- GitLab From 124efcaa973306ce42633cea07ed3cf55d63afde Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Tue, 9 Jan 2024 11:27:48 +0100 Subject: [PATCH 176/652] [mlir][bufferization][NFC] Clean up Bazel build files (#77429) `*OpsIncGen` should depend only on the respective `*OpsTdFiles`. --- utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 6 +++--- utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel | 2 -- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 6822a49ef0fc..05cbf7816370 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -12846,10 +12846,13 @@ td_library( includes = ["include"], deps = [ ":AllocationOpInterfaceTdFiles", + ":BufferizableOpInterfaceTdFiles", ":CopyOpInterfaceTdFiles", + ":DestinationStyleOpInterfaceTdFiles", ":InferTypeOpInterfaceTdFiles", ":OpBaseTdFiles", ":SideEffectInterfacesTdFiles", + ":SubsetOpInterfaceTdFiles", ], ) @@ -12976,10 +12979,7 @@ gentbl_cc_library( tblgen = ":mlir-tblgen", td_file = "include/mlir/Dialect/Bufferization/IR/BufferizationOps.td", deps = [ - ":BufferizableOpInterfaceTdFiles", ":BufferizationOpsTdFiles", - ":DestinationStyleOpInterfaceTdFiles", - ":SubsetOpInterfaceTdFiles", ], ) diff --git a/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel index 6f6f2b3798e8..f19c2336e6bc 100644 --- a/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel @@ -418,8 +418,6 @@ gentbl_filegroup( td_file = "mlir/dialects/BufferizationOps.td", deps = [ ":BufferizationOpsPyTdFiles", - "//mlir:DestinationStyleOpInterfaceTdFiles", - "//mlir:SubsetOpInterfaceTdFiles", ], ) -- GitLab From f92b928b1e1e662e091c8064a161bf4b5dfccdb9 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Tue, 9 Jan 2024 13:49:10 +0300 Subject: [PATCH 177/652] [GISel] Infer the type of an immediate when there is one element in TEC (#77399) When there is just one element in the type equivalence class (TEC), `inferNamedOperandType` fails because it does not consider the passed operand as a suitable one. This is incorrect when inferring the type of an (unnamed) immediate operand. --- .../type-inference.td | 27 ++++++++++++++++--- .../TableGen/GlobalISelCombinerEmitter.cpp | 16 ++++++----- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/type-inference.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/type-inference.td index c9ffe4e7adb3..ed4e0e411c7a 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/type-inference.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/type-inference.td @@ -1,5 +1,5 @@ // RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \ -// RUN: -gicombiner-debug-typeinfer -combiners=MyCombiner %s 2>&1 | \ +// RUN: -gicombiner-debug-typeinfer -combiners=MyCombiner %s 2>&1 >/dev/null | \ // RUN: FileCheck %s // Checks reasoning of the inference rules. @@ -10,13 +10,15 @@ include "llvm/Target/GlobalISel/Combine.td" def MyTargetISA : InstrInfo; def MyTarget : Target { let InstructionSet = MyTargetISA; } +// This also checks that the type of a def is preferred when inferring the type +// of an immediate. // CHECK: Rule Operand Type Equivalence Classes for inference_mul_by_neg_one: // CHECK-NEXT: Groups for __inference_mul_by_neg_one_match_0: [dst, x] // CHECK-NEXT: Groups for __inference_mul_by_neg_one_apply_0: [dst, x] // CHECK-NEXT: Final Type Equivalence Classes: [dst, x] -// CHECK-NEXT: INFER: imm 0 -> GITypeOf<$x> +// CHECK-NEXT: INFER: imm 0 -> GITypeOf<$dst> // CHECK-NEXT: Apply patterns for rule inference_mul_by_neg_one after inference: -// CHECK-NEXT: (CodeGenInstructionPattern name:__inference_mul_by_neg_one_apply_0 G_SUB operands:[$dst, (GITypeOf<$x> 0), $x]) +// CHECK-NEXT: (CodeGenInstructionPattern name:__inference_mul_by_neg_one_apply_0 G_SUB operands:[$dst, (GITypeOf<$dst> 0), $x]) def inference_mul_by_neg_one: GICombineRule < (defs root:$dst), (match (G_MUL $dst, $x, -1)), @@ -61,8 +63,25 @@ def infer_variadic_outs: GICombineRule < (COPY $dst, $tmp)) >; +// Check that the type of an immediate is inferred when there is just one +// element in the corresponding equivalence class. +// CHECK: Rule Operand Type Equivalence Classes for infer_imm_0: +// CHECK-NEXT: Groups for __infer_imm_0_match_0: [dst] +// CHECK-NEXT: Groups for __infer_imm_0_apply_0: [dst] +// CHECK-NEXT: Final Type Equivalence Classes: [dst] +// CHECK-NEXT: INFER: imm 1 -> GITypeOf<$dst> +// CHECK-NEXT: INFER: imm 2 -> GITypeOf<$dst> +// CHECK-NEXT: Apply patterns for rule infer_imm_0 after inference: +// CHECK-NEXT: (CodeGenInstructionPattern name:__infer_imm_0_apply_0 G_ADD operands:[$dst, (GITypeOf<$dst> 1), (GITypeOf<$dst> 2)]) +def infer_imm_0 : GICombineRule< + (defs root:$dst), + (match (G_ADD $dst, 0, 3)), + (apply (G_ADD $dst, 1, 2)) +>; + def MyCombiner: GICombiner<"GenMyCombiner", [ inference_mul_by_neg_one, infer_complex_tempreg, - infer_variadic_outs + infer_variadic_outs, + infer_imm_0, ]>; diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp index 89aca87a28ec..348b3b3e0898 100644 --- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp @@ -284,7 +284,8 @@ private: /// succeed. PatternType inferNamedOperandType(const InstructionPattern &IP, StringRef OpName, - const TypeEquivalenceClasses &TECs) const; + const TypeEquivalenceClasses &TECs, + bool AllowSelf = false) const; const Record &RuleDef; SmallVector MatchPats; @@ -427,8 +428,8 @@ PatternType CombineRuleOperandTypeChecker::inferImmediateType( continue; // Named operand with the same name, try to infer that. - if (PatternType InferTy = - inferNamedOperandType(IP, Op.getOperandName(), TECs)) + if (PatternType InferTy = inferNamedOperandType(IP, Op.getOperandName(), + TECs, /*AllowSelf=*/true)) return InferTy; } } @@ -438,16 +439,17 @@ PatternType CombineRuleOperandTypeChecker::inferImmediateType( PatternType CombineRuleOperandTypeChecker::inferNamedOperandType( const InstructionPattern &IP, StringRef OpName, - const TypeEquivalenceClasses &TECs) const { + const TypeEquivalenceClasses &TECs, bool AllowSelf) const { // This is the simplest possible case, we just need to find a TEC that - // contains OpName. Look at all other operands in equivalence class and try to - // find a suitable one. + // contains OpName. Look at all operands in equivalence class and try to + // find a suitable one. If `AllowSelf` is true, the operand itself is also + // considered suitable. // Check for a def of a matched pattern. This is guaranteed to always // be a register so we can blindly use that. StringRef GoodOpName; for (auto It = TECs.findLeader(OpName); It != TECs.member_end(); ++It) { - if (*It == OpName) + if (!AllowSelf && *It == OpName) continue; const auto LookupRes = MatchOpTable.lookup(*It); -- GitLab From 51afb101743855e2ae2624ebbe087da77128d92c Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 9 Jan 2024 10:50:08 +0000 Subject: [PATCH 178/652] [LV] Create block in mask up-front if needed. (#76635) At the moment, block and edge masks are created on demand, which means that they are inserted at the point where they are demanded and then cached. It is possible that the mask for a block is looked up later at a point that's not dominated by the point where the mask has been inserted. To avoid this, create masks up front on entry to the corresponding basic block and leave it to VPlan simplification to remove unneeded masks. Note that we need to create masks for all blocks, if any of the blocks in the loop needs predication, as computing the mask of a block depends on the masks of its predecessor. Needed for #76090. https://github.com/llvm/llvm-project/pull/76635 --- .../Transforms/Vectorize/LoopVectorize.cpp | 52 +++++----- .../Transforms/Vectorize/VPRecipeBuilder.h | 7 +- .../lib/Transforms/Vectorize/VPlanRecipes.cpp | 1 + .../LoopVectorize/AArch64/masked-call.ll | 4 +- .../AArch64/scalable-strict-fadd.ll | 4 +- .../sve-interleaved-masked-accesses.ll | 8 +- .../AArch64/sve-tail-folding-reductions.ll | 4 +- .../AArch64/sve-tail-folding-unroll.ll | 8 +- .../LoopVectorize/AArch64/sve-tail-folding.ll | 2 +- .../LoopVectorize/RISCV/uniform-load-store.ll | 8 +- .../X86/drop-poison-generating-flags.ll | 14 +-- .../X86/imprecise-through-phis.ll | 4 +- .../LoopVectorize/X86/masked_load_store.ll | 96 +++++++++---------- .../x86-interleaved-accesses-masked-group.ll | 12 +-- .../LoopVectorize/if-conversion-nest.ll | 4 +- .../LoopVectorize/if-pred-non-void.ll | 6 +- .../Transforms/LoopVectorize/if-reduction.ll | 10 +- .../load-of-struct-deref-pred.ll | 2 +- .../pr55167-fold-tail-live-out.ll | 10 +- .../LoopVectorize/reduction-inloop-pred.ll | 2 +- .../LoopVectorize/reduction-inloop.ll | 2 +- .../Transforms/LoopVectorize/reduction.ll | 2 +- .../LoopVectorize/single-value-blend-phis.ll | 8 +- .../Transforms/LoopVectorize/uniform-blend.ll | 4 +- .../LoopVectorize/vplan-printing.ll | 2 +- .../vplan-sink-scalars-and-merge.ll | 8 +- 26 files changed, 148 insertions(+), 136 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 8b6212aaa358..51ce88480c08 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -7947,7 +7947,7 @@ VPValue *VPRecipeBuilder::createEdgeMask(BasicBlock *Src, BasicBlock *Dst, if (ECEntryIt != EdgeMaskCache.end()) return ECEntryIt->second; - VPValue *SrcMask = createBlockInMask(Src, Plan); + VPValue *SrcMask = getBlockInMask(Src); // The terminator has to be a branch inst! BranchInst *BI = dyn_cast(Src->getTerminator()); @@ -8009,14 +8009,17 @@ void VPRecipeBuilder::createHeaderMask(VPlan &Plan) { BlockMaskCache[Header] = BlockMask; } -VPValue *VPRecipeBuilder::createBlockInMask(BasicBlock *BB, VPlan &Plan) { - assert(OrigLoop->contains(BB) && "Block is not a part of a loop"); - - // Look for cached value. - BlockMaskCacheTy::iterator BCEntryIt = BlockMaskCache.find(BB); - if (BCEntryIt != BlockMaskCache.end()) - return BCEntryIt->second; +VPValue *VPRecipeBuilder::getBlockInMask(BasicBlock *BB) const { + // Return the cached value. + BlockMaskCacheTy::const_iterator BCEntryIt = BlockMaskCache.find(BB); + assert(BCEntryIt != BlockMaskCache.end() && + "Trying to access mask for block without one."); + return BCEntryIt->second; +} +void VPRecipeBuilder::createBlockInMask(BasicBlock *BB, VPlan &Plan) { + assert(OrigLoop->contains(BB) && "Block is not a part of a loop"); + assert(BlockMaskCache.count(BB) == 0 && "Mask for block already computed"); assert(OrigLoop->getHeader() != BB && "Loop header must have cached block mask"); @@ -8026,8 +8029,9 @@ VPValue *VPRecipeBuilder::createBlockInMask(BasicBlock *BB, VPlan &Plan) { // This is the block mask. We OR all incoming edges. for (auto *Predecessor : predecessors(BB)) { VPValue *EdgeMask = createEdgeMask(Predecessor, BB, Plan); - if (!EdgeMask) // Mask of predecessor is all-one so mask of block is too. - return BlockMaskCache[BB] = EdgeMask; + if (!EdgeMask) { // Mask of predecessor is all-one so mask of block is too. + BlockMaskCache[BB] = EdgeMask; + } if (!BlockMask) { // BlockMask has its initialized nullptr value. BlockMask = EdgeMask; @@ -8037,7 +8041,7 @@ VPValue *VPRecipeBuilder::createBlockInMask(BasicBlock *BB, VPlan &Plan) { BlockMask = Builder.createOr(BlockMask, EdgeMask, {}); } - return BlockMaskCache[BB] = BlockMask; + BlockMaskCache[BB] = BlockMask; } VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(Instruction *I, @@ -8065,7 +8069,7 @@ VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(Instruction *I, VPValue *Mask = nullptr; if (Legal->isMaskRequired(I)) - Mask = createBlockInMask(I->getParent(), *Plan); + Mask = getBlockInMask(I->getParent()); // Determine if the pointer operand of the access is either consecutive or // reverse consecutive. @@ -8287,7 +8291,7 @@ VPWidenCallRecipe *VPRecipeBuilder::tryToWidenCall(CallInst *CI, // all-true mask. VPValue *Mask = nullptr; if (Legal->isMaskRequired(CI)) - Mask = createBlockInMask(CI->getParent(), *Plan); + Mask = getBlockInMask(CI->getParent()); else Mask = Plan->getVPValueOrAddLiveIn(ConstantInt::getTrue( IntegerType::getInt1Ty(Variant->getFunctionType()->getContext()))); @@ -8330,7 +8334,7 @@ VPRecipeBase *VPRecipeBuilder::tryToWiden(Instruction *I, // div/rem operation itself. Otherwise fall through to general handling below. if (CM.isPredicatedInst(I)) { SmallVector Ops(Operands.begin(), Operands.end()); - VPValue *Mask = createBlockInMask(I->getParent(), *Plan); + VPValue *Mask = getBlockInMask(I->getParent()); VPValue *One = Plan->getVPValueOrAddLiveIn( ConstantInt::get(I->getType(), 1u, false)); auto *SafeRHS = @@ -8424,7 +8428,7 @@ VPRecipeOrVPValueTy VPRecipeBuilder::handleReplication(Instruction *I, // added initially. Masked replicate recipes will later be placed under an // if-then construct to prevent side-effects. Generate recipes to compute // the block mask for this region. - BlockInMask = createBlockInMask(I->getParent(), Plan); + BlockInMask = getBlockInMask(I->getParent()); } auto *Recipe = new VPReplicateRecipe(I, Plan.mapToVPValues(I->operands()), @@ -8659,16 +8663,16 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) { bool HasNUW = Style == TailFoldingStyle::None; addCanonicalIVRecipes(*Plan, Legal->getWidestInductionType(), HasNUW, DL); - // Proactively create header mask. Masks for other blocks are created on - // demand. - RecipeBuilder.createHeaderMask(*Plan); - // Scan the body of the loop in a topological order to visit each basic block // after having visited its predecessor basic blocks. LoopBlocksDFS DFS(OrigLoop); DFS.perform(LI); VPBasicBlock *VPBB = HeaderVPBB; + bool NeedsMasks = CM.foldTailByMasking() || + any_of(OrigLoop->blocks(), [this](BasicBlock *BB) { + return Legal->blockNeedsPredication(BB); + }); for (BasicBlock *BB : make_range(DFS.beginRPO(), DFS.endRPO())) { // Relevant instructions from basic block BB will be grouped into VPRecipe // ingredients and fill a new VPBasicBlock. @@ -8676,6 +8680,11 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) { VPBB->setName(BB->getName()); Builder.setInsertPoint(VPBB); + if (VPBB == HeaderVPBB) + RecipeBuilder.createHeaderMask(*Plan); + else if (NeedsMasks) + RecipeBuilder.createBlockInMask(BB, *Plan); + // Introduce each ingredient into VPlan. // TODO: Model and preserve debug intrinsics in VPlan. for (Instruction &I : drop_end(BB->instructionsWithoutDebug(false))) { @@ -9024,7 +9033,7 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( if (CM.blockNeedsPredicationForAnyReason(BB)) { VPBuilder::InsertPointGuard Guard(Builder); Builder.setInsertPoint(CurrentLink); - CondOp = RecipeBuilder.createBlockInMask(BB, *Plan); + CondOp = RecipeBuilder.getBlockInMask(BB); } VPReductionRecipe *RedRecipe = new VPReductionRecipe( @@ -9052,8 +9061,7 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( auto *OrigExitingVPV = PhiR->getBackedgeValue(); auto *NewExitingVPV = PhiR->getBackedgeValue(); if (!PhiR->isInLoop() && CM.foldTailByMasking()) { - VPValue *Cond = - RecipeBuilder.createBlockInMask(OrigLoop->getHeader(), *Plan); + VPValue *Cond = RecipeBuilder.getBlockInMask(OrigLoop->getHeader()); assert(OrigExitingVPV->getDefiningRecipe()->getParent() != LatchVPBB && "reduction recipe must be defined before latch"); Type *PhiTy = PhiR->getOperand(0)->getLiveInIRValue()->getType(); diff --git a/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h b/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h index 7ff6749a0908..4b3143aead46 100644 --- a/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h +++ b/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h @@ -138,8 +138,11 @@ public: /// A helper function that computes the predicate of the block BB, assuming /// that the header block of the loop is set to True or the loop mask when - /// tail folding. It returns the *entry* mask for the block BB. - VPValue *createBlockInMask(BasicBlock *BB, VPlan &Plan); + /// tail folding. + void createBlockInMask(BasicBlock *BB, VPlan &Plan); + + /// Returns the *entry* mask for the block \p BB. + VPValue *getBlockInMask(BasicBlock *BB) const; /// A helper function that computes the predicate of the edge between SRC /// and DST. diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 349544f9e390..1f844bce2310 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -120,6 +120,7 @@ bool VPRecipeBase::mayHaveSideEffects() const { return false; case VPInstructionSC: switch (cast(this)->getOpcode()) { + case Instruction::Or: case Instruction::ICmp: case Instruction::Select: case VPInstruction::Not: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll b/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll index 144b29d84198..d2ef5b2d14bc 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll @@ -175,9 +175,9 @@ define void @test_if_then(ptr noalias %a, ptr readnone %b) #4 { ; TFCOMMON-NEXT: [[TMP8:%.*]] = call @foo_vector( [[WIDE_MASKED_LOAD]], [[TMP7]]) ; TFCOMMON-NEXT: [[TMP9:%.*]] = xor [[TMP6]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; TFCOMMON-NEXT: [[TMP10:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP9]], zeroinitializer +; TFCOMMON-NEXT: [[TMP12:%.*]] = or [[TMP7]], [[TMP10]] ; TFCOMMON-NEXT: [[PREDPHI:%.*]] = select [[TMP10]], zeroinitializer, [[TMP8]] ; TFCOMMON-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[B:%.*]], i64 [[INDEX]] -; TFCOMMON-NEXT: [[TMP12:%.*]] = or [[TMP7]], [[TMP10]] ; TFCOMMON-NEXT: call void @llvm.masked.store.nxv2i64.p0( [[PREDPHI]], ptr [[TMP11]], i32 8, [[TMP12]]) ; TFCOMMON-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP14]] ; TFCOMMON-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_NEXT]], i64 1025) @@ -298,9 +298,9 @@ define void @test_widen_if_then_else(ptr noalias %a, ptr readnone %b) #4 { ; TFCOMMON-NEXT: [[TMP9:%.*]] = call @foo_vector( zeroinitializer, [[TMP8]]) ; TFCOMMON-NEXT: [[TMP10:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP6]], zeroinitializer ; TFCOMMON-NEXT: [[TMP11:%.*]] = call @foo_vector( [[WIDE_MASKED_LOAD]], [[TMP10]]) +; TFCOMMON-NEXT: [[TMP13:%.*]] = or [[TMP8]], [[TMP10]] ; TFCOMMON-NEXT: [[PREDPHI:%.*]] = select [[TMP8]], [[TMP9]], [[TMP11]] ; TFCOMMON-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[B:%.*]], i64 [[INDEX]] -; TFCOMMON-NEXT: [[TMP13:%.*]] = or [[TMP8]], [[TMP10]] ; TFCOMMON-NEXT: call void @llvm.masked.store.nxv2i64.p0( [[PREDPHI]], ptr [[TMP12]], i32 8, [[TMP13]]) ; TFCOMMON-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP15]] ; TFCOMMON-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_NEXT]], i64 1025) diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll index e51190bae612..fc67fb5aded6 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll @@ -1250,14 +1250,14 @@ define float @fadd_conditional(ptr noalias nocapture readonly %a, ptr noalias no ; CHECK-ORDERED-TF-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i32 0 ; CHECK-ORDERED-TF-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call @llvm.masked.load.nxv4f32.p0(ptr [[TMP12]], i32 4, [[ACTIVE_LANE_MASK]], poison) ; CHECK-ORDERED-TF-NEXT: [[TMP13:%.*]] = fcmp une [[WIDE_MASKED_LOAD]], zeroinitializer -; CHECK-ORDERED-TF-NEXT: [[TMP14:%.*]] = getelementptr float, ptr [[A]], i64 [[TMP10]] ; CHECK-ORDERED-TF-NEXT: [[TMP15:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP13]], zeroinitializer +; CHECK-ORDERED-TF-NEXT: [[TMP14:%.*]] = getelementptr float, ptr [[A]], i64 [[TMP10]] ; CHECK-ORDERED-TF-NEXT: [[TMP16:%.*]] = getelementptr float, ptr [[TMP14]], i32 0 ; CHECK-ORDERED-TF-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call @llvm.masked.load.nxv4f32.p0(ptr [[TMP16]], i32 4, [[TMP15]], poison) ; CHECK-ORDERED-TF-NEXT: [[TMP17:%.*]] = xor [[TMP13]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; CHECK-ORDERED-TF-NEXT: [[TMP18:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP17]], zeroinitializer -; CHECK-ORDERED-TF-NEXT: [[PREDPHI:%.*]] = select [[TMP18]], shufflevector ( insertelement ( poison, float 3.000000e+00, i64 0), poison, zeroinitializer), [[WIDE_MASKED_LOAD1]] ; CHECK-ORDERED-TF-NEXT: [[TMP19:%.*]] = or [[TMP15]], [[TMP18]] +; CHECK-ORDERED-TF-NEXT: [[PREDPHI:%.*]] = select [[TMP18]], shufflevector ( insertelement ( poison, float 3.000000e+00, i64 0), poison, zeroinitializer), [[WIDE_MASKED_LOAD1]] ; CHECK-ORDERED-TF-NEXT: [[TMP20:%.*]] = select [[TMP19]], [[PREDPHI]], shufflevector ( insertelement ( poison, float -0.000000e+00, i64 0), poison, zeroinitializer) ; CHECK-ORDERED-TF-NEXT: [[TMP21]] = call float @llvm.vector.reduce.fadd.nxv4f32(float [[VEC_PHI]], [[TMP20]]) ; CHECK-ORDERED-TF-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP23]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll index 1b5df2c1bfb8..3ba91360850e 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll @@ -130,10 +130,10 @@ define dso_local void @masked_strided1(ptr noalias nocapture readonly %p, ptr no ; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] ; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND:%.*]] = phi [ [[TMP3]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP6:%.*]] = icmp ugt [[VEC_IND]], [[BROADCAST_SPLAT]] +; PREDICATED_TAIL_FOLDING-NEXT: [[TMP10:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP6]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP7:%.*]] = shl i32 [[INDEX]], 1 ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64 ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP8]] -; PREDICATED_TAIL_FOLDING-NEXT: [[TMP10:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP6]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK:%.*]] = call @llvm.experimental.vector.interleave2.nxv32i1( [[TMP10]], [[TMP10]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[WIDE_MASKED_VEC:%.*]] = call @llvm.masked.load.nxv32i8.p0(ptr [[TMP9]], i32 1, [[INTERLEAVED_MASK]], poison) ; PREDICATED_TAIL_FOLDING-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv32i8( [[WIDE_MASKED_VEC]]) @@ -309,10 +309,10 @@ define dso_local void @masked_strided2(ptr noalias nocapture readnone %p, ptr no ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[Q]], [[TMP7]] ; PREDICATED_TAIL_FOLDING-NEXT: call void @llvm.masked.scatter.nxv16i8.nxv16p0( shufflevector ( insertelement ( poison, i8 1, i64 0), poison, zeroinitializer), [[TMP8]], i32 1, [[ACTIVE_LANE_MASK]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP9:%.*]] = icmp ugt [[VEC_IND]], [[BROADCAST_SPLAT]] +; PREDICATED_TAIL_FOLDING-NEXT: [[TMP13:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP9]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP10:%.*]] = or disjoint [[TMP6]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP11:%.*]] = zext nneg [[TMP10]] to ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[Q]], [[TMP11]] -; PREDICATED_TAIL_FOLDING-NEXT: [[TMP13:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP9]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: call void @llvm.masked.scatter.nxv16i8.nxv16p0( shufflevector ( insertelement ( poison, i8 2, i64 0), poison, zeroinitializer), [[TMP12]], i32 1, [[TMP13]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP15]] ; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[INDEX]], i32 [[TMP2]]) @@ -479,15 +479,15 @@ define dso_local void @masked_strided3(ptr noalias nocapture readnone %p, ptr no ; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND:%.*]] = phi [ [[TMP3]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP6:%.*]] = shl nuw nsw [[VEC_IND]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP7:%.*]] = icmp ugt [[VEC_IND]], [[BROADCAST_SPLAT]] +; PREDICATED_TAIL_FOLDING-NEXT: [[TMP10:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP7]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP8:%.*]] = zext nneg [[TMP6]] to ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[Q]], [[TMP8]] -; PREDICATED_TAIL_FOLDING-NEXT: [[TMP10:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP7]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: call void @llvm.masked.scatter.nxv16i8.nxv16p0( shufflevector ( insertelement ( poison, i8 1, i64 0), poison, zeroinitializer), [[TMP9]], i32 1, [[TMP10]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP11:%.*]] = icmp ugt [[VEC_IND]], [[BROADCAST_SPLAT2]] +; PREDICATED_TAIL_FOLDING-NEXT: [[TMP15:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP11]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP12:%.*]] = or disjoint [[TMP6]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP13:%.*]] = zext nneg [[TMP12]] to ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[Q]], [[TMP13]] -; PREDICATED_TAIL_FOLDING-NEXT: [[TMP15:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP11]], zeroinitializer ; PREDICATED_TAIL_FOLDING-NEXT: call void @llvm.masked.scatter.nxv16i8.nxv16p0( shufflevector ( insertelement ( poison, i8 2, i64 0), poison, zeroinitializer), [[TMP14]], i32 1, [[TMP15]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP17]] ; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[INDEX]], i32 [[TMP2]]) diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll index 70e50992b438..9dcc751db7cf 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll @@ -299,8 +299,8 @@ define i32 @cond_xor_reduction(ptr noalias %a, ptr noalias %cond, i64 %N) #0 { ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i32 0 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call @llvm.masked.load.nxv4i32.p0(ptr [[TMP12]], i32 4, [[ACTIVE_LANE_MASK]], poison) ; CHECK-NEXT: [[TMP13:%.*]] = icmp eq [[WIDE_MASKED_LOAD]], shufflevector ( insertelement ( poison, i32 5, i64 0), poison, zeroinitializer) -; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[A:%.*]], i64 [[TMP10]] ; CHECK-NEXT: [[TMP15:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP13]], zeroinitializer +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[A:%.*]], i64 [[TMP10]] ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP14]], i32 0 ; CHECK-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call @llvm.masked.load.nxv4i32.p0(ptr [[TMP16]], i32 4, [[TMP15]], poison) ; CHECK-NEXT: [[TMP17:%.*]] = xor [[VEC_PHI]], [[WIDE_MASKED_LOAD1]] @@ -371,8 +371,8 @@ define i32 @cond_xor_reduction(ptr noalias %a, ptr noalias %cond, i64 %N) #0 { ; CHECK-IN-LOOP-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i32 0 ; CHECK-IN-LOOP-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call @llvm.masked.load.nxv4i32.p0(ptr [[TMP12]], i32 4, [[ACTIVE_LANE_MASK]], poison) ; CHECK-IN-LOOP-NEXT: [[TMP13:%.*]] = icmp eq [[WIDE_MASKED_LOAD]], shufflevector ( insertelement ( poison, i32 5, i64 0), poison, zeroinitializer) -; CHECK-IN-LOOP-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[A:%.*]], i64 [[TMP10]] ; CHECK-IN-LOOP-NEXT: [[TMP15:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP13]], zeroinitializer +; CHECK-IN-LOOP-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[A:%.*]], i64 [[TMP10]] ; CHECK-IN-LOOP-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP14]], i32 0 ; CHECK-IN-LOOP-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call @llvm.masked.load.nxv4i32.p0(ptr [[TMP16]], i32 4, [[TMP15]], poison) ; CHECK-IN-LOOP-NEXT: [[TMP17:%.*]] = select [[TMP15]], [[WIDE_MASKED_LOAD1]], zeroinitializer diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll index 02eac8c02d81..1a6e83a61ce7 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll @@ -242,14 +242,14 @@ define void @cond_memset(i32 %val, ptr noalias readonly %cond_ptr, ptr noalias % ; CHECK-NEXT: [[TMP62:%.*]] = icmp ne [[WIDE_MASKED_LOAD10]], zeroinitializer ; CHECK-NEXT: [[TMP63:%.*]] = icmp ne [[WIDE_MASKED_LOAD11]], zeroinitializer ; CHECK-NEXT: [[TMP64:%.*]] = icmp ne [[WIDE_MASKED_LOAD12]], zeroinitializer -; CHECK-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 [[TMP31]] -; CHECK-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[TMP36]] -; CHECK-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[TMP41]] -; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[TMP46]] ; CHECK-NEXT: [[TMP69:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP61]], zeroinitializer ; CHECK-NEXT: [[TMP70:%.*]] = select [[ACTIVE_LANE_MASK7]], [[TMP62]], zeroinitializer ; CHECK-NEXT: [[TMP71:%.*]] = select [[ACTIVE_LANE_MASK8]], [[TMP63]], zeroinitializer ; CHECK-NEXT: [[TMP72:%.*]] = select [[ACTIVE_LANE_MASK9]], [[TMP64]], zeroinitializer +; CHECK-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 [[TMP31]] +; CHECK-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[TMP36]] +; CHECK-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[TMP41]] +; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[TMP46]] ; CHECK-NEXT: [[TMP73:%.*]] = getelementptr i32, ptr [[TMP65]], i32 0 ; CHECK-NEXT: [[TMP74:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP75:%.*]] = mul i64 [[TMP74]], 4 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll index 579e8d4ebb3c..2b2742ca7ccb 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll @@ -480,9 +480,9 @@ define void @cond_uniform_load(ptr noalias %dst, ptr noalias readonly %src, ptr ; CHECK-NEXT: [[TMP15:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP14]], zeroinitializer ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[BROADCAST_SPLAT]], i32 4, [[TMP15]], poison) ; CHECK-NEXT: [[TMP16:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP13]], zeroinitializer +; CHECK-NEXT: [[TMP18:%.*]] = or [[TMP15]], [[TMP16]] ; CHECK-NEXT: [[PREDPHI:%.*]] = select [[TMP16]], zeroinitializer, [[WIDE_MASKED_GATHER]] ; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i64 [[TMP10]] -; CHECK-NEXT: [[TMP18:%.*]] = or [[TMP15]], [[TMP16]] ; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0 ; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0( [[PREDPHI]], ptr [[TMP19]], i32 4, [[TMP18]]) ; CHECK-NEXT: [[INDEX_NEXT2]] = add i64 [[INDEX1]], [[TMP21]] diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll b/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll index 8dc5e5d3ffd1..dcfa9bb105b6 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll @@ -467,9 +467,9 @@ define void @conditional_uniform_load(ptr noalias nocapture %a, ptr noalias noca ; TF-SCALABLE-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv2i64.nxv2p0( [[BROADCAST_SPLAT]], i32 8, [[TMP13]], poison) ; TF-SCALABLE-NEXT: [[TMP14:%.*]] = xor [[TMP12]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; TF-SCALABLE-NEXT: [[TMP15:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP14]], zeroinitializer +; TF-SCALABLE-NEXT: [[TMP17:%.*]] = or [[TMP13]], [[TMP15]] ; TF-SCALABLE-NEXT: [[PREDPHI:%.*]] = select [[TMP13]], [[WIDE_MASKED_GATHER]], zeroinitializer ; TF-SCALABLE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP11]] -; TF-SCALABLE-NEXT: [[TMP17:%.*]] = or [[TMP13]], [[TMP15]] ; TF-SCALABLE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i64, ptr [[TMP16]], i32 0 ; TF-SCALABLE-NEXT: call void @llvm.masked.store.nxv2i64.p0( [[PREDPHI]], ptr [[TMP18]], i32 8, [[TMP17]]) ; TF-SCALABLE-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP20]] @@ -515,9 +515,9 @@ define void @conditional_uniform_load(ptr noalias nocapture %a, ptr noalias noca ; TF-FIXEDLEN-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> [[BROADCAST_SPLAT]], i32 8, <4 x i1> [[TMP2]], <4 x i64> poison) ; TF-FIXEDLEN-NEXT: [[TMP3:%.*]] = xor <4 x i1> [[TMP1]], ; TF-FIXEDLEN-NEXT: [[TMP4:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i1> [[TMP3]], <4 x i1> zeroinitializer +; TF-FIXEDLEN-NEXT: [[TMP6:%.*]] = or <4 x i1> [[TMP2]], [[TMP4]] ; TF-FIXEDLEN-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP2]], <4 x i64> [[WIDE_MASKED_GATHER]], <4 x i64> zeroinitializer ; TF-FIXEDLEN-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP0]] -; TF-FIXEDLEN-NEXT: [[TMP6:%.*]] = or <4 x i1> [[TMP2]], [[TMP4]] ; TF-FIXEDLEN-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP5]], i32 0 ; TF-FIXEDLEN-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[PREDPHI]], ptr [[TMP7]], i32 8, <4 x i1> [[TMP6]]) ; TF-FIXEDLEN-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 @@ -1299,10 +1299,10 @@ define void @conditional_uniform_store(ptr noalias nocapture %a, ptr noalias noc ; TF-SCALABLE-NEXT: [[TMP12:%.*]] = icmp ugt [[VEC_IND]], shufflevector ( insertelement ( poison, i64 10, i64 0), poison, zeroinitializer) ; TF-SCALABLE-NEXT: [[TMP13:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP12]], zeroinitializer ; TF-SCALABLE-NEXT: call void @llvm.masked.scatter.nxv2i64.nxv2p0( [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT2]], i32 8, [[TMP13]]) -; TF-SCALABLE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP11]] ; TF-SCALABLE-NEXT: [[TMP15:%.*]] = xor [[TMP12]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; TF-SCALABLE-NEXT: [[TMP16:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP15]], zeroinitializer ; TF-SCALABLE-NEXT: [[TMP17:%.*]] = or [[TMP13]], [[TMP16]] +; TF-SCALABLE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP11]] ; TF-SCALABLE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i64, ptr [[TMP14]], i32 0 ; TF-SCALABLE-NEXT: call void @llvm.masked.store.nxv2i64.p0( [[BROADCAST_SPLAT]], ptr [[TMP18]], i32 8, [[TMP17]]) ; TF-SCALABLE-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP20]] @@ -1347,10 +1347,10 @@ define void @conditional_uniform_store(ptr noalias nocapture %a, ptr noalias noc ; TF-FIXEDLEN-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i64> [[VEC_IND]], ; TF-FIXEDLEN-NEXT: [[TMP2:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i1> [[TMP1]], <4 x i1> zeroinitializer ; TF-FIXEDLEN-NEXT: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> [[BROADCAST_SPLAT]], <4 x ptr> [[BROADCAST_SPLAT2]], i32 8, <4 x i1> [[TMP2]]) -; TF-FIXEDLEN-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP0]] ; TF-FIXEDLEN-NEXT: [[TMP4:%.*]] = xor <4 x i1> [[TMP1]], ; TF-FIXEDLEN-NEXT: [[TMP5:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i1> [[TMP4]], <4 x i1> zeroinitializer ; TF-FIXEDLEN-NEXT: [[TMP6:%.*]] = or <4 x i1> [[TMP2]], [[TMP5]] +; TF-FIXEDLEN-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP0]] ; TF-FIXEDLEN-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP3]], i32 0 ; TF-FIXEDLEN-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[BROADCAST_SPLAT]], ptr [[TMP7]], i32 8, <4 x i1> [[TMP6]]) ; TF-FIXEDLEN-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 diff --git a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll index 3c6cba1b0022..5944d9036b0a 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll @@ -26,9 +26,9 @@ define void @drop_scalar_nuw_nsw(ptr noalias nocapture readonly %input, ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK: [[TMP4:%.*]] = icmp eq <4 x i64> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP4]], ; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP0]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr float, ptr [[INPUT:%.*]], i64 [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP4]], ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr float, ptr [[TMP6]], i32 0 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[TMP8]], i32 4, <4 x i1> [[TMP7]], <4 x float> poison), !invariant.load !0 entry: @@ -107,10 +107,10 @@ define void @preserve_vector_nuw_nsw(ptr noalias nocapture readonly %input, ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK: [[TMP4:%.*]] = icmp eq <4 x i64> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i1> [[TMP4]], ; CHECK-NEXT: [[TMP5:%.*]] = sub nuw nsw <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP6:%.*]] = mul nuw nsw <4 x i64> [[TMP5]], ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[INPUT:%.*]], <4 x i64> [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i1> [[TMP4]], ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> [[TMP7]], i32 4, <4 x i1> [[TMP8]], <4 x float> poison), !invariant.load !0 entry: br label %loop.header @@ -192,8 +192,8 @@ define void @preserve_nuw_nsw_no_addr(ptr %output) local_unnamed_addr #0 { ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK: [[TMP4:%.*]] = icmp eq <4 x i64> [[VEC_IND]], zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = sub nuw nsw <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i1> [[TMP4]], +; CHECK-NEXT: [[TMP5:%.*]] = sub nuw nsw <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP5]], <4 x i64> zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[OUTPUT:%.*]], i64 [[TMP0]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP7]], i32 0 @@ -234,9 +234,9 @@ define void @drop_scalar_exact(ptr noalias nocapture readonly %input, ; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP5]], zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = and <4 x i1> [[TMP4]], [[TMP6]] +; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], ; CHECK-NEXT: [[TMP8:%.*]] = sdiv i64 [[TMP0]], 1 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr float, ptr [[INPUT:%.*]], i64 [[TMP8]] -; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr float, ptr [[TMP9]], i32 0 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[TMP11]], i32 4, <4 x i1> [[TMP10]], <4 x float> poison), !invariant.load !0 entry: @@ -358,9 +358,9 @@ define void @preserve_vector_exact_no_addr(ptr noalias nocapture readonly %input ; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP5]], zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = and <4 x i1> [[TMP4]], [[TMP6]] +; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], ; CHECK-NEXT: [[TMP8:%.*]] = sdiv exact <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[INPUT:%.*]], <4 x i64> [[TMP8]] -; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> [[TMP9]], i32 4, <4 x i1> [[TMP10]], <4 x float> poison), !invariant.load !0 ; entry: @@ -401,8 +401,8 @@ define void @preserve_exact_no_addr(ptr %output) local_unnamed_addr #0 { ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK: [[TMP4:%.*]] = icmp eq <4 x i64> [[VEC_IND]], zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = sdiv exact <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i1> [[TMP4]], +; CHECK-NEXT: [[TMP5:%.*]] = sdiv exact <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP5]], <4 x i64> zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[OUTPUT:%.*]], i64 [[TMP0]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP7]], i32 0 @@ -579,10 +579,10 @@ define void @Bgep_inbounds_unconditionally_due_to_store(ptr noalias %B, ptr read ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr float, ptr %B, i64 [[TMP0]] +; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP3]], ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[TMP4]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP5]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[WIDE_LOAD2]], -; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP3]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP3]], <4 x float> , <4 x float> [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 0 ; CHECK-NEXT: store <4 x float> [[PREDPHI]], ptr [[TMP8]], align 4 diff --git a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll index 8c33e7b8a59a..fd826ce454ed 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll @@ -78,8 +78,8 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; SSE-NEXT: [[TMP2:%.*]] = getelementptr double, ptr [[TMP1]], i32 0 ; SSE-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP2]], align 8 ; SSE-NEXT: [[TMP3:%.*]] = fcmp fast une <2 x double> [[WIDE_LOAD]], -; SSE-NEXT: [[TMP4:%.*]] = fadd fast <2 x double> [[VEC_PHI]], [[WIDE_LOAD]] ; SSE-NEXT: [[TMP5:%.*]] = xor <2 x i1> [[TMP3]], +; SSE-NEXT: [[TMP4:%.*]] = fadd fast <2 x double> [[VEC_PHI]], [[WIDE_LOAD]] ; SSE-NEXT: [[PREDPHI]] = select <2 x i1> [[TMP3]], <2 x double> [[TMP4]], <2 x double> [[VEC_PHI]] ; SSE-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; SSE-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 32 @@ -125,8 +125,8 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; AVX-NEXT: [[TMP2:%.*]] = getelementptr double, ptr [[TMP1]], i32 0 ; AVX-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP2]], align 8 ; AVX-NEXT: [[TMP3:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD]], -; AVX-NEXT: [[TMP4:%.*]] = fadd fast <4 x double> [[VEC_PHI]], [[WIDE_LOAD]] ; AVX-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP3]], +; AVX-NEXT: [[TMP4:%.*]] = fadd fast <4 x double> [[VEC_PHI]], [[WIDE_LOAD]] ; AVX-NEXT: [[PREDPHI]] = select <4 x i1> [[TMP3]], <4 x double> [[TMP4]], <4 x double> [[VEC_PHI]] ; AVX-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; AVX-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 32 diff --git a/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll b/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll index cf4327791628..eea2894f8279 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll @@ -1661,14 +1661,14 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX1-NEXT: [[TMP17:%.*]] = icmp eq <4 x i8> [[TMP13]], zeroinitializer ; AVX1-NEXT: [[TMP18:%.*]] = icmp eq <4 x i8> [[TMP14]], zeroinitializer ; AVX1-NEXT: [[TMP19:%.*]] = icmp eq <4 x i8> [[TMP15]], zeroinitializer -; AVX1-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] -; AVX1-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] -; AVX1-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] -; AVX1-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP24:%.*]] = xor <4 x i1> [[TMP16]], ; AVX1-NEXT: [[TMP25:%.*]] = xor <4 x i1> [[TMP17]], ; AVX1-NEXT: [[TMP26:%.*]] = xor <4 x i1> [[TMP18]], ; AVX1-NEXT: [[TMP27:%.*]] = xor <4 x i1> [[TMP19]], +; AVX1-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] +; AVX1-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] +; AVX1-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] +; AVX1-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP28:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 0 ; AVX1-NEXT: [[TMP29:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 4 ; AVX1-NEXT: [[TMP30:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 8 @@ -1681,10 +1681,6 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX1-NEXT: [[TMP33:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD4]], zeroinitializer ; AVX1-NEXT: [[TMP34:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD5]], zeroinitializer ; AVX1-NEXT: [[TMP35:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD6]], zeroinitializer -; AVX1-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] -; AVX1-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] -; AVX1-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] -; AVX1-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP40:%.*]] = xor <4 x i1> [[TMP32]], ; AVX1-NEXT: [[TMP41:%.*]] = xor <4 x i1> [[TMP33]], ; AVX1-NEXT: [[TMP42:%.*]] = xor <4 x i1> [[TMP34]], @@ -1693,6 +1689,10 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX1-NEXT: [[TMP45:%.*]] = select <4 x i1> [[TMP25]], <4 x i1> [[TMP41]], <4 x i1> zeroinitializer ; AVX1-NEXT: [[TMP46:%.*]] = select <4 x i1> [[TMP26]], <4 x i1> [[TMP42]], <4 x i1> zeroinitializer ; AVX1-NEXT: [[TMP47:%.*]] = select <4 x i1> [[TMP27]], <4 x i1> [[TMP43]], <4 x i1> zeroinitializer +; AVX1-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] +; AVX1-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] +; AVX1-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] +; AVX1-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP36]], i32 0 ; AVX1-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP36]], i32 4 ; AVX1-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP36]], i32 8 @@ -1773,14 +1773,14 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX2-NEXT: [[TMP17:%.*]] = icmp eq <4 x i8> [[TMP13]], zeroinitializer ; AVX2-NEXT: [[TMP18:%.*]] = icmp eq <4 x i8> [[TMP14]], zeroinitializer ; AVX2-NEXT: [[TMP19:%.*]] = icmp eq <4 x i8> [[TMP15]], zeroinitializer -; AVX2-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] -; AVX2-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] -; AVX2-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] -; AVX2-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP24:%.*]] = xor <4 x i1> [[TMP16]], ; AVX2-NEXT: [[TMP25:%.*]] = xor <4 x i1> [[TMP17]], ; AVX2-NEXT: [[TMP26:%.*]] = xor <4 x i1> [[TMP18]], ; AVX2-NEXT: [[TMP27:%.*]] = xor <4 x i1> [[TMP19]], +; AVX2-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] +; AVX2-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] +; AVX2-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] +; AVX2-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP28:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 0 ; AVX2-NEXT: [[TMP29:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 4 ; AVX2-NEXT: [[TMP30:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 8 @@ -1793,10 +1793,6 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX2-NEXT: [[TMP33:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD4]], zeroinitializer ; AVX2-NEXT: [[TMP34:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD5]], zeroinitializer ; AVX2-NEXT: [[TMP35:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD6]], zeroinitializer -; AVX2-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] -; AVX2-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] -; AVX2-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] -; AVX2-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP40:%.*]] = xor <4 x i1> [[TMP32]], ; AVX2-NEXT: [[TMP41:%.*]] = xor <4 x i1> [[TMP33]], ; AVX2-NEXT: [[TMP42:%.*]] = xor <4 x i1> [[TMP34]], @@ -1805,6 +1801,10 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX2-NEXT: [[TMP45:%.*]] = select <4 x i1> [[TMP25]], <4 x i1> [[TMP41]], <4 x i1> zeroinitializer ; AVX2-NEXT: [[TMP46:%.*]] = select <4 x i1> [[TMP26]], <4 x i1> [[TMP42]], <4 x i1> zeroinitializer ; AVX2-NEXT: [[TMP47:%.*]] = select <4 x i1> [[TMP27]], <4 x i1> [[TMP43]], <4 x i1> zeroinitializer +; AVX2-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] +; AVX2-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] +; AVX2-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] +; AVX2-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP36]], i32 0 ; AVX2-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP36]], i32 4 ; AVX2-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP36]], i32 8 @@ -1885,14 +1885,14 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX512-NEXT: [[TMP17:%.*]] = icmp eq <8 x i8> [[TMP13]], zeroinitializer ; AVX512-NEXT: [[TMP18:%.*]] = icmp eq <8 x i8> [[TMP14]], zeroinitializer ; AVX512-NEXT: [[TMP19:%.*]] = icmp eq <8 x i8> [[TMP15]], zeroinitializer -; AVX512-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] -; AVX512-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] -; AVX512-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] -; AVX512-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP24:%.*]] = xor <8 x i1> [[TMP16]], ; AVX512-NEXT: [[TMP25:%.*]] = xor <8 x i1> [[TMP17]], ; AVX512-NEXT: [[TMP26:%.*]] = xor <8 x i1> [[TMP18]], ; AVX512-NEXT: [[TMP27:%.*]] = xor <8 x i1> [[TMP19]], +; AVX512-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] +; AVX512-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] +; AVX512-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] +; AVX512-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP28:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 0 ; AVX512-NEXT: [[TMP29:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 8 ; AVX512-NEXT: [[TMP30:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 16 @@ -1905,10 +1905,6 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX512-NEXT: [[TMP33:%.*]] = icmp eq <8 x ptr> [[WIDE_MASKED_LOAD4]], zeroinitializer ; AVX512-NEXT: [[TMP34:%.*]] = icmp eq <8 x ptr> [[WIDE_MASKED_LOAD5]], zeroinitializer ; AVX512-NEXT: [[TMP35:%.*]] = icmp eq <8 x ptr> [[WIDE_MASKED_LOAD6]], zeroinitializer -; AVX512-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] -; AVX512-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] -; AVX512-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] -; AVX512-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP40:%.*]] = xor <8 x i1> [[TMP32]], ; AVX512-NEXT: [[TMP41:%.*]] = xor <8 x i1> [[TMP33]], ; AVX512-NEXT: [[TMP42:%.*]] = xor <8 x i1> [[TMP34]], @@ -1917,6 +1913,10 @@ define void @foo7(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX512-NEXT: [[TMP45:%.*]] = select <8 x i1> [[TMP25]], <8 x i1> [[TMP41]], <8 x i1> zeroinitializer ; AVX512-NEXT: [[TMP46:%.*]] = select <8 x i1> [[TMP26]], <8 x i1> [[TMP42]], <8 x i1> zeroinitializer ; AVX512-NEXT: [[TMP47:%.*]] = select <8 x i1> [[TMP27]], <8 x i1> [[TMP43]], <8 x i1> zeroinitializer +; AVX512-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] +; AVX512-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] +; AVX512-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] +; AVX512-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP36]], i32 0 ; AVX512-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP36]], i32 8 ; AVX512-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP36]], i32 16 @@ -2042,14 +2042,14 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX1-NEXT: [[TMP17:%.*]] = icmp eq <4 x i8> [[TMP13]], zeroinitializer ; AVX1-NEXT: [[TMP18:%.*]] = icmp eq <4 x i8> [[TMP14]], zeroinitializer ; AVX1-NEXT: [[TMP19:%.*]] = icmp eq <4 x i8> [[TMP15]], zeroinitializer -; AVX1-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] -; AVX1-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] -; AVX1-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] -; AVX1-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP24:%.*]] = xor <4 x i1> [[TMP16]], ; AVX1-NEXT: [[TMP25:%.*]] = xor <4 x i1> [[TMP17]], ; AVX1-NEXT: [[TMP26:%.*]] = xor <4 x i1> [[TMP18]], ; AVX1-NEXT: [[TMP27:%.*]] = xor <4 x i1> [[TMP19]], +; AVX1-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] +; AVX1-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] +; AVX1-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] +; AVX1-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP28:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 0 ; AVX1-NEXT: [[TMP29:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 4 ; AVX1-NEXT: [[TMP30:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 8 @@ -2062,10 +2062,6 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX1-NEXT: [[TMP33:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD4]], zeroinitializer ; AVX1-NEXT: [[TMP34:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD5]], zeroinitializer ; AVX1-NEXT: [[TMP35:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD6]], zeroinitializer -; AVX1-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] -; AVX1-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] -; AVX1-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] -; AVX1-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP40:%.*]] = xor <4 x i1> [[TMP32]], ; AVX1-NEXT: [[TMP41:%.*]] = xor <4 x i1> [[TMP33]], ; AVX1-NEXT: [[TMP42:%.*]] = xor <4 x i1> [[TMP34]], @@ -2074,6 +2070,10 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX1-NEXT: [[TMP45:%.*]] = select <4 x i1> [[TMP25]], <4 x i1> [[TMP41]], <4 x i1> zeroinitializer ; AVX1-NEXT: [[TMP46:%.*]] = select <4 x i1> [[TMP26]], <4 x i1> [[TMP42]], <4 x i1> zeroinitializer ; AVX1-NEXT: [[TMP47:%.*]] = select <4 x i1> [[TMP27]], <4 x i1> [[TMP43]], <4 x i1> zeroinitializer +; AVX1-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] +; AVX1-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] +; AVX1-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] +; AVX1-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX1-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP36]], i32 0 ; AVX1-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP36]], i32 4 ; AVX1-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP36]], i32 8 @@ -2154,14 +2154,14 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX2-NEXT: [[TMP17:%.*]] = icmp eq <4 x i8> [[TMP13]], zeroinitializer ; AVX2-NEXT: [[TMP18:%.*]] = icmp eq <4 x i8> [[TMP14]], zeroinitializer ; AVX2-NEXT: [[TMP19:%.*]] = icmp eq <4 x i8> [[TMP15]], zeroinitializer -; AVX2-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] -; AVX2-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] -; AVX2-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] -; AVX2-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP24:%.*]] = xor <4 x i1> [[TMP16]], ; AVX2-NEXT: [[TMP25:%.*]] = xor <4 x i1> [[TMP17]], ; AVX2-NEXT: [[TMP26:%.*]] = xor <4 x i1> [[TMP18]], ; AVX2-NEXT: [[TMP27:%.*]] = xor <4 x i1> [[TMP19]], +; AVX2-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] +; AVX2-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] +; AVX2-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] +; AVX2-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP28:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 0 ; AVX2-NEXT: [[TMP29:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 4 ; AVX2-NEXT: [[TMP30:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 8 @@ -2174,10 +2174,6 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX2-NEXT: [[TMP33:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD4]], zeroinitializer ; AVX2-NEXT: [[TMP34:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD5]], zeroinitializer ; AVX2-NEXT: [[TMP35:%.*]] = icmp eq <4 x ptr> [[WIDE_MASKED_LOAD6]], zeroinitializer -; AVX2-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] -; AVX2-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] -; AVX2-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] -; AVX2-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP40:%.*]] = xor <4 x i1> [[TMP32]], ; AVX2-NEXT: [[TMP41:%.*]] = xor <4 x i1> [[TMP33]], ; AVX2-NEXT: [[TMP42:%.*]] = xor <4 x i1> [[TMP34]], @@ -2186,6 +2182,10 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX2-NEXT: [[TMP45:%.*]] = select <4 x i1> [[TMP25]], <4 x i1> [[TMP41]], <4 x i1> zeroinitializer ; AVX2-NEXT: [[TMP46:%.*]] = select <4 x i1> [[TMP26]], <4 x i1> [[TMP42]], <4 x i1> zeroinitializer ; AVX2-NEXT: [[TMP47:%.*]] = select <4 x i1> [[TMP27]], <4 x i1> [[TMP43]], <4 x i1> zeroinitializer +; AVX2-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] +; AVX2-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] +; AVX2-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] +; AVX2-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX2-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP36]], i32 0 ; AVX2-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP36]], i32 4 ; AVX2-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP36]], i32 8 @@ -2266,14 +2266,14 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX512-NEXT: [[TMP17:%.*]] = icmp eq <8 x i8> [[TMP13]], zeroinitializer ; AVX512-NEXT: [[TMP18:%.*]] = icmp eq <8 x i8> [[TMP14]], zeroinitializer ; AVX512-NEXT: [[TMP19:%.*]] = icmp eq <8 x i8> [[TMP15]], zeroinitializer -; AVX512-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] -; AVX512-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] -; AVX512-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] -; AVX512-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP24:%.*]] = xor <8 x i1> [[TMP16]], ; AVX512-NEXT: [[TMP25:%.*]] = xor <8 x i1> [[TMP17]], ; AVX512-NEXT: [[TMP26:%.*]] = xor <8 x i1> [[TMP18]], ; AVX512-NEXT: [[TMP27:%.*]] = xor <8 x i1> [[TMP19]], +; AVX512-NEXT: [[TMP20:%.*]] = getelementptr ptr, ptr [[IN:%.*]], i64 [[TMP0]] +; AVX512-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP1]] +; AVX512-NEXT: [[TMP22:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP2]] +; AVX512-NEXT: [[TMP23:%.*]] = getelementptr ptr, ptr [[IN]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP28:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 0 ; AVX512-NEXT: [[TMP29:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 8 ; AVX512-NEXT: [[TMP30:%.*]] = getelementptr ptr, ptr [[TMP20]], i32 16 @@ -2286,10 +2286,6 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX512-NEXT: [[TMP33:%.*]] = icmp eq <8 x ptr> [[WIDE_MASKED_LOAD4]], zeroinitializer ; AVX512-NEXT: [[TMP34:%.*]] = icmp eq <8 x ptr> [[WIDE_MASKED_LOAD5]], zeroinitializer ; AVX512-NEXT: [[TMP35:%.*]] = icmp eq <8 x ptr> [[WIDE_MASKED_LOAD6]], zeroinitializer -; AVX512-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] -; AVX512-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] -; AVX512-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] -; AVX512-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP40:%.*]] = xor <8 x i1> [[TMP32]], ; AVX512-NEXT: [[TMP41:%.*]] = xor <8 x i1> [[TMP33]], ; AVX512-NEXT: [[TMP42:%.*]] = xor <8 x i1> [[TMP34]], @@ -2298,6 +2294,10 @@ define void @foo8(ptr noalias nocapture %out, ptr noalias nocapture readonly %in ; AVX512-NEXT: [[TMP45:%.*]] = select <8 x i1> [[TMP25]], <8 x i1> [[TMP41]], <8 x i1> zeroinitializer ; AVX512-NEXT: [[TMP46:%.*]] = select <8 x i1> [[TMP26]], <8 x i1> [[TMP42]], <8 x i1> zeroinitializer ; AVX512-NEXT: [[TMP47:%.*]] = select <8 x i1> [[TMP27]], <8 x i1> [[TMP43]], <8 x i1> zeroinitializer +; AVX512-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[OUT:%.*]], i64 [[TMP0]] +; AVX512-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP1]] +; AVX512-NEXT: [[TMP38:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP2]] +; AVX512-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[OUT]], i64 [[TMP3]] ; AVX512-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP36]], i32 0 ; AVX512-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP36]], i32 8 ; AVX512-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP36]], i32 16 diff --git a/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll b/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll index 8633d5e834cc..6b52023cfbca 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll @@ -401,8 +401,8 @@ define dso_local void @masked_strided1_optsize_unknown_tc(ptr noalias nocapture ; DISABLED_MASKED_STRIDED-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_LOAD_CONTINUE16]] ] ; DISABLED_MASKED_STRIDED-NEXT: [[TMP0:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; DISABLED_MASKED_STRIDED-NEXT: [[TMP1:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]] -; DISABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = shl nuw nsw <8 x i32> [[VEC_IND]], ; DISABLED_MASKED_STRIDED-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer +; DISABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = shl nuw nsw <8 x i32> [[VEC_IND]], ; DISABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] ; DISABLED_MASKED_STRIDED: pred.load.if: @@ -511,9 +511,9 @@ define dso_local void @masked_strided1_optsize_unknown_tc(ptr noalias nocapture ; ENABLED_MASKED_STRIDED-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; ENABLED_MASKED_STRIDED-NEXT: [[TMP0:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; ENABLED_MASKED_STRIDED-NEXT: [[TMP1:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]] +; ENABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = shl i32 [[INDEX]], 1 ; ENABLED_MASKED_STRIDED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 [[TMP2]] -; ENABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[INTERLEAVED_MASK:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> poison, <16 x i32> ; ENABLED_MASKED_STRIDED-NEXT: [[TMP5:%.*]] = and <16 x i1> [[INTERLEAVED_MASK]], ; ENABLED_MASKED_STRIDED-NEXT: [[WIDE_MASKED_VEC:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr [[TMP3]], i32 1, <16 x i1> [[TMP5]], <16 x i8> poison) @@ -605,8 +605,8 @@ define dso_local void @masked_strided3_optsize_unknown_tc(ptr noalias nocapture ; DISABLED_MASKED_STRIDED-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_LOAD_CONTINUE16]] ] ; DISABLED_MASKED_STRIDED-NEXT: [[TMP0:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; DISABLED_MASKED_STRIDED-NEXT: [[TMP1:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]] -; DISABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = mul nsw <8 x i32> [[VEC_IND]], ; DISABLED_MASKED_STRIDED-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer +; DISABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = mul nsw <8 x i32> [[VEC_IND]], ; DISABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] ; DISABLED_MASKED_STRIDED: pred.load.if: @@ -715,9 +715,9 @@ define dso_local void @masked_strided3_optsize_unknown_tc(ptr noalias nocapture ; ENABLED_MASKED_STRIDED-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; ENABLED_MASKED_STRIDED-NEXT: [[TMP0:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; ENABLED_MASKED_STRIDED-NEXT: [[TMP1:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]] +; ENABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = mul i32 [[INDEX]], 3 ; ENABLED_MASKED_STRIDED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 [[TMP2]] -; ENABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[INTERLEAVED_MASK:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> poison, <24 x i32> ; ENABLED_MASKED_STRIDED-NEXT: [[TMP5:%.*]] = and <24 x i1> [[INTERLEAVED_MASK]], ; ENABLED_MASKED_STRIDED-NEXT: [[WIDE_MASKED_VEC:%.*]] = call <24 x i8> @llvm.masked.load.v24i8.p0(ptr [[TMP3]], i32 1, <24 x i1> [[TMP5]], <24 x i8> poison) @@ -2214,8 +2214,8 @@ define dso_local void @masked_strided2_unknown_tc(ptr noalias nocapture readonly ; DISABLED_MASKED_STRIDED-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE62]] ] ; DISABLED_MASKED_STRIDED-NEXT: [[TMP0:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; DISABLED_MASKED_STRIDED-NEXT: [[TMP1:%.*]] = icmp sgt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]] -; DISABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = shl nuw nsw <8 x i32> [[VEC_IND]], ; DISABLED_MASKED_STRIDED-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer +; DISABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = shl nuw nsw <8 x i32> [[VEC_IND]], ; DISABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] ; DISABLED_MASKED_STRIDED: pred.load.if: @@ -2548,9 +2548,9 @@ define dso_local void @masked_strided2_unknown_tc(ptr noalias nocapture readonly ; ENABLED_MASKED_STRIDED-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; ENABLED_MASKED_STRIDED-NEXT: [[TMP0:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; ENABLED_MASKED_STRIDED-NEXT: [[TMP1:%.*]] = icmp sgt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]] +; ENABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[TMP2:%.*]] = shl i32 [[INDEX]], 1 ; ENABLED_MASKED_STRIDED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 [[TMP2]] -; ENABLED_MASKED_STRIDED-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i1> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[INTERLEAVED_MASK:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> poison, <16 x i32> ; ENABLED_MASKED_STRIDED-NEXT: [[WIDE_MASKED_VEC:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr [[TMP3]], i32 1, <16 x i1> [[INTERLEAVED_MASK]], <16 x i8> poison) ; ENABLED_MASKED_STRIDED-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i8> [[WIDE_MASKED_VEC]], <16 x i8> poison, <8 x i32> diff --git a/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll b/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll index 107e9ea189bc..b55c4214ec59 100644 --- a/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll +++ b/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll @@ -34,11 +34,11 @@ define i32 @foo(ptr nocapture %A, ptr nocapture %B, i32 %n) { ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4, !alias.scope [[META3]] ; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD2]] ; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], +; CHECK-NEXT: [[TMP12:%.*]] = xor <4 x i1> [[TMP8]], +; CHECK-NEXT: [[TMP13:%.*]] = and <4 x i1> [[TMP7]], [[TMP12]] ; CHECK-NEXT: [[TMP9:%.*]] = icmp slt <4 x i32> [[WIDE_LOAD2]], ; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[TMP9]], <4 x i32> , <4 x i32> ; CHECK-NEXT: [[TMP11:%.*]] = and <4 x i1> [[TMP7]], [[TMP8]] -; CHECK-NEXT: [[TMP12:%.*]] = xor <4 x i1> [[TMP8]], -; CHECK-NEXT: [[TMP13:%.*]] = and <4 x i1> [[TMP7]], [[TMP12]] ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> , <4 x i32> ; CHECK-NEXT: [[PREDPHI3:%.*]] = select <4 x i1> [[TMP13]], <4 x i32> [[TMP10]], <4 x i32> [[PREDPHI]] ; CHECK-NEXT: store <4 x i32> [[PREDPHI3]], ptr [[TMP5]], align 4, !alias.scope [[META0]], !noalias [[META3]] diff --git a/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll b/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll index e7e7c58b5d29..7e0727348b01 100644 --- a/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll +++ b/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll @@ -562,8 +562,8 @@ define void @pr30172(ptr nocapture %asd, ptr nocapture %bsd) !dbg !5 {; ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4, !alias.scope !32 ; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], -; CHECK-NEXT: [[TMP7:%.*]] = icmp sge <2 x i32> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i1> [[TMP6]], , !dbg [[DBG34:![0-9]+]] +; CHECK-NEXT: [[TMP7:%.*]] = icmp sge <2 x i32> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP8]], <2 x i1> [[TMP7]], <2 x i1> zeroinitializer, !dbg [[DBG35:![0-9]+]] ; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP6]] ; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP10]], i32 0 @@ -652,10 +652,10 @@ define void @pr30172(ptr nocapture %asd, ptr nocapture %bsd) !dbg !5 {; ; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = add nsw i32 [[TMP5]], 23 ; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP4]], 100 ; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = icmp slt i32 [[TMP5]], 100 -; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = icmp sge i32 [[TMP4]], 200 -; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP5]], 200 ; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = xor i1 [[TMP12]], true, !dbg [[DBG34:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = xor i1 [[TMP13]], true, !dbg [[DBG34]] +; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = icmp sge i32 [[TMP4]], 200 +; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP5]], 200 ; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = select i1 [[TMP16]], i1 [[TMP14]], i1 false, !dbg [[DBG35:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = select i1 [[TMP17]], i1 [[TMP15]], i1 false, !dbg [[DBG35]] ; UNROLL-NO-VF-NEXT: [[TMP20:%.*]] = or i1 [[TMP18]], [[TMP12]] diff --git a/llvm/test/Transforms/LoopVectorize/if-reduction.ll b/llvm/test/Transforms/LoopVectorize/if-reduction.ll index 6ef5d62b6505..d5a26e97eec3 100644 --- a/llvm/test/Transforms/LoopVectorize/if-reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/if-reduction.ll @@ -606,13 +606,13 @@ for.end: ; preds = %for.body, %entry ; CHECK-LABEL: @fcmp_multi( ; CHECK: %[[C1:.*]] = fcmp ogt <4 x float> %[[V0:.*]], %[[C1]], %[[V0]], %[[C2]], %[[C11]], <4 x i1> %[[C21]], <4 x i1> zeroinitializer ; CHECK-DAG: %[[M1:.*]] = fmul fast <4 x float> %[[V0]], %[[V0]], %[[C1]], %[[C11]], <4 x i1> %[[C2]], <4 x i1> zeroinitializer -; CHECK-DAG: %[[C21:.*]] = xor <4 x i1> %[[C2]], %[[C11]], <4 x i1> %[[C21]], <4 x i1> zeroinitializer ; CHECK: %[[S1:.*]] = select <4 x i1> %[[C22]], <4 x float> %[[M1]], <4 x float> %[[M2]] ; CHECK: %[[S2:.*]] = select <4 x i1> %[[C1]], <4 x float> %[[V0]], <4 x float> %[[S1]] ; CHECK: fadd fast <4 x float> %[[S2]], @@ -674,12 +674,12 @@ for.end: ; preds = %for.inc, %entry ; CHECK-LABEL: @fcmp_fadd_fsub( ; CHECK: %[[C1:.*]] = fcmp ogt <4 x float> %[[V0:.*]], %[[C1]], %[[V0]], %[[C2]], ; CHECK-DAG: %[[ADD:.*]] = fadd fast <4 x float> -; CHECK: %[[C11:.*]] = xor <4 x i1> %[[C1]], %[[C11]], <4 x i1> %[[C2]], <4 x i1> zeroinitializer -; CHECK-DAG: %[[C21:.*]] = xor <4 x i1> %[[C2]], %[[C11]], <4 x i1> %[[C21]], <4 x i1> zeroinitializer ; CHECK: %[[S1:.*]] = select <4 x i1> %[[C12]], <4 x float> %[[SUB]], <4 x float> %[[ADD]] ; CHECK: %[[S2:.*]] = select <4 x i1> %[[C22]], {{.*}} <4 x float> %[[S1]] diff --git a/llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll b/llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll index 7ddb8643beda..327ffaad63a6 100644 --- a/llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll +++ b/llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll @@ -21,13 +21,13 @@ define void @accesses_to_struct_dereferenceable(ptr noalias %dst) { ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <4 x i32> [[WIDE_LOAD]], zeroinitializer +; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i1> [[TMP3]], ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_FOO:%.*]], ptr @foo, i64 0, i32 1, i64 [[TMP0]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_FOO]], ptr @foo, i64 0, i32 0, i64 [[TMP0]] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i1> [[TMP3]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP8]], <4 x i32> [[WIDE_LOAD1]], <4 x i32> [[WIDE_LOAD2]] ; CHECK-NEXT: store <4 x i32> [[PREDPHI]], ptr [[TMP2]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 diff --git a/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll b/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll index e968d452009a..66153a002d0d 100644 --- a/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll +++ b/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll @@ -6,25 +6,25 @@ define i32 @test(i32 %a, i1 %c.1, i1 %c.2 ) #0 { ; CHECK-NEXT: bb: ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i1> poison, i1 [[C_1:%.*]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT1]], <2 x i1> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <2 x i1> poison, i1 [[C_2:%.*]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT3]], <2 x i1> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ , [[VECTOR_PH]] ], [ [[PREDPHI7:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT2]], ; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i32> [[VEC_PHI]], +; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT4]], +; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[TMP4]], <2 x i1> [[TMP6]], <2 x i1> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[TMP0]], ; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[BROADCAST_SPLAT]], ; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT2]], ; CHECK-NEXT: [[TMP5:%.*]] = select <2 x i1> [[TMP4]], <2 x i1> [[BROADCAST_SPLAT4]], <2 x i1> zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT4]], -; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[TMP4]], <2 x i1> [[TMP6]], <2 x i1> zeroinitializer ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP5]], <2 x i32> , <2 x i32> [[VEC_IND]] ; CHECK-NEXT: [[PREDPHI5:%.*]] = select <2 x i1> [[TMP7]], <2 x i32> , <2 x i32> [[PREDPHI]] ; CHECK-NEXT: [[PREDPHI6:%.*]] = select <2 x i1> [[TMP5]], <2 x i32> [[TMP0]], <2 x i32> [[VEC_PHI]] diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll index 0b0da0a22c27..b1c5ccbead64 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll @@ -1355,8 +1355,8 @@ define float @reduction_conditional(ptr %A, ptr %B, ptr %C, float %S) { ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP3]], align 4 ; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]] ; CHECK-NEXT: [[TMP6:%.*]] = fcmp ule <4 x float> [[WIDE_LOAD1]], -; CHECK-NEXT: [[TMP7:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP8:%.*]] = and <4 x i1> [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP9:%.*]] = and <4 x i1> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], ; CHECK-NEXT: [[TMP11:%.*]] = and <4 x i1> [[TMP8]], [[TMP10]] diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll index a7eb504cf296..d85241167d0c 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll @@ -690,8 +690,8 @@ define float @reduction_conditional(ptr %A, ptr %B, ptr %C, float %S) { ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]] ; CHECK-NEXT: [[TMP4:%.*]] = fcmp ule <4 x float> [[WIDE_LOAD1]], -; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i1> [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP7:%.*]] = and <4 x i1> [[TMP6]], [[TMP5]] ; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i1> [[TMP5]], ; CHECK-NEXT: [[TMP9:%.*]] = and <4 x i1> [[TMP6]], [[TMP8]] diff --git a/llvm/test/Transforms/LoopVectorize/reduction.ll b/llvm/test/Transforms/LoopVectorize/reduction.ll index 757b41db6a5b..ba82bac6fad2 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction.ll @@ -761,8 +761,8 @@ define float @reduction_conditional(ptr %A, ptr %B, ptr %C, float %S) { ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]] ; CHECK-NEXT: [[TMP4:%.*]] = fcmp ule <4 x float> [[WIDE_LOAD1]], -; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i1> [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP7:%.*]] = and <4 x i1> [[TMP6]], [[TMP5]] ; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i1> [[TMP5]], ; CHECK-NEXT: [[TMP9:%.*]] = and <4 x i1> [[TMP6]], [[TMP8]] diff --git a/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll b/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll index 47271ba11acb..4087f9b140e3 100644 --- a/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll +++ b/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll @@ -111,10 +111,10 @@ define void @single_incoming_phi_with_blend_mask(i64 %a, i64 %b) { ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i16, ptr [[TMP4]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i16>, ptr [[TMP5]], align 1 ; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt <2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP7:%.*]] = xor <2 x i1> [[TMP3]], +; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP3]], <2 x i1> [[TMP6]], <2 x i1> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i1> [[TMP6]], ; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP3]], <2 x i1> [[TMP8]], <2 x i1> zeroinitializer -; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP3]], <2 x i1> [[TMP6]], <2 x i1> zeroinitializer +; CHECK-NEXT: [[TMP7:%.*]] = xor <2 x i1> [[TMP3]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP9]], <2 x i16> [[WIDE_LOAD]], <2 x i16> zeroinitializer ; CHECK-NEXT: [[PREDPHI1:%.*]] = select <2 x i1> [[TMP10]], <2 x i16> , <2 x i16> [[PREDPHI]] ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP2]] @@ -306,10 +306,10 @@ define void @single_incoming_needs_predication(i64 %a, i64 %b) { ; CHECK: pred.load.continue2: ; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x i16> [ [[TMP8]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP13]], [[PRED_LOAD_IF1]] ] ; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt <2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i1> [[TMP2]], +; CHECK-NEXT: [[TMP19:%.*]] = select <2 x i1> [[TMP2]], <2 x i1> [[TMP15]], <2 x i1> zeroinitializer ; CHECK-NEXT: [[TMP17:%.*]] = xor <2 x i1> [[TMP15]], ; CHECK-NEXT: [[TMP18:%.*]] = select <2 x i1> [[TMP2]], <2 x i1> [[TMP17]], <2 x i1> zeroinitializer -; CHECK-NEXT: [[TMP19:%.*]] = select <2 x i1> [[TMP2]], <2 x i1> [[TMP15]], <2 x i1> zeroinitializer +; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i1> [[TMP2]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP18]], <2 x i16> [[TMP14]], <2 x i16> zeroinitializer ; CHECK-NEXT: [[PREDPHI3:%.*]] = select <2 x i1> [[TMP19]], <2 x i16> , <2 x i16> [[PREDPHI]] ; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP1]] diff --git a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll index 4039d7c50d5e..c21b4d45e9a0 100644 --- a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll +++ b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll @@ -99,12 +99,12 @@ define void @blend_chain_iv(i1 %c) { ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , %vector.ph ], [ [[VEC_IND_NEXT:%.*]], %vector.body ] +; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[MASK1]], <4 x i1> [[MASK1]], <4 x i1> zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i1> [[MASK1]], ; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[MASK1]], <4 x i1> [[TMP4]], <4 x i1> zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[MASK1]], <4 x i1> [[MASK1]], <4 x i1> zeroinitializer +; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i1> [[TMP6]], [[TMP5]] ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[VEC_IND]], <4 x i64> undef ; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[MASK1]], -; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i1> [[TMP6]], [[TMP5]] ; CHECK-NEXT: [[PREDPHI1:%.*]] = select <4 x i1> [[TMP8]], <4 x i64> [[PREDPHI]], <4 x i64> undef ; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i64> [[PREDPHI1]], i32 0 ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP9]] diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll index 79ed71a2685f..89178953010f 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -431,8 +431,8 @@ define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !db ; CHECK-NEXT: WIDEN ir<%lsd> = load vp<[[VEC_PTR]]> ; CHECK-NEXT: WIDEN ir<%psd> = add nuw nsw ir<%lsd>, ir<23> ; CHECK-NEXT: WIDEN ir<%cmp1> = icmp slt ir<%lsd>, ir<100> -; CHECK-NEXT: WIDEN ir<%cmp2> = icmp sge ir<%lsd>, ir<200> ; CHECK-NEXT: EMIT vp<[[NOT1:%.+]]> = not ir<%cmp1>, !dbg /tmp/s.c:5:3 +; CHECK-NEXT: WIDEN ir<%cmp2> = icmp sge ir<%lsd>, ir<200> ; CHECK-NEXT: EMIT vp<[[SEL1:%.+]]> = select vp<[[NOT1]]>, ir<%cmp2>, ir, !dbg /tmp/s.c:5:21 ; CHECK-NEXT: EMIT vp<[[OR1:%.+]]> = or vp<[[SEL1]]>, ir<%cmp1> ; CHECK-NEXT: Successor(s): pred.sdiv diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll index 229d5b139d97..9b9c3e704852 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll @@ -363,8 +363,8 @@ define void @pred_cfg1(i32 %k, i32 %j) { ; CHECK-NEXT: then.0.0: ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.1> ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]>, vp<[[NOT]]>, ir -; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: EMIT vp<[[OR:%.+]]> = or vp<[[MASK2]]>, vp<[[MASK3]]> +; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: ; CHECK-NEXT: pred.store: { @@ -464,8 +464,8 @@ define void @pred_cfg2(i32 %k, i32 %j) { ; CHECK-NEXT: then.0.0: ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.0> ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]>, vp<[[NOT]]>, ir -; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: EMIT vp<[[OR:%.+]]> = or vp<[[MASK2]]>, vp<[[MASK3]]> +; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: EMIT vp<[[MASK4:%.+]]> = select vp<[[OR]]>, ir<%c.1>, ir ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: @@ -572,8 +572,8 @@ define void @pred_cfg3(i32 %k, i32 %j) { ; CHECK-NEXT: then.0.0: ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.0> ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]>, vp<[[NOT]]>, ir -; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: EMIT vp<[[MASK4:%.+]]> = or vp<[[MASK2]]>, vp<[[MASK3]]> +; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: EMIT vp<[[MASK5:%.+]]> = select vp<[[MASK4]]>, ir<%c.0>, ir ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: @@ -683,8 +683,8 @@ define void @merge_3_replicate_region(i32 %k, i32 %j) { ; CHECK-EMPTY: ; CHECK-NEXT: loop.3: ; CHECK-NEXT: WIDEN ir<%c.0> = icmp ult ir<%iv>, ir<%j> -; CHECK-NEXT: WIDEN ir<%mul> = mul vp<[[PRED1]]>, vp<[[PRED2]]> ; CHECK-NEXT: EMIT vp<[[MASK2:%.+]]> = select vp<[[MASK]]>, ir<%c.0>, ir +; CHECK-NEXT: WIDEN ir<%mul> = mul vp<[[PRED1]]>, vp<[[PRED2]]> ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: ; CHECK-NEXT: pred.store: { -- GitLab From c7d404ea728f1f74d6bacd3dec3ebfa28ac6a0a5 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Tue, 9 Jan 2024 14:52:05 +0400 Subject: [PATCH 179/652] [clang] Update cxx_dr_status.html (#77372) This patch updates `cxx_dr_status.html` to bring it in sync with Core Issues List Revision 113. --- clang/test/CXX/drs/dr24xx.cpp | 2 +- clang/test/CXX/drs/dr25xx.cpp | 4 +- clang/test/CXX/drs/dr26xx.cpp | 4 +- clang/test/CXX/drs/dr27xx.cpp | 4 +- clang/www/cxx_dr_status.html | 724 +++++++++++++++++++++++++--------- 5 files changed, 552 insertions(+), 186 deletions(-) diff --git a/clang/test/CXX/drs/dr24xx.cpp b/clang/test/CXX/drs/dr24xx.cpp index b34ceb420788..66e9cf5a677f 100644 --- a/clang/test/CXX/drs/dr24xx.cpp +++ b/clang/test/CXX/drs/dr24xx.cpp @@ -45,7 +45,7 @@ void fallthrough(int n) { #endif } -namespace dr2450 { // dr2450: 18 drafting +namespace dr2450 { // dr2450: 18 review #if __cplusplus >= 202302L struct S {int a;}; template diff --git a/clang/test/CXX/drs/dr25xx.cpp b/clang/test/CXX/drs/dr25xx.cpp index 8c34b03c22d5..32bbfc63d0df 100644 --- a/clang/test/CXX/drs/dr25xx.cpp +++ b/clang/test/CXX/drs/dr25xx.cpp @@ -83,7 +83,7 @@ using ::dr2521::operator""_div; #if __cplusplus >= 202302L -namespace dr2553 { // dr2553: 18 +namespace dr2553 { // dr2553: 18 review struct B { virtual void f(this B&); // since-cxx23-error@-1 {{an explicit object parameter cannot appear in a virtual function}} @@ -143,7 +143,7 @@ void foo() { #endif -namespace dr2565 { // dr2565: 16 +namespace dr2565 { // dr2565: 16 open #if __cplusplus >= 202002L template concept C = requires (typename T::type x) { diff --git a/clang/test/CXX/drs/dr26xx.cpp b/clang/test/CXX/drs/dr26xx.cpp index 8a22dbeb98a3..47eeddcc5bf2 100644 --- a/clang/test/CXX/drs/dr26xx.cpp +++ b/clang/test/CXX/drs/dr26xx.cpp @@ -24,7 +24,7 @@ using enum E; #endif } -namespace dr2628 { // dr2628: no open +namespace dr2628 { // dr2628: no // this was reverted for the 16.x release // due to regressions, see the issue for more details: // https://github.com/llvm/llvm-project/issues/60777 @@ -197,7 +197,7 @@ J j = { "ghi" }; #endif } -namespace dr2672 { // dr2672: 18 open +namespace dr2672 { // dr2672: 18 #if __cplusplus >= 202002L template void f(T) requires requires { []() { T::invalid; } (); }; diff --git a/clang/test/CXX/drs/dr27xx.cpp b/clang/test/CXX/drs/dr27xx.cpp index 4f7d0d6b44a8..dd3fd5a20163 100644 --- a/clang/test/CXX/drs/dr27xx.cpp +++ b/clang/test/CXX/drs/dr27xx.cpp @@ -10,7 +10,7 @@ // expected-no-diagnostics #endif -namespace dr2789 { // dr2789: 18 open +namespace dr2789 { // dr2789: 18 #if __cplusplus >= 202302L template struct Base { @@ -42,7 +42,7 @@ void test() { #endif } -namespace dr2798 { // dr2798: 17 drafting +namespace dr2798 { // dr2798: 17 #if __cpp_static_assert >= 202306 struct string { constexpr string() { diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index d09cf616899a..22eb7ac63c7e 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -1055,7 +1055,7 @@ 170 - DR + DRWP Pointer-to-member conversions Unknown @@ -1426,11 +1426,11 @@ accessible? Visibility of names after using-directives Yes - + 232 - drafting + NAD Is indirection through a null pointer undefined behavior? - Not resolved + Unknown 233 @@ -2661,7 +2661,7 @@ of class templates 437 CD1 Is type of class allowed in member function exception specification? - Superseded by 1308 + Superseded by 1308 438 @@ -2753,11 +2753,11 @@ of class templates Wording nit on description of this Yes - + 453 - drafting + tentatively ready References may only bind to “valid” objects - Not resolved + Unknown 454 @@ -2789,11 +2789,11 @@ of class templates Hiding of member template parameters by other members Clang 11 - + 459 - open + NAD Hiding of template parameters by base class members - Not resolved + Unknown 460 @@ -5967,7 +5967,7 @@ and POD class 1027 - drafting + review Type consistency and reallocation of scalar types Not resolved @@ -6033,7 +6033,7 @@ and POD class 1038 - tentatively ready + DR Overload resolution of &x.static_func Unknown @@ -6339,7 +6339,7 @@ and POD class 1089 - drafting + open Template parameters in member selections Not resolved @@ -7923,7 +7923,7 @@ and POD class 1353 - DR + DRWP Array and variant members and deleted special member functions Unknown @@ -9657,7 +9657,7 @@ and POD class 1642 - DR + DRWP Missing requirements for prvalue operands Unknown @@ -9993,7 +9993,7 @@ and POD class 1698 - ready + DR Files ending in \ Unknown @@ -11527,11 +11527,11 @@ and POD class Data races and common initial sequence Not resolved - + 1954 - open + tentatively ready typeid null dereference check in subexpressions - Not resolved + Unknown 1955 @@ -11643,7 +11643,7 @@ and POD class 1973 - DR + DRWP Which parameter-declaration-clause in a lambda-expression? Unknown @@ -11911,11 +11911,11 @@ and POD class Flowing off end is not equivalent to no-expression return Unknown - + 2018 - drafting + dup Qualification conversion vs reference binding - Not resolved + Unknown 2019 @@ -12127,11 +12127,11 @@ and POD class auto in non-generic lambdas Unknown - + 2054 - review + DR Missing description of class SFINAE - Not resolved + Unknown 2055 @@ -12417,7 +12417,7 @@ and POD class 2102 - tentatively ready + DR Constructor checking in new-expression Unknown @@ -13315,11 +13315,11 @@ and POD class Unreachable enumeration list-initialization Unknown - + 2252 - review + DR Enumeration list-initialization from the same type - Not resolved + Unknown 2253 @@ -14505,7 +14505,7 @@ and POD class 2450 - drafting + review braced-init-list as a template-argument Clang 18 @@ -14715,7 +14715,7 @@ and POD class 2485 - DR + DRWP Bit-fields in integral promotions Unknown @@ -14827,11 +14827,11 @@ and POD class Unclear relationship among name, qualified name, and unqualified name Not resolved - + 2504 - review + DR Inheriting constructors from virtual base classes - Not resolved + Unknown 2505 @@ -14889,7 +14889,7 @@ and POD class 2514 - review + open Modifying const subobjects Not resolved @@ -14919,7 +14919,7 @@ and POD class 2519 - DR + DRWP Object representation of a bit-field Unknown @@ -14989,11 +14989,11 @@ and POD class Multiple definitions of enumerators Unknown - + 2531 - review + DR Static data members redeclared as constexpr - Not resolved + Unknown 2532 @@ -15057,7 +15057,7 @@ and POD class 2542 - DR + DRWP Is a closure type a structural type? Unknown @@ -15079,23 +15079,23 @@ and POD class Transparently replacing objects in constant expressions Not resolved - + 2546 - review + tentatively ready Defaulted secondary comparison operators defined as deleted - Not resolved + Unknown - + 2547 - review + tentatively ready Defaulted comparison operator function for non-classes - Not resolved + Unknown - + 2548 - review + NAD Array prvalues and additive operators - Not resolved + Unknown 2549 @@ -15105,7 +15105,7 @@ and POD class 2550 - DR + DRWP Type "reference to cv void" outside of a declarator Unknown @@ -15117,13 +15117,13 @@ and POD class 2552 - DR + DRWP Constant evaluation of non-defining variable declarations Unknown - + 2553 - ready + review Restrictions on explicit object member functions Clang 18 @@ -15141,7 +15141,7 @@ and POD class 2556 - tentatively ready + DR Unusable promise::return_void Unknown @@ -15163,11 +15163,11 @@ and POD class Defaulted consteval functions Not resolved - + 2560 - open + tentatively ready Parameter type determination in a requirement-parameter-list - Not resolved + Unknown 2561 @@ -15193,9 +15193,9 @@ and POD class Conversion to function pointer with an explicit object parameter Not resolved - + 2565 - tentatively ready + open Invalid types in the parameter-declaration-clause of a requires-expression Clang 16 @@ -15211,11 +15211,11 @@ and POD class Operator lookup ambiguity Unknown - + 2568 - review + tentatively ready Access checking during synthesis of defaulted comparison operator - Not resolved + Unknown 2569 @@ -15225,7 +15225,7 @@ and POD class 2570 - tentatively ready + DR Clarify constexpr for defaulted functions Unknown @@ -15241,17 +15241,17 @@ and POD class Address of overloaded function with no target Not resolved - + 2573 - open + DRWP Undefined behavior when splicing results in a universal-character-name - Not resolved + Unknown - + 2574 - open + DRWP Undefined behavior when lexing unmatched quotes - Not resolved + Unknown 2575 @@ -15351,7 +15351,7 @@ and POD class 2591 - tentatively ready + DR Implicit change of active union member for anonymous union in union Unknown @@ -15375,7 +15375,7 @@ and POD class 2595 - tentatively ready + DR "More constrained" for eligible special member functions Unknown @@ -15405,7 +15405,7 @@ and POD class 2600 - tentatively ready + DR Type dependency of placeholder types Unknown @@ -15571,9 +15571,9 @@ and POD class Bit-fields and narrowing conversions Unknown - + 2628 - open + DR Implicit deduction guides should propagate constraints No @@ -15597,7 +15597,7 @@ and POD class 2632 - open + review 'user-declared' is not defined Not resolved @@ -15607,11 +15607,11 @@ and POD class typeid of constexpr-unknown dynamic type Not resolved - + 2634 - open + tentatively ready Avoid circularity in specification of scope for friend class declarations - Not resolved + Unknown 2635 @@ -15625,17 +15625,17 @@ and POD class Update Annex E based on Unicode 15.0 UAX #31 N/A - + 2637 - open + tentatively ready Injected-class-name as a simple-template-id - Not resolved + Unknown - + 2638 - open + tentatively ready Improve the example for initializing by initializer list - Not resolved + Unknown 2639 @@ -15733,23 +15733,23 @@ and POD class Un-deprecation of compound volatile assignments Clang 16 - + 2655 - open + NAD Instantiation of default arguments in lambda-expressions - Not resolved + Unknown 2656 - open + drafting Converting consteval lambda to function pointer in non-immediate context Not resolved - + 2657 - open + tentatively ready Cv-qualification adjustment when binding reference to temporary - Not resolved + Unknown 2658 @@ -15783,7 +15783,7 @@ and POD class 2663 - DR + DRWP Example for member redeclarations with using-declarations Unknown @@ -15811,11 +15811,11 @@ and POD class Named module imports do not import macros Unknown - + 2668 - open + tentatively ready co_await in a lambda-expression - Not resolved + Unknown 2669 @@ -15835,9 +15835,9 @@ and POD class friend named by a template-id Not resolved - + 2672 - open + DR Lambda body SFINAE is still required, contrary to intent and note Clang 18 @@ -15903,7 +15903,7 @@ and POD class 2683 - DR + DRWP Default arguments for member functions of templated nested classes Unknown @@ -15937,11 +15937,11 @@ and POD class Calling explicit object member functions Not resolved - + 2689 - review + tentatively ready Are cv-qualified std::nullptr_t fundamental types? - Not resolved + Unknown 2690 @@ -15987,19 +15987,19 @@ and POD class 2697 - DR + DRWP Deduction guides using abbreviated function syntax Unknown 2698 - DR + DRWP Using extended integer types with z suffix Unknown 2699 - DR + DRWP Inconsistency of throw-expression specification Unknown @@ -16045,15 +16045,15 @@ and POD class Repeated structured binding declarations Not resolved - + 2707 - open + tentatively ready Deduction guides cannot have a trailing requires-clause - Not resolved + Unknown 2708 - DR + DRWP Parenthesized initialization of arrays Unknown @@ -16065,25 +16065,25 @@ and POD class 2710 - DR + DRWP Loops in constant expressions Unknown 2711 - DR + DRWP Source for copy-initializing the exception object Unknown 2712 - DR + DRWP Simplify restrictions on built-in assignment operator candidates Unknown 2713 - DR + DRWP Initialization of reference-to-aggregate from designated initializer list Unknown @@ -16095,67 +16095,67 @@ and POD class 2715 - DR + DRWP "calling function" for parameter initialization may not exist Unknown 2716 - DR + DRWP Rule about self-or-base conversion is normatively redundant Unknown 2717 - DR + DRWP Pack expansion for alignment-specifier Unknown 2718 - DR + DRWP Type completeness for derived-to-base conversions Unknown 2719 - DR + DRWP Creating objects in misaligned storage Unknown 2720 - DR + DRWP Template validity rules for templated entities and alias templates Unknown 2721 - DR + DRWP When exactly is storage reused? Unknown 2722 - DR + DRWP Temporary materialization conversion for noexcept operator Unknown 2723 - DR + DRWP Range of representable values for floating-point types Unknown 2724 - DR + DRWP Clarify rounding for arithmetic right shift Unknown 2725 - tentatively ready + DR Overload resolution for non-call of class member access Unknown @@ -16179,7 +16179,7 @@ and POD class 2729 - DR + DRWP Meaning of new-type-id Unknown @@ -16197,15 +16197,15 @@ and POD class 2732 - DR + DRWP Can importable headers react to preprocessor state from point of import? Unknown - + 2733 - review + DR Applying [[maybe_unused]] to a label - Not resolved + Unknown 2734 @@ -16287,33 +16287,33 @@ and POD class 2747 - ready + DR Cannot depend on an already-deleted splice Unknown - + 2748 - open + tentatively ready Accessing static data members via null pointer - Not resolved + Unknown 2749 - tentatively ready + DR Treatment of "pointer to void" for relational comparisons Unknown 2750 - DR + DRWP construct_at without constructor call Unknown - + 2751 - open + NAD Order of destruction for parameters for operator functions - Not resolved + Unknown 2752 @@ -16323,75 +16323,75 @@ and POD class 2753 - tentatively ready + DR Storage reuse for string literal objects and backing arrays Unknown 2754 - ready + DR Using *this in explicit object member functions that are coroutines Unknown 2755 - ready + DR Incorrect wording applied by P2738R1 Unknown - + 2756 - tentatively ready + review Completion of initialization by delegating constructor - Unknown + Not resolved 2757 - open + review Deleting or deallocating storage of an object during its construction Not resolved - + 2758 - open + DR What is "access and ambiguity control"? - Not resolved + Unknown - + 2759 - open + DR [[no_unique_address] and common initial sequence - Not resolved + Unknown - + 2760 - open + DR Defaulted constructor that is an immediate function - Not resolved + Unknown - + 2761 - open + DR Implicitly invoking the deleted destructor of an anonymous union member - Not resolved + Unknown - + 2762 - open + DR Type of implicit object parameter - Not resolved + Unknown - + 2763 - review + DR Ignorability of [[noreturn]] during constant evaluation - Not resolved + Unknown - + 2764 - open + DR Use of placeholders affecting name mangling - Not resolved + Unknown 2765 @@ -16411,11 +16411,11 @@ and POD class Non-defining declarations of anonymous unions Not resolved - + 2768 - open - Assignment to scalar with a braced-init-list - Not resolved + DR + Assignment to enumeration variable with a braced-init-list + Unknown 2769 @@ -16435,11 +16435,11 @@ and POD class Transformation for unqualified-ids in address operator Not resolved - + 2772 - open + DR Missing Annex C entry for linkage effects of linkage-specification - Not resolved + Unknown 2773 @@ -16453,11 +16453,11 @@ and POD class Value-dependence of requires-expressions Not resolved - + 2775 - open + tentatively ready Unclear argument type for copy of exception object - Not resolved + Unknown 2776 @@ -16483,10 +16483,376 @@ and POD class Restrictions on the ordinary literal encoding Not resolved - + 2780 - open + DR reinterpret_cast to reference to function types + Unknown + + + 2781 + open + Unclear recursion in the one-definition rule + Not resolved + + + 2782 + open + Treatment of closure types in the one-definition rule + Not resolved + + + 2783 + DR + Handling of deduction guides in global-module-fragment + Unknown + + + 2784 + open + Unclear definition of member-designator for offsetof + Not resolved + + + 2785 + DR + Type-dependence of requires-expression + Unknown + + + 2786 + open + Comparing pointers to complete objects + Not resolved + + + 2787 + open + Kind of explicit object copy/move assignment function + Not resolved + + + 2788 + open + Correspondence and redeclarations + Not resolved + + + 2789 + DR + Overload resolution with implicit and explicit object member functions + Clang 18 + + + 2790 + open + Aggregate initialization and user-defined conversion sequence + Not resolved + + + 2791 + DR + Unclear phrasing about "returning to the caller" + Unknown + + + 2792 + DR + Clean up specification of noexcept operator + Unknown + + + 2793 + DR + Block-scope declaration conflicting with parameter name + Unknown + + + 2794 + open + Uniqueness of lambdas in alias templates + Not resolved + + + 2795 + DR + Overlapping empty subobjects with different cv-qualification + Unknown + + + 2796 + DR + Function pointer conversions for relational operators + Unknown + + + 2797 + open + Meaning of "corresponds" for rewritten operator candidates + Not resolved + + + 2798 + DR + Manifestly constant evaluation of the static_assert message + Clang 17 + + + 2799 + drafting + Inheriting default constructors + Not resolved + + + 2800 + review + Instantiating constexpr variables for potential constant evaluation + Not resolved + + + 2801 + DR + Reference binding with reference-related types + Unknown + + + 2802 + open + Constrained auto and redeclaration with non-abbreviated syntax + Not resolved + + + 2803 + tentatively ready + Overload resolution for reference binding of similar types + Unknown + + + 2804 + open + Lookup for determining rewrite targets + Not resolved + + + 2805 + open + Underspecified selection of deallocation function + Not resolved + + + 2806 + DR + Make a type-requirement a type-only context + Unknown + + + 2807 + DR + Destructors declared consteval + Unknown + + + 2808 + review + Explicit specialization of defaulted special member function + Not resolved + + + 2809 + tentatively ready + An implicit definition does not redeclare a function + Unknown + + + 2810 + tentatively ready + Requiring the absence of diagnostics for templates + Unknown + + + 2811 + tentatively ready + Clarify "use" of main + Unknown + + + 2812 + open + Allocation with explicit alignment + Not resolved + + + 2813 + review + Class member access with prvalues + Not resolved + + + 2814 + review + Alignment requirement of incomplete class type + Not resolved + + + 2815 + open + Overload resolution for references/pointers to noexcept functions + Not resolved + + + 2816 + review + Unclear phrasing "may assume ... eventually" + Not resolved + + + 2817 + open + sizeof(abstract class) is underspecified + Not resolved + + + 2818 + review + Use of predefined reserved identifiers + Not resolved + + + 2819 + review + Cast from null pointer value in a constant expression + Not resolved + + + 2820 + open + Value-initialization and default constructors + Not resolved + + + 2821 + open + Lifetime, zero-initialization, and dynamic initialization + Not resolved + + + 2822 + tentatively ready + Side-effect-free pointer zap + Unknown + + + 2823 + DR + Implicit undefined behavior when dereferencing pointers + Unknown + + + 2824 + tentatively ready + Copy-initialization of arrays + Unknown + + + 2825 + tentatively ready + Range-based for statement using a braced-init-list + Unknown + + + 2826 + tentatively ready + Missing definition of "temporary expression" + Unknown + + + 2827 + review + Representation of unsigned integral types + Not resolved + + + 2828 + review + Ambiguous interpretation of C-style cast + Not resolved + + + 2829 + open + Redundant case in restricting user-defined conversion sequences + Not resolved + + + 2830 + open + Top-level cv-qualification should be ignored for list-initialization + Not resolved + + + 2831 + open + Non-templated function definitions and requires-clauses + Not resolved + + + 2832 + open + Invented temporary variables and temporary objects + Not resolved + + + 2833 + review + Evaluation of odr-use + Not resolved + + + 2834 + open + Partial ordering and explicit object parameters + Not resolved + + + 2835 + open + Name-independent declarations + Not resolved + + + 2836 + open + Conversion rank of long double and extended floating-point types + Not resolved + + + 2837 + open + Instantiating and inheriting by-value copy constructors + Not resolved + + + 2838 + open + Declaration conflicts in lambda-expressions + Not resolved + + + 2839 + open + Explicit destruction of base classes + Not resolved + + + 2840 + open + Missing requirements for fundamental alignments + Not resolved + + + 2841 + open + When do const objects start being const? Not resolved -- GitLab From 9be29ad48cdd948ad54f305f6ede391b83198eb9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 9 Jan 2024 17:55:29 +0700 Subject: [PATCH 180/652] AMDGPU: Regenerate test checks Fix test failures after auto-merge of f9fec402896a90f3b09cea359c330f65a0908649 --- llvm/test/CodeGen/AMDGPU/bf16.ll | 5010 +++++++++++++++--------------- 1 file changed, 2484 insertions(+), 2526 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll index 4e87b4e82ba3..4a696879ad7b 100644 --- a/llvm/test/CodeGen/AMDGPU/bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/bf16.ll @@ -6025,138 +6025,138 @@ define <32 x float> @global_extload_v32bf16_to_v32f32(ptr addrspace(1) %ptr) { ; GFX9-LABEL: global_extload_v32bf16_to_v32f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[16:19], v[0:1], off -; GFX9-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:16 -; GFX9-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:32 -; GFX9-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:48 +; GFX9-NEXT: global_load_dwordx4 v[4:7], v[0:1], off +; GFX9-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16 +; GFX9-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:32 +; GFX9-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:48 ; GFX9-NEXT: s_waitcnt vmcnt(3) -; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v17 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v5 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v6 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v12 +; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v13 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v13 +; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v14 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v21 +; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v22 +; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v23 +; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v32 -; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v33 -; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v34 -; GFX9-NEXT: v_and_b32_e32 v31, 0xffff0000, v35 -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v32 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v33 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v34 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v35 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v28 +; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v29 +; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v30 +; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v31 +; GFX9-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: global_extload_v32bf16_to_v32f32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_clause 0x3 -; GFX10-NEXT: global_load_dwordx4 v[32:35], v[0:1], off -; GFX10-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:16 -; GFX10-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:32 -; GFX10-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:48 +; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off +; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16 +; GFX10-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:32 +; GFX10-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:48 ; GFX10-NEXT: s_waitcnt vmcnt(3) -; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v33 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v34 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v35 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v36 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v37 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v38 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v12 +; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v48 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v50 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v51 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v21 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v22 +; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v23 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v52 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v53 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v54 -; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v55 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v33 -; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v34 -; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v35 -; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v36 -; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v37 -; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v38 -; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v39 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v48 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v49 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v50 -; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v51 -; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v52 -; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v53 -; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v54 -; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v55 +; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v28 +; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v29 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v30 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: global_extload_v32bf16_to_v32f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_clause 0x3 -; GFX11-NEXT: global_load_b128 v[32:35], v[0:1], off -; GFX11-NEXT: global_load_b128 v[36:39], v[0:1], off offset:16 -; GFX11-NEXT: global_load_b128 v[48:51], v[0:1], off offset:32 -; GFX11-NEXT: global_load_b128 v[52:55], v[0:1], off offset:48 +; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off +; GFX11-NEXT: global_load_b128 v[12:15], v[0:1], off offset:16 +; GFX11-NEXT: global_load_b128 v[20:23], v[0:1], off offset:32 +; GFX11-NEXT: global_load_b128 v[28:31], v[0:1], off offset:48 ; GFX11-NEXT: s_waitcnt vmcnt(3) -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 -; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v33 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v34 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v35 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v5 +; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6 +; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v36 -; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v37 -; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v38 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v39 +; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v12 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v13 +; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v13 +; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v14 +; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v15 +; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v48 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 -; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v50 -; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v51 +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v20 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 +; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v21 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v22 +; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v23 +; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v52 -; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v53 -; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v54 -; GFX11-NEXT: v_and_b32_e32 v31, 0xffff0000, v55 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v32 -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v33 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v34 -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v35 -; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v36 -; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v37 -; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v38 -; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v39 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v48 -; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v49 -; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v50 -; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v51 -; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v52 -; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v53 -; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v54 -; GFX11-NEXT: v_lshlrev_b32_e32 v30, 16, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v28 +; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v28 +; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v29 +; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v29 +; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v30 +; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v30 +; GFX11-NEXT: v_lshlrev_b32_e32 v30, 16, v31 +; GFX11-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; GFX11-NEXT: s_setpc_b64 s[30:31] %load = load <32 x bfloat>, ptr addrspace(1) %ptr %fpext = fpext <32 x bfloat> %load to <32 x float> @@ -9833,483 +9833,480 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_fadd_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX8-NEXT: v_add_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX8-NEXT: v_add_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX8-NEXT: v_add_f32_e32 v30, v14, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_add_f32_e32 v14, v32, v14 +; GFX8-NEXT: v_add_f32_e32 v13, v13, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_add_f32_e32 v29, v32, v29 +; GFX8-NEXT: v_add_f32_e32 v12, v12, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_add_f32_e32 v28, v32, v28 +; GFX8-NEXT: v_add_f32_e32 v11, v11, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_add_f32_e32 v27, v32, v27 +; GFX8-NEXT: v_add_f32_e32 v10, v10, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_add_f32_e32 v26, v32, v26 +; GFX8-NEXT: v_add_f32_e32 v9, v9, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX8-NEXT: v_add_f32_e32 v8, v8, v24 +; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX8-NEXT: v_add_f32_e32 v25, v32, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX8-NEXT: v_add_f32_e32 v32, v32, v33 +; GFX8-NEXT: v_add_f32_e32 v15, v15, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_add_f32_e32 v24, v33, v24 +; GFX8-NEXT: v_add_f32_e32 v7, v7, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_add_f32_e32 v23, v33, v23 +; GFX8-NEXT: v_add_f32_e32 v6, v6, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_add_f32_e32 v22, v33, v22 +; GFX8-NEXT: v_add_f32_e32 v5, v5, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_add_f32_e32 v21, v33, v21 +; GFX8-NEXT: v_add_f32_e32 v4, v4, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_add_f32_e32 v20, v33, v20 +; GFX8-NEXT: v_add_f32_e32 v3, v3, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_add_f32_e32 v19, v33, v19 +; GFX8-NEXT: v_add_f32_e32 v2, v2, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_add_f32_e32 v18, v33, v18 ; GFX8-NEXT: v_add_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_add_f32_e32 v16, v31, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX8-NEXT: v_add_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_add_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX8-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_add_f32_e32 v2, v2, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX8-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_add_f32_e32 v3, v3, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX8-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_add_f32_e32 v4, v4, v17 -; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_add_f32_e32 v5, v5, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_add_f32_e32 v6, v6, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_add_f32_e32 v7, v7, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_add_f32_e32 v8, v8, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_add_f32_e32 v9, v9, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_add_f32_e32 v10, v10, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_add_f32_e32 v11, v11, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_add_f32_e32 v12, v12, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_add_f32_e32 v13, v13, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_add_f32_e32 v14, v14, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_add_f32_e32 v15, v15, v17 -; GFX8-NEXT: v_add_f32_e32 v16, v18, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 +; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 +; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fadd_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX9-NEXT: v_add_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_add_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_add_f32_e32 v14, v14, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_add_f32_e32 v30, v32, v30 +; GFX9-NEXT: v_add_f32_e32 v13, v13, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_add_f32_e32 v29, v32, v29 +; GFX9-NEXT: v_add_f32_e32 v12, v12, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_add_f32_e32 v28, v32, v28 +; GFX9-NEXT: v_add_f32_e32 v11, v11, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_add_f32_e32 v27, v32, v27 +; GFX9-NEXT: v_add_f32_e32 v10, v10, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_add_f32_e32 v26, v32, v26 +; GFX9-NEXT: v_add_f32_e32 v9, v9, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_add_f32_e32 v8, v8, v24 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX9-NEXT: v_add_f32_e32 v25, v32, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 +; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 +; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 +; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 +; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 +; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 +; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_add_f32_e32 v32, v32, v33 +; GFX9-NEXT: v_add_f32_e32 v15, v15, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_add_f32_e32 v24, v33, v24 +; GFX9-NEXT: v_add_f32_e32 v7, v7, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_add_f32_e32 v23, v33, v23 +; GFX9-NEXT: v_add_f32_e32 v6, v6, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_add_f32_e32 v22, v33, v22 +; GFX9-NEXT: v_add_f32_e32 v5, v5, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_add_f32_e32 v21, v33, v21 +; GFX9-NEXT: v_add_f32_e32 v4, v4, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_add_f32_e32 v20, v33, v20 +; GFX9-NEXT: v_add_f32_e32 v3, v3, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_add_f32_e32 v19, v33, v19 +; GFX9-NEXT: v_add_f32_e32 v2, v2, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_add_f32_e32 v16, v31, v16 +; GFX9-NEXT: v_add_f32_e32 v18, v33, v18 ; GFX9-NEXT: v_add_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_add_f32_e32 v2, v2, v17 -; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_add_f32_e32 v3, v3, v17 -; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_add_f32_e32 v4, v4, v17 -; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_add_f32_e32 v5, v5, v17 -; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_add_f32_e32 v6, v6, v17 -; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_add_f32_e32 v7, v7, v17 -; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_add_f32_e32 v8, v8, v17 -; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_add_f32_e32 v9, v9, v17 -; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_add_f32_e32 v10, v10, v17 -; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_add_f32_e32 v11, v11, v17 -; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_add_f32_e32 v12, v12, v17 -; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_add_f32_e32 v13, v13, v17 -; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX9-NEXT: v_add_f32_e32 v14, v14, v17 -; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 -; GFX9-NEXT: v_add_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX9-NEXT: v_add_f32_e32 v15, v15, v17 -; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_add_f32_e32 v17, v33, v17 +; GFX9-NEXT: v_add_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 +; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 +; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 +; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 +; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 +; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 +; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 +; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_fadd_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_add_f32_e32 v39, v48, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 +; GFX10-NEXT: v_add_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_add_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_add_f32_e32 v21, v53, v52 -; GFX10-NEXT: v_add_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_add_f32_e32 v22, v55, v54 -; GFX10-NEXT: v_add_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_add_f32_e32 v49, v50, v49 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 +; GFX10-NEXT: v_add_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 ; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX10-NEXT: v_add_f32_e32 v32, v33, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX10-NEXT: v_add_f32_e32 v33, v34, v33 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 +; GFX10-NEXT: v_add_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_add_f32_e32 v35, v36, v35 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 +; GFX10-NEXT: v_add_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_add_f32_e32 v37, v38, v37 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 +; GFX10-NEXT: v_add_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX10-NEXT: v_add_f32_e32 v34, v35, v34 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 -; GFX10-NEXT: v_add_f32_e32 v36, v37, v36 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_add_f32_e32 v51, v52, v51 +; GFX10-NEXT: v_add_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_add_f32_e32 v25, v54, v53 +; GFX10-NEXT: v_add_f32_e32 v8, v8, v24 +; GFX10-NEXT: v_add_f32_e32 v24, v64, v55 +; GFX10-NEXT: v_add_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_add_f32_e32 v23, v66, v65 +; GFX10-NEXT: v_add_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_add_f32_e32 v22, v68, v67 +; GFX10-NEXT: v_add_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_add_f32_e32 v21, v30, v34 +; GFX10-NEXT: v_add_f32_e32 v29, v29, v36 +; GFX10-NEXT: v_add_f32_e32 v28, v28, v38 +; GFX10-NEXT: v_add_f32_e32 v27, v27, v48 +; GFX10-NEXT: v_add_f32_e32 v26, v26, v50 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; GFX10-NEXT: v_add_f32_e32 v38, v39, v38 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GFX10-NEXT: v_add_f32_e32 v3, v3, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 -; GFX10-NEXT: v_add_f32_e32 v48, v49, v48 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX10-NEXT: v_add_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX10-NEXT: v_add_f32_e32 v50, v51, v50 -; GFX10-NEXT: v_add_f32_e32 v23, v65, v64 -; GFX10-NEXT: v_add_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_add_f32_e32 v24, v67, v66 -; GFX10-NEXT: v_add_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_add_f32_e32 v25, v33, v68 -; GFX10-NEXT: v_add_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_add_f32_e32 v16, v35, v16 -; GFX10-NEXT: v_add_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_add_f32_e32 v17, v37, v17 -; GFX10-NEXT: v_add_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_add_f32_e32 v18, v39, v18 -; GFX10-NEXT: v_add_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_add_f32_e32 v19, v49, v19 -; GFX10-NEXT: v_add_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 +; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 -; GFX10-NEXT: v_add_f32_e32 v20, v20, v21 -; GFX10-NEXT: v_add_f32_e32 v15, v15, v22 -; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX10-NEXT: v_add_f32_e32 v16, v32, v16 +; GFX10-NEXT: v_add_f32_e32 v15, v15, v17 +; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_fadd_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 -; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX11-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 +; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX11-NEXT: v_dual_add_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 +; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX11-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 +; GFX11-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_dual_add_f32 v2, v2, v18 :: v_dual_add_f32 v3, v3, v19 +; GFX11-NEXT: v_dual_add_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 +; GFX11-NEXT: v_dual_add_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_add_f32_e32 v6, v6, v22 +; GFX11-NEXT: v_dual_add_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_add_f32_e32 v10, v10, v26 +; GFX11-NEXT: v_add_f32_e32 v26, v52, v51 +; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX11-NEXT: v_add_f32_e32 v25, v54, v53 +; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX11-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_dual_add_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 -; GFX11-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_add_f32_e32 v4, v4, v20 -; GFX11-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_add_f32 v9, v9, v25 -; GFX11-NEXT: v_add_f32_e32 v25, v69, v68 -; GFX11-NEXT: v_dual_add_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 -; GFX11-NEXT: v_add_f32_e32 v27, v81, v80 -; GFX11-NEXT: v_add_f32_e32 v12, v12, v28 -; GFX11-NEXT: v_dual_add_f32 v28, v83, v82 :: v_dual_add_f32 v29, v85, v84 -; GFX11-NEXT: v_dual_add_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_add_f32_e32 v22, v55, v54 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_add_f32_e32 v24, v64, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX11-NEXT: v_add_f32_e32 v7, v7, v23 +; GFX11-NEXT: v_add_f32_e32 v23, v66, v65 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_dual_add_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 +; GFX11-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 +; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX11-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_add_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX11-NEXT: v_add_f32_e32 v37, v86, v85 +; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 ; GFX11-NEXT: v_add_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_add_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_add_f32_e32 v23, v65, v64 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_dual_add_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_add_f32_e32 v2, v2, v18 -; GFX11-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 -; GFX11-NEXT: v_add_f32_e32 v18, v39, v38 -; GFX11-NEXT: v_dual_add_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_add_f32_e32 v19, v49, v48 -; GFX11-NEXT: v_add_f32_e32 v17, v37, v36 -; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX11-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_add_f32_e32 v21, v53, v52 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 -; GFX11-NEXT: v_add_f32_e32 v0, v0, v16 -; GFX11-NEXT: v_add_f32_e32 v16, v35, v34 -; GFX11-NEXT: v_add_f32_e32 v32, v33, v32 -; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 -; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 -; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 -; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_add_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_add_f32_e32 v15, v15, v17 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33 +; GFX11-NEXT: v_dual_add_f32 v34, v80, v71 :: v_dual_add_f32 v35, v82, v81 +; GFX11-NEXT: v_add_f32_e32 v36, v84, v83 +; GFX11-NEXT: v_dual_add_f32 v16, v32, v16 :: v_dual_add_f32 v15, v15, v17 +; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = fadd <32 x bfloat> %a, %b @@ -12148,483 +12145,480 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_fmul_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX8-NEXT: v_mul_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX8-NEXT: v_mul_f32_e32 v30, v14, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_mul_f32_e32 v14, v32, v14 +; GFX8-NEXT: v_mul_f32_e32 v13, v13, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_mul_f32_e32 v29, v32, v29 +; GFX8-NEXT: v_mul_f32_e32 v12, v12, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_mul_f32_e32 v28, v32, v28 +; GFX8-NEXT: v_mul_f32_e32 v11, v11, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_mul_f32_e32 v27, v32, v27 +; GFX8-NEXT: v_mul_f32_e32 v10, v10, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_mul_f32_e32 v26, v32, v26 +; GFX8-NEXT: v_mul_f32_e32 v9, v9, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX8-NEXT: v_mul_f32_e32 v8, v8, v24 +; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX8-NEXT: v_mul_f32_e32 v25, v32, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX8-NEXT: v_mul_f32_e32 v32, v32, v33 +; GFX8-NEXT: v_mul_f32_e32 v15, v15, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_mul_f32_e32 v24, v33, v24 +; GFX8-NEXT: v_mul_f32_e32 v7, v7, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_mul_f32_e32 v23, v33, v23 +; GFX8-NEXT: v_mul_f32_e32 v6, v6, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_mul_f32_e32 v22, v33, v22 +; GFX8-NEXT: v_mul_f32_e32 v5, v5, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_mul_f32_e32 v21, v33, v21 +; GFX8-NEXT: v_mul_f32_e32 v4, v4, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_mul_f32_e32 v20, v33, v20 +; GFX8-NEXT: v_mul_f32_e32 v3, v3, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_mul_f32_e32 v19, v33, v19 +; GFX8-NEXT: v_mul_f32_e32 v2, v2, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_mul_f32_e32 v18, v33, v18 ; GFX8-NEXT: v_mul_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_mul_f32_e32 v16, v31, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX8-NEXT: v_mul_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_mul_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_mul_f32_e32 v2, v2, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_mul_f32_e32 v3, v3, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_mul_f32_e32 v4, v4, v17 -; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_mul_f32_e32 v5, v5, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_mul_f32_e32 v6, v6, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_mul_f32_e32 v7, v7, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_mul_f32_e32 v8, v8, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_mul_f32_e32 v9, v9, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_mul_f32_e32 v10, v10, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_mul_f32_e32 v11, v11, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_mul_f32_e32 v12, v12, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_mul_f32_e32 v13, v13, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_mul_f32_e32 v14, v14, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_mul_f32_e32 v15, v15, v17 -; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 +; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 +; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_fmul_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX9-NEXT: v_mul_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_mul_f32_e32 v14, v14, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_mul_f32_e32 v30, v32, v30 +; GFX9-NEXT: v_mul_f32_e32 v13, v13, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_mul_f32_e32 v29, v32, v29 +; GFX9-NEXT: v_mul_f32_e32 v12, v12, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_mul_f32_e32 v28, v32, v28 +; GFX9-NEXT: v_mul_f32_e32 v11, v11, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_mul_f32_e32 v27, v32, v27 +; GFX9-NEXT: v_mul_f32_e32 v10, v10, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_mul_f32_e32 v26, v32, v26 +; GFX9-NEXT: v_mul_f32_e32 v9, v9, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_mul_f32_e32 v8, v8, v24 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX9-NEXT: v_mul_f32_e32 v25, v32, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 +; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 +; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 +; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 +; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 +; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 +; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_mul_f32_e32 v32, v32, v33 +; GFX9-NEXT: v_mul_f32_e32 v15, v15, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_mul_f32_e32 v24, v33, v24 +; GFX9-NEXT: v_mul_f32_e32 v7, v7, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_mul_f32_e32 v23, v33, v23 +; GFX9-NEXT: v_mul_f32_e32 v6, v6, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_mul_f32_e32 v22, v33, v22 +; GFX9-NEXT: v_mul_f32_e32 v5, v5, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_mul_f32_e32 v21, v33, v21 +; GFX9-NEXT: v_mul_f32_e32 v4, v4, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_mul_f32_e32 v20, v33, v20 +; GFX9-NEXT: v_mul_f32_e32 v3, v3, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_mul_f32_e32 v19, v33, v19 +; GFX9-NEXT: v_mul_f32_e32 v2, v2, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_mul_f32_e32 v16, v31, v16 +; GFX9-NEXT: v_mul_f32_e32 v18, v33, v18 ; GFX9-NEXT: v_mul_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_mul_f32_e32 v2, v2, v17 -; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_mul_f32_e32 v3, v3, v17 -; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_mul_f32_e32 v4, v4, v17 -; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_mul_f32_e32 v5, v5, v17 -; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_mul_f32_e32 v6, v6, v17 -; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_mul_f32_e32 v7, v7, v17 -; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_mul_f32_e32 v8, v8, v17 -; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_mul_f32_e32 v9, v9, v17 -; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_mul_f32_e32 v10, v10, v17 -; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_mul_f32_e32 v11, v11, v17 -; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_mul_f32_e32 v12, v12, v17 -; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_mul_f32_e32 v13, v13, v17 -; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX9-NEXT: v_mul_f32_e32 v14, v14, v17 -; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 -; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX9-NEXT: v_mul_f32_e32 v15, v15, v17 -; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_mul_f32_e32 v17, v33, v17 +; GFX9-NEXT: v_mul_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 +; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 +; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 +; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 +; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 +; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 +; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 +; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_fmul_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_mul_f32_e32 v39, v48, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 +; GFX10-NEXT: v_mul_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_mul_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_mul_f32_e32 v21, v53, v52 -; GFX10-NEXT: v_mul_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_mul_f32_e32 v22, v55, v54 -; GFX10-NEXT: v_mul_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_mul_f32_e32 v49, v50, v49 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 +; GFX10-NEXT: v_mul_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 ; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX10-NEXT: v_mul_f32_e32 v32, v33, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX10-NEXT: v_mul_f32_e32 v33, v34, v33 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 +; GFX10-NEXT: v_mul_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_mul_f32_e32 v35, v36, v35 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 +; GFX10-NEXT: v_mul_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_mul_f32_e32 v37, v38, v37 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 +; GFX10-NEXT: v_mul_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX10-NEXT: v_mul_f32_e32 v0, v0, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX10-NEXT: v_mul_f32_e32 v34, v35, v34 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GFX10-NEXT: v_mul_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 -; GFX10-NEXT: v_mul_f32_e32 v36, v37, v36 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_mul_f32_e32 v51, v52, v51 +; GFX10-NEXT: v_mul_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_mul_f32_e32 v25, v54, v53 +; GFX10-NEXT: v_mul_f32_e32 v8, v8, v24 +; GFX10-NEXT: v_mul_f32_e32 v24, v64, v55 +; GFX10-NEXT: v_mul_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_mul_f32_e32 v23, v66, v65 +; GFX10-NEXT: v_mul_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_mul_f32_e32 v22, v68, v67 +; GFX10-NEXT: v_mul_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_mul_f32_e32 v21, v30, v34 +; GFX10-NEXT: v_mul_f32_e32 v29, v29, v36 +; GFX10-NEXT: v_mul_f32_e32 v28, v28, v38 +; GFX10-NEXT: v_mul_f32_e32 v27, v27, v48 +; GFX10-NEXT: v_mul_f32_e32 v26, v26, v50 ; GFX10-NEXT: v_mul_f32_e32 v2, v2, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; GFX10-NEXT: v_mul_f32_e32 v38, v39, v38 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GFX10-NEXT: v_mul_f32_e32 v3, v3, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 -; GFX10-NEXT: v_mul_f32_e32 v48, v49, v48 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX10-NEXT: v_mul_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX10-NEXT: v_mul_f32_e32 v50, v51, v50 -; GFX10-NEXT: v_mul_f32_e32 v23, v65, v64 -; GFX10-NEXT: v_mul_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_mul_f32_e32 v24, v67, v66 -; GFX10-NEXT: v_mul_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_mul_f32_e32 v25, v33, v68 -; GFX10-NEXT: v_mul_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_mul_f32_e32 v16, v35, v16 -; GFX10-NEXT: v_mul_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_mul_f32_e32 v17, v37, v17 -; GFX10-NEXT: v_mul_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_mul_f32_e32 v18, v39, v18 -; GFX10-NEXT: v_mul_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_mul_f32_e32 v19, v49, v19 -; GFX10-NEXT: v_mul_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 +; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 -; GFX10-NEXT: v_mul_f32_e32 v20, v20, v21 -; GFX10-NEXT: v_mul_f32_e32 v15, v15, v22 -; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX10-NEXT: v_mul_f32_e32 v16, v32, v16 +; GFX10-NEXT: v_mul_f32_e32 v15, v15, v17 +; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_fmul_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 -; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX11-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 +; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX11-NEXT: v_dual_mul_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 +; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX11-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 +; GFX11-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_dual_mul_f32 v2, v2, v18 :: v_dual_mul_f32 v3, v3, v19 +; GFX11-NEXT: v_dual_mul_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 +; GFX11-NEXT: v_dual_mul_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_mul_f32_e32 v6, v6, v22 +; GFX11-NEXT: v_dual_mul_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_mul_f32_e32 v10, v10, v26 +; GFX11-NEXT: v_mul_f32_e32 v26, v52, v51 +; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX11-NEXT: v_mul_f32_e32 v25, v54, v53 +; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX11-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_dual_mul_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 -; GFX11-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_mul_f32_e32 v4, v4, v20 -; GFX11-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_mul_f32 v9, v9, v25 -; GFX11-NEXT: v_mul_f32_e32 v25, v69, v68 -; GFX11-NEXT: v_dual_mul_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 -; GFX11-NEXT: v_mul_f32_e32 v27, v81, v80 -; GFX11-NEXT: v_mul_f32_e32 v12, v12, v28 -; GFX11-NEXT: v_dual_mul_f32 v28, v83, v82 :: v_dual_mul_f32 v29, v85, v84 -; GFX11-NEXT: v_dual_mul_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_mul_f32_e32 v22, v55, v54 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_mul_f32_e32 v24, v64, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX11-NEXT: v_mul_f32_e32 v7, v7, v23 +; GFX11-NEXT: v_mul_f32_e32 v23, v66, v65 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_dual_mul_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 +; GFX11-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 +; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX11-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_mul_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX11-NEXT: v_mul_f32_e32 v37, v86, v85 +; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 ; GFX11-NEXT: v_mul_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_mul_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_mul_f32_e32 v23, v65, v64 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_dual_mul_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_mul_f32_e32 v2, v2, v18 -; GFX11-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 -; GFX11-NEXT: v_mul_f32_e32 v18, v39, v38 -; GFX11-NEXT: v_dual_mul_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_mul_f32_e32 v19, v49, v48 -; GFX11-NEXT: v_mul_f32_e32 v17, v37, v36 -; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX11-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_mul_f32_e32 v21, v53, v52 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v16 -; GFX11-NEXT: v_mul_f32_e32 v16, v35, v34 -; GFX11-NEXT: v_mul_f32_e32 v32, v33, v32 -; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 -; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 -; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 -; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mul_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_mul_f32_e32 v15, v15, v17 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33 +; GFX11-NEXT: v_dual_mul_f32 v34, v80, v71 :: v_dual_mul_f32 v35, v82, v81 +; GFX11-NEXT: v_mul_f32_e32 v36, v84, v83 +; GFX11-NEXT: v_dual_mul_f32 v16, v32, v16 :: v_dual_mul_f32 v15, v15, v17 +; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = fmul <32 x bfloat> %a, %b @@ -14686,483 +14680,480 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_minnum_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX8-NEXT: v_min_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX8-NEXT: v_min_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX8-NEXT: v_min_f32_e32 v30, v14, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_min_f32_e32 v14, v32, v14 +; GFX8-NEXT: v_min_f32_e32 v13, v13, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_min_f32_e32 v29, v32, v29 +; GFX8-NEXT: v_min_f32_e32 v12, v12, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_min_f32_e32 v28, v32, v28 +; GFX8-NEXT: v_min_f32_e32 v11, v11, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_min_f32_e32 v27, v32, v27 +; GFX8-NEXT: v_min_f32_e32 v10, v10, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_min_f32_e32 v26, v32, v26 +; GFX8-NEXT: v_min_f32_e32 v9, v9, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX8-NEXT: v_min_f32_e32 v8, v8, v24 +; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX8-NEXT: v_min_f32_e32 v25, v32, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX8-NEXT: v_min_f32_e32 v32, v32, v33 +; GFX8-NEXT: v_min_f32_e32 v15, v15, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_min_f32_e32 v24, v33, v24 +; GFX8-NEXT: v_min_f32_e32 v7, v7, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_min_f32_e32 v23, v33, v23 +; GFX8-NEXT: v_min_f32_e32 v6, v6, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_min_f32_e32 v22, v33, v22 +; GFX8-NEXT: v_min_f32_e32 v5, v5, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_min_f32_e32 v21, v33, v21 +; GFX8-NEXT: v_min_f32_e32 v4, v4, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_min_f32_e32 v20, v33, v20 +; GFX8-NEXT: v_min_f32_e32 v3, v3, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_min_f32_e32 v19, v33, v19 +; GFX8-NEXT: v_min_f32_e32 v2, v2, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_min_f32_e32 v18, v33, v18 ; GFX8-NEXT: v_min_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_min_f32_e32 v16, v31, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX8-NEXT: v_min_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_min_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX8-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_min_f32_e32 v2, v2, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX8-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_min_f32_e32 v3, v3, v17 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX8-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_min_f32_e32 v4, v4, v17 -; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_min_f32_e32 v5, v5, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_min_f32_e32 v6, v6, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_min_f32_e32 v7, v7, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_min_f32_e32 v8, v8, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_min_f32_e32 v9, v9, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_min_f32_e32 v10, v10, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_min_f32_e32 v11, v11, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_min_f32_e32 v12, v12, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_min_f32_e32 v13, v13, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_min_f32_e32 v14, v14, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_min_f32_e32 v15, v15, v17 -; GFX8-NEXT: v_min_f32_e32 v16, v18, v16 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 +; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 +; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minnum_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX9-NEXT: v_min_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_min_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_min_f32_e32 v14, v14, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_min_f32_e32 v30, v32, v30 +; GFX9-NEXT: v_min_f32_e32 v13, v13, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_min_f32_e32 v29, v32, v29 +; GFX9-NEXT: v_min_f32_e32 v12, v12, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_min_f32_e32 v28, v32, v28 +; GFX9-NEXT: v_min_f32_e32 v11, v11, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_min_f32_e32 v27, v32, v27 +; GFX9-NEXT: v_min_f32_e32 v10, v10, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_min_f32_e32 v26, v32, v26 +; GFX9-NEXT: v_min_f32_e32 v9, v9, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_min_f32_e32 v8, v8, v24 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX9-NEXT: v_min_f32_e32 v25, v32, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 +; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 +; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 +; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 +; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 +; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 +; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_min_f32_e32 v32, v32, v33 +; GFX9-NEXT: v_min_f32_e32 v15, v15, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_min_f32_e32 v24, v33, v24 +; GFX9-NEXT: v_min_f32_e32 v7, v7, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_min_f32_e32 v23, v33, v23 +; GFX9-NEXT: v_min_f32_e32 v6, v6, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_min_f32_e32 v22, v33, v22 +; GFX9-NEXT: v_min_f32_e32 v5, v5, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_min_f32_e32 v21, v33, v21 +; GFX9-NEXT: v_min_f32_e32 v4, v4, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_min_f32_e32 v20, v33, v20 +; GFX9-NEXT: v_min_f32_e32 v3, v3, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_min_f32_e32 v19, v33, v19 +; GFX9-NEXT: v_min_f32_e32 v2, v2, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_min_f32_e32 v16, v31, v16 +; GFX9-NEXT: v_min_f32_e32 v18, v33, v18 ; GFX9-NEXT: v_min_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_min_f32_e32 v2, v2, v17 -; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_min_f32_e32 v3, v3, v17 -; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_min_f32_e32 v4, v4, v17 -; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_min_f32_e32 v5, v5, v17 -; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_min_f32_e32 v6, v6, v17 -; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_min_f32_e32 v7, v7, v17 -; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_min_f32_e32 v8, v8, v17 -; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_min_f32_e32 v9, v9, v17 -; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_min_f32_e32 v10, v10, v17 -; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_min_f32_e32 v11, v11, v17 -; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_min_f32_e32 v12, v12, v17 -; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_min_f32_e32 v13, v13, v17 -; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX9-NEXT: v_min_f32_e32 v14, v14, v17 -; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 -; GFX9-NEXT: v_min_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX9-NEXT: v_min_f32_e32 v15, v15, v17 -; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_min_f32_e32 v17, v33, v17 +; GFX9-NEXT: v_min_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 +; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 +; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 +; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 +; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 +; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 +; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 +; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minnum_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_min_f32_e32 v39, v48, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 +; GFX10-NEXT: v_min_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_min_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_min_f32_e32 v21, v53, v52 -; GFX10-NEXT: v_min_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_min_f32_e32 v22, v55, v54 -; GFX10-NEXT: v_min_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_min_f32_e32 v49, v50, v49 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 +; GFX10-NEXT: v_min_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 ; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX10-NEXT: v_min_f32_e32 v32, v33, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX10-NEXT: v_min_f32_e32 v33, v34, v33 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 +; GFX10-NEXT: v_min_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_min_f32_e32 v35, v36, v35 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 +; GFX10-NEXT: v_min_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_min_f32_e32 v37, v38, v37 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 +; GFX10-NEXT: v_min_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX10-NEXT: v_min_f32_e32 v0, v0, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX10-NEXT: v_min_f32_e32 v34, v35, v34 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GFX10-NEXT: v_min_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 -; GFX10-NEXT: v_min_f32_e32 v36, v37, v36 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_min_f32_e32 v51, v52, v51 +; GFX10-NEXT: v_min_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_min_f32_e32 v25, v54, v53 +; GFX10-NEXT: v_min_f32_e32 v8, v8, v24 +; GFX10-NEXT: v_min_f32_e32 v24, v64, v55 +; GFX10-NEXT: v_min_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_min_f32_e32 v23, v66, v65 +; GFX10-NEXT: v_min_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_min_f32_e32 v22, v68, v67 +; GFX10-NEXT: v_min_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_min_f32_e32 v21, v30, v34 +; GFX10-NEXT: v_min_f32_e32 v29, v29, v36 +; GFX10-NEXT: v_min_f32_e32 v28, v28, v38 +; GFX10-NEXT: v_min_f32_e32 v27, v27, v48 +; GFX10-NEXT: v_min_f32_e32 v26, v26, v50 ; GFX10-NEXT: v_min_f32_e32 v2, v2, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; GFX10-NEXT: v_min_f32_e32 v38, v39, v38 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GFX10-NEXT: v_min_f32_e32 v3, v3, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 -; GFX10-NEXT: v_min_f32_e32 v48, v49, v48 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX10-NEXT: v_min_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX10-NEXT: v_min_f32_e32 v50, v51, v50 -; GFX10-NEXT: v_min_f32_e32 v23, v65, v64 -; GFX10-NEXT: v_min_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_min_f32_e32 v24, v67, v66 -; GFX10-NEXT: v_min_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_min_f32_e32 v25, v33, v68 -; GFX10-NEXT: v_min_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_min_f32_e32 v16, v35, v16 -; GFX10-NEXT: v_min_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_min_f32_e32 v17, v37, v17 -; GFX10-NEXT: v_min_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_min_f32_e32 v18, v39, v18 -; GFX10-NEXT: v_min_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_min_f32_e32 v19, v49, v19 -; GFX10-NEXT: v_min_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 +; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 -; GFX10-NEXT: v_min_f32_e32 v20, v20, v21 -; GFX10-NEXT: v_min_f32_e32 v15, v15, v22 -; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX10-NEXT: v_min_f32_e32 v16, v32, v16 +; GFX10-NEXT: v_min_f32_e32 v15, v15, v17 +; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minnum_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 -; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX11-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 +; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX11-NEXT: v_dual_min_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 +; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX11-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 +; GFX11-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_dual_min_f32 v2, v2, v18 :: v_dual_min_f32 v3, v3, v19 +; GFX11-NEXT: v_dual_min_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 +; GFX11-NEXT: v_dual_min_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_min_f32_e32 v6, v6, v22 +; GFX11-NEXT: v_dual_min_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_min_f32_e32 v10, v10, v26 +; GFX11-NEXT: v_min_f32_e32 v26, v52, v51 +; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX11-NEXT: v_min_f32_e32 v25, v54, v53 +; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX11-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_dual_min_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 -; GFX11-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_min_f32_e32 v4, v4, v20 -; GFX11-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_min_f32 v9, v9, v25 -; GFX11-NEXT: v_min_f32_e32 v25, v69, v68 -; GFX11-NEXT: v_dual_min_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 -; GFX11-NEXT: v_min_f32_e32 v27, v81, v80 -; GFX11-NEXT: v_min_f32_e32 v12, v12, v28 -; GFX11-NEXT: v_dual_min_f32 v28, v83, v82 :: v_dual_min_f32 v29, v85, v84 -; GFX11-NEXT: v_dual_min_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_min_f32_e32 v22, v55, v54 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_min_f32_e32 v24, v64, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX11-NEXT: v_min_f32_e32 v7, v7, v23 +; GFX11-NEXT: v_min_f32_e32 v23, v66, v65 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_dual_min_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 +; GFX11-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 +; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX11-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_min_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX11-NEXT: v_min_f32_e32 v37, v86, v85 +; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 ; GFX11-NEXT: v_min_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_min_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_min_f32_e32 v23, v65, v64 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_dual_min_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_min_f32_e32 v2, v2, v18 -; GFX11-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 -; GFX11-NEXT: v_min_f32_e32 v18, v39, v38 -; GFX11-NEXT: v_dual_min_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_min_f32_e32 v19, v49, v48 -; GFX11-NEXT: v_min_f32_e32 v17, v37, v36 -; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX11-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_min_f32_e32 v21, v53, v52 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 -; GFX11-NEXT: v_min_f32_e32 v0, v0, v16 -; GFX11-NEXT: v_min_f32_e32 v16, v35, v34 -; GFX11-NEXT: v_min_f32_e32 v32, v33, v32 -; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 -; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 -; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 -; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_min_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_min_f32_e32 v15, v15, v17 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33 +; GFX11-NEXT: v_dual_min_f32 v34, v80, v71 :: v_dual_min_f32 v35, v82, v81 +; GFX11-NEXT: v_min_f32_e32 v36, v84, v83 +; GFX11-NEXT: v_dual_min_f32 v16, v32, v16 :: v_dual_min_f32 v15, v15, v17 +; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = call <32 x bfloat> @llvm.minnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) @@ -16813,483 +16804,480 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX8-LABEL: v_maxnum_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX8-NEXT: v_max_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX8-NEXT: v_max_f32_e32 v31, v32, v31 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX8-NEXT: v_max_f32_e32 v1, v1, v17 -; GFX8-NEXT: v_max_f32_e32 v16, v31, v16 -; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX8-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX8-NEXT: v_max_f32_e32 v2, v2, v17 -; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX8-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX8-NEXT: v_max_f32_e32 v3, v3, v17 -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX8-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX8-NEXT: v_max_f32_e32 v4, v4, v17 -; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21 -; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX8-NEXT: v_max_f32_e32 v5, v5, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 -; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX8-NEXT: v_max_f32_e32 v6, v6, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23 -; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX8-NEXT: v_max_f32_e32 v7, v7, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 +; GFX8-NEXT: v_max_f32_e32 v30, v14, v30 +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX8-NEXT: v_max_f32_e32 v14, v32, v14 +; GFX8-NEXT: v_max_f32_e32 v13, v13, v29 +; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX8-NEXT: v_max_f32_e32 v29, v32, v29 +; GFX8-NEXT: v_max_f32_e32 v12, v12, v28 +; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX8-NEXT: v_max_f32_e32 v28, v32, v28 +; GFX8-NEXT: v_max_f32_e32 v11, v11, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX8-NEXT: v_max_f32_e32 v27, v32, v27 +; GFX8-NEXT: v_max_f32_e32 v10, v10, v26 +; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX8-NEXT: v_max_f32_e32 v26, v32, v26 +; GFX8-NEXT: v_max_f32_e32 v9, v9, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 ; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX8-NEXT: v_max_f32_e32 v8, v8, v18 +; GFX8-NEXT: v_max_f32_e32 v8, v8, v24 +; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX8-NEXT: v_max_f32_e32 v25, v32, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25 -; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX8-NEXT: v_max_f32_e32 v9, v9, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 -; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX8-NEXT: v_max_f32_e32 v10, v10, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27 -; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX8-NEXT: v_max_f32_e32 v11, v11, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28 -; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX8-NEXT: v_max_f32_e32 v12, v12, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29 -; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX8-NEXT: v_max_f32_e32 v13, v13, v18 ; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16 -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 -; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30 -; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX8-NEXT: v_max_f32_e32 v14, v14, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16 +; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16 +; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16 +; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16 +; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16 +; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16 ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX8-NEXT: v_max_f32_e32 v32, v32, v33 +; GFX8-NEXT: v_max_f32_e32 v15, v15, v24 +; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX8-NEXT: v_max_f32_e32 v24, v33, v24 +; GFX8-NEXT: v_max_f32_e32 v7, v7, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX8-NEXT: v_max_f32_e32 v23, v33, v23 +; GFX8-NEXT: v_max_f32_e32 v6, v6, v22 +; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX8-NEXT: v_max_f32_e32 v22, v33, v22 +; GFX8-NEXT: v_max_f32_e32 v5, v5, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX8-NEXT: v_max_f32_e32 v21, v33, v21 +; GFX8-NEXT: v_max_f32_e32 v4, v4, v20 +; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX8-NEXT: v_max_f32_e32 v20, v33, v20 +; GFX8-NEXT: v_max_f32_e32 v3, v3, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX8-NEXT: v_max_f32_e32 v19, v33, v19 +; GFX8-NEXT: v_max_f32_e32 v2, v2, v18 +; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX8-NEXT: v_max_f32_e32 v15, v15, v17 -; GFX8-NEXT: v_max_f32_e32 v16, v18, v16 +; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX8-NEXT: v_max_f32_e32 v18, v33, v18 +; GFX8-NEXT: v_max_f32_e32 v1, v1, v17 +; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX8-NEXT: v_max_f32_e32 v0, v0, v16 +; GFX8-NEXT: v_max_f32_e32 v17, v33, v17 +; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16 +; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30 +; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16 +; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16 +; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16 +; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16 +; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16 +; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16 +; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16 +; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16 +; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16 +; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maxnum_v32bf16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14 +; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX9-NEXT: v_max_f32_e32 v31, v32, v31 -; GFX9-NEXT: v_max_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_max_f32_e32 v14, v14, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13 +; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX9-NEXT: v_max_f32_e32 v30, v32, v30 +; GFX9-NEXT: v_max_f32_e32 v13, v13, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX9-NEXT: v_max_f32_e32 v29, v32, v29 +; GFX9-NEXT: v_max_f32_e32 v12, v12, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX9-NEXT: v_max_f32_e32 v28, v32, v28 +; GFX9-NEXT: v_max_f32_e32 v11, v11, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10 +; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX9-NEXT: v_max_f32_e32 v27, v32, v27 +; GFX9-NEXT: v_max_f32_e32 v10, v10, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9 +; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 +; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX9-NEXT: v_max_f32_e32 v26, v32, v26 +; GFX9-NEXT: v_max_f32_e32 v9, v9, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX9-NEXT: v_max_f32_e32 v8, v8, v24 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 +; GFX9-NEXT: v_max_f32_e32 v25, v32, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 ; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17 -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1 +; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4 +; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4 +; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4 +; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4 +; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4 +; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4 +; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24 +; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX9-NEXT: v_max_f32_e32 v32, v32, v33 +; GFX9-NEXT: v_max_f32_e32 v15, v15, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7 +; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX9-NEXT: v_max_f32_e32 v24, v33, v24 +; GFX9-NEXT: v_max_f32_e32 v7, v7, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6 +; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX9-NEXT: v_max_f32_e32 v23, v33, v23 +; GFX9-NEXT: v_max_f32_e32 v6, v6, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5 +; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX9-NEXT: v_max_f32_e32 v22, v33, v22 +; GFX9-NEXT: v_max_f32_e32 v5, v5, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4 +; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX9-NEXT: v_max_f32_e32 v21, v33, v21 +; GFX9-NEXT: v_max_f32_e32 v4, v4, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3 +; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX9-NEXT: v_max_f32_e32 v20, v33, v20 +; GFX9-NEXT: v_max_f32_e32 v3, v3, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2 +; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX9-NEXT: v_max_f32_e32 v19, v33, v19 +; GFX9-NEXT: v_max_f32_e32 v2, v2, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1 ; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX9-NEXT: v_max_f32_e32 v16, v31, v16 +; GFX9-NEXT: v_max_f32_e32 v18, v33, v18 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v17 -; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX9-NEXT: v_max_f32_e32 v2, v2, v17 -; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX9-NEXT: v_max_f32_e32 v3, v3, v17 -; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20 -; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX9-NEXT: v_max_f32_e32 v4, v4, v17 -; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21 -; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX9-NEXT: v_max_f32_e32 v5, v5, v17 -; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22 -; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX9-NEXT: v_max_f32_e32 v6, v6, v17 -; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23 -; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX9-NEXT: v_max_f32_e32 v7, v7, v17 -; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24 -; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX9-NEXT: v_max_f32_e32 v8, v8, v17 -; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25 -; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX9-NEXT: v_max_f32_e32 v9, v9, v17 -; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26 -; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX9-NEXT: v_max_f32_e32 v10, v10, v17 -; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27 -; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX9-NEXT: v_max_f32_e32 v11, v11, v17 -; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX9-NEXT: v_max_f32_e32 v12, v12, v17 -; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX9-NEXT: v_max_f32_e32 v13, v13, v17 -; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30 -; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX9-NEXT: v_max_f32_e32 v14, v14, v17 -; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15 -; GFX9-NEXT: v_max_f32_e32 v16, v17, v16 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 -; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX9-NEXT: v_max_f32_e32 v15, v15, v17 -; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0 +; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-NEXT: v_max_f32_e32 v17, v33, v17 +; GFX9-NEXT: v_max_f32_e32 v0, v0, v16 +; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4 +; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4 +; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4 +; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4 +; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4 +; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4 +; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4 +; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maxnum_v32bf16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22 -; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 +; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10 +; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 +; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14 +; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 +; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_max_f32_e32 v39, v48, v39 +; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17 +; GFX10-NEXT: v_max_f32_e32 v11, v11, v27 +; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1 ; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3 -; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4 -; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; GFX10-NEXT: v_max_f32_e32 v5, v5, v21 -; GFX10-NEXT: v_max_f32_e32 v21, v53, v52 -; GFX10-NEXT: v_max_f32_e32 v6, v6, v22 -; GFX10-NEXT: v_max_f32_e32 v22, v55, v54 -; GFX10-NEXT: v_max_f32_e32 v7, v7, v23 -; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25 -; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9 +; GFX10-NEXT: v_max_f32_e32 v49, v50, v49 +; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16 +; GFX10-NEXT: v_max_f32_e32 v10, v10, v26 +; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0 +; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9 ; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX10-NEXT: v_max_f32_e32 v32, v33, v32 -; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10 -; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX10-NEXT: v_max_f32_e32 v33, v34, v33 +; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20 +; GFX10-NEXT: v_max_f32_e32 v14, v14, v30 +; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4 +; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX10-NEXT: v_max_f32_e32 v35, v36, v35 +; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19 +; GFX10-NEXT: v_max_f32_e32 v13, v13, v29 +; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3 +; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX10-NEXT: v_max_f32_e32 v37, v38, v37 +; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18 +; GFX10-NEXT: v_max_f32_e32 v12, v12, v28 +; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2 +; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; GFX10-NEXT: v_max_f32_e32 v0, v0, v16 -; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27 -; GFX10-NEXT: v_max_f32_e32 v34, v35, v34 -; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11 -; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 ; GFX10-NEXT: v_max_f32_e32 v1, v1, v17 -; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28 -; GFX10-NEXT: v_max_f32_e32 v36, v37, v36 -; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12 -; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX10-NEXT: v_max_f32_e32 v51, v52, v51 +; GFX10-NEXT: v_max_f32_e32 v9, v9, v25 +; GFX10-NEXT: v_max_f32_e32 v25, v54, v53 +; GFX10-NEXT: v_max_f32_e32 v8, v8, v24 +; GFX10-NEXT: v_max_f32_e32 v24, v64, v55 +; GFX10-NEXT: v_max_f32_e32 v7, v7, v23 +; GFX10-NEXT: v_max_f32_e32 v23, v66, v65 +; GFX10-NEXT: v_max_f32_e32 v6, v6, v22 +; GFX10-NEXT: v_max_f32_e32 v22, v68, v67 +; GFX10-NEXT: v_max_f32_e32 v5, v5, v21 +; GFX10-NEXT: v_max_f32_e32 v21, v30, v34 +; GFX10-NEXT: v_max_f32_e32 v29, v29, v36 +; GFX10-NEXT: v_max_f32_e32 v28, v28, v38 +; GFX10-NEXT: v_max_f32_e32 v27, v27, v48 +; GFX10-NEXT: v_max_f32_e32 v26, v26, v50 ; GFX10-NEXT: v_max_f32_e32 v2, v2, v18 -; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; GFX10-NEXT: v_max_f32_e32 v38, v39, v38 -; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13 -; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 ; GFX10-NEXT: v_max_f32_e32 v3, v3, v19 -; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30 -; GFX10-NEXT: v_max_f32_e32 v48, v49, v48 -; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14 -; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 ; GFX10-NEXT: v_max_f32_e32 v4, v4, v20 -; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15 -; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX10-NEXT: v_max_f32_e32 v50, v51, v50 -; GFX10-NEXT: v_max_f32_e32 v23, v65, v64 -; GFX10-NEXT: v_max_f32_e32 v8, v8, v24 -; GFX10-NEXT: v_max_f32_e32 v24, v67, v66 -; GFX10-NEXT: v_max_f32_e32 v9, v9, v25 -; GFX10-NEXT: v_max_f32_e32 v25, v33, v68 -; GFX10-NEXT: v_max_f32_e32 v10, v10, v26 -; GFX10-NEXT: v_max_f32_e32 v16, v35, v16 -; GFX10-NEXT: v_max_f32_e32 v11, v11, v27 -; GFX10-NEXT: v_max_f32_e32 v17, v37, v17 -; GFX10-NEXT: v_max_f32_e32 v12, v12, v28 -; GFX10-NEXT: v_max_f32_e32 v18, v39, v18 -; GFX10-NEXT: v_max_f32_e32 v13, v13, v29 -; GFX10-NEXT: v_max_f32_e32 v19, v49, v19 -; GFX10-NEXT: v_max_f32_e32 v14, v14, v30 -; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302 -; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302 -; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302 -; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302 -; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302 -; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302 -; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302 -; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302 -; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302 +; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302 +; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302 +; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302 +; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302 +; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 +; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302 +; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302 +; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302 +; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302 +; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302 +; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31 -; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31 -; GFX10-NEXT: v_max_f32_e32 v20, v20, v21 -; GFX10-NEXT: v_max_f32_e32 v15, v15, v22 -; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302 +; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31 +; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX10-NEXT: v_max_f32_e32 v16, v32, v16 +; GFX10-NEXT: v_max_f32_e32 v15, v15, v17 +; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maxnum_v32bf16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10 -; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27 -; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8 -; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5 -; GFX11-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25 +; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17 +; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16 +; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0 +; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7 +; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22 +; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11 +; GFX11-NEXT: v_dual_max_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11 +; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21 +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25 +; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20 +; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4 +; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 +; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23 +; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3 ; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22 +; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 +; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9 +; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 +; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2 +; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24 +; GFX11-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24 +; GFX11-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10 +; GFX11-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10 +; GFX11-NEXT: v_dual_max_f32 v2, v2, v18 :: v_dual_max_f32 v3, v3, v19 +; GFX11-NEXT: v_dual_max_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26 +; GFX11-NEXT: v_dual_max_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26 +; GFX11-NEXT: v_max_f32_e32 v6, v6, v22 +; GFX11-NEXT: v_dual_max_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28 ; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29 -; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_max_f32_e32 v10, v10, v26 +; GFX11-NEXT: v_max_f32_e32 v26, v52, v51 +; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302 +; GFX11-NEXT: v_max_f32_e32 v25, v54, v53 +; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302 +; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 ; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31 +; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30 -; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14 -; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20 -; GFX11-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; GFX11-NEXT: v_dual_max_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4 -; GFX11-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_max_f32_e32 v4, v4, v20 -; GFX11-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_max_f32 v9, v9, v25 -; GFX11-NEXT: v_max_f32_e32 v25, v69, v68 -; GFX11-NEXT: v_dual_max_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3 -; GFX11-NEXT: v_max_f32_e32 v27, v81, v80 -; GFX11-NEXT: v_max_f32_e32 v12, v12, v28 -; GFX11-NEXT: v_dual_max_f32 v28, v83, v82 :: v_dual_max_f32 v29, v85, v84 -; GFX11-NEXT: v_dual_max_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3 -; GFX11-NEXT: v_max_f32_e32 v22, v55, v54 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17 -; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; GFX11-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27 +; GFX11-NEXT: v_max_f32_e32 v24, v64, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12 +; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GFX11-NEXT: v_max_f32_e32 v7, v7, v23 +; GFX11-NEXT: v_max_f32_e32 v23, v66, v65 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29 +; GFX11-NEXT: v_dual_max_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30 +; GFX11-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14 +; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15 +; GFX11-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14 +; GFX11-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30 +; GFX11-NEXT: v_max_f32_e32 v29, v38, v37 +; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; GFX11-NEXT: v_max_f32_e32 v37, v86, v85 +; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302 ; GFX11-NEXT: v_max_f32_e32 v14, v14, v30 -; GFX11-NEXT: v_dual_max_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX11-NEXT: v_max_f32_e32 v23, v65, v64 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; GFX11-NEXT: v_dual_max_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21 -; GFX11-NEXT: v_max_f32_e32 v2, v2, v18 -; GFX11-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16 -; GFX11-NEXT: v_max_f32_e32 v18, v39, v38 -; GFX11-NEXT: v_dual_max_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16 -; GFX11-NEXT: v_max_f32_e32 v19, v49, v48 -; GFX11-NEXT: v_max_f32_e32 v17, v37, v36 -; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0 -; GFX11-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0 -; GFX11-NEXT: v_max_f32_e32 v21, v53, v52 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302 -; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302 -; GFX11-NEXT: v_max_f32_e32 v0, v0, v16 -; GFX11-NEXT: v_max_f32_e32 v16, v35, v34 -; GFX11-NEXT: v_max_f32_e32 v32, v33, v32 -; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302 -; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302 -; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302 -; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302 -; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302 -; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302 -; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302 -; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302 -; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302 -; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302 -; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302 -; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302 -; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_max_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31 -; GFX11-NEXT: v_max_f32_e32 v15, v15, v17 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33 +; GFX11-NEXT: v_dual_max_f32 v34, v80, v71 :: v_dual_max_f32 v35, v82, v81 +; GFX11-NEXT: v_max_f32_e32 v36, v84, v83 +; GFX11-NEXT: v_dual_max_f32 v16, v32, v16 :: v_dual_max_f32 v15, v15, v17 +; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302 +; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302 +; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302 +; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302 +; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302 +; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302 +; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302 +; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302 +; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302 +; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302 ; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = call <32 x bfloat> @llvm.maxnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) @@ -28228,171 +28216,235 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_writelane_b32 v31, s30, 0 ; GFX8-NEXT: v_writelane_b32 v31, s31, 1 ; GFX8-NEXT: v_writelane_b32 v31, s34, 2 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_writelane_b32 v31, s35, 3 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v1 ; GFX8-NEXT: v_writelane_b32 v31, s36, 4 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v2 ; GFX8-NEXT: v_writelane_b32 v31, s37, 5 -; GFX8-NEXT: v_and_b32_e32 v21, 1, v21 -; GFX8-NEXT: v_and_b32_e32 v18, 1, v18 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v3 ; GFX8-NEXT: v_writelane_b32 v31, s38, 6 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v21 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v18 -; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68 -; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 -; GFX8-NEXT: v_and_b32_e32 v17, 1, v17 -; GFX8-NEXT: v_and_b32_e32 v16, 1, v16 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v4 ; GFX8-NEXT: v_writelane_b32 v31, s39, 7 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v17 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v16 -; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 -; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:8 -; GFX8-NEXT: v_and_b32_e32 v15, 1, v15 -; GFX8-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v5 ; GFX8-NEXT: v_writelane_b32 v31, s40, 8 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v15 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v14 -; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:76 -; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:12 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v6 ; GFX8-NEXT: v_writelane_b32 v31, s41, 9 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v7 ; GFX8-NEXT: v_writelane_b32 v31, s42, 10 -; GFX8-NEXT: v_and_b32_e32 v13, 1, v13 -; GFX8-NEXT: v_and_b32_e32 v12, 1, v12 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v8 ; GFX8-NEXT: v_writelane_b32 v31, s43, 11 -; GFX8-NEXT: v_and_b32_e32 v20, 1, v20 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v13 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v12 -; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:80 -; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:16 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v20 -; GFX8-NEXT: buffer_load_ushort v20, off, s[0:3], s32 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v9 ; GFX8-NEXT: v_writelane_b32 v31, s44, 12 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v10 ; GFX8-NEXT: v_writelane_b32 v31, s45, 13 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v11 ; GFX8-NEXT: v_writelane_b32 v31, s46, 14 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v12 ; GFX8-NEXT: v_writelane_b32 v31, s47, 15 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v13 ; GFX8-NEXT: v_writelane_b32 v31, s48, 16 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v14 ; GFX8-NEXT: v_writelane_b32 v31, s49, 17 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v15 ; GFX8-NEXT: v_writelane_b32 v31, s50, 18 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v16 ; GFX8-NEXT: v_writelane_b32 v31, s51, 19 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v17 ; GFX8-NEXT: v_writelane_b32 v31, s52, 20 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v18 ; GFX8-NEXT: v_writelane_b32 v31, s53, 21 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v19 ; GFX8-NEXT: v_writelane_b32 v31, s54, 22 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v20 ; GFX8-NEXT: v_writelane_b32 v31, s55, 23 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v21 ; GFX8-NEXT: v_writelane_b32 v31, s56, 24 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v22 ; GFX8-NEXT: v_writelane_b32 v31, s57, 25 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v23 ; GFX8-NEXT: v_writelane_b32 v31, s58, 26 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v24 ; GFX8-NEXT: v_writelane_b32 v31, s59, 27 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v25 ; GFX8-NEXT: v_writelane_b32 v31, s60, 28 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v26 ; GFX8-NEXT: v_writelane_b32 v31, s61, 29 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v27 ; GFX8-NEXT: v_writelane_b32 v31, s62, 30 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v28 ; GFX8-NEXT: v_writelane_b32 v31, s63, 31 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v29 ; GFX8-NEXT: v_writelane_b32 v31, s64, 32 -; GFX8-NEXT: v_and_b32_e32 v8, 1, v8 -; GFX8-NEXT: v_and_b32_e32 v7, 1, v7 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 1, v30 ; GFX8-NEXT: v_writelane_b32 v31, s65, 33 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v8 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v7 -; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:84 -; GFX8-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20 -; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX8-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX8-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v0 +; GFX8-NEXT: buffer_load_ushort v0, off, s[0:3], s32 ; GFX8-NEXT: v_writelane_b32 v31, s66, 34 -; GFX8-NEXT: v_and_b32_e32 v3, 1, v3 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v2 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v1 -; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_writelane_b32 v31, s67, 35 -; GFX8-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX8-NEXT: v_and_b32_e32 v5, 1, v5 -; GFX8-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[66:67], 1, v0 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v6 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v5 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v4 -; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 -; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 -; GFX8-NEXT: v_and_b32_e32 v10, 1, v10 -; GFX8-NEXT: v_and_b32_e32 v9, 1, v9 -; GFX8-NEXT: v_and_b32_e32 v11, 1, v11 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v10 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v9 -; GFX8-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:92 -; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:28 -; GFX8-NEXT: v_and_b32_e32 v25, 1, v25 -; GFX8-NEXT: v_and_b32_e32 v24, 1, v24 -; GFX8-NEXT: v_and_b32_e32 v23, 1, v23 -; GFX8-NEXT: v_and_b32_e32 v22, 1, v22 -; GFX8-NEXT: v_and_b32_e32 v19, 1, v19 -; GFX8-NEXT: s_waitcnt vmcnt(14) -; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v18 -; GFX8-NEXT: s_waitcnt vmcnt(13) -; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v21 -; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[64:65] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v18, v21, s[66:67] -; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX8-NEXT: s_waitcnt vmcnt(13) -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v16 -; GFX8-NEXT: s_waitcnt vmcnt(12) -; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v17 -; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[60:61] -; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[62:63] -; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:40 +; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:68 +; GFX8-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 +; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 +; GFX8-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 +; GFX8-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 +; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12 +; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 +; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16 +; GFX8-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84 +; GFX8-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20 +; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88 +; GFX8-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:24 +; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92 +; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:28 +; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 +; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:32 +; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 +; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:36 +; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 +; GFX8-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 +; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 -; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56 -; GFX8-NEXT: s_waitcnt vmcnt(13) -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v14 -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[56:57] -; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_cndmask_b32_e64 v2, v14, v15, s[58:59] -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: s_waitcnt vmcnt(11) -; GFX8-NEXT: v_cndmask_b32_e64 v3, v12, v13, s[54:55] -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v13 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v11 -; GFX8-NEXT: s_waitcnt vmcnt(10) -; GFX8-NEXT: v_and_b32_e32 v11, 1, v20 -; GFX8-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[52:53] -; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 -; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v25 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v24 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v23 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v22 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v19 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v11 -; GFX8-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 -; GFX8-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:108 -; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96 -; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:32 -; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 -; GFX8-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 -; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:48 -; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 -; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:124 -; GFX8-NEXT: v_and_b32_e32 v26, 1, v26 -; GFX8-NEXT: v_and_b32_e32 v28, 1, v28 -; GFX8-NEXT: v_and_b32_e32 v27, 1, v27 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v26 -; GFX8-NEXT: v_and_b32_e32 v29, 1, v29 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v28 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v27 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29 -; GFX8-NEXT: v_and_b32_e32 v30, 1, v30 -; GFX8-NEXT: s_waitcnt vmcnt(14) -; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v8, s[50:51] -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[48:49] -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30 +; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 +; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:48 +; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 +; GFX8-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 +; GFX8-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 +; GFX8-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:56 +; GFX8-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 +; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60 +; GFX8-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:128 +; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v29 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v33 +; GFX8-NEXT: v_cndmask_b32_e64 v28, v34, v28, s[66:67] +; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v33, s[64:65] +; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v32 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30 +; GFX8-NEXT: v_cndmask_b32_e64 v33, v34, v33, s[62:63] +; GFX8-NEXT: v_cndmask_b32_e64 v30, v30, v32, s[60:61] +; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v27 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v26 +; GFX8-NEXT: v_cndmask_b32_e64 v32, v34, v32, s[58:59] +; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, v27, s[56:57] +; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v25 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v24 +; GFX8-NEXT: v_cndmask_b32_e64 v27, v34, v27, s[54:55] +; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, v25, s[52:53] +; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v23 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v22 +; GFX8-NEXT: v_cndmask_b32_e64 v25, v34, v25, s[50:51] +; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, v23, s[48:49] +; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v20 +; GFX8-NEXT: v_cndmask_b32_e64 v23, v34, v23, s[46:47] +; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, v21, s[44:45] +; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v19 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v18 +; GFX8-NEXT: v_cndmask_b32_e64 v21, v34, v21, s[42:43] +; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, v19, s[40:41] +; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v17 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v19, v34, v19, s[38:39] +; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v17, s[36:37] +; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v15 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v14 +; GFX8-NEXT: v_cndmask_b32_e64 v17, v34, v17, s[34:35] +; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[30:31] +; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v13 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v12 +; GFX8-NEXT: v_cndmask_b32_e64 v15, v34, v15, s[28:29] +; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[26:27] +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v11 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v10 +; GFX8-NEXT: v_cndmask_b32_e64 v13, v34, v13, s[24:25] +; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[22:23] +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v9 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v11, v34, v11, s[20:21] +; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[18:19] +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v7 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v6 +; GFX8-NEXT: v_cndmask_b32_e64 v9, v34, v9, s[16:17] +; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[14:15] +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v5 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v4 +; GFX8-NEXT: v_cndmask_b32_e64 v7, v34, v7, s[12:13] +; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[10:11] +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v5, v34, v5, s[8:9] +; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[6:7] +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v0 +; GFX8-NEXT: v_cndmask_b32_e64 v3, v34, v3, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v5 +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7 +; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v9 +; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v11 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v13 +; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v15 +; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v17 +; GFX8-NEXT: v_or_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v6, v12, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v7, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v19 +; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v21 +; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v23 +; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v25 +; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v27 +; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v32 +; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v33 +; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v28 +; GFX8-NEXT: v_or_b32_sdwa v8, v16, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v9, v18, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v11, v22, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v12, v24, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v13, v26, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v14, v30, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v15, v29, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_readlane_b32 s67, v31, 35 ; GFX8-NEXT: v_readlane_b32 s66, v31, 34 ; GFX8-NEXT: v_readlane_b32 s65, v31, 33 @@ -28403,18 +28455,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_readlane_b32 s60, v31, 28 ; GFX8-NEXT: v_readlane_b32 s59, v31, 27 ; GFX8-NEXT: v_readlane_b32 s58, v31, 26 -; GFX8-NEXT: v_cndmask_b32_e64 v7, v5, v6, s[46:47] -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[44:45] -; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX8-NEXT: v_or_b32_sdwa v5, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v10 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX8-NEXT: v_cndmask_b32_e64 v6, v9, v10, s[42:43] -; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[40:41] -; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX8-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_readlane_b32 s57, v31, 25 ; GFX8-NEXT: v_readlane_b32 s56, v31, 24 ; GFX8-NEXT: v_readlane_b32 s55, v31, 23 @@ -28433,43 +28473,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_readlane_b32 s42, v31, 10 ; GFX8-NEXT: v_readlane_b32 s41, v31, 9 ; GFX8-NEXT: v_readlane_b32 s40, v31, 8 -; GFX8-NEXT: s_waitcnt vmcnt(6) -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v22 -; GFX8-NEXT: s_waitcnt vmcnt(5) -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v23 -; GFX8-NEXT: v_cndmask_b32_e64 v8, v9, v8, s[36:37] -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v18 -; GFX8-NEXT: s_waitcnt vmcnt(3) -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v25 -; GFX8-NEXT: v_cndmask_b32_e64 v7, v22, v23, s[38:39] -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX8-NEXT: v_cndmask_b32_e64 v9, v10, v9, s[30:31] -; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_cndmask_b32_e64 v8, v25, v18, s[34:35] -; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX8-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_cndmask_b32_e64 v9, v24, v16, s[28:29] -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v16 -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v24 -; GFX8-NEXT: v_cndmask_b32_e64 v10, v16, v10, s[26:27] -; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52 -; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX8-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_cndmask_b32_e64 v10, v11, v21, s[24:25] -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v21 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[22:23] -; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 -; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX8-NEXT: v_or_b32_sdwa v10, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: s_waitcnt vmcnt(4) -; GFX8-NEXT: v_cndmask_b32_e64 v11, v19, v20, s[20:21] -; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[16:17] -; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 -; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX8-NEXT: v_or_b32_sdwa v11, v11, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_readlane_b32 s39, v31, 7 ; GFX8-NEXT: v_readlane_b32 s38, v31, 6 ; GFX8-NEXT: v_readlane_b32 s37, v31, 5 @@ -28478,33 +28481,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_readlane_b32 s34, v31, 2 ; GFX8-NEXT: v_readlane_b32 s31, v31, 1 ; GFX8-NEXT: v_readlane_b32 s30, v31, 0 -; GFX8-NEXT: s_waitcnt vmcnt(2) -; GFX8-NEXT: v_cndmask_b32_e64 v19, v12, v18, s[14:15] -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v18, s[12:13] -; GFX8-NEXT: v_cndmask_b32_e64 v18, v13, v17, s[10:11] -; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[8:9] -; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_cndmask_b32_e64 v17, v14, v16, s[6:7] -; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[4:5] -; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX8-NEXT: v_or_b32_sdwa v14, v17, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v16, v15, v20, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v20 -; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[18:19] -; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX8-NEXT: v_or_b32_sdwa v12, v19, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v13, v18, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; GFX8-NEXT: s_mov_b64 exec, s[4:5] @@ -28520,169 +28496,223 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX9-NEXT: v_writelane_b32 v31, s30, 0 ; GFX9-NEXT: v_writelane_b32 v31, s31, 1 ; GFX9-NEXT: v_writelane_b32 v31, s34, 2 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_writelane_b32 v31, s35, 3 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v3 ; GFX9-NEXT: v_writelane_b32 v31, s36, 4 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v2 ; GFX9-NEXT: v_writelane_b32 v31, s37, 5 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v5 ; GFX9-NEXT: v_writelane_b32 v31, s38, 6 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v4 ; GFX9-NEXT: v_writelane_b32 v31, s39, 7 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v7 ; GFX9-NEXT: v_writelane_b32 v31, s40, 8 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v6 ; GFX9-NEXT: v_writelane_b32 v31, s41, 9 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v9 ; GFX9-NEXT: v_writelane_b32 v31, s42, 10 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v8 ; GFX9-NEXT: v_writelane_b32 v31, s43, 11 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v11 ; GFX9-NEXT: v_writelane_b32 v31, s44, 12 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v10 ; GFX9-NEXT: v_writelane_b32 v31, s45, 13 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v13 ; GFX9-NEXT: v_writelane_b32 v31, s46, 14 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v12 ; GFX9-NEXT: v_writelane_b32 v31, s47, 15 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v15 ; GFX9-NEXT: v_writelane_b32 v31, s48, 16 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v14 ; GFX9-NEXT: v_writelane_b32 v31, s49, 17 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v17 ; GFX9-NEXT: v_writelane_b32 v31, s50, 18 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v16 ; GFX9-NEXT: v_writelane_b32 v31, s51, 19 -; GFX9-NEXT: v_and_b32_e32 v21, 1, v21 -; GFX9-NEXT: v_and_b32_e32 v18, 1, v18 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v19 ; GFX9-NEXT: v_writelane_b32 v31, s52, 20 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v21 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v18 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68 -; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 -; GFX9-NEXT: v_and_b32_e32 v17, 1, v17 -; GFX9-NEXT: v_and_b32_e32 v16, 1, v16 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v18 ; GFX9-NEXT: v_writelane_b32 v31, s53, 21 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v17 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v16 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:8 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v21 ; GFX9-NEXT: v_writelane_b32 v31, s54, 22 -; GFX9-NEXT: v_and_b32_e32 v15, 1, v15 -; GFX9-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v20 ; GFX9-NEXT: v_writelane_b32 v31, s55, 23 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v15 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v14 -; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:76 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:12 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v23 ; GFX9-NEXT: v_writelane_b32 v31, s56, 24 -; GFX9-NEXT: v_and_b32_e32 v13, 1, v13 -; GFX9-NEXT: v_and_b32_e32 v12, 1, v12 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v22 ; GFX9-NEXT: v_writelane_b32 v31, s57, 25 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v13 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v12 -; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:80 -; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:16 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v25 ; GFX9-NEXT: v_writelane_b32 v31, s58, 26 -; GFX9-NEXT: v_and_b32_e32 v5, 1, v5 -; GFX9-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v24 ; GFX9-NEXT: v_writelane_b32 v31, s59, 27 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v5 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v4 -; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84 -; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:20 -; GFX9-NEXT: v_and_b32_e32 v20, 1, v20 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v20 -; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v27 ; GFX9-NEXT: v_writelane_b32 v31, s60, 28 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v26 ; GFX9-NEXT: v_writelane_b32 v31, s61, 29 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v29 ; GFX9-NEXT: v_writelane_b32 v31, s62, 30 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v28 ; GFX9-NEXT: v_writelane_b32 v31, s63, 31 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0 +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 ; GFX9-NEXT: v_writelane_b32 v31, s64, 32 ; GFX9-NEXT: v_writelane_b32 v31, s65, 33 ; GFX9-NEXT: v_writelane_b32 v31, s66, 34 -; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_writelane_b32 v31, s67, 35 -; GFX9-NEXT: v_and_b32_e32 v3, 1, v3 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v2 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v1 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v0 +; GFX9-NEXT: v_and_b32_e32 v0, 1, v30 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[66:67], 1, v0 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v3 -; GFX9-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX9-NEXT: v_and_b32_e32 v7, 1, v7 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v6 -; GFX9-NEXT: v_and_b32_e32 v8, 1, v8 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v7 -; GFX9-NEXT: v_and_b32_e32 v9, 1, v9 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v8 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v9 -; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 -; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:24 -; GFX9-NEXT: v_and_b32_e32 v24, 1, v24 -; GFX9-NEXT: v_and_b32_e32 v11, 1, v11 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v24 -; GFX9-NEXT: v_and_b32_e32 v23, 1, v23 -; GFX9-NEXT: v_and_b32_e32 v22, 1, v22 -; GFX9-NEXT: v_and_b32_e32 v19, 1, v19 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v11 -; GFX9-NEXT: v_and_b32_e32 v10, 1, v10 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:48 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v23 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v22 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v19 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v10 -; GFX9-NEXT: v_and_b32_e32 v26, 1, v26 -; GFX9-NEXT: v_and_b32_e32 v25, 1, v25 -; GFX9-NEXT: v_and_b32_e32 v28, 1, v28 -; GFX9-NEXT: v_and_b32_e32 v27, 1, v27 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v26 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v25 -; GFX9-NEXT: v_and_b32_e32 v29, 1, v29 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v28 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v27 -; GFX9-NEXT: v_and_b32_e32 v30, 1, v30 -; GFX9-NEXT: s_waitcnt vmcnt(13) -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v18 -; GFX9-NEXT: s_waitcnt vmcnt(12) -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v21 -; GFX9-NEXT: v_cndmask_b32_e64 v0, v18, v21, s[66:67] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[64:65] -; GFX9-NEXT: s_mov_b32 s64, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v1, v0, s64 -; GFX9-NEXT: s_waitcnt vmcnt(11) -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v16 -; GFX9-NEXT: s_waitcnt vmcnt(10) -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v17 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[62:63] -; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[60:61] -; GFX9-NEXT: v_perm_b32 v1, v2, v1, s64 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:40 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:68 +; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16 +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84 +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20 +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88 +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:24 +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92 +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:28 +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:32 +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:36 +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 +; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 -; GFX9-NEXT: s_waitcnt vmcnt(11) -; GFX9-NEXT: v_cndmask_b32_e64 v2, v14, v15, s[58:59] -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v15 +; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:48 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 +; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 +; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:56 +; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:124 +; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:60 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_cndmask_b32_e64 v29, v32, v33, s[66:67] +; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX9-NEXT: v_cndmask_b32_e64 v32, v32, v33, s[64:65] +; GFX9-NEXT: v_cndmask_b32_e64 v33, v28, v30, s[62:63] +; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX9-NEXT: v_cndmask_b32_e64 v28, v28, v30, s[60:61] +; GFX9-NEXT: v_cndmask_b32_e64 v30, v26, v27, s[58:59] +; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX9-NEXT: v_cndmask_b32_e64 v26, v26, v27, s[56:57] +; GFX9-NEXT: v_cndmask_b32_e64 v27, v24, v25, s[54:55] +; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX9-NEXT: v_cndmask_b32_e64 v24, v24, v25, s[52:53] +; GFX9-NEXT: v_cndmask_b32_e64 v25, v22, v23, s[50:51] +; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX9-NEXT: v_cndmask_b32_e64 v22, v22, v23, s[48:49] +; GFX9-NEXT: v_cndmask_b32_e64 v23, v20, v21, s[46:47] +; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX9-NEXT: v_cndmask_b32_e64 v20, v20, v21, s[44:45] +; GFX9-NEXT: v_cndmask_b32_e64 v21, v18, v19, s[42:43] +; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX9-NEXT: v_cndmask_b32_e64 v18, v18, v19, s[40:41] +; GFX9-NEXT: v_cndmask_b32_e64 v19, v16, v17, s[38:39] +; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_cndmask_b32_e64 v16, v16, v17, s[36:37] +; GFX9-NEXT: v_cndmask_b32_e64 v17, v14, v15, s[34:35] +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v14, v3, s[56:57] -; GFX9-NEXT: v_perm_b32 v2, v3, v2, s64 -; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:124 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 -; GFX9-NEXT: s_waitcnt vmcnt(11) -; GFX9-NEXT: v_cndmask_b32_e64 v3, v12, v13, s[54:55] +; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[30:31] +; GFX9-NEXT: v_cndmask_b32_e64 v15, v12, v13, s[28:29] ; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 ; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[52:53] -; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 -; GFX9-NEXT: v_perm_b32 v3, v12, v3, s64 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29 -; GFX9-NEXT: s_waitcnt vmcnt(10) -; GFX9-NEXT: v_cndmask_b32_e64 v12, v4, v5, s[50:51] +; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[26:27] +; GFX9-NEXT: v_cndmask_b32_e64 v13, v10, v11, s[24:25] +; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[22:23] +; GFX9-NEXT: v_cndmask_b32_e64 v11, v8, v9, s[20:21] +; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[18:19] +; GFX9-NEXT: v_cndmask_b32_e64 v9, v6, v7, s[16:17] +; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[14:15] +; GFX9-NEXT: v_cndmask_b32_e64 v7, v4, v5, s[12:13] ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[48:49] -; GFX9-NEXT: v_perm_b32 v4, v4, v12, s64 -; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 -; GFX9-NEXT: s_waitcnt vmcnt(10) -; GFX9-NEXT: v_and_b32_e32 v11, 1, v20 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v11 -; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:92 -; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28 -; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 -; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 -; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:104 -; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:100 -; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96 -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:32 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30 +; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[10:11] +; GFX9-NEXT: v_cndmask_b32_e64 v5, v2, v3, s[8:9] +; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[6:7] +; GFX9-NEXT: v_cndmask_b32_e64 v3, v0, v1, s[4:5] +; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4 +; GFX9-NEXT: v_perm_b32 v1, v2, v5, s4 +; GFX9-NEXT: v_perm_b32 v2, v4, v7, s4 +; GFX9-NEXT: v_perm_b32 v3, v6, v9, s4 +; GFX9-NEXT: v_perm_b32 v4, v8, v11, s4 +; GFX9-NEXT: v_perm_b32 v5, v10, v13, s4 +; GFX9-NEXT: v_perm_b32 v6, v12, v15, s4 +; GFX9-NEXT: v_perm_b32 v7, v14, v17, s4 +; GFX9-NEXT: v_perm_b32 v8, v16, v19, s4 +; GFX9-NEXT: v_perm_b32 v9, v18, v21, s4 +; GFX9-NEXT: v_perm_b32 v10, v20, v23, s4 +; GFX9-NEXT: v_perm_b32 v11, v22, v25, s4 +; GFX9-NEXT: v_perm_b32 v12, v24, v27, s4 +; GFX9-NEXT: v_perm_b32 v13, v26, v30, s4 +; GFX9-NEXT: v_perm_b32 v14, v28, v33, s4 +; GFX9-NEXT: v_perm_b32 v15, v32, v29, s4 ; GFX9-NEXT: v_readlane_b32 s67, v31, 35 ; GFX9-NEXT: v_readlane_b32 s66, v31, 34 ; GFX9-NEXT: v_readlane_b32 s65, v31, 33 +; GFX9-NEXT: v_readlane_b32 s64, v31, 32 ; GFX9-NEXT: v_readlane_b32 s63, v31, 31 ; GFX9-NEXT: v_readlane_b32 s62, v31, 30 ; GFX9-NEXT: v_readlane_b32 s61, v31, 29 @@ -28698,54 +28728,11 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX9-NEXT: v_readlane_b32 s51, v31, 19 ; GFX9-NEXT: v_readlane_b32 s50, v31, 18 ; GFX9-NEXT: v_readlane_b32 s49, v31, 17 -; GFX9-NEXT: s_waitcnt vmcnt(16) -; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v7, s[46:47] -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[44:45] -; GFX9-NEXT: v_perm_b32 v5, v6, v5, s64 ; GFX9-NEXT: v_readlane_b32 s48, v31, 16 ; GFX9-NEXT: v_readlane_b32 s47, v31, 15 ; GFX9-NEXT: v_readlane_b32 s46, v31, 14 ; GFX9-NEXT: v_readlane_b32 s45, v31, 13 ; GFX9-NEXT: v_readlane_b32 s44, v31, 12 -; GFX9-NEXT: s_waitcnt vmcnt(6) -; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v9, s[42:43] -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v9 -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[40:41] -; GFX9-NEXT: v_perm_b32 v6, v7, v6, s64 -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v22 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v23 -; GFX9-NEXT: v_cndmask_b32_e64 v7, v22, v23, s[38:39] -; GFX9-NEXT: v_cndmask_b32_e64 v8, v9, v8, s[36:37] -; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v20 -; GFX9-NEXT: v_perm_b32 v7, v8, v7, s64 -; GFX9-NEXT: v_cndmask_b32_e64 v8, v20, v18, s[34:35] -; GFX9-NEXT: v_cndmask_b32_e64 v9, v17, v9, s[30:31] -; GFX9-NEXT: v_perm_b32 v8, v9, v8, s64 -; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, v16, s[28:29] -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52 -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56 -; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[26:27] -; GFX9-NEXT: v_perm_b32 v9, v11, v9, s64 -; GFX9-NEXT: v_cndmask_b32_e64 v11, v10, v21, s[24:25] -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v21 -; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v16, s[22:23] -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 -; GFX9-NEXT: v_perm_b32 v10, v10, v11, s64 -; GFX9-NEXT: v_cndmask_b32_e64 v11, v19, v24, s[20:21] -; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v24 -; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX9-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[16:17] -; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 -; GFX9-NEXT: v_perm_b32 v11, v19, v11, s64 ; GFX9-NEXT: v_readlane_b32 s43, v31, 11 ; GFX9-NEXT: v_readlane_b32 s42, v31, 10 ; GFX9-NEXT: v_readlane_b32 s41, v31, 9 @@ -28758,31 +28745,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX9-NEXT: v_readlane_b32 s34, v31, 2 ; GFX9-NEXT: v_readlane_b32 s31, v31, 1 ; GFX9-NEXT: v_readlane_b32 s30, v31, 0 -; GFX9-NEXT: s_waitcnt vmcnt(3) -; GFX9-NEXT: v_cndmask_b32_e64 v19, v12, v18, s[14:15] -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v18, s[12:13] -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_cndmask_b32_e64 v18, v13, v17, s[10:11] -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[8:9] -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_cndmask_b32_e64 v17, v14, v16, s[6:7] -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[4:5] -; GFX9-NEXT: v_perm_b32 v14, v14, v17, s64 -; GFX9-NEXT: v_perm_b32 v12, v12, v19, s64 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v16, v15, v20, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v20 -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[18:19] -; GFX9-NEXT: v_perm_b32 v13, v13, v18, s64 -; GFX9-NEXT: v_perm_b32 v15, v15, v16, s64 -; GFX9-NEXT: v_readlane_b32 s64, v31, 32 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -28796,205 +28758,208 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX10-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s4 -; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 -; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v3 -; GFX10-NEXT: v_and_b32_e32 v3, 1, v6 -; GFX10-NEXT: v_and_b32_e32 v8, 1, v8 -; GFX10-NEXT: v_and_b32_e32 v10, 1, v10 -; GFX10-NEXT: v_and_b32_e32 v12, 1, v12 -; GFX10-NEXT: v_and_b32_e32 v14, 1, v14 -; GFX10-NEXT: v_and_b32_e32 v16, 1, v16 -; GFX10-NEXT: s_clause 0x15 -; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:68 -; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 -; GFX10-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:72 -; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8 -; GFX10-NEXT: buffer_load_ushort v36, off, s[0:3], s32 -; GFX10-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:76 -; GFX10-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:12 -; GFX10-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:80 -; GFX10-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16 -; GFX10-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:20 -; GFX10-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:84 -; GFX10-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:88 -; GFX10-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24 -; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92 -; GFX10-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:28 -; GFX10-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:96 -; GFX10-NEXT: buffer_load_dword v64, off, s[0:3], s32 offset:32 -; GFX10-NEXT: buffer_load_dword v65, off, s[0:3], s32 offset:36 -; GFX10-NEXT: buffer_load_dword v66, off, s[0:3], s32 offset:104 -; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:40 -; GFX10-NEXT: buffer_load_dword v68, off, s[0:3], s32 offset:100 -; GFX10-NEXT: buffer_load_dword v69, off, s[0:3], s32 offset:52 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v0 -; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112 -; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v2 -; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:48 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v4 -; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 -; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v3 -; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 -; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v8 -; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 -; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 -; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v10 -; GFX10-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 -; GFX10-NEXT: v_cmp_eq_u32_e64 s11, 1, v12 -; GFX10-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:60 -; GFX10-NEXT: v_cmp_eq_u32_e64 s12, 1, v14 -; GFX10-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:128 -; GFX10-NEXT: v_cmp_eq_u32_e64 s13, 1, v16 -; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64 -; GFX10-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:44 -; GFX10-NEXT: v_writelane_b32 v31, s30, 0 +; GFX10-NEXT: v_and_b32_e32 v29, 1, v29 ; GFX10-NEXT: v_and_b32_e32 v30, 1, v30 ; GFX10-NEXT: v_and_b32_e32 v28, 1, v28 ; GFX10-NEXT: v_and_b32_e32 v26, 1, v26 ; GFX10-NEXT: v_and_b32_e32 v24, 1, v24 -; GFX10-NEXT: v_writelane_b32 v31, s31, 1 ; GFX10-NEXT: v_and_b32_e32 v22, 1, v22 ; GFX10-NEXT: v_and_b32_e32 v20, 1, v20 -; GFX10-NEXT: v_and_b32_e32 v17, 1, v17 -; GFX10-NEXT: v_and_b32_e32 v9, 1, v9 -; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 -; GFX10-NEXT: v_writelane_b32 v31, s34, 2 -; GFX10-NEXT: v_and_b32_e32 v29, 1, v29 -; GFX10-NEXT: v_and_b32_e32 v27, 1, v27 -; GFX10-NEXT: v_and_b32_e32 v25, 1, v25 -; GFX10-NEXT: v_and_b32_e32 v23, 1, v23 -; GFX10-NEXT: v_and_b32_e32 v21, 1, v21 -; GFX10-NEXT: v_and_b32_e32 v19, 1, v19 ; GFX10-NEXT: v_and_b32_e32 v18, 1, v18 -; GFX10-NEXT: v_and_b32_e32 v15, 1, v15 -; GFX10-NEXT: v_and_b32_e32 v13, 1, v13 -; GFX10-NEXT: v_and_b32_e32 v11, 1, v11 +; GFX10-NEXT: v_and_b32_e32 v16, 1, v16 +; GFX10-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX10-NEXT: v_and_b32_e32 v12, 1, v12 +; GFX10-NEXT: s_clause 0x14 +; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60 +; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:124 +; GFX10-NEXT: buffer_load_ushort v34, off, s[0:3], s32 +; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:128 +; GFX10-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:64 +; GFX10-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:48 +; GFX10-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:116 +; GFX10-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:52 +; GFX10-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:120 +; GFX10-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:56 +; GFX10-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32 +; GFX10-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:100 +; GFX10-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:36 +; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:104 +; GFX10-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:40 +; GFX10-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:108 +; GFX10-NEXT: buffer_load_dword v64, off, s[0:3], s32 offset:44 +; GFX10-NEXT: buffer_load_dword v65, off, s[0:3], s32 offset:112 +; GFX10-NEXT: buffer_load_dword v66, off, s[0:3], s32 offset:72 +; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:76 +; GFX10-NEXT: buffer_load_dword v68, off, s[0:3], s32 offset:80 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29 +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:92 +; GFX10-NEXT: buffer_load_dword v69, off, s[0:3], s32 offset:28 +; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v30 +; GFX10-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 +; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v28 +; GFX10-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 +; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v26 +; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v24 +; GFX10-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 +; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v22 +; GFX10-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:20 +; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v20 +; GFX10-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:16 +; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v18 +; GFX10-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:12 +; GFX10-NEXT: v_cmp_eq_u32_e64 s11, 1, v16 +; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:8 +; GFX10-NEXT: v_cmp_eq_u32_e64 s12, 1, v14 +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:68 +; GFX10-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:24 +; GFX10-NEXT: v_cmp_eq_u32_e64 s13, 1, v12 +; GFX10-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:4 +; GFX10-NEXT: v_writelane_b32 v31, s30, 0 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX10-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX10-NEXT: v_writelane_b32 v31, s31, 1 +; GFX10-NEXT: v_and_b32_e32 v8, 1, v8 +; GFX10-NEXT: v_and_b32_e32 v10, 1, v10 +; GFX10-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX10-NEXT: v_writelane_b32 v31, s34, 2 ; GFX10-NEXT: v_and_b32_e32 v5, 1, v5 -; GFX10-NEXT: v_cmp_eq_u32_e64 s15, 1, v20 -; GFX10-NEXT: v_cmp_eq_u32_e64 s16, 1, v22 -; GFX10-NEXT: v_cmp_eq_u32_e64 s17, 1, v24 -; GFX10-NEXT: v_cmp_eq_u32_e64 s18, 1, v26 -; GFX10-NEXT: v_cmp_eq_u32_e64 s19, 1, v28 -; GFX10-NEXT: v_cmp_eq_u32_e64 s20, 1, v30 -; GFX10-NEXT: v_cmp_eq_u32_e64 s22, 1, v7 -; GFX10-NEXT: v_cmp_eq_u32_e64 s23, 1, v9 -; GFX10-NEXT: v_cmp_eq_u32_e64 s27, 1, v17 +; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 +; GFX10-NEXT: v_and_b32_e32 v9, 1, v9 +; GFX10-NEXT: v_and_b32_e32 v11, 1, v11 +; GFX10-NEXT: v_and_b32_e32 v13, 1, v13 +; GFX10-NEXT: v_and_b32_e32 v15, 1, v15 +; GFX10-NEXT: v_and_b32_e32 v17, 1, v17 +; GFX10-NEXT: v_and_b32_e32 v19, 1, v19 +; GFX10-NEXT: v_and_b32_e32 v21, 1, v21 +; GFX10-NEXT: v_and_b32_e32 v23, 1, v23 +; GFX10-NEXT: v_and_b32_e32 v25, 1, v25 +; GFX10-NEXT: v_and_b32_e32 v27, 1, v27 +; GFX10-NEXT: v_cmp_eq_u32_e64 s14, 1, v10 +; GFX10-NEXT: v_cmp_eq_u32_e64 s15, 1, v8 +; GFX10-NEXT: v_cmp_eq_u32_e64 s16, 1, v6 +; GFX10-NEXT: v_cmp_eq_u32_e64 s17, 1, v4 +; GFX10-NEXT: v_cmp_eq_u32_e64 s18, 1, v2 +; GFX10-NEXT: v_cmp_eq_u32_e64 s19, 1, v0 ; GFX10-NEXT: v_writelane_b32 v31, s35, 3 -; GFX10-NEXT: v_cmp_eq_u32_e64 s14, 1, v18 -; GFX10-NEXT: v_cmp_eq_u32_e64 s21, 1, v5 -; GFX10-NEXT: v_cmp_eq_u32_e64 s24, 1, v11 -; GFX10-NEXT: v_cmp_eq_u32_e64 s25, 1, v13 +; GFX10-NEXT: v_cmp_eq_u32_e64 s20, 1, v27 +; GFX10-NEXT: v_cmp_eq_u32_e64 s21, 1, v25 +; GFX10-NEXT: v_cmp_eq_u32_e64 s22, 1, v23 +; GFX10-NEXT: v_cmp_eq_u32_e64 s23, 1, v21 +; GFX10-NEXT: v_cmp_eq_u32_e64 s24, 1, v19 +; GFX10-NEXT: v_cmp_eq_u32_e64 s25, 1, v17 ; GFX10-NEXT: v_cmp_eq_u32_e64 s26, 1, v15 -; GFX10-NEXT: v_cmp_eq_u32_e64 s28, 1, v19 -; GFX10-NEXT: v_cmp_eq_u32_e64 s29, 1, v21 -; GFX10-NEXT: v_cmp_eq_u32_e64 s30, 1, v23 -; GFX10-NEXT: v_cmp_eq_u32_e64 s31, 1, v25 -; GFX10-NEXT: v_cmp_eq_u32_e64 s34, 1, v27 -; GFX10-NEXT: v_cmp_eq_u32_e64 s35, 1, v29 +; GFX10-NEXT: v_cmp_eq_u32_e64 s27, 1, v13 +; GFX10-NEXT: v_cmp_eq_u32_e64 s28, 1, v11 +; GFX10-NEXT: v_cmp_eq_u32_e64 s29, 1, v7 +; GFX10-NEXT: v_cmp_eq_u32_e64 s30, 1, v3 +; GFX10-NEXT: v_cmp_eq_u32_e64 s31, 1, v1 +; GFX10-NEXT: v_cmp_eq_u32_e64 s34, 1, v5 +; GFX10-NEXT: v_cmp_eq_u32_e64 s35, 1, v9 ; GFX10-NEXT: s_waitcnt vmcnt(32) -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v32 +; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v32 ; GFX10-NEXT: s_waitcnt vmcnt(31) -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v33 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v32, v33, s4 +; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v33 +; GFX10-NEXT: s_waitcnt vmcnt(30) +; GFX10-NEXT: v_and_b32_e32 v2, 1, v34 ; GFX10-NEXT: s_waitcnt vmcnt(29) -; GFX10-NEXT: v_cndmask_b32_e64 v11, v34, v35, s5 +; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v35 ; GFX10-NEXT: s_waitcnt vmcnt(28) -; GFX10-NEXT: v_and_b32_e32 v17, 1, v36 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v35 -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v34 -; GFX10-NEXT: s_waitcnt vmcnt(26) -; GFX10-NEXT: v_cndmask_b32_e64 v18, v37, v38, s7 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v38 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v37 +; GFX10-NEXT: v_cndmask_b32_e64 v15, v35, v36, s4 +; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v36 +; GFX10-NEXT: v_cndmask_b32_e64 v17, v33, v32, s5 +; GFX10-NEXT: s_waitcnt vmcnt(25) +; GFX10-NEXT: v_cndmask_b32_e64 v19, v38, v39, s7 ; GFX10-NEXT: s_waitcnt vmcnt(24) -; GFX10-NEXT: v_cndmask_b32_e64 v21, v39, v48, s8 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v48 -; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v39 -; GFX10-NEXT: s_waitcnt vmcnt(22) -; GFX10-NEXT: v_cndmask_b32_e64 v24, v50, v49, s9 -; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v49 -; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v50 -; GFX10-NEXT: s_waitcnt vmcnt(20) -; GFX10-NEXT: v_cndmask_b32_e64 v27, v51, v52, s10 -; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v52 -; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v51 +; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v48 +; GFX10-NEXT: s_waitcnt vmcnt(23) +; GFX10-NEXT: v_cndmask_b32_e64 v13, v48, v49, s6 +; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v49 +; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v39 +; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v38 +; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v37 ; GFX10-NEXT: s_waitcnt vmcnt(18) -; GFX10-NEXT: v_cndmask_b32_e64 v30, v53, v54, s11 +; GFX10-NEXT: v_cndmask_b32_e64 v27, v53, v54, s10 +; GFX10-NEXT: s_waitcnt vmcnt(17) +; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v55 +; GFX10-NEXT: s_waitcnt vmcnt(16) +; GFX10-NEXT: v_cndmask_b32_e64 v21, v55, v64, s9 +; GFX10-NEXT: s_waitcnt vmcnt(15) +; GFX10-NEXT: v_cndmask_b32_e64 v11, v65, v37, s8 +; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v65 +; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v64 ; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v54 ; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v53 -; GFX10-NEXT: s_waitcnt vmcnt(16) -; GFX10-NEXT: v_cndmask_b32_e64 v34, v55, v64, s12 -; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v64 -; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v55 -; GFX10-NEXT: s_waitcnt vmcnt(12) -; GFX10-NEXT: v_cndmask_b32_e64 v37, v68, v65, s13 -; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v65 -; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v68 -; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v67 -; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v66 +; GFX10-NEXT: v_cndmask_b32_e64 v34, v51, v52, s11 +; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v52 +; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v51 ; GFX10-NEXT: s_waitcnt vmcnt(9) -; GFX10-NEXT: v_cndmask_b32_e64 v52, v0, v2, s16 -; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v37, v30, v50, s12 +; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v50 +; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX10-NEXT: v_cndmask_b32_e64 v39, v29, v69, s13 +; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v69 +; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v29 ; GFX10-NEXT: s_waitcnt vmcnt(6) -; GFX10-NEXT: v_cndmask_b32_e64 v53, v8, v69, s17 -; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v69 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e64 v55, v4, v3, s18 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: s_waitcnt vmcnt(3) -; GFX10-NEXT: v_cndmask_b32_e64 v64, v10, v12, s19 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e64 v51, v1, v6, s15 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e64 v65, v14, v16, s20 +; GFX10-NEXT: v_cndmask_b32_e64 v50, v24, v22, s15 +; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX10-NEXT: s_waitcnt vmcnt(5) +; GFX10-NEXT: v_cndmask_b32_e64 v51, v68, v20, s16 +; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v68 +; GFX10-NEXT: s_waitcnt vmcnt(4) +; GFX10-NEXT: v_cndmask_b32_e64 v53, v67, v18, s17 +; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_cndmask_b32_e64 v49, v28, v26, s14 +; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v67 +; GFX10-NEXT: v_cndmask_b32_e64 v55, v66, v16, s18 ; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v66 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cndmask_b32_e64 v65, v14, v12, s19 +; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 ; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 -; GFX10-NEXT: v_cndmask_b32_e64 v48, v66, v67, s14 -; GFX10-NEXT: v_cndmask_b32_e64 v9, v15, v13, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v13, v20, v19, s21 -; GFX10-NEXT: v_cndmask_b32_e64 v15, v23, v22, s22 -; GFX10-NEXT: v_cndmask_b32_e64 v19, v26, v25, s23 -; GFX10-NEXT: v_cndmask_b32_e64 v20, v29, v28, s24 -; GFX10-NEXT: v_cndmask_b32_e64 v22, v33, v32, s25 -; GFX10-NEXT: v_cndmask_b32_e64 v23, v36, v35, s26 -; GFX10-NEXT: v_cndmask_b32_e64 v25, v39, v38, s27 -; GFX10-NEXT: v_cndmask_b32_e64 v26, v50, v49, s28 -; GFX10-NEXT: v_cndmask_b32_e64 v28, v1, v6, s29 -; GFX10-NEXT: v_cndmask_b32_e64 v17, v0, v2, s30 -; GFX10-NEXT: v_cndmask_b32_e64 v29, v8, v54, s31 -; GFX10-NEXT: v_cndmask_b32_e64 v32, v4, v3, s34 -; GFX10-NEXT: v_cndmask_b32_e64 v33, v10, v12, s35 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v14, v16, vcc_lo -; GFX10-NEXT: v_perm_b32 v0, v7, v5, 0x5040100 -; GFX10-NEXT: v_perm_b32 v1, v9, v11, 0x5040100 -; GFX10-NEXT: v_perm_b32 v2, v13, v18, 0x5040100 -; GFX10-NEXT: v_perm_b32 v3, v15, v21, 0x5040100 -; GFX10-NEXT: v_perm_b32 v4, v19, v24, 0x5040100 -; GFX10-NEXT: v_perm_b32 v5, v20, v27, 0x5040100 -; GFX10-NEXT: v_perm_b32 v6, v22, v30, 0x5040100 -; GFX10-NEXT: v_perm_b32 v7, v23, v34, 0x5040100 -; GFX10-NEXT: v_perm_b32 v8, v25, v37, 0x5040100 -; GFX10-NEXT: v_perm_b32 v9, v26, v48, 0x5040100 -; GFX10-NEXT: v_perm_b32 v10, v28, v51, 0x5040100 -; GFX10-NEXT: v_perm_b32 v11, v17, v52, 0x5040100 -; GFX10-NEXT: v_perm_b32 v12, v29, v53, 0x5040100 -; GFX10-NEXT: v_perm_b32 v13, v32, v55, 0x5040100 -; GFX10-NEXT: v_perm_b32 v14, v33, v64, 0x5040100 -; GFX10-NEXT: v_perm_b32 v15, v16, v65, 0x5040100 +; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v66, v1, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v67, v6, v5, s20 +; GFX10-NEXT: v_cndmask_b32_e64 v68, v8, v7, s21 +; GFX10-NEXT: v_cndmask_b32_e64 v69, v10, v9, s22 +; GFX10-NEXT: v_cndmask_b32_e64 v10, v25, v23, s23 +; GFX10-NEXT: v_cndmask_b32_e64 v9, v33, v32, s24 +; GFX10-NEXT: v_cndmask_b32_e64 v8, v36, v35, s25 +; GFX10-NEXT: v_cndmask_b32_e64 v7, v30, v38, s26 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v29, v48, s27 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v28, v26, s28 +; GFX10-NEXT: v_cndmask_b32_e64 v20, v52, v20, s29 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v14, v12, s31 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v64, v16, s30 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v54, v18, s34 +; GFX10-NEXT: v_cndmask_b32_e64 v12, v24, v22, s35 +; GFX10-NEXT: v_cndmask_b32_e64 v16, v4, v3, s4 +; GFX10-NEXT: v_perm_b32 v0, v0, v65, 0x5040100 +; GFX10-NEXT: v_perm_b32 v1, v1, v55, 0x5040100 +; GFX10-NEXT: v_perm_b32 v2, v2, v53, 0x5040100 +; GFX10-NEXT: v_perm_b32 v3, v20, v51, 0x5040100 +; GFX10-NEXT: v_perm_b32 v4, v12, v50, 0x5040100 +; GFX10-NEXT: v_perm_b32 v5, v5, v49, 0x5040100 +; GFX10-NEXT: v_perm_b32 v6, v6, v39, 0x5040100 +; GFX10-NEXT: v_perm_b32 v7, v7, v37, 0x5040100 +; GFX10-NEXT: v_perm_b32 v8, v8, v34, 0x5040100 +; GFX10-NEXT: v_perm_b32 v9, v9, v27, 0x5040100 +; GFX10-NEXT: v_perm_b32 v10, v10, v21, 0x5040100 +; GFX10-NEXT: v_perm_b32 v11, v69, v11, 0x5040100 +; GFX10-NEXT: v_perm_b32 v12, v68, v19, 0x5040100 +; GFX10-NEXT: v_perm_b32 v13, v67, v13, 0x5040100 +; GFX10-NEXT: v_perm_b32 v14, v66, v17, 0x5040100 +; GFX10-NEXT: v_perm_b32 v15, v16, v15, 0x5040100 ; GFX10-NEXT: v_readlane_b32 s35, v31, 3 ; GFX10-NEXT: v_readlane_b32 s34, v31, 2 ; GFX10-NEXT: v_readlane_b32 s31, v31, 1 @@ -29011,205 +28976,198 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_clause 0x20 ; GFX11-NEXT: scratch_load_u16 v31, off, s32 -; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:124 -; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:64 -; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX11-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX11-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX11-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX11-NEXT: v_and_b32_e32 v8, 1, v8 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_and_b32_e32 v27, 1, v27 -; GFX11-NEXT: v_and_b32_e32 v10, 1, v10 -; GFX11-NEXT: v_and_b32_e32 v12, 1, v12 -; GFX11-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:128 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:124 +; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:120 +; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:116 +; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:112 +; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:108 +; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:104 +; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:100 +; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:96 +; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:92 +; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:88 +; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:84 +; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:80 +; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:76 +; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:4 +; GFX11-NEXT: v_and_b32_e32 v30, 1, v30 +; GFX11-NEXT: v_and_b32_e32 v28, 1, v28 +; GFX11-NEXT: v_and_b32_e32 v26, 1, v26 +; GFX11-NEXT: v_and_b32_e32 v24, 1, v24 +; GFX11-NEXT: v_and_b32_e32 v22, 1, v22 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v30 +; GFX11-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX11-NEXT: v_and_b32_e32 v20, 1, v20 +; GFX11-NEXT: v_and_b32_e32 v18, 1, v18 +; GFX11-NEXT: v_and_b32_e32 v16, 1, v16 ; GFX11-NEXT: s_waitcnt vmcnt(30) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v32, v33, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 -; GFX11-NEXT: v_and_b32_e32 v29, 1, v29 +; GFX11-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28 +; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v33 ; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-NEXT: v_and_b32_e32 v30, 1, v30 +; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: s_waitcnt vmcnt(28) -; GFX11-NEXT: v_cndmask_b32_e32 v2, v34, v35, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 -; GFX11-NEXT: v_and_b32_e32 v23, 1, v23 +; GFX11-NEXT: v_cndmask_b32_e32 v28, v34, v35, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26 +; GFX11-NEXT: v_and_b32_e32 v7, 1, v7 ; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v35 ; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-NEXT: v_and_b32_e32 v28, 1, v28 +; GFX11-NEXT: v_and_b32_e32 v2, 1, v2 ; GFX11-NEXT: s_waitcnt vmcnt(26) -; GFX11-NEXT: v_cndmask_b32_e32 v4, v36, v37, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 -; GFX11-NEXT: v_and_b32_e32 v25, 1, v25 +; GFX11-NEXT: v_cndmask_b32_e32 v26, v36, v37, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24 +; GFX11-NEXT: v_and_b32_e32 v5, 1, v5 ; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v37 ; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-NEXT: v_and_b32_e32 v26, 1, v26 +; GFX11-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX11-NEXT: s_waitcnt vmcnt(24) -; GFX11-NEXT: v_cndmask_b32_e32 v6, v38, v39, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 -; GFX11-NEXT: v_and_b32_e32 v19, 1, v19 +; GFX11-NEXT: v_cndmask_b32_e32 v24, v38, v39, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22 +; GFX11-NEXT: v_and_b32_e32 v11, 1, v11 ; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v39 ; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v38 -; GFX11-NEXT: v_and_b32_e32 v24, 1, v24 +; GFX11-NEXT: v_and_b32_e32 v6, 1, v6 ; GFX11-NEXT: s_waitcnt vmcnt(22) -; GFX11-NEXT: v_cndmask_b32_e32 v8, v48, v49, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 -; GFX11-NEXT: v_and_b32_e32 v21, 1, v21 +; GFX11-NEXT: v_cndmask_b32_e32 v22, v48, v49, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20 +; GFX11-NEXT: v_and_b32_e32 v9, 1, v9 ; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v49 ; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v48 -; GFX11-NEXT: v_and_b32_e32 v22, 1, v22 +; GFX11-NEXT: v_and_b32_e32 v8, 1, v8 ; GFX11-NEXT: s_waitcnt vmcnt(20) -; GFX11-NEXT: v_cndmask_b32_e32 v10, v50, v51, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 +; GFX11-NEXT: v_cndmask_b32_e32 v20, v50, v51, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18 ; GFX11-NEXT: v_and_b32_e32 v15, 1, v15 ; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v51 ; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v50 -; GFX11-NEXT: v_and_b32_e32 v20, 1, v20 +; GFX11-NEXT: v_and_b32_e32 v10, 1, v10 ; GFX11-NEXT: s_waitcnt vmcnt(18) -; GFX11-NEXT: v_cndmask_b32_e32 v12, v52, v53, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 -; GFX11-NEXT: v_and_b32_e32 v17, 1, v17 +; GFX11-NEXT: v_cndmask_b32_e32 v18, v52, v53, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 +; GFX11-NEXT: v_and_b32_e32 v13, 1, v13 ; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v53 ; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v52 -; GFX11-NEXT: v_and_b32_e32 v18, 1, v18 +; GFX11-NEXT: v_and_b32_e32 v12, 1, v12 ; GFX11-NEXT: s_waitcnt vmcnt(16) -; GFX11-NEXT: v_cndmask_b32_e32 v14, v54, v55, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v16, v54, v55, vcc_lo ; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v55 ; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v54 -; GFX11-NEXT: v_and_b32_e32 v16, 1, v16 +; GFX11-NEXT: v_and_b32_e32 v14, 1, v14 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 ; GFX11-NEXT: s_waitcnt vmcnt(14) -; GFX11-NEXT: v_dual_cndmask_b32 v16, v64, v65 :: v_dual_and_b32 v11, 1, v11 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18 -; GFX11-NEXT: v_and_b32_e32 v13, 1, v13 +; GFX11-NEXT: v_dual_cndmask_b32 v14, v64, v65 :: v_dual_and_b32 v19, 1, v19 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 +; GFX11-NEXT: v_and_b32_e32 v17, 1, v17 ; GFX11-NEXT: v_lshrrev_b32_e32 v65, 16, v65 ; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v64 ; GFX11-NEXT: s_waitcnt vmcnt(12) -; GFX11-NEXT: v_cndmask_b32_e32 v18, v66, v67, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20 -; GFX11-NEXT: v_and_b32_e32 v7, 1, v7 +; GFX11-NEXT: v_cndmask_b32_e32 v12, v66, v67, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 +; GFX11-NEXT: v_and_b32_e32 v23, 1, v23 ; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v67 ; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v66 ; GFX11-NEXT: s_waitcnt vmcnt(10) -; GFX11-NEXT: v_cndmask_b32_e32 v20, v68, v69, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22 -; GFX11-NEXT: v_and_b32_e32 v9, 1, v9 +; GFX11-NEXT: v_cndmask_b32_e32 v10, v68, v69, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 +; GFX11-NEXT: v_and_b32_e32 v21, 1, v21 ; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v69 ; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v68 ; GFX11-NEXT: s_waitcnt vmcnt(8) -; GFX11-NEXT: v_cndmask_b32_e32 v22, v70, v71, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24 -; GFX11-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX11-NEXT: v_cndmask_b32_e32 v8, v70, v71, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 +; GFX11-NEXT: v_and_b32_e32 v27, 1, v27 ; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v71 ; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v70 ; GFX11-NEXT: s_waitcnt vmcnt(6) -; GFX11-NEXT: v_cndmask_b32_e32 v24, v80, v81, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26 -; GFX11-NEXT: v_and_b32_e32 v5, 1, v5 +; GFX11-NEXT: v_cndmask_b32_e32 v6, v80, v81, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 +; GFX11-NEXT: v_and_b32_e32 v25, 1, v25 ; GFX11-NEXT: v_lshrrev_b32_e32 v81, 16, v81 ; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v80 ; GFX11-NEXT: s_waitcnt vmcnt(4) -; GFX11-NEXT: v_cndmask_b32_e32 v26, v82, v83, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28 +; GFX11-NEXT: v_cndmask_b32_e32 v4, v82, v83, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 ; GFX11-NEXT: v_and_b32_e32 v31, 1, v31 ; GFX11-NEXT: v_lshrrev_b32_e32 v83, 16, v83 ; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v82 ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_cndmask_b32_e32 v28, v84, v85, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v30 -; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX11-NEXT: v_cndmask_b32_e32 v2, v84, v85, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_and_b32_e32 v29, 1, v29 ; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v85 ; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v84 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v30, v86, v87, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX11-NEXT: v_cndmask_b32_e32 v0, v86, v87, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v31 ; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v87 ; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v86 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29 +; GFX11-NEXT: v_cndmask_b32_e32 v29, v34, v35, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27 +; GFX11-NEXT: v_cndmask_b32_e32 v27, v36, v37, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25 +; GFX11-NEXT: v_cndmask_b32_e32 v25, v38, v39, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23 +; GFX11-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21 +; GFX11-NEXT: v_cndmask_b32_e32 v21, v50, v51, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19 +; GFX11-NEXT: v_cndmask_b32_e32 v19, v52, v53, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 +; GFX11-NEXT: v_cndmask_b32_e32 v17, v54, v55, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 +; GFX11-NEXT: v_cndmask_b32_e32 v15, v64, v65, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 +; GFX11-NEXT: v_cndmask_b32_e32 v13, v66, v67, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 +; GFX11-NEXT: v_cndmask_b32_e32 v11, v68, v69, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 +; GFX11-NEXT: v_cndmask_b32_e32 v7, v80, v81, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v34, v35, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, v84, v85, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX11-NEXT: v_cndmask_b32_e32 v1, v86, v87, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 -; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v36, v37, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v38, v39, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v5, v82, v83, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 +; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 ; GFX11-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v48, v49, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v11, v50, v51, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 -; GFX11-NEXT: v_perm_b32 v5, v11, v10, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v13, v52, v53, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v6, v13, v12, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v54, v55, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 +; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v9, v70, v71, vcc_lo +; GFX11-NEXT: v_perm_b32 v5, v11, v10, 0x5040100 ; GFX11-NEXT: v_perm_b32 v7, v15, v14, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v17, v64, v65, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_perm_b32 v8, v17, v16, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v19, v66, v67, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21 -; GFX11-NEXT: v_perm_b32 v9, v19, v18, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v21, v68, v69, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v10, v21, v20, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v23, v70, v71, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25 ; GFX11-NEXT: v_perm_b32 v11, v23, v22, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v25, v80, v81, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 +; GFX11-NEXT: v_perm_b32 v8, v17, v16, 0x5040100 +; GFX11-NEXT: v_perm_b32 v9, v19, v18, 0x5040100 ; GFX11-NEXT: v_perm_b32 v12, v25, v24, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v27, v82, v83, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29 ; GFX11-NEXT: v_perm_b32 v13, v27, v26, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v29, v84, v85, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v31 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v14, v29, v28, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v31, v86, v87, vcc_lo ; GFX11-NEXT: v_perm_b32 v15, v31, v30, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] %op = select <32 x i1> %cond, <32 x bfloat> %a, <32 x bfloat> %b -- GitLab From 4f68ee36fc80212fe5d31085ac2d8503630d99cc Mon Sep 17 00:00:00 2001 From: hstk30-hw Date: Tue, 9 Jan 2024 19:04:29 +0800 Subject: [PATCH 181/652] [ARM] arm_acle.h add Coprocessor Instrinsics (#75440) https://github.com/llvm/llvm-project/issues/75424 Add Coprocessor Instrinsics --- clang/lib/Basic/Targets/ARM.cpp | 64 +++ clang/lib/Basic/Targets/ARM.h | 13 + clang/lib/Headers/arm_acle.h | 59 +++ clang/test/CodeGen/arm-acle-coproc.c | 383 ++++++++++++++++++ .../Preprocessor/aarch64-target-features.c | 1 + 5 files changed, 520 insertions(+) create mode 100644 clang/test/CodeGen/arm-acle-coproc.c diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index 01f9e844da12..a72bd42bad41 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -17,6 +17,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" +#include "llvm/TargetParser/ARMTargetParser.h" using namespace clang; using namespace clang::targets; @@ -837,6 +838,69 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, if (Opts.RWPI) Builder.defineMacro("__ARM_RWPI", "1"); + // Macros for enabling co-proc intrinsics + uint64_t FeatureCoprocBF = 0; + switch (ArchKind) { + default: + break; + case llvm::ARM::ArchKind::ARMV4: + case llvm::ARM::ArchKind::ARMV4T: + // Filter __arm_ldcl and __arm_stcl in acle.h + FeatureCoprocBF = isThumb() ? 0 : FEATURE_COPROC_B1; + break; + case llvm::ARM::ArchKind::ARMV5T: + FeatureCoprocBF = isThumb() ? 0 : FEATURE_COPROC_B1 | FEATURE_COPROC_B2; + break; + case llvm::ARM::ArchKind::ARMV5TE: + case llvm::ARM::ArchKind::ARMV5TEJ: + if (!isThumb()) + FeatureCoprocBF = + FEATURE_COPROC_B1 | FEATURE_COPROC_B2 | FEATURE_COPROC_B3; + break; + case llvm::ARM::ArchKind::ARMV6: + case llvm::ARM::ArchKind::ARMV6K: + case llvm::ARM::ArchKind::ARMV6KZ: + case llvm::ARM::ArchKind::ARMV6T2: + if (!isThumb() || ArchKind == llvm::ARM::ArchKind::ARMV6T2) + FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B2 | + FEATURE_COPROC_B3 | FEATURE_COPROC_B4; + break; + case llvm::ARM::ArchKind::ARMV7A: + case llvm::ARM::ArchKind::ARMV7R: + case llvm::ARM::ArchKind::ARMV7M: + case llvm::ARM::ArchKind::ARMV7S: + case llvm::ARM::ArchKind::ARMV7EM: + FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B2 | + FEATURE_COPROC_B3 | FEATURE_COPROC_B4; + break; + case llvm::ARM::ArchKind::ARMV8A: + case llvm::ARM::ArchKind::ARMV8R: + case llvm::ARM::ArchKind::ARMV8_1A: + case llvm::ARM::ArchKind::ARMV8_2A: + case llvm::ARM::ArchKind::ARMV8_3A: + case llvm::ARM::ArchKind::ARMV8_4A: + case llvm::ARM::ArchKind::ARMV8_5A: + case llvm::ARM::ArchKind::ARMV8_6A: + case llvm::ARM::ArchKind::ARMV8_7A: + case llvm::ARM::ArchKind::ARMV8_8A: + case llvm::ARM::ArchKind::ARMV8_9A: + case llvm::ARM::ArchKind::ARMV9A: + case llvm::ARM::ArchKind::ARMV9_1A: + case llvm::ARM::ArchKind::ARMV9_2A: + case llvm::ARM::ArchKind::ARMV9_3A: + case llvm::ARM::ArchKind::ARMV9_4A: + // Filter __arm_cdp, __arm_ldcl, __arm_stcl in arm_acle.h + FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B3; + break; + case llvm::ARM::ArchKind::ARMV8MMainline: + case llvm::ARM::ArchKind::ARMV8_1MMainline: + FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B2 | + FEATURE_COPROC_B3 | FEATURE_COPROC_B4; + break; + } + Builder.defineMacro("__ARM_FEATURE_COPROC", + "0x" + Twine::utohexstr(FeatureCoprocBF)); + if (ArchKind == llvm::ARM::ArchKind::XSCALE) Builder.defineMacro("__XSCALE__"); diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h index b1aa2794c7e4..9802eb01abf3 100644 --- a/clang/lib/Basic/Targets/ARM.h +++ b/clang/lib/Basic/Targets/ARM.h @@ -100,6 +100,19 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo { }; uint32_t HW_FP; + enum { + /// __arm_cdp __arm_ldc, __arm_ldcl, __arm_stc, + /// __arm_stcl, __arm_mcr and __arm_mrc + FEATURE_COPROC_B1 = (1 << 0), + /// __arm_cdp2, __arm_ldc2, __arm_stc2, __arm_ldc2l, + /// __arm_stc2l, __arm_mcr2 and __arm_mrc2 + FEATURE_COPROC_B2 = (1 << 1), + /// __arm_mcrr, __arm_mrrc + FEATURE_COPROC_B3 = (1 << 2), + /// __arm_mcrr2, __arm_mrrc2 + FEATURE_COPROC_B4 = (1 << 3), + }; + void setABIAAPCS(); void setABIAPCS(bool IsAAPCS16); diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h index 61d80258d166..9aae2285aeb1 100644 --- a/clang/lib/Headers/arm_acle.h +++ b/clang/lib/Headers/arm_acle.h @@ -756,6 +756,65 @@ __arm_st64bv0(void *__addr, data512_t __value) { __builtin_arm_mops_memset_tag(__tagged_address, __value, __size) #endif +/* Coprocessor Intrinsics */ +#if defined(__ARM_FEATURE_COPROC) + +#if (__ARM_FEATURE_COPROC & 0x1) + +#if (__ARM_ARCH < 8) +#define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) \ + __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) +#endif /* __ARM_ARCH < 8 */ + +#define __arm_ldc(coproc, CRd, p) __builtin_arm_ldc(coproc, CRd, p) +#define __arm_stc(coproc, CRd, p) __builtin_arm_stc(coproc, CRd, p) + +#define __arm_mcr(coproc, opc1, value, CRn, CRm, opc2) \ + __builtin_arm_mcr(coproc, opc1, value, CRn, CRm, opc2) +#define __arm_mrc(coproc, opc1, CRn, CRm, opc2) \ + __builtin_arm_mrc(coproc, opc1, CRn, CRm, opc2) + +#if (__ARM_ARCH != 4) && (__ARM_ARCH < 8) +#define __arm_ldcl(coproc, CRd, p) __builtin_arm_ldcl(coproc, CRd, p) +#define __arm_stcl(coproc, CRd, p) __builtin_arm_stcl(coproc, CRd, p) +#endif /* (__ARM_ARCH != 4) && (__ARM_ARCH != 8) */ + +#if (__ARM_ARCH_8M_MAIN__) || (__ARM_ARCH_8_1M_MAIN__) +#define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) \ + __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) +#define __arm_ldcl(coproc, CRd, p) __builtin_arm_ldcl(coproc, CRd, p) +#define __arm_stcl(coproc, CRd, p) __builtin_arm_stcl(coproc, CRd, p) +#endif /* ___ARM_ARCH_8M_MAIN__ */ + +#endif /* __ARM_FEATURE_COPROC & 0x1 */ + +#if (__ARM_FEATURE_COPROC & 0x2) +#define __arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2) \ + __builtin_arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2) +#define __arm_ldc2(coproc, CRd, p) __builtin_arm_ldc2(coproc, CRd, p) +#define __arm_stc2(coproc, CRd, p) __builtin_arm_stc2(coproc, CRd, p) +#define __arm_ldc2l(coproc, CRd, p) __builtin_arm_ldc2l(coproc, CRd, p) +#define __arm_stc2l(coproc, CRd, p) __builtin_arm_stc2l(coproc, CRd, p) +#define __arm_mcr2(coproc, opc1, value, CRn, CRm, opc2) \ + __builtin_arm_mcr2(coproc, opc1, value, CRn, CRm, opc2) +#define __arm_mrc2(coproc, opc1, CRn, CRm, opc2) \ + __builtin_arm_mrc2(coproc, opc1, CRn, CRm, opc2) +#endif + +#if (__ARM_FEATURE_COPROC & 0x4) +#define __arm_mcrr(coproc, opc1, value, CRm) \ + __builtin_arm_mcrr(coproc, opc1, value, CRm) +#define __arm_mrrc(coproc, opc1, CRm) __builtin_arm_mrrc(coproc, opc1, CRm) +#endif + +#if (__ARM_FEATURE_COPROC & 0x8) +#define __arm_mcrr2(coproc, opc1, value, CRm) \ + __builtin_arm_mcrr2(coproc, opc1, value, CRm) +#define __arm_mrrc2(coproc, opc1, CRm) __builtin_arm_mrrc2(coproc, opc1, CRm) +#endif + +#endif // __ARM_FEATURE_COPROC + /* Transactional Memory Extension (TME) Intrinsics */ #if defined(__ARM_FEATURE_TME) && __ARM_FEATURE_TME diff --git a/clang/test/CodeGen/arm-acle-coproc.c b/clang/test/CodeGen/arm-acle-coproc.c new file mode 100644 index 000000000000..cf87130932ed --- /dev/null +++ b/clang/test/CodeGen/arm-acle-coproc.c @@ -0,0 +1,383 @@ +// RUN: %clang_cc1 -triple armv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s +// RUN: %clang_cc1 -triple armv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s +// RUN: %clang_cc1 -triple armv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5 %s +// RUN: %clang_cc1 -triple armv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s +// RUN: %clang_cc1 -triple armv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s +// RUN: %clang_cc1 -triple armv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6 %s +// RUN: %clang_cc1 -triple armv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s +// RUN: %clang_cc1 -triple armv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s +// RUN: %clang_cc1 -triple armv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s +// RUN: %clang_cc1 -triple armv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s +// RUN: %clang_cc1 -triple armv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv8.9a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv9a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv9.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv9.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv9.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple armv9.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s +// RUN: %clang_cc1 -triple thumbv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s +// RUN: %clang_cc1 -triple thumbv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-THUMB %s +// RUN: %clang_cc1 -triple thumbv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s +// RUN: %clang_cc1 -triple thumbv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s +// RUN: %clang_cc1 -triple thumbv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s +// RUN: %clang_cc1 -triple thumbv6k %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s +// RUN: %clang_cc1 -triple thumbv6kz %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s +// RUN: %clang_cc1 -triple thumbv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s +// RUN: %clang_cc1 -triple thumbv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s +// RUN: %clang_cc1 -triple thumbv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s +// RUN: %clang_cc1 -triple thumbv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s +// RUN: %clang_cc1 -triple thumbv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8.9a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv9a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv9.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv9.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv9.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv9.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s +// RUN: %clang_cc1 -triple thumbv8m.base %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-BASE %s +// RUN: %clang_cc1 -triple thumbv8m.main %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-MAIN %s +// RUN: %clang_cc1 -triple thumbv8.1m.main %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-MAIN %s + +#include + +void cdp() { + __arm_cdp(1, 2, 3, 4, 5, 6); + // CHECK-LABEL: void cdp() + // CHECK-V4: __builtin_arm_cdp + // CHECK-V4-THUMB-NOT: __builtin_arm_cdp + // CHECK-V5: __builtin_arm_cdp + // CHECK-V5-TE: __builtin_arm_cdp + // CHECK-V5-THUMB-NOT: __builtin_arm_cdp + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_cdp + // CHECK-V6: __builtin_arm_cdp + // CHECK-V6-THUMB-NOT: __builtin_arm_cdp + // CHECK-V6M-NOT: __builtin_arm_cdp + // CHECK-V7: __builtin_arm_cdp + // CHECK-V8-NOT: __builtin_arm_cdp + // CHECK-V8-BASE-NOT: __builtin_arm_cdp + // CHECK-V8-MAIN: __builtin_arm_cdp +} + +void cdp2() { + __arm_cdp2(1, 2, 3, 4, 5, 6); + // CHECK-LABEL: void cdp2() + // CHECK-V4-NOT: __builtin_arm_cdp2 + // CHECK-V4-THUMB-NOT: __builtin_arm_cdp2 + // CHECK-V5: __builtin_arm_cdp2 + // CHECK-V5-TE: __builtin_arm_cdp2 + // CHECK-V5-THUMB-NOT: __builtin_arm_cdp2 + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_cdp2 + // CHECK-V6: __builtin_arm_cdp2 + // CHECK-V6-THUMB-NOT: __builtin_arm_cdp2 + // CHECK-V6M-NOT: __builtin_arm_cdp2 + // CHECK-V7: __builtin_arm_cdp2 + // CHECK-V8-NOT: __builtin_arm_cdp2 + // CHECK-V8-BASE-NOT: __builtin_arm_cdp2 + // CHECK-V8-MAIN: __builtin_arm_cdp2 +} + +void ldc(int i) { + __arm_ldc(1, 2, &i); + // CHECK-LABEL: void ldc() + // CHECK-V4: __builtin_arm_ldc + // CHECK-V4-THUMB-NOT: __builtin_arm_ldc + // CHECK-V5: __builtin_arm_ldc + // CHECK-V5-TE: __builtin_arm_ldc + // CHECK-V5-THUMB-NOT: __builtin_arm_ldc + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_ldc + // CHECK-V6: __builtin_arm_ldc + // CHECK-V6-THUMB-NOT: __builtin_arm_ldc + // CHECK-V6M-NOT: __builtin_arm_ldc + // CHECK-V7: __builtin_arm_ldc + // CHECK-V8: __builtin_arm_ldc + // CHECK-V8-BASE-NOT: __builtin_arm_ldc + // CHECK-V8-MAIN: __builtin_arm_ldc +} + +void ldcl(int i) { + __arm_ldcl(1, 2, &i); + // CHECK-LABEL: void ldcl() + // CHECK-V4-NOT: __builtin_arm_ldcl + // CHECK-V4-THUMB-NOT: __builtin_arm_ldcl + // CHECK-V5: __builtin_arm_ldcl + // CHECK-V5-TE: __builtin_arm_ldcl + // CHECK-V5-THUMB-NOT: __builtin_arm_ldcl + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_ldcl + // CHECK-V6: __builtin_arm_ldcl + // CHECK-V6-THUMB-NOT: __builtin_arm_ldcl + // CHECK-V6M-NOT: __builtin_arm_ldcl + // CHECK-V7: __builtin_arm_ldcl + // CHECK-V8-NOT: __builtin_arm_ldcl + // CHECK-V8-BASE-NOT: __builtin_arm_ldcl + // CHECK-V8-MAIN: __builtin_arm_ldcl +} + +void ldc2(int i) { + __arm_ldc2(1, 2, &i); + // CHECK-LABEL: void ldc2() + // CHECK-V4-NOT: __builtin_arm_ldc2 + // CHECK-V4-THUMB-NOT: __builtin_arm_ldc2 + // CHECK-V5: __builtin_arm_ldc2 + // CHECK-V5-TE: __builtin_arm_ldc2 + // CHECK-V5-THUMB-NOT: __builtin_arm_ldc2 + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_ldc2 + // CHECK-V6: __builtin_arm_ldc2 + // CHECK-V6-THUMB-NOT: __builtin_arm_ldc2 + // CHECK-V6M-NOT: __builtin_arm_ldc2 + // CHECK-V7: __builtin_arm_ldc2 + // CHECK-V8-NOT: __builtin_arm_ldc2 + // CHECK-V8-BASE-NOT: __builtin_arm_ldc2 + // CHECK-V8-MAIN: __builtin_arm_ldc2 +} + +void ldc2l(int i) { + __arm_ldc2l(1, 2, &i); + // CHECK-LABEL: void ldc2l() + // CHECK-V4-NOT: __builtin_arm_ldc2l + // CHECK-V4-THUMB-NOT: __builtin_arm_ldc2l + // CHECK-V5: __builtin_arm_ldc2l + // CHECK-V5-TE: __builtin_arm_ldc2l + // CHECK-V5-THUMB-NOT: __builtin_arm_ldc2l + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_ldc2l + // CHECK-V6: __builtin_arm_ldc2l + // CHECK-V6-THUMB-NOT: __builtin_arm_ldc2l + // CHECK-V6M-NOT: __builtin_arm_ldc2l + // CHECK-V7: __builtin_arm_ldc2l + // CHECK-V8-NOT: __builtin_arm_ldc2l + // CHECK-V8-BASE-NOT: __builtin_arm_ldc2l + // CHECK-V8-MAIN: __builtin_arm_ldc2l +} + +void stc(int i) { + __arm_stc(1, 2, &i); + // CHECK-LABEL: void stc() + // CHECK-V4: __builtin_arm_stc + // CHECK-V4-THUMB-NOT: __builtin_arm_stc + // CHECK-V5: __builtin_arm_stc + // CHECK-V5-TE: __builtin_arm_stc + // CHECK-V5-THUMB-NOT: __builtin_arm_stc + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_stc + // CHECK-V6: __builtin_arm_stc + // CHECK-V6-THUMB-NOT: __builtin_arm_stc + // CHECK-V6M-NOT: __builtin_arm_stc + // CHECK-V7: __builtin_arm_stc + // CHECK-V8: __builtin_arm_stc + // CHECK-V8-BASE-NOT: __builtin_arm_stc + // CHECK-V8-MAIN: __builtin_arm_stc +} + +void stcl(int i) { + __arm_stcl(1, 2, &i); + // CHECK-LABEL: void stcl() + // CHECK-V4-NOT: __builtin_arm_stcl + // CHECK-V4-THUMB-NOT: __builtin_arm_stcl + // CHECK-V5: __builtin_arm_stcl + // CHECK-V5-TE: __builtin_arm_stcl + // CHECK-V5-THUMB-NOT: __builtin_arm_stcl + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_stcl + // CHECK-V6: __builtin_arm_stcl + // CHECK-V6-THUMB-NOT: __builtin_arm_stcl + // CHECK-V6M-NOT: __builtin_arm_stcl + // CHECK-V7: __builtin_arm_stcl + // CHECK-V8-NOT: __builtin_arm_stcl + // CHECK-V8-BASE-NOT: __builtin_arm_stcl + // CHECK-V8-MAIN: __builtin_arm_stcl +} + +void stc2(int i) { + __arm_stc2(1, 2, &i); + // CHECK-LABEL: void stc2() + // CHECK-V4-NOT: __builtin_arm_stc2 + // CHECK-V4-THUMB-NOT: __builtin_arm_stc2 + // CHECK-V5: __builtin_arm_stc2 + // CHECK-V5-TE: __builtin_arm_stc2 + // CHECK-V5-THUMB-NOT: __builtin_arm_stc2 + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_stc2 + // CHECK-V6: __builtin_arm_stc2 + // CHECK-V6-THUMB-NOT: __builtin_arm_stc2 + // CHECK-V6M-NOT: __builtin_arm_stc2 + // CHECK-V7: __builtin_arm_stc2 + // CHECK-V8-NOT: __builtin_arm_stc2 + // CHECK-V8-BASE-NOT: __builtin_arm_stc2 + // CHECK-V8-MAIN: __builtin_arm_stc2 +} + +void stc2l(int i) { + __arm_stc2l(1, 2, &i); + // CHECK-LABEL: void stc2l() + // CHECK-V4-NOT: __builtin_arm_stc2l + // CHECK-V4-THUMB-NOT: __builtin_arm_stc2l + // CHECK-V5: __builtin_arm_stc2l + // CHECK-V5-TE: __builtin_arm_stc2l + // CHECK-V5-THUMB-NOT: __builtin_arm_stc2l + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_stc2l + // CHECK-V6: __builtin_arm_stc2l + // CHECK-V6-THUMB-NOT: __builtin_arm_stc2l + // CHECK-V6M-NOT: __builtin_arm_stc2l + // CHECK-V7: __builtin_arm_stc2l + // CHECK-V8-NOT: __builtin_arm_stc2l + // CHECK-V8-BASE-NOT: __builtin_arm_stc2l + // CHECK-V8-MAIN: __builtin_arm_stc2l +} + +void mcr() { + __arm_mcr(1, 2, 3, 4, 5, 6); + // CHECK-LABEL: void mcr() + // CHECK-V4: __builtin_arm_mcr + // CHECK-V4-THUMB-NOT: __builtin_arm_mcr + // CHECK-V5: __builtin_arm_mcr + // CHECK-V5-TE: __builtin_arm_mcr + // CHECK-V5-THUMB-NOT: __builtin_arm_mcr + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_mcr + // CHECK-V6: __builtin_arm_mcr + // CHECK-V6-THUMB-NOT: __builtin_arm_mcr + // CHECK-V6M-NOT: __builtin_arm_mcr + // CHECK-V7: __builtin_arm_mcr + // CHECK-V8: __builtin_arm_mcr + // CHECK-V8-BASE-NOT: __builtin_arm_mcr + // CHECK-V8-MAIN: __builtin_arm_mcr +} + +void mcr2() { + __arm_mcr2(1, 2, 3, 4, 5, 6); + // CHECK-LABEL: void mcr2() + // CHECK-V4-NOT: __builtin_arm_mcr2 + // CHECK-V4-THUMB-NOT: __builtin_arm_mcr2 + // CHECK-V5: __builtin_arm_mcr2 + // CHECK-V5-TE: __builtin_arm_mcr2 + // CHECK-V5-THUMB-NOT: __builtin_arm_mcr2 + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_mcr2 + // CHECK-V6: __builtin_arm_mcr2 + // CHECK-V6-THUMB-NOT: __builtin_arm_mcr2 + // CHECK-V6M-NOT: __builtin_arm_mcr2 + // CHECK-V7: __builtin_arm_mcr2 + // CHECK-V8-NOT: __builtin_arm_mcr2 + // CHECK-V8-BASE-NOT: __builtin_arm_mcr2 + // CHECK-V8-MAIN: __builtin_arm_mcr2 +} + +void mrc() { + __arm_mrc(1, 2, 3, 4, 5); + // CHECK-LABEL: void mrc() + // CHECK-V4: __builtin_arm_mrc + // CHECK-V4-THUMB-NOT: __builtin_arm_mrc + // CHECK-V5: __builtin_arm_mrc + // CHECK-V5-TE: __builtin_arm_mrc + // CHECK-V5-THUMB-NOT: __builtin_arm_mrc + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_mrc + // CHECK-V6: __builtin_arm_mrc + // CHECK-V6-THUMB-NOT: __builtin_arm_mrc + // CHECK-V6M-NOT: __builtin_arm_mrc + // CHECK-V7: __builtin_arm_mrc + // CHECK-V8: __builtin_arm_mrc + // CHECK-V8-BASE-NOT: __builtin_arm_mrc + // CHECK-V8-MAIN: __builtin_arm_mrc +} + +void mrc2() { + __arm_mrc2(1, 2, 3, 4, 5); + // CHECK-LABEL: void mrc2() + // CHECK-V4-NOT: __builtin_arm_mrc2 + // CHECK-V4-THUMB-NOT: __builtin_arm_mrc2 + // CHECK-V5: __builtin_arm_mrc2 + // CHECK-V5-TE: __builtin_arm_mrc2 + // CHECK-V5-THUMB-NOT: __builtin_arm_mrc2 + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_mrc2 + // CHECK-V6: __builtin_arm_mrc2 + // CHECK-V6-THUMB-NOT: __builtin_arm_mrc2 + // CHECK-V6M-NOT: __builtin_arm_mrc2 + // CHECK-V7: __builtin_arm_mrc2 + // CHECK-V8-NOT: __builtin_arm_mrc2 + // CHECK-V8-BASE-NOT: __builtin_arm_mrc2 + // CHECK-V8-MAIN: __builtin_arm_mrc2 +} + +void mcrr() { + __arm_mcrr(1, 2, 3, 4); + // CHECK-LABEL: void mcrr() + // CHECK-V4-NOT: __builtin_arm_mcrr + // CHECK-V4-THUMB-NOT: __builtin_arm_mcrr + // CHECK-V5-NOT: __builtin_arm_mcrr + // CHECK-V5-TE: __builtin_arm_mcrr + // CHECK-V5-THUMB-NOT: __builtin_arm_mcrr + // CHECK-V5-THUMB-NOT: __builtin_arm_mcrr + // CHECK-V6: __builtin_arm_mcrr + // CHECK-V6-THUMB-NOT: __builtin_arm_mcrr + // CHECK-V6M-NOT: __builtin_arm_mcrr + // CHECK-V7: __builtin_arm_mcrr + // CHECK-V8: __builtin_arm_mcrr + // CHECK-V8-BASE-NOT: __builtin_arm_mcrr + // CHECK-V8-MAIN: __builtin_arm_mcrr +} + +void mcrr2() { + __arm_mcrr2(1, 2, 3, 4); + // CHECK-LABEL: void mcrr2() + // CHECK-V4-NOT: __builtin_arm_mcrr2 + // CHECK-V4-THUMB-NOT: __builtin_arm_mcrr2 + // CHECK-V5-NOT: __builtin_arm_mcrr2 + // CHECK-V5-TE-NOT: __builtin_arm_mcrr2 + // CHECK-V5-THUMB-NOT: __builtin_arm_mcrr2 + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_mcrr2 + // CHECK-V6: __builtin_arm_mcrr2 + // CHECK-V6-THUMB-NOT: __builtin_arm_mcrr2 + // CHECK-V6M-NOT: __builtin_arm_mcrr2 + // CHECK-V7: __builtin_arm_mcrr2 + // CHECK-V8-NOT: __builtin_arm_mcrr2 + // CHECK-V8-BASE-NOT: __builtin_arm_mcrr2 + // CHECK-V8-MAIN: __builtin_arm_mcrr2 +} + +void mrrc() { + __arm_mrrc(1, 2, 3); + // CHECK-LABEL: void mrrc() + // CHECK-V4-NOT: __builtin_arm_mrrc + // CHECK-V4-THUMB-NOT: __builtin_arm_mrrc + // CHECK-V5-NOT: __builtin_arm_mrrc + // CHECK-V5-TE: __builtin_arm_mrrc + // CHECK-V5-THUMB-NOT: __builtin_arm_mrrc + // CHECK-V5-THUMB-TE-NOT: __builtin_arm_mrrc + // CHECK-V6: __builtin_arm_mrrc + // CHECK-V6-THUMB-NOT: __builtin_arm_mrrc + // CHECK-V6M-NOT: __builtin_arm_mrrc + // CHECK-V7: __builtin_arm_mrrc + // CHECK-V8: __builtin_arm_mrrc + // CHECK-V8-BASE-NOT: __builtin_arm_mrrc + // CHECK-V8-MAIN: __builtin_arm_mrrc +} + +void mrrc2() { + __arm_mrrc2(1, 2, 3); + // CHECK-LABEL: void mrrc2() + // CHECK-V4-NOT: __builtin_arm_mrrc2 + // CHECK-V4-THUMB-NOT: __builtin_arm_mrrc2 + // CHECK-V5-NOT: __builtin_arm_mrrc2 + // CHECK-V5-TE-NOT: __builtin_arm_mrrc2 + // CHECK-V5-THUMB-NOT: __builtin_arm_mrrc2 + // CHECK-V5-TE-THUMB-NOT: __builtin_arm_mrrc2 + // CHECK-V6: __builtin_arm_mrrc2 + // CHECK-V6-THUMB-NOT: __builtin_arm_mrrc2 + // CHECK-V6M-NOT: __builtin_arm_mrrc2 + // CHECK-V7: __builtin_arm_mrrc2 + // CHECK-V8-NOT: __builtin_arm_mrrc2 + // CHECK-V8-BASE-NOT: __builtin_arm_mrrc2 + // CHECK-V8-MAIN: __builtin_arm_mrrc2 +} diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index b3da54162da0..96c7e39a18af 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -45,6 +45,7 @@ // CHECK-NOT: __ARM_PCS_VFP 1 // CHECK-NOT: __ARM_SIZEOF_MINIMAL_ENUM 1 // CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2 +// CHECK-NOT: __ARM_FEATURE_COPROC // CHECK-NOT: __ARM_FEATURE_SVE // CHECK-NOT: __ARM_FEATURE_DOTPROD // CHECK-NOT: __ARM_FEATURE_PAC_DEFAULT -- GitLab From f9a1d157e5168acefaa2281ef14c3809bc6ee539 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Tue, 9 Jan 2024 19:13:33 +0800 Subject: [PATCH 182/652] [CodeGen] Port `StackProtector` to new pass manager (#75334) The original `StackProtector` is both transform and analysis pass, break it into two passes now. `getAnalysis()` could be now replaced by `FAM.getResult(F)` in new pass system. --- .../include/llvm/CodeGen/CodeGenPassBuilder.h | 3 +- .../llvm/CodeGen/MachinePassRegistry.def | 3 +- llvm/include/llvm/CodeGen/StackProtector.h | 93 +++++++---- llvm/lib/CodeGen/StackProtector.cpp | 154 ++++++++++++------ llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/lib/Passes/PassRegistry.def | 2 + 6 files changed, 176 insertions(+), 80 deletions(-) diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index c52bd41086e1..a1382a5e8e40 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -40,6 +40,7 @@ #include "llvm/CodeGen/SelectOptimize.h" #include "llvm/CodeGen/ShadowStackGCLowering.h" #include "llvm/CodeGen/SjLjEHPrepare.h" +#include "llvm/CodeGen/StackProtector.h" #include "llvm/CodeGen/UnreachableBlockElim.h" #include "llvm/CodeGen/WasmEHPrepare.h" #include "llvm/CodeGen/WinEHPrepare.h" @@ -749,7 +750,7 @@ void CodeGenPassBuilder::addISelPrepare(AddIRPass &addPass) const { // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. addPass(SafeStackPass(&TM)); - addPass(StackProtectorPass()); + addPass(StackProtectorPass(&TM)); if (Opt.PrintISelInput) addPass(PrintFunctionPass(dbgs(), diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index 4ddbb2419abc..cbfd4327da6e 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -34,6 +34,7 @@ MODULE_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ()) #endif FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis, ()) FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) +FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis, ()) FUNCTION_ANALYSIS("targetir", TargetIRAnalysis, (std::move(TM.getTargetIRAnalysis()))) #undef FUNCTION_ANALYSIS @@ -65,6 +66,7 @@ FUNCTION_PASS("safe-stack", SafeStackPass, (TM)) FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass, ()) FUNCTION_PASS("select-optimize", SelectOptimizePass, (TM)) FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass, (TM)) +FUNCTION_PASS("stack-protector", StackProtectorPass, (TM)) FUNCTION_PASS("tlshoist", TLSVariableHoistPass, ()) FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ()) FUNCTION_PASS("verify", VerifierPass, ()) @@ -134,7 +136,6 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, #endif DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ()) -DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ()) #undef DUMMY_FUNCTION_PASS #ifndef DUMMY_MACHINE_MODULE_PASS diff --git a/llvm/include/llvm/CodeGen/StackProtector.h b/llvm/include/llvm/CodeGen/StackProtector.h index 57cb7a1c85ae..91d0b0d5e304 100644 --- a/llvm/include/llvm/CodeGen/StackProtector.h +++ b/llvm/include/llvm/CodeGen/StackProtector.h @@ -19,6 +19,7 @@ #include "llvm/Analysis/DomTreeUpdater.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include "llvm/TargetParser/Triple.h" @@ -30,25 +31,15 @@ class Module; class TargetLoweringBase; class TargetMachine; -class StackProtector : public FunctionPass { -private: +class SSPLayoutInfo { + friend class StackProtectorPass; + friend class SSPLayoutAnalysis; + friend class StackProtector; static constexpr unsigned DefaultSSPBufferSize = 8; /// A mapping of AllocaInsts to their required SSP layout. - using SSPLayoutMap = DenseMap; - - const TargetMachine *TM = nullptr; - - /// TLI - Keep a pointer of a TargetLowering to consult for determining - /// target type sizes. - const TargetLoweringBase *TLI = nullptr; - Triple Trip; - - Function *F = nullptr; - Module *M = nullptr; - - std::optional DTU; + using SSPLayoutMap = + DenseMap; /// Layout - Mapping of allocations to the required SSPLayoutKind. /// StackProtector analysis will update this map when determining if an @@ -59,23 +50,59 @@ private: /// protection when -fstack-protection is used. unsigned SSPBufferSize = DefaultSSPBufferSize; + bool RequireStackProtector = false; + // A prologue is generated. bool HasPrologue = false; // IR checking code is generated. bool HasIRCheck = false; - /// InsertStackProtectors - Insert code into the prologue and epilogue of - /// the function. - /// - /// - The prologue code loads and stores the stack guard onto the stack. - /// - The epilogue checks the value stored in the prologue against the - /// original value. It calls __stack_chk_fail if they differ. - bool InsertStackProtectors(); +public: + // Return true if StackProtector is supposed to be handled by SelectionDAG. + bool shouldEmitSDCheck(const BasicBlock &BB) const; + + void copyToMachineFrameInfo(MachineFrameInfo &MFI) const; +}; + +class SSPLayoutAnalysis : public AnalysisInfoMixin { + friend class AnalysisInfoMixin; + using SSPLayoutMap = SSPLayoutInfo::SSPLayoutMap; + + static AnalysisKey Key; + +public: + using Result = SSPLayoutInfo; + + Result run(Function &F, FunctionAnalysisManager &FAM); - /// CreateFailBB - Create a basic block to jump to when the stack protector - /// check fails. - BasicBlock *CreateFailBB(); + /// Check whether or not \p F needs a stack protector based upon the stack + /// protector level. + static bool requiresStackProtector(Function *F, + SSPLayoutMap *Layout = nullptr); +}; + +class StackProtectorPass : public PassInfoMixin { + const TargetMachine *TM; + +public: + explicit StackProtectorPass(const TargetMachine *TM) : TM(TM) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + +class StackProtector : public FunctionPass { +private: + /// A mapping of AllocaInsts to their required SSP layout. + using SSPLayoutMap = SSPLayoutInfo::SSPLayoutMap; + + const TargetMachine *TM = nullptr; + + Function *F = nullptr; + Module *M = nullptr; + + std::optional DTU; + + SSPLayoutInfo LayoutInfo; public: static char ID; // Pass identification, replacement for typeid. @@ -85,16 +112,22 @@ public: void getAnalysisUsage(AnalysisUsage &AU) const override; // Return true if StackProtector is supposed to be handled by SelectionDAG. - bool shouldEmitSDCheck(const BasicBlock &BB) const; + bool shouldEmitSDCheck(const BasicBlock &BB) const { + return LayoutInfo.shouldEmitSDCheck(BB); + } bool runOnFunction(Function &Fn) override; - void copyToMachineFrameInfo(MachineFrameInfo &MFI) const; + void copyToMachineFrameInfo(MachineFrameInfo &MFI) const { + LayoutInfo.copyToMachineFrameInfo(MFI); + } /// Check whether or not \p F needs a stack protector based upon the stack /// protector level. - static bool requiresStackProtector(Function *F, SSPLayoutMap *Layout = nullptr); - + static bool requiresStackProtector(Function *F, + SSPLayoutMap *Layout = nullptr) { + return SSPLayoutAnalysis::requiresStackProtector(F, Layout); + } }; } // end namespace llvm diff --git a/llvm/lib/CodeGen/StackProtector.cpp b/llvm/lib/CodeGen/StackProtector.cpp index 48dc7cb232e3..fca822a485ca 100644 --- a/llvm/lib/CodeGen/StackProtector.cpp +++ b/llvm/lib/CodeGen/StackProtector.cpp @@ -64,6 +64,90 @@ static cl::opt EnableSelectionDAGSP("enable-selectiondag-sp", static cl::opt DisableCheckNoReturn("disable-check-noreturn-call", cl::init(false), cl::Hidden); +/// InsertStackProtectors - Insert code into the prologue and epilogue of the +/// function. +/// +/// - The prologue code loads and stores the stack guard onto the stack. +/// - The epilogue checks the value stored in the prologue against the original +/// value. It calls __stack_chk_fail if they differ. +static bool InsertStackProtectors(const TargetMachine *TM, Function *F, + DomTreeUpdater *DTU, bool &HasPrologue, + bool &HasIRCheck); + +/// CreateFailBB - Create a basic block to jump to when the stack protector +/// check fails. +static BasicBlock *CreateFailBB(Function *F, const Triple &Trip); + +bool SSPLayoutInfo::shouldEmitSDCheck(const BasicBlock &BB) const { + return HasPrologue && !HasIRCheck && isa(BB.getTerminator()); +} + +void SSPLayoutInfo::copyToMachineFrameInfo(MachineFrameInfo &MFI) const { + if (Layout.empty()) + return; + + for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) { + if (MFI.isDeadObjectIndex(I)) + continue; + + const AllocaInst *AI = MFI.getObjectAllocation(I); + if (!AI) + continue; + + SSPLayoutMap::const_iterator LI = Layout.find(AI); + if (LI == Layout.end()) + continue; + + MFI.setObjectSSPLayout(I, LI->second); + } +} + +SSPLayoutInfo SSPLayoutAnalysis::run(Function &F, + FunctionAnalysisManager &FAM) { + + SSPLayoutInfo Info; + Info.RequireStackProtector = + SSPLayoutAnalysis::requiresStackProtector(&F, &Info.Layout); + Info.SSPBufferSize = F.getFnAttributeAsParsedInteger( + "stack-protector-buffer-size", SSPLayoutInfo::DefaultSSPBufferSize); + return Info; +} + +AnalysisKey SSPLayoutAnalysis::Key; + +PreservedAnalyses StackProtectorPass::run(Function &F, + FunctionAnalysisManager &FAM) { + auto &Info = FAM.getResult(F); + auto *DT = FAM.getCachedResult(F); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); + + if (!Info.RequireStackProtector) + return PreservedAnalyses::all(); + + // TODO(etienneb): Functions with funclets are not correctly supported now. + // Do nothing if this is funclet-based personality. + if (F.hasPersonalityFn()) { + EHPersonality Personality = classifyEHPersonality(F.getPersonalityFn()); + if (isFuncletEHPersonality(Personality)) + return PreservedAnalyses::all(); + } + + ++NumFunProtected; + bool Changed = InsertStackProtectors(TM, &F, DT ? &DTU : nullptr, + Info.HasPrologue, Info.HasIRCheck); +#ifdef EXPENSIVE_CHECKS + assert((!DT || DT->verify(DominatorTree::VerificationLevel::Full)) && + "Failed to maintain validity of domtree!"); +#endif + + if (!Changed) + return PreservedAnalyses::all(); + PreservedAnalyses PA; + PA.preserve(); + PA.preserve(); + return PA; +} + char StackProtector::ID = 0; StackProtector::StackProtector() : FunctionPass(ID) { @@ -90,14 +174,12 @@ bool StackProtector::runOnFunction(Function &Fn) { if (auto *DTWP = getAnalysisIfAvailable()) DTU.emplace(DTWP->getDomTree(), DomTreeUpdater::UpdateStrategy::Lazy); TM = &getAnalysis().getTM(); - Trip = TM->getTargetTriple(); - TLI = TM->getSubtargetImpl(Fn)->getTargetLowering(); - HasPrologue = false; - HasIRCheck = false; - - SSPBufferSize = Fn.getFnAttributeAsParsedInteger( - "stack-protector-buffer-size", DefaultSSPBufferSize); - if (!requiresStackProtector(F, &Layout)) + LayoutInfo.HasPrologue = false; + LayoutInfo.HasIRCheck = false; + + LayoutInfo.SSPBufferSize = Fn.getFnAttributeAsParsedInteger( + "stack-protector-buffer-size", SSPLayoutInfo::DefaultSSPBufferSize); + if (!requiresStackProtector(F, &LayoutInfo.Layout)) return false; // TODO(etienneb): Functions with funclets are not correctly supported now. @@ -109,7 +191,9 @@ bool StackProtector::runOnFunction(Function &Fn) { } ++NumFunProtected; - bool Changed = InsertStackProtectors(); + bool Changed = + InsertStackProtectors(TM, F, DTU ? &*DTU : nullptr, + LayoutInfo.HasPrologue, LayoutInfo.HasIRCheck); #ifdef EXPENSIVE_CHECKS assert((!DTU || DTU->getDomTree().verify(DominatorTree::VerificationLevel::Full)) && @@ -284,7 +368,8 @@ static const CallInst *findStackProtectorIntrinsic(Function &F) { /// functions with aggregates that contain any buffer regardless of type and /// size, and functions that contain stack-based variables that have had their /// address taken. -bool StackProtector::requiresStackProtector(Function *F, SSPLayoutMap *Layout) { +bool SSPLayoutAnalysis::requiresStackProtector(Function *F, + SSPLayoutMap *Layout) { Module *M = F->getParent(); bool Strong = false; bool NeedsProtector = false; @@ -295,7 +380,7 @@ bool StackProtector::requiresStackProtector(Function *F, SSPLayoutMap *Layout) { SmallPtrSet VisitedPHIs; unsigned SSPBufferSize = F->getFnAttributeAsParsedInteger( - "stack-protector-buffer-size", DefaultSSPBufferSize); + "stack-protector-buffer-size", SSPLayoutInfo::DefaultSSPBufferSize); if (F->hasFnAttribute(Attribute::SafeStack)) return false; @@ -460,13 +545,12 @@ static bool CreatePrologue(Function *F, Module *M, Instruction *CheckLoc, return SupportsSelectionDAGSP; } -/// InsertStackProtectors - Insert code into the prologue and epilogue of the -/// function. -/// -/// - The prologue code loads and stores the stack guard onto the stack. -/// - The epilogue checks the value stored in the prologue against the original -/// value. It calls __stack_chk_fail if they differ. -bool StackProtector::InsertStackProtectors() { +bool InsertStackProtectors(const TargetMachine *TM, Function *F, + DomTreeUpdater *DTU, bool &HasPrologue, + bool &HasIRCheck) { + auto *M = F->getParent(); + auto *TLI = TM->getSubtargetImpl(*F)->getTargetLowering(); + // If the target wants to XOR the frame pointer into the guard value, it's // impossible to emit the check in IR, so the target *must* support stack // protection in SDAG. @@ -574,7 +658,7 @@ bool StackProtector::InsertStackProtectors() { // merge pass will merge together all of the various BB into one including // fail BB generated by the stack protector pseudo instruction. if (!FailBB) - FailBB = CreateFailBB(); + FailBB = CreateFailBB(F, TM->getTargetTriple()); IRBuilder<> B(CheckLoc); Value *Guard = getStackGuard(TLI, M, B); @@ -589,8 +673,7 @@ bool StackProtector::InsertStackProtectors() { SuccessProb.getNumerator()); SplitBlockAndInsertIfThen(Cmp, CheckLoc, - /*Unreachable=*/false, Weights, - DTU ? &*DTU : nullptr, + /*Unreachable=*/false, Weights, DTU, /*LI=*/nullptr, /*ThenBlock=*/FailBB); auto *BI = cast(Cmp->getParent()->getTerminator()); @@ -608,9 +691,8 @@ bool StackProtector::InsertStackProtectors() { return HasPrologue; } -/// CreateFailBB - Create a basic block to jump to when the stack protector -/// check fails. -BasicBlock *StackProtector::CreateFailBB() { +BasicBlock *CreateFailBB(Function *F, const Triple &Trip) { + auto *M = F->getParent(); LLVMContext &Context = F->getContext(); BasicBlock *FailBB = BasicBlock::Create(Context, "CallStackCheckFailBlk", F); IRBuilder<> B(FailBB); @@ -633,27 +715,3 @@ BasicBlock *StackProtector::CreateFailBB() { B.CreateUnreachable(); return FailBB; } - -bool StackProtector::shouldEmitSDCheck(const BasicBlock &BB) const { - return HasPrologue && !HasIRCheck && isa(BB.getTerminator()); -} - -void StackProtector::copyToMachineFrameInfo(MachineFrameInfo &MFI) const { - if (Layout.empty()) - return; - - for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) { - if (MFI.isDeadObjectIndex(I)) - continue; - - const AllocaInst *AI = MFI.getObjectAllocation(I); - if (!AI) - continue; - - SSPLayoutMap::const_iterator LI = Layout.find(AI); - if (LI == Layout.end()) - continue; - - MFI.setObjectSSPLayout(I, LI->second); - } -} diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index b4a48e713d05..27bfe12127cc 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -90,6 +90,7 @@ #include "llvm/CodeGen/SelectOptimize.h" #include "llvm/CodeGen/ShadowStackGCLowering.h" #include "llvm/CodeGen/SjLjEHPrepare.h" +#include "llvm/CodeGen/StackProtector.h" #include "llvm/CodeGen/TypePromotion.h" #include "llvm/CodeGen/WasmEHPrepare.h" #include "llvm/CodeGen/WinEHPrepare.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index bceac8374ba9..bda36bd8c107 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -256,6 +256,7 @@ FUNCTION_ANALYSIS("should-not-run-function-passes", ShouldNotRunFunctionPassesAnalysis()) FUNCTION_ANALYSIS("should-run-extra-vector-passes", ShouldRunExtraVectorPasses()) +FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis()) FUNCTION_ANALYSIS("stack-safety-local", StackSafetyAnalysis()) FUNCTION_ANALYSIS("targetir", TM ? TM->getTargetIRAnalysis() : TargetIRAnalysis()) @@ -414,6 +415,7 @@ FUNCTION_PASS("sink", SinkingPass()) FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass(TM)) FUNCTION_PASS("slp-vectorizer", SLPVectorizerPass()) FUNCTION_PASS("slsr", StraightLineStrengthReducePass()) +FUNCTION_PASS("stack-protector", StackProtectorPass(TM)) FUNCTION_PASS("strip-gc-relocates", StripGCRelocates()) FUNCTION_PASS("structurizecfg", StructurizeCFGPass()) FUNCTION_PASS("tailcallelim", TailCallElimPass()) -- GitLab From a529b6eaf05d24518bbe0f0a5539c378252d2671 Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Tue, 9 Jan 2024 19:21:43 +0800 Subject: [PATCH 183/652] [CodeGen] Fix -Wmismatched-tags in StackProtector.h (NFC) llvm-project/llvm/include/llvm/CodeGen/StackProtector.h:69:10: error: class 'AnalysisInfoMixin' was previously declared as a struct; this is valid, but may result in linker errors under the Microsoft C++ ABI [-Werror,-Wmismatched-tags] 69 | friend class AnalysisInfoMixin; | ^ llvm-project/llvm/include/llvm/IR/PassManager.h:414:8: note: previous use is here 414 | struct AnalysisInfoMixin : PassInfoMixin { | ^ llvm-project/llvm/include/llvm/CodeGen/StackProtector.h:69:10: note: did you mean struct here? 69 | friend class AnalysisInfoMixin; | ^~~~~ | struct 1 error generated. --- llvm/include/llvm/CodeGen/StackProtector.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/CodeGen/StackProtector.h b/llvm/include/llvm/CodeGen/StackProtector.h index 91d0b0d5e304..068990f69f2e 100644 --- a/llvm/include/llvm/CodeGen/StackProtector.h +++ b/llvm/include/llvm/CodeGen/StackProtector.h @@ -66,7 +66,7 @@ public: }; class SSPLayoutAnalysis : public AnalysisInfoMixin { - friend class AnalysisInfoMixin; + friend struct AnalysisInfoMixin; using SSPLayoutMap = SSPLayoutInfo::SSPLayoutMap; static AnalysisKey Key; -- GitLab From 839435cc6ccbd84fff20790285af84bdba83778a Mon Sep 17 00:00:00 2001 From: jeanPerier Date: Tue, 9 Jan 2024 12:23:21 +0100 Subject: [PATCH 184/652] [flang] Fix fir::isPolymorphic for TYPE(*) assumed-size arrays (#77339) fir::isPolymorphic was returning false for TYPE(*) assumed-size arrays causing bad fir.rebox to be created when passing a polymorphic actual argument to such TYPE(*) dummy. Fix fir::isAssumedSize to return true for fir.ref> and fir.ref. @cabreraam, I found this bug when testing your patch, although it is not caused by it, so you may hit it when passing TYPE(*) deferred shape of to assumed size TYPE(*) with a different rank. --- .../include/flang/Optimizer/Dialect/FIRType.h | 4 ++- flang/lib/Optimizer/Dialect/FIRType.cpp | 27 +++++++++---------- .../HLFIR/calls-poly-to-assumed-type.f90 | 20 ++++++++++++++ flang/test/Lower/polymorphic.f90 | 4 +-- 4 files changed, 37 insertions(+), 18 deletions(-) create mode 100644 flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 diff --git a/flang/include/flang/Optimizer/Dialect/FIRType.h b/flang/include/flang/Optimizer/Dialect/FIRType.h index ecfa9839617d..8672fcaf60f7 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRType.h +++ b/flang/include/flang/Optimizer/Dialect/FIRType.h @@ -330,7 +330,9 @@ bool isPolymorphicType(mlir::Type ty); /// value. bool isUnlimitedPolymorphicType(mlir::Type ty); -/// Return true iff `ty` is the type of an assumed type. +/// Return true iff `ty` is the type of an assumed type. In FIR, +/// assumed types are of the form `[fir.ref|ptr|heap]fir.box<[fir.array]none>`, +/// or `fir.ref|ptr|heap<[fir.array]none>`. bool isAssumedType(mlir::Type ty); /// Return true iff `ty` is the type of an assumed shape array. diff --git a/flang/lib/Optimizer/Dialect/FIRType.cpp b/flang/lib/Optimizer/Dialect/FIRType.cpp index d0c7bae674b6..110b3a5e0620 100644 --- a/flang/lib/Optimizer/Dialect/FIRType.cpp +++ b/flang/lib/Optimizer/Dialect/FIRType.cpp @@ -302,13 +302,16 @@ bool isScalarBoxedRecordType(mlir::Type ty) { } bool isAssumedType(mlir::Type ty) { - if (auto boxTy = ty.dyn_cast()) { - if (boxTy.getEleTy().isa()) - return true; - if (auto seqTy = boxTy.getEleTy().dyn_cast()) - return seqTy.getEleTy().isa(); - } - return false; + // Rule out CLASS(*) which are `fir.class<[fir.array] none>`. + if (mlir::isa(ty)) + return false; + mlir::Type valueType = fir::unwrapPassByRefType(fir::unwrapRefType(ty)); + // Refuse raw `none` or `fir.array` since assumed type + // should be in memory variables. + if (valueType == ty) + return false; + mlir::Type inner = fir::unwrapSequenceType(valueType); + return mlir::isa(inner); } bool isAssumedShape(mlir::Type ty) { @@ -331,20 +334,16 @@ bool isAllocatableOrPointerArray(mlir::Type ty) { } bool isPolymorphicType(mlir::Type ty) { - if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) - ty = refTy; - // CLASS(*) - if (ty.isa()) + // CLASS(T) or CLASS(*) + if (mlir::isa(fir::unwrapRefType(ty))) return true; // assumed type are polymorphic. return isAssumedType(ty); } bool isUnlimitedPolymorphicType(mlir::Type ty) { - if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) - ty = refTy; // CLASS(*) - if (auto clTy = ty.dyn_cast()) { + if (auto clTy = mlir::dyn_cast(fir::unwrapRefType(ty))) { if (clTy.getEleTy().isa()) return true; mlir::Type innerType = clTy.unwrapInnerType(); diff --git a/flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 b/flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 new file mode 100644 index 000000000000..ffd21e01ef98 --- /dev/null +++ b/flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 @@ -0,0 +1,20 @@ +! Test passing rank 2 CLASS(*) deferred shape to assumed size assumed type +! This requires copy-in/copy-out logic. +! RUN: bbc -emit-hlfir -polymorphic-type -o - %s | FileCheck %s + +subroutine pass_poly_to_assumed_type_assumed_size(x) + class(*), target :: x(:,:) + interface + subroutine assumed_type_assumed_size(x) + type(*), target :: x(*) + end subroutine + end interface + call assumed_type_assumed_size(x) +end subroutine +! CHECK-LABEL: func.func @_QPpass_poly_to_assumed_type_assumed_size( +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpass_poly_to_assumed_type_assumed_sizeEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.class>) -> (!fir.class>, i1) +! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]]#0 : (!fir.class>) -> !fir.ref> +! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref>) -> !fir.ref> +! CHECK: fir.call @_QPassumed_type_assumed_size(%[[VAL_4]]) fastmath : (!fir.ref>) -> () +! CHECK: hlfir.copy_out %[[VAL_2]]#0, %[[VAL_2]]#1 to %[[VAL_1]]#0 : (!fir.class>, i1, !fir.class>) -> () diff --git a/flang/test/Lower/polymorphic.f90 b/flang/test/Lower/polymorphic.f90 index 1770b34d0fe1..a813eff690b7 100644 --- a/flang/test/Lower/polymorphic.f90 +++ b/flang/test/Lower/polymorphic.f90 @@ -839,9 +839,7 @@ module polymorphic_test ! CHECK: %[[IS_ALLOCATED_OR_ASSOCIATED:.*]] = arith.cmpi ne, %[[BOX_ADDR_I64]], %[[C0]] : i64 ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.class ! CHECK: %[[PTR_LOAD2:.*]] = fir.load %[[NULL_PTR]] : !fir.ref>> -! CHECK: %[[BOX_ADDR2:.*]] = fir.box_addr %[[PTR_LOAD2]] : (!fir.box>) -> !fir.ptr -! CHECK: %[[BOX_NONE:.*]] = fir.embox %[[BOX_ADDR2]] : (!fir.ptr) -> !fir.box -! CHECK: %[[CLASS_NONE:.*]] = fir.convert %[[BOX_NONE]] : (!fir.box) -> !fir.class +! CHECK: %[[CLASS_NONE:.*]] = fir.rebox %[[PTR_LOAD2]] : (!fir.box>) -> !fir.class ! CHECK: %[[ARG:.*]] = arith.select %[[IS_ALLOCATED_OR_ASSOCIATED]], %[[CLASS_NONE]], %[[ABSENT]] : !fir.class ! CHECK: fir.call @_QMpolymorphic_testPsub_with_poly_optional(%[[ARG]]) {{.*}} : (!fir.class) -> () -- GitLab From c7148467fc08eefaaae876c7d11d629c849f42cf Mon Sep 17 00:00:00 2001 From: David Sherwood <57997763+david-arm@users.noreply.github.com> Date: Tue, 9 Jan 2024 11:29:28 +0000 Subject: [PATCH 185/652] [AArch64] Add an AArch64 pass for loop idiom transformations (#72273) We have added a new pass that looks for loops such as the following: ``` while (i != max_len) if (a[i] != b[i]) break; ... use index i ... ``` Although similar to a memcmp, this is slightly different because instead of returning the difference between the values of the first non-matching pair of bytes, it returns the index of the first mismatch. As such, we are not able to lower this to a memcmp call. The new pass can now spot such idioms and transform them into a specialised predicated loop that gives a significant performance improvement for AArch64. It is intended as a stop-gap solution until this can be handled by the vectoriser, which doesn't currently deal with early exits. This specialised loop makes use of a generic intrinsic that counts the trailing zero elements in a predicate vector. This was added in https://reviews.llvm.org/D159283 and for SVE we end up with brkb & incp instructions. Although we have added this pass only for AArch64, it was written in a generic way so that in theory it could be used by other targets. Currently the pass requires scalable vector support and needs to know the minimum page size for the target, however it's possible to make it work for fixed-width vectors too. Also, the llvm.experimental.cttz.elts intrinsic used by the pass has generic lowering, but can be made efficient for targets with instructions similar to SVE's brkb, cntp and incp. Original version of patch was posted on Phabricator: https://reviews.llvm.org/D158291 Patch co-authored by Kerry McLaughlin (@kmclaughlin-arm) and David Sherwood (@david-arm) See the original discussion on Discourse: https://discourse.llvm.org/t/aarch64-target-specific-loop-idiom-recognition/72383 --- .../llvm/Analysis/TargetTransformInfo.h | 8 + .../llvm/Analysis/TargetTransformInfoImpl.h | 2 + llvm/lib/Analysis/TargetTransformInfo.cpp | 9 + llvm/lib/Target/AArch64/AArch64.h | 1 + .../AArch64/AArch64LoopIdiomTransform.cpp | 828 +++++++ .../AArch64/AArch64LoopIdiomTransform.h | 25 + .../Target/AArch64/AArch64TargetMachine.cpp | 11 + .../lib/Target/AArch64/AArch64TargetMachine.h | 4 + .../AArch64/AArch64TargetTransformInfo.h | 2 + llvm/lib/Target/AArch64/CMakeLists.txt | 1 + .../LoopIdiom/AArch64/byte-compare-index.ll | 1985 +++++++++++++++++ .../llvm/lib/Target/AArch64/BUILD.gn | 1 + 12 files changed, 2877 insertions(+) create mode 100644 llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp create mode 100644 llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.h create mode 100644 llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 048912beaba5..9697278eaeae 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1174,6 +1174,9 @@ public: /// \return The associativity of the cache level, if available. std::optional getCacheAssociativity(CacheLevel Level) const; + /// \return The minimum architectural page size for the target. + std::optional getMinPageSize() const; + /// \return How much before a load we should place the prefetch /// instruction. This is currently measured in number of /// instructions. @@ -1923,6 +1926,7 @@ public: virtual std::optional getCacheSize(CacheLevel Level) const = 0; virtual std::optional getCacheAssociativity(CacheLevel Level) const = 0; + virtual std::optional getMinPageSize() const = 0; /// \return How much before a load we should place the prefetch /// instruction. This is currently measured in number of @@ -2520,6 +2524,10 @@ public: return Impl.getCacheAssociativity(Level); } + std::optional getMinPageSize() const override { + return Impl.getMinPageSize(); + } + /// Return the preferred prefetch distance in terms of instructions. /// unsigned getPrefetchDistance() const override { diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 2be7256423e4..60eab53fa2f6 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -501,6 +501,8 @@ public: llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); } + std::optional getMinPageSize() const { return {}; } + unsigned getPrefetchDistance() const { return 0; } unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 67246afa2314..a5a18a538d76 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -37,6 +37,10 @@ static cl::opt CacheLineSize( cl::desc("Use this to override the target cache line size when " "specified by the user.")); +static cl::opt MinPageSize( + "min-page-size", cl::init(0), cl::Hidden, + cl::desc("Use this to override the target's minimum page size.")); + static cl::opt PredictableBranchThreshold( "predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc( @@ -762,6 +766,11 @@ TargetTransformInfo::getCacheAssociativity(CacheLevel Level) const { return TTIImpl->getCacheAssociativity(Level); } +std::optional TargetTransformInfo::getMinPageSize() const { + return MinPageSize.getNumOccurrences() > 0 ? MinPageSize + : TTIImpl->getMinPageSize(); +} + unsigned TargetTransformInfo::getPrefetchDistance() const { return TTIImpl->getPrefetchDistance(); } diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h index 901769c54b6e..d20ef63a72e8 100644 --- a/llvm/lib/Target/AArch64/AArch64.h +++ b/llvm/lib/Target/AArch64/AArch64.h @@ -88,6 +88,7 @@ void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&); void initializeAArch64ExpandPseudoPass(PassRegistry &); void initializeAArch64GlobalsTaggingPass(PassRegistry &); void initializeAArch64LoadStoreOptPass(PassRegistry&); +void initializeAArch64LoopIdiomTransformLegacyPassPass(PassRegistry &); void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &); void initializeAArch64MIPeepholeOptPass(PassRegistry &); void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &); diff --git a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp new file mode 100644 index 000000000000..6fcd9c290e9c --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp @@ -0,0 +1,828 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass implements a pass that recognizes certain loop idioms and +// transforms them into more optimized versions of the same loop. In cases +// where this happens, it can be a significant performance win. +// +// We currently only recognize one loop that finds the first mismatched byte +// in an array and returns the index, i.e. something like: +// +// while (++i != n) { +// if (a[i] != b[i]) +// break; +// } +// +// In this example we can actually vectorize the loop despite the early exit, +// although the loop vectorizer does not support it. It requires some extra +// checks to deal with the possibility of faulting loads when crossing page +// boundaries. However, even with these checks it is still profitable to do the +// transformation. +// +//===----------------------------------------------------------------------===// +// +// TODO List: +// +// * Add support for the inverse case where we scan for a matching element. +// * Permit 64-bit induction variable types. +// * Recognize loops that increment the IV *after* comparing bytes. +// * Allow 32-bit sign-extends of the IV used by the GEP. +// +//===----------------------------------------------------------------------===// + +#include "AArch64LoopIdiomTransform.h" +#include "llvm/Analysis/DomTreeUpdater.h" +#include "llvm/Analysis/LoopPass.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/IR/Dominators.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/IR/MDBuilder.h" +#include "llvm/IR/PatternMatch.h" +#include "llvm/InitializePasses.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" + +using namespace llvm; +using namespace PatternMatch; + +#define DEBUG_TYPE "aarch64-loop-idiom-transform" + +static cl::opt + DisableAll("disable-aarch64-lit-all", cl::Hidden, cl::init(true), + cl::desc("Disable AArch64 Loop Idiom Transform Pass.")); + +static cl::opt DisableByteCmp( + "disable-aarch64-lit-bytecmp", cl::Hidden, cl::init(false), + cl::desc("Proceed with AArch64 Loop Idiom Transform Pass, but do " + "not convert byte-compare loop(s).")); + +static cl::opt VerifyLoops( + "aarch64-lit-verify", cl::Hidden, cl::init(false), + cl::desc("Verify loops generated AArch64 Loop Idiom Transform Pass.")); + +namespace llvm { + +void initializeAArch64LoopIdiomTransformLegacyPassPass(PassRegistry &); +Pass *createAArch64LoopIdiomTransformPass(); + +} // end namespace llvm + +namespace { + +class AArch64LoopIdiomTransform { + Loop *CurLoop = nullptr; + DominatorTree *DT; + LoopInfo *LI; + const TargetTransformInfo *TTI; + const DataLayout *DL; + +public: + explicit AArch64LoopIdiomTransform(DominatorTree *DT, LoopInfo *LI, + const TargetTransformInfo *TTI, + const DataLayout *DL) + : DT(DT), LI(LI), TTI(TTI), DL(DL) {} + + bool run(Loop *L); + +private: + /// \name Countable Loop Idiom Handling + /// @{ + + bool runOnCountableLoop(); + bool runOnLoopBlock(BasicBlock *BB, const SCEV *BECount, + SmallVectorImpl &ExitBlocks); + + bool recognizeByteCompare(); + Value *expandFindMismatch(IRBuilder<> &Builder, DomTreeUpdater &DTU, + GetElementPtrInst *GEPA, GetElementPtrInst *GEPB, + Instruction *Index, Value *Start, Value *MaxLen); + void transformByteCompare(GetElementPtrInst *GEPA, GetElementPtrInst *GEPB, + PHINode *IndPhi, Value *MaxLen, Instruction *Index, + Value *Start, bool IncIdx, BasicBlock *FoundBB, + BasicBlock *EndBB); + /// @} +}; + +class AArch64LoopIdiomTransformLegacyPass : public LoopPass { +public: + static char ID; + + explicit AArch64LoopIdiomTransformLegacyPass() : LoopPass(ID) { + initializeAArch64LoopIdiomTransformLegacyPassPass( + *PassRegistry::getPassRegistry()); + } + + StringRef getPassName() const override { + return "Transform AArch64-specific loop idioms"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + } + + bool runOnLoop(Loop *L, LPPassManager &LPM) override; +}; + +bool AArch64LoopIdiomTransformLegacyPass::runOnLoop(Loop *L, + LPPassManager &LPM) { + + if (skipLoop(L)) + return false; + + auto *DT = &getAnalysis().getDomTree(); + auto *LI = &getAnalysis().getLoopInfo(); + auto &TTI = getAnalysis().getTTI( + *L->getHeader()->getParent()); + return AArch64LoopIdiomTransform( + DT, LI, &TTI, &L->getHeader()->getModule()->getDataLayout()) + .run(L); +} + +} // end anonymous namespace + +char AArch64LoopIdiomTransformLegacyPass::ID = 0; + +INITIALIZE_PASS_BEGIN( + AArch64LoopIdiomTransformLegacyPass, "aarch64-lit", + "Transform specific loop idioms into optimized vector forms", false, false) +INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(LoopSimplify) +INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass) +INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass) +INITIALIZE_PASS_END( + AArch64LoopIdiomTransformLegacyPass, "aarch64-lit", + "Transform specific loop idioms into optimized vector forms", false, false) + +Pass *llvm::createAArch64LoopIdiomTransformPass() { + return new AArch64LoopIdiomTransformLegacyPass(); +} + +PreservedAnalyses +AArch64LoopIdiomTransformPass::run(Loop &L, LoopAnalysisManager &AM, + LoopStandardAnalysisResults &AR, + LPMUpdater &) { + if (DisableAll) + return PreservedAnalyses::all(); + + const auto *DL = &L.getHeader()->getModule()->getDataLayout(); + + AArch64LoopIdiomTransform LIT(&AR.DT, &AR.LI, &AR.TTI, DL); + if (!LIT.run(&L)) + return PreservedAnalyses::all(); + + return PreservedAnalyses::none(); +} + +//===----------------------------------------------------------------------===// +// +// Implementation of AArch64LoopIdiomTransform +// +//===----------------------------------------------------------------------===// + +bool AArch64LoopIdiomTransform::run(Loop *L) { + CurLoop = L; + + if (DisableAll || L->getHeader()->getParent()->hasOptSize()) + return false; + + // If the loop could not be converted to canonical form, it must have an + // indirectbr in it, just give up. + if (!L->getLoopPreheader()) + return false; + + LLVM_DEBUG(dbgs() << DEBUG_TYPE " Scanning: F[" + << CurLoop->getHeader()->getParent()->getName() + << "] Loop %" << CurLoop->getHeader()->getName() << "\n"); + + return recognizeByteCompare(); +} + +bool AArch64LoopIdiomTransform::recognizeByteCompare() { + // Currently the transformation only works on scalable vector types, although + // there is no fundamental reason why it cannot be made to work for fixed + // width too. + + // We also need to know the minimum page size for the target in order to + // generate runtime memory checks to ensure the vector version won't fault. + if (!TTI->supportsScalableVectors() || !TTI->getMinPageSize().has_value() || + DisableByteCmp) + return false; + + BasicBlock *Header = CurLoop->getHeader(); + + // In AArch64LoopIdiomTransform::run we have already checked that the loop + // has a preheader so we can assume it's in a canonical form. + if (CurLoop->getNumBackEdges() != 1 || CurLoop->getNumBlocks() != 2) + return false; + + PHINode *PN = dyn_cast(&Header->front()); + if (!PN || PN->getNumIncomingValues() != 2) + return false; + + auto LoopBlocks = CurLoop->getBlocks(); + // The first block in the loop should contain only 4 instructions, e.g. + // + // while.cond: + // %res.phi = phi i32 [ %start, %ph ], [ %inc, %while.body ] + // %inc = add i32 %res.phi, 1 + // %cmp.not = icmp eq i32 %inc, %n + // br i1 %cmp.not, label %while.end, label %while.body + // + auto CondBBInsts = LoopBlocks[0]->instructionsWithoutDebug(); + if (std::distance(CondBBInsts.begin(), CondBBInsts.end()) > 4) + return false; + + // The second block should contain 7 instructions, e.g. + // + // while.body: + // %idx = zext i32 %inc to i64 + // %idx.a = getelementptr inbounds i8, ptr %a, i64 %idx + // %load.a = load i8, ptr %idx.a + // %idx.b = getelementptr inbounds i8, ptr %b, i64 %idx + // %load.b = load i8, ptr %idx.b + // %cmp.not.ld = icmp eq i8 %load.a, %load.b + // br i1 %cmp.not.ld, label %while.cond, label %while.end + // + auto LoopBBInsts = LoopBlocks[1]->instructionsWithoutDebug(); + if (std::distance(LoopBBInsts.begin(), LoopBBInsts.end()) > 7) + return false; + + // The incoming value to the PHI node from the loop should be an add of 1. + Value *StartIdx = nullptr; + Instruction *Index = nullptr; + if (!CurLoop->contains(PN->getIncomingBlock(0))) { + StartIdx = PN->getIncomingValue(0); + Index = dyn_cast(PN->getIncomingValue(1)); + } else { + StartIdx = PN->getIncomingValue(1); + Index = dyn_cast(PN->getIncomingValue(0)); + } + + // Limit to 32-bit types for now + if (!Index || !Index->getType()->isIntegerTy(32) || + !match(Index, m_c_Add(m_Specific(PN), m_One()))) + return false; + + // If we match the pattern, PN and Index will be replaced with the result of + // the cttz.elts intrinsic. If any other instructions are used outside of + // the loop, we cannot replace it. + for (BasicBlock *BB : LoopBlocks) + for (Instruction &I : *BB) + if (&I != PN && &I != Index) + for (User *U : I.users()) + if (!CurLoop->contains(cast(U))) + return false; + + // Match the branch instruction for the header + ICmpInst::Predicate Pred; + Value *MaxLen; + BasicBlock *EndBB, *WhileBB; + if (!match(Header->getTerminator(), + m_Br(m_ICmp(Pred, m_Specific(Index), m_Value(MaxLen)), + m_BasicBlock(EndBB), m_BasicBlock(WhileBB))) || + Pred != ICmpInst::Predicate::ICMP_EQ || !CurLoop->contains(WhileBB)) + return false; + + // WhileBB should contain the pattern of load & compare instructions. Match + // the pattern and find the GEP instructions used by the loads. + ICmpInst::Predicate WhilePred; + BasicBlock *FoundBB; + BasicBlock *TrueBB; + Value *LoadA, *LoadB; + if (!match(WhileBB->getTerminator(), + m_Br(m_ICmp(WhilePred, m_Value(LoadA), m_Value(LoadB)), + m_BasicBlock(TrueBB), m_BasicBlock(FoundBB))) || + WhilePred != ICmpInst::Predicate::ICMP_EQ || !CurLoop->contains(TrueBB)) + return false; + + Value *A, *B; + if (!match(LoadA, m_Load(m_Value(A))) || !match(LoadB, m_Load(m_Value(B)))) + return false; + + LoadInst *LoadAI = cast(LoadA); + LoadInst *LoadBI = cast(LoadB); + if (!LoadAI->isSimple() || !LoadBI->isSimple()) + return false; + + GetElementPtrInst *GEPA = dyn_cast(A); + GetElementPtrInst *GEPB = dyn_cast(B); + + if (!GEPA || !GEPB) + return false; + + Value *PtrA = GEPA->getPointerOperand(); + Value *PtrB = GEPB->getPointerOperand(); + + // Check we are loading i8 values from two loop invariant pointers + if (!CurLoop->isLoopInvariant(PtrA) || !CurLoop->isLoopInvariant(PtrB) || + !GEPA->getResultElementType()->isIntegerTy(8) || + !GEPB->getResultElementType()->isIntegerTy(8) || + !LoadAI->getType()->isIntegerTy(8) || + !LoadBI->getType()->isIntegerTy(8) || PtrA == PtrB) + return false; + + // Check that the index to the GEPs is the index we found earlier + if (GEPA->getNumIndices() > 1 || GEPB->getNumIndices() > 1) + return false; + + Value *IdxA = GEPA->getOperand(GEPA->getNumIndices()); + Value *IdxB = GEPB->getOperand(GEPB->getNumIndices()); + if (IdxA != IdxB || !match(IdxA, m_ZExt(m_Specific(Index)))) + return false; + + // We only ever expect the pre-incremented index value to be used inside the + // loop. + if (!PN->hasOneUse()) + return false; + + // Ensure that when the Found and End blocks are identical the PHIs have the + // supported format. We don't currently allow cases like this: + // while.cond: + // ... + // br i1 %cmp.not, label %while.end, label %while.body + // + // while.body: + // ... + // br i1 %cmp.not2, label %while.cond, label %while.end + // + // while.end: + // %final_ptr = phi ptr [ %c, %while.body ], [ %d, %while.cond ] + // + // Where the incoming values for %final_ptr are unique and from each of the + // loop blocks, but not actually defined in the loop. This requires extra + // work setting up the byte.compare block, i.e. by introducing a select to + // choose the correct value. + // TODO: We could add support for this in future. + if (FoundBB == EndBB) { + for (PHINode &EndPN : EndBB->phis()) { + Value *WhileCondVal = EndPN.getIncomingValueForBlock(Header); + Value *WhileBodyVal = EndPN.getIncomingValueForBlock(WhileBB); + + // The value of the index when leaving the while.cond block is always the + // same as the end value (MaxLen) so we permit either. Otherwise for any + // other value defined outside the loop we only allow values that are the + // same as the exit value for while.body. + if (WhileCondVal != Index && WhileCondVal != MaxLen && + WhileCondVal != WhileBodyVal) + return false; + } + } + + LLVM_DEBUG(dbgs() << "FOUND IDIOM IN LOOP: \n" + << *(EndBB->getParent()) << "\n\n"); + + // The index is incremented before the GEP/Load pair so we need to + // add 1 to the start value. + transformByteCompare(GEPA, GEPB, PN, MaxLen, Index, StartIdx, /*IncIdx=*/true, + FoundBB, EndBB); + return true; +} + +Value *AArch64LoopIdiomTransform::expandFindMismatch( + IRBuilder<> &Builder, DomTreeUpdater &DTU, GetElementPtrInst *GEPA, + GetElementPtrInst *GEPB, Instruction *Index, Value *Start, Value *MaxLen) { + Value *PtrA = GEPA->getPointerOperand(); + Value *PtrB = GEPB->getPointerOperand(); + + // Get the arguments and types for the intrinsic. + BasicBlock *Preheader = CurLoop->getLoopPreheader(); + BranchInst *PHBranch = cast(Preheader->getTerminator()); + LLVMContext &Ctx = PHBranch->getContext(); + Type *LoadType = Type::getInt8Ty(Ctx); + Type *ResType = Builder.getInt32Ty(); + + // Split block in the original loop preheader. + BasicBlock *EndBlock = + SplitBlock(Preheader, PHBranch, DT, LI, nullptr, "mismatch_end"); + + // Create the blocks that we're going to need: + // 1. A block for checking the zero-extended length exceeds 0 + // 2. A block to check that the start and end addresses of a given array + // lie on the same page. + // 3. The SVE loop preheader. + // 4. The first SVE loop block. + // 5. The SVE loop increment block. + // 6. A block we can jump to from the SVE loop when a mismatch is found. + // 7. The first block of the scalar loop itself, containing PHIs , loads + // and cmp. + // 8. A scalar loop increment block to increment the PHIs and go back + // around the loop. + + BasicBlock *MinItCheckBlock = BasicBlock::Create( + Ctx, "mismatch_min_it_check", EndBlock->getParent(), EndBlock); + + // Update the terminator added by SplitBlock to branch to the first block + Preheader->getTerminator()->setSuccessor(0, MinItCheckBlock); + + BasicBlock *MemCheckBlock = BasicBlock::Create( + Ctx, "mismatch_mem_check", EndBlock->getParent(), EndBlock); + + BasicBlock *SVELoopPreheaderBlock = BasicBlock::Create( + Ctx, "mismatch_sve_loop_preheader", EndBlock->getParent(), EndBlock); + + BasicBlock *SVELoopStartBlock = BasicBlock::Create( + Ctx, "mismatch_sve_loop", EndBlock->getParent(), EndBlock); + + BasicBlock *SVELoopIncBlock = BasicBlock::Create( + Ctx, "mismatch_sve_loop_inc", EndBlock->getParent(), EndBlock); + + BasicBlock *SVELoopMismatchBlock = BasicBlock::Create( + Ctx, "mismatch_sve_loop_found", EndBlock->getParent(), EndBlock); + + BasicBlock *LoopPreHeaderBlock = BasicBlock::Create( + Ctx, "mismatch_loop_pre", EndBlock->getParent(), EndBlock); + + BasicBlock *LoopStartBlock = + BasicBlock::Create(Ctx, "mismatch_loop", EndBlock->getParent(), EndBlock); + + BasicBlock *LoopIncBlock = BasicBlock::Create( + Ctx, "mismatch_loop_inc", EndBlock->getParent(), EndBlock); + + DTU.applyUpdates({{DominatorTree::Insert, Preheader, MinItCheckBlock}, + {DominatorTree::Delete, Preheader, EndBlock}}); + + // Update LoopInfo with the new SVE & scalar loops. + auto SVELoop = LI->AllocateLoop(); + auto ScalarLoop = LI->AllocateLoop(); + + if (CurLoop->getParentLoop()) { + CurLoop->getParentLoop()->addBasicBlockToLoop(MinItCheckBlock, *LI); + CurLoop->getParentLoop()->addBasicBlockToLoop(MemCheckBlock, *LI); + CurLoop->getParentLoop()->addBasicBlockToLoop(SVELoopPreheaderBlock, *LI); + CurLoop->getParentLoop()->addChildLoop(SVELoop); + CurLoop->getParentLoop()->addBasicBlockToLoop(SVELoopMismatchBlock, *LI); + CurLoop->getParentLoop()->addBasicBlockToLoop(LoopPreHeaderBlock, *LI); + CurLoop->getParentLoop()->addChildLoop(ScalarLoop); + } else { + LI->addTopLevelLoop(SVELoop); + LI->addTopLevelLoop(ScalarLoop); + } + + // Add the new basic blocks to their associated loops. + SVELoop->addBasicBlockToLoop(SVELoopStartBlock, *LI); + SVELoop->addBasicBlockToLoop(SVELoopIncBlock, *LI); + + ScalarLoop->addBasicBlockToLoop(LoopStartBlock, *LI); + ScalarLoop->addBasicBlockToLoop(LoopIncBlock, *LI); + + // Set up some types and constants that we intend to reuse. + Type *I64Type = Builder.getInt64Ty(); + + // Check the zero-extended iteration count > 0 + Builder.SetInsertPoint(MinItCheckBlock); + Value *ExtStart = Builder.CreateZExt(Start, I64Type); + Value *ExtEnd = Builder.CreateZExt(MaxLen, I64Type); + // This check doesn't really cost us very much. + + Value *LimitCheck = Builder.CreateICmpULE(Start, MaxLen); + BranchInst *MinItCheckBr = + BranchInst::Create(MemCheckBlock, LoopPreHeaderBlock, LimitCheck); + MinItCheckBr->setMetadata( + LLVMContext::MD_prof, + MDBuilder(MinItCheckBr->getContext()).createBranchWeights(99, 1)); + Builder.Insert(MinItCheckBr); + + DTU.applyUpdates( + {{DominatorTree::Insert, MinItCheckBlock, MemCheckBlock}, + {DominatorTree::Insert, MinItCheckBlock, LoopPreHeaderBlock}}); + + // For each of the arrays, check the start/end addresses are on the same + // page. + Builder.SetInsertPoint(MemCheckBlock); + + // The early exit in the original loop means that when performing vector + // loads we are potentially reading ahead of the early exit. So we could + // fault if crossing a page boundary. Therefore, we create runtime memory + // checks based on the minimum page size as follows: + // 1. Calculate the addresses of the first memory accesses in the loop, + // i.e. LhsStart and RhsStart. + // 2. Get the last accessed addresses in the loop, i.e. LhsEnd and RhsEnd. + // 3. Determine which pages correspond to all the memory accesses, i.e + // LhsStartPage, LhsEndPage, RhsStartPage, RhsEndPage. + // 4. If LhsStartPage == LhsEndPage and RhsStartPage == RhsEndPage, then + // we know we won't cross any page boundaries in the loop so we can + // enter the vector loop! Otherwise we fall back on the scalar loop. + Value *LhsStartGEP = Builder.CreateGEP(LoadType, PtrA, ExtStart); + Value *RhsStartGEP = Builder.CreateGEP(LoadType, PtrB, ExtStart); + Value *RhsStart = Builder.CreatePtrToInt(RhsStartGEP, I64Type); + Value *LhsStart = Builder.CreatePtrToInt(LhsStartGEP, I64Type); + Value *LhsEndGEP = Builder.CreateGEP(LoadType, PtrA, ExtEnd); + Value *RhsEndGEP = Builder.CreateGEP(LoadType, PtrB, ExtEnd); + Value *LhsEnd = Builder.CreatePtrToInt(LhsEndGEP, I64Type); + Value *RhsEnd = Builder.CreatePtrToInt(RhsEndGEP, I64Type); + + const uint64_t MinPageSize = TTI->getMinPageSize().value(); + const uint64_t AddrShiftAmt = llvm::Log2_64(MinPageSize); + Value *LhsStartPage = Builder.CreateLShr(LhsStart, AddrShiftAmt); + Value *LhsEndPage = Builder.CreateLShr(LhsEnd, AddrShiftAmt); + Value *RhsStartPage = Builder.CreateLShr(RhsStart, AddrShiftAmt); + Value *RhsEndPage = Builder.CreateLShr(RhsEnd, AddrShiftAmt); + Value *LhsPageCmp = Builder.CreateICmpNE(LhsStartPage, LhsEndPage); + Value *RhsPageCmp = Builder.CreateICmpNE(RhsStartPage, RhsEndPage); + + Value *CombinedPageCmp = Builder.CreateOr(LhsPageCmp, RhsPageCmp); + BranchInst *CombinedPageCmpCmpBr = BranchInst::Create( + LoopPreHeaderBlock, SVELoopPreheaderBlock, CombinedPageCmp); + CombinedPageCmpCmpBr->setMetadata( + LLVMContext::MD_prof, MDBuilder(CombinedPageCmpCmpBr->getContext()) + .createBranchWeights(10, 90)); + Builder.Insert(CombinedPageCmpCmpBr); + + DTU.applyUpdates( + {{DominatorTree::Insert, MemCheckBlock, LoopPreHeaderBlock}, + {DominatorTree::Insert, MemCheckBlock, SVELoopPreheaderBlock}}); + + // Set up the SVE loop preheader, i.e. calculate initial loop predicate, + // zero-extend MaxLen to 64-bits, determine the number of vector elements + // processed in each iteration, etc. + Builder.SetInsertPoint(SVELoopPreheaderBlock); + + // At this point we know two things must be true: + // 1. Start <= End + // 2. ExtMaxLen <= MinPageSize due to the page checks. + // Therefore, we know that we can use a 64-bit induction variable that + // starts from 0 -> ExtMaxLen and it will not overflow. + ScalableVectorType *PredVTy = + ScalableVectorType::get(Builder.getInt1Ty(), 16); + + Value *InitialPred = Builder.CreateIntrinsic( + Intrinsic::get_active_lane_mask, {PredVTy, I64Type}, {ExtStart, ExtEnd}); + + Value *VecLen = Builder.CreateIntrinsic(Intrinsic::vscale, {I64Type}, {}); + VecLen = Builder.CreateMul(VecLen, ConstantInt::get(I64Type, 16), "", + /*HasNUW=*/true, /*HasNSW=*/true); + + Value *PFalse = Builder.CreateVectorSplat(PredVTy->getElementCount(), + Builder.getInt1(false)); + + BranchInst *JumpToSVELoop = BranchInst::Create(SVELoopStartBlock); + Builder.Insert(JumpToSVELoop); + + DTU.applyUpdates( + {{DominatorTree::Insert, SVELoopPreheaderBlock, SVELoopStartBlock}}); + + // Set up the first SVE loop block by creating the PHIs, doing the vector + // loads and comparing the vectors. + Builder.SetInsertPoint(SVELoopStartBlock); + PHINode *LoopPred = Builder.CreatePHI(PredVTy, 2, "mismatch_sve_loop_pred"); + LoopPred->addIncoming(InitialPred, SVELoopPreheaderBlock); + PHINode *SVEIndexPhi = Builder.CreatePHI(I64Type, 2, "mismatch_sve_index"); + SVEIndexPhi->addIncoming(ExtStart, SVELoopPreheaderBlock); + Type *SVELoadType = ScalableVectorType::get(Builder.getInt8Ty(), 16); + Value *Passthru = ConstantInt::getNullValue(SVELoadType); + + Value *SVELhsGep = Builder.CreateGEP(LoadType, PtrA, SVEIndexPhi); + if (GEPA->isInBounds()) + cast(SVELhsGep)->setIsInBounds(true); + Value *SVELhsLoad = Builder.CreateMaskedLoad(SVELoadType, SVELhsGep, Align(1), + LoopPred, Passthru); + + Value *SVERhsGep = Builder.CreateGEP(LoadType, PtrB, SVEIndexPhi); + if (GEPB->isInBounds()) + cast(SVERhsGep)->setIsInBounds(true); + Value *SVERhsLoad = Builder.CreateMaskedLoad(SVELoadType, SVERhsGep, Align(1), + LoopPred, Passthru); + + Value *SVEMatchCmp = Builder.CreateICmpNE(SVELhsLoad, SVERhsLoad); + SVEMatchCmp = Builder.CreateSelect(LoopPred, SVEMatchCmp, PFalse); + Value *SVEMatchHasActiveLanes = Builder.CreateOrReduce(SVEMatchCmp); + BranchInst *SVEEarlyExit = BranchInst::Create( + SVELoopMismatchBlock, SVELoopIncBlock, SVEMatchHasActiveLanes); + Builder.Insert(SVEEarlyExit); + + DTU.applyUpdates( + {{DominatorTree::Insert, SVELoopStartBlock, SVELoopMismatchBlock}, + {DominatorTree::Insert, SVELoopStartBlock, SVELoopIncBlock}}); + + // Increment the index counter and calculate the predicate for the next + // iteration of the loop. We branch back to the start of the loop if there + // is at least one active lane. + Builder.SetInsertPoint(SVELoopIncBlock); + Value *NewSVEIndexPhi = Builder.CreateAdd(SVEIndexPhi, VecLen, "", + /*HasNUW=*/true, /*HasNSW=*/true); + SVEIndexPhi->addIncoming(NewSVEIndexPhi, SVELoopIncBlock); + Value *NewPred = + Builder.CreateIntrinsic(Intrinsic::get_active_lane_mask, + {PredVTy, I64Type}, {NewSVEIndexPhi, ExtEnd}); + LoopPred->addIncoming(NewPred, SVELoopIncBlock); + + Value *PredHasActiveLanes = + Builder.CreateExtractElement(NewPred, uint64_t(0)); + BranchInst *SVELoopBranchBack = + BranchInst::Create(SVELoopStartBlock, EndBlock, PredHasActiveLanes); + Builder.Insert(SVELoopBranchBack); + + DTU.applyUpdates({{DominatorTree::Insert, SVELoopIncBlock, SVELoopStartBlock}, + {DominatorTree::Insert, SVELoopIncBlock, EndBlock}}); + + // If we found a mismatch then we need to calculate which lane in the vector + // had a mismatch and add that on to the current loop index. + Builder.SetInsertPoint(SVELoopMismatchBlock); + PHINode *FoundPred = Builder.CreatePHI(PredVTy, 1, "mismatch_sve_found_pred"); + FoundPred->addIncoming(SVEMatchCmp, SVELoopStartBlock); + PHINode *LastLoopPred = + Builder.CreatePHI(PredVTy, 1, "mismatch_sve_last_loop_pred"); + LastLoopPred->addIncoming(LoopPred, SVELoopStartBlock); + PHINode *SVEFoundIndex = + Builder.CreatePHI(I64Type, 1, "mismatch_sve_found_index"); + SVEFoundIndex->addIncoming(SVEIndexPhi, SVELoopStartBlock); + + Value *PredMatchCmp = Builder.CreateAnd(LastLoopPred, FoundPred); + Value *Ctz = Builder.CreateIntrinsic( + Intrinsic::experimental_cttz_elts, {ResType, PredMatchCmp->getType()}, + {PredMatchCmp, /*ZeroIsPoison=*/Builder.getInt1(true)}); + Ctz = Builder.CreateZExt(Ctz, I64Type); + Value *SVELoopRes64 = Builder.CreateAdd(SVEFoundIndex, Ctz, "", + /*HasNUW=*/true, /*HasNSW=*/true); + Value *SVELoopRes = Builder.CreateTrunc(SVELoopRes64, ResType); + + Builder.Insert(BranchInst::Create(EndBlock)); + + DTU.applyUpdates({{DominatorTree::Insert, SVELoopMismatchBlock, EndBlock}}); + + // Generate code for scalar loop. + Builder.SetInsertPoint(LoopPreHeaderBlock); + Builder.Insert(BranchInst::Create(LoopStartBlock)); + + DTU.applyUpdates( + {{DominatorTree::Insert, LoopPreHeaderBlock, LoopStartBlock}}); + + Builder.SetInsertPoint(LoopStartBlock); + PHINode *IndexPhi = Builder.CreatePHI(ResType, 2, "mismatch_index"); + IndexPhi->addIncoming(Start, LoopPreHeaderBlock); + + // Otherwise compare the values + // Load bytes from each array and compare them. + Value *GepOffset = Builder.CreateZExt(IndexPhi, I64Type); + + Value *LhsGep = Builder.CreateGEP(LoadType, PtrA, GepOffset); + if (GEPA->isInBounds()) + cast(LhsGep)->setIsInBounds(true); + Value *LhsLoad = Builder.CreateLoad(LoadType, LhsGep); + + Value *RhsGep = Builder.CreateGEP(LoadType, PtrB, GepOffset); + if (GEPB->isInBounds()) + cast(RhsGep)->setIsInBounds(true); + Value *RhsLoad = Builder.CreateLoad(LoadType, RhsGep); + + Value *MatchCmp = Builder.CreateICmpEQ(LhsLoad, RhsLoad); + // If we have a mismatch then exit the loop ... + BranchInst *MatchCmpBr = BranchInst::Create(LoopIncBlock, EndBlock, MatchCmp); + Builder.Insert(MatchCmpBr); + + DTU.applyUpdates({{DominatorTree::Insert, LoopStartBlock, LoopIncBlock}, + {DominatorTree::Insert, LoopStartBlock, EndBlock}}); + + // Have we reached the maximum permitted length for the loop? + Builder.SetInsertPoint(LoopIncBlock); + Value *PhiInc = Builder.CreateAdd(IndexPhi, ConstantInt::get(ResType, 1), "", + /*HasNUW=*/Index->hasNoUnsignedWrap(), + /*HasNSW=*/Index->hasNoSignedWrap()); + IndexPhi->addIncoming(PhiInc, LoopIncBlock); + Value *IVCmp = Builder.CreateICmpEQ(PhiInc, MaxLen); + BranchInst *IVCmpBr = BranchInst::Create(EndBlock, LoopStartBlock, IVCmp); + Builder.Insert(IVCmpBr); + + DTU.applyUpdates({{DominatorTree::Insert, LoopIncBlock, EndBlock}, + {DominatorTree::Insert, LoopIncBlock, LoopStartBlock}}); + + // In the end block we need to insert a PHI node to deal with three cases: + // 1. We didn't find a mismatch in the scalar loop, so we return MaxLen. + // 2. We exitted the scalar loop early due to a mismatch and need to return + // the index that we found. + // 3. We didn't find a mismatch in the SVE loop, so we return MaxLen. + // 4. We exitted the SVE loop early due to a mismatch and need to return + // the index that we found. + Builder.SetInsertPoint(EndBlock, EndBlock->getFirstInsertionPt()); + PHINode *ResPhi = Builder.CreatePHI(ResType, 4, "mismatch_result"); + ResPhi->addIncoming(MaxLen, LoopIncBlock); + ResPhi->addIncoming(IndexPhi, LoopStartBlock); + ResPhi->addIncoming(MaxLen, SVELoopIncBlock); + ResPhi->addIncoming(SVELoopRes, SVELoopMismatchBlock); + + Value *FinalRes = Builder.CreateTrunc(ResPhi, ResType); + + if (VerifyLoops) { + ScalarLoop->verifyLoop(); + SVELoop->verifyLoop(); + if (!SVELoop->isRecursivelyLCSSAForm(*DT, *LI)) + report_fatal_error("Loops must remain in LCSSA form!"); + if (!ScalarLoop->isRecursivelyLCSSAForm(*DT, *LI)) + report_fatal_error("Loops must remain in LCSSA form!"); + } + + return FinalRes; +} + +void AArch64LoopIdiomTransform::transformByteCompare( + GetElementPtrInst *GEPA, GetElementPtrInst *GEPB, PHINode *IndPhi, + Value *MaxLen, Instruction *Index, Value *Start, bool IncIdx, + BasicBlock *FoundBB, BasicBlock *EndBB) { + + // Insert the byte compare code at the end of the preheader block + BasicBlock *Preheader = CurLoop->getLoopPreheader(); + BasicBlock *Header = CurLoop->getHeader(); + BranchInst *PHBranch = cast(Preheader->getTerminator()); + IRBuilder<> Builder(PHBranch); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); + Builder.SetCurrentDebugLocation(PHBranch->getDebugLoc()); + + // Increment the pointer if this was done before the loads in the loop. + if (IncIdx) + Start = Builder.CreateAdd(Start, ConstantInt::get(Start->getType(), 1)); + + Value *ByteCmpRes = + expandFindMismatch(Builder, DTU, GEPA, GEPB, Index, Start, MaxLen); + + // Replaces uses of index & induction Phi with intrinsic (we already + // checked that the the first instruction of Header is the Phi above). + assert(IndPhi->hasOneUse() && "Index phi node has more than one use!"); + Index->replaceAllUsesWith(ByteCmpRes); + + assert(PHBranch->isUnconditional() && + "Expected preheader to terminate with an unconditional branch."); + + // If no mismatch was found, we can jump to the end block. Create a + // new basic block for the compare instruction. + auto *CmpBB = BasicBlock::Create(Preheader->getContext(), "byte.compare", + Preheader->getParent()); + CmpBB->moveBefore(EndBB); + + // Replace the branch in the preheader with an always-true conditional branch. + // This ensures there is still a reference to the original loop. + Builder.CreateCondBr(Builder.getTrue(), CmpBB, Header); + PHBranch->eraseFromParent(); + + BasicBlock *MismatchEnd = cast(ByteCmpRes)->getParent(); + DTU.applyUpdates({{DominatorTree::Insert, MismatchEnd, CmpBB}}); + + // Create the branch to either the end or found block depending on the value + // returned by the intrinsic. + Builder.SetInsertPoint(CmpBB); + if (FoundBB != EndBB) { + Value *FoundCmp = Builder.CreateICmpEQ(ByteCmpRes, MaxLen); + Builder.CreateCondBr(FoundCmp, EndBB, FoundBB); + DTU.applyUpdates({{DominatorTree::Insert, CmpBB, FoundBB}, + {DominatorTree::Insert, CmpBB, EndBB}}); + + } else { + Builder.CreateBr(FoundBB); + DTU.applyUpdates({{DominatorTree::Insert, CmpBB, FoundBB}}); + } + + auto fixSuccessorPhis = [&](BasicBlock *SuccBB) { + for (PHINode &PN : SuccBB->phis()) { + // At this point we've already replaced all uses of the result from the + // loop with ByteCmp. Look through the incoming values to find ByteCmp, + // meaning this is a Phi collecting the results of the byte compare. + bool ResPhi = false; + for (Value *Op : PN.incoming_values()) + if (Op == ByteCmpRes) { + ResPhi = true; + break; + } + + // Any PHI that depended upon the result of the byte compare needs a new + // incoming value from CmpBB. This is because the original loop will get + // deleted. + if (ResPhi) + PN.addIncoming(ByteCmpRes, CmpBB); + else { + // There should be no other outside uses of other values in the + // original loop. Any incoming values should either: + // 1. Be for blocks outside the loop, which aren't interesting. Or .. + // 2. These are from blocks in the loop with values defined outside + // the loop. We should a similar incoming value from CmpBB. + for (BasicBlock *BB : PN.blocks()) + if (CurLoop->contains(BB)) { + PN.addIncoming(PN.getIncomingValueForBlock(BB), CmpBB); + break; + } + } + } + }; + + // Ensure all Phis in the successors of CmpBB have an incoming value from it. + fixSuccessorPhis(EndBB); + if (EndBB != FoundBB) + fixSuccessorPhis(FoundBB); + + // The new CmpBB block isn't part of the loop, but will need to be added to + // the outer loop if there is one. + if (!CurLoop->isOutermost()) + CurLoop->getParentLoop()->addBasicBlockToLoop(CmpBB, *LI); + + if (VerifyLoops && CurLoop->getParentLoop()) { + CurLoop->getParentLoop()->verifyLoop(); + if (!CurLoop->getParentLoop()->isRecursivelyLCSSAForm(*DT, *LI)) + report_fatal_error("Loops must remain in LCSSA form!"); + } +} diff --git a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.h b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.h new file mode 100644 index 000000000000..cc68425bb68b --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.h @@ -0,0 +1,25 @@ +//===- AArch64LoopIdiomTransform.h --------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64LOOPIDIOMTRANSFORM_H +#define LLVM_LIB_TARGET_AARCH64_AARCH64LOOPIDIOMTRANSFORM_H + +#include "llvm/IR/PassManager.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" + +namespace llvm { + +struct AArch64LoopIdiomTransformPass + : PassInfoMixin { + PreservedAnalyses run(Loop &L, LoopAnalysisManager &AM, + LoopStandardAnalysisResults &AR, LPMUpdater &U); +}; + +} // namespace llvm + +#endif // LLVM_LIB_TARGET_AARCH64_AARCH64LOOPIDIOMTRANSFORM_H diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 036719be06d8..144610e021c5 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -11,6 +11,7 @@ #include "AArch64TargetMachine.h" #include "AArch64.h" +#include "AArch64LoopIdiomTransform.h" #include "AArch64MachineFunctionInfo.h" #include "AArch64MachineScheduler.h" #include "AArch64MacroFusion.h" @@ -43,6 +44,7 @@ #include "llvm/MC/MCTargetOptions.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Pass.h" +#include "llvm/Passes/PassBuilder.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetLoweringObjectFile.h" @@ -222,6 +224,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() { initializeAArch64DeadRegisterDefinitionsPass(*PR); initializeAArch64ExpandPseudoPass(*PR); initializeAArch64LoadStoreOptPass(*PR); + initializeAArch64LoopIdiomTransformLegacyPassPass(*PR); initializeAArch64MIPeepholeOptPass(*PR); initializeAArch64SIMDInstrOptPass(*PR); initializeAArch64O0PreLegalizerCombinerPass(*PR); @@ -537,6 +540,14 @@ public: } // end anonymous namespace +void AArch64TargetMachine::registerPassBuilderCallbacks( + PassBuilder &PB, bool PopulateClassToPassNames) { + PB.registerLateLoopOptimizationsEPCallback( + [=](LoopPassManager &LPM, OptimizationLevel Level) { + LPM.addPass(AArch64LoopIdiomTransformPass()); + }); +} + TargetTransformInfo AArch64TargetMachine::getTargetTransformInfo(const Function &F) const { return TargetTransformInfo(AArch64TTIImpl(this, F)); diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h index 12b971853f84..8fb68b06f137 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -14,6 +14,7 @@ #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H #include "AArch64InstrInfo.h" +#include "AArch64LoopIdiomTransform.h" #include "AArch64Subtarget.h" #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" @@ -43,6 +44,9 @@ public: // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + void registerPassBuilderCallbacks(PassBuilder &PB, + bool PopulateClassToPassNames) override; + TargetTransformInfo getTargetTransformInfo(const Function &F) const override; TargetLoweringObjectFile* getObjFileLowering() const override { diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index 0b220069a388..f471294ffc25 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -420,6 +420,8 @@ public: return BaseT::getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy); } + + std::optional getMinPageSize() const { return 4096; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt index d97342b0829d..cb5f85801c65 100644 --- a/llvm/lib/Target/AArch64/CMakeLists.txt +++ b/llvm/lib/Target/AArch64/CMakeLists.txt @@ -64,6 +64,7 @@ add_llvm_target(AArch64CodeGen AArch64ISelLowering.cpp AArch64InstrInfo.cpp AArch64LoadStoreOptimizer.cpp + AArch64LoopIdiomTransform.cpp AArch64LowerHomogeneousPrologEpilog.cpp AArch64MachineFunctionInfo.cpp AArch64MachineScheduler.cpp diff --git a/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll b/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll new file mode 100644 index 000000000000..8f011e2d00a0 --- /dev/null +++ b/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll @@ -0,0 +1,1985 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 +; RUN: opt -aarch64-lit -disable-aarch64-lit-all=false -aarch64-lit-verify -verify-dom-info -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s +; RUN: opt -aarch64-lit -disable-aarch64-lit-all=false -simplifycfg -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s --check-prefix=LOOP-DEL +; RUN: opt -aarch64-lit -disable-aarch64-lit-all=false -mtriple aarch64-unknown-linux-gnu -S < %s | FileCheck %s --check-prefix=NO-TRANSFORM + +define i32 @compare_bytes_simple(ptr %a, ptr %b, i32 %len, i32 %extra, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_simple( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; CHECK-NEXT: br label [[MISMATCH_MIN_IT_CHECK:%.*]] +; CHECK: mismatch_min_it_check: +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; CHECK-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0:![0-9]+]] +; CHECK: mismatch_mem_check: +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; CHECK-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; CHECK-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1:![0-9]+]] +; CHECK: mismatch_sve_loop_preheader: +; CHECK-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; CHECK-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; CHECK: mismatch_sve_loop: +; CHECK-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; CHECK-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; CHECK-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; CHECK-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; CHECK: mismatch_sve_loop_inc: +; CHECK-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; CHECK-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; CHECK-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[MISMATCH_END:%.*]] +; CHECK: mismatch_sve_loop_found: +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; CHECK-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; CHECK-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; CHECK-NEXT: br label [[MISMATCH_END]] +; CHECK: mismatch_loop_pre: +; CHECK-NEXT: br label [[MISMATCH_LOOP:%.*]] +; CHECK: mismatch_loop: +; CHECK-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; CHECK-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[MISMATCH_END]] +; CHECK: mismatch_loop_inc: +; CHECK-NEXT: [[TMP43]] = add i32 [[MISMATCH_INDEX]], 1 +; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; CHECK-NEXT: br i1 [[TMP44]], label [[MISMATCH_END]], label [[MISMATCH_LOOP]] +; CHECK: mismatch_end: +; CHECK-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; CHECK-NEXT: br i1 true, label [[BYTE_COMPARE:%.*]], label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[MISMATCH_END]] ], [ [[MISMATCH_RESULT]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC:%.*]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[MISMATCH_RESULT]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP45]], [[TMP46]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: byte.compare: +; CHECK-NEXT: br label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[MISMATCH_RESULT]], [[WHILE_BODY]] ], [ [[MISMATCH_RESULT]], [[WHILE_COND]] ], [ [[MISMATCH_RESULT]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ], [ [[EXTRA]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; CHECK-NEXT: ret i32 [[RES]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; LOOP-DEL-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; LOOP-DEL-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; LOOP-DEL-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0:![0-9]+]] +; LOOP-DEL: mismatch_mem_check: +; LOOP-DEL-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; LOOP-DEL-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; LOOP-DEL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; LOOP-DEL-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; LOOP-DEL-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; LOOP-DEL-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; LOOP-DEL-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; LOOP-DEL-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; LOOP-DEL-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; LOOP-DEL-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; LOOP-DEL-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; LOOP-DEL-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1:![0-9]+]] +; LOOP-DEL: mismatch_sve_loop_preheader: +; LOOP-DEL-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; LOOP-DEL-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; LOOP-DEL-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; LOOP-DEL: mismatch_sve_loop: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; LOOP-DEL-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; LOOP-DEL-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; LOOP-DEL-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; LOOP-DEL-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; LOOP-DEL: mismatch_sve_loop_inc: +; LOOP-DEL-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; LOOP-DEL-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; LOOP-DEL-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[WHILE_END:%.*]] +; LOOP-DEL: mismatch_sve_loop_found: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; LOOP-DEL-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; LOOP-DEL-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; LOOP-DEL-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; LOOP-DEL-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; LOOP-DEL-NEXT: br label [[WHILE_END]] +; LOOP-DEL: mismatch_loop_pre: +; LOOP-DEL-NEXT: br label [[MISMATCH_LOOP:%.*]] +; LOOP-DEL: mismatch_loop: +; LOOP-DEL-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; LOOP-DEL-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; LOOP-DEL-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; LOOP-DEL-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; LOOP-DEL-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[WHILE_END]] +; LOOP-DEL: mismatch_loop_inc: +; LOOP-DEL-NEXT: [[TMP43]] = add i32 [[MISMATCH_INDEX]], 1 +; LOOP-DEL-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP44]], label [[WHILE_END]], label [[MISMATCH_LOOP]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; LOOP-DEL-NEXT: [[RES:%.*]] = add i32 [[MISMATCH_RESULT]], [[EXTRA]] +; LOOP-DEL-NEXT: ret i32 [[RES]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; NO-TRANSFORM-NEXT: ret i32 [[RES]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + %extra.phi = phi i32 [ %extra, %while.body ], [ %extra, %while.cond ] + %res = add i32 %inc.lcssa, %extra.phi + ret i32 %res +} + + +define i32 @compare_bytes_signed_wrap(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_signed_wrap( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; CHECK-NEXT: br label [[MISMATCH_MIN_IT_CHECK:%.*]] +; CHECK: mismatch_min_it_check: +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; CHECK-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0]] +; CHECK: mismatch_mem_check: +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; CHECK-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; CHECK-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1]] +; CHECK: mismatch_sve_loop_preheader: +; CHECK-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; CHECK-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; CHECK: mismatch_sve_loop: +; CHECK-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; CHECK-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; CHECK-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; CHECK-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; CHECK: mismatch_sve_loop_inc: +; CHECK-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; CHECK-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; CHECK-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[MISMATCH_END:%.*]] +; CHECK: mismatch_sve_loop_found: +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; CHECK-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; CHECK-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; CHECK-NEXT: br label [[MISMATCH_END]] +; CHECK: mismatch_loop_pre: +; CHECK-NEXT: br label [[MISMATCH_LOOP:%.*]] +; CHECK: mismatch_loop: +; CHECK-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; CHECK-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[MISMATCH_END]] +; CHECK: mismatch_loop_inc: +; CHECK-NEXT: [[TMP43]] = add nsw i32 [[MISMATCH_INDEX]], 1 +; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; CHECK-NEXT: br i1 [[TMP44]], label [[MISMATCH_END]], label [[MISMATCH_LOOP]] +; CHECK: mismatch_end: +; CHECK-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; CHECK-NEXT: br i1 true, label [[BYTE_COMPARE:%.*]], label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[MISMATCH_END]] ], [ [[MISMATCH_RESULT]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[MISMATCH_RESULT]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP45]], [[TMP46]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: byte.compare: +; CHECK-NEXT: br label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[MISMATCH_RESULT]], [[WHILE_BODY]] ], [ [[MISMATCH_RESULT]], [[WHILE_COND]] ], [ [[MISMATCH_RESULT]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_signed_wrap( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; LOOP-DEL-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; LOOP-DEL-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; LOOP-DEL-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0]] +; LOOP-DEL: mismatch_mem_check: +; LOOP-DEL-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; LOOP-DEL-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; LOOP-DEL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; LOOP-DEL-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; LOOP-DEL-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; LOOP-DEL-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; LOOP-DEL-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; LOOP-DEL-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; LOOP-DEL-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; LOOP-DEL-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; LOOP-DEL-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; LOOP-DEL-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1]] +; LOOP-DEL: mismatch_sve_loop_preheader: +; LOOP-DEL-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; LOOP-DEL-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; LOOP-DEL-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; LOOP-DEL: mismatch_sve_loop: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; LOOP-DEL-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; LOOP-DEL-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; LOOP-DEL-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; LOOP-DEL-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; LOOP-DEL: mismatch_sve_loop_inc: +; LOOP-DEL-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; LOOP-DEL-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; LOOP-DEL-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[WHILE_END:%.*]] +; LOOP-DEL: mismatch_sve_loop_found: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; LOOP-DEL-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; LOOP-DEL-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; LOOP-DEL-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; LOOP-DEL-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; LOOP-DEL-NEXT: br label [[WHILE_END]] +; LOOP-DEL: mismatch_loop_pre: +; LOOP-DEL-NEXT: br label [[MISMATCH_LOOP:%.*]] +; LOOP-DEL: mismatch_loop: +; LOOP-DEL-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; LOOP-DEL-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; LOOP-DEL-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; LOOP-DEL-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; LOOP-DEL-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[WHILE_END]] +; LOOP-DEL: mismatch_loop_inc: +; LOOP-DEL-NEXT: [[TMP43]] = add nsw i32 [[MISMATCH_INDEX]], 1 +; LOOP-DEL-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP44]], label [[WHILE_END]], label [[MISMATCH_LOOP]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; LOOP-DEL-NEXT: ret i32 [[MISMATCH_RESULT]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_signed_wrap( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add nsw i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add nsw i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i32 %inc.lcssa +} + + +define i32 @compare_bytes_simple_end_ne_found(ptr %a, ptr %b, ptr %c, ptr %d, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_simple_end_ne_found( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; CHECK-NEXT: br label [[MISMATCH_MIN_IT_CHECK:%.*]] +; CHECK: mismatch_min_it_check: +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; CHECK-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0]] +; CHECK: mismatch_mem_check: +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; CHECK-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; CHECK-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1]] +; CHECK: mismatch_sve_loop_preheader: +; CHECK-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; CHECK-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; CHECK: mismatch_sve_loop: +; CHECK-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; CHECK-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; CHECK-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; CHECK-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; CHECK: mismatch_sve_loop_inc: +; CHECK-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; CHECK-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; CHECK-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[MISMATCH_END:%.*]] +; CHECK: mismatch_sve_loop_found: +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; CHECK-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; CHECK-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; CHECK-NEXT: br label [[MISMATCH_END]] +; CHECK: mismatch_loop_pre: +; CHECK-NEXT: br label [[MISMATCH_LOOP:%.*]] +; CHECK: mismatch_loop: +; CHECK-NEXT: [[MISMATCH_INDEX3:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX3]] to i64 +; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; CHECK-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[MISMATCH_END]] +; CHECK: mismatch_loop_inc: +; CHECK-NEXT: [[TMP43]] = add i32 [[MISMATCH_INDEX3]], 1 +; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; CHECK-NEXT: br i1 [[TMP44]], label [[MISMATCH_END]], label [[MISMATCH_LOOP]] +; CHECK: mismatch_end: +; CHECK-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX3]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; CHECK-NEXT: br i1 true, label [[BYTE_COMPARE:%.*]], label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[MISMATCH_END]] ], [ [[MISMATCH_RESULT]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC:%.*]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[MISMATCH_RESULT]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP45]], [[TMP46]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_FOUND:%.*]] +; CHECK: while.found: +; CHECK-NEXT: [[MISMATCH_INDEX1:%.*]] = phi i32 [ [[MISMATCH_RESULT]], [[WHILE_BODY]] ], [ [[MISMATCH_RESULT]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: [[FOUND_PTR:%.*]] = phi ptr [ [[C]], [[WHILE_BODY]] ], [ [[C]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: br label [[END:%.*]] +; CHECK: byte.compare: +; CHECK-NEXT: [[TMP47:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], [[N]] +; CHECK-NEXT: br i1 [[TMP47]], label [[WHILE_END]], label [[WHILE_FOUND]] +; CHECK: while.end: +; CHECK-NEXT: [[MISMATCH_INDEX2:%.*]] = phi i32 [ [[N]], [[WHILE_COND]] ], [ [[N]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: [[END_PTR:%.*]] = phi ptr [ [[D]], [[WHILE_COND]] ], [ [[D]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: br label [[END]] +; CHECK: end: +; CHECK-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[MISMATCH_INDEX1]], [[WHILE_FOUND]] ], [ [[MISMATCH_INDEX2]], [[WHILE_END]] ] +; CHECK-NEXT: [[STORE_PTR:%.*]] = phi ptr [ [[END_PTR]], [[WHILE_END]] ], [ [[FOUND_PTR]], [[WHILE_FOUND]] ] +; CHECK-NEXT: store i32 [[MISMATCH_INDEX]], ptr [[STORE_PTR]], align 4 +; CHECK-NEXT: ret i32 [[MISMATCH_INDEX]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple_end_ne_found( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; LOOP-DEL-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; LOOP-DEL-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; LOOP-DEL-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0]] +; LOOP-DEL: mismatch_mem_check: +; LOOP-DEL-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; LOOP-DEL-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; LOOP-DEL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; LOOP-DEL-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; LOOP-DEL-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; LOOP-DEL-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; LOOP-DEL-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; LOOP-DEL-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; LOOP-DEL-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; LOOP-DEL-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; LOOP-DEL-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; LOOP-DEL-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1]] +; LOOP-DEL: mismatch_sve_loop_preheader: +; LOOP-DEL-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; LOOP-DEL-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; LOOP-DEL-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; LOOP-DEL: mismatch_sve_loop: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; LOOP-DEL-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; LOOP-DEL-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; LOOP-DEL-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; LOOP-DEL-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; LOOP-DEL: mismatch_sve_loop_inc: +; LOOP-DEL-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; LOOP-DEL-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; LOOP-DEL-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[BYTE_COMPARE:%.*]] +; LOOP-DEL: mismatch_sve_loop_found: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; LOOP-DEL-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; LOOP-DEL-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; LOOP-DEL-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; LOOP-DEL-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; LOOP-DEL-NEXT: br label [[BYTE_COMPARE]] +; LOOP-DEL: mismatch_loop_pre: +; LOOP-DEL-NEXT: br label [[MISMATCH_LOOP:%.*]] +; LOOP-DEL: mismatch_loop: +; LOOP-DEL-NEXT: [[MISMATCH_INDEX3:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX3]] to i64 +; LOOP-DEL-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; LOOP-DEL-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; LOOP-DEL-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; LOOP-DEL-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[BYTE_COMPARE]] +; LOOP-DEL: mismatch_loop_inc: +; LOOP-DEL-NEXT: [[TMP43]] = add i32 [[MISMATCH_INDEX3]], 1 +; LOOP-DEL-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP44]], label [[BYTE_COMPARE]], label [[MISMATCH_LOOP]] +; LOOP-DEL: byte.compare: +; LOOP-DEL-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX3]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; LOOP-DEL-NEXT: [[TMP45:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], [[N]] +; LOOP-DEL-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP45]], i32 [[N]], i32 [[MISMATCH_RESULT]] +; LOOP-DEL-NEXT: [[SPEC_SELECT4:%.*]] = select i1 [[TMP45]], ptr [[D]], ptr [[C]] +; LOOP-DEL-NEXT: store i32 [[SPEC_SELECT]], ptr [[SPEC_SELECT4]], align 4 +; LOOP-DEL-NEXT: ret i32 [[SPEC_SELECT]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple_end_ne_found( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_FOUND:%.*]] +; NO-TRANSFORM: while.found: +; NO-TRANSFORM-NEXT: [[MISMATCH_INDEX1:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ] +; NO-TRANSFORM-NEXT: [[FOUND_PTR:%.*]] = phi ptr [ [[C]], [[WHILE_BODY]] ] +; NO-TRANSFORM-NEXT: br label [[END:%.*]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[MISMATCH_INDEX2:%.*]] = phi i32 [ [[N]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[END_PTR:%.*]] = phi ptr [ [[D]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: br label [[END]] +; NO-TRANSFORM: end: +; NO-TRANSFORM-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[MISMATCH_INDEX1]], [[WHILE_FOUND]] ], [ [[MISMATCH_INDEX2]], [[WHILE_END]] ] +; NO-TRANSFORM-NEXT: [[STORE_PTR:%.*]] = phi ptr [ [[END_PTR]], [[WHILE_END]] ], [ [[FOUND_PTR]], [[WHILE_FOUND]] ] +; NO-TRANSFORM-NEXT: store i32 [[MISMATCH_INDEX]], ptr [[STORE_PTR]], align 4 +; NO-TRANSFORM-NEXT: ret i32 [[MISMATCH_INDEX]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.found + +while.found: + %mismatch_index1 = phi i32 [ %inc, %while.body ] + %found_ptr = phi ptr [ %c, %while.body ] + br label %end + +while.end: + %mismatch_index2 = phi i32 [ %n, %while.cond ] + %end_ptr = phi ptr [ %d, %while.cond ] + br label %end + +end: + %mismatch_index = phi i32 [ %mismatch_index1, %while.found ], [ %mismatch_index2, %while.end ] + %store_ptr = phi ptr [ %end_ptr, %while.end ], [ %found_ptr, %while.found ] + store i32 %mismatch_index, ptr %store_ptr + ret i32 %mismatch_index +} + + + +define i32 @compare_bytes_extra_cmp(ptr %a, ptr %b, i32 %len, i32 %n, i32 %x) { +; CHECK-LABEL: define i32 @compare_bytes_extra_cmp( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP_X:%.*]] = icmp ult i32 [[N]], [[X]] +; CHECK-NEXT: br i1 [[CMP_X]], label [[PH:%.*]], label [[WHILE_END:%.*]] +; CHECK: ph: +; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; CHECK-NEXT: br label [[MISMATCH_MIN_IT_CHECK:%.*]] +; CHECK: mismatch_min_it_check: +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; CHECK-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0]] +; CHECK: mismatch_mem_check: +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; CHECK-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; CHECK-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1]] +; CHECK: mismatch_sve_loop_preheader: +; CHECK-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; CHECK-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; CHECK: mismatch_sve_loop: +; CHECK-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; CHECK-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; CHECK-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; CHECK-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; CHECK: mismatch_sve_loop_inc: +; CHECK-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; CHECK-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; CHECK-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; CHECK-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[MISMATCH_END:%.*]] +; CHECK: mismatch_sve_loop_found: +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; CHECK-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; CHECK-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; CHECK-NEXT: br label [[MISMATCH_END]] +; CHECK: mismatch_loop_pre: +; CHECK-NEXT: br label [[MISMATCH_LOOP:%.*]] +; CHECK: mismatch_loop: +; CHECK-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; CHECK-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; CHECK-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[MISMATCH_END]] +; CHECK: mismatch_loop_inc: +; CHECK-NEXT: [[TMP43]] = add i32 [[MISMATCH_INDEX]], 1 +; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; CHECK-NEXT: br i1 [[TMP44]], label [[MISMATCH_END]], label [[MISMATCH_LOOP]] +; CHECK: mismatch_end: +; CHECK-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; CHECK-NEXT: br i1 true, label [[BYTE_COMPARE:%.*]], label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[MISMATCH_END]] ], [ [[MISMATCH_RESULT]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC:%.*]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[MISMATCH_RESULT]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP45]], [[TMP46]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: byte.compare: +; CHECK-NEXT: br label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[MISMATCH_RESULT]], [[WHILE_BODY]] ], [ [[MISMATCH_RESULT]], [[WHILE_COND]] ], [ [[X]], [[ENTRY:%.*]] ], [ [[MISMATCH_RESULT]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_extra_cmp( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: [[CMP_X:%.*]] = icmp ult i32 [[N]], [[X]] +; LOOP-DEL-NEXT: br i1 [[CMP_X]], label [[PH:%.*]], label [[WHILE_END:%.*]] +; LOOP-DEL: ph: +; LOOP-DEL-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], 1 +; LOOP-DEL-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; LOOP-DEL-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; LOOP-DEL-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP0]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP3]], label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0]] +; LOOP-DEL: mismatch_mem_check: +; LOOP-DEL-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; LOOP-DEL-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; LOOP-DEL-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; LOOP-DEL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP2]] +; LOOP-DEL-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP8]] to i64 +; LOOP-DEL-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +; LOOP-DEL-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP7]], 12 +; LOOP-DEL-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP10]], 12 +; LOOP-DEL-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP6]], 12 +; LOOP-DEL-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 12 +; LOOP-DEL-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP12]], [[TMP13]] +; LOOP-DEL-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP14]], [[TMP15]] +; LOOP-DEL-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]] +; LOOP-DEL-NEXT: br i1 [[TMP18]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1]] +; LOOP-DEL: mismatch_sve_loop_preheader: +; LOOP-DEL-NEXT: [[TMP19:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP1]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() +; LOOP-DEL-NEXT: [[TMP21:%.*]] = mul nuw nsw i64 [[TMP20]], 16 +; LOOP-DEL-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; LOOP-DEL: mismatch_sve_loop: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP19]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP30:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ [[TMP1]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP29:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; LOOP-DEL-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP23:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP22]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[MISMATCH_SVE_INDEX]] +; LOOP-DEL-NEXT: [[TMP25:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP24]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; LOOP-DEL-NEXT: [[TMP26:%.*]] = icmp ne [[TMP23]], [[TMP25]] +; LOOP-DEL-NEXT: [[TMP27:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP26]], zeroinitializer +; LOOP-DEL-NEXT: [[TMP28:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP27]]) +; LOOP-DEL-NEXT: br i1 [[TMP28]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; LOOP-DEL: mismatch_sve_loop_inc: +; LOOP-DEL-NEXT: [[TMP29]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP21]] +; LOOP-DEL-NEXT: [[TMP30]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP29]], i64 [[TMP2]]) +; LOOP-DEL-NEXT: [[TMP31:%.*]] = extractelement [[TMP30]], i64 0 +; LOOP-DEL-NEXT: br i1 [[TMP31]], label [[MISMATCH_SVE_LOOP]], label [[WHILE_END]] +; LOOP-DEL: mismatch_sve_loop_found: +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP27]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; LOOP-DEL-NEXT: [[TMP32:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; LOOP-DEL-NEXT: [[TMP33:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP32]], i1 true) +; LOOP-DEL-NEXT: [[TMP34:%.*]] = zext i32 [[TMP33]] to i64 +; LOOP-DEL-NEXT: [[TMP35:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP34]] +; LOOP-DEL-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; LOOP-DEL-NEXT: br label [[WHILE_END]] +; LOOP-DEL: mismatch_loop_pre: +; LOOP-DEL-NEXT: br label [[MISMATCH_LOOP:%.*]] +; LOOP-DEL: mismatch_loop: +; LOOP-DEL-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ [[TMP0]], [[MISMATCH_LOOP_PRE]] ], [ [[TMP43:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; LOOP-DEL-NEXT: [[TMP37:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; LOOP-DEL-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1 +; LOOP-DEL-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[TMP37]] +; LOOP-DEL-NEXT: [[TMP41:%.*]] = load i8, ptr [[TMP40]], align 1 +; LOOP-DEL-NEXT: [[TMP42:%.*]] = icmp eq i8 [[TMP39]], [[TMP41]] +; LOOP-DEL-NEXT: br i1 [[TMP42]], label [[MISMATCH_LOOP_INC]], label [[WHILE_END]] +; LOOP-DEL: mismatch_loop_inc: +; LOOP-DEL-NEXT: [[TMP43]] = add i32 [[MISMATCH_INDEX]], 1 +; LOOP-DEL-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], [[N]] +; LOOP-DEL-NEXT: br i1 [[TMP44]], label [[WHILE_END]], label [[MISMATCH_LOOP]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[X]], [[ENTRY:%.*]] ], [ [[N]], [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX]], [[MISMATCH_LOOP]] ], [ [[N]], [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP36]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_extra_cmp( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]], i32 [[X:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: [[CMP_X:%.*]] = icmp ult i32 [[N]], [[X]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_X]], label [[PH:%.*]], label [[WHILE_END:%.*]] +; NO-TRANSFORM: ph: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[PH]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ], [ [[X]], [[ENTRY:%.*]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + %cmp.x = icmp ult i32 %n, %x + br i1 %cmp.x, label %ph, label %while.end + +ph: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %ph ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ], [ %x, %entry ] + ret i32 %inc.lcssa +} + +define void @compare_bytes_cleanup_block(ptr %src1, ptr %src2) { +; CHECK-LABEL: define void @compare_bytes_cleanup_block( +; CHECK-SAME: ptr [[SRC1:%.*]], ptr [[SRC2:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[MISMATCH_MIN_IT_CHECK:%.*]] +; CHECK: mismatch_min_it_check: +; CHECK-NEXT: br i1 false, label [[MISMATCH_MEM_CHECK:%.*]], label [[MISMATCH_LOOP_PRE:%.*]], !prof [[PROF0]] +; CHECK: mismatch_mem_check: +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[SRC1]], i64 1 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[SRC2]], i64 1 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP0]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[SRC1]], i64 0 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SRC2]], i64 0 +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP4]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP5]] to i64 +; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP3]], 12 +; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP6]], 12 +; CHECK-NEXT: [[TMP10:%.*]] = lshr i64 [[TMP2]], 12 +; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP7]], 12 +; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i64 [[TMP8]], [[TMP9]] +; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP10]], [[TMP11]] +; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[TMP13]] +; CHECK-NEXT: br i1 [[TMP14]], label [[MISMATCH_LOOP_PRE]], label [[MISMATCH_SVE_LOOP_PREHEADER:%.*]], !prof [[PROF1]] +; CHECK: mismatch_sve_loop_preheader: +; CHECK-NEXT: [[TMP15:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 1, i64 0) +; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP17:%.*]] = mul nuw nsw i64 [[TMP16]], 16 +; CHECK-NEXT: br label [[MISMATCH_SVE_LOOP:%.*]] +; CHECK: mismatch_sve_loop: +; CHECK-NEXT: [[MISMATCH_SVE_LOOP_PRED:%.*]] = phi [ [[TMP15]], [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP26:%.*]], [[MISMATCH_SVE_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[MISMATCH_SVE_INDEX:%.*]] = phi i64 [ 1, [[MISMATCH_SVE_LOOP_PREHEADER]] ], [ [[TMP25:%.*]], [[MISMATCH_SVE_LOOP_INC]] ] +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[SRC1]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP19:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP18]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[SRC2]], i64 [[MISMATCH_SVE_INDEX]] +; CHECK-NEXT: [[TMP21:%.*]] = call @llvm.masked.load.nxv16i8.p0(ptr [[TMP20]], i32 1, [[MISMATCH_SVE_LOOP_PRED]], zeroinitializer) +; CHECK-NEXT: [[TMP22:%.*]] = icmp ne [[TMP19]], [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = select [[MISMATCH_SVE_LOOP_PRED]], [[TMP22]], zeroinitializer +; CHECK-NEXT: [[TMP24:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1( [[TMP23]]) +; CHECK-NEXT: br i1 [[TMP24]], label [[MISMATCH_SVE_LOOP_FOUND:%.*]], label [[MISMATCH_SVE_LOOP_INC]] +; CHECK: mismatch_sve_loop_inc: +; CHECK-NEXT: [[TMP25]] = add nuw nsw i64 [[MISMATCH_SVE_INDEX]], [[TMP17]] +; CHECK-NEXT: [[TMP26]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP25]], i64 0) +; CHECK-NEXT: [[TMP27:%.*]] = extractelement [[TMP26]], i64 0 +; CHECK-NEXT: br i1 [[TMP27]], label [[MISMATCH_SVE_LOOP]], label [[MISMATCH_END:%.*]] +; CHECK: mismatch_sve_loop_found: +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_PRED:%.*]] = phi [ [[TMP23]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_LAST_LOOP_PRED:%.*]] = phi [ [[MISMATCH_SVE_LOOP_PRED]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[MISMATCH_SVE_FOUND_INDEX:%.*]] = phi i64 [ [[MISMATCH_SVE_INDEX]], [[MISMATCH_SVE_LOOP]] ] +; CHECK-NEXT: [[TMP28:%.*]] = and [[MISMATCH_SVE_LAST_LOOP_PRED]], [[MISMATCH_SVE_FOUND_PRED]] +; CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( [[TMP28]], i1 true) +; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 +; CHECK-NEXT: [[TMP31:%.*]] = add nuw nsw i64 [[MISMATCH_SVE_FOUND_INDEX]], [[TMP30]] +; CHECK-NEXT: [[TMP32:%.*]] = trunc i64 [[TMP31]] to i32 +; CHECK-NEXT: br label [[MISMATCH_END]] +; CHECK: mismatch_loop_pre: +; CHECK-NEXT: br label [[MISMATCH_LOOP:%.*]] +; CHECK: mismatch_loop: +; CHECK-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ 1, [[MISMATCH_LOOP_PRE]] ], [ [[TMP39:%.*]], [[MISMATCH_LOOP_INC:%.*]] ] +; CHECK-NEXT: [[TMP33:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; CHECK-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[SRC1]], i64 [[TMP33]] +; CHECK-NEXT: [[TMP35:%.*]] = load i8, ptr [[TMP34]], align 1 +; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[SRC2]], i64 [[TMP33]] +; CHECK-NEXT: [[TMP37:%.*]] = load i8, ptr [[TMP36]], align 1 +; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i8 [[TMP35]], [[TMP37]] +; CHECK-NEXT: br i1 [[TMP38]], label [[MISMATCH_LOOP_INC]], label [[MISMATCH_END]] +; CHECK: mismatch_loop_inc: +; CHECK-NEXT: [[TMP39]] = add i32 [[MISMATCH_INDEX]], 1 +; CHECK-NEXT: [[TMP40:%.*]] = icmp eq i32 [[TMP39]], 0 +; CHECK-NEXT: br i1 [[TMP40]], label [[MISMATCH_END]], label [[MISMATCH_LOOP]] +; CHECK: mismatch_end: +; CHECK-NEXT: [[MISMATCH_RESULT:%.*]] = phi i32 [ 0, [[MISMATCH_LOOP_INC]] ], [ [[MISMATCH_INDEX]], [[MISMATCH_LOOP]] ], [ 0, [[MISMATCH_SVE_LOOP_INC]] ], [ [[TMP32]], [[MISMATCH_SVE_LOOP_FOUND]] ] +; CHECK-NEXT: br i1 true, label [[BYTE_COMPARE:%.*]], label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN:%.*]] = phi i32 [ [[MISMATCH_RESULT]], [[WHILE_BODY:%.*]] ], [ 0, [[MISMATCH_END]] ] +; CHECK-NEXT: [[INC:%.*]] = add i32 [[LEN]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], 0 +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[CLEANUP_THREAD:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[MISMATCH_RESULT]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr i8, ptr [[SRC1]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP41:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[SRC2]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP41]], [[TMP42]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[IF_END:%.*]] +; CHECK: byte.compare: +; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i32 [[MISMATCH_RESULT]], 0 +; CHECK-NEXT: br i1 [[TMP43]], label [[CLEANUP_THREAD]], label [[IF_END]] +; CHECK: cleanup.thread: +; CHECK-NEXT: ret void +; CHECK: if.end: +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[MISMATCH_RESULT]], [[WHILE_BODY]] ], [ [[MISMATCH_RESULT]], [[BYTE_COMPARE]] ] +; CHECK-NEXT: ret void +; +; LOOP-DEL-LABEL: define void @compare_bytes_cleanup_block( +; LOOP-DEL-SAME: ptr [[SRC1:%.*]], ptr [[SRC2:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[MISMATCH_LOOP:%.*]] +; LOOP-DEL: mismatch_loop: +; LOOP-DEL-NEXT: [[MISMATCH_INDEX:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[TMP6:%.*]], [[MISMATCH_LOOP]] ] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = zext i32 [[MISMATCH_INDEX]] to i64 +; LOOP-DEL-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[SRC1]], i64 [[TMP0]] +; LOOP-DEL-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 +; LOOP-DEL-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[SRC2]], i64 [[TMP0]] +; LOOP-DEL-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; LOOP-DEL-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP2]], [[TMP4]] +; LOOP-DEL-NEXT: [[TMP6]] = add i32 [[MISMATCH_INDEX]], 1 +; LOOP-DEL-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 +; LOOP-DEL-NEXT: [[OR_COND:%.*]] = or i1 [[TMP5]], [[TMP7]] +; LOOP-DEL-NEXT: br i1 [[OR_COND]], label [[COMMON_RET:%.*]], label [[MISMATCH_LOOP]] +; LOOP-DEL: common.ret: +; LOOP-DEL-NEXT: ret void +; +; NO-TRANSFORM-LABEL: define void @compare_bytes_cleanup_block( +; NO-TRANSFORM-SAME: ptr [[SRC1:%.*]], ptr [[SRC2:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN:%.*]] = phi i32 [ [[INC:%.*]], [[WHILE_BODY:%.*]] ], [ 0, [[ENTRY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], 0 +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[CLEANUP_THREAD:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr i8, ptr [[SRC1]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[SRC2]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[IF_END:%.*]] +; NO-TRANSFORM: cleanup.thread: +; NO-TRANSFORM-NEXT: ret void +; NO-TRANSFORM: if.end: +; NO-TRANSFORM-NEXT: [[RES:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ] +; NO-TRANSFORM-NEXT: ret void +; +entry: + br label %while.cond + +while.cond: + %len = phi i32 [ %inc, %while.body ], [ 0, %entry ] + %inc = add i32 %len, 1 + %cmp.not = icmp eq i32 %inc, 0 + br i1 %cmp.not, label %cleanup.thread, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr i8, ptr %src1, i64 %idxprom + %0 = load i8, ptr %arrayidx, align 1 + %arrayidx2 = getelementptr i8, ptr %src2, i64 %idxprom + %1 = load i8, ptr %arrayidx2, align 1 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %if.end + +cleanup.thread: + ret void + +if.end: + %res = phi i32 [ %inc, %while.body ] + ret void +} + +; +; NEGATIVE TESTS +; + + +; Similar to @compare_bytes_simple, except in the while.end block we have an extra PHI +; with unique values for each incoming block from the loop. +define i32 @compare_bytes_simple2(ptr %a, ptr %b, ptr %c, ptr %d, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_simple2( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: [[FINAL_PTR:%.*]] = phi ptr [ [[C]], [[WHILE_BODY]] ], [ [[D]], [[WHILE_COND]] ] +; CHECK-NEXT: store i32 [[INC_LCSSA]], ptr [[FINAL_PTR]], align 4 +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple2( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: [[FINAL_PTR:%.*]] = phi ptr [ [[C]], [[WHILE_BODY]] ], [ [[D]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: store i32 [[INC_LCSSA]], ptr [[FINAL_PTR]], align 4 +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple2( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[FINAL_PTR:%.*]] = phi ptr [ [[C]], [[WHILE_BODY]] ], [ [[D]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: store i32 [[INC_LCSSA]], ptr [[FINAL_PTR]], align 4 +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + %final_ptr = phi ptr [ %c, %while.body ], [ %d, %while.cond ] + store i32 %inc.lcssa, ptr %final_ptr + ret i32 %inc.lcssa +} + + +define i32 @compare_bytes_sign_ext(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_sign_ext( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_sign_ext( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = sext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_sign_ext( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = sext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = sext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i32 %inc.lcssa +} + + +define i32 @compare_bytes_outside_uses(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_outside_uses( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[IV]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[RES:%.*]] = phi i1 [ [[CMP_NOT2]], [[WHILE_BODY]] ], [ [[CMP_NOT]], [[WHILE_COND]] ] +; CHECK-NEXT: [[EXT_RES:%.*]] = zext i1 [[RES]] to i32 +; CHECK-NEXT: ret i32 [[EXT_RES]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_outside_uses( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[IV]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[RES:%.*]] = phi i1 [ [[CMP_NOT2]], [[WHILE_BODY]] ], [ [[CMP_NOT]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: [[EXT_RES:%.*]] = zext i1 [[RES]] to i32 +; LOOP-DEL-NEXT: ret i32 [[EXT_RES]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_outside_uses( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[IV]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[RES:%.*]] = phi i1 [ [[CMP_NOT2]], [[WHILE_BODY]] ], [ [[CMP_NOT]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[EXT_RES:%.*]] = zext i1 [[RES]] to i32 +; NO-TRANSFORM-NEXT: ret i32 [[EXT_RES]] +; +entry: + br label %while.cond + +while.cond: + %iv = phi i32 [ 0, %entry ], [ %inc, %while.body ] + %inc = add i32 %iv, 1 + %cmp.not = icmp eq i32 %inc, %len + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %res = phi i1 [ %cmp.not2, %while.body ], [ %cmp.not, %while.cond ] + %ext_res = zext i1 %res to i32 + ret i32 %ext_res +} + +define i64 @compare_bytes_i64_index(ptr %a, ptr %b, i64 %len, i64 %n) { +; CHECK-LABEL: define i64 @compare_bytes_i64_index( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[LEN:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i64 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i64 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INC]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INC]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i64 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: ret i64 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i64 @compare_bytes_i64_index( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[LEN:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i64 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i64 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INC]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INC]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i64 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: ret i64 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i64 @compare_bytes_i64_index( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[LEN:%.*]], i64 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i64 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i64 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INC]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INC]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i64 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i64 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i64 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i64 %len.addr, 1 + %cmp.not = icmp eq i64 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %inc + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %inc + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i64 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i64 %inc.lcssa +} + +define i32 @compare_bytes_simple_wrong_icmp1(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_simple_wrong_icmp1( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp ne i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple_wrong_icmp1( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp ne i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple_wrong_icmp1( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp ne i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp ne i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i32 %inc.lcssa +} + +define i32 @compare_bytes_simple_wrong_icmp2(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_simple_wrong_icmp2( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_BODY]], label [[WHILE_END:%.*]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple_wrong_icmp2( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_BODY]], label [[WHILE_END:%.*]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple_wrong_icmp2( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_BODY]], label [[WHILE_END:%.*]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.body, label %while.end + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i32 %inc.lcssa +} + +define i32 @compare_bytes_simple_wrong_icmp3(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_simple_wrong_icmp3( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp ne i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple_wrong_icmp3( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp ne i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple_wrong_icmp3( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp ne i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp ne i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i32 %inc.lcssa +} + +define i32 @compare_bytes_simple_wrong_icmp4(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_simple_wrong_icmp4( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_END]], label [[WHILE_COND]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple_wrong_icmp4( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_END]], label [[WHILE_COND]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple_wrong_icmp4( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_END]], label [[WHILE_COND]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.end, label %while.cond + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i32 %inc.lcssa +} + +define i32 @compare_bytes_bad_load_type(ptr %a, ptr %b, i32 %len, i32 %n) { +; CHECK-LABEL: define i32 @compare_bytes_bad_load_type( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i16 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: ret i32 [[INC_LCSSA]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_bad_load_type( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i16 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: ret i32 [[INC_LCSSA]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_bad_load_type( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[N:%.*]]) { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i16 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: ret i32 [[INC_LCSSA]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i16, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i16, ptr %arrayidx2 + %cmp.not2 = icmp eq i16 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + ret i32 %inc.lcssa +} + + +define i32 @compare_bytes_simple_optsize(ptr %a, ptr %b, i32 %len, i32 %extra, i32 %n) optsize { +; CHECK-LABEL: define i32 @compare_bytes_simple_optsize( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ] +; CHECK-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; CHECK-NEXT: ret i32 [[RES]] +; +; LOOP-DEL-LABEL: define i32 @compare_bytes_simple_optsize( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR1:[0-9]+]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; LOOP-DEL-NEXT: ret i32 [[RES]] +; +; NO-TRANSFORM-LABEL: define i32 @compare_bytes_simple_optsize( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; NO-TRANSFORM-NEXT: ret i32 [[RES]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + %extra.phi = phi i32 [ %extra, %while.body ], [ %extra, %while.cond ] + %res = add i32 %inc.lcssa, %extra.phi + ret i32 %res +} + diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn index 4642c8a70672..43c01cf5c766 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn @@ -129,6 +129,7 @@ static_library("LLVMAArch64CodeGen") { "AArch64ISelLowering.cpp", "AArch64InstrInfo.cpp", "AArch64LoadStoreOptimizer.cpp", + "AArch64LoopIdiomTransform.cpp", "AArch64LowerHomogeneousPrologEpilog.cpp", "AArch64MCInstLower.cpp", "AArch64MIPeepholeOpt.cpp", -- GitLab From 19870ed9c3238f348bf82dcc2b2e0a2894536874 Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Tue, 9 Jan 2024 19:43:14 +0800 Subject: [PATCH 186/652] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (#75580) Since Knight Landing and Knight Mill microarchitectures are EOL, we would like to remove intrinsic supports for its specific ISA in LLVM 19. In LLVM 18, we will first emit a warning for the usage. --- clang/docs/ReleaseNotes.rst | 8 ++++++++ clang/include/clang/Basic/DiagnosticCommonKinds.td | 3 +++ clang/lib/Basic/Targets/X86.cpp | 3 +++ clang/test/CodeGen/X86/avx512er-builtins.c | 2 +- clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +- clang/test/Driver/cl-x86-flags.c | 10 ++++++++-- clang/test/Frontend/x86-target-cpu.c | 10 ++++++++-- 7 files changed, 32 insertions(+), 6 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 980be4fe0ef7..1b2d7c86a962 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -936,6 +936,14 @@ X86 Support - Support ISA of ``AVX10.1``. - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported. - Added ABI handling for ``__float128`` to match with GCC. +- Emit warnings for options to enable knl/knm specific ISAs: AVX512PF, AVX512ER + and PREFETCHWT1. From next version (LLVM 19), these ISAs' intrinsic supports + will be deprecated: + * intrinsic series of *_exp2a23_* + * intrinsic series of *_rsqrt28_* + * intrinsic series of *_rcp28_* + * intrinsic series of *_prefetch_i[3|6][2|4]gather_* + * intrinsic series of *_prefetch_i[3|6][2|4]scatter_* Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index 65a33f61a694..72952b08c04a 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -349,6 +349,9 @@ def warn_invalid_feature_combination : Warning< def warn_target_unrecognized_env : Warning< "mismatch between architecture and environment in target triple '%0'; did you mean '%1'?">, InGroup; +def warn_knl_knm_isa_support_removed : Warning< + "KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.">, + InGroup>; // Source manager def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 3deaa19f8d4f..64e281b888a9 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -295,11 +295,13 @@ bool X86TargetInfo::handleTargetFeatures(std::vector &Features, HasAVX512BF16 = true; } else if (Feature == "+avx512er") { HasAVX512ER = true; + Diags.Report(diag::warn_knl_knm_isa_support_removed); } else if (Feature == "+avx512fp16") { HasAVX512FP16 = true; HasLegalHalfType = true; } else if (Feature == "+avx512pf") { HasAVX512PF = true; + Diags.Report(diag::warn_knl_knm_isa_support_removed); } else if (Feature == "+avx512dq") { HasAVX512DQ = true; } else if (Feature == "+avx512bitalg") { @@ -358,6 +360,7 @@ bool X86TargetInfo::handleTargetFeatures(std::vector &Features, HasPREFETCHI = true; } else if (Feature == "+prefetchwt1") { HasPREFETCHWT1 = true; + Diags.Report(diag::warn_knl_knm_isa_support_removed); } else if (Feature == "+clzero") { HasCLZERO = true; } else if (Feature == "+cldemote") { diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c b/clang/test/CodeGen/X86/avx512er-builtins.c index ee31236a3c01..11ec6aabec1e 100644 --- a/clang/test/CodeGen/X86/avx512er-builtins.c +++ b/clang/test/CodeGen/X86/avx512er-builtins.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er -emit-llvm -o - -Wall | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c b/clang/test/CodeGen/X86/avx512pf-builtins.c index 4ca70f578796..3a117ed6a946 100644 --- a/clang/test/CodeGen/X86/avx512pf-builtins.c +++ b/clang/test/CodeGen/X86/avx512pf-builtins.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall | FileCheck %s #include diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c index 51b16f0ce354..716b02f02a15 100644 --- a/clang/test/Driver/cl-x86-flags.c +++ b/clang/test/Driver/cl-x86-flags.c @@ -69,7 +69,10 @@ // RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s | FileCheck -check-prefix=avx2 %s // avx2: invalid /arch: argument -// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify -DTEST_32_ARCH_AVX512F -- %s +// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s +// KNL1-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// KNL1-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// KNL1-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} #if defined(TEST_32_ARCH_AVX512F) #if _M_IX86_FP != 2 || !__AVX__ || !__AVX2__ || !__AVX512F__ || __AVX512BW__ #error fail @@ -109,7 +112,10 @@ // RUN: %clang_cl -m64 -arch:avx2 --target=x86_64-pc-windows -### -- 2>&1 %s | FileCheck -check-prefix=avx264 %s // avx264: invalid /arch: argument -// RUN: %clang_cl -m64 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify -DTEST_64_ARCH_AVX512F -- %s +// RUN: %clang_cl -m64 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify=KNL2 -DTEST_64_ARCH_AVX512F -- %s +// KNL2-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// KNL2-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// KNL2-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} #if defined(TEST_64_ARCH_AVX512F) #if _M_IX86_FP || !__AVX__ || !__AVX2__ || !__AVX512F__ || __AVX512BW__ #error fail diff --git a/clang/test/Frontend/x86-target-cpu.c b/clang/test/Frontend/x86-target-cpu.c index 6c8502ac2c21..6b99b2c8574a 100644 --- a/clang/test/Frontend/x86-target-cpu.c +++ b/clang/test/Frontend/x86-target-cpu.c @@ -15,8 +15,14 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu cannonlake -verify %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu icelake-client -verify %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu icelake-server -verify %s -// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu knl -verify %s -// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu knm -verify %s +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu knl -verify=knl %s +// knl-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// knl-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// knl-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu knm -verify=knm %s +// knm-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// knm-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} +// knm-warning@*:* {{KNL, KNM related Intel Xeon Phi CPU's specific ISA's supports will be removed in LLVM 19.}} // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bonnell -verify %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu silvermont -verify %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu k8 -verify %s -- GitLab From d5985d4c70bad7b25740027cb873c91a31ff0659 Mon Sep 17 00:00:00 2001 From: Kohei Yamaguchi Date: Tue, 9 Jan 2024 20:45:40 +0900 Subject: [PATCH 187/652] [mlir][docs] Fix a broken passes documentation (#77402) - Add EmitC passes into Pass.md - Modify header level of the pass description to under the `LegalizeVectorStorage` pass --- mlir/docs/Passes.md | 4 ++++ mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/mlir/docs/Passes.md b/mlir/docs/Passes.md index 66e2dc077f98..ee7d47cc0227 100644 --- a/mlir/docs/Passes.md +++ b/mlir/docs/Passes.md @@ -40,6 +40,10 @@ This document describes the available MLIR passes and their contracts. [include "AsyncPasses.md"] +## 'emitc' Dialect Passes + +[include "EmitCPasses.md"] + ## 'func' Dialect Passes [include "FuncPasses.md"] diff --git a/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td b/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td index d7cb309db525..b9b06cec1f97 100644 --- a/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td @@ -21,7 +21,7 @@ def LegalizeVectorStorage This pass currently addresses two issues. - ## Loading and storing predicate types + #### Loading and storing predicate types It is only legal to load/store predicate types equal to (or greater than) a full predicate register, which in MLIR is `vector<[16]xi1>`. Smaller @@ -49,7 +49,7 @@ def LegalizeVectorStorage %reload = arm_sve.convert_from_svbool %reload_svbool : vector<[4]xi1> ``` - ## Relax alignments for SVE vector allocas + #### Relax alignments for SVE vector allocas The storage for SVE vector types only needs to have an alignment that matches the element type (for example 4 byte alignment for `f32`s). However, -- GitLab From 62b30e7948d1278900585518523794f9286fa5c9 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Tue, 9 Jan 2024 19:47:42 +0800 Subject: [PATCH 188/652] [CodeGen] Fix friend declaration in SSPLayoutAnalysis (#77447) --- llvm/include/llvm/CodeGen/StackProtector.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/CodeGen/StackProtector.h b/llvm/include/llvm/CodeGen/StackProtector.h index 068990f69f2e..eb5d9d0caebc 100644 --- a/llvm/include/llvm/CodeGen/StackProtector.h +++ b/llvm/include/llvm/CodeGen/StackProtector.h @@ -66,7 +66,7 @@ public: }; class SSPLayoutAnalysis : public AnalysisInfoMixin { - friend struct AnalysisInfoMixin; + friend AnalysisInfoMixin; using SSPLayoutMap = SSPLayoutInfo::SSPLayoutMap; static AnalysisKey Key; -- GitLab From e7636b1094ba53fe4edc16dd52ef981c01e35ceb Mon Sep 17 00:00:00 2001 From: paperchalice Date: Tue, 9 Jan 2024 19:49:05 +0800 Subject: [PATCH 189/652] [NewPM] Update `CodeGenPreparePass` reference in `CodeGenPassBuilder.h` (#77446) Reland #77054. --- llvm/include/llvm/CodeGen/CodeGenPassBuilder.h | 3 ++- llvm/include/llvm/CodeGen/MachinePassRegistry.def | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index a1382a5e8e40..fa81ff504ac6 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -24,6 +24,7 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" #include "llvm/CodeGen/CallBrPrepare.h" +#include "llvm/CodeGen/CodeGenPrepare.h" #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/ExpandReductions.h" @@ -735,7 +736,7 @@ void CodeGenPassBuilder::addPassesToHandleExceptions( template void CodeGenPassBuilder::addCodeGenPrepare(AddIRPass &addPass) const { if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableCGP) - addPass(CodeGenPreparePass()); + addPass(CodeGenPreparePass(&TM)); // TODO: Default ctor'd RewriteSymbolPass is no-op. // addPass(RewriteSymbolPass()); } diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index cbfd4327da6e..e789747036ef 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -44,6 +44,7 @@ FUNCTION_ANALYSIS("targetir", TargetIRAnalysis, #endif FUNCTION_PASS("callbrprepare", CallBrPreparePass, ()) FUNCTION_PASS("cfguard", CFGuardPass, ()) +FUNCTION_PASS("codegenprepare", CodeGenPreparePass, (TM)) FUNCTION_PASS("consthoist", ConstantHoistingPass, ()) FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass, (TM)) FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass, (false)) @@ -135,7 +136,6 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) #endif DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) -DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ()) #undef DUMMY_FUNCTION_PASS #ifndef DUMMY_MACHINE_MODULE_PASS -- GitLab From 0b9b00c8c86d42f72f8abf379052a451778dcc63 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 9 Jan 2024 11:52:51 +0000 Subject: [PATCH 190/652] [AMDGPU] Make isScalarLoadLegal a member of AMDGPURegisterBankInfo. NFC. --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index ecb7bb9d1d97..391c2b9ec256 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -441,7 +441,7 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects( // FIXME: Returns uniform if there's no source value information. This is // probably wrong. -static bool isScalarLoadLegal(const MachineInstr &MI) { +bool AMDGPURegisterBankInfo::isScalarLoadLegal(const MachineInstr &MI) const { if (!MI.hasOneMemOperand()) return false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h index 2bb5ef57fe03..5f550b426ec0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h @@ -176,6 +176,8 @@ public: const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override; + bool isScalarLoadLegal(const MachineInstr &MI) const; + InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override; -- GitLab From 4f7c402d9ff1b2c908b97b78baf84157f08745e8 Mon Sep 17 00:00:00 2001 From: Saiyedul Islam Date: Tue, 9 Jan 2024 17:31:42 +0530 Subject: [PATCH 191/652] [AMDGPU][NFC] Update left over tests for COV5 (#76984) Update AMDGPU CodeGen lit tests to check for COV5 ABI. --- llvm/test/CodeGen/AMDGPU/attributor-noopt.ll | 11 ++-- .../AMDGPU/call-alias-register-usage-agpr.ll | 9 ++-- .../AMDGPU/call-alias-register-usage0.ll | 5 +- .../AMDGPU/call-alias-register-usage1.ll | 5 +- .../AMDGPU/call-alias-register-usage2.ll | 5 +- .../AMDGPU/call-alias-register-usage3.ll | 5 +- .../CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll | 9 ++-- llvm/test/CodeGen/AMDGPU/fneg-fabs.ll | 5 +- .../AMDGPU/gfx11-user-sgpr-init16-bug.ll | 31 ++++++----- .../CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll | 18 ++++--- .../AMDGPU/promote-alloca-calling-conv.ll | 5 +- .../CodeGen/AMDGPU/reqd-work-group-size.ll | 51 ++++++++++--------- .../CodeGen/AMDGPU/simple-indirect-call.ll | 9 ++-- 13 files changed, 106 insertions(+), 62 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/attributor-noopt.ll b/llvm/test/CodeGen/AMDGPU/attributor-noopt.ll index d83884635546..a374689da573 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-noopt.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-noopt.ll @@ -1,5 +1,6 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=OPT %s -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=NOOPT %s +; RUN: sed 's/CODE_OBJECT_VERSION/500/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck -check-prefix=OPT %s +; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck -check-prefixes=NOOPT,COV4 %s +; RUN: sed 's/CODE_OBJECT_VERSION/500/g' %s | llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck -check-prefixes=NOOPT,COV5 %s ; Check that AMDGPUAttributor is not run with -O0. ; OPT: .amdhsa_user_sgpr_private_segment_buffer 1 @@ -18,7 +19,8 @@ ; NOOPT: .amdhsa_user_sgpr_private_segment_buffer 1 ; NOOPT: .amdhsa_user_sgpr_dispatch_ptr 1 -; NOOPT: .amdhsa_user_sgpr_queue_ptr 1 +; COV4: .amdhsa_user_sgpr_queue_ptr 1 +; COV5: .amdhsa_user_sgpr_queue_ptr 0 ; NOOPT: .amdhsa_user_sgpr_kernarg_segment_ptr 1 ; NOOPT: .amdhsa_user_sgpr_dispatch_id 1 ; NOOPT: .amdhsa_user_sgpr_flat_scratch_init 0 @@ -32,3 +34,6 @@ define amdgpu_kernel void @foo() { ret void } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 CODE_OBJECT_VERSION} diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll index 6ff2dbabc8ec..72bb515ba57e 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll @@ -9,10 +9,10 @@ ; ALL-LABEL: {{^}}kernel: ; GFX908: .amdhsa_next_free_vgpr 32 -; GFX908-NEXT: .amdhsa_next_free_sgpr 36 +; GFX908-NEXT: .amdhsa_next_free_sgpr 33 -; GFX90A: .amdhsa_next_free_vgpr 65 -; GFX90A-NEXT: .amdhsa_next_free_sgpr 36 +; GFX90A: .amdhsa_next_free_vgpr 59 +; GFX90A-NEXT: .amdhsa_next_free_sgpr 33 ; GFX90A-NEXT: .amdhsa_accum_offset 32 define amdgpu_kernel void @kernel() #0 { bb: @@ -29,3 +29,6 @@ bb: attributes #0 = { noinline norecurse nounwind optnone } attributes #1 = { noinline norecurse nounwind readnone willreturn } attributes #2 = { nounwind readnone willreturn } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll index 797376535cde..6afc90639dce 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: {{^}}kernel0: ; CHECK: .amdhsa_next_free_vgpr 53 -; CHECK-NEXT: .amdhsa_next_free_sgpr 36 +; CHECK-NEXT: .amdhsa_next_free_sgpr 33 define amdgpu_kernel void @kernel0() #0 { bb: call void @alias0() #2 @@ -24,3 +24,6 @@ bb: attributes #0 = { noinline norecurse nounwind optnone } attributes #1 = { noinline norecurse nounwind readnone willreturn } attributes #2 = { nounwind readnone willreturn } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll index 79bb2fb64117..137bb13330fd 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: {{^}}kernel1: ; CHECK: .amdhsa_next_free_vgpr 41 -; CHECK-NEXT: .amdhsa_next_free_sgpr 36 +; CHECK-NEXT: .amdhsa_next_free_sgpr 33 define amdgpu_kernel void @kernel1() #0 { bb: call void asm sideeffect "; clobber v40 ", "~{v40}"() @@ -27,3 +27,6 @@ bb: attributes #0 = { noinline norecurse nounwind optnone } attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="8,10" } attributes #2 = { nounwind readnone willreturn } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll index 5745dd9fdb67..2800ed635bdb 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: {{^}}kernel2: ; CHECK: .amdhsa_next_free_vgpr 53 -; CHECK-NEXT: .amdhsa_next_free_sgpr 36 +; CHECK-NEXT: .amdhsa_next_free_sgpr 33 define amdgpu_kernel void @kernel2() #0 { bb: call void @alias2() #2 @@ -24,3 +24,6 @@ bb: attributes #0 = { noinline norecurse nounwind optnone } attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="4,10" } attributes #2 = { nounwind readnone willreturn } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll index b922297c493f..f7c0a57f5217 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: {{^}}kernel3: ; CHECK: .amdhsa_next_free_vgpr 253 -; CHECK-NEXT: .amdhsa_next_free_sgpr 36 +; CHECK-NEXT: .amdhsa_next_free_sgpr 33 define amdgpu_kernel void @kernel3() #0 { bb: call void @alias3() #2 @@ -24,3 +24,6 @@ bb: attributes #0 = { noinline norecurse nounwind optnone } attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="1,1" } attributes #2 = { nounwind readnone willreturn } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll index 084b9686f88a..ce478d41380a 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll @@ -28,7 +28,6 @@ define i32 @divergent_lshr_and_cmp(i32 %x) { entry: %0 = and i32 %x, 2 %1 = icmp ne i32 %0, 0 - ; Prevent removal of truncate in SDag by inserting llvm.amdgcn.if br i1 %1, label %out.true, label %out.else out.true: @@ -43,9 +42,9 @@ define amdgpu_kernel void @uniform_opt_lshr_and_cmp(ptr addrspace(1) %out, i32 % ; GCN-LABEL: name: uniform_opt_lshr_and_cmp ; GCN: bb.0.entry: ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) - ; GCN-NEXT: liveins: $sgpr4_sgpr5 + ; GCN-NEXT: liveins: $sgpr2_sgpr3 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr2_sgpr3 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 9, 0 :: (dereferenceable invariant load (s64) from %ir.out.kernarg.offset, align 4, addrspace 4) ; GCN-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 11, 0 :: (dereferenceable invariant load (s32) from %ir.x.kernarg.offset, addrspace 4) ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX2_IMM]] @@ -84,7 +83,6 @@ define amdgpu_kernel void @uniform_opt_lshr_and_cmp(ptr addrspace(1) %out, i32 % entry: %0 = and i32 %x, 2 %1 = icmp ne i32 %0, 0 - ; Don't optimize the truncate in the SDag away. br i1 %1, label %out.true, label %out.else out.true: @@ -96,3 +94,6 @@ out.else: store i1 %1, ptr addrspace(1) %out ret void } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll index e2e1effc9b40..3be2d9435119 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll @@ -49,7 +49,7 @@ define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) { ; R600: |PV.{{[XYZW]}}| ; R600: -PV -; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 +; SI: s_load_dwordx2 s[0:1], s[2:3], 0x9 define amdgpu_kernel void @fneg_fabsf_fn_free_f32(ptr addrspace(1) %out, i32 %in) { %bc = bitcast i32 %in to float %fabs = call float @fabsf(float %bc) @@ -109,3 +109,6 @@ declare float @fabsf(float) readnone declare float @llvm.fabs.f32(float) readnone declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll index ea5add023d15..3973cf1eec83 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll @@ -36,6 +36,7 @@ ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_wavefront_size32 +; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_enable_private_segment 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 @@ -64,6 +65,7 @@ define amdgpu_kernel void @minimal_kernel_inputs() { ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_wavefront_size32 +; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_enable_private_segment 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 @@ -81,7 +83,7 @@ define amdgpu_kernel void @minimal_kernel_inputs_with_stack() { } ; GCN-LABEL: {{^}}queue_ptr: -; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] +; GCN: global_load_u8 v{{[0-9]+}}, ; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15 ; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s2 @@ -91,11 +93,12 @@ define amdgpu_kernel void @minimal_kernel_inputs_with_stack() { ; WORKAROUND: .amdhsa_user_sgpr_count 15 ; NOWORKAROUND: .amdhsa_user_sgpr_count 2 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 -; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 -; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 +; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 +; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_wavefront_size32 +; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_enable_private_segment 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 @@ -117,16 +120,16 @@ define amdgpu_kernel void @queue_ptr() { ; WORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s14 ; WORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s15 -; NOWORKAROUND: v_mov_b32_e32 [[V_X:v[0-9]+]], s8 -; NOWORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s9 -; NOWORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s10 +; NOWORKAROUND: v_mov_b32_e32 [[V_X:v[0-9]+]], s6 +; NOWORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s7 +; NOWORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s8 ; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] +; GCN: global_load_u8 v{{[0-9]+}}, ; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[2:3] -; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5] -; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6 -; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7 +; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s4 +; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s5 ; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_X]], off ; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Y]], off @@ -135,13 +138,14 @@ define amdgpu_kernel void @queue_ptr() { ; GCN: .amdhsa_kernel all_inputs ; WORKAROUND: .amdhsa_user_sgpr_count 13 -; NOWORKAROUND: .amdhsa_user_sgpr_count 8 +; NOWORKAROUND: .amdhsa_user_sgpr_count 6 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1 -; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 +; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 1 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_wavefront_size32 +; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_enable_private_segment 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1 @@ -149,7 +153,7 @@ define amdgpu_kernel void @queue_ptr() { ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 ; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 ; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 -; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 8 +; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 6 define amdgpu_kernel void @all_inputs() { %alloca = alloca i32, addrspace(5) store volatile i32 0, ptr addrspace(5) %alloca @@ -188,3 +192,6 @@ declare align 4 ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0 declare i64 @llvm.amdgcn.dispatch.id() #0 attributes #0 = { nounwind readnone speculatable willreturn } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll index 7479fc87e318..2672c12ecf1f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll @@ -1,15 +1,16 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIT %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIH %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: {{^}}is_local_vgpr: ; GCN-DAG: {{flat|global|buffer}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]] -; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 +; CI-DAG: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX9: s_mov_b64 s[{{[0-9]+}}:[[HI:[0-9]+]]], src_shared_base ; GFX9: v_cmp_eq_u32_e32 vcc, s[[HI]], v[[PTR_HI]] -; CI: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]] +; CIT: v_cmp_eq_u32_e32 vcc, s4, v[[PTR_HI]] +; CIH: v_cmp_eq_u32_e32 vcc, s2, v[[PTR_HI]] ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc define amdgpu_kernel void @is_local_vgpr(ptr addrspace(1) %ptr.ptr) { %id = call i32 @llvm.amdgcn.workitem.id.x() @@ -25,15 +26,15 @@ define amdgpu_kernel void @is_local_vgpr(ptr addrspace(1) %ptr.ptr) { ; select and vcc branch. ; GCN-LABEL: {{^}}is_local_sgpr: -; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} +; CI-DAG: s_load_dword s0, s[4:5], 0x1 -; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}} +; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[4:5], 0x33{{$}} ; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[4:5], 0x4{{$}} ; GFX9: s_mov_b64 s[{{[0-9]+}}:[[HI:[0-9]+]]], src_shared_base ; GFX9: s_cmp_eq_u32 [[PTR_HI]], s[[HI]] -; CI: s_cmp_eq_u32 [[PTR_HI]], [[APERTURE]] +; CI: s_cmp_eq_u32 s0, [[PTR_HI]] ; GCN: s_cbranch_vccnz define amdgpu_kernel void @is_local_sgpr(ptr %ptr) { %val = call i1 @llvm.amdgcn.is.shared(ptr %ptr) @@ -51,3 +52,6 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i1 @llvm.amdgcn.is.shared(ptr nocapture) #0 attributes #0 = { nounwind readnone speculatable } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll index ec83d7f313d6..a8bb36bc0d19 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll @@ -77,7 +77,7 @@ declare i32 @foo(ptr addrspace(5)) #0 ; ASM: buffer_store_dword ; ASM: buffer_store_dword ; ASM: s_swappc_b64 -; ASM: ScratchSize: 16400 +; ASM: ScratchSize: 16 define amdgpu_kernel void @call_private(ptr addrspace(1) %out, i32 %in) #0 { entry: %tmp = alloca [2 x i32], addrspace(5) @@ -94,3 +94,6 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1 attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" } attributes #1 = { nounwind readnone } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll b/llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll index ecdc3845efc4..7d7917e0b20c 100644 --- a/llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll +++ b/llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll @@ -24,7 +24,7 @@ define amdgpu_kernel void @volatile_load_group_size_x(ptr addrspace(1) %out) #0 } ; CHECK-LABEL: @load_group_size_x( -; CHECK-NEXT: store i16 8, +; CHECK: store i16 %group.size.x, define amdgpu_kernel void @load_group_size_x(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -34,7 +34,7 @@ define amdgpu_kernel void @load_group_size_x(ptr addrspace(1) %out) #0 !reqd_wor } ; CHECK-LABEL: @load_group_size_y( -; CHECK-NEXT: store i16 16, +; CHECK: store i16 %group.size.y, define amdgpu_kernel void @load_group_size_y(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.y = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 6 @@ -44,7 +44,7 @@ define amdgpu_kernel void @load_group_size_y(ptr addrspace(1) %out) #0 !reqd_wor } ; CHECK-LABEL: @load_group_size_z( -; CHECK-NEXT: store i16 2, +; CHECK: store i16 %group.size.z, define amdgpu_kernel void @load_group_size_z(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.z = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 8 @@ -55,7 +55,7 @@ define amdgpu_kernel void @load_group_size_z(ptr addrspace(1) %out) #0 !reqd_wor ; Metadata uses i64 instead of i32 ; CHECK-LABEL: @load_group_size_x_reqd_work_group_size_i64( -; CHECK-NEXT: store i16 8, +; CHECK: store i16 %group.size.x, define amdgpu_kernel void @load_group_size_x_reqd_work_group_size_i64(ptr addrspace(1) %out) #0 !reqd_work_group_size !2 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -66,7 +66,7 @@ define amdgpu_kernel void @load_group_size_x_reqd_work_group_size_i64(ptr addrsp ; Metadata uses i16 instead of i32 ; CHECK-LABEL: @load_group_size_x_reqd_work_group_size_i16( -; CHECK-NEXT: store i16 8, +; CHECK: store i16 %group.size.x, define amdgpu_kernel void @load_group_size_x_reqd_work_group_size_i16(ptr addrspace(1) %out) #0 !reqd_work_group_size !3 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -76,7 +76,7 @@ define amdgpu_kernel void @load_group_size_x_reqd_work_group_size_i16(ptr addrsp } ; CHECK-LABEL: @use_local_size_x_8_16_2( -; CHECK-NEXT: store i64 8, +; CHECK: store i64 %zext, define amdgpu_kernel void @use_local_size_x_8_16_2(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -94,7 +94,7 @@ define amdgpu_kernel void @use_local_size_x_8_16_2(ptr addrspace(1) %out) #0 !re } ; CHECK-LABEL: @use_local_size_y_8_16_2( -; CHECK-NEXT: store i64 16, +; CHECK: store i64 %zext, define amdgpu_kernel void @use_local_size_y_8_16_2(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.y = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 6 @@ -112,7 +112,7 @@ define amdgpu_kernel void @use_local_size_y_8_16_2(ptr addrspace(1) %out) #0 !re } ; CHECK-LABEL: @use_local_size_z_8_16_2( -; CHECK-NEXT: store i64 2, +; CHECK: store i64 %zext, define amdgpu_kernel void @use_local_size_z_8_16_2(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.z = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 8 @@ -134,7 +134,7 @@ define amdgpu_kernel void @use_local_size_z_8_16_2(ptr addrspace(1) %out) #0 !re ; CHECK-LABEL: @local_size_x_8_16_2_wrong_group_id( ; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.y() -; CHECK: %group.id_x_group.size.x = shl i32 %group.id, 3 +; CHECK: %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext define amdgpu_kernel void @local_size_x_8_16_2_wrong_group_id(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -154,7 +154,7 @@ define amdgpu_kernel void @local_size_x_8_16_2_wrong_group_id(ptr addrspace(1) % ; CHECK-LABEL: @local_size_x_8_16_2_wrong_grid_size( ; CHECK: %grid.size.x = load i32, ptr addrspace(4) %gep.grid.size.x, align 4 ; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() -; CHECK: %group.id_x_group.size.x = shl i32 %group.id, 3 +; CHECK: %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext define amdgpu_kernel void @local_size_x_8_16_2_wrong_grid_size(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -174,9 +174,9 @@ define amdgpu_kernel void @local_size_x_8_16_2_wrong_group_id(ptr addrspace(1) % ; CHECK-LABEL: @local_size_x_8_16_2_wrong_cmp_type( ; CHECK: %grid.size.x = load i32, ptr addrspace(4) %gep.grid.size.x, align 4 ; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() -; CHECK: %group.id_x_group.size.x = shl i32 %group.id, 3 +; CHECK: %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext ; CHECK: %sub = sub i32 %grid.size.x, %group.id_x_group.size.x -; CHECK: %smin = call i32 @llvm.smin.i32(i32 %sub, i32 8) +; CHECK: %smin = call i32 @llvm.smin.i32(i32 %sub, i32 %group.size.x.zext) define amdgpu_kernel void @local_size_x_8_16_2_wrong_cmp_type(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -194,9 +194,9 @@ define amdgpu_kernel void @local_size_x_8_16_2_wrong_cmp_type(ptr addrspace(1) % } ; CHECK-LABEL: @local_size_x_8_16_2_wrong_select( -; CHECK: %group.id_x_group.size.x = shl i32 %group.id, 3 +; CHECK: %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext ; CHECK: %sub = sub i32 %grid.size.x, %group.id_x_group.size.x -; CHECK: %umax = call i32 @llvm.umax.i32(i32 %sub, i32 8) +; CHECK: %umax = call i32 @llvm.umax.i32(i32 %sub, i32 %group.size.x.zext) ; CHECK: %zext = zext i32 %umax to i64 define amdgpu_kernel void @local_size_x_8_16_2_wrong_select(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() @@ -218,7 +218,7 @@ define amdgpu_kernel void @local_size_x_8_16_2_wrong_select(ptr addrspace(1) %ou ; CHECK: %grid.size.x = load i16, ptr addrspace(4) %gep.grid.size.x, align 4 ; CHECK: %grid.size.x.zext = zext i16 %grid.size.x to i32 ; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() -; CHECK: %group.id_x_group.size.x = shl i32 %group.id, 3 +; CHECK: %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext ; CHECK: %sub = sub i32 %grid.size.x.zext, %group.id_x_group.size.x define amdgpu_kernel void @use_local_size_x_8_16_2_wrong_grid_load_size(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() @@ -238,7 +238,7 @@ define amdgpu_kernel void @use_local_size_x_8_16_2_wrong_grid_load_size(ptr addr } ; CHECK-LABEL: @func_group_size_x( -; CHECK-NEXT: ret i32 8 +; CHECK: ret i32 %zext define i32 @func_group_size_x(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -248,7 +248,7 @@ define i32 @func_group_size_x(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 } ; CHECK-LABEL: @__ockl_get_local_size_reqd_size( -; CHECK: %group.size = phi i32 [ 2, %bb17 ], [ 16, %bb9 ], [ 8, %bb1 ], [ 1, %bb ] +; CHECK: %group.size = phi i16 [ %tmp24, %bb17 ], [ %tmp16, %bb9 ], [ %tmp8, %bb1 ], [ 1, %bb ] define i64 @__ockl_get_local_size_reqd_size(i32 %arg) #1 !reqd_work_group_size !0 { bb: %tmp = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #2 @@ -295,9 +295,9 @@ bb25: ; preds = %bb17, %bb9, %bb1, % } ; CHECK-LABEL: @all_local_size( -; CHECK-NEXT: store volatile i64 8, ptr addrspace(1) %out, align 4 -; CHECK-NEXT: store volatile i64 16, ptr addrspace(1) %out, align 4 -; CHECK-NEXT: store volatile i64 2, ptr addrspace(1) %out, align 4 +; CHECK: store volatile i64 %tmp34.i, ptr addrspace(1) %out, align 4 +; CHECK-NEXT: store volatile i64 %tmp34.i14, ptr addrspace(1) %out, align 4 +; CHECK-NEXT: store volatile i64 %tmp34.i7, ptr addrspace(1) %out, align 4 define amdgpu_kernel void @all_local_size(ptr addrspace(1) nocapture readnone %out) #0 !reqd_work_group_size !0 { %tmp.i = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0 %tmp2.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #0 @@ -376,8 +376,8 @@ define amdgpu_kernel void @load_group_size_xy_i32(ptr addrspace(1) %out) #0 !req } ; CHECK-LABEL: @load_group_size_x_y_multiple_dispatch_ptr( -; CHECK-NEXT: store volatile i16 8, ptr addrspace(1) %out, align 2 -; CHECK-NEXT: store volatile i16 16, ptr addrspace(1) %out, align 2 +; CHECK: store volatile i16 %group.size.x, ptr addrspace(1) %out, align 2 +; CHECK: store volatile i16 %group.size.y, ptr addrspace(1) %out, align 2 define amdgpu_kernel void @load_group_size_x_y_multiple_dispatch_ptr(ptr addrspace(1) %out) #0 !reqd_work_group_size !0 { %dispatch.ptr0 = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr0, i64 4 @@ -396,8 +396,8 @@ define amdgpu_kernel void @load_group_size_x_y_multiple_dispatch_ptr(ptr addrspa ; CHECK-NEXT: %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() ; CHECK-NEXT: %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 ; CHECK-NEXT: %group.size.x = load i16, ptr addrspace(4) %gep.group.size.x, align 4 -; CHECK-NEXT: %zext = zext i16 %group.size.x to i64 -; CHECK-NEXT: store i64 %zext, ptr addrspace(1) %out, align 4 +; CHECK: %group.size.x.zext = zext i16 %group.size.x to i32 +; CHECK: store i64 %zext, ptr addrspace(1) %out define amdgpu_kernel void @use_local_size_x_uniform_work_group_size(ptr addrspace(1) %out) #2 { %dispatch.ptr = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() %gep.group.size.x = getelementptr inbounds i8, ptr addrspace(4) %dispatch.ptr, i64 4 @@ -456,3 +456,6 @@ attributes #3 = { nounwind "uniform-work-group-size"="false" } !1 = !{i32 8, i32 16} !2 = !{i64 8, i64 16, i64 2} !3 = !{i16 8, i16 16, i16 2} + +!llvm.module.flags = !{!4} +!4 = !{i32 1, !"amdgpu_code_object_version", i32 500} diff --git a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll index dcc90c0dcd40..e7c5aaf043ef 100644 --- a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll @@ -43,9 +43,9 @@ define amdgpu_kernel void @test_simple_indirect_call() { ; GFX9-LABEL: test_simple_indirect_call: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x4 -; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17 -; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0 -; GFX9-NEXT: s_add_u32 s0, s0, s17 +; GFX9-NEXT: s_add_u32 flat_scratch_lo, s10, s15 +; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s11, 0 +; GFX9-NEXT: s_add_u32 s0, s0, s15 ; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_lshr_b32 s4, s4, 16 @@ -76,3 +76,6 @@ define amdgpu_kernel void @test_simple_indirect_call() { ; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" } ; ATTRIBUTOR_GCN: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } ;. + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"amdgpu_code_object_version", i32 500} -- GitLab From 633d9184f5f8ab227ab22fd7a7db366b843a02d2 Mon Sep 17 00:00:00 2001 From: "Oleksandr \"Alex\" Zinenko" Date: Tue, 9 Jan 2024 13:18:57 +0100 Subject: [PATCH 192/652] [mlir] introduce transform.collect_matching (#76724) Introduce a new match combinator into the transform dialect. This operation collects all operations that are yielded by a satisfactory match into its results. This is a simpler version of `foreach_match` that can be inserted directly into existing transform scripts. --- .../mlir/Dialect/Transform/IR/TransformOps.td | 35 +++- .../lib/Dialect/Transform/IR/TransformOps.cpp | 150 ++++++++++++++++-- mlir/test/Dialect/Transform/ops-invalid.mlir | 68 ++++++++ .../Dialect/Transform/test-interpreter.mlir | 44 +++++ 4 files changed, 279 insertions(+), 18 deletions(-) diff --git a/mlir/include/mlir/Dialect/Transform/IR/TransformOps.td b/mlir/include/mlir/Dialect/Transform/IR/TransformOps.td index fcdb21d21503..fe2c28f45aea 100644 --- a/mlir/include/mlir/Dialect/Transform/IR/TransformOps.td +++ b/mlir/include/mlir/Dialect/Transform/IR/TransformOps.td @@ -460,6 +460,39 @@ def NumAssociationsOp : TransformDialectOp<"num_associations", let hasVerifier = 1; } +def CollectMatchingOp : TransformDialectOp<"collect_matching", [ + DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods]> { + let summary = "Collects all payload ops that match the given named matcher"; + let description = [{ + Collects operations or other payload IR objects nested under `root` + (inclusive) that match the given matcher expressed as a named sequence. The + matcher sequence must accept exactly one argument that it is not allowed to + modify. It must yield as many values as this op has results. Each of the + yielded values must be associated with exactly one payload object. If any + operation in the matcher sequence produces a silenceable failure, the + matcher advances to the next payload operation in the walk order without + finishing the sequence. + + The i-th result of this operation is constructed by concatenating the i-th + yielded payload IR objects of all successful matcher sequence applications. + All results are guaranteed to be mapped to the same number of payload IR + objects. + + The operation succeeds unless the matcher sequence produced a definite + failure for any invocation. + }]; + + let arguments = (ins TransformHandleTypeInterface:$root, + SymbolRefAttr:$matcher); + let results = (outs Variadic:$results); + + let assemblyFormat = [{ + $matcher `in` $root attr-dict `:` functional-type($root, $results) + }]; +} + def ForeachMatchOp : TransformDialectOp<"foreach_match", [ DeclareOpInterfaceMethods, DeclareOpInterfaceMethods, @@ -674,7 +707,7 @@ def GetParentOp : TransformDialectOp<"get_parent_op", def GetProducerOfOperand : TransformDialectOp<"get_producer_of_operand", [DeclareOpInterfaceMethods, - NavigationTransformOpTrait, MemoryEffectsOpInterface]> { + NavigationTransformOpTrait, MatchOpInterface, MemoryEffectsOpInterface]> { let summary = "Get handle to the producer of this operation's operand number"; let description = [{ The handle defined by this Transform op corresponds to operation that diff --git a/mlir/lib/Dialect/Transform/IR/TransformOps.cpp b/mlir/lib/Dialect/Transform/IR/TransformOps.cpp index aa4694c88d3b..b80fc09751d2 100644 --- a/mlir/lib/Dialect/Transform/IR/TransformOps.cpp +++ b/mlir/lib/Dialect/Transform/IR/TransformOps.cpp @@ -22,6 +22,7 @@ #include "mlir/IR/Verifier.h" #include "mlir/Interfaces/ControlFlowInterfaces.h" #include "mlir/Interfaces/FunctionImplementation.h" +#include "mlir/Interfaces/FunctionInterfaces.h" #include "mlir/Pass/Pass.h" #include "mlir/Pass/PassManager.h" #include "mlir/Pass/PassRegistry.h" @@ -783,7 +784,7 @@ bool transform::CastOp::areCastCompatible(TypeRange inputs, TypeRange outputs) { } //===----------------------------------------------------------------------===// -// ForeachMatchOp +// CollectMatchingOp //===----------------------------------------------------------------------===// /// Applies matcher operations from the given `block` assigning `op` as the @@ -822,6 +823,137 @@ matchBlock(Block &block, Operation *op, transform::TransformState &state, return DiagnosedSilenceableFailure::success(); } +/// Returns `true` if both types implement one of the interfaces provided as +/// template parameters. +template +static bool implementSameInterface(Type t1, Type t2) { + return ((isa(t1) && isa(t2)) || ... || false); +} + +/// Returns `true` if both types implement one of the transform dialect +/// interfaces. +static bool implementSameTransformInterface(Type t1, Type t2) { + return implementSameInterface( + t1, t2); +} + +//===----------------------------------------------------------------------===// +// CollectMatchingOp +//===----------------------------------------------------------------------===// + +DiagnosedSilenceableFailure +transform::CollectMatchingOp::apply(transform::TransformRewriter &rewriter, + transform::TransformResults &results, + transform::TransformState &state) { + auto matcher = SymbolTable::lookupNearestSymbolFrom( + getOperation(), getMatcher()); + if (matcher.isExternal()) { + return emitDefiniteFailure() + << "unresolved external symbol " << getMatcher(); + } + + SmallVector, 2> rawResults; + rawResults.resize(getOperation()->getNumResults()); + std::optional maybeFailure; + for (Operation *root : state.getPayloadOps(getRoot())) { + WalkResult walkResult = root->walk([&](Operation *op) { + DEBUG_MATCHER({ + DBGS_MATCHER() << "matching "; + op->print(llvm::dbgs(), + OpPrintingFlags().assumeVerified().skipRegions()); + llvm::dbgs() << " @" << op << "\n"; + }); + + // Try matching. + SmallVector> mappings; + DiagnosedSilenceableFailure diag = + matchBlock(matcher.getFunctionBody().front(), op, state, mappings); + if (diag.isDefiniteFailure()) + return WalkResult::interrupt(); + if (diag.isSilenceableFailure()) { + DEBUG_MATCHER(DBGS_MATCHER() << "matcher " << matcher.getName() + << " failed: " << diag.getMessage()); + return WalkResult::advance(); + } + + // If succeeded, collect results. + for (auto &&[i, mapping] : llvm::enumerate(mappings)) { + if (mapping.size() != 1) { + maybeFailure.emplace(emitSilenceableError() + << "result #" << i << ", associated with " + << mapping.size() + << " payload objects, expected 1"); + return WalkResult::interrupt(); + } + rawResults[i].push_back(mapping[0]); + } + return WalkResult::advance(); + }); + if (walkResult.wasInterrupted()) + return std::move(*maybeFailure); + assert(!maybeFailure && "failure set but the walk was not interrupted"); + + for (auto &&[opResult, rawResult] : + llvm::zip_equal(getOperation()->getResults(), rawResults)) { + results.setMappedValues(opResult, rawResult); + } + } + return DiagnosedSilenceableFailure::success(); +} + +void transform::CollectMatchingOp::getEffects( + SmallVectorImpl &effects) { + onlyReadsHandle(getRoot(), effects); + producesHandle(getResults(), effects); + onlyReadsPayload(effects); +} + +LogicalResult transform::CollectMatchingOp::verifySymbolUses( + SymbolTableCollection &symbolTable) { + auto matcherSymbol = dyn_cast_or_null( + symbolTable.lookupNearestSymbolFrom(getOperation(), getMatcher())); + if (!matcherSymbol || + !isa(matcherSymbol.getOperation())) + return emitError() << "unresolved matcher symbol " << getMatcher(); + + ArrayRef argumentTypes = matcherSymbol.getArgumentTypes(); + if (argumentTypes.size() != 1 || + !isa(argumentTypes[0])) { + return emitError() + << "expected the matcher to take one operation handle argument"; + } + if (!matcherSymbol.getArgAttr( + 0, transform::TransformDialect::kArgReadOnlyAttrName)) { + return emitError() << "expected the matcher argument to be marked readonly"; + } + + ArrayRef resultTypes = matcherSymbol.getResultTypes(); + if (resultTypes.size() != getOperation()->getNumResults()) { + return emitError() + << "expected the matcher to yield as many values as op has results (" + << getOperation()->getNumResults() << "), got " + << resultTypes.size(); + } + + for (auto &&[i, matcherType, resultType] : + llvm::enumerate(resultTypes, getOperation()->getResultTypes())) { + if (implementSameTransformInterface(matcherType, resultType)) + continue; + + return emitError() + << "mismatching type interfaces for matcher result and op result #" + << i; + } + + return success(); +} + +//===----------------------------------------------------------------------===// +// ForeachMatchOp +//===----------------------------------------------------------------------===// + DiagnosedSilenceableFailure transform::ForeachMatchOp::apply(transform::TransformRewriter &rewriter, transform::TransformResults &results, @@ -978,22 +1110,6 @@ LogicalResult transform::ForeachMatchOp::verify() { return success(); } -/// Returns `true` if both types implement one of the interfaces provided as -/// template parameters. -template -static bool implementSameInterface(Type t1, Type t2) { - return ((isa(t1) && isa(t2)) || ... || false); -} - -/// Returns `true` if both types implement one of the transform dialect -/// interfaces. -static bool implementSameTransformInterface(Type t1, Type t2) { - return implementSameInterface( - t1, t2); -} - /// Checks that the attributes of the function-like operation have correct /// consumption effect annotations. If `alsoVerifyInternal`, checks for /// annotations being present even if they can be inferred from the body. diff --git a/mlir/test/Dialect/Transform/ops-invalid.mlir b/mlir/test/Dialect/Transform/ops-invalid.mlir index 5123958b02bf..233dbbcb6804 100644 --- a/mlir/test/Dialect/Transform/ops-invalid.mlir +++ b/mlir/test/Dialect/Transform/ops-invalid.mlir @@ -704,3 +704,71 @@ transform.sequence failures(propagate) { // expected-error @below {{expected the type of the parameter attribute ('i64') to match the parameter type ('i32')}} transform.num_associations %arg0 : (!transform.any_op) -> !transform.param } + +// ----- + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-error @below {{unresolved matcher symbol @missing_symbol}} + transform.collect_matching @missing_symbol in %arg0 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-error @below {{expected the matcher to take one operation handle argument}} + transform.collect_matching @matcher in %arg0 : (!transform.any_op) -> !transform.any_op + transform.yield + } + + transform.named_sequence @matcher() { + transform.yield + } +} + +// ----- + + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-error @below {{expected the matcher argument to be marked readonly}} + transform.collect_matching @matcher in %arg0 : (!transform.any_op) -> !transform.any_op + transform.yield + } + + transform.named_sequence @matcher(%arg0: !transform.any_op) { + transform.yield + } +} + + +// ----- + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-error @below {{expected the matcher to yield as many values as op has results (1), got 0}} + transform.collect_matching @matcher in %arg0 : (!transform.any_op) -> !transform.any_op + transform.yield + } + + transform.named_sequence @matcher(%arg0: !transform.any_op {transform.readonly}) { + transform.yield + } +} + +// ----- + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-error @below {{mismatching type interfaces for matcher result and op result #0}} + transform.collect_matching @matcher in %arg0 : (!transform.any_op) -> !transform.any_value + transform.yield + } + + transform.named_sequence @matcher(%arg0: !transform.any_op {transform.readonly}) -> !transform.any_op { + transform.yield %arg0 : !transform.any_op + } +} diff --git a/mlir/test/Dialect/Transform/test-interpreter.mlir b/mlir/test/Dialect/Transform/test-interpreter.mlir index 3bbf875ef309..4ecd731ce417 100644 --- a/mlir/test/Dialect/Transform/test-interpreter.mlir +++ b/mlir/test/Dialect/Transform/test-interpreter.mlir @@ -2380,3 +2380,47 @@ module @named_inclusion attributes { transform.with_named_sequence } { transform.yield } } + +// ----- + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-error @below {{result #0, associated with 2 payload objects, expected 1}} + transform.collect_matching @matcher in %arg0 : (!transform.any_op) -> !transform.any_op + transform.yield + } + + transform.named_sequence @matcher(%arg0: !transform.any_op {transform.readonly}) -> !transform.any_op { + %0 = transform.merge_handles %arg0, %arg0 : !transform.any_op + transform.yield %0 : !transform.any_op + } +} + +// ----- + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-error @below {{unresolved external symbol @matcher}} + transform.collect_matching @matcher in %arg0 : (!transform.any_op) -> !transform.any_op + transform.yield + } + + transform.named_sequence @matcher(%arg0: !transform.any_op {transform.readonly}) -> !transform.any_op +} + +// ----- + +module attributes { transform.with_named_sequence } { + transform.named_sequence @__transform_main(%arg0: !transform.any_op) { + // expected-remark @below {{matched}} + %0 = transform.collect_matching @matcher in %arg0 : (!transform.any_op) -> !transform.any_op + // expected-remark @below {{matched}} + transform.test_print_remark_at_operand %0, "matched" : !transform.any_op + transform.yield + } + + transform.named_sequence @matcher(%arg0: !transform.any_op {transform.readonly}) -> !transform.any_op { + transform.match.operation_name %arg0 ["transform.test_print_remark_at_operand", "transform.collect_matching"] : !transform.any_op + transform.yield %arg0 : !transform.any_op + } +} -- GitLab From 4cb2ef4fe372d32d1773f4dd358d6dff91518b5f Mon Sep 17 00:00:00 2001 From: "Oleksandr \"Alex\" Zinenko" Date: Tue, 9 Jan 2024 13:19:41 +0100 Subject: [PATCH 193/652] [mlir] add a chapter on matchers to the transform dialect tutorial (#76725) These operations has been available for a while, but were not described in the tutorial. Add a new chapter on using and defining match operations. --- mlir/docs/Tutorials/transform/Ch4.md | 581 ++++++++++++++++++ mlir/docs/Tutorials/transform/_index.md | 1 + mlir/examples/transform/CMakeLists.txt | 1 + .../Ch3/transform-opt/transform-opt.cpp | 2 +- mlir/examples/transform/Ch4/CMakeLists.txt | 21 + .../transform/Ch4/include/CMakeLists.txt | 14 + .../transform/Ch4/include/MyExtension.h | 30 + .../transform/Ch4/include/MyExtension.td | 46 ++ .../examples/transform/Ch4/lib/CMakeLists.txt | 20 + .../transform/Ch4/lib/MyExtension.cpp | 207 +++++++ .../Ch4/transform-opt/transform-opt.cpp | 55 ++ mlir/test/CMakeLists.txt | 2 + .../test/Examples/transform/Ch4/features.mlir | 123 ++++ .../test/Examples/transform/Ch4/multiple.mlir | 131 ++++ .../test/Examples/transform/Ch4/sequence.mlir | 139 +++++ mlir/test/lit.cfg.py | 5 +- 16 files changed, 1375 insertions(+), 3 deletions(-) create mode 100644 mlir/docs/Tutorials/transform/Ch4.md create mode 100644 mlir/examples/transform/Ch4/CMakeLists.txt create mode 100644 mlir/examples/transform/Ch4/include/CMakeLists.txt create mode 100644 mlir/examples/transform/Ch4/include/MyExtension.h create mode 100644 mlir/examples/transform/Ch4/include/MyExtension.td create mode 100644 mlir/examples/transform/Ch4/lib/CMakeLists.txt create mode 100644 mlir/examples/transform/Ch4/lib/MyExtension.cpp create mode 100644 mlir/examples/transform/Ch4/transform-opt/transform-opt.cpp create mode 100644 mlir/test/Examples/transform/Ch4/features.mlir create mode 100644 mlir/test/Examples/transform/Ch4/multiple.mlir create mode 100644 mlir/test/Examples/transform/Ch4/sequence.mlir diff --git a/mlir/docs/Tutorials/transform/Ch4.md b/mlir/docs/Tutorials/transform/Ch4.md new file mode 100644 index 000000000000..77c36eab343d --- /dev/null +++ b/mlir/docs/Tutorials/transform/Ch4.md @@ -0,0 +1,581 @@ +# Chapter 4: Matching Payload with Transform Operations + +**Check the continuously-tested version of MLIR files under +[mlir/test/Examples/transform/Ch4](https://github.com/llvm/llvm-project/tree/main/mlir/test/Examples/transform/Ch4).** + +Up until now, we were applying transform dialect scripts under the assumption +that specific payload operations are identified by the caller when the transform +dialect interpreter is invoked. This may be seen as contrary to the idea of +driving transformations from a dialect since the transformation targets must be +identified through mechanisms external to the transform dialect interpreter, for +example, when invoking the interpreter programmatically in C++ or through pass +arguments as seen in previous chapters. It also adds practical overhead due to +increased interaction with the interpreter in C++, and cognitive overhead of +manipulating two interfaces at once. To remedy this, Transform dialect proposes +a subset of operations for _matching_ payload operations that need to be +transformed. + +_Match_ operations are simply transform operations with some additional +guarantees. In particular, they are not expected to modify the payload IR and +are expected to fail if their operands (typically payload operation handles) are +not associated with payload IR objects having desired properties, such as +operation names or kinds of arguments. Using simple combinator operations, it +becomes possible to set up a higher-level match and rewrite infrastructure +directly within the transform dialect. + + +## Simple match + +Let us reconsider the “fully connected layer” example from [Chapter +1](Ch1.md#chaining-transformations-with-handles), reproduced below for +convenience. + + +```mlir +// Original function to optimize. +func.func @fc_relu(%lhs: tensor<512x512xf32>, %rhs: tensor<512x512xf32>, + %bias: tensor<512x512xf32>, %output: tensor<512x512xf32>) + -> tensor<512x512xf32> { + // Matrix-matrix multiplication. + %matmul = linalg.matmul + ins(%lhs, %rhs: tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output: tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise addition. + %biased = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%matmul, %bias : tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise max with 0 (ReLU). + %c0f = arith.constant 0.0 : f32 + %relued = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%biased, %c0f : tensor<512x512xf32>, f32) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + func.return %relued : tensor<512x512xf32> +} + +``` + + +In Chapter 1, we were calling the test transform interpreter pass with +additional arguments, `bind-first-extra-to-ops=linalg.matmul +bind-second-extra-to-ops=linalg.elemwise_binary`, to provide initial +associations for operation handles. Instead, we can use match operations to +discover relevant operations in the payload IR. Match operations can be combined +with “regular” transform operations using, e.g., the +`transform.collect_matching` combinator operation that leverages the concept of +named sequences to organize matchers. + + +```mlir +// The module containing named sequences must have an attribute allowing them +// to enable verification. +module @transforms attributes { transform.with_named_sequence } { + // Entry point. This takes as the only argument the root operation (typically + // pass root) given to the transform interpreter. + transform.named_sequence @__transform_main( + %root: !transform.any_op {transform.readonly}) { + // Collect operations that match the criteria specified in named sequence. + // If the named sequence fails with a silenceable failure, silences it (the + // message is forwarded to the debug stream). If the named sequence + // succeeds, appends its results to the results of this operation. + %elemwise = transform.collect_matching @match_elemwise in %root + : (!transform.any_op) -> !transform.any_op + %matmul = transform.collect_matching @match_matmul in %root + : (!transform.any_op) -> !transform.any_op + transform.include @print_elemwise failures(propagate) (%elemwise) + : (!transform.any_op) -> () + transform.include @print_matmul failures(propagate) (%matmul) + : (!transform.any_op) -> () + + transform.yield + } + + // This is a matcher sequence. It is given an operation to match and the + // match is considered successful unless any nested operation produces a + // failure. The values yielded by this operation will be forwarded to the + // rewriter sequence on success. + transform.named_sequence @match_elemwise( + %entry: !transform.any_op {transform.readonly}) -> !transform.any_op { + transform.match.operation_name %entry ["linalg.elemwise_binary"] + : !transform.any_op + transform.yield %entry : !transform.any_op + } + transform.named_sequence @match_matmul( + %entry: !transform.any_op {transform.readonly}) -> !transform.any_op { + transform.match.operation_name %entry ["linalg.matmul"] : !transform.any_op + transform.yield %entry : !transform.any_op + } + + // This is a rewriter sequence. + transform.named_sequence @print_elemwise( + %elemwise_binary: !transform.any_op {transform.readonly}) { + transform.test_print_remark_at_operand + %elemwise_binary, "elementwise binary" : !transform.any_op + transform.yield + } + transform.named_sequence @print_matmul( + %matmul: !transform.any_op {transform.readonly}) { + transform.test_print_remark_at_operand %matmul, "matmul" : !transform.any_op + transform.yield + } +} + +``` + + +This script can be executed using the non-test interpreter pass running on the +root operation of the translation unit without additional flags: `mlir-opt +--transform-interpreter`. It will emit corresponding remarks at +`linalg.elemwise_binary` and `linalg.matmul` operations. In debug builds, the +infrastructure provides a convenient method to understand the matching process +by passing `-debug-only=transform-matcher` to `mlir-opt` or a derived tool. It +will print the silenceable failure messages produced by the match operations +into the debug stream, for example: + + +``` +<...> +[transform-matcher] matching %0 = linalg.matmul ins(%arg0, %arg1 : tensor<512x512xf32>, tensor<512x512xf32>) outs(%arg3 : tensor<512x512xf32>) -> tensor<512x512xf32> @0x5622eee08410 +[transform-matcher] matcher match_elemwise failed: wrong operation name +<...> +``` + + +This is now sufficient to run the rest of the transform script from Chapter 1, +substituting `%arg1` with `%matmul` and `%arg2` with `%elemwise`. + + +## Matching Chains of Operations + +The matcher above remains naive as it matches _all_ operations of the certain +kind under the payload root. These operations may or may not be related, and +may, for example, belong to different functions. Even if they are in a single +function, if there are multiple groups of such operations, we wouldn’t be able +to differentiate them with this approach. In reality, we want to match a +specific group of operations where a `matmul` operation produces a result that +is used by an elementwise operation, which in turn feeds another elementwise +operation in a similar way. + +This can be achieved using the following matcher sequence. + + +```mlir +// This is also a matcher sequence. It is similarly given an operation to +// match and nested operations must succeed in order for a match to be deemed +// successful. It starts matching from the last operation in the use-def chain +// and goes back because each operand (use) has exactly one definition. +transform.named_sequence @match_matmul_elemwise( + %last: !transform.any_op {transform.readonly}) + -> (!transform.any_op, !transform.any_op, !transform.any_op) { + // The last operation must be an elementwise binary. + transform.match.operation_name %last ["linalg.elemwise_binary"] + : !transform.any_op + // Its first operand must be defined by another operation, to which we + // will get a handle here. We are guaranteed that the first operand exists + // because we know the operation is binary, but even in absence of such a + // guarantee, this operation would have produced a silenceable failure when + // `%last` does not have enough operands. + %middle = transform.get_producer_of_operand %last[0] + : (!transform.any_op) -> !transform.any_op + // The defining operation must itself be an elementwise binary. + transform.match.operation_name %middle ["linalg.elemwise_binary"] + : !transform.any_op + // And the first operand of that operation must be defined by yet another + // operation. + %matmul = transform.get_producer_of_operand %middle[0] + : (!transform.any_op) -> !transform.any_op + // And that operation is a matmul. + transform.match.operation_name %matmul ["linalg.matmul"] : !transform.any_op + // We will yield the handles to the matmul and the two elementwise + // operations separately. + transform.yield %matmul, %middle, %last + : !transform.any_op, !transform.any_op, !transform.any_op +} +``` + +This matcher is applicable in presence of other `elemwise` and `matmul` +operations and will return the triple of _related_ operations rather than +operations in the order in which they are found. It can be exercised similarly +to the previous incarnation, as follows. + +```mlir +// Alternative entry point. +transform.named_sequence @__transform_main( + %root: !transform.any_op {transform.readonly}) { + // Collect groups of operations that match the criteria specified in the + // named sequence. + %matmul, %el1, %el2 = transform.collect_matching @match_matmul_elemwise in %root + : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %elemwise = transform.merge_handles %el1, %el2 : !transform.any_op + + transform.include @print_elemwise failures(propagate) (%elemwise) + : (!transform.any_op) -> () + transform.include @print_matmul failures(propagate) (%matmul) + : (!transform.any_op) -> () + + transform.yield +} +``` + + +## Defining Match Operations + +The matcher of a chain of operations is correct in presence of other operations, +but is still insufficiently robust for many cases of interest. In particular, +using `transform.get_producer_of_operand %last[0]` requires that the _first_ +operand of elementwise operations is produced by another operation. The same +transformation strategy may however apply regardless of the operand position: +many binary operations are associative. Let us use this opportunity to introduce +a new match operation. Specifically, we would like this operation to succeed if +_any_ of the operands satisfies certain conditions that can be expressed as +other match operations. We also want it to return some of the state and the +position of the matched operand in the operand list. + +Match operations are defined similarly to other transform operations, with the +only difference of additionally implementing the `MatchOpInterface`. Note that +this interface has _no additional methods_ (though it may add some eventually) +and is only used as a verification contract that the operation is intended for +matching and will not attempt to transform the payload. The minimal definition +of our operation is as follows. + + +```tablegen +// Define the new operation. By convention, prefix its name with `match` +// followed by the name of the dialect extension. +def HasOperandSatisfyingOp : TransformDialectOp<"match.my.has_operand_satisfying", + [DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods, + // Indicate that the operation implements MatchOpInterface in addition to + // the TransformOpInterface. This interface is only used as a tag at this + // point and has no methods that are mandatory to implement. + MatchOpInterface, + SingleBlockImplicitTerminator<"::mlir::transform::YieldOp">]> { + let summary = "Succeed if any of the operands matches all nested criteria"; + let arguments = (ins TransformHandleTypeInterface:$op); + let results = (outs TransformParamTypeInterface:$position, + Variadic:$results); + + // Match operations can be arbitrarily complex, e.g., containing regions. + let regions = (region SizedRegion<1>:$body); + let hasVerifier = 1; + let assemblyFormat = [{ + $op `:` functional-type($op, results) attr-dict-with-keyword $body + }]; +} +``` + + +It takes as argument the handle associated with the payload operations whose +operands it will match, has an associated single-block region containing the +match criteria, and returns the position of the matched operand as well as any +other transform value yielded from the body on the successful match. + +The matching logic is implemented in the `apply` method of the +`TransformOpInterface` and is easily composable with other transform operations. +All facilities for managing the interpreter state and recursively entering the +blocks are available in the same way as they are for “regular” transform +operations. Match operations are expected to return a silenceable failure to +indicate failure to match, and to immediately propagate definite failures. If +they have nested operations, they are expected to handle and, in most cases, +silence the silenceable failures produced when applying those operations. For +our operation, the matching is essentially a loop iterating over all operands of +the (single) payload operation and applying nested transform ops until they all +succeed for one of the operands. + + +```cpp +// Matcher ops implement `apply` similarly to other transform ops. They are not +// expected to modify payload, but use the tri-state result to signal failure or +// success to match, as well as potential irrecoverable errors. +mlir::DiagnosedSilenceableFailure +mlir::transform::HasOperandSatisfyingOp::apply( + mlir::transform::TransformRewriter &rewriter, + mlir::transform::TransformResults &results, + mlir::transform::TransformState &state) { + // For simplicity, only handle a single payload op. Actual implementations + // can use `SingleOpMatcher` trait to simplify implementation and document + // this expectation. + auto payloadOps = state.getPayloadOps(getOp()); + if (!llvm::hasSingleElement(payloadOps)) + return emitSilenceableError() << "expected single payload"; + + // Iterate over all operands of the payload op to see if they can be matched + // using the body of this op. + Operation *payload = *payloadOps.begin(); + for (OpOperand &operand : payload->getOpOperands()) { + // Create a scope for transform values defined in the body. This corresponds + // to the syntactic scope of the region attached to this op. Any values + // associated with payloads from now on will be automatically dissociated + // when this object is destroyed, i.e. at the end of the iteration. + // Associate the block argument handle with the operand. + auto matchScope = state.make_region_scope(getBody()); + if (failed(state.mapBlockArgument(getBody().getArgument(0), + {operand.get()}))) { + return DiagnosedSilenceableFailure::definiteFailure(); + } + + // Iterate over all nested matchers with the current mapping and see if they + // succeed. + bool matchSucceeded = true; + for (Operation &matcher : getBody().front().without_terminator()) { + // Matcher ops are applied similarly to any other transform op. + DiagnosedSilenceableFailure diag = + state.applyTransform(cast(matcher)); + + // Definite failures are immediately propagated as they are irrecoverable. + if (diag.isDefiniteFailure()) + return diag; + + // On success, keep checking the remaining conditions. + if (diag.succeeded()) + continue; + + // Report failure-to-match for debugging purposes and stop matching this + // operand. + assert(diag.isSilenceableFailure()); + DEBUG_MATCHER(DBGS_MATCHER() + << "failed to match operand #" << operand.getOperandNumber() + << ": " << diag.getMessage()); + (void)diag.silence(); + matchSucceeded = false; + break; + } + // If failed to match this operand, try other operands. + if (!matchSucceeded) + continue; + + // If we reached this point, the matching succeeded for the current operand. + // Remap the values associated with terminator operands to be associated + // with op results, and also map the parameter result to the operand's + // position. Note that it is safe to do here despite the end of the scope + // as `results` are integrated into `state` by the interpreter after `apply` + // returns rather than immediately. + SmallVector> yieldedMappings; + transform::detail::prepareValueMappings( + yieldedMappings, getBody().front().getTerminator()->getOperands(), + state); + results.setParams(getPosition().cast(), + {rewriter.getI32IntegerAttr(operand.getOperandNumber())}); + for (auto &&[result, mapping] : llvm::zip(getResults(), yieldedMappings)) + results.setMappedValues(result, mapping); + return DiagnosedSilenceableFailure::success(); + } + + // If we reached this point, none of the operands succeeded the match. + return emitSilenceableError() + << "none of the operands satisfied the conditions"; +} + +``` + + +By convention, operations implementing `MatchOpInterface` must not modify +payload IR and must therefore specify that they only read operand handles and +payload as their effects. + + +```cpp +void transform::CollectMatchingOp::getEffects( + SmallVectorImpl &effects) { + onlyReadsHandle(getRoot(), effects); + producesHandle(getResults(), effects); + onlyReadsPayload(effects); +} +``` + + +This operation can now be included in a transform dialect extension, loaded and +used in our matcher. Specifically, we will use it to indicate that either of the +operands of the “max” elementwise operation in our example can be produced by +the previous elementwise operation. The previous operation will still require +the matmul to produce the first operand for simplicity. The updated matcher +sequence looks as follows. + + +```mlir +transform.named_sequence @match_matmul_elemwise( + %last: !transform.any_op {transform.readonly}) + -> (!transform.any_op, !transform.any_op, !transform.any_op, + !transform.param) { + // The last operation must be an elementwise binary. + transform.match.operation_name %last ["linalg.elemwise_binary"] + : !transform.any_op + + // One of its operands must be defined by another operation, to which we + // will get a handle here. This is achieved thanks to a newly defined + // operation that tries to match operands one by one using the match + // operations nested in its region. + %pos, %middle = transform.match.my.has_operand_satisfying %last + : (!transform.any_op) -> (!transform.param, !transform.any_op) { + ^bb0(%operand: !transform.any_value): + // The operand must be defined by an operation. + %def = transform.get_defining_op %operand + : (!transform.any_value) -> !transform.any_op + // The defining operation must itself be an elementwise binary. + transform.match.operation_name %def ["linalg.elemwise_binary"] + : !transform.any_op + transform.yield %def : !transform.any_op + } + + // And the first operand of that operation must be defined by yet another + // operation. + %matmul = transform.get_producer_of_operand %middle[0] + : (!transform.any_op) -> !transform.any_op + // And that operation is a matmul. + transform.match.operation_name %matmul ["linalg.matmul"] : !transform.any_op + // We will yield the handles to the matmul and the two elementwise + // operations separately. + transform.yield %matmul, %middle, %last, %pos + : !transform.any_op, !transform.any_op, !transform.any_op, + !transform.param +} +``` + + +This achieves the desired effect and matches both `max(add(matmul(...), bias), +0)` and `max(0, add(matmul(...), bias))` in the same values. The `%pos` value is +a transform dialect _parameter_, which is used to store lists of entities known +to be constant throughout the transform application. Most often, parameters are +numeric values, but they can generally be any MLIR attributes. + +In order to demonstrate that groups of operations are matched independently of +each other, let us use the `transform.foreach_match` operation that allows one +to implement a simple high-level pattern rewriting approach within the transform +dialect (for advanced or lower-level pattern rewriting, consider PDL(L) or C++ +rewriting APIs). It maps a matcher named sequence to an action named sequence, +and the latter gets invoked whenever the former succeeds. + + +```mlir +// Traverses the payload IR associated with the operand handle, invoking +// @match_matmul_elemwise on each of the operations. If the named sequence +// succeeds, i.e., if none of the nested match (transform) operations +// produced a silenceable failure, invokes @print_matmul_elemwise and +// forwards the values yielded as arguments of the new invocation. If the +// named sequence fails with a silenceable failure, silences it (the message +// is forwarded to the debug stream). Definite failures are propagated +// immediately and unconditionally, as usual. +transform.foreach_match in %root + @match_matmul_elemwise -> @print_matmul_elemwise + : (!transform.any_op) -> !transform.any_op +``` + + +The `@print_matmul_elemwise` named sequence, available in `multiple.mlir`, will +use the parameter with the position of the operand to differentiate the two +groups. + + +## Matchers for Inferred Features + +The matcher sequences described above, although useful to drive transformations +from within the transform dialect interpreter, are rather basic since they +mostly rely on operation names and use-def chains. Alternative implementations +using APIs or various declarative rewrite rules are barely less expressive and +sometimes more concise. The real power of transform dialect matcher ops lies in +the possibility to define matchers of _inferred properties_ of payloads, i.e., +properties that are not directly accessible as an attribute of an operation or +any straightforward relation between IR components. + +The utility of such matchers can be easily demonstrated by slightly modifying +our original example. If matrix multiplication is expressed as a special case of +tensor contraction using `linalg.generic` instead of `linalg.matmul`, the +operation name-based matcher no longer applies. Yet such a representation is +very common and can appear both in the original input and during the course of +transformation, e.g., where a higher-dimensional contraction is decomposed into +loops around a matrix multiplication. + +In order to be a (potentially transposed) matrix multiplication, the +`linalg.generic` operation must have the following features: + + + +* Total rank of 3. +* Two inputs accessed as projected permutation of iteration dimensions. +* One output accessed as projected permutation of iteration dimensions. +* Iteration dimensions can be subdivided into LHS parallel, RHS parallel and reduction dimensions. +* The body block consists of a multiplication and an addition. + +Most of these features can be derived from the properties of the operation, +e.g., the total rank corresponds to the number of entries in the `iterators` +attribute, but almost none of them are immediately accessible in the IR or in +any declarative form, which is usually limited to checking the presence or the +exact match of an attribute or a type. The transform dialect allows these +features to be implemented in the `apply` method of a matcher op and reused +across multiple matching cases. For structured linear algebra payload +operations, many such match operations are readily available in the `structured` +extension. They are sufficient to implement a matrix multiplication matcher +using the features listed above almost verbatim. + + +```mlir +transform.named_sequence @match_generic_matmul( + %candidate: !transform.any_op {transform.readonly}) -> !transform.any_op { + // Match a structured linear algebra operation. + transform.match.structured %candidate : !transform.any_op { + ^bb0(%c: !transform.any_op): + // With a rank equal to 3. + %rank = transform.match.structured.rank %c + : (!transform.any_op) -> !transform.param + %c3 = transform.param.constant 3 : i64 -> !transform.param + transform.match.param.cmpi eq %rank, %c3 : !transform.param + + // With 2 inputs. + %n_ins = transform.match.structured.num_inputs %c + : (!transform.any_op) -> !transform.param + %c2 = transform.param.constant 2 : i64 -> !transform.param + transform.match.param.cmpi eq %n_ins, %c2 : !transform.param + + // With 1 output (note that structured ops in destination passing style + // has as many inits as outputs). + %n_inits = transform.match.structured.num_inits %c + : (!transform.any_op) -> !transform.param + %c1 = transform.param.constant 1 : i64 -> !transform.param + transform.match.param.cmpi eq %n_inits, %c1 : !transform.param + + // All inputs and inits are accessed with a projected permutation. + transform.match.structured.input %c[all] {projected_permutation} + : !transform.any_op + transform.match.structured.init %c[0] {projected_permutation} + : !transform.any_op + + // The body is a mulf/addf contraction with appropriate dimensions. + transform.match.structured.body %c + { contraction = ["arith.mulf", "arith.addf"] } : !transform.any_op + %batch, %lhs, %rhs, %reduction = + transform.match.structured.classify_contraction_dims %c + : (!transform.any_op) + -> (!transform.param, !transform.param, !transform.param, + !transform.param) + + + // There is one of lhs, rhs and reduction dimensions and zero batch + // dimensions. + %n_batch = transform.num_associations %batch + : (!transform.param) -> !transform.param + %n_lhs = transform.num_associations %lhs + : (!transform.param) -> !transform.param + %n_rhs = transform.num_associations %rhs + : (!transform.param) -> !transform.param + %n_reduction = transform.num_associations %reduction + : (!transform.param) -> !transform.param + %c0 = transform.param.constant 0 : i64 -> !transform.param + transform.match.param.cmpi eq %n_batch, %c0 : !transform.param + transform.match.param.cmpi eq %n_lhs, %c1 : !transform.param + transform.match.param.cmpi eq %n_rhs, %c1 : !transform.param + transform.match.param.cmpi eq %n_reduction, %c1 : !transform.param + } + transform.yield %candidate : !transform.any_op +} +``` + + +While this example leverages the contraction-specific matchers that have a +rather non-trivial C++ implementation, the transform dialect is sufficiently +flexible to implement this reasoning directly if desired. One could, for +example, obtain the access map of each input as a parameter and extract the +accessed dimensions as other parameters that can be compared with each other to +ensure the subscripts are `m,k` for LHS, `k,n` for RHS and `m,n` for the +init/result given the `m,n,k` notation for loops. + diff --git a/mlir/docs/Tutorials/transform/_index.md b/mlir/docs/Tutorials/transform/_index.md index b508a5d1d535..8a5af5625450 100644 --- a/mlir/docs/Tutorials/transform/_index.md +++ b/mlir/docs/Tutorials/transform/_index.md @@ -26,6 +26,7 @@ The tutorial is divided into the following chapters. - [Chapter #1](Ch1.md): Combining Existing Transformations - [Chapter #2](Ch2.md): Adding a Simple New Transformation Operation - [Chapter #3](Ch3.md): More than Simple Transform Operations +- [Chapter #4](Ch4.md): Matching Payload with Transform Operations - [Chapter H](ChH.md): Reproducing Halide Schedule The code corresponding to this tutorial is located under diff --git a/mlir/examples/transform/CMakeLists.txt b/mlir/examples/transform/CMakeLists.txt index 3f3740ad2a8d..b688aa7461d6 100644 --- a/mlir/examples/transform/CMakeLists.txt +++ b/mlir/examples/transform/CMakeLists.txt @@ -2,3 +2,4 @@ add_custom_target(TransformExample) add_subdirectory(Ch2) add_subdirectory(Ch3) +add_subdirectory(Ch4) diff --git a/mlir/examples/transform/Ch3/transform-opt/transform-opt.cpp b/mlir/examples/transform/Ch3/transform-opt/transform-opt.cpp index 1e4367ad4690..3c348c663aba 100644 --- a/mlir/examples/transform/Ch3/transform-opt/transform-opt.cpp +++ b/mlir/examples/transform/Ch3/transform-opt/transform-opt.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This is the top-level file for the Transform dialect tutorial chapter 2. +// This is the top-level file for the Transform dialect tutorial chapter 3. // //===----------------------------------------------------------------------===// diff --git a/mlir/examples/transform/Ch4/CMakeLists.txt b/mlir/examples/transform/Ch4/CMakeLists.txt new file mode 100644 index 000000000000..c070a04a35a8 --- /dev/null +++ b/mlir/examples/transform/Ch4/CMakeLists.txt @@ -0,0 +1,21 @@ +# For a better top-level template to copy, see examples/standalone. + +include_directories(${CMAKE_CURRENT_BINARY_DIR}) +include_directories(${CMAKE_CURRENT_BINARY_DIR}/include) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include) + +add_subdirectory(include) +add_subdirectory(lib) + +add_dependencies(TransformExample transform-opt-ch4) +add_llvm_example(transform-opt-ch4 + transform-opt/transform-opt.cpp) + +target_link_libraries(transform-opt-ch4 + PRIVATE + MLIRIR + MLIRMlirOptMain + MLIRSideEffectInterfaces + MLIRTransformDialectTransforms + MyExtensionCh4 +) diff --git a/mlir/examples/transform/Ch4/include/CMakeLists.txt b/mlir/examples/transform/Ch4/include/CMakeLists.txt new file mode 100644 index 000000000000..1f960e590529 --- /dev/null +++ b/mlir/examples/transform/Ch4/include/CMakeLists.txt @@ -0,0 +1,14 @@ +# Tell Tablegen to use MyExtension.td as input. +set(LLVM_TARGET_DEFINITIONS MyExtension.td) + +# Ask Tablegen to generate op declarations and definitions from ODS. +mlir_tablegen(MyExtension.h.inc -gen-op-decls) +mlir_tablegen(MyExtension.cpp.inc -gen-op-defs) + +# Add a CMakeTarget we can depend on to ensure the generation happens before the +# compilation. +add_public_tablegen_target(MyExtensionCh4IncGen) + +# Don't forget to generate the documentation, this will produce a +# MyExtensionCh4.md under Tutorials/transform +add_mlir_doc(MyExtension MyExtensionCh4 Tutorials/transform/ -gen-op-doc) diff --git a/mlir/examples/transform/Ch4/include/MyExtension.h b/mlir/examples/transform/Ch4/include/MyExtension.h new file mode 100644 index 000000000000..13e5b3c04b02 --- /dev/null +++ b/mlir/examples/transform/Ch4/include/MyExtension.h @@ -0,0 +1,30 @@ +//===-- MyExtension.h - Transform dialect tutorial --------------*- c++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines Transform dialect extension operations used in the +// Chapter 4 of the Transform dialect tutorial. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Bytecode/BytecodeOpInterface.h" +#include "mlir/Dialect/Transform/IR/TransformDialect.h" +#include "mlir/Dialect/Transform/IR/TransformInterfaces.h" +#include "mlir/Dialect/Transform/IR/TransformOps.h" + +namespace mlir { +class CallOpInterface; +namespace func { +class CallOp; +} // namespace func +} // namespace mlir + +#define GET_OP_CLASSES +#include "MyExtension.h.inc" + +// Registers our Transform dialect extension. +void registerMyExtension(::mlir::DialectRegistry ®istry); diff --git a/mlir/examples/transform/Ch4/include/MyExtension.td b/mlir/examples/transform/Ch4/include/MyExtension.td new file mode 100644 index 000000000000..ae58dc37db43 --- /dev/null +++ b/mlir/examples/transform/Ch4/include/MyExtension.td @@ -0,0 +1,46 @@ +//===-- MyExtension.td - Transform dialect tutorial --------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines Transform dialect extension operations used in the +// Chapter 4 of the Transform dialect tutorial. +// +//===----------------------------------------------------------------------===// + +#ifndef MY_EXTENSION +#define MY_EXTENSION + +include "mlir/Dialect/Transform/IR/MatchInterfaces.td" +include "mlir/Dialect/Transform/IR/TransformDialect.td" +include "mlir/Dialect/Transform/IR/TransformInterfaces.td" +include "mlir/IR/OpBase.td" +include "mlir/Interfaces/SideEffectInterfaces.td" + +// Define the new operation. By convention, prefix its name with `match` +// followed by the name of the dialect extension. +def HasOperandSatisfyingOp : TransformDialectOp<"match.my.has_operand_satisfying", + [DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods, + // Indicate that the operation implements MatchOpInterface in addition to + // the TransformOpInterface. This interface is only used as a tag at this + // point and has no methods that are mandatory to implement. + MatchOpInterface, + SingleBlockImplicitTerminator<"::mlir::transform::YieldOp">]> { + let summary = "Succeed if any of the operands matches all nested criteria"; + let arguments = (ins TransformHandleTypeInterface:$op); + let results = (outs TransformParamTypeInterface:$position, + Variadic:$results); + + // Match operations can be arbitrarily complex, e.g., containing regions. + let regions = (region SizedRegion<1>:$body); + let hasVerifier = 1; + let assemblyFormat = [{ + $op `:` functional-type($op, results) attr-dict-with-keyword $body + }]; +} + +#endif // MY_EXTENSION diff --git a/mlir/examples/transform/Ch4/lib/CMakeLists.txt b/mlir/examples/transform/Ch4/lib/CMakeLists.txt new file mode 100644 index 000000000000..33338a679af3 --- /dev/null +++ b/mlir/examples/transform/Ch4/lib/CMakeLists.txt @@ -0,0 +1,20 @@ +# Outside examples, this should be `add_mlir_library`. +add_mlir_example_library( + # Library called MyExtension. + MyExtensionCh4 + + # Built from the following source files. + MyExtension.cpp + + # Make includes visible without top-level path. + ADDITIONAL_HEADER_DIRS + ${PROJECT_SOURCE_DIR}/examples/transform/Ch4/include + + # Make sure ODS declaration and definitions are generated before compiling this. + DEPENDS + MyExtensionCh4IncGen + + # Link in the transform dialect, an all generated dialects. + LINK_LIBS PRIVATE + MLIRTransformDialect +) diff --git a/mlir/examples/transform/Ch4/lib/MyExtension.cpp b/mlir/examples/transform/Ch4/lib/MyExtension.cpp new file mode 100644 index 000000000000..26e348f2a30e --- /dev/null +++ b/mlir/examples/transform/Ch4/lib/MyExtension.cpp @@ -0,0 +1,207 @@ +//===-- MyExtension.cpp - Transform dialect tutorial ----------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines Transform dialect extension operations used in the +// Chapter 4 of the Transform dialect tutorial. +// +//===----------------------------------------------------------------------===// + +#include "MyExtension.h" +#include "mlir/Dialect/Transform/IR/TransformDialect.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE_MATCHER "transform-matcher" +#define DBGS_MATCHER() (llvm::dbgs() << "[" DEBUG_TYPE_MATCHER "] ") +#define DEBUG_MATCHER(x) DEBUG_WITH_TYPE(DEBUG_TYPE_MATCHER, x) + +#define GET_OP_CLASSES +#include "MyExtension.cpp.inc" + +//===---------------------------------------------------------------------===// +// MyExtension +//===---------------------------------------------------------------------===// + +// Define a new transform dialect extension. This uses the CRTP idiom to +// identify extensions. +class MyExtension + : public ::mlir::transform::TransformDialectExtension { +public: + // The extension must derive the base constructor. + using Base::Base; + + // This function initializes the extension, similarly to `initialize` in + // dialect definitions. List individual operations and dependent dialects + // here. + void init(); +}; + +void MyExtension::init() { + // Register the additional match operations with the dialect similarly to + // other transform operations. List all operations generated from ODS. This + // call will perform additional checks that the operations implement the + // transform and memory effect interfaces required by the dialect interpreter + // and assert if they do not. + registerTransformOps< +#define GET_OP_LIST +#include "MyExtension.cpp.inc" + >(); +} + +//===---------------------------------------------------------------------===// +// HasOperandSatisfyingOp +//===---------------------------------------------------------------------===// + +/// Returns `true` if both types implement one of the interfaces provided as +/// template parameters. +template +static bool implementSameInterface(mlir::Type t1, mlir::Type t2) { + return ((llvm::isa(t1) && llvm::isa(t2)) || ... || false); +} + +/// Returns `true` if both types implement one of the transform dialect +/// interfaces. +static bool implementSameTransformInterface(mlir::Type t1, mlir::Type t2) { + return implementSameInterface< + mlir::transform::TransformHandleTypeInterface, + mlir::transform::TransformParamTypeInterface, + mlir::transform::TransformValueHandleTypeInterface>(t1, t2); +} + +// Matcher ops implement `apply` similarly to other transform ops. They are not +// expected to modify payload, but use the tri-state result to signal failure or +// success to match, as well as potential irrecoverable errors. +mlir::DiagnosedSilenceableFailure +mlir::transform::HasOperandSatisfyingOp::apply( + mlir::transform::TransformRewriter &rewriter, + mlir::transform::TransformResults &results, + mlir::transform::TransformState &state) { + // For simplicity, only handle a single payload op. Actual implementations + // can use `SingleOpMatcher` trait to simplify implementation and document + // this expectation. + auto payloadOps = state.getPayloadOps(getOp()); + if (!llvm::hasSingleElement(payloadOps)) + return emitSilenceableError() << "expected single payload"; + + // Iterate over all operands of the payload op to see if they can be matched + // using the body of this op. + Operation *payload = *payloadOps.begin(); + for (OpOperand &operand : payload->getOpOperands()) { + // Create a scope for transform values defined in the body. This corresponds + // to the syntactic scope of the region attached to this op. Any values + // associated with payloads from now on will be automatically dissociated + // when this object is destroyed, i.e. at the end of the iteration. + // Associate the block argument handle with the operand. + auto matchScope = state.make_region_scope(getBody()); + if (failed(state.mapBlockArgument(getBody().getArgument(0), + {operand.get()}))) { + return DiagnosedSilenceableFailure::definiteFailure(); + } + + // Iterate over all nested matchers with the current mapping and see if they + // succeed. + bool matchSucceeded = true; + for (Operation &matcher : getBody().front().without_terminator()) { + // Matcher ops are applied similarly to any other transform op. + DiagnosedSilenceableFailure diag = + state.applyTransform(cast(matcher)); + + // Definite failures are immediately propagated as they are irrecoverable. + if (diag.isDefiniteFailure()) + return diag; + + // On success, keep checking the remaining conditions. + if (diag.succeeded()) + continue; + + // Report failure-to-match for debugging purposes and stop matching this + // operand. + assert(diag.isSilenceableFailure()); + DEBUG_MATCHER(DBGS_MATCHER() + << "failed to match operand #" << operand.getOperandNumber() + << ": " << diag.getMessage()); + (void)diag.silence(); + matchSucceeded = false; + break; + } + // If failed to match this operand, try other operands. + if (!matchSucceeded) + continue; + + // If we reached this point, the matching succeeded for the current operand. + // Remap the values associated with terminator operands to be associated + // with op results, and also map the parameter result to the operand's + // position. Note that it is safe to do here despite the end of the scope + // as `results` are integrated into `state` by the interpreter after `apply` + // returns rather than immediately. + SmallVector> yieldedMappings; + transform::detail::prepareValueMappings( + yieldedMappings, getBody().front().getTerminator()->getOperands(), + state); + results.setParams(getPosition().cast(), + {rewriter.getI32IntegerAttr(operand.getOperandNumber())}); + for (auto &&[result, mapping] : llvm::zip(getResults(), yieldedMappings)) + results.setMappedValues(result, mapping); + return DiagnosedSilenceableFailure::success(); + } + + // If we reached this point, none of the operands succeeded the match. + return emitSilenceableError() + << "none of the operands satisfied the conditions"; +} + +// By convention, operations implementing MatchOpInterface must not modify +// payload IR and must therefore specify that they only read operand handles and +// payload as their effects. +void mlir::transform::HasOperandSatisfyingOp::getEffects( + llvm::SmallVectorImpl &effects) { + onlyReadsPayload(effects); + onlyReadsHandle(getOp(), effects); + producesHandle(getPosition(), effects); + producesHandle(getResults(), effects); +} + +// Verify well-formedness of the operation and emit diagnostics if it is +// ill-formed. +mlir::LogicalResult mlir::transform::HasOperandSatisfyingOp::verify() { + mlir::Block &bodyBlock = getBody().front(); + if (bodyBlock.getNumArguments() != 1 || + !isa( + bodyBlock.getArgument(0).getType())) { + return emitOpError() + << "expects the body to have one value handle argument"; + } + if (bodyBlock.getTerminator()->getNumOperands() != getNumResults() - 1) { + return emitOpError() << "expects the body to yield " + << (getNumResults() - 1) << " values, got " + << bodyBlock.getTerminator()->getNumOperands(); + } + for (auto &&[i, operand, result] : + llvm::enumerate(bodyBlock.getTerminator()->getOperands().getTypes(), + getResults().getTypes())) { + if (implementSameTransformInterface(operand, result)) + continue; + return emitOpError() << "expects terminator operand #" << i + << " and result #" << (i + 1) + << " to implement the same transform interface"; + } + + for (Operation &op : bodyBlock.without_terminator()) { + if (!isa(op) || !isa(op)) { + InFlightDiagnostic diag = emitOpError() + << "expects body to contain match ops"; + diag.attachNote(op.getLoc()) << "non-match operation"; + return diag; + } + } + + return success(); +} + +void registerMyExtension(::mlir::DialectRegistry ®istry) { + registry.addExtensions(); +} diff --git a/mlir/examples/transform/Ch4/transform-opt/transform-opt.cpp b/mlir/examples/transform/Ch4/transform-opt/transform-opt.cpp new file mode 100644 index 000000000000..10190664b51c --- /dev/null +++ b/mlir/examples/transform/Ch4/transform-opt/transform-opt.cpp @@ -0,0 +1,55 @@ +//===-- transform-opt.cpp - Transform dialect tutorial entry point --------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This is the top-level file for the Transform dialect tutorial chapter 4. +// +//===----------------------------------------------------------------------===// + +#include "MyExtension.h" + +#include "mlir/Dialect/Transform/Transforms/Passes.h" +#include "mlir/IR/DialectRegistry.h" +#include "mlir/IR/MLIRContext.h" +#include "mlir/InitAllDialects.h" +#include "mlir/InitAllExtensions.h" +#include "mlir/Tools/mlir-opt/MlirOptMain.h" +#include "mlir/Transforms/Passes.h" +#include + +namespace test { +void registerTestTransformDialectExtension(mlir::DialectRegistry &); +} // namespace test + +int main(int argc, char **argv) { + // Register all "core" dialects and our transform dialect extension. + mlir::DialectRegistry registry; + mlir::registerAllDialects(registry); + mlir::registerAllExtensions(registry); + registerMyExtension(registry); + + // Register a handful of cleanup passes that we can run to make the output IR + // look nicer. + mlir::registerCanonicalizerPass(); + mlir::registerCSEPass(); + mlir::registerSymbolDCEPass(); + mlir::transform::registerInterpreterPass(); + + // Register the test passes. +#ifdef MLIR_INCLUDE_TESTS + test::registerTestTransformDialectExtension(registry); +#else + llvm::errs() << "warning: MLIR built without test extension, interpreter " + "testing will not be available\n"; +#endif // MLIR_INCLUDE_TESTS + + // Delegate to the MLIR utility for parsing and pass management. + return mlir::MlirOptMain(argc, argv, "transform-opt-ch4", registry) + .succeeded() + ? EXIT_SUCCESS + : EXIT_FAILURE; +} diff --git a/mlir/test/CMakeLists.txt b/mlir/test/CMakeLists.txt index 7ec4c8f0963a..8ce030feeded 100644 --- a/mlir/test/CMakeLists.txt +++ b/mlir/test/CMakeLists.txt @@ -166,6 +166,8 @@ if(LLVM_BUILD_EXAMPLES) list(APPEND MLIR_TEST_DEPENDS transform-opt-ch2 transform-opt-ch3 + transform-opt-ch4 + mlir-minimal-opt ) if(MLIR_ENABLE_EXECUTION_ENGINE) list(APPEND MLIR_TEST_DEPENDS diff --git a/mlir/test/Examples/transform/Ch4/features.mlir b/mlir/test/Examples/transform/Ch4/features.mlir new file mode 100644 index 000000000000..9a2af474aa4f --- /dev/null +++ b/mlir/test/Examples/transform/Ch4/features.mlir @@ -0,0 +1,123 @@ +// RUN: transform-opt-ch4 %s --transform-interpreter --verify-diagnostics + +// Matmul as a named operation. +func.func @named( + %lhs: tensor<512x512xf32>, %rhs: tensor<512x512xf32>, + %bias: tensor<512x512xf32>, %output: tensor<512x512xf32>) + -> tensor<512x512xf32> { + // expected-remark @below {{matmul}} + %matmul = linalg.matmul ins(%lhs, %rhs: tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output: tensor<512x512xf32>) -> tensor<512x512xf32> + func.return %matmul : tensor<512x512xf32> +} + +// Matmul as a generic operation. +func.func @generic( + %lhs: tensor<512x512xf32>, %rhs: tensor<512x512xf32>, + %bias: tensor<512x512xf32>, %output: tensor<512x512xf32>) + -> tensor<512x512xf32> { + // expected-remark @below {{matmul}} + %matmul = linalg.generic { + iterator_types = ["parallel", "parallel", "reduction"], + indexing_maps = [ + affine_map<(d0, d1, d2) -> (d0, d2)>, + affine_map<(d0, d1, d2) -> (d2, d1)>, + affine_map<(d0, d1, d2) -> (d0, d1)>] + } ins(%lhs, %rhs: tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output: tensor<512x512xf32>) { + ^bb0(%arg0: f32, %arg1: f32, %arg2: f32): + %0 = arith.mulf %arg0, %arg1 : f32 + %1 = arith.addf %0, %arg2 : f32 + linalg.yield %1 : f32 + } -> tensor<512x512xf32> + return %matmul : tensor<512x512xf32> +} + +// The module containing named sequences must have an attribute allowing them +// to enable verification. +module @transforms attributes { transform.with_named_sequence } { + // Entry point. This takes as the only argument the root operation (typically + // pass root) given to the transform interpreter. + transform.named_sequence @__transform_main( + %root: !transform.any_op {transform.consumed}) { + + // Traverses the payload IR associated with the operand handle, invoking + // @match_matmul_elemwise on each of the operations. If the named sequence + // succeeds, i.e., if none of the nested match (transform) operations + // produced a silenceable failure, invokes @print_matmul_elemwise and + // forwards the values yielded as arguments of the new invocation. If the + // named sequence fails with a silenceable failure, silences it (the message + // is forwarded to the debug stream). Definite failures are propagated + // immediately and unconditionally, as usual. + transform.foreach_match in %root + @match_generic_matmul -> @print_generic_matmul + : (!transform.any_op) -> !transform.any_op + + transform.yield + } + + // This is an action sequence. + transform.named_sequence @print_generic_matmul( + %matmul: !transform.any_op {transform.readonly}) { + transform.test_print_remark_at_operand %matmul, "matmul" : !transform.any_op + transform.yield + } + + transform.named_sequence @match_generic_matmul( + %candidate: !transform.any_op {transform.readonly}) -> !transform.any_op { + // Match a structured linear algebra operation. + transform.match.structured %candidate : !transform.any_op { + ^bb0(%c: !transform.any_op): + // With a rank equal to 3. + %rank = transform.match.structured.rank %c + : (!transform.any_op) -> !transform.param + %c3 = transform.param.constant 3 : i64 -> !transform.param + transform.match.param.cmpi eq %rank, %c3 : !transform.param + + // With 2 inputs. + %n_ins = transform.match.structured.num_inputs %c + : (!transform.any_op) -> !transform.param + %c2 = transform.param.constant 2 : i64 -> !transform.param + transform.match.param.cmpi eq %n_ins, %c2 : !transform.param + + // With 1 output (note that structured ops in destination passing style + // has as many inits as outputs). + %n_inits = transform.match.structured.num_inits %c + : (!transform.any_op) -> !transform.param + %c1 = transform.param.constant 1 : i64 -> !transform.param + transform.match.param.cmpi eq %n_inits, %c1 : !transform.param + + // All inputs and inits are accessed with a projected permutation. + transform.match.structured.input %c[all] {projected_permutation} + : !transform.any_op + transform.match.structured.init %c[0] {projected_permutation} + : !transform.any_op + + // The body is a mulf/addf contraction with appropriate dimensions. + transform.match.structured.body %c + { contraction = ["arith.mulf", "arith.addf"] } : !transform.any_op + %batch, %lhs, %rhs, %reduction = + transform.match.structured.classify_contraction_dims %c + : (!transform.any_op) + -> (!transform.param, !transform.param, !transform.param, + !transform.param) + + // There is one of lhs, rhs and reduction dimensions and zero batch + // dimensions. + %n_batch = transform.num_associations %batch + : (!transform.param) -> !transform.param + %n_lhs = transform.num_associations %lhs + : (!transform.param) -> !transform.param + %n_rhs = transform.num_associations %rhs + : (!transform.param) -> !transform.param + %n_reduction = transform.num_associations %reduction + : (!transform.param) -> !transform.param + %c0 = transform.param.constant 0 : i64 -> !transform.param + transform.match.param.cmpi eq %n_batch, %c0 : !transform.param + transform.match.param.cmpi eq %n_lhs, %c1 : !transform.param + transform.match.param.cmpi eq %n_rhs, %c1 : !transform.param + transform.match.param.cmpi eq %n_reduction, %c1 : !transform.param + } + transform.yield %candidate : !transform.any_op + } +} diff --git a/mlir/test/Examples/transform/Ch4/multiple.mlir b/mlir/test/Examples/transform/Ch4/multiple.mlir new file mode 100644 index 000000000000..22ef7c99f86a --- /dev/null +++ b/mlir/test/Examples/transform/Ch4/multiple.mlir @@ -0,0 +1,131 @@ +// RUN: transform-opt-ch4 %s --transform-interpreter --verify-diagnostics + +// Matmul+ReLU. +func.func @fc_relu_operands_00( + %lhs: tensor<512x512xf32>, %rhs: tensor<512x512xf32>, + %bias: tensor<512x512xf32>, %output: tensor<512x512xf32>) + -> tensor<512x512xf32> { + // Matrix-matrix multiplication. + // expected-remark @below {{matmul # 0}} + %matmul = linalg.matmul ins(%lhs, %rhs: tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output: tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise addition. + // expected-remark @below {{add # 0}} + %biased = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%matmul, %bias : tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise max with 0 (ReLU). + %c0f = arith.constant 0.0 : f32 + // expected-remark @below {{max # 0}} + %relued = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%biased, %c0f : tensor<512x512xf32>, f32) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + func.return %relued : tensor<512x512xf32> +} + +// Matmul+ReLU with swapped operands. +func.func @fc_relu_operands_01( + %lhs: tensor<512x512xf32>, %rhs: tensor<512x512xf32>, + %bias: tensor<512x512xf32>, %output: tensor<512x512xf32>) + -> tensor<512x512xf32> { + // Matrix-matrix multiplication. + // expected-remark @below {{matmul # 1}} + %matmul = linalg.matmul ins(%lhs, %rhs: tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output: tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise addition. + // expected-remark @below {{add # 1}} + %biased = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%matmul, %bias : tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise max with 0 (ReLU). + %c0f = arith.constant 0.0 : f32 + // expected-remark @below {{max # 1}} + %relued = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%c0f, %biased : f32, tensor<512x512xf32>) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + func.return %relued : tensor<512x512xf32> +} + +// The module containing named sequences must have an attribute allowing them +// to enable verification. +module @transforms attributes { transform.with_named_sequence } { + // Entry point. This takes as the only argument the root operation (typically + // pass root) given to the transform interpreter. + transform.named_sequence @__transform_main( + %root: !transform.any_op {transform.consumed}) { + + // Traverses the payload IR associated with the operand handle, invoking + // @match_matmul_elemwise on each of the operations. If the named sequence + // succeeds, i.e., if none of the nested match (transform) operations + // produced a silenceable failure, invokes @print_matmul_elemwise and + // forwards the values yielded as arguments of the new invocation. If the + // named sequence fails with a silenceable failure, silences it (the message + // is forwarded to the debug stream). Definite failures are propagated + // immediately and unconditionally, as usual. + transform.foreach_match in %root + @match_matmul_elemwise -> @print_matmul_elemwise + : (!transform.any_op) -> !transform.any_op + + transform.yield + } + + // This is an action sequence. + transform.named_sequence @print_matmul_elemwise( + %matmul: !transform.any_op {transform.readonly}, + %add: !transform.any_op {transform.readonly}, + %max: !transform.any_op {transform.readonly}, + %pos: !transform.param {transform.readonly}) { + transform.test_print_param %pos, "matmul #" at %matmul + : !transform.param, !transform.any_op + transform.test_print_param %pos, "add #" at %add + : !transform.param, !transform.any_op + transform.test_print_param %pos, "max #" at %max + : !transform.param, !transform.any_op + transform.yield + } + + // This is also a matcher sequence. It is similarly given an operation to + // match and nested operations must succeed in order for a match to be deemed + // successful. It starts matching from the last operation in the use-def chain + // and goes back because each operand (use) has exactly one definition. + transform.named_sequence @match_matmul_elemwise( + %last: !transform.any_op {transform.readonly}) + -> (!transform.any_op, !transform.any_op, !transform.any_op, + !transform.param) { + // The last operation must be an elementwise binary. + transform.match.operation_name %last ["linalg.elemwise_binary"] + : !transform.any_op + + // One of its operands must be defined by another operation, to which we + // will get a handle here. This is achieved thanks to a newly defined + // operation that tries to match operands one by one using the match + // operations nested in its region. + %pos, %middle = transform.match.my.has_operand_satisfying %last + : (!transform.any_op) -> (!transform.param, !transform.any_op) { + ^bb0(%operand: !transform.any_value): + // The operand must be defined by an operation. + %def = transform.get_defining_op %operand + : (!transform.any_value) -> !transform.any_op + // The defining operation must itself be an elementwise binary. + transform.match.operation_name %def ["linalg.elemwise_binary"] + : !transform.any_op + transform.yield %def : !transform.any_op + } + + // And the first operand of that operation must be defined by yet another + // operation. + %matmul = transform.get_producer_of_operand %middle[0] + : (!transform.any_op) -> !transform.any_op + // And that operation is a matmul. + transform.match.operation_name %matmul ["linalg.matmul"] : !transform.any_op + // We will yield the handles to the matmul and the two elementwise + // operations separately. + transform.yield %matmul, %middle, %last, %pos + : !transform.any_op, !transform.any_op, !transform.any_op, + !transform.param + } +} diff --git a/mlir/test/Examples/transform/Ch4/sequence.mlir b/mlir/test/Examples/transform/Ch4/sequence.mlir new file mode 100644 index 000000000000..28c3e9649bd9 --- /dev/null +++ b/mlir/test/Examples/transform/Ch4/sequence.mlir @@ -0,0 +1,139 @@ +// RUN: transform-opt-ch4 %s --transform-interpreter --verify-diagnostics +// +// RUN: transform-opt-ch4 %s \ +// RUN: --transform-interpreter='entry-point=__transform_main_v2' \ +// RUN: --verify-diagnostics + +// ****************************** IMPORTANT NOTE ****************************** +// +// If you are changing this file, you may also need to change +// mlir/docs/Tutorials/Transform accordingly. +// +// **************************************************************************** + +// Original function to optimize. +func.func @fc_relu(%lhs: tensor<512x512xf32>, %rhs: tensor<512x512xf32>, + %bias: tensor<512x512xf32>, %output: tensor<512x512xf32>) + -> tensor<512x512xf32> { + // Matrix-matrix multiplication. + // expected-remark @below {{matmul}} + %matmul = linalg.matmul ins(%lhs, %rhs: tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output: tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise addition. + // expected-remark @below {{elementwise binary}} + %biased = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%matmul, %bias : tensor<512x512xf32>, tensor<512x512xf32>) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + + // Elementwise max with 0 (ReLU). + %c0f = arith.constant 0.0 : f32 + // expected-remark @below {{elementwise binary}} + %relued = linalg.elemwise_binary { fun = #linalg.binary_fn } + ins(%biased, %c0f : tensor<512x512xf32>, f32) + outs(%output : tensor<512x512xf32>) -> tensor<512x512xf32> + func.return %relued : tensor<512x512xf32> +} + +// The module containing named sequences must have an attribute allowing them +// to enable verification. +module @transforms attributes { transform.with_named_sequence } { + // Entry point. This takes as the only argument the root operation (typically + // pass root) given to the transform interpreter. + transform.named_sequence @__transform_main( + %root: !transform.any_op {transform.readonly}) { + // Collect operations that match the criteria specified in the named + // sequence. If the named sequence fails with a silenceable failure, + // silences it (the message is forwarded to the debug stream). If the named + // sequence succeeds, appends its results to the results of this operation. + %elemwise = transform.collect_matching @match_elemwise in %root + : (!transform.any_op) -> !transform.any_op + %matmul = transform.collect_matching @match_matmul in %root + : (!transform.any_op) -> !transform.any_op + + transform.include @print_elemwise failures(propagate) (%elemwise) + : (!transform.any_op) -> () + transform.include @print_matmul failures(propagate) (%matmul) + : (!transform.any_op) -> () + + transform.yield + } + + // Alternative entry point. + transform.named_sequence @__transform_main_v2( + %root: !transform.any_op {transform.readonly}) { + // Collect groups of operations that match the criteria specified in the + // named sequence. + %matmul, %el1, %el2 = transform.collect_matching @match_matmul_elemwise in %root + : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %elemwise = transform.merge_handles %el1, %el2 : !transform.any_op + + transform.include @print_elemwise failures(propagate) (%elemwise) + : (!transform.any_op) -> () + transform.include @print_matmul failures(propagate) (%matmul) + : (!transform.any_op) -> () + + transform.yield + } + + // This is a matcher sequence. It is given an operation to match and the + // match is considered successful unless any nested operation produces a + // failure. The values yielded by this operation will be forwarded to the + // rewriter sequence on success. + transform.named_sequence @match_elemwise( + %entry: !transform.any_op {transform.readonly}) -> !transform.any_op { + transform.match.operation_name %entry ["linalg.elemwise_binary"] + : !transform.any_op + transform.yield %entry : !transform.any_op + } + transform.named_sequence @match_matmul( + %entry: !transform.any_op {transform.readonly}) -> !transform.any_op { + transform.match.operation_name %entry ["linalg.matmul"] : !transform.any_op + transform.yield %entry : !transform.any_op + } + + // This is an action sequence. + transform.named_sequence @print_elemwise( + %elemwise_binary: !transform.any_op {transform.readonly}) { + transform.test_print_remark_at_operand + %elemwise_binary, "elementwise binary" : !transform.any_op + transform.yield + } + transform.named_sequence @print_matmul( + %matmul: !transform.any_op {transform.readonly}) { + transform.test_print_remark_at_operand %matmul, "matmul" : !transform.any_op + transform.yield + } + + // This is also a matcher sequence. It is similarly given an operation to + // match and nested operations must succeed in order for a match to be deemed + // successful. It starts matching from the last operation in the use-def chain + // and goes back because each operand (use) has exactly one definition. + transform.named_sequence @match_matmul_elemwise( + %last: !transform.any_op {transform.readonly}) + -> (!transform.any_op, !transform.any_op, !transform.any_op) { + // The last operation must be an elementwise binary. + transform.match.operation_name %last ["linalg.elemwise_binary"] + : !transform.any_op + // Its first operand must be defined by another operation, to which we + // will get a handle here. We are guaranteed that the first operand exists + // because we know the operation is binary, but even in absence of such a + // guarantee, this operation would have produced a silenceable failure when + // `%last` does not have enough operands. + %middle = transform.get_producer_of_operand %last[0] + : (!transform.any_op) -> !transform.any_op + // The defining operation must itself be an elementwise binary. + transform.match.operation_name %middle ["linalg.elemwise_binary"] + : !transform.any_op + // And the first operand of that operation must be defined by yet another + // operation. + %matmul = transform.get_producer_of_operand %middle[0] + : (!transform.any_op) -> !transform.any_op + // And that operation is a matmul. + transform.match.operation_name %matmul ["linalg.matmul"] : !transform.any_op + // We will yield the handles to the matmul and the two elementwise + // operations separately. + transform.yield %matmul, %middle, %last + : !transform.any_op, !transform.any_op, !transform.any_op + } +} diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py index 5b92491175e5..0a1ea1d16da4 100644 --- a/mlir/test/lit.cfg.py +++ b/mlir/test/lit.cfg.py @@ -154,8 +154,9 @@ tools.extend( ToolSubst("toyc-ch5", unresolved="ignore"), ToolSubst("toyc-ch6", unresolved="ignore"), ToolSubst("toyc-ch7", unresolved="ignore"), - ToolSubst('transform-opt-ch2', unresolved='ignore'), - ToolSubst('transform-opt-ch3', unresolved='ignore'), + ToolSubst("transform-opt-ch2", unresolved="ignore"), + ToolSubst("transform-opt-ch3", unresolved="ignore"), + ToolSubst("transform-opt-ch4", unresolved="ignore"), ToolSubst("%mlir_lib_dir", config.mlir_lib_dir, unresolved="ignore"), ToolSubst("%mlir_src_dir", config.mlir_src_root, unresolved="ignore"), ] -- GitLab From 197214e39b7100dd0e88aa38cffdce9ee1f4464b Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Tue, 9 Jan 2024 12:25:17 +0000 Subject: [PATCH 194/652] [RFC][SelectionDAG] Add and use SDNode::getAsZExtVal() helper (#76710) This follows on from #76708, allowing `cast(N)->getZExtValue()` to be replaced with just `N->getAsZextVal();` Introduced via `git grep -l "cast\(.*\).*getZExtValue" | xargs sed -E -i 's/cast\((.*)\)->getZExtValue/\1->getAsZExtVal/'` and then using `git clang-format` on the result. --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 7 ++++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- .../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 4 +-- .../SelectionDAG/LegalizeFloatTypes.cpp | 2 +- .../SelectionDAG/LegalizeIntegerTypes.cpp | 2 +- .../SelectionDAG/LegalizeVectorTypes.cpp | 10 +++--- .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 ++-- .../SelectionDAG/SelectionDAGBuilder.cpp | 33 ++++++++----------- .../SelectionDAG/SelectionDAGDumper.cpp | 2 +- .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 15 ++++----- .../Target/AArch64/AArch64ISelDAGToDAG.cpp | 6 ++-- .../Target/AArch64/AArch64ISelLowering.cpp | 11 +++---- .../AArch64/AArch64SelectionDAGInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 8 ++--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 ++-- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +-- llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp | 2 +- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 24 +++++++------- llvm/lib/Target/ARM/ARMISelLowering.cpp | 19 +++++------ llvm/lib/Target/AVR/AVRISelLowering.cpp | 4 +-- .../Target/Hexagon/HexagonISelDAGToDAG.cpp | 2 +- .../Target/Hexagon/HexagonISelLoweringHVX.cpp | 6 ++-- .../LoongArch/LoongArchISelLowering.cpp | 19 +++++------ llvm/lib/Target/M68k/M68kISelLowering.cpp | 4 +-- llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 4 +-- llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 6 ++-- llvm/lib/Target/Mips/MipsISelLowering.cpp | 3 +- llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 8 ++--- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 13 ++++---- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 16 ++++----- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 21 +++++------- .../Target/SystemZ/SystemZISelDAGToDAG.cpp | 8 ++--- .../Target/SystemZ/SystemZISelLowering.cpp | 27 +++++++-------- .../WebAssembly/WebAssemblyISelLowering.cpp | 7 ++-- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 22 ++++++------- llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp | 2 +- 40 files changed, 159 insertions(+), 186 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 7f957878343a..ebf410cc94de 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -929,6 +929,9 @@ public: /// Helper method returns the integer value of a ConstantSDNode operand. inline uint64_t getConstantOperandVal(unsigned Num) const; + /// Helper method returns the zero-extended integer value of a ConstantSDNode. + inline uint64_t getAsZExtVal() const; + /// Helper method returns the APInt of a ConstantSDNode operand. inline const APInt &getConstantOperandAPInt(unsigned Num) const; @@ -1645,6 +1648,10 @@ uint64_t SDNode::getConstantOperandVal(unsigned Num) const { return cast(getOperand(Num))->getZExtValue(); } +uint64_t SDNode::getAsZExtVal() const { + return cast(this)->getZExtValue(); +} + const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const { return cast(getOperand(Num))->getAPIntValue(); } diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 464e1becc0b8..2327664516cc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -14713,7 +14713,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { SDValue EltNo = N0->getOperand(1); if (isa(EltNo) && isTypeLegal(NVT)) { - int Elt = cast(EltNo)->getZExtValue(); + int Elt = EltNo->getAsZExtVal(); int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); SDLoc DL(N); diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 34fa1f5a7ed1..032cff416cda 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -551,7 +551,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, SDValue N0 = Node->getOperand(0); SDValue N1 = Node->getOperand(1); SDValue N2 = Node->getOperand(2); - unsigned SubIdx = cast(N2)->getZExtValue(); + unsigned SubIdx = N2->getAsZExtVal(); // Figure out the register class to create for the destreg. It should be // the largest legal register class supporting SubIdx sub-registers. @@ -650,7 +650,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node, // Skip physical registers as they don't have a vreg to get and we'll // insert copies for them in TwoAddressInstructionPass anyway. if (!R || !R->getReg().isPhysical()) { - unsigned SubIdx = cast(Op)->getZExtValue(); + unsigned SubIdx = Op->getAsZExtVal(); unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); const TargetRegisterClass *SRC = diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 6e0e1e23419b..589fec0e56f7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -2511,7 +2511,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) { EVT VecVT = Vec->getValueType(0); EVT EltVT = VecVT.getVectorElementType(); - uint64_t IdxVal = cast(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); switch (getTypeAction(VecVT)) { default: break; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 92598d885619..814f746f5a4d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -5570,7 +5570,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { getTypeAction(InVT) == TargetLowering::TypeLegal) { EVT NInVT = InVT.getHalfNumVectorElementsVT(*DAG.getContext()); unsigned NElts = NInVT.getVectorMinNumElements(); - uint64_t IdxVal = cast(BaseIdx)->getZExtValue(); + uint64_t IdxVal = BaseIdx->getAsZExtVal(); SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0, DAG.getConstant(alignDown(IdxVal, NElts), dl, diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 66461b26468f..ec74d2940099 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1442,7 +1442,7 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0)); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); - uint64_t IdxVal = cast(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); Hi = DAG.getNode( ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorMinNumElements(), dl)); @@ -1466,7 +1466,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, // If we know the index is in the first half, and we know the subvector // doesn't cross the boundary between the halves, we can avoid spilling the // vector, and insert into the lower half of the split vector directly. - unsigned IdxVal = cast(Idx)->getZExtValue(); + unsigned IdxVal = Idx->getAsZExtVal(); if (IdxVal + SubElems <= LoElems) { Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); return; @@ -3279,7 +3279,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_INSERT_SUBVECTOR(SDNode *N, SDValue Lo, Hi; GetSplitVector(SubVec, Lo, Hi); - uint64_t IdxVal = cast(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); uint64_t LoElts = Lo.getValueType().getVectorMinNumElements(); SDValue FirstInsertion = @@ -3301,7 +3301,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { GetSplitVector(N->getOperand(0), Lo, Hi); uint64_t LoEltsMin = Lo.getValueType().getVectorMinNumElements(); - uint64_t IdxVal = cast(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); if (IdxVal < LoEltsMin) { assert(IdxVal + SubVT.getVectorMinNumElements() <= LoEltsMin && @@ -5257,7 +5257,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { EVT InVT = InOp.getValueType(); // Check if we can just return the input vector after widening. - uint64_t IdxVal = cast(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); if (IdxVal == 0 && InVT == WidenVT) return InOp; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 4151964adc7d..b39be64c06f9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -7197,8 +7197,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, assert(isa(N3) && "Insert subvector index must be constant"); assert((VT.isScalableVector() != N2VT.isScalableVector() || - (N2VT.getVectorMinNumElements() + - cast(N3)->getZExtValue()) <= + (N2VT.getVectorMinNumElements() + N3->getAsZExtVal()) <= VT.getVectorMinNumElements()) && "Insert subvector overflow!"); assert(cast(N3)->getAPIntValue().getBitWidth() == @@ -9986,8 +9985,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, Ops[1].getValueType().isFloatingPoint() && VTList.VTs[0].bitsLT(Ops[1].getValueType()) && isa(Ops[2]) && - (cast(Ops[2])->getZExtValue() == 0 || - cast(Ops[2])->getZExtValue() == 1) && + (Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) && "Invalid STRICT_FP_ROUND!"); break; #if 0 diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 1ae682eaf251..2c477b947430 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5644,7 +5644,7 @@ static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, // expansion/promotion) if it was possible to expand a libcall of an // illegal type during operation legalization. But it's not, so things // get a bit hacky. - unsigned ScaleInt = cast(Scale)->getZExtValue(); + unsigned ScaleInt = Scale->getAsZExtVal(); if ((ScaleInt > 0 || (Saturating && Signed)) && (TLI.isTypeLegal(VT) || (VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) { @@ -7657,8 +7657,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, // suitable for the target. Convert the index as required. MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); if (Index.getValueType() != VectorIdxTy) - Index = DAG.getVectorIdxConstant( - cast(Index)->getZExtValue(), sdl); + Index = DAG.getVectorIdxConstant(Index->getAsZExtVal(), sdl); EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, @@ -7674,8 +7673,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, // suitable for the target. Convert the index as required. MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); if (Index.getValueType() != VectorIdxTy) - Index = DAG.getVectorIdxConstant( - cast(Index)->getZExtValue(), sdl); + Index = DAG.getVectorIdxConstant(Index->getAsZExtVal(), sdl); setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); @@ -8138,7 +8136,7 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic( case ISD::VP_IS_FPCLASS: { const DataLayout DLayout = DAG.getDataLayout(); EVT DestVT = TLI.getValueType(DLayout, VPIntrin.getType()); - auto Constant = cast(OpValues[1])->getZExtValue(); + auto Constant = OpValues[1]->getAsZExtVal(); SDValue Check = DAG.getTargetConstant(Constant, DL, MVT::i32); SDValue V = DAG.getNode(ISD::VP_IS_FPCLASS, DL, DestVT, {OpValues[0], Check, OpValues[2], OpValues[3]}); @@ -9175,8 +9173,7 @@ findMatchingInlineAsmOperand(unsigned OperandNo, unsigned CurOp = InlineAsm::Op_FirstOperand; for (; OperandNo; --OperandNo) { // Advance to the next operand. - unsigned OpFlag = - cast(AsmNodeOperands[CurOp])->getZExtValue(); + unsigned OpFlag = AsmNodeOperands[CurOp]->getAsZExtVal(); const InlineAsm::Flag F(OpFlag); assert( (F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isMemKind()) && @@ -9482,8 +9479,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call, // just use its register. auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(), AsmNodeOperands); - InlineAsm::Flag Flag( - cast(AsmNodeOperands[CurOp])->getZExtValue()); + InlineAsm::Flag Flag(AsmNodeOperands[CurOp]->getAsZExtVal()); if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) { if (OpInfo.isIndirect) { // This happens on gcc/testsuite/gcc.dg/pr8788-1.c @@ -9987,14 +9983,14 @@ void SelectionDAGBuilder::visitStackmap(const CallInst &CI) { // constant nodes. SDValue ID = getValue(CI.getArgOperand(0)); assert(ID.getValueType() == MVT::i64); - SDValue IDConst = DAG.getTargetConstant( - cast(ID)->getZExtValue(), DL, ID.getValueType()); + SDValue IDConst = + DAG.getTargetConstant(ID->getAsZExtVal(), DL, ID.getValueType()); Ops.push_back(IDConst); SDValue Shad = getValue(CI.getArgOperand(1)); assert(Shad.getValueType() == MVT::i32); - SDValue ShadConst = DAG.getTargetConstant( - cast(Shad)->getZExtValue(), DL, Shad.getValueType()); + SDValue ShadConst = + DAG.getTargetConstant(Shad->getAsZExtVal(), DL, Shad.getValueType()); Ops.push_back(ShadConst); // Add the live variables. @@ -10043,7 +10039,7 @@ void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB, // Get the real number of arguments participating in the call SDValue NArgVal = getValue(CB.getArgOperand(PatchPointOpers::NArgPos)); - unsigned NumArgs = cast(NArgVal)->getZExtValue(); + unsigned NumArgs = NArgVal->getAsZExtVal(); // Skip the four meta args: , , , // Intrinsics include all meta-operands up to but not including CC. @@ -10090,12 +10086,9 @@ void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB, // Add the and constants. SDValue IDVal = getValue(CB.getArgOperand(PatchPointOpers::IDPos)); - Ops.push_back(DAG.getTargetConstant( - cast(IDVal)->getZExtValue(), dl, MVT::i64)); + Ops.push_back(DAG.getTargetConstant(IDVal->getAsZExtVal(), dl, MVT::i64)); SDValue NBytesVal = getValue(CB.getArgOperand(PatchPointOpers::NBytesPos)); - Ops.push_back(DAG.getTargetConstant( - cast(NBytesVal)->getZExtValue(), dl, - MVT::i32)); + Ops.push_back(DAG.getTargetConstant(NBytesVal->getAsZExtVal(), dl, MVT::i32)); // Add the callee. Ops.push_back(Callee); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 4ae30000015e..9ebef642e423 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -149,7 +149,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::INTRINSIC_VOID: case ISD::INTRINSIC_W_CHAIN: { unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1; - unsigned IID = cast(getOperand(OpNo))->getZExtValue(); + unsigned IID = getOperand(OpNo)->getAsZExtVal(); if (IID < Intrinsic::num_intrinsics) return Intrinsic::getBaseName((Intrinsic::ID)IID).str(); if (!G) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 99bb3d875d4f..9acfc76d7d5e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2125,7 +2125,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops, --e; // Don't process a glue operand if it is here. while (i != e) { - InlineAsm::Flag Flags(cast(InOps[i])->getZExtValue()); + InlineAsm::Flag Flags(InOps[i]->getAsZExtVal()); if (!Flags.isMemKind() && !Flags.isFuncKind()) { // Just skip over this operand, copying the operands verbatim. Ops.insert(Ops.end(), InOps.begin() + i, @@ -2139,12 +2139,10 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops, if (Flags.isUseOperandTiedToDef(TiedToOperand)) { // We need the constraint ID from the operand this is tied to. unsigned CurOp = InlineAsm::Op_FirstOperand; - Flags = - InlineAsm::Flag(cast(InOps[CurOp])->getZExtValue()); + Flags = InlineAsm::Flag(InOps[CurOp]->getAsZExtVal()); for (; TiedToOperand; --TiedToOperand) { CurOp += Flags.getNumOperandRegisters() + 1; - Flags = InlineAsm::Flag( - cast(InOps[CurOp])->getZExtValue()); + Flags = InlineAsm::Flag(InOps[CurOp]->getAsZExtVal()); } } @@ -2384,9 +2382,8 @@ void SelectionDAGISel::pushStackMapLiveVariable(SmallVectorImpl &Ops, if (OpNode->getOpcode() == ISD::Constant) { Ops.push_back( CurDAG->getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64)); - Ops.push_back( - CurDAG->getTargetConstant(cast(OpNode)->getZExtValue(), - DL, OpVal.getValueType())); + Ops.push_back(CurDAG->getTargetConstant(OpNode->getAsZExtVal(), DL, + OpVal.getValueType())); } else { Ops.push_back(OpVal); } @@ -2456,7 +2453,7 @@ void SelectionDAGISel::Select_PATCHPOINT(SDNode *N) { Ops.push_back(*It++); // Push the args for the call. - for (uint64_t I = cast(NumArgs)->getZExtValue(); I != 0; I--) + for (uint64_t I = NumArgs->getAsZExtVal(); I != 0; I--) Ops.push_back(*It++); // Now push the live variables. diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 476d99c2a7e0..edc8cc7d4d1e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -580,7 +580,7 @@ bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val, if (!isa(N.getNode())) return false; - uint64_t Immed = cast(N.getNode())->getZExtValue(); + uint64_t Immed = N.getNode()->getAsZExtVal(); unsigned ShiftAmt; if (Immed >> 12 == 0) { @@ -611,7 +611,7 @@ bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val, return false; // The immediate operand must be a 24-bit zero-extended immediate. - uint64_t Immed = cast(N.getNode())->getZExtValue(); + uint64_t Immed = N.getNode()->getAsZExtVal(); // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0" // have the opposite effect on the C flag, so this pattern mustn't match under @@ -1326,7 +1326,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size, // MOV X0, WideImmediate // LDR X2, [BaseReg, X0] if (isa(RHS)) { - int64_t ImmOff = (int64_t)cast(RHS)->getZExtValue(); + int64_t ImmOff = (int64_t)RHS->getAsZExtVal(); // Skip the immediate can be selected by load/store addressing mode. // Also skip the immediate can be encoded by a single ADD (SUB is also // checked by using -ImmOff). diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 3583b7d2ce4e..47e665176e8b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -3588,8 +3588,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, // cmp w13, w12 // can be turned into: // cmp w12, w11, lsl #1 - if (!isa(RHS) || - !isLegalArithImmed(cast(RHS)->getZExtValue())) { + if (!isa(RHS) || !isLegalArithImmed(RHS->getAsZExtVal())) { SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS; if (getCmpOperandFoldingProfit(TheLHS) > getCmpOperandFoldingProfit(RHS)) { @@ -3623,7 +3622,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, cast(LHS)->getExtensionType() == ISD::ZEXTLOAD && cast(LHS)->getMemoryVT() == MVT::i16 && LHS.getNode()->hasNUsesOfValue(1, 0)) { - int16_t ValueofRHS = cast(RHS)->getZExtValue(); + int16_t ValueofRHS = RHS->getAsZExtVal(); if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) { SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS, @@ -5619,7 +5618,7 @@ SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op, // SVE supports an index scaled by sizeof(MemVT.elt) only, everything else // must be calculated before hand. - uint64_t ScaleVal = cast(Scale)->getZExtValue(); + uint64_t ScaleVal = Scale->getAsZExtVal(); if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) { assert(isPowerOf2_64(ScaleVal) && "Expecting power-of-two types"); EVT IndexVT = Index.getValueType(); @@ -5707,7 +5706,7 @@ SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op, // SVE supports an index scaled by sizeof(MemVT.elt) only, everything else // must be calculated before hand. - uint64_t ScaleVal = cast(Scale)->getZExtValue(); + uint64_t ScaleVal = Scale->getAsZExtVal(); if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) { assert(isPowerOf2_64(ScaleVal) && "Expecting power-of-two types"); EVT IndexVT = Index.getValueType(); @@ -22011,7 +22010,7 @@ static SDValue performBRCONDCombine(SDNode *N, SDValue Cmp = N->getOperand(3); assert(isa(CCVal) && "Expected a ConstantSDNode here!"); - unsigned CC = cast(CCVal)->getZExtValue(); + unsigned CC = CCVal->getAsZExtVal(); if (CC != AArch64CC::EQ && CC != AArch64CC::NE) return SDValue(); diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp index 1a76f354589e..9e43f206efcf 100644 --- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp @@ -172,7 +172,7 @@ static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl, SDValue AArch64SelectionDAGInfo::EmitTargetCodeForSetTag( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr, SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const { - uint64_t ObjSize = cast(Size)->getZExtValue(); + uint64_t ObjSize = Size->getAsZExtVal(); assert(ObjSize % 16 == 0); MachineFunction &MF = DAG.getMachineFunction(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 18f434be3cd3..719ae2e8750c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -373,7 +373,7 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N, Subtarget->getRegisterInfo()->getRegClass(RCID); SDValue SubRegOp = N->getOperand(OpNo + 1); - unsigned SubRegIdx = cast(SubRegOp)->getZExtValue(); + unsigned SubRegIdx = SubRegOp->getAsZExtVal(); return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx); } diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 9a2fb0bc37b2..674fd04f2fc1 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1651,7 +1651,7 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap); for (unsigned i = 0; i < 4; i++) { - unsigned Idx = cast(Swz[i])->getZExtValue(); + unsigned Idx = Swz[i]->getAsZExtVal(); if (SwizzleRemap.contains(Idx)) Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); } @@ -1659,7 +1659,7 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SwizzleRemap.clear(); BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap); for (unsigned i = 0; i < 4; i++) { - unsigned Idx = cast(Swz[i])->getZExtValue(); + unsigned Idx = Swz[i]->getAsZExtVal(); if (SwizzleRemap.contains(Idx)) Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); } @@ -1780,7 +1780,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, // Check that we know which element is being inserted if (!isa(EltNo)) return SDValue(); - unsigned Elt = cast(EltNo)->getZExtValue(); + unsigned Elt = EltNo->getAsZExtVal(); // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially // be converted to a BUILD_VECTOR). Fill in the Ops vector with the @@ -2021,7 +2021,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, } case R600::MOV_IMM_GLOBAL_ADDR: // Check if the Imm slot is used. Taken from below. - if (cast(Imm)->getZExtValue()) + if (Imm->getAsZExtVal()) return false; Imm = Src.getOperand(0); Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 975178b313ae..6ddc7e864fb2 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -6638,7 +6638,7 @@ SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op, EVT InsVT = Ins.getValueType(); EVT EltVT = VecVT.getVectorElementType(); unsigned InsNumElts = InsVT.getVectorNumElements(); - unsigned IdxVal = cast(Idx)->getZExtValue(); + unsigned IdxVal = Idx->getAsZExtVal(); SDLoc SL(Op); if (EltVT.getScalarSizeInBits() == 16 && IdxVal % 2 == 0) { @@ -7668,7 +7668,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op, Ops.push_back(IsA16 ? True : False); if (!Subtarget->hasGFX90AInsts()) { Ops.push_back(TFE); //tfe - } else if (cast(TFE)->getZExtValue()) { + } else if (TFE->getAsZExtVal()) { report_fatal_error("TFE is not supported on this GPU"); } if (!IsGFX12Plus || BaseOpcode->Sampler || BaseOpcode->MSAA) @@ -7805,7 +7805,7 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, setBufferOffsets(Offset, DAG, &Ops[3], NumLoads > 1 ? Align(16 * NumLoads) : Align(4)); - uint64_t InstOffset = cast(Ops[5])->getZExtValue(); + uint64_t InstOffset = Ops[5]->getAsZExtVal(); for (unsigned i = 0; i < NumLoads; ++i) { Ops[5] = DAG.getTargetConstant(InstOffset + 16 * i, DL, MVT::i32); Loads.push_back(getMemIntrinsicNode(AMDGPUISD::BUFFER_LOAD, DL, VTList, Ops, diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index d4c7a457e9aa..fee900b3efb2 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -338,8 +338,8 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, if (!isa(Off0) || !isa(Off1)) return false; - Offset0 = cast(Off0)->getZExtValue(); - Offset1 = cast(Off1)->getZExtValue(); + Offset0 = Off0->getAsZExtVal(); + Offset1 = Off1->getAsZExtVal(); return true; } diff --git a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp index 28e35f8f2a54..17c2d7bb13b4 100644 --- a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp @@ -170,7 +170,7 @@ bool ARCDAGToDAGISel::SelectFrameADDR_ri(SDValue Addr, SDValue &Base, void ARCDAGToDAGISel::Select(SDNode *N) { switch (N->getOpcode()) { case ISD::Constant: { - uint64_t CVal = cast(N)->getZExtValue(); + uint64_t CVal = N->getAsZExtVal(); ReplaceNode(N, CurDAG->getMachineNode( isInt<12>(CVal) ? ARC::MOV_rs12 : ARC::MOV_rlimm, SDLoc(N), MVT::i32, diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index adc429b61bbc..e99ee299412a 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -372,7 +372,7 @@ INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { - Imm = cast(N)->getZExtValue(); + Imm = N->getAsZExtVal(); return true; } return false; @@ -1101,8 +1101,7 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N, if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) { Offset = N.getOperand(0); SDValue N1 = N.getOperand(1); - Label = CurDAG->getTargetConstant(cast(N1)->getZExtValue(), - SDLoc(N), MVT::i32); + Label = CurDAG->getTargetConstant(N1->getAsZExtVal(), SDLoc(N), MVT::i32); return true; } @@ -1942,7 +1941,7 @@ SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, const SDLoc &dl, if (!is64BitVector && NumVecs < 3) NumRegs *= 2; - unsigned Alignment = cast(Align)->getZExtValue(); + unsigned Alignment = Align->getAsZExtVal(); if (Alignment >= 32 && NumRegs == 4) Alignment = 32; else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4)) @@ -2428,7 +2427,7 @@ void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, unsigned Alignment = 0; if (NumVecs != 3) { - Alignment = cast(Align)->getZExtValue(); + Alignment = Align->getAsZExtVal(); unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8; if (Alignment > NumBytes) Alignment = NumBytes; @@ -2871,7 +2870,7 @@ void ARMDAGToDAGISel::SelectMVE_VxDUP(SDNode *N, const uint16_t *Opcodes, Ops.push_back(N->getOperand(OpIdx++)); // limit SDValue ImmOp = N->getOperand(OpIdx++); // step - int ImmValue = cast(ImmOp)->getZExtValue(); + int ImmValue = ImmOp->getAsZExtVal(); Ops.push_back(getI32Imm(ImmValue, Loc)); if (Predicated) @@ -2892,7 +2891,7 @@ void ARMDAGToDAGISel::SelectCDE_CXxD(SDNode *N, uint16_t Opcode, // Convert and append the immediate operand designating the coprocessor. SDValue ImmCorpoc = N->getOperand(OpIdx++); - uint32_t ImmCoprocVal = cast(ImmCorpoc)->getZExtValue(); + uint32_t ImmCoprocVal = ImmCorpoc->getAsZExtVal(); Ops.push_back(getI32Imm(ImmCoprocVal, Loc)); // For accumulating variants copy the low and high order parts of the @@ -2911,7 +2910,7 @@ void ARMDAGToDAGISel::SelectCDE_CXxD(SDNode *N, uint16_t Opcode, // Convert and append the immediate operand SDValue Imm = N->getOperand(OpIdx); - uint32_t ImmVal = cast(Imm)->getZExtValue(); + uint32_t ImmVal = Imm->getAsZExtVal(); Ops.push_back(getI32Imm(ImmVal, Loc)); // Accumulating variants are IT-predicable, add predicate operands. @@ -2965,7 +2964,7 @@ void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool IsIntrinsic, unsigned Alignment = 0; if (NumVecs != 3) { - Alignment = cast(Align)->getZExtValue(); + Alignment = Align->getAsZExtVal(); unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8; if (Alignment > NumBytes) Alignment = NumBytes; @@ -3697,7 +3696,7 @@ void ARMDAGToDAGISel::Select(SDNode *N) { // Other cases are autogenerated. break; case ISD::Constant: { - unsigned Val = cast(N)->getZExtValue(); + unsigned Val = N->getAsZExtVal(); // If we can't materialize the constant we need to use a literal pool if (ConstantMaterializationCost(Val, Subtarget) > 2 && !Subtarget->genExecuteOnly()) { @@ -4132,7 +4131,7 @@ void ARMDAGToDAGISel::Select(SDNode *N) { assert(N2.getOpcode() == ISD::Constant); assert(N3.getOpcode() == ISD::Register); - unsigned CC = (unsigned) cast(N2)->getZExtValue(); + unsigned CC = (unsigned)N2->getAsZExtVal(); if (InGlue.getOpcode() == ARMISD::CMPZ) { if (InGlue.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN) { @@ -4243,8 +4242,7 @@ void ARMDAGToDAGISel::Select(SDNode *N) { if (SwitchEQNEToPLMI) { SDValue ARMcc = N->getOperand(2); - ARMCC::CondCodes CC = - (ARMCC::CondCodes)cast(ARMcc)->getZExtValue(); + ARMCC::CondCodes CC = (ARMCC::CondCodes)ARMcc->getAsZExtVal(); switch (CC) { default: llvm_unreachable("CMPZ must be either NE or EQ!"); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 9f3bcffc7a99..568085bd0ab3 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4820,8 +4820,7 @@ SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, // some tweaks to the heuristics for the previous and->shift transform. // FIXME: Optimize cases where the LHS isn't a shift. if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL && - isa(RHS) && - cast(RHS)->getZExtValue() == 0x80000000U && + isa(RHS) && RHS->getAsZExtVal() == 0x80000000U && CC == ISD::SETUGT && isa(LHS.getOperand(1)) && LHS.getConstantOperandVal(1) < 31) { unsigned ShiftAmt = LHS.getConstantOperandVal(1) + 1; @@ -5533,7 +5532,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); // Choose GE over PL, which vsel does now support - if (cast(ARMcc)->getZExtValue() == ARMCC::PL) + if (ARMcc->getAsZExtVal() == ARMCC::PL) ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32); return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG); } @@ -7749,7 +7748,7 @@ static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, uint64_t Val; if (!isa(N)) return SDValue(); - Val = cast(N)->getZExtValue(); + Val = N->getAsZExtVal(); if (ST->isThumb1Only()) { if (Val <= 255 || ~Val <= 255) @@ -7804,7 +7803,7 @@ static SDValue LowerBUILD_VECTOR_i1(SDValue Op, SelectionDAG &DAG, SDValue V = Op.getOperand(i); if (!isa(V) && !V.isUndef()) continue; - bool BitSet = V.isUndef() ? false : cast(V)->getZExtValue(); + bool BitSet = V.isUndef() ? false : V->getAsZExtVal(); if (BitSet) Bits32 |= BoolMask << (i * BitsPerBool); } @@ -9240,7 +9239,7 @@ static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG, EVT VT = Op.getValueType(); EVT Op1VT = V1.getValueType(); unsigned NumElts = VT.getVectorNumElements(); - unsigned Index = cast(V2)->getZExtValue(); + unsigned Index = V2->getAsZExtVal(); assert(VT.getScalarSizeInBits() == 1 && "Unexpected custom EXTRACT_SUBVECTOR lowering"); @@ -14618,7 +14617,7 @@ static SDValue PerformORCombineToBFI(SDNode *N, // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask // where lsb(mask) == #shamt and masked bits of B are known zero. SDValue ShAmt = N00.getOperand(1); - unsigned ShAmtC = cast(ShAmt)->getZExtValue(); + unsigned ShAmtC = ShAmt->getAsZExtVal(); unsigned LSB = llvm::countr_zero(Mask); if (ShAmtC != LSB) return SDValue(); @@ -18339,8 +18338,7 @@ ARMTargetLowering::PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const { SDValue Chain = N->getOperand(0); SDValue BB = N->getOperand(1); SDValue ARMcc = N->getOperand(2); - ARMCC::CondCodes CC = - (ARMCC::CondCodes)cast(ARMcc)->getZExtValue(); + ARMCC::CondCodes CC = (ARMCC::CondCodes)ARMcc->getAsZExtVal(); // (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0)) // -> (brcond Chain BB CC CPSR Cmp) @@ -18373,8 +18371,7 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { SDValue FalseVal = N->getOperand(0); SDValue TrueVal = N->getOperand(1); SDValue ARMcc = N->getOperand(2); - ARMCC::CondCodes CC = - (ARMCC::CondCodes)cast(ARMcc)->getZExtValue(); + ARMCC::CondCodes CC = (ARMCC::CondCodes)ARMcc->getAsZExtVal(); // BFI is only available on V6T2+. if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) { diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index d36bfb188ed3..f91e77adb8f8 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -660,7 +660,7 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, SDValue Cmp; if (LHS.getSimpleValueType() == MVT::i16 && isa(RHS)) { - uint64_t Imm = cast(RHS)->getZExtValue(); + uint64_t Imm = RHS->getAsZExtVal(); // Generate a CPI/CPC pair if RHS is a 16-bit constant. Use the zero // register for the constant RHS if its lower or higher byte is zero. SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, @@ -680,7 +680,7 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, } else if (RHS.getSimpleValueType() == MVT::i16 && isa(LHS)) { // Generate a CPI/CPC pair if LHS is a 16-bit constant. Use the zero // register for the constant LHS if its lower or higher byte is zero. - uint64_t Imm = cast(LHS)->getZExtValue(); + uint64_t Imm = LHS->getAsZExtVal(); SDValue LHSlo = (Imm & 0xff) == 0 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8) : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index eb5c59672224..defb1f7324f4 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -743,7 +743,7 @@ void HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) { // void HexagonDAGToDAGISel::SelectConstant(SDNode *N) { if (N->getValueType(0) == MVT::i1) { - assert(!(cast(N)->getZExtValue() >> 1)); + assert(!(N->getAsZExtVal() >> 1)); unsigned Opc = (cast(N)->getSExtValue() != 0) ? Hexagon::PS_true : Hexagon::PS_false; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 665e2d79c83d..81035849491b 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1256,7 +1256,7 @@ HexagonTargetLowering::extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const { MVT VecTy = ty(VecV); unsigned HwLen = Subtarget.getVectorLength(); - unsigned Idx = cast(IdxV.getNode())->getZExtValue(); + unsigned Idx = IdxV.getNode()->getAsZExtVal(); MVT ElemTy = VecTy.getVectorElementType(); unsigned ElemWidth = ElemTy.getSizeInBits(); @@ -1299,7 +1299,7 @@ HexagonTargetLowering::extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, MVT ByteTy = MVT::getVectorVT(MVT::i8, HwLen); SDValue ByteVec = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, VecV); // IdxV is required to be a constant. - unsigned Idx = cast(IdxV.getNode())->getZExtValue(); + unsigned Idx = IdxV.getNode()->getAsZExtVal(); unsigned ResLen = ResTy.getVectorNumElements(); unsigned BitBytes = HwLen / VecTy.getVectorNumElements(); @@ -1801,7 +1801,7 @@ HexagonTargetLowering::LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) MVT SrcTy = ty(SrcV); MVT DstTy = ty(Op); SDValue IdxV = Op.getOperand(1); - unsigned Idx = cast(IdxV.getNode())->getZExtValue(); + unsigned Idx = IdxV.getNode()->getAsZExtVal(); assert(Idx % DstTy.getVectorNumElements() == 0); (void)Idx; const SDLoc &dl(Op); diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 3e75b9fa5230..70f782b81270 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -525,8 +525,7 @@ LoongArchTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, if (isa(Idx) && (EltTy == MVT::i32 || EltTy == MVT::i64 || EltTy == MVT::f32 || - EltTy == MVT::f64 || - cast(Idx)->getZExtValue() < NumElts / 2)) + EltTy == MVT::f64 || Idx->getAsZExtVal() < NumElts / 2)) return Op; return SDValue(); @@ -1395,28 +1394,28 @@ SDValue LoongArchTargetLowering::lowerINTRINSIC_VOID(SDValue Op, if (IntrinsicEnum == Intrinsic::loongarch_cacop_w && Subtarget.is64Bit()) return emitIntrinsicErrorMessage(Op, ErrorMsgReqLA32, DAG); // call void @llvm.loongarch.cacop.[d/w](uimm5, rj, simm12) - unsigned Imm1 = cast(Op2)->getZExtValue(); + unsigned Imm1 = Op2->getAsZExtVal(); int Imm2 = cast(Op.getOperand(4))->getSExtValue(); if (!isUInt<5>(Imm1) || !isInt<12>(Imm2)) return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG); return Op; } case Intrinsic::loongarch_dbar: { - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); return !isUInt<15>(Imm) ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG) : DAG.getNode(LoongArchISD::DBAR, DL, MVT::Other, Chain, DAG.getConstant(Imm, DL, GRLenVT)); } case Intrinsic::loongarch_ibar: { - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); return !isUInt<15>(Imm) ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG) : DAG.getNode(LoongArchISD::IBAR, DL, MVT::Other, Chain, DAG.getConstant(Imm, DL, GRLenVT)); } case Intrinsic::loongarch_break: { - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); return !isUInt<15>(Imm) ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG) : DAG.getNode(LoongArchISD::BREAK, DL, MVT::Other, Chain, @@ -1425,7 +1424,7 @@ SDValue LoongArchTargetLowering::lowerINTRINSIC_VOID(SDValue Op, case Intrinsic::loongarch_movgr2fcsr: { if (!Subtarget.hasBasicF()) return emitIntrinsicErrorMessage(Op, ErrorMsgReqF, DAG); - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); return !isUInt<2>(Imm) ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG) : DAG.getNode(LoongArchISD::MOVGR2FCSR, DL, MVT::Other, Chain, @@ -1434,7 +1433,7 @@ SDValue LoongArchTargetLowering::lowerINTRINSIC_VOID(SDValue Op, Op.getOperand(3))); } case Intrinsic::loongarch_syscall: { - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); return !isUInt<15>(Imm) ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG) : DAG.getNode(LoongArchISD::SYSCALL, DL, MVT::Other, Chain, @@ -1937,7 +1936,7 @@ void LoongArchTargetLowering::ReplaceNodeResults( emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqF); return; } - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); if (!isUInt<2>(Imm)) { emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgOOR); return; @@ -1993,7 +1992,7 @@ void LoongArchTargetLowering::ReplaceNodeResults( CSR_CASE(iocsrrd_d); #undef CSR_CASE case Intrinsic::loongarch_csrrd_w: { - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); if (!isUInt<14>(Imm)) { emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgOOR); return; diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp index c4d7a0dec7f3..158393f02a24 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.cpp +++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -2375,7 +2375,7 @@ SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { // a >= b ? -1 : 0 -> RES = setcc_carry // a >= b ? 0 : -1 -> RES = ~setcc_carry if (Cond.getOpcode() == M68kISD::SUB) { - unsigned CondCode = cast(CC)->getZExtValue(); + unsigned CondCode = CC->getAsZExtVal(); if ((CondCode == M68k::COND_CC || CondCode == M68k::COND_CS) && (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) && @@ -2491,7 +2491,7 @@ SDValue M68kTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { Cond = Cmp; AddTest = false; } else { - switch (cast(CC)->getZExtValue()) { + switch (CC->getAsZExtVal()) { default: break; case M68k::COND_VS: diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 660861a5d521..efb23b1a4e3f 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -308,12 +308,12 @@ static bool isValidIndexedLoad(const LoadSDNode *LD) { switch (VT.getSimpleVT().SimpleTy) { case MVT::i8: - if (cast(LD->getOffset())->getZExtValue() != 1) + if (LD->getOffset()->getAsZExtVal() != 1) return false; break; case MVT::i16: - if (cast(LD->getOffset())->getZExtValue() != 2) + if (LD->getOffset()->getAsZExtVal() != 2) return false; break; diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index 1ed19f9381ec..e68904863cfc 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -1169,8 +1169,8 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { bool Invert = false; bool Shift = false; bool Convert = true; - switch (cast(TargetCC)->getZExtValue()) { - default: + switch (TargetCC->getAsZExtVal()) { + default: Convert = false; break; case MSP430CC::COND_HS: @@ -1194,7 +1194,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however, // Res = (SR >> 1) & 1 is 1 word shorter. break; - } + } EVT VT = Op.getValueType(); SDValue One = DAG.getConstant(1, dl, VT); if (Convert) { diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 483eba4e4f47..d431d3d91494 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2042,8 +2042,7 @@ SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { return Op; SDValue CCNode = CondRes.getOperand(2); - Mips::CondCode CC = - (Mips::CondCode)cast(CCNode)->getZExtValue(); + Mips::CondCode CC = (Mips::CondCode)CCNode->getAsZExtVal(); unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 0ed87ee0809a..c0e978018919 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -76,7 +76,7 @@ void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, } unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { - uint64_t RegNum = cast(RegIdx)->getZExtValue(); + uint64_t RegNum = RegIdx->getAsZExtVal(); return Mips::MSACtrlRegClass.getRegister(RegNum); } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index 815c46edb6fa..7abe984b34e1 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -2076,7 +2076,7 @@ bool NVPTXDAGToDAGISel::tryLoadParam(SDNode *Node) { VTs = CurDAG->getVTList(EVTs); } - unsigned OffsetVal = cast(Offset)->getZExtValue(); + unsigned OffsetVal = Offset->getAsZExtVal(); SmallVector Ops; Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32)); @@ -2091,7 +2091,7 @@ bool NVPTXDAGToDAGISel::tryStoreRetval(SDNode *N) { SDLoc DL(N); SDValue Chain = N->getOperand(0); SDValue Offset = N->getOperand(1); - unsigned OffsetVal = cast(Offset)->getZExtValue(); + unsigned OffsetVal = Offset->getAsZExtVal(); MemSDNode *Mem = cast(N); // How many elements do we have? @@ -2158,9 +2158,9 @@ bool NVPTXDAGToDAGISel::tryStoreParam(SDNode *N) { SDLoc DL(N); SDValue Chain = N->getOperand(0); SDValue Param = N->getOperand(1); - unsigned ParamVal = cast(Param)->getZExtValue(); + unsigned ParamVal = Param->getAsZExtVal(); SDValue Offset = N->getOperand(2); - unsigned OffsetVal = cast(Offset)->getZExtValue(); + unsigned OffsetVal = Offset->getAsZExtVal(); MemSDNode *Mem = cast(N); SDValue Glue = N->getOperand(N->getNumOperands() - 1); diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index de6de3214521..c65090d915ef 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -5812,7 +5812,7 @@ static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG, SDLoc DL(N); // Get the intrinsic ID - unsigned IntrinNo = cast(Intrin.getNode())->getZExtValue(); + unsigned IntrinNo = Intrin.getNode()->getAsZExtVal(); switch (IntrinNo) { default: return; diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index ed96339240d9..26ed74108ec3 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -565,7 +565,7 @@ static bool hasTocDataAttr(SDValue Val, unsigned PointerSize) { /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { - Imm = cast(N)->getZExtValue(); + Imm = N->getAsZExtVal(); return true; } return false; @@ -575,7 +575,7 @@ static bool isInt32Immediate(SDNode *N, unsigned &Imm) { /// operand. If so Imm will receive the 64-bit value. static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { - Imm = cast(N)->getZExtValue(); + Imm = N->getAsZExtVal(); return true; } return false; @@ -1500,7 +1500,7 @@ static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) { SDLoc dl(N); // Get 64 bit value. - int64_t Imm = cast(N)->getZExtValue(); + int64_t Imm = N->getAsZExtVal(); if (unsigned MinSize = allUsesTruncate(CurDAG, N)) { uint64_t SextImm = SignExtend64(Imm, MinSize); SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64); @@ -4923,7 +4923,7 @@ bool PPCDAGToDAGISel::trySelectLoopCountIntrinsic(SDNode *N) { SDNode *NewDecrement = CurDAG->getMachineNode(DecrementOpcode, DecrementLoc, MVT::i1, DecrementOps); - unsigned Val = cast(RHS)->getZExtValue(); + unsigned Val = RHS->getAsZExtVal(); bool IsBranchOnTrue = (CC == ISD::SETEQ && Val) || (CC == ISD::SETNE && !Val); unsigned Opcode = IsBranchOnTrue ? PPC::BC : PPC::BCn; @@ -5765,7 +5765,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) { break; // If the multiplier fits int16, we can handle it with mulli. - int64_t Imm = cast(Op1)->getZExtValue(); + int64_t Imm = Op1->getAsZExtVal(); unsigned Shift = llvm::countr_zero(Imm); if (isInt<16>(Imm) || !Shift) break; @@ -6612,8 +6612,7 @@ void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) { // For us to materialize these using one instruction, we must be able to // represent them as signed 16-bit integers. - uint64_t True = cast(TrueRes)->getZExtValue(), - False = cast(FalseRes)->getZExtValue(); + uint64_t True = TrueRes->getAsZExtVal(), False = FalseRes->getAsZExtVal(); if (!isInt<16>(True) || !isInt<16>(False)) break; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 8f27e6677afa..235df1880b37 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2566,7 +2566,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { if (LeadingZero) { if (!UniquedVals[Multiple-1].getNode()) return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef - int Val = cast(UniquedVals[Multiple-1])->getZExtValue(); + int Val = UniquedVals[Multiple - 1]->getAsZExtVal(); if (Val < 16) // 0,0,0,4 -> vspltisw(4) return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); } @@ -2635,11 +2635,11 @@ bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) { if (!isa(N)) return false; - Imm = (int16_t)cast(N)->getZExtValue(); + Imm = (int16_t)N->getAsZExtVal(); if (N->getValueType(0) == MVT::i32) - return Imm == (int32_t)cast(N)->getZExtValue(); + return Imm == (int32_t)N->getAsZExtVal(); else - return Imm == (int64_t)cast(N)->getZExtValue(); + return Imm == (int64_t)N->getAsZExtVal(); } bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) { return isIntS16Immediate(Op.getNode(), Imm); @@ -2684,7 +2684,7 @@ bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) { if (!isa(N)) return false; - Imm = (int64_t)cast(N)->getZExtValue(); + Imm = (int64_t)N->getAsZExtVal(); return isInt<34>(Imm); } bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) { @@ -15580,7 +15580,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, NarrowOp.getOpcode() != ISD::ROTL && NarrowOp.getOpcode() != ISD::ROTR) break; - uint64_t Imm = cast(Op2)->getZExtValue(); + uint64_t Imm = Op2->getAsZExtVal(); // Make sure that the constant is narrow enough to fit in the narrow type. if (!isUInt<32>(Imm)) break; @@ -16795,7 +16795,7 @@ void PPCTargetLowering::CollectTargetIntrinsicOperands(const CallInst &I, return; if (!isa(Ops[1].getNode())) return; - auto IntrinsicID = cast(Ops[1].getNode())->getZExtValue(); + auto IntrinsicID = Ops[1].getNode()->getAsZExtVal(); if (IntrinsicID != Intrinsic::ppc_tdw && IntrinsicID != Intrinsic::ppc_tw && IntrinsicID != Intrinsic::ppc_trapd && IntrinsicID != Intrinsic::ppc_trap) return; @@ -18430,7 +18430,7 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent, if (Flags & PPC::MOF_RPlusSImm16) { SDValue Op0 = N.getOperand(0); SDValue Op1 = N.getOperand(1); - int16_t Imm = cast(Op1)->getZExtValue(); + int16_t Imm = Op1->getAsZExtVal(); if (!Align || isAligned(*Align, Imm)) { Disp = DAG.getTargetConstant(Imm, DL, N.getValueType()); Base = Op0; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a5b33e8e293a..0a1a466af591 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -3497,7 +3497,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG, for (unsigned I = 0; I < NumElts;) { SDValue V = Op.getOperand(I); - bool BitValue = !V.isUndef() && cast(V)->getZExtValue(); + bool BitValue = !V.isUndef() && V->getAsZExtVal(); Bits |= ((uint64_t)BitValue << BitPos); ++BitPos; ++I; @@ -3628,8 +3628,8 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG, for (const auto &OpIdx : enumerate(Op->op_values())) { const auto &SeqV = OpIdx.value(); if (!SeqV.isUndef()) - SplatValue |= ((cast(SeqV)->getZExtValue() & EltMask) - << (OpIdx.index() * EltBitSize)); + SplatValue |= + ((SeqV->getAsZExtVal() & EltMask) << (OpIdx.index() * EltBitSize)); } // On RV64, sign-extend from 32 to 64 bits where possible in order to @@ -3684,8 +3684,8 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG, // vector type. for (const auto &SeqV : Sequence) { if (!SeqV.isUndef()) - SplatValue |= ((cast(SeqV)->getZExtValue() & EltMask) - << (EltIdx * EltBitSize)); + SplatValue |= + ((SeqV->getAsZExtVal() & EltMask) << (EltIdx * EltBitSize)); EltIdx++; } @@ -3946,8 +3946,7 @@ static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Passthru, (isa(VL) && cast(VL)->getReg() == RISCV::X0)) NewVL = DAG.getRegister(RISCV::X0, MVT::i32); - else if (isa(VL) && - isUInt<4>(cast(VL)->getZExtValue())) + else if (isa(VL) && isUInt<4>(VL->getAsZExtVal())) NewVL = DAG.getNode(ISD::ADD, DL, VL.getValueType(), VL, VL); if (NewVL) { @@ -7916,8 +7915,7 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, // Use tail agnostic policy if Idx is the last index of Vec. unsigned Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED; if (VecVT.isFixedLengthVector() && isa(Idx) && - cast(Idx)->getZExtValue() + 1 == - VecVT.getVectorNumElements()) + Idx->getAsZExtVal() + 1 == VecVT.getVectorNumElements()) Policy = RISCVII::TAIL_AGNOSTIC; SDValue Slideup = getVSlideup(DAG, Subtarget, DL, ContainerVT, Vec, ValInVec, Idx, Mask, InsertVL, Policy); @@ -8177,7 +8175,7 @@ static SDValue lowerVectorIntrinsicScalars(SDValue Op, SelectionDAG &DAG, const auto [MinVLMAX, MaxVLMAX] = RISCVTargetLowering::computeVLMAXBounds(VT, Subtarget); - uint64_t AVLInt = cast(AVL)->getZExtValue(); + uint64_t AVLInt = AVL->getAsZExtVal(); if (AVLInt <= MinVLMAX) { I32VL = DAG.getConstant(2 * AVLInt, DL, XLenVT); } else if (AVLInt >= 2 * MaxVLMAX) { @@ -8243,8 +8241,7 @@ static SDValue lowerVectorIntrinsicScalars(SDValue Op, SelectionDAG &DAG, SDValue Mask = Operands[NumOps - 3]; SDValue MaskedOff = Operands[1]; // Assume Policy operand is the last operand. - uint64_t Policy = - cast(Operands[NumOps - 1])->getZExtValue(); + uint64_t Policy = Operands[NumOps - 1]->getAsZExtVal(); // We don't need to select maskedoff if it's undef. if (MaskedOff.isUndef()) return Vec; diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index c7d8591c5bdf..320f91c76057 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -1641,7 +1641,7 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) { // If this is a 64-bit constant that is out of the range of LLILF, // LLIHF and LGFI, split it into two 32-bit pieces. if (Node->getValueType(0) == MVT::i64) { - uint64_t Val = cast(Node)->getZExtValue(); + uint64_t Val = Node->getAsZExtVal(); if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) { splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val), uint32_t(Val)); @@ -1677,10 +1677,8 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) { isInt<16>(cast(Op0)->getSExtValue())))) { SDValue CCValid = Node->getOperand(2); SDValue CCMask = Node->getOperand(3); - uint64_t ConstCCValid = - cast(CCValid.getNode())->getZExtValue(); - uint64_t ConstCCMask = - cast(CCMask.getNode())->getZExtValue(); + uint64_t ConstCCValid = CCValid.getNode()->getAsZExtVal(); + uint64_t ConstCCMask = CCMask.getNode()->getAsZExtVal(); // Invert the condition. CCMask = CurDAG->getTargetConstant(ConstCCValid ^ ConstCCMask, SDLoc(Node), CCMask.getValueType()); diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 045c4c0aac07..2450c6801a66 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -2662,10 +2662,8 @@ static void adjustForFNeg(Comparison &C) { // with (sext (trunc X)) into a comparison with (shl X, 32). static void adjustForLTGFR(Comparison &C) { // Check for a comparison between (shl X, 32) and 0. - if (C.Op0.getOpcode() == ISD::SHL && - C.Op0.getValueType() == MVT::i64 && - C.Op1.getOpcode() == ISD::Constant && - cast(C.Op1)->getZExtValue() == 0) { + if (C.Op0.getOpcode() == ISD::SHL && C.Op0.getValueType() == MVT::i64 && + C.Op1.getOpcode() == ISD::Constant && C.Op1->getAsZExtVal() == 0) { auto *C1 = dyn_cast(C.Op0.getOperand(1)); if (C1 && C1->getZExtValue() == 32) { SDValue ShlOp0 = C.Op0.getOperand(0); @@ -2690,7 +2688,7 @@ static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL, C.Op0.getOperand(0).getOpcode() == ISD::LOAD && C.Op1.getOpcode() == ISD::Constant && cast(C.Op1)->getValueSizeInBits(0) <= 64 && - cast(C.Op1)->getZExtValue() == 0) { + C.Op1->getAsZExtVal() == 0) { auto *L = cast(C.Op0.getOperand(0)); if (L->getMemoryVT().getStoreSizeInBits().getFixedValue() <= C.Op0.getValueSizeInBits().getFixedValue()) { @@ -3035,12 +3033,12 @@ static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) && isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid)) return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, - cast(CmpOp1)->getZExtValue(), Cond); + CmpOp1->getAsZExtVal(), Cond); if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN && CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 && isIntrinsicWithCC(CmpOp0, Opcode, CCValid)) return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, - cast(CmpOp1)->getZExtValue(), Cond); + CmpOp1->getAsZExtVal(), Cond); } Comparison C(CmpOp0, CmpOp1, Chain); C.CCMask = CCMaskForCondCode(Cond); @@ -3457,12 +3455,11 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op, // Check for absolute and negative-absolute selections, including those // where the comparison value is sign-extended (for LPGFR and LNGFR). // This check supplements the one in DAGCombiner. - if (C.Opcode == SystemZISD::ICMP && - C.CCMask != SystemZ::CCMASK_CMP_EQ && + if (C.Opcode == SystemZISD::ICMP && C.CCMask != SystemZ::CCMASK_CMP_EQ && C.CCMask != SystemZ::CCMASK_CMP_NE && C.Op1.getOpcode() == ISD::Constant && cast(C.Op1)->getValueSizeInBits(0) <= 64 && - cast(C.Op1)->getZExtValue() == 0) { + C.Op1->getAsZExtVal() == 0) { if (isAbsolute(C.Op0, TrueOp, FalseOp)) return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT); if (isAbsolute(C.Op0, FalseOp, TrueOp)) @@ -3947,8 +3944,7 @@ SystemZTargetLowering::lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, // If user has set the no alignment function attribute, ignore // alloca alignments. - uint64_t AlignVal = - (RealignOpt ? cast(Align)->getZExtValue() : 0); + uint64_t AlignVal = (RealignOpt ? Align->getAsZExtVal() : 0); uint64_t StackAlign = TFI->getStackAlignment(); uint64_t RequiredAlign = std::max(AlignVal, StackAlign); @@ -4013,8 +4009,7 @@ SystemZTargetLowering::lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, // If user has set the no alignment function attribute, ignore // alloca alignments. - uint64_t AlignVal = - (RealignOpt ? cast(Align)->getZExtValue() : 0); + uint64_t AlignVal = (RealignOpt ? Align->getAsZExtVal() : 0); uint64_t StackAlign = TFI->getStackAlignment(); uint64_t RequiredAlign = std::max(AlignVal, StackAlign); @@ -4213,7 +4208,7 @@ SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const { // If the low part is a constant that is outside the range of LHI, // then we're better off using IILF. if (LowOp.getOpcode() == ISD::Constant) { - int64_t Value = int32_t(cast(LowOp)->getZExtValue()); + int64_t Value = int32_t(LowOp->getAsZExtVal()); if (!isInt<16>(Value)) return Op; } @@ -5897,7 +5892,7 @@ SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, Op1.getOpcode() != ISD::BITCAST && Op1.getOpcode() != ISD::ConstantFP && Op2.getOpcode() == ISD::Constant) { - uint64_t Index = cast(Op2)->getZExtValue(); + uint64_t Index = Op2->getAsZExtVal(); unsigned Mask = VT.getVectorNumElements() - 1; if (Index <= Mask) return Op; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 4bcf89690505..7c47790d1e35 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -1869,8 +1869,7 @@ SDValue WebAssemblyTargetLowering::LowerIntrinsic(SDValue Op, Ops[OpIdx++] = Op.getOperand(2); while (OpIdx < 18) { const SDValue &MaskIdx = Op.getOperand(OpIdx + 1); - if (MaskIdx.isUndef() || - cast(MaskIdx.getNode())->getZExtValue() >= 32) { + if (MaskIdx.isUndef() || MaskIdx.getNode()->getAsZExtVal() >= 32) { bool isTarget = MaskIdx.getNode()->getOpcode() == ISD::TargetConstant; Ops[OpIdx++] = DAG.getConstant(0, DL, MVT::i32, isTarget); } else { @@ -1912,7 +1911,7 @@ WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, const SDNode *Index = Extract.getOperand(1).getNode(); if (!isa(Index)) return SDValue(); - unsigned IndexVal = cast(Index)->getZExtValue(); + unsigned IndexVal = Index->getAsZExtVal(); unsigned Scale = ExtractedVecT.getVectorNumElements() / VecT.getVectorNumElements(); assert(Scale > 1); @@ -2335,7 +2334,7 @@ WebAssemblyTargetLowering::LowerAccessVectorElement(SDValue Op, SDNode *IdxNode = Op.getOperand(Op.getNumOperands() - 1).getNode(); if (isa(IdxNode)) { // Ensure the index type is i32 to match the tablegen patterns - uint64_t Idx = cast(IdxNode)->getZExtValue(); + uint64_t Idx = IdxNode->getAsZExtVal(); SmallVector Ops(Op.getNode()->ops()); Ops[Op.getNumOperands() - 1] = DAG.getConstant(Idx, SDLoc(IdxNode), MVT::i32); diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 73b10cf3067e..53ce720be2da 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -2852,7 +2852,7 @@ bool X86DAGToDAGISel::selectVectorAddr(MemSDNode *Parent, SDValue BasePtr, SDValue &Index, SDValue &Disp, SDValue &Segment) { X86ISelAddressMode AM; - AM.Scale = cast(ScaleOp)->getZExtValue(); + AM.Scale = ScaleOp->getAsZExtVal(); // Attempt to match index patterns, as long as we're not relying on implicit // sign-extension, which is performed BEFORE scale. diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c14e03197aae..5a28240ea9e2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7371,7 +7371,7 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp, /// index. static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec, SDValue ExtIdx) { - int Idx = cast(ExtIdx)->getZExtValue(); + int Idx = ExtIdx->getAsZExtVal(); if (!isa(ExtractedFromVec)) return Idx; @@ -8795,7 +8795,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); MachinePointerInfo MPI = MachinePointerInfo::getConstantPool(MF); SDValue Ld = DAG.getLoad(VT, dl, DAG.getEntryNode(), LegalDAGConstVec, MPI); - unsigned InsertC = cast(InsIndex)->getZExtValue(); + unsigned InsertC = InsIndex->getAsZExtVal(); unsigned NumEltsInLow128Bits = 128 / VT.getScalarSizeInBits(); if (InsertC < NumEltsInLow128Bits) return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ld, VarElt, InsIndex); @@ -17756,7 +17756,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, DAG.getBitcast(MVT::v4i32, Vec), Idx)); - unsigned IdxVal = cast(Idx)->getZExtValue(); + unsigned IdxVal = Idx->getAsZExtVal(); SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, Vec, DAG.getTargetConstant(IdxVal, dl, MVT::i8)); return DAG.getNode(ISD::TRUNCATE, dl, VT, Extract); @@ -24069,7 +24069,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { // a >= b ? -1 : 0 -> RES = setcc_carry // a >= b ? 0 : -1 -> RES = ~setcc_carry if (Cond.getOpcode() == X86ISD::SUB) { - unsigned CondCode = cast(CC)->getZExtValue(); + unsigned CondCode = CC->getAsZExtVal(); if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) && @@ -25367,8 +25367,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, if (IntrData->Type == INTR_TYPE_3OP_IMM8 && Src3.getValueType() != MVT::i8) { - Src3 = DAG.getTargetConstant( - cast(Src3)->getZExtValue() & 0xff, dl, MVT::i8); + Src3 = DAG.getTargetConstant(Src3->getAsZExtVal() & 0xff, dl, MVT::i8); } // We specify 2 possible opcodes for intrinsics with rounding modes. @@ -25393,8 +25392,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, assert(Op.getOperand(4)->getOpcode() == ISD::TargetConstant); SDValue Src4 = Op.getOperand(4); if (Src4.getValueType() != MVT::i8) { - Src4 = DAG.getTargetConstant( - cast(Src4)->getZExtValue() & 0xff, dl, MVT::i8); + Src4 = DAG.getTargetConstant(Src4->getAsZExtVal() & 0xff, dl, MVT::i8); } return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), @@ -26796,7 +26794,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget, {Chain, Op1, Op2, Size}, VT, MMO); Chain = Res.getValue(1); Res = DAG.getZExtOrTrunc(getSETCC(X86::COND_B, Res, DL, DAG), DL, VT); - unsigned Imm = cast(Op2)->getZExtValue(); + unsigned Imm = Op2->getAsZExtVal(); if (Imm) Res = DAG.getNode(ISD::SHL, DL, VT, Res, DAG.getShiftAmountConstant(Imm, VT, DL)); @@ -41845,7 +41843,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode( SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); - unsigned ShAmt = cast(Op1)->getZExtValue(); + unsigned ShAmt = Op1->getAsZExtVal(); if (ShAmt >= BitWidth) break; @@ -42630,7 +42628,7 @@ static SDValue combinevXi1ConstantToInteger(SDValue Op, SelectionDAG &DAG) { APInt Imm(SrcVT.getVectorNumElements(), 0); for (unsigned Idx = 0, e = Op.getNumOperands(); Idx < e; ++Idx) { SDValue In = Op.getOperand(Idx); - if (!In.isUndef() && (cast(In)->getZExtValue() & 0x1)) + if (!In.isUndef() && (In->getAsZExtVal() & 0x1)) Imm.setBit(Idx); } EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), Imm.getBitWidth()); @@ -53307,7 +53305,7 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG, if (Index.getOpcode() == ISD::ADD && Index.getValueType().getVectorElementType() == PtrVT && isa(Scale)) { - uint64_t ScaleAmt = cast(Scale)->getZExtValue(); + uint64_t ScaleAmt = Scale->getAsZExtVal(); if (auto *BV = dyn_cast(Index.getOperand(1))) { BitVector UndefElts; if (ConstantSDNode *C = BV->getConstantSplatNode(&UndefElts)) { diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 05003ec304ad..1535eb622da6 100644 --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -142,7 +142,7 @@ void XCoreDAGToDAGISel::Select(SDNode *N) { switch (N->getOpcode()) { default: break; case ISD::Constant: { - uint64_t Val = cast(N)->getZExtValue(); + uint64_t Val = N->getAsZExtVal(); if (immMskBitp(N)) { // Transformation function: get the size of a mask // Look for the first non-zero bit -- GitLab From f499472de3e1184b83fc6cd78bc244a55f2cac7d Mon Sep 17 00:00:00 2001 From: wanglei Date: Tue, 9 Jan 2024 20:32:20 +0800 Subject: [PATCH 195/652] [LoongArch] Pre-commit test for #76913. NFC This test will crash with expensive check. Crash message: ``` *** Bad machine code: Using an undefined physical register *** - function: main - basic block: %bb.0 entry (0x20fee70) - instruction: $r3 = frame-destroy ADDI_D $r22, -288 - operand 1: $r22 ``` --- .../LoongArch/can-not-realign-stack.ll | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll diff --git a/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll b/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll new file mode 100644 index 000000000000..526821076498 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll @@ -0,0 +1,39 @@ +; REQUIRES: expensive_checks +; RUN: llc --mtriple=loongarch64 --frame-pointer=none --mattr=+lasx < %s + +; XFAIL: * + +;; FIXME: This test will crash with expensive check. The subsequent patch will +;; address and fix this issue. + +%struct.S = type { [64 x i16] } + +define dso_local noundef signext i32 @main() nounwind { +entry: + %s = alloca %struct.S, align 2 + call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %s) + store <16 x i16> , ptr %s, align 2 + %0 = getelementptr inbounds [64 x i16], ptr %s, i64 0, i64 16 + store <16 x i16> , ptr %0, align 2 + %1 = getelementptr inbounds [64 x i16], ptr %s, i64 0, i64 32 + store <16 x i16> , ptr %1, align 2 + %2 = getelementptr inbounds [64 x i16], ptr %s, i64 0, i64 48 + store <16 x i16> , ptr %2, align 2 + call void @foo(ptr noundef nonnull %s) + store <16 x i16> , ptr %s, align 2 + %3 = getelementptr inbounds [64 x i16], ptr %s, i64 0, i64 16 + store <16 x i16> , ptr %3, align 2 + %4 = getelementptr inbounds [64 x i16], ptr %s, i64 0, i64 32 + store <16 x i16> , ptr %4, align 2 + %5 = getelementptr inbounds [64 x i16], ptr %s, i64 0, i64 48 + store <16 x i16> , ptr %5, align 2 + call void @bar(ptr noundef nonnull %s) + call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %s) + ret i32 0 +} + +declare void @foo(ptr nocapture noundef) +declare void @bar(ptr nocapture noundef) + +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) -- GitLab From 98c6aa72299caeff6b188e1ff2fc1b39c5b893b6 Mon Sep 17 00:00:00 2001 From: wanglei Date: Tue, 9 Jan 2024 20:35:49 +0800 Subject: [PATCH 196/652] [LoongArch] Implement LoongArchRegisterInfo::canRealignStack() (#76913) This patch fixes the crash issue in the test: CodeGen/LoongArch/can-not-realign-stack.ll Register allocator may spill virtual registers to the stack, which introduces stack alignment requirements (when the size of spilled registers exceeds the default alignment size of the stack). If a function does not have stack alignment requirements before register allocation, registers used for stack alignment will not be preserved. Therefore, we should implement `canRealignStack()` to inform the register allocator whether it is allowed to perform stack realignment operations. --- .../LoongArch/LoongArchRegisterInfo.cpp | 23 ++++++++ .../Target/LoongArch/LoongArchRegisterInfo.h | 1 + .../LoongArch/can-not-realign-stack.ll | 56 +++++++++++++++++-- 3 files changed, 75 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp index 257b947a3ce4..092b5f1fb442 100644 --- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp @@ -15,6 +15,7 @@ #include "LoongArch.h" #include "LoongArchInstrInfo.h" #include "LoongArchSubtarget.h" +#include "MCTargetDesc/LoongArchBaseInfo.h" #include "MCTargetDesc/LoongArchMCTargetDesc.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -194,3 +195,25 @@ bool LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed()); return false; } + +bool LoongArchRegisterInfo::canRealignStack(const MachineFunction &MF) const { + if (!TargetRegisterInfo::canRealignStack(MF)) + return false; + + const MachineRegisterInfo *MRI = &MF.getRegInfo(); + const LoongArchFrameLowering *TFI = getFrameLowering(MF); + + // Stack realignment requires a frame pointer. If we already started + // register allocation with frame pointer elimination, it is too late now. + if (!MRI->canReserveReg(LoongArch::R22)) + return false; + + // We may also need a base pointer if there are dynamic allocas or stack + // pointer adjustments around calls. + if (TFI->hasReservedCallFrame(MF)) + return true; + + // A base pointer is required and allowed. Check that it isn't too late to + // reserve it. + return MRI->canReserveReg(LoongArchABI::getBPReg()); +} diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h index 7e8f26b14097..d1e40254c297 100644 --- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h +++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h @@ -51,6 +51,7 @@ struct LoongArchRegisterInfo : public LoongArchGenRegisterInfo { bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { return true; } + bool canRealignStack(const MachineFunction &MF) const override; }; } // end namespace llvm diff --git a/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll b/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll index 526821076498..af24ae64b7c7 100644 --- a/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll +++ b/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll @@ -1,14 +1,60 @@ -; REQUIRES: expensive_checks -; RUN: llc --mtriple=loongarch64 --frame-pointer=none --mattr=+lasx < %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --frame-pointer=none --mattr=+lasx < %s | FileCheck %s -; XFAIL: * +;; This test is checking that when a function allows stack realignment and +;; realignment needs were not detected before register allocation (at this +;; point, fp is not preserved), but realignment is required during register +;; allocation, the stack should not undergo realignment. -;; FIXME: This test will crash with expensive check. The subsequent patch will -;; address and fix this issue. +;; Ensure that the `bstrins.d $sp, $zero, n, 0` instruction is not generated. +;; n = log2(realign_size) - 1 %struct.S = type { [64 x i16] } define dso_local noundef signext i32 @main() nounwind { +; CHECK-LABEL: main: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi.d $sp, $sp, -272 +; CHECK-NEXT: st.d $ra, $sp, 264 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 256 # 8-byte Folded Spill +; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0) +; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_0) +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvst $xr0, $sp, 96 # 32-byte Folded Spill +; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_1) +; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_1) +; CHECK-NEXT: xvld $xr1, $a0, 0 +; CHECK-NEXT: xvst $xr1, $sp, 64 # 32-byte Folded Spill +; CHECK-NEXT: xvst $xr1, $sp, 224 +; CHECK-NEXT: xvst $xr0, $sp, 192 +; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_2) +; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_2) +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvst $xr0, $sp, 32 # 32-byte Folded Spill +; CHECK-NEXT: xvst $xr0, $sp, 160 +; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_3) +; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_3) +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvst $xr0, $sp, 0 # 32-byte Folded Spill +; CHECK-NEXT: xvst $xr0, $sp, 128 +; CHECK-NEXT: addi.d $fp, $sp, 128 +; CHECK-NEXT: move $a0, $fp +; CHECK-NEXT: bl %plt(foo) +; CHECK-NEXT: xvld $xr0, $sp, 64 # 32-byte Folded Reload +; CHECK-NEXT: xvst $xr0, $sp, 224 +; CHECK-NEXT: xvld $xr0, $sp, 96 # 32-byte Folded Reload +; CHECK-NEXT: xvst $xr0, $sp, 192 +; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload +; CHECK-NEXT: xvst $xr0, $sp, 160 +; CHECK-NEXT: xvld $xr0, $sp, 0 # 32-byte Folded Reload +; CHECK-NEXT: xvst $xr0, $sp, 128 +; CHECK-NEXT: move $a0, $fp +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: move $a0, $zero +; CHECK-NEXT: ld.d $fp, $sp, 256 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 264 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 272 +; CHECK-NEXT: ret entry: %s = alloca %struct.S, align 2 call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %s) -- GitLab From d9710d7624171ff3d476925da0f4670c2c9a34cd Mon Sep 17 00:00:00 2001 From: agozillon Date: Tue, 9 Jan 2024 13:54:44 +0100 Subject: [PATCH 197/652] [Flang][Driver] Enable gpulibc/nogpulibc options for Flang, which allows linking of GPU LIBC for the fortran and OpenMP runtime (#77135) This patch seeks to add the -gpulibc and -nogpulibc for Flang, which allows the linking of the GPU libc library, this allows the use of memcpy and other useful library functions for GPU. In particular, this allows the Fortran runtime (written in C++) to be compiled for offload and then linked against the GPU LIBC library via this option to resolve memcpy and other C library functions that the fortran runtime depends on for AMD GPU devices (and likely other GPU devices). This is the current method I've tested and found to be able to utilise the Fortran runtime when compiled for AMD GPU, albeit it requires compiling libc for GPU and then the Fortran runtime for GPU, so not particularly straight forward or user friendly yet. Activating this option will allow the subset of C functions to also be utilised for GPU in other C/C++ based Fortran libraries if any are made when linking against GPU libc. --- clang/include/clang/Driver/Options.td | 4 ++-- flang/test/Driver/driver-help-hidden.f90 | 1 + flang/test/Driver/driver-help.f90 | 2 ++ flang/test/Driver/omp-driver-offload.f90 | 13 +++++++++++++ 4 files changed, 18 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index bffdddc28aac..84648c6d5500 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5200,9 +5200,9 @@ def nogpulib : Flag<["-"], "nogpulib">, MarshallingInfoFlag Visibility<[ClangOption, CC1Option]>, HelpText<"Do not link device library for CUDA/HIP device compilation">; def : Flag<["-"], "nocudalib">, Alias; -def gpulibc : Flag<["-"], "gpulibc">, Visibility<[ClangOption, CC1Option]>, +def gpulibc : Flag<["-"], "gpulibc">, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Link the LLVM C Library for GPUs">; -def nogpulibc : Flag<["-"], "nogpulibc">, Visibility<[ClangOption, CC1Option]>; +def nogpulibc : Flag<["-"], "nogpulibc">, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>; def nodefaultlibs : Flag<["-"], "nodefaultlibs">; def nodriverkitlib : Flag<["-"], "nodriverkitlib">; def nofixprebinding : Flag<["-"], "nofixprebinding">; diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90 index 9a11a7a571ff..70bb9f8eb512 100644 --- a/flang/test/Driver/driver-help-hidden.f90 +++ b/flang/test/Driver/driver-help-hidden.f90 @@ -108,6 +108,7 @@ ! CHECK-NEXT: -fxor-operator Enable .XOR. as a synonym of .NEQV. ! CHECK-NEXT: -gline-directives-only Emit debug line info directives only ! CHECK-NEXT: -gline-tables-only Emit debug line number tables only +! CHECK-NEXT: -gpulibc Link the LLVM C Library for GPUs ! CHECK-NEXT: -g Generate source-level debug information ! CHECK-NEXT: --help-hidden Display help for hidden options ! CHECK-NEXT: -help Display available options diff --git a/flang/test/Driver/driver-help.f90 b/flang/test/Driver/driver-help.f90 index e0e74dc56f33..0d760616aace 100644 --- a/flang/test/Driver/driver-help.f90 +++ b/flang/test/Driver/driver-help.f90 @@ -94,6 +94,7 @@ ! HELP-NEXT: -fxor-operator Enable .XOR. as a synonym of .NEQV. ! HELP-NEXT: -gline-directives-only Emit debug line info directives only ! HELP-NEXT: -gline-tables-only Emit debug line number tables only +! HELP-NEXT: -gpulibc Link the LLVM C Library for GPUs ! HELP-NEXT: -g Generate source-level debug information ! HELP-NEXT: --help-hidden Display help for hidden options ! HELP-NEXT: -help Display available options @@ -228,6 +229,7 @@ ! HELP-FC1-NEXT: -fversion-loops-for-stride ! HELP-FC1-NEXT: Create unit-strided versions of loops ! HELP-FC1-NEXT: -fxor-operator Enable .XOR. as a synonym of .NEQV. +! HELP-FC1-NEXT: -gpulibc Link the LLVM C Library for GPUs ! HELP-FC1-NEXT: -help Display available options ! HELP-FC1-NEXT: -init-only Only execute frontend initialization ! HELP-FC1-NEXT: -I Add directory to the end of the list of include search paths diff --git a/flang/test/Driver/omp-driver-offload.f90 b/flang/test/Driver/omp-driver-offload.f90 index ad50723b0e3a..b45ed70195fb 100644 --- a/flang/test/Driver/omp-driver-offload.f90 +++ b/flang/test/Driver/omp-driver-offload.f90 @@ -169,3 +169,16 @@ ! RUN: -fopenmp-host-ir-file-path non-existant-file.bc \ ! RUN: | FileCheck %s --check-prefix=HOST-IR-MISSING ! HOST-IR-MISSING: error: provided host compiler IR file 'non-existant-file.bc' is required to generate code for OpenMP target regions but cannot be found + +! Check that `-gpulibc` includes the LLVM C libraries for the GPU. +! RUN: %flang -### --target=x86_64-unknown-linux-gnu -fopenmp \ +! RUN: --offload-arch=gfx90a --offload-arch=sm_52 \ +! RUN: -gpulibc %s 2>&1 \ +! RUN: | FileCheck --check-prefix=LIBC-GPU %s +! LIBC-GPU: "-lcgpu"{{.*}}"-lmgpu" + +! RUN: %flang -### --target=x86_64-unknown-linux-gnu -fopenmp \ +! RUN: --offload-arch=gfx90a --offload-arch=sm_52 \ +! RUN: -nogpulibc %s 2>&1 \ +! RUN: | FileCheck --check-prefix=NO-LIBC-GPU %s +! NO-LIBC-GPU-NOT: "-lcgpu"{{.*}}"-lmgpu" -- GitLab From c1ed45a271145acbfad81d87706aeebf361809c3 Mon Sep 17 00:00:00 2001 From: agozillon Date: Tue, 9 Jan 2024 13:56:11 +0100 Subject: [PATCH 198/652] [mlir] Add global and program memory space handling to the data layout subsystem (#77367) This patch is based on a previous PR https://reviews.llvm.org/D144657 that added alloca address space handling to MLIR's DataLayout and DLTI interface. This patch aims to add identical features to import and access the global and program memory space through MLIR's DataLayout/DLTI system. --- mlir/include/mlir/Dialect/DLTI/DLTI.h | 6 ++ mlir/include/mlir/Dialect/DLTI/DLTIBase.td | 6 ++ .../mlir/Interfaces/DataLayoutInterfaces.h | 18 +++++- .../mlir/Interfaces/DataLayoutInterfaces.td | 36 +++++++++++ mlir/lib/Dialect/DLTI/DLTI.cpp | 18 ++++++ mlir/lib/Interfaces/DataLayoutInterfaces.cpp | 62 ++++++++++++++++++- mlir/lib/Target/LLVMIR/DataLayoutImporter.cpp | 23 +++++-- mlir/lib/Target/LLVMIR/DataLayoutImporter.h | 3 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 20 ++++++ mlir/test/Dialect/LLVMIR/layout.mlir | 18 ++++++ .../lib/Dialect/DLTI/TestDataLayoutQuery.cpp | 10 +++ .../Interfaces/DataLayoutInterfacesTest.cpp | 38 ++++++++++++ 12 files changed, 250 insertions(+), 8 deletions(-) diff --git a/mlir/include/mlir/Dialect/DLTI/DLTI.h b/mlir/include/mlir/Dialect/DLTI/DLTI.h index b9a8763eb449..bf23aa2d48a8 100644 --- a/mlir/include/mlir/Dialect/DLTI/DLTI.h +++ b/mlir/include/mlir/Dialect/DLTI/DLTI.h @@ -103,6 +103,12 @@ public: /// Returns the alloca memory space identifier. StringAttr getAllocaMemorySpaceIdentifier(MLIRContext *context) const; + /// Returns the program memory space identifier. + StringAttr getProgramMemorySpaceIdentifier(MLIRContext *context) const; + + /// Returns the global memory space identifier. + StringAttr getGlobalMemorySpaceIdentifier(MLIRContext *context) const; + /// Returns the stack alignment identifier. StringAttr getStackAlignmentIdentifier(MLIRContext *context) const; diff --git a/mlir/include/mlir/Dialect/DLTI/DLTIBase.td b/mlir/include/mlir/Dialect/DLTI/DLTIBase.td index 7d519f4efcd2..3572a99fad87 100644 --- a/mlir/include/mlir/Dialect/DLTI/DLTIBase.td +++ b/mlir/include/mlir/Dialect/DLTI/DLTIBase.td @@ -39,6 +39,12 @@ def DLTI_Dialect : Dialect { constexpr const static ::llvm::StringLiteral kDataLayoutAllocaMemorySpaceKey = "dlti.alloca_memory_space"; + + constexpr const static ::llvm::StringLiteral + kDataLayoutProgramMemorySpaceKey = "dlti.program_memory_space"; + + constexpr const static ::llvm::StringLiteral + kDataLayoutGlobalMemorySpaceKey = "dlti.global_memory_space"; constexpr const static ::llvm::StringLiteral kDataLayoutStackAlignmentKey = "dlti.stack_alignment"; diff --git a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h index f4b9b95fb89f..4a21f76dfc5d 100644 --- a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h +++ b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h @@ -61,6 +61,14 @@ getDefaultPreferredAlignment(Type type, const DataLayout &dataLayout, /// DataLayoutInterface if specified, otherwise returns the default. Attribute getDefaultAllocaMemorySpace(DataLayoutEntryInterface entry); +/// Default handler for program memory space request. Dispatches to the +/// DataLayoutInterface if specified, otherwise returns the default. +Attribute getDefaultProgramMemorySpace(DataLayoutEntryInterface entry); + +/// Default handler for global memory space request. Dispatches to the +/// DataLayoutInterface if specified, otherwise returns the default. +Attribute getDefaultGlobalMemorySpace(DataLayoutEntryInterface entry); + /// Default handler for the stack alignment request. Dispatches to the /// DataLayoutInterface if specified, otherwise returns the default. uint64_t getDefaultStackAlignment(DataLayoutEntryInterface entry); @@ -175,6 +183,12 @@ public: /// Returns the memory space used for AllocaOps. Attribute getAllocaMemorySpace() const; + /// Returns the memory space used for program memory operations. + Attribute getProgramMemorySpace() const; + + /// Returns the memory space used for global operations. + Attribute getGlobalMemorySpace() const; + /// Returns the natural alignment of the stack in bits. Alignment promotion of /// stack variables should be limited to the natural stack alignment to /// prevent dynamic stack alignment. Returns zero if the stack alignment is @@ -203,8 +217,10 @@ private: mutable DenseMap abiAlignments; mutable DenseMap preferredAlignments; - /// Cache for alloca memory space. + /// Cache for alloca, global, and program memory spaces. mutable std::optional allocaMemorySpace; + mutable std::optional programMemorySpace; + mutable std::optional globalMemorySpace; /// Cache for stack alignment. mutable std::optional stackAlignment; diff --git a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td index 2f60a16baf50..a8def967fffc 100644 --- a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td +++ b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td @@ -112,6 +112,18 @@ def DataLayoutSpecInterface : AttrInterface<"DataLayoutSpecInterface"> { /*methodName=*/"getAllocaMemorySpaceIdentifier", /*args=*/(ins "::mlir::MLIRContext *":$context) >, + InterfaceMethod< + /*description=*/"Returns the program memory space identifier.", + /*retTy=*/"::mlir::StringAttr", + /*methodName=*/"getProgramMemorySpaceIdentifier", + /*args=*/(ins "::mlir::MLIRContext *":$context) + >, + InterfaceMethod< + /*description=*/"Returns the global memory space identifier.", + /*retTy=*/"::mlir::StringAttr", + /*methodName=*/"getGlobalMemorySpaceIdentifier", + /*args=*/(ins "::mlir::MLIRContext *":$context) + >, InterfaceMethod< /*description=*/"Returns the stack alignment identifier.", /*retTy=*/"::mlir::StringAttr", @@ -280,6 +292,30 @@ def DataLayoutOpInterface : OpInterface<"DataLayoutOpInterface"> { return ::mlir::detail::getDefaultAllocaMemorySpace(entry); }] >, + StaticInterfaceMethod< + /*description=*/"Returns the memory space used by the ABI computed " + "using the relevant entries. The data layout object " + "can be used for recursive queries.", + /*retTy=*/"::mlir::Attribute", + /*methodName=*/"getProgramMemorySpace", + /*args=*/(ins "::mlir::DataLayoutEntryInterface":$entry), + /*methodBody=*/"", + /*defaultImplementation=*/[{ + return ::mlir::detail::getDefaultProgramMemorySpace(entry); + }] + >, + StaticInterfaceMethod< + /*description=*/"Returns the memory space used by the ABI computed " + "using the relevant entries. The data layout object " + "can be used for recursive queries.", + /*retTy=*/"::mlir::Attribute", + /*methodName=*/"getGlobalMemorySpace", + /*args=*/(ins "::mlir::DataLayoutEntryInterface":$entry), + /*methodBody=*/"", + /*defaultImplementation=*/[{ + return ::mlir::detail::getDefaultGlobalMemorySpace(entry); + }] + >, StaticInterfaceMethod< /*description=*/"Returns the natural stack alignment in bits computed " "using the relevant entries. The data layout object " diff --git a/mlir/lib/Dialect/DLTI/DLTI.cpp b/mlir/lib/Dialect/DLTI/DLTI.cpp index aba9e7db0a2f..daef2349430d 100644 --- a/mlir/lib/Dialect/DLTI/DLTI.cpp +++ b/mlir/lib/Dialect/DLTI/DLTI.cpp @@ -108,6 +108,11 @@ void DataLayoutEntryAttr::print(AsmPrinter &os) const { constexpr const StringLiteral mlir::DataLayoutSpecAttr::kAttrKeyword; constexpr const StringLiteral mlir::DLTIDialect::kDataLayoutAllocaMemorySpaceKey; +constexpr const StringLiteral + mlir::DLTIDialect::kDataLayoutProgramMemorySpaceKey; +constexpr const StringLiteral + mlir::DLTIDialect::kDataLayoutGlobalMemorySpaceKey; + constexpr const StringLiteral mlir::DLTIDialect::kDataLayoutStackAlignmentKey; namespace mlir { @@ -282,6 +287,17 @@ DataLayoutSpecAttr::getAllocaMemorySpaceIdentifier(MLIRContext *context) const { DLTIDialect::kDataLayoutAllocaMemorySpaceKey); } +StringAttr DataLayoutSpecAttr::getProgramMemorySpaceIdentifier( + MLIRContext *context) const { + return Builder(context).getStringAttr( + DLTIDialect::kDataLayoutProgramMemorySpaceKey); +} + +StringAttr +DataLayoutSpecAttr::getGlobalMemorySpaceIdentifier(MLIRContext *context) const { + return Builder(context).getStringAttr( + DLTIDialect::kDataLayoutGlobalMemorySpaceKey); +} StringAttr DataLayoutSpecAttr::getStackAlignmentIdentifier(MLIRContext *context) const { return Builder(context).getStringAttr( @@ -345,6 +361,8 @@ public: << DLTIDialect::kDataLayoutEndiannessLittle << "'"; } if (entryName == DLTIDialect::kDataLayoutAllocaMemorySpaceKey || + entryName == DLTIDialect::kDataLayoutProgramMemorySpaceKey || + entryName == DLTIDialect::kDataLayoutGlobalMemorySpaceKey || entryName == DLTIDialect::kDataLayoutStackAlignmentKey) return success(); return emitError(loc) << "unknown data layout entry name: " << entryName; diff --git a/mlir/lib/Interfaces/DataLayoutInterfaces.cpp b/mlir/lib/Interfaces/DataLayoutInterfaces.cpp index 1178417fd2a6..65c41f44192a 100644 --- a/mlir/lib/Interfaces/DataLayoutInterfaces.cpp +++ b/mlir/lib/Interfaces/DataLayoutInterfaces.cpp @@ -230,6 +230,30 @@ mlir::detail::getDefaultAllocaMemorySpace(DataLayoutEntryInterface entry) { return entry.getValue(); } +// Returns the memory space used for the program memory space. if +// specified in the given entry. If the entry is empty the default +// memory space represented by an empty attribute is returned. +Attribute +mlir::detail::getDefaultProgramMemorySpace(DataLayoutEntryInterface entry) { + if (entry == DataLayoutEntryInterface()) { + return Attribute(); + } + + return entry.getValue(); +} + +// Returns the memory space used for global the global memory space. if +// specified in the given entry. If the entry is empty the default memory +// space represented by an empty attribute is returned. +Attribute +mlir::detail::getDefaultGlobalMemorySpace(DataLayoutEntryInterface entry) { + if (entry == DataLayoutEntryInterface()) { + return Attribute(); + } + + return entry.getValue(); +} + // Returns the stack alignment if specified in the given entry. If the entry is // empty the default alignment zero is returned. uint64_t @@ -382,7 +406,8 @@ mlir::DataLayout::DataLayout() : DataLayout(ModuleOp()) {} mlir::DataLayout::DataLayout(DataLayoutOpInterface op) : originalLayout(getCombinedDataLayout(op)), scope(op), - allocaMemorySpace(std::nullopt), stackAlignment(std::nullopt) { + allocaMemorySpace(std::nullopt), programMemorySpace(std::nullopt), + globalMemorySpace(std::nullopt), stackAlignment(std::nullopt) { #if LLVM_ENABLE_ABI_BREAKING_CHECKS checkMissingLayout(originalLayout, op); collectParentLayouts(op, layoutStack); @@ -391,7 +416,8 @@ mlir::DataLayout::DataLayout(DataLayoutOpInterface op) mlir::DataLayout::DataLayout(ModuleOp op) : originalLayout(getCombinedDataLayout(op)), scope(op), - allocaMemorySpace(std::nullopt), stackAlignment(std::nullopt) { + allocaMemorySpace(std::nullopt), programMemorySpace(std::nullopt), + globalMemorySpace(std::nullopt), stackAlignment(std::nullopt) { #if LLVM_ENABLE_ABI_BREAKING_CHECKS checkMissingLayout(originalLayout, op); collectParentLayouts(op, layoutStack); @@ -510,6 +536,38 @@ mlir::Attribute mlir::DataLayout::getAllocaMemorySpace() const { return *allocaMemorySpace; } +mlir::Attribute mlir::DataLayout::getProgramMemorySpace() const { + checkValid(); + if (programMemorySpace) + return *programMemorySpace; + DataLayoutEntryInterface entry; + if (originalLayout) + entry = originalLayout.getSpecForIdentifier( + originalLayout.getProgramMemorySpaceIdentifier( + originalLayout.getContext())); + if (auto iface = dyn_cast_or_null(scope)) + programMemorySpace = iface.getProgramMemorySpace(entry); + else + programMemorySpace = detail::getDefaultProgramMemorySpace(entry); + return *programMemorySpace; +} + +mlir::Attribute mlir::DataLayout::getGlobalMemorySpace() const { + checkValid(); + if (globalMemorySpace) + return *globalMemorySpace; + DataLayoutEntryInterface entry; + if (originalLayout) + entry = originalLayout.getSpecForIdentifier( + originalLayout.getGlobalMemorySpaceIdentifier( + originalLayout.getContext())); + if (auto iface = dyn_cast_or_null(scope)) + globalMemorySpace = iface.getGlobalMemorySpace(entry); + else + globalMemorySpace = detail::getDefaultGlobalMemorySpace(entry); + return *globalMemorySpace; +} + uint64_t mlir::DataLayout::getStackAlignment() const { checkValid(); if (stackAlignment) diff --git a/mlir/lib/Target/LLVMIR/DataLayoutImporter.cpp b/mlir/lib/Target/LLVMIR/DataLayoutImporter.cpp index 95f3cc074b1d..392f552f480c 100644 --- a/mlir/lib/Target/LLVMIR/DataLayoutImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DataLayoutImporter.cpp @@ -164,9 +164,9 @@ DataLayoutImporter::tryToEmplaceEndiannessEntry(StringRef endianness, } LogicalResult -DataLayoutImporter::tryToEmplaceAllocaAddrSpaceEntry(StringRef token) { - auto key = - StringAttr::get(context, DLTIDialect::kDataLayoutAllocaMemorySpaceKey); +DataLayoutImporter::tryToEmplaceAddrSpaceEntry(StringRef token, + llvm::StringLiteral spaceKey) { + auto key = StringAttr::get(context, spaceKey); if (keyEntries.count(key)) return success(); @@ -247,9 +247,24 @@ void DataLayoutImporter::translateDataLayout( return; continue; } + // Parse the program address space. + if (*prefix == "P") { + if (failed(tryToEmplaceAddrSpaceEntry( + token, DLTIDialect::kDataLayoutProgramMemorySpaceKey))) + return; + continue; + } + // Parse the global address space. + if (*prefix == "G") { + if (failed(tryToEmplaceAddrSpaceEntry( + token, DLTIDialect::kDataLayoutGlobalMemorySpaceKey))) + return; + continue; + } // Parse the alloca address space. if (*prefix == "A") { - if (failed(tryToEmplaceAllocaAddrSpaceEntry(token))) + if (failed(tryToEmplaceAddrSpaceEntry( + token, DLTIDialect::kDataLayoutAllocaMemorySpaceKey))) return; continue; } diff --git a/mlir/lib/Target/LLVMIR/DataLayoutImporter.h b/mlir/lib/Target/LLVMIR/DataLayoutImporter.h index 15f0f7ddf070..59b60acd24be 100644 --- a/mlir/lib/Target/LLVMIR/DataLayoutImporter.h +++ b/mlir/lib/Target/LLVMIR/DataLayoutImporter.h @@ -97,7 +97,8 @@ private: StringRef token); /// Adds an alloca address space entry if there is none yet. - LogicalResult tryToEmplaceAllocaAddrSpaceEntry(StringRef token); + LogicalResult tryToEmplaceAddrSpaceEntry(StringRef token, + llvm::StringLiteral spaceKey); /// Adds a stack alignment entry if there is none yet. LogicalResult tryToEmplaceStackAlignmentEntry(StringRef token); diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp index 1722d74c08b6..ce46a194ea7d 100644 --- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp @@ -190,6 +190,26 @@ translateDataLayout(DataLayoutSpecInterface attribute, layoutStream.flush(); continue; } + if (key.getValue() == DLTIDialect::kDataLayoutProgramMemorySpaceKey) { + auto value = cast(entry.getValue()); + uint64_t space = value.getValue().getZExtValue(); + // Skip the default address space. + if (space == 0) + continue; + layoutStream << "-P" << space; + layoutStream.flush(); + continue; + } + if (key.getValue() == DLTIDialect::kDataLayoutGlobalMemorySpaceKey) { + auto value = cast(entry.getValue()); + uint64_t space = value.getValue().getZExtValue(); + // Skip the default address space. + if (space == 0) + continue; + layoutStream << "-G" << space; + layoutStream.flush(); + continue; + } if (key.getValue() == DLTIDialect::kDataLayoutAllocaMemorySpaceKey) { auto value = cast(entry.getValue()); uint64_t space = value.getValue().getZExtValue(); diff --git a/mlir/test/Dialect/LLVMIR/layout.mlir b/mlir/test/Dialect/LLVMIR/layout.mlir index 99d617853844..2868e1740f86 100644 --- a/mlir/test/Dialect/LLVMIR/layout.mlir +++ b/mlir/test/Dialect/LLVMIR/layout.mlir @@ -6,21 +6,27 @@ module { // CHECK: alignment = 8 // CHECK: alloca_memory_space = 0 // CHECK: bitsize = 64 + // CHECK: global_memory_space = 0 // CHECK: preferred = 8 + // CHECK: program_memory_space = 0 // CHECK: size = 8 // CHECK: stack_alignment = 0 "test.data_layout_query"() : () -> !llvm.ptr // CHECK: alignment = 8 // CHECK: alloca_memory_space = 0 // CHECK: bitsize = 64 + // CHECK: global_memory_space = 0 // CHECK: preferred = 8 + // CHECK: program_memory_space = 0 // CHECK: size = 8 // CHECK: stack_alignment = 0 "test.data_layout_query"() : () -> !llvm.ptr<3> // CHECK: alignment = 8 // CHECK: alloca_memory_space = 0 // CHECK: bitsize = 64 + // CHECK: global_memory_space = 0 // CHECK: preferred = 8 + // CHECK: program_memory_space = 0 // CHECK: size = 8 // CHECK: stack_alignment = 0 "test.data_layout_query"() : () -> !llvm.ptr<5> @@ -35,6 +41,8 @@ module attributes { dlti.dl_spec = #dlti.dl_spec< #dlti.dl_entry, dense<[64, 64, 64]> : vector<3xi64>>, #dlti.dl_entry, dense<[32, 64, 64]> : vector<3xi64>>, #dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui64>, + #dlti.dl_entry<"dlti.global_memory_space", 2 : ui64>, + #dlti.dl_entry<"dlti.program_memory_space", 3 : ui64>, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64> >} { // CHECK: @spec @@ -42,35 +50,45 @@ module attributes { dlti.dl_spec = #dlti.dl_spec< // CHECK: alignment = 4 // CHECK: alloca_memory_space = 5 // CHECK: bitsize = 32 + // CHECK: global_memory_space = 2 // CHECK: preferred = 8 + // CHECK: program_memory_space = 3 // CHECK: size = 4 // CHECK: stack_alignment = 128 "test.data_layout_query"() : () -> !llvm.ptr // CHECK: alignment = 4 // CHECK: alloca_memory_space = 5 // CHECK: bitsize = 32 + // CHECK: global_memory_space = 2 // CHECK: preferred = 8 + // CHECK: program_memory_space = 3 // CHECK: size = 4 // CHECK: stack_alignment = 128 "test.data_layout_query"() : () -> !llvm.ptr<3> // CHECK: alignment = 8 // CHECK: alloca_memory_space = 5 // CHECK: bitsize = 64 + // CHECK: global_memory_space = 2 // CHECK: preferred = 8 + // CHECK: program_memory_space = 3 // CHECK: size = 8 // CHECK: stack_alignment = 128 "test.data_layout_query"() : () -> !llvm.ptr<5> // CHECK: alignment = 4 // CHECK: alloca_memory_space = 5 // CHECK: bitsize = 32 + // CHECK: global_memory_space = 2 // CHECK: preferred = 8 + // CHECK: program_memory_space = 3 // CHECK: size = 4 // CHECK: stack_alignment = 128 "test.data_layout_query"() : () -> !llvm.ptr<3> // CHECK: alignment = 8 // CHECK: alloca_memory_space = 5 // CHECK: bitsize = 32 + // CHECK: global_memory_space = 2 // CHECK: preferred = 8 + // CHECK: program_memory_space = 3 // CHECK: size = 4 // CHECK: stack_alignment = 128 "test.data_layout_query"() : () -> !llvm.ptr<4> diff --git a/mlir/test/lib/Dialect/DLTI/TestDataLayoutQuery.cpp b/mlir/test/lib/Dialect/DLTI/TestDataLayoutQuery.cpp index 7e3d3f6dc3f0..740562e77830 100644 --- a/mlir/test/lib/Dialect/DLTI/TestDataLayoutQuery.cpp +++ b/mlir/test/lib/Dialect/DLTI/TestDataLayoutQuery.cpp @@ -41,6 +41,8 @@ struct TestDataLayoutQuery unsigned alignment = layout.getTypeABIAlignment(op.getType()); unsigned preferred = layout.getTypePreferredAlignment(op.getType()); Attribute allocaMemorySpace = layout.getAllocaMemorySpace(); + Attribute programMemorySpace = layout.getProgramMemorySpace(); + Attribute globalMemorySpace = layout.getGlobalMemorySpace(); unsigned stackAlignment = layout.getStackAlignment(); op->setAttrs( {builder.getNamedAttr("size", builder.getIndexAttr(size)), @@ -51,6 +53,14 @@ struct TestDataLayoutQuery allocaMemorySpace == Attribute() ? builder.getUI32IntegerAttr(0) : allocaMemorySpace), + builder.getNamedAttr("program_memory_space", + programMemorySpace == Attribute() + ? builder.getUI32IntegerAttr(0) + : programMemorySpace), + builder.getNamedAttr("global_memory_space", + globalMemorySpace == Attribute() + ? builder.getUI32IntegerAttr(0) + : globalMemorySpace), builder.getNamedAttr("stack_alignment", builder.getIndexAttr(stackAlignment))}); }); diff --git a/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp b/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp index 79599b8c4850..794e19710fad 100644 --- a/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp +++ b/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp @@ -24,6 +24,10 @@ namespace { constexpr static llvm::StringLiteral kAttrName = "dltest.layout"; constexpr static llvm::StringLiteral kAllocaKeyName = "dltest.alloca_memory_space"; +constexpr static llvm::StringLiteral kProgramKeyName = + "dltest.program_memory_space"; +constexpr static llvm::StringLiteral kGlobalKeyName = + "dltest.global_memory_space"; constexpr static llvm::StringLiteral kStackAlignmentKeyName = "dltest.stack_alignment"; @@ -72,6 +76,12 @@ struct CustomDataLayoutSpec StringAttr getAllocaMemorySpaceIdentifier(MLIRContext *context) const { return Builder(context).getStringAttr(kAllocaKeyName); } + StringAttr getProgramMemorySpaceIdentifier(MLIRContext *context) const { + return Builder(context).getStringAttr(kProgramKeyName); + } + StringAttr getGlobalMemorySpaceIdentifier(MLIRContext *context) const { + return Builder(context).getStringAttr(kGlobalKeyName); + } StringAttr getStackAlignmentIdentifier(MLIRContext *context) const { return Builder(context).getStringAttr(kStackAlignmentKeyName); } @@ -128,6 +138,24 @@ struct SingleQueryType executed = true; return Attribute(); } + + Attribute getProgramMemorySpace(DataLayoutEntryInterface entry) { + static bool executed = false; + if (executed) + llvm::report_fatal_error("repeated call"); + + executed = true; + return Attribute(); + } + + Attribute getGlobalMemorySpace(DataLayoutEntryInterface entry) { + static bool executed = false; + if (executed) + llvm::report_fatal_error("repeated call"); + + executed = true; + return Attribute(); + } }; /// A types that is not subject to data layout. @@ -290,6 +318,8 @@ module {} EXPECT_EQ(layout.getTypePreferredAlignment(Float16Type::get(&ctx)), 2u); EXPECT_EQ(layout.getAllocaMemorySpace(), Attribute()); + EXPECT_EQ(layout.getProgramMemorySpace(), Attribute()); + EXPECT_EQ(layout.getGlobalMemorySpace(), Attribute()); EXPECT_EQ(layout.getStackAlignment(), 0u); } @@ -317,6 +347,8 @@ TEST(DataLayout, NullSpec) { EXPECT_EQ(layout.getTypePreferredAlignment(Float16Type::get(&ctx)), 32u); EXPECT_EQ(layout.getAllocaMemorySpace(), Attribute()); + EXPECT_EQ(layout.getProgramMemorySpace(), Attribute()); + EXPECT_EQ(layout.getGlobalMemorySpace(), Attribute()); EXPECT_EQ(layout.getStackAlignment(), 0u); } @@ -343,6 +375,8 @@ TEST(DataLayout, EmptySpec) { EXPECT_EQ(layout.getTypePreferredAlignment(Float16Type::get(&ctx)), 32u); EXPECT_EQ(layout.getAllocaMemorySpace(), Attribute()); + EXPECT_EQ(layout.getProgramMemorySpace(), Attribute()); + EXPECT_EQ(layout.getGlobalMemorySpace(), Attribute()); EXPECT_EQ(layout.getStackAlignment(), 0u); } @@ -352,6 +386,8 @@ TEST(DataLayout, SpecWithEntries) { #dlti.dl_entry, #dlti.dl_entry, #dlti.dl_entry<"dltest.alloca_memory_space", 5 : i32>, + #dlti.dl_entry<"dltest.program_memory_space", 3 : i32>, + #dlti.dl_entry<"dltest.global_memory_space", 2 : i32>, #dlti.dl_entry<"dltest.stack_alignment", 128 : i32> > } : () -> () )MLIR"; @@ -383,6 +419,8 @@ TEST(DataLayout, SpecWithEntries) { EXPECT_EQ(layout.getTypePreferredAlignment(Float32Type::get(&ctx)), 64u); EXPECT_EQ(layout.getAllocaMemorySpace(), Builder(&ctx).getI32IntegerAttr(5)); + EXPECT_EQ(layout.getProgramMemorySpace(), Builder(&ctx).getI32IntegerAttr(3)); + EXPECT_EQ(layout.getGlobalMemorySpace(), Builder(&ctx).getI32IntegerAttr(2)); EXPECT_EQ(layout.getStackAlignment(), 128u); } -- GitLab From 2c651e6c381905aff6c7ac4b1585bad168f5b553 Mon Sep 17 00:00:00 2001 From: David Sherwood <57997763+david-arm@users.noreply.github.com> Date: Tue, 9 Jan 2024 13:22:28 +0000 Subject: [PATCH 199/652] =?UTF-8?q?[AArch64]=20Fix=20regression=20introduc?= =?UTF-8?q?ed=20by=20c7148467fc08eefaaae876c7d11d62=E2=80=A6=20(#77467)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …9c849f42cf --- llvm/test/Transforms/LoopIdiom/AArch64/lit.local.cfg | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 llvm/test/Transforms/LoopIdiom/AArch64/lit.local.cfg diff --git a/llvm/test/Transforms/LoopIdiom/AArch64/lit.local.cfg b/llvm/test/Transforms/LoopIdiom/AArch64/lit.local.cfg new file mode 100644 index 000000000000..10d4a0e953ed --- /dev/null +++ b/llvm/test/Transforms/LoopIdiom/AArch64/lit.local.cfg @@ -0,0 +1,2 @@ +if not "AArch64" in config.root.targets: + config.unsupported = True -- GitLab From 20c144ea10be1e4b2620a4a1c949cbad315cff72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 9 Jan 2024 11:04:03 +0100 Subject: [PATCH 200/652] [clang][Sema][NFC] Make a few parameters const --- clang/include/clang/Sema/Sema.h | 2 +- clang/lib/Sema/SemaExpr.cpp | 44 ++++++++++++++++----------------- 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 4c464a1ae4c6..edaee4c4b66d 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -12972,7 +12972,7 @@ public: QualType FindCompositeObjCPointerType(ExprResult &LHS, ExprResult &RHS, SourceLocation QuestionLoc); - bool DiagnoseConditionalForNull(Expr *LHSExpr, Expr *RHSExpr, + bool DiagnoseConditionalForNull(const Expr *LHSExpr, const Expr *RHSExpr, SourceLocation QuestionLoc); void DiagnoseAlwaysNonNullPointer(Expr *E, diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 960f513d1111..60ad035570c8 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -8691,10 +8691,10 @@ ExprResult Sema::ActOnParenListExpr(SourceLocation L, /// Emit a specialized diagnostic when one expression is a null pointer /// constant and the other is not a pointer. Returns true if a diagnostic is /// emitted. -bool Sema::DiagnoseConditionalForNull(Expr *LHSExpr, Expr *RHSExpr, +bool Sema::DiagnoseConditionalForNull(const Expr *LHSExpr, const Expr *RHSExpr, SourceLocation QuestionLoc) { - Expr *NullExpr = LHSExpr; - Expr *NonPointerExpr = RHSExpr; + const Expr *NullExpr = LHSExpr; + const Expr *NonPointerExpr = RHSExpr; Expr::NullPointerConstantKind NullKind = NullExpr->isNullPointerConstant(Context, Expr::NPC_ValueDependentIsNotNull); @@ -8730,7 +8730,8 @@ bool Sema::DiagnoseConditionalForNull(Expr *LHSExpr, Expr *RHSExpr, } /// Return false if the condition expression is valid, true otherwise. -static bool checkCondition(Sema &S, Expr *Cond, SourceLocation QuestionLoc) { +static bool checkCondition(Sema &S, const Expr *Cond, + SourceLocation QuestionLoc) { QualType CondTy = Cond->getType(); // OpenCL v1.1 s6.3.i says the condition cannot be a floating point type. @@ -9542,28 +9543,27 @@ static bool IsArithmeticOp(BinaryOperatorKind Opc) { /// expression, either using a built-in or overloaded operator, /// and sets *OpCode to the opcode and *RHSExprs to the right-hand side /// expression. -static bool IsArithmeticBinaryExpr(Expr *E, BinaryOperatorKind *Opcode, - Expr **RHSExprs) { +static bool IsArithmeticBinaryExpr(const Expr *E, BinaryOperatorKind *Opcode, + const Expr **RHSExprs) { // Don't strip parenthesis: we should not warn if E is in parenthesis. E = E->IgnoreImpCasts(); E = E->IgnoreConversionOperatorSingleStep(); E = E->IgnoreImpCasts(); - if (auto *MTE = dyn_cast(E)) { + if (const auto *MTE = dyn_cast(E)) { E = MTE->getSubExpr(); E = E->IgnoreImpCasts(); } // Built-in binary operator. - if (BinaryOperator *OP = dyn_cast(E)) { - if (IsArithmeticOp(OP->getOpcode())) { - *Opcode = OP->getOpcode(); - *RHSExprs = OP->getRHS(); - return true; - } + if (const auto *OP = dyn_cast(E); + OP && IsArithmeticOp(OP->getOpcode())) { + *Opcode = OP->getOpcode(); + *RHSExprs = OP->getRHS(); + return true; } // Overloaded operator. - if (CXXOperatorCallExpr *Call = dyn_cast(E)) { + if (const auto *Call = dyn_cast(E)) { if (Call->getNumArgs() != 2) return false; @@ -9588,14 +9588,14 @@ static bool IsArithmeticBinaryExpr(Expr *E, BinaryOperatorKind *Opcode, /// ExprLooksBoolean - Returns true if E looks boolean, i.e. it has boolean type /// or is a logical expression such as (x==y) which has int type, but is /// commonly interpreted as boolean. -static bool ExprLooksBoolean(Expr *E) { +static bool ExprLooksBoolean(const Expr *E) { E = E->IgnoreParenImpCasts(); if (E->getType()->isBooleanType()) return true; - if (BinaryOperator *OP = dyn_cast(E)) + if (const auto *OP = dyn_cast(E)) return OP->isComparisonOp() || OP->isLogicalOp(); - if (UnaryOperator *OP = dyn_cast(E)) + if (const auto *OP = dyn_cast(E)) return OP->getOpcode() == UO_LNot; if (E->getType()->isPointerType()) return true; @@ -9609,13 +9609,11 @@ static bool ExprLooksBoolean(Expr *E) { /// and binary operator are mixed in a way that suggests the programmer assumed /// the conditional operator has higher precedence, for example: /// "int x = a + someBinaryCondition ? 1 : 2". -static void DiagnoseConditionalPrecedence(Sema &Self, - SourceLocation OpLoc, - Expr *Condition, - Expr *LHSExpr, - Expr *RHSExpr) { +static void DiagnoseConditionalPrecedence(Sema &Self, SourceLocation OpLoc, + Expr *Condition, const Expr *LHSExpr, + const Expr *RHSExpr) { BinaryOperatorKind CondOpcode; - Expr *CondRHS; + const Expr *CondRHS; if (!IsArithmeticBinaryExpr(Condition, &CondOpcode, &CondRHS)) return; -- GitLab From 963a2ebef8e9b3409ffc728e377dc53b0baff722 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 9 Jan 2024 15:07:41 +0100 Subject: [PATCH 201/652] [JumpThreading] Regenerate test checks (NFC) --- .../Transforms/JumpThreading/ddt-crash.ll | 134 +++++++++--------- .../test/Transforms/JumpThreading/loop-phi.ll | 38 +++-- .../JumpThreading/unreachable-loops.ll | 8 +- 3 files changed, 101 insertions(+), 79 deletions(-) diff --git a/llvm/test/Transforms/JumpThreading/ddt-crash.ll b/llvm/test/Transforms/JumpThreading/ddt-crash.ll index e91b0b6f30c7..3f191a9d49db 100644 --- a/llvm/test/Transforms/JumpThreading/ddt-crash.ll +++ b/llvm/test/Transforms/JumpThreading/ddt-crash.ll @@ -20,10 +20,10 @@ define void @blam() { ; CHECK: bb2: ; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @wombat.2() ; CHECK-NEXT: switch i32 [[TMP3]], label [[BB10:%.*]] [ -; CHECK-NEXT: i32 0, label [[BB7:%.*]] -; CHECK-NEXT: i32 1, label [[BB10]] -; CHECK-NEXT: i32 2, label [[BB10]] -; CHECK-NEXT: i32 3, label [[BB11]] +; CHECK-NEXT: i32 0, label [[BB7:%.*]] +; CHECK-NEXT: i32 1, label [[BB10]] +; CHECK-NEXT: i32 2, label [[BB10]] +; CHECK-NEXT: i32 3, label [[BB11]] ; CHECK-NEXT: ] ; CHECK: bb7: ; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @wombat.2() @@ -41,10 +41,10 @@ bb: bb2: %tmp3 = tail call i32 @wombat.2() switch i32 %tmp3, label %bb4 [ - i32 0, label %bb5 - i32 1, label %bb7 - i32 2, label %bb7 - i32 3, label %bb11 + i32 0, label %bb5 + i32 1, label %bb7 + i32 2, label %bb7 + i32 3, label %bb11 ] bb4: @@ -71,10 +71,10 @@ define void @spam(ptr %arg) { ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP:%.*]] = load i8, ptr undef, align 8 ; CHECK-NEXT: switch i8 [[TMP]], label [[BB11:%.*]] [ -; CHECK-NEXT: i8 1, label [[BB11]] -; CHECK-NEXT: i8 2, label [[BB11]] -; CHECK-NEXT: i8 3, label [[BB1:%.*]] -; CHECK-NEXT: i8 4, label [[BB1]] +; CHECK-NEXT: i8 1, label [[BB11]] +; CHECK-NEXT: i8 2, label [[BB11]] +; CHECK-NEXT: i8 3, label [[BB1:%.*]] +; CHECK-NEXT: i8 4, label [[BB1]] ; CHECK-NEXT: ] ; CHECK: bb1: ; CHECK-NEXT: br label [[BB2:%.*]] @@ -84,20 +84,20 @@ define void @spam(ptr %arg) { ; CHECK: bb4: ; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr undef, align 8 ; CHECK-NEXT: switch i8 [[TMP5]], label [[BB11]] [ -; CHECK-NEXT: i8 0, label [[BB11]] -; CHECK-NEXT: i8 1, label [[BB10:%.*]] -; CHECK-NEXT: i8 2, label [[BB10]] -; CHECK-NEXT: i8 3, label [[BB8]] -; CHECK-NEXT: i8 4, label [[BB8]] +; CHECK-NEXT: i8 0, label [[BB11]] +; CHECK-NEXT: i8 1, label [[BB10:%.*]] +; CHECK-NEXT: i8 2, label [[BB10]] +; CHECK-NEXT: i8 3, label [[BB8]] +; CHECK-NEXT: i8 4, label [[BB8]] ; CHECK-NEXT: ] ; CHECK: bb8: ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq ptr undef, [[ARG:%.*]] ; CHECK-NEXT: br i1 [[TMP9]], label [[BB10]], label [[BB2]] ; CHECK: bb10: ; CHECK-NEXT: switch i32 [[TMP3]], label [[BB4]] [ -; CHECK-NEXT: i32 0, label [[BB16:%.*]] -; CHECK-NEXT: i32 1, label [[BB11]] -; CHECK-NEXT: i32 2, label [[BB12:%.*]] +; CHECK-NEXT: i32 0, label [[BB16:%.*]] +; CHECK-NEXT: i32 1, label [[BB11]] +; CHECK-NEXT: i32 2, label [[BB12:%.*]] ; CHECK-NEXT: ] ; CHECK: bb11: ; CHECK-NEXT: unreachable @@ -108,9 +108,9 @@ define void @spam(ptr %arg) { ; CHECK-NEXT: [[TMP15:%.*]] = phi ptr [ [[TMP13]], [[BB12]] ], [ null, [[BB10]] ] ; CHECK-NEXT: [[TMP17:%.*]] = load i8, ptr undef, align 8 ; CHECK-NEXT: switch i8 [[TMP17]], label [[BB11]] [ -; CHECK-NEXT: i8 0, label [[BB11]] -; CHECK-NEXT: i8 11, label [[BB23:%.*]] -; CHECK-NEXT: i8 12, label [[BB23]] +; CHECK-NEXT: i8 0, label [[BB11]] +; CHECK-NEXT: i8 11, label [[BB23:%.*]] +; CHECK-NEXT: i8 12, label [[BB23]] ; CHECK-NEXT: ] ; CHECK: bb23: ; CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr undef, align 8 @@ -148,10 +148,10 @@ define void @spam(ptr %arg) { bb: %tmp = load i8, ptr undef, align 8 switch i8 %tmp, label %bb11 [ - i8 1, label %bb11 - i8 2, label %bb11 - i8 3, label %bb1 - i8 4, label %bb1 + i8 1, label %bb11 + i8 2, label %bb11 + i8 3, label %bb1 + i8 4, label %bb1 ] bb1: @@ -164,11 +164,11 @@ bb2: bb4: %tmp5 = load i8, ptr undef, align 8 switch i8 %tmp5, label %bb11 [ - i8 0, label %bb11 - i8 1, label %bb10 - i8 2, label %bb10 - i8 3, label %bb6 - i8 4, label %bb6 + i8 0, label %bb11 + i8 1, label %bb10 + i8 2, label %bb10 + i8 3, label %bb6 + i8 4, label %bb6 ] bb6: @@ -183,9 +183,9 @@ bb8: bb10: switch i32 %tmp3, label %bb4 [ - i32 0, label %bb14 - i32 1, label %bb11 - i32 2, label %bb12 + i32 0, label %bb14 + i32 1, label %bb11 + i32 2, label %bb12 ] bb11: @@ -202,9 +202,9 @@ bb14: bb16: %tmp17 = load i8, ptr undef, align 8 switch i8 %tmp17, label %bb11 [ - i8 0, label %bb11 - i8 11, label %bb18 - i8 12, label %bb18 + i8 0, label %bb11 + i8 11, label %bb18 + i8 12, label %bb18 ] bb18: @@ -216,9 +216,9 @@ bb19: bb20: %tmp21 = load ptr, ptr undef switch i8 undef, label %bb22 [ - i8 0, label %bb4 - i8 11, label %bb10 - i8 12, label %bb10 + i8 0, label %bb4 + i8 11, label %bb10 + i8 12, label %bb10 ] bb22: @@ -271,76 +271,76 @@ define void @zot() align 2 personality ptr @foo { ; CHECK-LABEL: @zot( ; CHECK-NEXT: bb: ; CHECK-NEXT: invoke void @bar() -; CHECK-NEXT: to label [[BB1:%.*]] unwind label [[BB3:%.*]] +; CHECK-NEXT: to label [[BB1:%.*]] unwind label [[BB3:%.*]] ; CHECK: bb1: ; CHECK-NEXT: invoke void @bar() -; CHECK-NEXT: to label [[BB2:%.*]] unwind label [[BB4:%.*]] +; CHECK-NEXT: to label [[BB2:%.*]] unwind label [[BB4:%.*]] ; CHECK: bb2: ; CHECK-NEXT: invoke void @bar() -; CHECK-NEXT: to label [[BB6:%.*]] unwind label [[BB17:%.*]] +; CHECK-NEXT: to label [[BB6:%.*]] unwind label [[BB17:%.*]] ; CHECK: bb3: ; CHECK-NEXT: [[TMP:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: unreachable ; CHECK: bb4: ; CHECK-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: unreachable ; CHECK: bb6: ; CHECK-NEXT: invoke void @bar() -; CHECK-NEXT: to label [[BB7:%.*]] unwind label [[BB19:%.*]] +; CHECK-NEXT: to label [[BB7:%.*]] unwind label [[BB19:%.*]] ; CHECK: bb7: ; CHECK-NEXT: invoke void @bar() -; CHECK-NEXT: to label [[BB10:%.*]] unwind label [[BB8:%.*]] +; CHECK-NEXT: to label [[BB10:%.*]] unwind label [[BB8:%.*]] ; CHECK: bb8: ; CHECK-NEXT: [[TMP9:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: cleanup -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: cleanup +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: unreachable ; CHECK: bb10: ; CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr undef, align 8 ; CHECK-NEXT: [[TMP12:%.*]] = invoke i32 [[TMP11]](ptr nonnull undef) -; CHECK-NEXT: to label [[BB13:%.*]] unwind label [[BB21:%.*]] +; CHECK-NEXT: to label [[BB13:%.*]] unwind label [[BB21:%.*]] ; CHECK: bb13: ; CHECK-NEXT: invoke void @bar() -; CHECK-NEXT: to label [[BB14:%.*]] unwind label [[BB30:%.*]] +; CHECK-NEXT: to label [[BB14:%.*]] unwind label [[BB30:%.*]] ; CHECK: bb14: ; CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr undef, align 8 ; CHECK-NEXT: [[TMP16:%.*]] = invoke i32 [[TMP15]](ptr nonnull undef) -; CHECK-NEXT: to label [[BB26:%.*]] unwind label [[BB30_THREAD:%.*]] +; CHECK-NEXT: to label [[BB26:%.*]] unwind label [[BB30_THREAD:%.*]] ; CHECK: bb17: ; CHECK-NEXT: [[TMP18:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: unreachable ; CHECK: bb19: ; CHECK-NEXT: [[TMP20:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: unreachable ; CHECK: bb21: ; CHECK-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: unreachable ; CHECK: bb26: ; CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr undef, align 8 ; CHECK-NEXT: [[TMP28:%.*]] = invoke i32 [[TMP27]](ptr nonnull undef) -; CHECK-NEXT: to label [[BB29:%.*]] unwind label [[BB30_THREAD]] +; CHECK-NEXT: to label [[BB29:%.*]] unwind label [[BB30_THREAD]] ; CHECK: bb29: ; CHECK-NEXT: unreachable ; CHECK: bb30.thread: ; CHECK-NEXT: [[LPAD_THR_COMM:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: br label [[BB32:%.*]] ; CHECK: bb30: ; CHECK-NEXT: [[LPAD_THR_COMM_SPLIT_LP:%.*]] = landingpad { ptr, i32 } -; CHECK-NEXT: catch ptr @global.1 -; CHECK-NEXT: catch ptr null +; CHECK-NEXT: catch ptr @global.1 +; CHECK-NEXT: catch ptr null ; CHECK-NEXT: br label [[BB32]] ; CHECK: bb32: ; CHECK-NEXT: unreachable diff --git a/llvm/test/Transforms/JumpThreading/loop-phi.ll b/llvm/test/Transforms/JumpThreading/loop-phi.ll index 1d22d69d75fa..9b8208296345 100644 --- a/llvm/test/Transforms/JumpThreading/loop-phi.ll +++ b/llvm/test/Transforms/JumpThreading/loop-phi.ll @@ -1,17 +1,39 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=jump-threading -S -jump-threading-across-loop-headers | FileCheck %s ; Make sure we correctly distinguish between %tmp15 and %tmp16 when we clone ; body2. -; CHECK: body2.thread: -; CHECK-NEXT: %tmp163 = add i32 %tmp165, 1 -; CHECK-NEXT: br label %latch1 - -; CHECK: latch1: -; CHECK-NEXT: %tmp165 = phi i32 [ %tmp163, %body2.thread ], [ %tmp16, %body2 ] -; CHECK-NEXT: %tmp154 = phi i32 [ %tmp165, %body2.thread ], [ %tmp15, %body2 ] - define i32 @test(i1 %ARG1, i1 %ARG2, i32 %n) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: i1 [[ARG1:%.*]], i1 [[ARG2:%.*]], i32 [[N:%.*]]) { +; CHECK-NEXT: head1: +; CHECK-NEXT: br i1 [[ARG1]], label [[EXIT:%.*]], label [[BODY2:%.*]] +; CHECK: head1.thread: +; CHECK-NEXT: br i1 [[ARG1]], label [[EXIT]], label [[BODY2_THREAD9:%.*]] +; CHECK: body2.thread9: +; CHECK-NEXT: [[TMP1612:%.*]] = add i32 [[TMP165:%.*]], 1 +; CHECK-NEXT: br label [[LATCH1:%.*]] +; CHECK: body1: +; CHECK-NEXT: [[TMP12:%.*]] = icmp sgt i32 [[TMP165]], 1 +; CHECK-NEXT: br i1 [[TMP12]], label [[BODY2_THREAD:%.*]], label [[HEAD1_THREAD:%.*]] +; CHECK: body2.thread: +; CHECK-NEXT: [[TMP163:%.*]] = add i32 [[TMP165]], 1 +; CHECK-NEXT: br label [[LATCH1]] +; CHECK: body2: +; CHECK-NEXT: [[TMP14:%.*]] = phi i32 [ 0, [[HEAD1:%.*]] ] +; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ 0, [[HEAD1]] ] +; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP14]], 1 +; CHECK-NEXT: br i1 [[ARG2]], label [[EXIT]], label [[LATCH1]] +; CHECK: latch1: +; CHECK-NEXT: [[TMP165]] = phi i32 [ [[TMP163]], [[BODY2_THREAD]] ], [ [[TMP16]], [[BODY2]] ], [ [[TMP1612]], [[BODY2_THREAD9]] ] +; CHECK-NEXT: [[TMP154:%.*]] = phi i32 [ [[TMP165]], [[BODY2_THREAD]] ], [ [[TMP15]], [[BODY2]] ], [ [[TMP165]], [[BODY2_THREAD9]] ] +; CHECK-NEXT: [[TMP18:%.*]] = icmp sgt i32 [[TMP165]], [[N]] +; CHECK-NEXT: br i1 [[TMP18]], label [[EXIT]], label [[BODY1:%.*]] +; CHECK: exit: +; CHECK-NEXT: [[RC:%.*]] = phi i32 [ [[TMP15]], [[BODY2]] ], [ [[TMP154]], [[LATCH1]] ], [ -1, [[HEAD1]] ], [ -1, [[HEAD1_THREAD]] ] +; CHECK-NEXT: ret i32 [[RC]] +; entry: br label %head1 diff --git a/llvm/test/Transforms/JumpThreading/unreachable-loops.ll b/llvm/test/Transforms/JumpThreading/unreachable-loops.ll index 8d649761700a..7b0dc4ad3ae7 100644 --- a/llvm/test/Transforms/JumpThreading/unreachable-loops.ll +++ b/llvm/test/Transforms/JumpThreading/unreachable-loops.ll @@ -15,8 +15,8 @@ define void @unreachable_single_bb_loop() { ; CHECK: bb2: ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP]], 1 ; CHECK-NEXT: switch i1 [[TMP4]], label [[BB2:%.*]] [ -; CHECK-NEXT: i1 false, label [[BB8]] -; CHECK-NEXT: i1 true, label [[BB8]] +; CHECK-NEXT: i1 false, label [[BB8]] +; CHECK-NEXT: i1 true, label [[BB8]] ; CHECK-NEXT: ] ; CHECK: bb8: ; CHECK-NEXT: ret void @@ -57,8 +57,8 @@ define void @unreachable_multi_bbs_loop() { ; CHECK: bb2: ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP]], 1 ; CHECK-NEXT: switch i1 [[TMP4]], label [[BB3:%.*]] [ -; CHECK-NEXT: i1 false, label [[BB8]] -; CHECK-NEXT: i1 true, label [[BB8]] +; CHECK-NEXT: i1 false, label [[BB8]] +; CHECK-NEXT: i1 true, label [[BB8]] ; CHECK-NEXT: ] ; CHECK: bb8: ; CHECK-NEXT: ret void -- GitLab From 7c00a5be5cdeb34711a546054ba0aa89c26d14eb Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 9 Jan 2024 15:09:01 +0100 Subject: [PATCH 202/652] [PhaseOrdering] Regenerate test checks (NFC) --- .../constraint-elimination-placement.ll | 6 +- .../PhaseOrdering/SystemZ/sub-xor.ll | 84 +++++++++---------- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll index ad4d4cf28ace..335a850f1ec6 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll @@ -100,9 +100,9 @@ define void @test2(ptr %this) #0 { ; CHECK-NEXT: [[CALL2_I_I:%.*]] = load i64, ptr inttoptr (i64 8 to ptr), align 8 ; CHECK-NEXT: [[COND_I_I:%.*]] = select i1 [[CALL1_I_I]], i64 [[CALL2_I_I]], i64 0 ; CHECK-NEXT: switch i64 [[COND_I_I]], label [[COMMON_RET:%.*]] [ -; CHECK-NEXT: i64 11, label [[IF_END_I:%.*]] -; CHECK-NEXT: i64 13, label [[TEST2_FN2_EXIT12:%.*]] -; CHECK-NEXT: i64 17, label [[IF_END_I31:%.*]] +; CHECK-NEXT: i64 11, label [[IF_END_I:%.*]] +; CHECK-NEXT: i64 13, label [[TEST2_FN2_EXIT12:%.*]] +; CHECK-NEXT: i64 17, label [[IF_END_I31:%.*]] ; CHECK-NEXT: ] ; CHECK: if.end.i: ; CHECK-NEXT: [[CALL8_I_I:%.*]] = tail call fastcc noundef i32 @test2_fn6() diff --git a/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll b/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll index 20fc7c2a7e53..5fe267d62f93 100644 --- a/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll +++ b/llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll @@ -23,32 +23,32 @@ define dso_local zeroext i32 @foo(ptr noundef %a) #0 { ; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG]] ; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ADD_PTR]], align 4, !tbaa [[TBAA3:![0-9]+]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[SUM_11]] -; CHECK-NEXT: [[IDX_NEG_19:%.*]] = xor i64 [[INDVARS_IV]], -1 -; CHECK-NEXT: [[ADD_PTR_110:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_19]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_NEG:%.*]] = xor i64 [[INDVARS_IV]], -1 +; CHECK-NEXT: [[ADD_PTR_110:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_NEG]] ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ADD_PTR_110]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[ADD_111:%.*]] = add i32 [[TMP1]], [[ADD]] -; CHECK-NEXT: [[IDX_NEG_216:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV]] -; CHECK-NEXT: [[ADD_PTR_217:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_216]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_112_NEG:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV]] +; CHECK-NEXT: [[ADD_PTR_217:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_112_NEG]] ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ADD_PTR_217]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[ADD_218:%.*]] = add i32 [[TMP2]], [[ADD_111]] -; CHECK-NEXT: [[IDX_NEG_3:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV]] -; CHECK-NEXT: [[ADD_PTR_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_3]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_219_NEG:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV]] +; CHECK-NEXT: [[ADD_PTR_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_219_NEG]] ; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ADD_PTR_3]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[TMP3]], [[ADD_218]] -; CHECK-NEXT: [[IDX_NEG_4:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV]] -; CHECK-NEXT: [[ADD_PTR_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_4]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_3_NEG:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV]] +; CHECK-NEXT: [[ADD_PTR_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_3_NEG]] ; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ADD_PTR_4]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[ADD_4:%.*]] = add i32 [[TMP4]], [[ADD_3]] -; CHECK-NEXT: [[IDX_NEG_5:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV]] -; CHECK-NEXT: [[ADD_PTR_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_5]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_4_NEG:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV]] +; CHECK-NEXT: [[ADD_PTR_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_4_NEG]] ; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ADD_PTR_5]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[ADD_5:%.*]] = add i32 [[TMP5]], [[ADD_4]] -; CHECK-NEXT: [[IDX_NEG_6:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV]] -; CHECK-NEXT: [[ADD_PTR_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_6]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_5_NEG:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV]] +; CHECK-NEXT: [[ADD_PTR_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_5_NEG]] ; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ADD_PTR_6]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[ADD_6:%.*]] = add i32 [[TMP6]], [[ADD_5]] -; CHECK-NEXT: [[IDX_NEG_7:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV]] -; CHECK-NEXT: [[ADD_PTR_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_7]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_6_NEG:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV]] +; CHECK-NEXT: [[ADD_PTR_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_6_NEG]] ; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ADD_PTR_7]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[ADD_7]] = add i32 [[TMP7]], [[ADD_6]] ; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV]], 8 @@ -60,32 +60,32 @@ define dso_local zeroext i32 @foo(ptr noundef %a) #0 { ; CHECK-NEXT: [[IDX_NEG_1:%.*]] = sub nsw i64 0, [[INDVARS_IV_1]] ; CHECK-NEXT: [[ADD_PTR_1:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1]] ; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ADD_PTR_1]], align 4, !tbaa [[TBAA3]] -; CHECK-NEXT: [[IDX_NEG_1_1:%.*]] = xor i64 [[INDVARS_IV_1]], -1 -; CHECK-NEXT: [[ADD_PTR_1_1:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_1]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_1_NEG:%.*]] = xor i64 [[INDVARS_IV_1]], -1 +; CHECK-NEXT: [[ADD_PTR_1_1:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_1_NEG]] ; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ADD_PTR_1_1]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] -; CHECK-NEXT: [[IDX_NEG_1_2:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_1]] -; CHECK-NEXT: [[ADD_PTR_1_2:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_2]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_1_1_NEG:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_1]] +; CHECK-NEXT: [[ADD_PTR_1_2:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_1_1_NEG]] ; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ADD_PTR_1_2]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] -; CHECK-NEXT: [[IDX_NEG_1_3:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_1]] -; CHECK-NEXT: [[ADD_PTR_1_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_3]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_1_2_NEG:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_1]] +; CHECK-NEXT: [[ADD_PTR_1_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_1_2_NEG]] ; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ADD_PTR_1_3]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] -; CHECK-NEXT: [[IDX_NEG_1_4:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_1]] -; CHECK-NEXT: [[ADD_PTR_1_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_4]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_1_3_NEG:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_1]] +; CHECK-NEXT: [[ADD_PTR_1_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_1_3_NEG]] ; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ADD_PTR_1_4]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP14]], [[TMP15]] -; CHECK-NEXT: [[IDX_NEG_1_5:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_1]] -; CHECK-NEXT: [[ADD_PTR_1_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_5]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_1_4_NEG:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_1]] +; CHECK-NEXT: [[ADD_PTR_1_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_1_4_NEG]] ; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ADD_PTR_1_5]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP16]], [[TMP17]] -; CHECK-NEXT: [[IDX_NEG_1_6:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_1]] -; CHECK-NEXT: [[ADD_PTR_1_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_6]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_1_5_NEG:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_1]] +; CHECK-NEXT: [[ADD_PTR_1_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_1_5_NEG]] ; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[ADD_PTR_1_6]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP18]], [[TMP19]] -; CHECK-NEXT: [[IDX_NEG_1_7:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_1]] -; CHECK-NEXT: [[ADD_PTR_1_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_7]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_1_6_NEG:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_1]] +; CHECK-NEXT: [[ADD_PTR_1_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_1_6_NEG]] ; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[ADD_PTR_1_7]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP20]], [[TMP21]] ; CHECK-NEXT: [[TMP23:%.*]] = shl i32 [[TMP22]], 1 @@ -101,38 +101,38 @@ define dso_local zeroext i32 @foo(ptr noundef %a) #0 { ; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[ADD_PTR_2]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[TMP24]], 3 ; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[MUL_2]], [[SUM_11_2]] -; CHECK-NEXT: [[IDX_NEG_2_1:%.*]] = xor i64 [[INDVARS_IV_2]], -1 -; CHECK-NEXT: [[ADD_PTR_2_1:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_1]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_2_NEG:%.*]] = xor i64 [[INDVARS_IV_2]], -1 +; CHECK-NEXT: [[ADD_PTR_2_1:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_2_NEG]] ; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[ADD_PTR_2_1]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2_1:%.*]] = mul i32 [[TMP25]], 3 ; CHECK-NEXT: [[ADD_2_1:%.*]] = add i32 [[MUL_2_1]], [[ADD_2]] -; CHECK-NEXT: [[IDX_NEG_2_2:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_2]] -; CHECK-NEXT: [[ADD_PTR_2_2:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_2]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_2_1_NEG:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_2]] +; CHECK-NEXT: [[ADD_PTR_2_2:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_2_1_NEG]] ; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[ADD_PTR_2_2]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2_2:%.*]] = mul i32 [[TMP26]], 3 ; CHECK-NEXT: [[ADD_2_2:%.*]] = add i32 [[MUL_2_2]], [[ADD_2_1]] -; CHECK-NEXT: [[IDX_NEG_2_3:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_2]] -; CHECK-NEXT: [[ADD_PTR_2_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_3]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_2_2_NEG:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_2]] +; CHECK-NEXT: [[ADD_PTR_2_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_2_2_NEG]] ; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[ADD_PTR_2_3]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2_3:%.*]] = mul i32 [[TMP27]], 3 ; CHECK-NEXT: [[ADD_2_3:%.*]] = add i32 [[MUL_2_3]], [[ADD_2_2]] -; CHECK-NEXT: [[IDX_NEG_2_4:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_2]] -; CHECK-NEXT: [[ADD_PTR_2_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_4]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_2_3_NEG:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_2]] +; CHECK-NEXT: [[ADD_PTR_2_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_2_3_NEG]] ; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[ADD_PTR_2_4]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2_4:%.*]] = mul i32 [[TMP28]], 3 ; CHECK-NEXT: [[ADD_2_4:%.*]] = add i32 [[MUL_2_4]], [[ADD_2_3]] -; CHECK-NEXT: [[IDX_NEG_2_5:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_2]] -; CHECK-NEXT: [[ADD_PTR_2_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_5]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_2_4_NEG:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_2]] +; CHECK-NEXT: [[ADD_PTR_2_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_2_4_NEG]] ; CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[ADD_PTR_2_5]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2_5:%.*]] = mul i32 [[TMP29]], 3 ; CHECK-NEXT: [[ADD_2_5:%.*]] = add i32 [[MUL_2_5]], [[ADD_2_4]] -; CHECK-NEXT: [[IDX_NEG_2_6:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_2]] -; CHECK-NEXT: [[ADD_PTR_2_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_6]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_2_5_NEG:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_2]] +; CHECK-NEXT: [[ADD_PTR_2_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_2_5_NEG]] ; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[ADD_PTR_2_6]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2_6:%.*]] = mul i32 [[TMP30]], 3 ; CHECK-NEXT: [[ADD_2_6:%.*]] = add i32 [[MUL_2_6]], [[ADD_2_5]] -; CHECK-NEXT: [[IDX_NEG_2_7:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_2]] -; CHECK-NEXT: [[ADD_PTR_2_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_7]] +; CHECK-NEXT: [[INDVARS_IV_NEXT_2_6_NEG:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_2]] +; CHECK-NEXT: [[ADD_PTR_2_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[INDVARS_IV_NEXT_2_6_NEG]] ; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[ADD_PTR_2_7]], align 4, !tbaa [[TBAA3]] ; CHECK-NEXT: [[MUL_2_7:%.*]] = mul i32 [[TMP31]], 3 ; CHECK-NEXT: [[ADD_2_7]] = add i32 [[MUL_2_7]], [[ADD_2_6]] -- GitLab From 2d54ec36f762a081c9f17cacd3407cc6f35622b1 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Tue, 9 Jan 2024 14:27:07 +0000 Subject: [PATCH 203/652] [SelectionDAG] Add and use SDNode::getAsAPIntVal() helper (#77455) This is the logical equivalent for #76710 for APInt and uses the same naming scheme. Converted existing users through: `git grep -l "cast\(.*\).*getAPIntValueValue" | xargs sed -E -i 's/cast\((.*)\)->getAPIntValue/\1->getAsAPIntVal/'` --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 7 +++++++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 18 +++++++++--------- .../SelectionDAG/LegalizeVectorTypes.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 ++++++------ .../CodeGen/SelectionDAG/TargetLowering.cpp | 5 ++--- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +++---- .../lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++--- llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 2 +- 12 files changed, 36 insertions(+), 31 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index ebf410cc94de..65b06d0f4579 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -935,6 +935,9 @@ public: /// Helper method returns the APInt of a ConstantSDNode operand. inline const APInt &getConstantOperandAPInt(unsigned Num) const; + /// Helper method returns the APInt value of a ConstantSDNode. + inline const APInt &getAsAPIntVal() const; + const SDValue &getOperand(unsigned Num) const { assert(Num < NumOperands && "Invalid child # of SDNode!"); return OperandList[Num]; @@ -1656,6 +1659,10 @@ const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const { return cast(getOperand(Num))->getAPIntValue(); } +const APInt &SDNode::getAsAPIntVal() const { + return cast(this)->getAPIntValue(); +} + class ConstantFPSDNode : public SDNode { friend class SelectionDAG; diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 2327664516cc..8b70148d8ce7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4380,7 +4380,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) { } else { N1IsConst = isa(N1); if (N1IsConst) { - ConstValue1 = cast(N1)->getAPIntValue(); + ConstValue1 = N1->getAsAPIntVal(); N1IsOpaqueConst = cast(N1)->isOpaque(); } } @@ -12087,8 +12087,8 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) { if (N1Elt.getValueType() != N2Elt.getValueType()) continue; - const APInt &C1 = cast(N1Elt)->getAPIntValue(); - const APInt &C2 = cast(N2Elt)->getAPIntValue(); + const APInt &C1 = N1Elt->getAsAPIntVal(); + const APInt &C2 = N2Elt->getAsAPIntVal(); if (C1 != C2 + 1) AllAddOne = false; if (C1 != C2 - 1) @@ -12764,7 +12764,7 @@ static SDValue tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI, SDLoc DL(Op); // Get the constant value and if needed trunc it to the size of the type. // Nodes like build_vector might have constants wider than the scalar type. - APInt C = cast(Op)->getAPIntValue().zextOrTrunc(EVTBits); + APInt C = Op->getAsAPIntVal().zextOrTrunc(EVTBits); if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT)); else @@ -17942,10 +17942,10 @@ SDValue DAGCombiner::rebuildSetCC(SDValue N) { SDValue AndOp1 = Op0.getOperand(1); if (AndOp1.getOpcode() == ISD::Constant) { - const APInt &AndConst = cast(AndOp1)->getAPIntValue(); + const APInt &AndConst = AndOp1->getAsAPIntVal(); if (AndConst.isPowerOf2() && - cast(Op1)->getAPIntValue() == AndConst.logBase2()) { + Op1->getAsAPIntVal() == AndConst.logBase2()) { SDLoc DL(N); return DAG.getSetCC(DL, getSetCCResultType(Op0.getValueType()), Op0, DAG.getConstant(0, DL, Op0.getValueType()), @@ -18266,7 +18266,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { auto *CN = cast(OtherUses[i]->getOperand(OffsetIdx)); const APInt &Offset0 = CN->getAPIntValue(); - const APInt &Offset1 = cast(Offset)->getAPIntValue(); + const APInt &Offset1 = Offset->getAsAPIntVal(); int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; int X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; @@ -19573,7 +19573,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { // Find the type to narrow it the load / op / store to. SDValue N1 = Value.getOperand(1); unsigned BitWidth = N1.getValueSizeInBits(); - APInt Imm = cast(N1)->getAPIntValue(); + APInt Imm = N1->getAsAPIntVal(); if (Opc == ISD::AND) Imm ^= APInt::getAllOnes(BitWidth); if (Imm == 0 || Imm.isAllOnes()) @@ -26543,7 +26543,7 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { APInt Bits; if (isa(Elt)) - Bits = cast(Elt)->getAPIntValue(); + Bits = Elt->getAsAPIntVal(); else if (isa(Elt)) Bits = cast(Elt)->getValueAPF().bitcastToAPInt(); else diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index ec74d2940099..c278bdc07360 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1854,7 +1854,7 @@ void DAGTypeLegalizer::SplitVecRes_STEP_VECTOR(SDNode *N, SDValue &Lo, // Hi = Lo + (EltCnt * Step) EVT EltVT = Step.getValueType(); - APInt StepVal = cast(Step)->getAPIntValue(); + APInt StepVal = Step->getAsAPIntVal(); SDValue StartOfHi = DAG.getVScale(dl, EltVT, StepVal * LoVT.getVectorMinNumElements()); StartOfHi = DAG.getSExtOrTrunc(StartOfHi, dl, HiVT.getVectorElementType()); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index b39be64c06f9..01d31806c844 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -327,7 +327,7 @@ bool ISD::isVectorShrinkable(const SDNode *N, unsigned NewEltSize, if (!isa(Op)) return false; - APInt C = cast(Op)->getAPIntValue().trunc(EltSize); + APInt C = Op->getAsAPIntVal().trunc(EltSize); if (Signed && C.trunc(NewEltSize).sext(EltSize) != C) return false; if (!Signed && C.trunc(NewEltSize).zext(EltSize) != C) @@ -7200,7 +7200,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, (N2VT.getVectorMinNumElements() + N3->getAsZExtVal()) <= VT.getVectorMinNumElements()) && "Insert subvector overflow!"); - assert(cast(N3)->getAPIntValue().getBitWidth() == + assert(N3->getAsAPIntVal().getBitWidth() == TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() && "Constant index for INSERT_SUBVECTOR has an invalid size"); @@ -9304,7 +9304,7 @@ SDValue SelectionDAG::getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, N->getValueType(0).getVectorElementCount()) && "Vector width mismatch between index and data"); assert(isa(N->getScale()) && - cast(N->getScale())->getAPIntValue().isPowerOf2() && + N->getScale()->getAsAPIntVal().isPowerOf2() && "Scale should be a constant power of 2"); CSEMap.InsertNode(N, IP); @@ -9348,7 +9348,7 @@ SDValue SelectionDAG::getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, N->getValue().getValueType().getVectorElementCount()) && "Vector width mismatch between index and data"); assert(isa(N->getScale()) && - cast(N->getScale())->getAPIntValue().isPowerOf2() && + N->getScale()->getAsAPIntVal().isPowerOf2() && "Scale should be a constant power of 2"); CSEMap.InsertNode(N, IP); @@ -9490,7 +9490,7 @@ SDValue SelectionDAG::getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, N->getValueType(0).getVectorElementCount()) && "Vector width mismatch between index and data"); assert(isa(N->getScale()) && - cast(N->getScale())->getAPIntValue().isPowerOf2() && + N->getScale()->getAsAPIntVal().isPowerOf2() && "Scale should be a constant power of 2"); CSEMap.InsertNode(N, IP); @@ -9536,7 +9536,7 @@ SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, N->getValue().getValueType().getVectorElementCount()) && "Vector width mismatch between index and data"); assert(isa(N->getScale()) && - cast(N->getScale())->getAPIntValue().isPowerOf2() && + N->getScale()->getAsAPIntVal().isPowerOf2() && "Scale should be a constant power of 2"); CSEMap.InsertNode(N, IP); diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index e3e3e375d6a6..3bbef6e6d85d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1108,7 +1108,7 @@ bool TargetLowering::SimplifyDemandedBits( if (Op.getOpcode() == ISD::Constant) { // We know all of the bits for a constant! - Known = KnownBits::makeConstant(cast(Op)->getAPIntValue()); + Known = KnownBits::makeConstant(Op->getAsAPIntVal()); return false; } @@ -6350,8 +6350,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, LeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros(); // UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros in // the dividend exceeds the leading zeros for the divisor. - LeadingZeros = std::min( - LeadingZeros, cast(N1)->getAPIntValue().countl_zero()); + LeadingZeros = std::min(LeadingZeros, N1->getAsAPIntVal().countl_zero()); } bool UseNPQ = false, UsePreShift = false, UsePostShift = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 719ae2e8750c..119aa80b9bb5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -2483,7 +2483,7 @@ void AMDGPUDAGToDAGISel::SelectDSAppendConsume(SDNode *N, unsigned IntrID) { SDValue PtrBase = Ptr.getOperand(0); SDValue PtrOffset = Ptr.getOperand(1); - const APInt &OffsetVal = cast(PtrOffset)->getAPIntValue(); + const APInt &OffsetVal = PtrOffset->getAsAPIntVal(); if (isDSOffsetLegal(PtrBase, OffsetVal.getZExtValue())) { N = glueCopyToM0(N, PtrBase); Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i32); diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index c65090d915ef..407cd6c0f8be 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -2297,7 +2297,7 @@ SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op, if (VT == MVT::v2f16 || VT == MVT::v2bf16) Value = cast(Operand)->getValueAPF().bitcastToAPInt(); else if (VT == MVT::v2i16 || VT == MVT::v4i8) - Value = cast(Operand)->getAPIntValue(); + Value = Operand->getAsAPIntVal(); else llvm_unreachable("Unsupported type"); // i8 values are carried around as i16, so we need to zero out upper bits, diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 235df1880b37..4e164fda1d8d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -16241,7 +16241,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, // Since we are doing this pre-legalize, the RHS can be a constant of // arbitrary bitwidth which may cause issues when trying to get the value // from the underlying APInt. - auto RHSAPInt = cast(RHS)->getAPIntValue(); + auto RHSAPInt = RHS->getAsAPIntVal(); if (!RHSAPInt.isIntN(64)) break; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 0a1a466af591..b4abebc27eed 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -7023,8 +7023,7 @@ foldBinOpIntoSelectIfProfitable(SDNode *BO, SelectionDAG &DAG, if (!NewConstOp) return SDValue(); - const APInt &NewConstAPInt = - cast(NewConstOp)->getAPIntValue(); + const APInt &NewConstAPInt = NewConstOp->getAsAPIntVal(); if (!NewConstAPInt.isZero() && !NewConstAPInt.isAllOnes()) return SDValue(); @@ -7154,8 +7153,8 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { // is SETGE/SETLE to avoid an XORI. if (isa(TrueV) && isa(FalseV) && CCVal == ISD::SETLT) { - const APInt &TrueVal = cast(TrueV)->getAPIntValue(); - const APInt &FalseVal = cast(FalseV)->getAPIntValue(); + const APInt &TrueVal = TrueV->getAsAPIntVal(); + const APInt &FalseVal = FalseV->getAsAPIntVal(); if (TrueVal - 1 == FalseVal) return DAG.getNode(ISD::ADD, DL, VT, CondV, FalseV); if (TrueVal + 1 == FalseVal) diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 320f91c76057..815eca1240d8 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -1649,7 +1649,7 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) { } } if (Node->getValueType(0) == MVT::i128) { - const APInt &Val = cast(Node)->getAPIntValue(); + const APInt &Val = Node->getAsAPIntVal(); SystemZVectorConstantInfo VCI(Val); if (VCI.isVectorConstantLegal(*Subtarget)) { loadVectorConstant(VCI, Node); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5a28240ea9e2..25c4e02abc2e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -22551,7 +22551,7 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, // FIXME: Do this for non-constant compares for constant on LHS? if (CmpVT == MVT::i64 && isa(Op1) && !isX86CCSigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. - cast(Op1)->getAPIntValue().getActiveBits() <= 32 && + Op1->getAsAPIntVal().getActiveBits() <= 32 && DAG.MaskedValueIsZero(Op0, APInt::getHighBitsSet(64, 32))) { CmpVT = MVT::i32; Op0 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op0); @@ -47029,8 +47029,8 @@ static SDValue combineShiftRightArithmetic(SDNode *N, SelectionDAG &DAG, SDValue N00 = N0.getOperand(0); SDValue N01 = N0.getOperand(1); - APInt ShlConst = (cast(N01))->getAPIntValue(); - APInt SarConst = (cast(N1))->getAPIntValue(); + APInt ShlConst = N01->getAsAPIntVal(); + APInt SarConst = N1->getAsAPIntVal(); EVT CVT = N1.getValueType(); if (SarConst.isNegative()) diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp index e481f7e38e6a..f88e25ea1d16 100644 --- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -1368,7 +1368,7 @@ std::string TreePredicateFn::getCodeToRunOnSDNode() const { if (immCodeUsesAPFloat()) Result += "cast(Node)->getValueAPF();\n"; else if (immCodeUsesAPInt()) - Result += "cast(Node)->getAPIntValue();\n"; + Result += "Node->getAsAPIntVal();\n"; else Result += "cast(Node)->getSExtValue();\n"; return Result + ImmCode; -- GitLab From a2dba0c97756c65c7dd9d91bec2ceda80a933bb1 Mon Sep 17 00:00:00 2001 From: HaohaiWen Date: Tue, 9 Jan 2024 22:30:13 +0800 Subject: [PATCH 204/652] [SEH][CodeGen] Add test to track CFG optimization bug for SEH (#77441) LiveDebugValues requires CFG only has one entry. BranchFolding and MachineBlockPlacement may remove all predecessors of landing pad which leaves it to be another entry. --- .../X86/windows-seh-EHa-PreserveCFG.ll | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll diff --git a/llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll b/llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll new file mode 100644 index 000000000000..bd6743f7c414 --- /dev/null +++ b/llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll @@ -0,0 +1,81 @@ +; XFAIL: * +; RUN: llc -mtriple=x86_64-pc-windows-msvc %s +define dso_local void @main(ptr %addr, ptr %src, ptr %dst) personality ptr @__CxxFrameHandler3 !dbg !11 { +entry: + %tmp0 = load float, ptr %src + %src1 = getelementptr inbounds float, ptr %src, i64 1 + %tmp1 = load float, ptr %src1 + %src2 = getelementptr inbounds float, ptr %src, i64 2 + %tmp2 = load float, ptr %src2 + %src3 = getelementptr inbounds float, ptr %src, i64 3 + %tmp3 = load float, ptr %src3 + %src4 = getelementptr inbounds float, ptr %src, i64 4 + %tmp4 = load float, ptr %src4 + %src5 = getelementptr inbounds float, ptr %src, i64 5 + %tmp5 = load float, ptr %src5 + %src6 = getelementptr inbounds float, ptr %src, i64 6 + %tmp6 = load float, ptr %src6 + invoke void @foo(ptr %addr) + to label %scope_begin unwind label %ehcleanup1, !dbg !13 + +scope_begin: + invoke void @llvm.seh.scope.begin() + to label %scope_end unwind label %ehcleanup, !dbg !13 + +scope_end: + invoke void @llvm.seh.scope.end() + to label %finish unwind label %ehcleanup, !dbg !13 + +ehcleanup: + %0 = cleanuppad within none [], !dbg !13 + call void @llvm.dbg.value(metadata ptr %addr, metadata !12, metadata !DIExpression()), !dbg !13 + call void @foo(ptr %addr) [ "funclet"(token %0) ], !dbg !13 + cleanupret from %0 unwind label %ehcleanup1, !dbg !13 + +ehcleanup1: + %1 = cleanuppad within none [], !dbg !13 + call void @foo(ptr %addr) [ "funclet"(token %1) ], !dbg !13 + cleanupret from %1 unwind to caller, !dbg !13 + +finish: + store float %tmp0, ptr %dst + %dst1 = getelementptr inbounds float, ptr %dst, i64 1 + store float %tmp1, ptr %dst1 + %dst2 = getelementptr inbounds float, ptr %dst, i64 2 + store float %tmp2, ptr %dst2 + %dst3 = getelementptr inbounds float, ptr %dst, i64 3 + store float %tmp3, ptr %dst3 + %dst4 = getelementptr inbounds float, ptr %dst, i64 4 + store float %tmp4, ptr %dst4 + %dst5 = getelementptr inbounds float, ptr %dst, i64 5 + store float %tmp5, ptr %dst5 + %dst6 = getelementptr inbounds float, ptr %dst, i64 6 + store float %tmp6, ptr %dst6 + ret void +} + +declare dso_local void @llvm.seh.scope.begin() +declare dso_local void @llvm.seh.scope.end() +declare dso_local i32 @__CxxFrameHandler3(...) +declare dso_local void @foo(ptr %addr) +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.module.flags = !{!0, !1, !2, !3} +!llvm.dbg.cu = !{!14} + +!0 = !{i32 2, !"eh-asynch", i32 1} +!1 = !{i32 2, !"CodeView", i32 1} +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 7, !"uwtable", i32 2} + +!4 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +!5 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64) +!6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !6, size: 64) +!8 = !DISubroutineType(types: !9) +!9 = !{null, !7, !5, !5} +!10 = !DIFile(filename: "c:/main.cpp", directory: "") +!11 = distinct !DISubprogram(name: "main", scope: !10, file: !10, line: 5, type: !8, scopeLine: 11, unit: !14) +!12 = !DILocalVariable(name: "addr", scope: !11, file: !10, line: 5, type: !7) +!13 = !DILocation(line: 7, scope: !11) +!14 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !10, isOptimized: true, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -- GitLab From 06286a553280fc843d6f5df477a2c776aa2ece35 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Tue, 9 Jan 2024 17:55:21 +0300 Subject: [PATCH 205/652] [GISel] Add RegState::Define to temporary defs in apply patterns (#77425) Previously, registers created for temporary defs in apply patterns were rendered as uses, resulting in machine verifier errors. --- .../builtins/match-table-replacerreg.td | 20 +++---- .../match-table-operand-types.td | 8 +-- .../match-table-temp-defs.td | 56 +++++++++++++++++++ .../match-table-typeof.td | 8 +-- .../TableGen/GlobalISelCombinerEmitter.cpp | 2 +- 5 files changed, 75 insertions(+), 19 deletions(-) create mode 100644 llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td index f4f1faf7cc6d..38ee0166b869 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td @@ -28,11 +28,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(65), GIMT_Encode2(181), /*)*//*default:*//*Label 2*/ GIMT_Encode4(556), +// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(65), GIMT_Encode2(181), /*)*//*default:*//*Label 2*/ GIMT_Encode4(558), // CHECK-NEXT: /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ GIMT_Encode4(474), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), -// CHECK-NEXT: /*TargetOpcode::G_FNEG*//*Label 1*/ GIMT_Encode4(524), +// CHECK-NEXT: /*TargetOpcode::G_FNEG*//*Label 1*/ GIMT_Encode4(526), // CHECK-NEXT: // Label 0: @474 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(523), // Rule ID 1 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(525), // Rule ID 1 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: // MIs[0] a @@ -52,15 +52,15 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // Combiner Rule #1: ReplaceTemp // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a -// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @523 +// CHECK-NEXT: // Label 3: @525 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @524 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(555), // Rule ID 0 // +// CHECK-NEXT: // Label 1: @526 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(557), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -75,10 +75,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_ReplaceReg, /*OldInsnID*/0, /*OldOpIdx*/0, /*NewInsnId*/1, /*NewOpIdx*/1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @555 +// CHECK-NEXT: // Label 4: @557 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 2: @556 +// CHECK-NEXT: // Label 2: @558 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 557 bytes +// CHECK-NEXT: }; // Size: 559 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td index 06368db75e3b..a441b0e01ebe 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td @@ -21,7 +21,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(79), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(81), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s8, @@ -36,7 +36,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, // CHECK-NEXT: // Combiner Rule #0: InstTest0 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), -// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, @@ -45,8 +45,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @79 +// CHECK-NEXT: // Label 0: @81 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; +// CHECK-NEXT: }; // Size: 82 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td new file mode 100644 index 000000000000..4e473355e14c --- /dev/null +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td @@ -0,0 +1,56 @@ +// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \ +// RUN: -combiners=MyCombiner %s | FileCheck %s + +// Checks that temporary registers defined in apply patterns +// are emitted with RegState::Define. + +include "llvm/Target/Target.td" +include "llvm/Target/GlobalISel/Combine.td" + +def MyTargetISA : InstrInfo; +def MyTarget : Target { let InstructionSet = MyTargetISA; } + +def Test0 : GICombineRule< + (defs root:$dst), + (match (G_ADD $dst, $lhs, $rhs)), + (apply (G_UDIVREM $tmp, $dst, $lhs, $rhs)) +>; + +def Test1 : GICombineRule< + (defs root:$dst), + (match (G_ADD $dst, $lhs, $rhs)), + (apply (G_UDIVREM $dst, $tmp, $lhs, $rhs)) +>; + +def Test2 : GICombineRule< + (defs root:$dst), + (match (G_ADD $dst, $lhs, $rhs)), + (apply (G_ADD $tmp, 0, $lhs), + (G_ADD $dst, $tmp, $rhs)) +>; + +def MyCombiner: GICombiner<"GenMyCombiner", [ + Test0, + Test1, + Test2, +]>; + +// CHECK: // Combiner Rule #0: Test0 +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // lhs +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rhs + +// CHECK: // Combiner Rule #1: Test1 +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // lhs +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rhs + +// CHECK: // Combiner Rule #2: Test2 +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // lhs diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td index 3cffee7ab581..d8921df638fb 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td @@ -16,7 +16,7 @@ def Test0 : GICombineRule< // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(75), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(77), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] dst @@ -30,7 +30,7 @@ def Test0 : GICombineRule< // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/uint8_t(-1), // CHECK-NEXT: // Combiner Rule #0: Test0 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), -// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/uint8_t(-2), /*Imm*/GIMT_Encode8(42), // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB), @@ -38,9 +38,9 @@ def Test0 : GICombineRule< // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @75 +// CHECK-NEXT: // Label 0: @77 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 76 bytes +// CHECK-NEXT: }; // Size: 78 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp index 348b3b3e0898..c092772386ec 100644 --- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp @@ -2318,7 +2318,7 @@ bool CombineRuleBuilder::emitInstructionApplyPattern( M.actions_begin(), getLLTCodeGenOrTempType(Ty, M), TempRegID); } - DstMI.addRenderer(TempRegID); + DstMI.addRenderer(TempRegID, /*IsDef=*/true); } // Render MIFlags -- GitLab From e9ac2dc68d0b0578a5c1a98b4e083d133c1d7b2b Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Jan 2024 15:08:25 +0000 Subject: [PATCH 206/652] [DAG] XformToShuffleWithZero - use dyn_cast instead of isa/cast pair. NFCI. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8b70148d8ce7..58c8ccfb63ea 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -26542,10 +26542,10 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { } APInt Bits; - if (isa(Elt)) - Bits = Elt->getAsAPIntVal(); - else if (isa(Elt)) - Bits = cast(Elt)->getValueAPF().bitcastToAPInt(); + if (auto *Cst = dyn_cast(Elt)) + Bits = Cst->getAPIntValue(); + else if (auto *CstFP = dyn_cast(Elt)) + Bits = CstFP->getValueAPF().bitcastToAPInt(); else return SDValue(); -- GitLab From db1d9ad109d8e0f17acb2de60c8b57085fe2de77 Mon Sep 17 00:00:00 2001 From: Sameer Sahasrabuddhe Date: Tue, 9 Jan 2024 21:01:48 +0530 Subject: [PATCH 207/652] [llvm/unittests] Reset the IsSSA property when using finalizeBundle() (#77469) --- llvm/unittests/MI/LiveIntervalTest.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp index 1fd1c78a5e55..edc4baa6bfec 100644 --- a/llvm/unittests/MI/LiveIntervalTest.cpp +++ b/llvm/unittests/MI/LiveIntervalTest.cpp @@ -156,6 +156,7 @@ static void testHandleMoveIntoNewBundle(MachineFunction &MF, LiveIntervals &LIS, // Build bundle finalizeBundle(MBB, I, std::next(ToInstr.getIterator())); + MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA); // Update LiveIntervals MachineBasicBlock::instr_iterator BundleStart = std::prev(I); -- GitLab From 0242d27dc89ff19e331ae4945933cdb360c7d4cf Mon Sep 17 00:00:00 2001 From: Pradeep Kumar Date: Tue, 9 Jan 2024 21:01:51 +0530 Subject: [PATCH 208/652] [MLIR][NVVM] Add missing `;` when lowering stmatrix Op (#77471) --- mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 4 ++-- mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td index 52857164ffaf..3a6c6e5438c6 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td @@ -1345,8 +1345,8 @@ def NVVM_StMatrixOp: NVVM_PTXBuilder_Op<"stmatrix">, ptx += ".x" + std::to_string(d); if (getLayout() == NVVM::MMALayout::col) ptx += ".trans"; - if(d == 1) ptx += ".m8n8.shared.b16 [%0], {%1}"; - if(d == 2) ptx += ".m8n8.shared.b16 [%0], {%1, %2}"; + if(d == 1) ptx += ".m8n8.shared.b16 [%0], {%1};"; + if(d == 2) ptx += ".m8n8.shared.b16 [%0], {%1, %2};"; if(d == 4) ptx += ".m8n8.shared.b16 [%0], {%1, %2, %3, %4};"; return ptx; } diff --git a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir index 74186138c3a9..7e08ec6ffcbd 100644 --- a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir +++ b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir @@ -599,11 +599,11 @@ func.func @elect_one_leader_sync() { // CHECK-SAME: %[[arg3:[a-zA-Z0-9_]+]]: i32, // CHECK-SAME: %[[arg4:[a-zA-Z0-9_]+]]: i32) llvm.func @stmatrix(%arg0 : !llvm.ptr<3>, %m1 : i32, %m2 : i32, %m3 : i32, %m4 : i32) { -// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x1.m8n8.shared.b16 [$0], {$1}", "r,r" %[[arg0]], %[[arg1]] : (!llvm.ptr<3>, i32) -> () -// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x2.m8n8.shared.b16 [$0], {$1, $2}", "r,r,r" %[[arg0]], %[[arg1]], %[[arg2]] : (!llvm.ptr<3>, i32, i32) -> () +// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x1.m8n8.shared.b16 [$0], {$1};", "r,r" %[[arg0]], %[[arg1]] : (!llvm.ptr<3>, i32) -> () +// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x2.m8n8.shared.b16 [$0], {$1, $2};", "r,r,r" %[[arg0]], %[[arg1]], %[[arg2]] : (!llvm.ptr<3>, i32, i32) -> () // CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x4.m8n8.shared.b16 [$0], {$1, $2, $3, $4};", "r,r,r,r,r" %[[arg0]], %[[arg1]], %[[arg2]], %[[arg3]], %[[arg4]] : (!llvm.ptr<3>, i32, i32, i32, i32) -> () -// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x1.trans.m8n8.shared.b16 [$0], {$1}", "r,r" %[[arg0]], %[[arg1]] : (!llvm.ptr<3>, i32) -> () -// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x2.trans.m8n8.shared.b16 [$0], {$1, $2}", "r,r,r" %[[arg0]], %[[arg1]], %[[arg2]] : (!llvm.ptr<3>, i32, i32) -> () +// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x1.trans.m8n8.shared.b16 [$0], {$1};", "r,r" %[[arg0]], %[[arg1]] : (!llvm.ptr<3>, i32) -> () +// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x2.trans.m8n8.shared.b16 [$0], {$1, $2};", "r,r,r" %[[arg0]], %[[arg1]], %[[arg2]] : (!llvm.ptr<3>, i32, i32) -> () // CHECK: llvm.inline_asm has_side_effects asm_dialect = att "stmatrix.sync.aligned.x4.trans.m8n8.shared.b16 [$0], {$1, $2, $3, $4};", "r,r,r,r,r" %[[arg0]], %[[arg1]], %[[arg2]], %[[arg3]], %[[arg4]] : (!llvm.ptr<3>, i32, i32, i32, i32) -> () nvvm.stmatrix %arg0, %m1 {layout = #nvvm.mma_layout} : !llvm.ptr<3>, i32 nvvm.stmatrix %arg0, %m1, %m2 {layout = #nvvm.mma_layout} : !llvm.ptr<3>, i32, i32 -- GitLab From ab4af25d5dfaecf01e6c6e94dc79e7304321c376 Mon Sep 17 00:00:00 2001 From: Razvan Lupusoru Date: Tue, 9 Jan 2024 07:33:11 -0800 Subject: [PATCH 209/652] [acc] OpenACC dialect design philosophy and details (#75548) This document captures the design philosophy of the acc dialect. It also shares the rationale behind the design and implementation of various operations - and ties that back to the dialect design goals. Co-authored-by: Valentin Clement Co-authored-by: Slava Zakharin --- mlir/docs/Dialects/OpenACC.md | 449 ++++++++++++++++++ .../mlir/Dialect/OpenACC/OpenACCBase.td | 8 +- 2 files changed, 450 insertions(+), 7 deletions(-) create mode 100755 mlir/docs/Dialects/OpenACC.md diff --git a/mlir/docs/Dialects/OpenACC.md b/mlir/docs/Dialects/OpenACC.md new file mode 100755 index 000000000000..da7d4be07e3e --- /dev/null +++ b/mlir/docs/Dialects/OpenACC.md @@ -0,0 +1,449 @@ +The `acc` dialect is an MLIR dialect for representing the OpenACC +programming model. OpenACC is a standardized directive-based model which +is used with C, C++, and Fortran to enable programmers to expose +parallelism in their code. The descriptive approach used by OpenACC +allows targeting of parallel multicore and accelerator targets like GPUs +by giving the compiler the freedom of how to parallelize for specific +architectures. OpenACC also provides the ability to optimize the +parallelism through increasingly more prescriptive clauses. + +This dialect models the constructs from the [OpenACC 3.3 specification] +(https://www.openacc.org/sites/default/files/inline-images/Specification/OpenACC-3.3-final.pdf) + +This document describes the design of the OpenACC dialect in MLIR. It +lists and explains design goals and design choices along with their +rationale. It also describes specifics with regards to acc dialect +operations, types, and attributes. + +[TOC] + +## Dialect Design Goals + +* Needs to have complete representation of the OpenACC language. + - A frontend requires this in order to properly generate a + representation of possible `acc` pragmas in MLIR. Additionally, + this dialect is expected to be further lowered when materializing + its semantics. Without a complete representation, a frontend might + choose a lower abstraction (such as direct runtime call) - but this + would impact the ability to do analysis and optimizations on the + dialect. +* Allow representation at the same semantic level as the OpenACC +language while having capability to represent nuances of the source +language semantics (such as Fortran descriptors) in an agnostic manner. + - Using abstractions that closely model the OpenACC language + simplifies frontend implementation. It also allows for easier + debugging of the IR. However, sometimes source language specific + behavior is needed when materializing OpenACC. In these cases, such + as privatization of C++ objects with default constructor, the + frontend fills in the `recipe` along with the `private` operation + which can be packaged neatly with the `acc` dialect operations. +* Be able to regenerate the semantic equivalent of the user pragmas from +the dialect (including bounds, names, clauses, modifiers, etc). + - This is a strong measure of making sure that the dialect is not + lossy in semantics. It also allows capability to generate + appropriate and useful debug information outside of the frontend. +* Be dialect agnostic so that it can be used and coexist with other +dialects including but not limited to `hlfir`, `fir`, `llvm`, `cir`. + - Directive-based models such as OpenACC are always used with a + source language, so the `acc` dialect coexisting with other + dialect(s) is necessary by construction. Through proper + abstractions, neither the `acc` dialect nor the source language + dialect should have dependencies on each other; where needed, + interfaces should be used to ensure `acc` dialect can verify + expected properties. +* The dialect must allow dataflow to be modeled accurately and +performantly using MLIR's existing facilities. + - Appropriate dataflow modeling is important for analyses and IR + reasoning - even something as simple as walking the uses. Therefore + operations, like data operations, are expected to generate results + which can be used in modeling behavior. For example, consider an + `acc copyin` clause. After the `acc.copyin` operation, a pointer + which lives on devices should be distinguishable from one that lives + in host memory. +* Be friendly to MLIR optimization passes by implementing common +interfaces. + - Interfaces, such as `MemoryEffects`, are the key way MLIR + transformations and analyses are designed to interact with the IR. + In order for the operations in the `acc` dialect to be optimizable + (either directly or even indirectly by not blocking optimizations + of nested IR), implementing relevant common interfaces is needed. + +The design philosophy of the acc dialect is one where the design goals +are adhered to. Current and planned operations, attributes, types must +adhere to the design goals. + +## Operation Categories + +The OpenACC dialect includes both high-level operations (which retain +the same semantic meaning as their OpenACC language equivalent), +intermediate-level operations (which are used to decompose clauses +from constructs), and low-level operations (to encode specifics +associated with source language in a generic way). + +The high-level operations list contains the following OpenACC language +constructs and their corresponding operations: +* `acc parallel` → `acc.parallel` +* `acc kernels` → `acc.kernels` +* `acc serial` → `acc.serial` +* `acc data` → `acc.data` +* `acc loop` → `acc.loop` +* `acc enter data` → `acc.enter_data` +* `acc exit data` → `acc.exit_data` +* `acc host_data` → `acc.host_data` +* `acc init` → `acc.init` +* `acc shutdown` → `acc.shutdown` +* `acc update` → `acc.update` +* `acc set` → `acc.set` +* `acc wait` → `acc.wait` +* `acc atomic read` → `acc.atomic.read` +* `acc atomic write` → `acc.atomic.write` +* `acc atomic update` → `acc.atomic.update` +* `acc atomic capture` → `acc.atomic.capture` + +This second group contains operations which are used to represent +either decomposed constructs or clauses for more accurate modeling: +* `acc routine` → `acc.routine` + `acc.routine_info` attribute +* `acc declare` → `acc.declare_enter` + `acc.declare_exit` or +`acc.declare` +* `acc {construct} copyin` → `acc.copyin` (before region) + +`acc.delete` (after region) +* `acc {construct} copy` → `acc.copyin` (before region) + +`acc.copyout` (after region) +* `acc {construct} copyout` → `acc.create` (before region) + +`acc.copyout` (after region) +* `acc {construct} attach` → `acc.attach` (before region) + +`acc.detach` (after region) +* `acc {construct} create` → `acc.create` (before region) + +`acc.delete` (after region) +* `acc {construct} present` → `acc.present` (before region) + +`acc.delete` (after region) +* `acc {construct} no_create` → `acc.nocreate` (before region) + +`acc.delete` (after region) +* `acc {construct} deviceptr` → `acc.deviceptr` +* `acc {construct} private` → `acc.private` +* `acc {construct} firstprivate` → `acc.firstprivate` +* `acc {construct} reduction` → `acc.reduction` +* `acc cache` → `acc.cache` +* `acc update device` → `acc.update_device` +* `acc update host` → `acc.update_host` +* `acc host_data use_device` → `acc.use_device` +* `acc declare device_resident` → `acc.declare_device_resident` +* `acc declare link` → `acc.declare_link` +* `acc exit data delete` → `acc.delete` (with `structured` flag as +false) +* `acc exit data detach` → `acc.detach` (with `structured` flag as +false) +* `acc {construct} {data_clause}(var[lb:ub])` → `acc.bounds` + +The low-level operations are: +* `acc.private.recipe` +* `acc.reduction.recipe` +* `acc.firstprivate.recipe` +* `acc.global_ctor` +* `acc.global_dtor` +* `acc.yield` +* `acc.terminator` +The low-level operations semantics and reasoning are further explained +in sections below. + +### Data Operations + +#### Data Clause Decomposition +The data clauses are decomposed from their constructs for better +dataflow modeling in MLIR. There are multiple reasons for this which +are consistent with the dialect goals: +* Correctly represents dataflow. Data clauses have different effects +at entry to region and at exit from region. +* Friendlier to add attributes such as `MemoryEffects` to a single +operation. This can better reflect semantics (like the fact that an +`acc.copyin` operation only reads host memory) +* Operations can be moved or optimized individually (eg `CSE`). +* Easier to keep track of debug information. Line location can point to +the text representing the data clause instead of the construct. +Additionally, attributes can be used to keep track of variable names in +clauses without having to walk the IR tree in attempt to recover the +information (this makes acc dialect more agnostic with regards to what +other dialect it is used with). +* Clear operation ordering since all data operations are on same +list. + +Each of the `acc` dialect data operations represents either the +entry or the exit portion of the data action specification. Thus, +`acc.copyin` represents the semantics defined in section +`2.7.7 copyin clause` whose wording starts with +`At entry to a region`. The decomposed exit operation `acc.delete` +represents the second part of that section, whose wording starts with +`At exit from the region`. The `delete` action may be performed +after checking and updating of the relevant reference counters noted. + +The `acc` data operations, even when decomposed, retain their original +data clause in an operation operand `dataClause` for possibility to +recover this information during debugging. For example, `acc copy`, +does not translate to `acc.copy` operation, but instead to `acc.copyin` +for entry and `acc.copyout` for exit. Both the decomposed operations +hold a `dataClause` field that specifies this was an `acc copy`. + +The link between the decomposed entry and exit operations is the ssa +value produced by the entry operation. Namely, it is the `accPtr` result +which is used both in the `dataOperands` of the operation used for the +construct and in the `accPtr` operand of the exit operation. + +#### Bounds + +OpenACC data clauses allow the use of bounds specifiers as per +`2.7.1 Data Specification in Data Clauses`. However, array dimensions +for the data are not always required in the clause if the source +language's type system captures this information - the user can just +specify the variable name in the data clause. So the `acc.bounds` +operation is an important piece to ensure uniform representation of both +explicit user set dimensions and implicit type-based dimensions. It +contains several key features to allow properly encoding sizes in a +manner flexible and agnostic to the source language's dialect: +* Multi-dimensional arrays can be represented by using multiple ordered +`acc.bounds` operations. +* Bounds are required to be zero-normalized. This works well with the +`PointerLikeType` requirement in data clauses - since a lowerbound of 0 +means looking at data at the zero offset from pointer. This requirement +also works well in ensuring the `acc` dialect is agnostic to source +language dialect since it prevents ambiguity such as the case of Fortran +arrays where the lower bound is not a fixed value. +* If the source dialect does not encode the dimensions in the type (eg +`!fir.array`) but instead encodes it in some other way (such as +through descriptors), then the frontend must fill in the `acc.bounds` +operands with appropriate information (such as loads from descriptor). +The `acc.bounds` operation also permits lossy source dialect, such +as if the frontend uses aggressive pointer decay and cannot represent +the dimensions in the type system (eg using `!llvm.ptr` for arrays). +Both of these aspects show `acc.bounds`' operation's flexibility to +allow the representation to be agnostic since the `acc` dialect is not +expected to be able to understand how to extract dimension information +from the types of the source dialect. +* The OpenACC specification allows either extent or upperbound in the +data clause depending on whether it is Fortran or C and C++. The +`acc.bounds` operation is rich enough to accept either or both - for +convenience in lowering to the dialect and for ability to precisely +capture the meaning from the clause. +* The stride, either in units or bytes, can be also captured in the +`acc.bounds` operation. This is also an important part to be able to +accept a source language's arrays without forcing the frontend to +normalize them in some way. For example, consider a case where in a +parent function, a whole array is mapped to device. Then only a view of +a non-1 stride is passed to child function (eg Fortran array slice with +non-1 stride). A `copy` operation of this data in child should be able +to avoid remapping this array. If instead the operation required +normalizing the array (such as making it contiguous), then unexpected +disjoint mapping of the same host data would be error-prone since it +would result in multiple mappings to device. + +#### Counters + +The data operations also maintain semantics described in the OpenACC +specification related to runtime counters. More specifically, consider +the specification of the entry portion of `acc copyin` in section 2.7.7: +``` +At entry to a region, the structured reference counter is used. On an +enter data directive, the dynamic reference counter is used. +- If var is present and is not a null pointer, a present increment +action with the appropriate reference counter is performed. +- If var is not present, a copyin action with the appropriate reference +counter is performed. +- If var is a pointer reference, an attach action is performed. +``` +The `acc.copyin` operation includes these semantics, including those +related to attach, which is specified through the `varPtrPtr` operand. +The `structured` flag on the operation is important since the +`structured reference counter` should be used when the flag is true; and +the `dynamic reference counter` should be used when it is false. + +At exit from structured regions (`acc data`, `acc kernels`), the +`acc copyin` operation is decomposed to `acc.delete` (with the +`structured` flag as true). The semantics of the `acc.delete` are +also consistent with the OpenACC specification noted for the exit +portion of the `acc copyin` clause: +``` +At exit from the region: +- If the structured reference counter for var is zero, no action is +taken. +- Otherwise, a detach action is performed if var is a pointer reference, +and a present decrement action with the structured reference counter is +performed if var is not a null pointer. If both structured and dynamic +reference counters are zero, a delete action is performed. +``` + +### Types + +There are a few acc dialect type categories to describe: +* type of acc data clause operation input `varPtr` + - The type of `varPtr` must be pointer-like. This is done by + attaching the `PointerLikeType` interface to the appropriate MLIR + type. Although memory/storage concept is a lower level abstraction, + it is useful because the OpenACC model distinguishes between host + and device memory explicitly - and the mapping between the two is + done through pointers. Thus, by explicitly requiring it in the + dialect, the appropriate language frontend must create storage or + use type that satisfies the mapping constraint. +* type of result of acc data clause operations + - The type of the acc data clause operation is exactly the same as + `varPtr`. This was done intentionally instead of introducing an + `acc.ref/ptr` type so that IR compatibility and the dialect's + existing strong type checking can be maintained. This is needed + since the `acc` dialect must live within another dialect whose type + system is unknown to it. The only constraint is that the appropriate + dialect type must use the `PointerLikeType` interface. +* type of decomposed clauses + - Decomposed clauses, such as `acc.bounds` and `acc.declare_enter` + produce types to allow their results to be used only in specific + operations. + +### Recipes + +Recipes are a generic way to express source language specific semantics. + +There are currently two categories of recipes, but the recipe concept +can be extended for any additional low-level information that needs +to be captured for successful lowering of OpenACC. The two categories +are: +* recipes used in the context of privatization associated with a +construct +* recipes used in the context of additional specification of data +semantics + +The intention of the recipes is to specify how materialization of +action, such as privatization, should be done when the semantics +of the action needs interpreted and lowered, such as before generating +LLVM dialect. + +The recipes used for privatization provide a source-language independent +way of specifying the creation of a local variable of that type. This +means using the appropriate `alloca` instruction and being able to +specify default initialization or default constructor. + +### Routine + +The routine directive is used to note that a procedure should be made +available for the accelerator in a way that is consistent with its +modifiers, such as those that describe the parallelism. In the acc +dialect, an acc routine is represented through two joint pieces - an +attribute and an operation: +* The `acc.routine` operation is simply a specifier which notes which +symbol (or string) the acc routine is needed for, along with parallelism +associated. This defines a symbol that can be referenced in attribute. +* The `acc.routine_info` attribute is an attribute used on the source +dialect specific operation which specifies one or multiple `acc.routine` +symbols. Typically, this is attached to `func.func` which either +provides the declaration (in case of externals) or provides the +actual body of the acc routine in the dialect that the source language +was translated to. + +### Declare + +OpenACC `declare` is a mechanism which declares a definition of a global +or a local to be accessible to accelerator with an implicit lifetime +as that of the scope where it was declared in. Thus, `declare` semantics +are represented through multiple operations and attributes: +* `acc.declare` - This is a structured operation which contains an +MLIR region and can be used in similar manner as acc.data to specify +an implicit data region with specific procedure lifetime. This is +typically used inside `func.func` after variable declarations. +* `acc.declare_enter` - This is an unstructured operation which is +used as a decomposed form of `acc declare`. It effectively allows the +entry operation to exist in a scope different than the exit operation. +It can also be used along `acc.declare_exit` which consumes its token +to define a scoped region without using MLIR region. This operation is +also used in `acc.global_ctor`. +* `acc.declare_exit` - The matching equivalent of `acc.declare_enter` +except that it specifies exit semantics. This operation is typically +used inside a `func.func` at the exit points or with `acc.global_dtor`. +* `acc.global_ctor` - Lives at the same level as source dialect globals +and is used to specify data actions to be done at program entry. This +is used in conjunction with source dialect globals whose lifetime is +not just a single procedure. +* `acc.global_dtor` - Defines the exit data actions that should be done +at program exit. Typically used to revert the actions of +`acc.global_ctor`. + +The attributes: +* `acc.declare` - This is a facility for easier determination of +variables which are `acc declare`'d. This attribute is used on +operations producing globals and on operations producing locals such as +dialect specific `alloca`'s. Having this attribute is required in order +to appear in a data mapping operation associated with any of the +`acc.declare*` operations. +* `acc.declare_action` - Since the OpenACC specification allows +declaration of variables that have yet to be allocated, this attribute +is used at the allocation and deallocation points. More specifically, +this attribute captures symbols of functions to be called to perform +an action either pre-allocate, post-allocate, pre-deallocate, or +post-deallocate. Calls to these functions should be materialized when +lowering OpenACC semantics to ensure proper data actions are done +after the allocation/deallocation. + +## OpenACC Transforms and Analyses + +The design goal for the `acc` dialect is to be friendly to MLIR +optimization passes including CSE and LICM. Additionally, since it is +designed to recover original clauses, it makes late verification and +analysis possible in the MLIR framework outside of the frontend. + +This section describes a few MLIR-level passes for which the `acc` +dialect design should be friendly for. This section is currently +solely outlining the possibilities intended by the design and not +necessarily existing passes. + +### Verification + +Since the OpenACC dialect is not lossy with regards to its +representation, it is possible to do OpenACC language semantic checking +at the MLIR-level. What follows is a list of various semantic checks +needed. + +This first list is required to be done in the frontend because the `acc` +dialect operations must be valid when constructed: +* Ensure that only listed clauses are allowed for each directive. +* Ensure that only listed modifiers are allowed for each clause. + +However, the following are semantic checks that can be done at the +MLIR-level (either in a separate pass or as part of the operation +verifier): +* Specify the validity checks that each modifier needs. (eg num_gangs +may need a positive integer). +* Ensure valid clause nesting. +* Validate clause restrictions which cannot appear with others. +* Validate that no conflicting clauses are used on variables. + +Note that some of these checks can be even more precise when done at the +MLIR level because optimizations like inlining and constant propagation +expose detail that wouldn't have been visible in the frontend. + +### Implicit Data Attributes + +The OpenACC specification includes a section on `2.6.2 Variables with +Implicitly Determined Data Attributes`. What this section describes are +the data actions that should be applied to a variable for which +user did not specify a data action for. The action depends on the +construct being used and also on the default clause. However, the point +to note here is that variables which are live-in into the acc region +must employ some data mapping so the data can be passed to accelerator. + +One possible optimizations that affects data attributes needed is +`Scalar Replacement of Aggregates (SROA)`. The `acc` dialect should +not prevent this from happening on the source dialect. + +Because it is intended to be possible to apply optimizations across an +`acc` region, the analysis/transformation pass that applies the implicit +data attributes should be run as late as possible - ideally right before +any outlining process which uses the `acc` region body to create an +accelerator procedure. It is expected that existing MLIR facilities, +such as `mlir::Liveness` will work for the `acc` region and thus can be +used to perform this analysis. + +### Redundant Clause Elimination + +The data operations are modeled in a way where data entry operations +look like loads and data exit operations look like stores. Thus these +operations are intended to be optimized in the following ways: +* Be able to eliminate redundant operations such as when an `acc.copyin` +dominates another. +* Be able to hoist/sink such operations out of loops. + +[include "Dialects/OpenACCDialect.md"] diff --git a/mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td b/mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td index 60e2ccfa18b6..2f7dfb2751c9 100644 --- a/mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td +++ b/mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td @@ -7,6 +7,7 @@ // ============================================================================= // // Defines MLIR OpenACC dialect. +// See [`OpenACC Dialect Documentation`](Dialects/OpenACC.md) for more details. // //===----------------------------------------------------------------------===// @@ -17,13 +18,6 @@ include "mlir/IR/AttrTypeBase.td" def OpenACC_Dialect : Dialect { let name = "acc"; - - let summary = "An OpenACC dialect for MLIR."; - - let description = [{ - This dialect models the construct from the OpenACC 3.3 directive language. - }]; - let useDefaultAttributePrinterParser = 1; let useDefaultTypePrinterParser = 1; let cppNamespace = "::mlir::acc"; -- GitLab From a85cbe8f9036c8771fbf61335eb288eaefcda365 Mon Sep 17 00:00:00 2001 From: Zibi Sarbinowski Date: Tue, 9 Jan 2024 08:31:48 -0600 Subject: [PATCH 210/652] Disable autolink_private_module.m for z/OS & AIX This change disables it on z/OS and AIX since it fails on both platforms with: fatal error: error in backend: Objective-C support is unimplemented for object file format --- clang/test/Modules/autolink_private_module.m | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/test/Modules/autolink_private_module.m b/clang/test/Modules/autolink_private_module.m index 54bebc3a587b..f83f0a26b530 100644 --- a/clang/test/Modules/autolink_private_module.m +++ b/clang/test/Modules/autolink_private_module.m @@ -1,4 +1,6 @@ // Test that autolink hints for frameworks don't use the private module name. +// UNSUPPORTED: target={{.*}}-zos{{.*}}, target={{.*}}-aix{{.*}} + // RUN: rm -rf %t && mkdir %t // RUN: split-file %s %t -- GitLab From 07c9189fcc063bdf6219d2733843c89cde3991e1 Mon Sep 17 00:00:00 2001 From: Qiongsi Wu <274595+qiongsiwu@users.noreply.github.com> Date: Tue, 9 Jan 2024 10:38:17 -0500 Subject: [PATCH 211/652] [PGO] Exposing PGO's Counter Reset and File Dumping APIs (#76471) This PR exposes four PGO functions - `__llvm_profile_set_filename` - `__llvm_profile_reset_counters`, - `__llvm_profile_dump` - `__llvm_orderfile_dump` to user programs through the new header `instr_prof_interface.h` under `compiler-rt/include/profile`. This way, the user can include the header `profile/instr_prof_interface.h` to introduce these four names to their programs. Additionally, this PR defines macro `__LLVM_INSTR_PROFILE_GENERATE` when the program is compiled with profile generation, and defines macro `__LLVM_INSTR_PROFILE_USE` when the program is compiled with profile use. `__LLVM_INSTR_PROFILE_GENERATE` together with `instr_prof_interface.h` define the PGO functions only when the program is compiled with profile generation. When profile generation is off, these PGO functions are defined away and leave no trace in the user's program. Background: https://discourse.llvm.org/t/pgo-are-the-llvm-profile-functions-stable-c-apis-across-llvm-releases/75832 --- .../ExpandModularHeadersPPCallbacks.cpp | 2 +- clang/docs/UsersManual.rst | 104 ++++++++++++++++++ clang/include/clang/Basic/CodeGenOptions.h | 6 + clang/include/clang/Frontend/Utils.h | 4 +- clang/lib/Frontend/CompilerInstance.cpp | 2 +- clang/lib/Frontend/InitPreprocessor.cpp | 23 +++- clang/test/Profile/c-general.c | 10 ++ compiler-rt/include/CMakeLists.txt | 1 + .../include/profile/instr_prof_interface.h | 92 ++++++++++++++++ compiler-rt/lib/profile/InstrProfiling.h | 61 ++-------- .../profile/Linux/instrprof-weak-symbol.c | 16 +++ compiler-rt/test/profile/instrprof-api.c | 46 ++++++++ 12 files changed, 310 insertions(+), 57 deletions(-) create mode 100644 compiler-rt/include/profile/instr_prof_interface.h create mode 100644 compiler-rt/test/profile/Linux/instrprof-weak-symbol.c create mode 100644 compiler-rt/test/profile/instrprof-api.c diff --git a/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp b/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp index e414ac8c7705..5ecd4fb19131 100644 --- a/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp +++ b/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp @@ -100,7 +100,7 @@ ExpandModularHeadersPPCallbacks::ExpandModularHeadersPPCallbacks( /*OwnsHeaderSearch=*/false); PP->Initialize(Compiler.getTarget(), Compiler.getAuxTarget()); InitializePreprocessor(*PP, *PO, Compiler.getPCHContainerReader(), - Compiler.getFrontendOpts()); + Compiler.getFrontendOpts(), Compiler.getCodeGenOpts()); ApplyHeaderSearchOptions(*HeaderInfo, *HSO, LangOpts, Compiler.getTarget().getTriple()); } diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 7c30570437e8..27c629a1ffc6 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -2809,6 +2809,110 @@ indexed format, regardeless whether it is produced by frontend or the IR pass. overhead. ``prefer-atomic`` will be transformed to ``atomic`` when supported by the target, or ``single`` otherwise. +Fine Tuning Profile Collection +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The PGO infrastructure provides user program knobs to fine tune profile +collection. Specifically, the PGO runtime provides the following functions +that can be used to control the regions in the program where profiles should +be collected. + + * ``void __llvm_profile_set_filename(const char *Name)``: changes the name of + the profile file to ``Name``. + * ``void __llvm_profile_reset_counters(void)``: resets all counters to zero. + * ``int __llvm_profile_dump(void)``: write the profile data to disk. + * ``int __llvm_orderfile_dump(void)``: write the order file to disk. + +For example, the following pattern can be used to skip profiling program +initialization, profile two specific hot regions, and skip profiling program +cleanup: + +.. code-block:: c + + int main() { + initialize(); + + // Reset all profile counters to 0 to omit profile collected during + // initialize()'s execution. + __llvm_profile_reset_counters(); + ... hot region 1 + // Dump the profile for hot region 1. + __llvm_profile_set_filename("region1.profraw"); + __llvm_profile_dump(); + + // Reset counters before proceeding to hot region 2. + __llvm_profile_reset_counters(); + ... hot region 2 + // Dump the profile for hot region 2. + __llvm_profile_set_filename("region2.profraw"); + __llvm_profile_dump(); + + // Since the profile has been dumped, no further profile data + // will be collected beyond the above __llvm_profile_dump(). + cleanup(); + return 0; + } + +These APIs' names can be introduced to user programs in two ways. +They can be declared as weak symbols on platforms which support +treating weak symbols as ``null`` during linking. For example, the user can +have + +.. code-block:: c + + __attribute__((weak)) int __llvm_profile_dump(void); + + // Then later in the same source file + if (__llvm_profile_dump) + if (__llvm_profile_dump() != 0) { ... } + // The first if condition tests if the symbol is actually defined. + // Profile dumping only happens if the symbol is defined. Hence, + // the user program works correctly during normal (not profile-generate) + // executions. + +Alternatively, the user program can include the header +``profile/instr_prof_interface.h``, which contains the API names. For example, + +.. code-block:: c + + #include "profile/instr_prof_interface.h" + + // Then later in the same source file + if (__llvm_profile_dump() != 0) { ... } + +The user code does not need to check if the API names are defined, because +these names are automatically replaced by ``(0)`` or the equivalence of noop +if the ``clang`` is not compiling for profile generation. + +Such replacement can happen because ``clang`` adds one of two macros depending +on the ``-fprofile-generate`` and the ``-fprofile-use`` flags. + + * ``__LLVM_INSTR_PROFILE_GENERATE``: defined when one of + ``-fprofile[-instr]-generate``/``-fcs-profile-generate`` is in effect. + * ``__LLVM_INSTR_PROFILE_USE``: defined when one of + ``-fprofile-use``/``-fprofile-instr-use`` is in effect. + +The two macros can be used to provide more flexibiilty so a user program +can execute code specifically intended for profile generate or profile use. +For example, a user program can have special logging during profile generate: + +.. code-block:: c + + #if __LLVM_INSTR_PROFILE_GENERATE + expensive_logging_of_full_program_state(); + #endif + +The logging is automatically excluded during a normal build of the program, +hence it does not impact performance during a normal execution. + +It is advised to use such fine tuning only in a program's cold regions. The weak +symbols can introduce extra control flow (the ``if`` checks), while the macros +(hence declarations they guard in ``profile/instr_prof_interface.h``) +can change the control flow of the functions that use them between profile +generation and profile use (which can lead to discarded counters in such +functions). Using these APIs in the program's cold regions introduces less +overhead and leads to more optimized code. + Disabling Instrumentation ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h index 6952b48e898a..e06f1094784c 100644 --- a/clang/include/clang/Basic/CodeGenOptions.h +++ b/clang/include/clang/Basic/CodeGenOptions.h @@ -494,6 +494,12 @@ public: return getProfileInstr() == ProfileCSIRInstr; } + /// Check if any form of instrumentation is on. + bool hasProfileInstr() const { + return hasProfileClangInstr() || hasProfileIRInstr() || + hasProfileCSIRInstr(); + } + /// Check if Clang profile use is on. bool hasProfileClangUse() const { return getProfileUse() == ProfileClangInstr; diff --git a/clang/include/clang/Frontend/Utils.h b/clang/include/clang/Frontend/Utils.h index 143cf4359f00..604e42067a3f 100644 --- a/clang/include/clang/Frontend/Utils.h +++ b/clang/include/clang/Frontend/Utils.h @@ -43,12 +43,14 @@ class PCHContainerReader; class Preprocessor; class PreprocessorOptions; class PreprocessorOutputOptions; +class CodeGenOptions; /// InitializePreprocessor - Initialize the preprocessor getting it and the /// environment ready to process a single file. void InitializePreprocessor(Preprocessor &PP, const PreprocessorOptions &PPOpts, const PCHContainerReader &PCHContainerRdr, - const FrontendOptions &FEOpts); + const FrontendOptions &FEOpts, + const CodeGenOptions &CodeGenOpts); /// DoPrintPreprocessedInput - Implement -E mode. void DoPrintPreprocessedInput(Preprocessor &PP, raw_ostream *OS, diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp index 56bbef9697b6..ea44a26b6db7 100644 --- a/clang/lib/Frontend/CompilerInstance.cpp +++ b/clang/lib/Frontend/CompilerInstance.cpp @@ -470,7 +470,7 @@ void CompilerInstance::createPreprocessor(TranslationUnitKind TUKind) { // Predefine macros and configure the preprocessor. InitializePreprocessor(*PP, PPOpts, getPCHContainerReader(), - getFrontendOpts()); + getFrontendOpts(), getCodeGenOpts()); // Initialize the header search object. In CUDA compilations, we use the aux // triple (the host triple) to initialize our header search, since we need to diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index d83128adb511..fe0fd3614113 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -1364,12 +1364,22 @@ static void InitializePredefinedMacros(const TargetInfo &TI, TI.getTargetDefines(LangOpts, Builder); } +static void InitializePGOProfileMacros(const CodeGenOptions &CodeGenOpts, + MacroBuilder &Builder) { + if (CodeGenOpts.hasProfileInstr()) + Builder.defineMacro("__LLVM_INSTR_PROFILE_GENERATE"); + + if (CodeGenOpts.hasProfileIRUse() || CodeGenOpts.hasProfileClangUse()) + Builder.defineMacro("__LLVM_INSTR_PROFILE_USE"); +} + /// InitializePreprocessor - Initialize the preprocessor getting it and the /// environment ready to process a single file. -void clang::InitializePreprocessor( - Preprocessor &PP, const PreprocessorOptions &InitOpts, - const PCHContainerReader &PCHContainerRdr, - const FrontendOptions &FEOpts) { +void clang::InitializePreprocessor(Preprocessor &PP, + const PreprocessorOptions &InitOpts, + const PCHContainerReader &PCHContainerRdr, + const FrontendOptions &FEOpts, + const CodeGenOptions &CodeGenOpts) { const LangOptions &LangOpts = PP.getLangOpts(); std::string PredefineBuffer; PredefineBuffer.reserve(4080); @@ -1416,6 +1426,11 @@ void clang::InitializePreprocessor( InitializeStandardPredefinedMacros(PP.getTargetInfo(), PP.getLangOpts(), FEOpts, Builder); + // The PGO instrumentation profile macros are driven by options + // -fprofile[-instr]-generate/-fcs-profile-generate/-fprofile[-instr]-use, + // hence they are not guarded by InitOpts.UsePredefines. + InitializePGOProfileMacros(CodeGenOpts, Builder); + // Add on the predefines from the driver. Wrap in a #line directive to report // that they come from the command line. Builder.append("# 1 \"\" 1"); diff --git a/clang/test/Profile/c-general.c b/clang/test/Profile/c-general.c index b841f9c3d2a1..2f621ec9b0bf 100644 --- a/clang/test/Profile/c-general.c +++ b/clang/test/Profile/c-general.c @@ -9,6 +9,16 @@ // Also check compatibility with older profiles. // RUN: %clang_cc1 -triple x86_64-apple-macosx10.9 -main-file-name c-general.c %s -o - -emit-llvm -fprofile-instrument-use-path=%S/Inputs/c-general.profdata.v1 | FileCheck -allow-deprecated-dag-overlap -check-prefix=PGOUSE %s +// RUN: %clang -fprofile-generate -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFGENMACRO %s +// RUN: %clang -fprofile-instr-generate -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFGENMACRO %s +// RUN: %clang -fcs-profile-generate -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFGENMACRO %s +// +// RUN: %clang -fprofile-use=%t.profdata -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFUSEMACRO %s +// RUN: %clang -fprofile-instr-use=%t.profdata -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFUSEMACRO %s + +// PROFGENMACRO:#define __LLVM_INSTR_PROFILE_GENERATE 1 +// PROFUSEMACRO:#define __LLVM_INSTR_PROFILE_USE 1 + // PGOGEN: @[[SLC:__profc_simple_loops]] = private global [4 x i64] zeroinitializer // PGOGEN: @[[IFC:__profc_conditionals]] = private global [13 x i64] zeroinitializer // PGOGEN: @[[EEC:__profc_early_exits]] = private global [9 x i64] zeroinitializer diff --git a/compiler-rt/include/CMakeLists.txt b/compiler-rt/include/CMakeLists.txt index 78427beedb3c..7a100c66bbcf 100644 --- a/compiler-rt/include/CMakeLists.txt +++ b/compiler-rt/include/CMakeLists.txt @@ -44,6 +44,7 @@ endif(COMPILER_RT_BUILD_ORC) if (COMPILER_RT_BUILD_PROFILE) set(PROFILE_HEADERS profile/InstrProfData.inc + profile/instr_prof_interface.h ) endif(COMPILER_RT_BUILD_PROFILE) diff --git a/compiler-rt/include/profile/instr_prof_interface.h b/compiler-rt/include/profile/instr_prof_interface.h new file mode 100644 index 000000000000..be40f2685934 --- /dev/null +++ b/compiler-rt/include/profile/instr_prof_interface.h @@ -0,0 +1,92 @@ +/*===---- instr_prof_interface.h - Instrumentation PGO User Program API ----=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + * + * This header provides a public interface for fine-grained control of counter + * reset and profile dumping. These interface functions can be directly called + * in user programs. + * +\*===---------------------------------------------------------------------===*/ + +#ifndef COMPILER_RT_INSTR_PROFILING +#define COMPILER_RT_INSTR_PROFILING + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __LLVM_INSTR_PROFILE_GENERATE +// Profile file reset and dump interfaces. +// When `-fprofile[-instr]-generate`/`-fcs-profile-generate` is in effect, +// clang defines __LLVM_INSTR_PROFILE_GENERATE to pick up the API calls. + +/*! + * \brief Set the filename for writing instrumentation data. + * + * Sets the filename to be used for subsequent calls to + * \a __llvm_profile_write_file(). + * + * \c Name is not copied, so it must remain valid. Passing NULL resets the + * filename logic to the default behaviour. + * + * Note: There may be multiple copies of the profile runtime (one for each + * instrumented image/DSO). This API only modifies the filename within the + * copy of the runtime available to the calling image. + * + * Warning: This is a no-op if continuous mode (\ref + * __llvm_profile_is_continuous_mode_enabled) is on. The reason for this is + * that in continuous mode, profile counters are mmap()'d to the profile at + * program initialization time. Support for transferring the mmap'd profile + * counts to a new file has not been implemented. + */ +void __llvm_profile_set_filename(const char *Name); + +/*! + * \brief Interface to set all PGO counters to zero for the current process. + * + */ +void __llvm_profile_reset_counters(void); + +/*! + * \brief this is a wrapper interface to \c __llvm_profile_write_file. + * After this interface is invoked, an already dumped flag will be set + * so that profile won't be dumped again during program exit. + * Invocation of interface __llvm_profile_reset_counters will clear + * the flag. This interface is designed to be used to collect profile + * data from user selected hot regions. The use model is + * __llvm_profile_reset_counters(); + * ... hot region 1 + * __llvm_profile_dump(); + * .. some other code + * __llvm_profile_reset_counters(); + * ... hot region 2 + * __llvm_profile_dump(); + * + * It is expected that on-line profile merging is on with \c %m specifier + * used in profile filename . If merging is not turned on, user is expected + * to invoke __llvm_profile_set_filename to specify different profile names + * for different regions before dumping to avoid profile write clobbering. + */ +int __llvm_profile_dump(void); + +// Interface to dump the current process' order file to disk. +int __llvm_orderfile_dump(void); + +#else + +#define __llvm_profile_set_filename(Name) +#define __llvm_profile_reset_counters() +#define __llvm_profile_dump() (0) +#define __llvm_orderfile_dump() (0) + +#endif + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/compiler-rt/lib/profile/InstrProfiling.h b/compiler-rt/lib/profile/InstrProfiling.h index 137115996748..012390833691 100644 --- a/compiler-rt/lib/profile/InstrProfiling.h +++ b/compiler-rt/lib/profile/InstrProfiling.h @@ -12,6 +12,17 @@ #include "InstrProfilingPort.h" #include +// Make sure __LLVM_INSTR_PROFILE_GENERATE is always defined before +// including instr_prof_interface.h so the interface functions are +// declared correctly for the runtime. +// __LLVM_INSTR_PROFILE_GENERATE is always `#undef`ed after the header, +// because compiler-rt does not support profiling the profiling runtime itself. +#ifndef __LLVM_INSTR_PROFILE_GENERATE +#define __LLVM_INSTR_PROFILE_GENERATE +#endif +#include "profile/instr_prof_interface.h" +#undef __LLVM_INSTR_PROFILE_GENERATE + #define INSTR_PROF_VISIBILITY COMPILER_RT_VISIBILITY #include "profile/InstrProfData.inc" @@ -100,12 +111,6 @@ ValueProfNode *__llvm_profile_begin_vnodes(); ValueProfNode *__llvm_profile_end_vnodes(); uint32_t *__llvm_profile_begin_orderfile(); -/*! - * \brief Clear profile counters to zero. - * - */ -void __llvm_profile_reset_counters(void); - /*! * \brief Merge profile data from buffer. * @@ -156,50 +161,6 @@ void __llvm_profile_instrument_target_value(uint64_t TargetValue, void *Data, int __llvm_profile_write_file(void); int __llvm_orderfile_write_file(void); -/*! - * \brief this is a wrapper interface to \c __llvm_profile_write_file. - * After this interface is invoked, an already dumped flag will be set - * so that profile won't be dumped again during program exit. - * Invocation of interface __llvm_profile_reset_counters will clear - * the flag. This interface is designed to be used to collect profile - * data from user selected hot regions. The use model is - * __llvm_profile_reset_counters(); - * ... hot region 1 - * __llvm_profile_dump(); - * .. some other code - * __llvm_profile_reset_counters(); - * ... hot region 2 - * __llvm_profile_dump(); - * - * It is expected that on-line profile merging is on with \c %m specifier - * used in profile filename . If merging is not turned on, user is expected - * to invoke __llvm_profile_set_filename to specify different profile names - * for different regions before dumping to avoid profile write clobbering. - */ -int __llvm_profile_dump(void); - -int __llvm_orderfile_dump(void); - -/*! - * \brief Set the filename for writing instrumentation data. - * - * Sets the filename to be used for subsequent calls to - * \a __llvm_profile_write_file(). - * - * \c Name is not copied, so it must remain valid. Passing NULL resets the - * filename logic to the default behaviour. - * - * Note: There may be multiple copies of the profile runtime (one for each - * instrumented image/DSO). This API only modifies the filename within the - * copy of the runtime available to the calling image. - * - * Warning: This is a no-op if continuous mode (\ref - * __llvm_profile_is_continuous_mode_enabled) is on. The reason for this is - * that in continuous mode, profile counters are mmap()'d to the profile at - * program initialization time. Support for transferring the mmap'd profile - * counts to a new file has not been implemented. - */ -void __llvm_profile_set_filename(const char *Name); /*! * \brief Set the FILE object for writing instrumentation data. Return 0 if set diff --git a/compiler-rt/test/profile/Linux/instrprof-weak-symbol.c b/compiler-rt/test/profile/Linux/instrprof-weak-symbol.c new file mode 100644 index 000000000000..eda299cb6610 --- /dev/null +++ b/compiler-rt/test/profile/Linux/instrprof-weak-symbol.c @@ -0,0 +1,16 @@ +// Test the linker feature that treats undefined weak symbols as null values. + +// RUN: %clang_pgogen -o %t %s +// RUN: not %t +// RUN: %clang -o %t %s +// RUN: %t + +__attribute__((weak)) void __llvm_profile_reset_counters(void); + +int main() { + if (__llvm_profile_reset_counters) { + __llvm_profile_reset_counters(); + return 1; + } + return 0; +} diff --git a/compiler-rt/test/profile/instrprof-api.c b/compiler-rt/test/profile/instrprof-api.c new file mode 100644 index 000000000000..1381300c1ad1 --- /dev/null +++ b/compiler-rt/test/profile/instrprof-api.c @@ -0,0 +1,46 @@ +// Testing profile generate. +// RUN: %clang_profgen %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFGEN +// RUN: %clang_pgogen %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFGEN + +// Testing profile use. Generate some profile file first. +// RUN: rm -rf rawprof.profraw +// RUN: %clang_profgen -o %t1 %s +// RUN: %run %t1 +// RUN: llvm-profdata merge -o %t1.profdata rawprof.profraw +// RUN: %clang_profuse=%t1.profdata %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFUSE +// RUN: rm -rf rawprof.profraw +// RUN: %clang_pgogen -o %t2 %s +// RUN: %run %t2 +// RUN: llvm-profdata merge -o %t2.profdata rawprof.profraw +// RUN: %clang_pgouse=%t2.profdata %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFUSE +#include "profile/instr_prof_interface.h" + +__attribute__((noinline)) int bar() { return 4; } + +int foo() { + __llvm_profile_reset_counters(); + // PROFGEN: call void @__llvm_profile_reset_counters() + // PROFUSE-NOT: call void @__llvm_profile_reset_counters() + return bar(); +} + +// PROFUSE-NOT: declare void @__llvm_profile_reset_counters() + +int main() { + int z = foo() + 3; + __llvm_profile_set_filename("rawprof.profraw"); + // PROFGEN: call void @__llvm_profile_set_filename(ptr noundef @.str) + // PROFUSE-NOT: call void @__llvm_profile_set_filename(ptr noundef @.str) + if (__llvm_profile_dump()) + return 2; + // PROFGEN: %call1 = call {{(signext )*}}i32 @__llvm_profile_dump() + // PROFUSE-NOT: %call1 = call {{(signext )*}}i32 @__llvm_profile_dump() + __llvm_orderfile_dump(); + // PROFGEN: %call2 = call {{(signext )*}}i32 @__llvm_orderfile_dump() + // PROFUSE-NOT: %call2 = call {{(signext )*}}i32 @__llvm_orderfile_dump() + return z + bar() - 11; +} + +// PROFUSE-NOT: declare void @__llvm_profile_set_filename(ptr noundef) +// PROFUSE-NOT: declare signext i32 @__llvm_profile_dump() +// PROFUSE-NOT: declare signext i32 @__llvm_orderfile_dump() -- GitLab From ca06c330fd07f05e65a638892c32ca1474d47b5e Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 9 Jan 2024 10:39:14 -0500 Subject: [PATCH 212/652] [libc++] Allow running the test suite with optimizations (#68753) This patch adds a configuration of the libc++ test suite that enables optimizations when building the tests. It also adds a new CI configuration to exercise this on a regular basis. This is added in the context of [1], which requires building with optimizations in order to hit the bug. [1]: https://github.com/llvm/llvm-project/issues/68552 --- .github/workflows/libcxx-build-and-test.yaml | 1 + .../caches/Generic-optimized-speed.cmake | 4 +++ .../allocator.members/allocate.cxx2a.pass.cpp | 2 +- .../support.dynamic/libcpp_deallocate.sh.cpp | 16 ++++----- .../simd.class/simd_ctor_conversion.pass.cpp | 4 +++ .../path.member/path.assign/move.pass.cpp | 2 +- .../path.member/path.construct/move.pass.cpp | 2 +- .../new.size.replace.indirect.pass.cpp | 2 +- .../new.size.replace.pass.cpp | 2 +- .../new.size_align.replace.indirect.pass.cpp | 6 ++-- ...ze_align_nothrow.replace.indirect.pass.cpp | 6 ++-- .../new.size_align_nothrow.replace.pass.cpp | 6 ++-- ...new.size_nothrow.replace.indirect.pass.cpp | 2 +- .../new.size_nothrow.replace.pass.cpp | 2 +- .../new.size.replace.pass.cpp | 2 +- ...ze_align_nothrow.replace.indirect.pass.cpp | 6 ++-- ...new.size_nothrow.replace.indirect.pass.cpp | 2 +- .../func.wrap.func.alg/swap.pass.cpp | 16 ++++----- .../func.wrap.func.con/F.pass.cpp | 2 +- .../func.wrap.func.con/copy_assign.pass.cpp | 8 ++--- .../func.wrap.func.con/copy_move.pass.cpp | 8 ++--- .../nullptr_t_assign.pass.cpp | 2 +- .../func.wrap.func.mod/swap.pass.cpp | 12 +++---- .../make_shared.pass.cpp | 4 +-- libcxx/test/support/count_new.h | 5 +++ libcxx/test/support/test_macros.h | 16 ++++++--- libcxx/utils/ci/run-buildbot | 5 +++ libcxx/utils/libcxx/test/params.py | 36 ++++++++++++++++++- libunwind/test/libunwind_02.pass.cpp | 28 ++++++++++++--- libunwind/test/unw_resume.pass.cpp | 2 +- libunwind/test/unwind_leaffunction.pass.cpp | 20 ++++++----- 31 files changed, 157 insertions(+), 74 deletions(-) create mode 100644 libcxx/cmake/caches/Generic-optimized-speed.cmake diff --git a/.github/workflows/libcxx-build-and-test.yaml b/.github/workflows/libcxx-build-and-test.yaml index 3fd49541fd7c..985790a0ee23 100644 --- a/.github/workflows/libcxx-build-and-test.yaml +++ b/.github/workflows/libcxx-build-and-test.yaml @@ -161,6 +161,7 @@ jobs: 'generic-no-unicode', 'generic-no-wide-characters', 'generic-no-rtti', + 'generic-optimized-speed', 'generic-static', 'generic-with_llvm_unwinder', # TODO Find a better place for the benchmark and bootstrapping builds to live. They're either very expensive diff --git a/libcxx/cmake/caches/Generic-optimized-speed.cmake b/libcxx/cmake/caches/Generic-optimized-speed.cmake new file mode 100644 index 000000000000..577a5de9f34c --- /dev/null +++ b/libcxx/cmake/caches/Generic-optimized-speed.cmake @@ -0,0 +1,4 @@ +set(CMAKE_BUILD_TYPE RelWithDebInfo CACHE STRING "") +set(LIBCXX_TEST_PARAMS "optimization=speed" CACHE STRING "") +set(LIBCXXABI_TEST_PARAMS "${LIBCXX_TEST_PARAMS}" CACHE STRING "") +set(LIBUNWIND_TEST_PARAMS "${LIBCXX_TEST_PARAMS}" CACHE STRING "") diff --git a/libcxx/test/libcxx/depr/depr.default.allocator/allocator.members/allocate.cxx2a.pass.cpp b/libcxx/test/libcxx/depr/depr.default.allocator/allocator.members/allocate.cxx2a.pass.cpp index da35465c5295..f2fb606ee6db 100644 --- a/libcxx/test/libcxx/depr/depr.default.allocator/allocator.members/allocate.cxx2a.pass.cpp +++ b/libcxx/test/libcxx/depr/depr.default.allocator/allocator.members/allocate.cxx2a.pass.cpp @@ -60,7 +60,7 @@ void test_aligned() { { globalMemCounter.last_new_size = 0; globalMemCounter.last_new_align = 0; - T* volatile ap2 = a.allocate(11, (const void*)5); + T* ap2 = a.allocate(11, (const void*)5); DoNotOptimize(ap2); assert(globalMemCounter.checkOutstandingNewEq(1)); assert(globalMemCounter.checkNewCalledEq(1)); diff --git a/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp b/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp index fb56ce4518a7..267f87bd3f6f 100644 --- a/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp +++ b/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp @@ -187,13 +187,13 @@ void test_allocator_and_new_match() { stats.reset(); #if defined(NO_SIZE) && defined(NO_ALIGN) { - int* x = new int(42); + int* x = DoNotOptimize(new int(42)); delete x; assert(stats.expect_plain()); } stats.reset(); { - AlignedType* a = new AlignedType(); + AlignedType* a = DoNotOptimize(new AlignedType()); delete a; assert(stats.expect_plain()); } @@ -202,14 +202,14 @@ void test_allocator_and_new_match() { stats.reset(); #if TEST_STD_VER >= 11 { - int* x = new int(42); + int* x = DoNotOptimize(new int(42)); delete x; assert(stats.expect_plain()); } #endif stats.reset(); { - AlignedType* a = new AlignedType(); + AlignedType* a = DoNotOptimize(new AlignedType()); delete a; assert(stats.expect_align(TEST_ALIGNOF(AlignedType))); } @@ -217,13 +217,13 @@ void test_allocator_and_new_match() { #elif defined(NO_ALIGN) stats.reset(); { - int* x = new int(42); + int* x = DoNotOptimize(new int(42)); delete x; assert(stats.expect_size(sizeof(int))); } stats.reset(); { - AlignedType* a = new AlignedType(); + AlignedType* a = DoNotOptimize(new AlignedType()); delete a; assert(stats.expect_size(sizeof(AlignedType))); } @@ -231,13 +231,13 @@ void test_allocator_and_new_match() { #else stats.reset(); { - int* x = new int(42); + int* x = DoNotOptimize(new int(42)); delete x; assert(stats.expect_size(sizeof(int))); } stats.reset(); { - AlignedType* a = new AlignedType(); + AlignedType* a = DoNotOptimize(new AlignedType()); delete a; assert(stats.expect_size_align(sizeof(AlignedType), TEST_ALIGNOF(AlignedType))); diff --git a/libcxx/test/std/experimental/simd/simd.class/simd_ctor_conversion.pass.cpp b/libcxx/test/std/experimental/simd/simd.class/simd_ctor_conversion.pass.cpp index 7ce4bed9c7db..5920d62e0e5a 100644 --- a/libcxx/test/std/experimental/simd/simd.class/simd_ctor_conversion.pass.cpp +++ b/libcxx/test/std/experimental/simd/simd.class/simd_ctor_conversion.pass.cpp @@ -9,6 +9,10 @@ // UNSUPPORTED: c++03, c++11, c++14 // XFAIL: target=powerpc{{.*}}le-unknown-linux-gnu +// TODO: This test makes incorrect assumptions about floating point conversions. +// See https://github.com/llvm/llvm-project/issues/74327. +// XFAIL: optimization=speed + // // // [simd.class] diff --git a/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/move.pass.cpp b/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/move.pass.cpp index 0efd9596f1c2..93295d9f6d5f 100644 --- a/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/move.pass.cpp +++ b/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/move.pass.cpp @@ -31,7 +31,7 @@ int main(int, char**) { const std::string s("we really really really really really really really " "really really long string so that we allocate"); ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS( - globalMemCounter.checkOutstandingNewEq(1)); + globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); const fs::path::string_type ps(s.begin(), s.end()); path p(s); { diff --git a/libcxx/test/std/input.output/filesystems/class.path/path.member/path.construct/move.pass.cpp b/libcxx/test/std/input.output/filesystems/class.path/path.member/path.construct/move.pass.cpp index 15782dffa7df..3c762ee676be 100644 --- a/libcxx/test/std/input.output/filesystems/class.path/path.member/path.construct/move.pass.cpp +++ b/libcxx/test/std/input.output/filesystems/class.path/path.member/path.construct/move.pass.cpp @@ -31,7 +31,7 @@ int main(int, char**) { const std::string s("we really really really really really really really " "really really long string so that we allocate"); ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS( - globalMemCounter.checkOutstandingNewEq(1)); + globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); const fs::path::string_type ps(s.begin(), s.end()); path p(s); { diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp index f6f586a2b547..8eaf50d538be 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp @@ -42,7 +42,7 @@ void operator delete(void* p) TEST_NOEXCEPT { int main(int, char**) { new_called = delete_called = 0; - int* x = new int[3]; + int* x = DoNotOptimize(new int[3]); assert(x != nullptr); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp index 29e739d8515f..9715bc9207aa 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp @@ -40,7 +40,7 @@ void operator delete[](void* p) TEST_NOEXCEPT { int main(int, char**) { new_called = delete_called = 0; - int* x = new int[3]; + int* x = DoNotOptimize(new int[3]); assert(x != nullptr); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.replace.indirect.pass.cpp index dcaa76a650d3..66cbb4b9c8eb 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.replace.indirect.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.replace.indirect.pass.cpp @@ -51,7 +51,7 @@ int main(int, char**) { // Test with an overaligned type { new_called = delete_called = 0; - OverAligned* x = new OverAligned[3]; + OverAligned* x = DoNotOptimize(new OverAligned[3]); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(static_cast(x) == DummyData); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); @@ -62,7 +62,7 @@ int main(int, char**) { // Test with a type that is right on the verge of being overaligned { new_called = delete_called = 0; - MaxAligned* x = new MaxAligned[3]; + MaxAligned* x = DoNotOptimize(new MaxAligned[3]); assert(x != nullptr); assert(new_called == 0); @@ -73,7 +73,7 @@ int main(int, char**) { // Test with a type that is clearly not overaligned { new_called = delete_called = 0; - int* x = new int[3]; + int* x = DoNotOptimize(new int[3]); assert(x != nullptr); assert(new_called == 0); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.indirect.pass.cpp index eba8a9026fa4..df8a651932ce 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.indirect.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.indirect.pass.cpp @@ -51,7 +51,7 @@ int main(int, char**) { // Test with an overaligned type { new_called = delete_called = 0; - OverAligned* x = new (std::nothrow) OverAligned[3]; + OverAligned* x = DoNotOptimize(new (std::nothrow) OverAligned[3]); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(static_cast(x) == DummyData); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); @@ -62,7 +62,7 @@ int main(int, char**) { // Test with a type that is right on the verge of being overaligned { new_called = delete_called = 0; - MaxAligned* x = new (std::nothrow) MaxAligned[3]; + MaxAligned* x = DoNotOptimize(new (std::nothrow) MaxAligned[3]); assert(x != nullptr); assert(new_called == 0); @@ -73,7 +73,7 @@ int main(int, char**) { // Test with a type that is clearly not overaligned { new_called = delete_called = 0; - int* x = new (std::nothrow) int[3]; + int* x = DoNotOptimize(new (std::nothrow) int[3]); assert(x != nullptr); assert(new_called == 0); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.pass.cpp index 62a040e297ae..b984e8cf0a43 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.replace.pass.cpp @@ -48,7 +48,7 @@ int main(int, char**) { // Test with an overaligned type { new_nothrow_called = delete_called = 0; - OverAligned* x = new (std::nothrow) OverAligned[3]; + OverAligned* x = DoNotOptimize(new (std::nothrow) OverAligned[3]); assert(static_cast(x) == DummyData); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_nothrow_called == 1); @@ -59,7 +59,7 @@ int main(int, char**) { // Test with a type that is right on the verge of being overaligned { new_nothrow_called = delete_called = 0; - MaxAligned* x = new (std::nothrow) MaxAligned[3]; + MaxAligned* x = DoNotOptimize(new (std::nothrow) MaxAligned[3]); assert(x != nullptr); assert(new_nothrow_called == 0); @@ -70,7 +70,7 @@ int main(int, char**) { // Test with a type that is clearly not overaligned { new_nothrow_called = delete_called = 0; - int* x = new (std::nothrow) int[3]; + int* x = DoNotOptimize(new (std::nothrow) int[3]); assert(x != nullptr); assert(new_nothrow_called == 0); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp index b26eec0324af..70d891b2a82c 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp @@ -46,7 +46,7 @@ void operator delete(void* p) TEST_NOEXCEPT { int main(int, char**) { new_called = delete_called = 0; - int* x = new (std::nothrow) int[3]; + int* x = DoNotOptimize(new (std::nothrow) int[3]); assert(x != nullptr); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.pass.cpp index b85e15ce64b4..2b8918276d77 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.pass.cpp @@ -35,7 +35,7 @@ void operator delete[](void* p) TEST_NOEXCEPT { int main(int, char**) { new_nothrow_called = delete_called = 0; - int* x = new (std::nothrow) int[3]; + int* x = DoNotOptimize(new (std::nothrow) int[3]); assert(x != nullptr); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_nothrow_called == 1); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp index ab1cf5ea4644..3e0020b4f517 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp @@ -38,7 +38,7 @@ void operator delete(void* p) TEST_NOEXCEPT { int main(int, char**) { new_called = delete_called = 0; - int* x = new int(3); + int* x = DoNotOptimize(new int(3)); assert(x != nullptr); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.replace.indirect.pass.cpp index 4a18ad2df8f2..a68cdab54528 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.replace.indirect.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.replace.indirect.pass.cpp @@ -50,7 +50,7 @@ int main(int, char**) { // Test with an overaligned type { new_called = delete_called = 0; - OverAligned* x = new (std::nothrow) OverAligned; + OverAligned* x = DoNotOptimize(new (std::nothrow) OverAligned); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(static_cast(x) == DummyData); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); @@ -61,7 +61,7 @@ int main(int, char**) { // Test with a type that is right on the verge of being overaligned { new_called = delete_called = 0; - MaxAligned* x = new (std::nothrow) MaxAligned; + MaxAligned* x = DoNotOptimize(new (std::nothrow) MaxAligned); assert(x != nullptr); assert(new_called == 0); @@ -72,7 +72,7 @@ int main(int, char**) { // Test with a type that is clearly not overaligned { new_called = delete_called = 0; - int* x = new (std::nothrow) int; + int* x = DoNotOptimize(new (std::nothrow) int); assert(x != nullptr); assert(new_called == 0); diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp index 35a601339ddd..64edbfd7e9af 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp @@ -41,7 +41,7 @@ void operator delete(void* p) TEST_NOEXCEPT { int main(int, char**) { new_called = delete_called = 0; - int* x = new (std::nothrow) int(3); + int* x = DoNotOptimize(new (std::nothrow) int(3)); assert(x != nullptr); ASSERT_WITH_OPERATOR_NEW_FALLBACKS(new_called == 1); diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.alg/swap.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.alg/swap.pass.cpp index 3924274190c4..97f78ac62dab 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.alg/swap.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.alg/swap.pass.cpp @@ -69,12 +69,12 @@ int main(int, char**) static_assert(noexcept(swap(f1, f2)), "" ); #endif assert(A::count == 2); - assert(globalMemCounter.checkOutstandingNewEq(2)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(2)); RTTI_ASSERT(f1.target()->id() == 1); RTTI_ASSERT(f2.target()->id() == 2); swap(f1, f2); assert(A::count == 2); - assert(globalMemCounter.checkOutstandingNewEq(2)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(2)); RTTI_ASSERT(f1.target()->id() == 2); RTTI_ASSERT(f2.target()->id() == 1); } @@ -87,12 +87,12 @@ int main(int, char**) static_assert(noexcept(swap(f1, f2)), "" ); #endif assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f1.target()->id() == 1); RTTI_ASSERT(*f2.target() == g); swap(f1, f2); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(*f1.target() == g); RTTI_ASSERT(f2.target()->id() == 1); } @@ -105,12 +105,12 @@ int main(int, char**) static_assert(noexcept(swap(f1, f2)), "" ); #endif assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(*f1.target() == g); RTTI_ASSERT(f2.target()->id() == 1); swap(f1, f2); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f1.target()->id() == 1); RTTI_ASSERT(*f2.target() == g); } @@ -123,12 +123,12 @@ int main(int, char**) static_assert(noexcept(swap(f1, f2)), "" ); #endif assert(A::count == 0); - assert(globalMemCounter.checkOutstandingNewEq(0)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(0)); RTTI_ASSERT(*f1.target() == g); RTTI_ASSERT(*f2.target() == h); swap(f1, f2); assert(A::count == 0); - assert(globalMemCounter.checkOutstandingNewEq(0)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(0)); RTTI_ASSERT(*f1.target() == h); RTTI_ASSERT(*f2.target() == g); } diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/F.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/F.pass.cpp index c1ad528254af..92409577d60d 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/F.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/F.pass.cpp @@ -69,7 +69,7 @@ int main(int, char**) { std::function f = A(); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f.target()); RTTI_ASSERT(f.target() == 0); } diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_assign.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_assign.pass.cpp index 75eaa55dc71e..e3bd6ef78d61 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_assign.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_assign.pass.cpp @@ -57,13 +57,13 @@ int main(int, char**) { { std::function f = A(); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f.target()); RTTI_ASSERT(f.target() == 0); std::function f2; f2 = f; assert(A::count == 2); - assert(globalMemCounter.checkOutstandingNewEq(2)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(2)); RTTI_ASSERT(f2.target()); RTTI_ASSERT(f2.target() == 0); } @@ -125,13 +125,13 @@ int main(int, char**) { { std::function f = A(); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f.target()); RTTI_ASSERT(f.target() == 0); std::function f2; f2 = std::move(f); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f2.target()); RTTI_ASSERT(f2.target() == 0); RTTI_ASSERT(f.target() == 0); diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_move.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_move.pass.cpp index 4a2a272ae0a3..5b3f4f10cadb 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_move.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/copy_move.pass.cpp @@ -64,12 +64,12 @@ int main(int, char**) { std::function f = A(); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f.target()); RTTI_ASSERT(f.target() == 0); std::function f2 = f; assert(A::count == 2); - assert(globalMemCounter.checkOutstandingNewEq(2)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(2)); RTTI_ASSERT(f2.target()); RTTI_ASSERT(f2.target() == 0); } @@ -113,7 +113,7 @@ int main(int, char**) { // Test rvalue references std::function f = A(); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f.target()); RTTI_ASSERT(f.target() == 0); LIBCPP_ASSERT_NOEXCEPT(std::function(std::move(f))); @@ -122,7 +122,7 @@ int main(int, char**) #endif std::function f2 = std::move(f); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f2.target()); RTTI_ASSERT(f2.target() == 0); RTTI_ASSERT(f.target() == 0); diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/nullptr_t_assign.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/nullptr_t_assign.pass.cpp index 391e2a7434bf..b2f61fa9b68a 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/nullptr_t_assign.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/nullptr_t_assign.pass.cpp @@ -57,7 +57,7 @@ int main(int, char**) { std::function f = A(); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f.target()); f = nullptr; assert(A::count == 0); diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.mod/swap.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.mod/swap.pass.cpp index d51c35ea44fa..1723ddfd33be 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.mod/swap.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.mod/swap.pass.cpp @@ -68,12 +68,12 @@ int main(int, char**) { std::function f1 = A(1); std::function f2 = A(2); assert(A::count == 2); - assert(globalMemCounter.checkOutstandingNewEq(2)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(2)); RTTI_ASSERT(f1.target()->id() == 1); RTTI_ASSERT(f2.target()->id() == 2); f1.swap(f2); assert(A::count == 2); - assert(globalMemCounter.checkOutstandingNewEq(2)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(2)); RTTI_ASSERT(f1.target()->id() == 2); RTTI_ASSERT(f2.target()->id() == 1); } @@ -83,12 +83,12 @@ int main(int, char**) { std::function f1 = A(1); std::function f2 = g; assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f1.target()->id() == 1); RTTI_ASSERT(*f2.target() == g); f1.swap(f2); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(*f1.target() == g); RTTI_ASSERT(f2.target()->id() == 1); } @@ -98,12 +98,12 @@ int main(int, char**) { std::function f1 = g; std::function f2 = A(1); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(*f1.target() == g); RTTI_ASSERT(f2.target()->id() == 1); f1.swap(f2); assert(A::count == 1); - assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(1)); RTTI_ASSERT(f1.target()->id() == 1); RTTI_ASSERT(*f2.target() == g); } diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared.pass.cpp index 23a904f8ae11..be7505f218cd 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared.pass.cpp @@ -96,7 +96,7 @@ int main(int, char**) int i = 67; char c = 'e'; std::shared_ptr p = std::make_shared(i, c); - assert(globalMemCounter.checkOutstandingNewEq(nc+1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(nc+1)); assert(A::count == 1); assert(p->get_int() == 67); assert(p->get_char() == 'e'); @@ -116,7 +116,7 @@ int main(int, char**) { char c = 'e'; std::shared_ptr p = std::make_shared(67, c); - assert(globalMemCounter.checkOutstandingNewEq(nc+1)); + assert(globalMemCounter.checkOutstandingNewLessThanOrEqual(nc+1)); assert(A::count == 1); assert(p->get_int() == 67); assert(p->get_char() == 'e'); diff --git a/libcxx/test/support/count_new.h b/libcxx/test/support/count_new.h index b64248501016..ef4306e520b1 100644 --- a/libcxx/test/support/count_new.h +++ b/libcxx/test/support/count_new.h @@ -181,6 +181,11 @@ public: return disable_checking || n == outstanding_new; } + bool checkOutstandingNewLessThanOrEqual(int n) const + { + return disable_checking || outstanding_new <= n; + } + bool checkOutstandingNewNotEq(int n) const { return disable_checking || n != outstanding_new; diff --git a/libcxx/test/support/test_macros.h b/libcxx/test/support/test_macros.h index ea289f0432e6..5ca4d611e1e4 100644 --- a/libcxx/test/support/test_macros.h +++ b/libcxx/test/support/test_macros.h @@ -283,27 +283,35 @@ struct is_same { enum {value = 1}; }; #endif #if defined(__GNUC__) || defined(__clang__) +// This function can be used to hide some objects from compiler optimizations. +// +// For example, this is useful to hide the result of a call to `new` and ensure +// that the compiler doesn't elide the call to new/delete. Otherwise, elliding +// calls to new/delete is allowed by the Standard and compilers actually do it +// when optimizations are enabled. template -inline -void DoNotOptimize(Tp const& value) { +inline Tp const& DoNotOptimize(Tp const& value) { asm volatile("" : : "r,m"(value) : "memory"); + return value; } template -inline void DoNotOptimize(Tp& value) { +inline Tp& DoNotOptimize(Tp& value) { #if defined(__clang__) asm volatile("" : "+r,m"(value) : : "memory"); #else asm volatile("" : "+m,r"(value) : : "memory"); #endif + return value; } #else #include template -inline void DoNotOptimize(Tp const& value) { +inline Tp const& DoNotOptimize(Tp const& value) { const volatile void* volatile unused = __builtin_addressof(value); static_cast(unused); _ReadWriteBarrier(); + return value; } #endif diff --git a/libcxx/utils/ci/run-buildbot b/libcxx/utils/ci/run-buildbot index 672d5cb70ae8..ed2bc2a14f17 100755 --- a/libcxx/utils/ci/run-buildbot +++ b/libcxx/utils/ci/run-buildbot @@ -522,6 +522,11 @@ generic-abi-unstable) generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-abi-unstable.cmake" check-runtimes ;; +generic-optimized-speed) + clean + generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-optimized-speed.cmake" + check-runtimes +;; apple-system) clean diff --git a/libcxx/utils/libcxx/test/params.py b/libcxx/utils/libcxx/test/params.py index 4e209901f43b..89d9f22e9dc6 100644 --- a/libcxx/utils/libcxx/test/params.py +++ b/libcxx/utils/libcxx/test/params.py @@ -11,7 +11,7 @@ import shlex from pathlib import Path from libcxx.test.dsl import * -from libcxx.test.features import _isMSVC +from libcxx.test.features import _isClang, _isAppleClang, _isGCC, _isMSVC _warningFlags = [ @@ -88,6 +88,28 @@ def getStdFlag(cfg, std): return None +def getSpeedOptimizationFlag(cfg): + if _isClang(cfg) or _isAppleClang(cfg) or _isGCC(cfg): + return "-O3" + elif _isMSVC(cfg): + return "/O2" + else: + raise RuntimeError( + "Can't figure out what compiler is used in the configuration" + ) + + +def getSizeOptimizationFlag(cfg): + if _isClang(cfg) or _isAppleClang(cfg) or _isGCC(cfg): + return "-Os" + elif _isMSVC(cfg): + return "/O1" + else: + raise RuntimeError( + "Can't figure out what compiler is used in the configuration" + ) + + # fmt: off DEFAULT_PARAMETERS = [ Parameter( @@ -118,6 +140,18 @@ DEFAULT_PARAMETERS = [ AddCompileFlag(lambda cfg: getStdFlag(cfg, std)), ], ), + Parameter( + name="optimization", + choices=["none", "speed", "size"], + type=str, + help="The optimization level to use when compiling the test suite.", + default="none", + actions=lambda opt: filter(None, [ + AddCompileFlag(lambda cfg: getSpeedOptimizationFlag(cfg)) if opt == "speed" else None, + AddCompileFlag(lambda cfg: getSizeOptimizationFlag(cfg)) if opt == "size" else None, + AddFeature(f'optimization={opt}'), + ]), + ), Parameter( name="enable_modules", choices=["none", "clang", "clang-lsv"], diff --git a/libunwind/test/libunwind_02.pass.cpp b/libunwind/test/libunwind_02.pass.cpp index ea34cd54222c..9fd8e5d7159c 100644 --- a/libunwind/test/libunwind_02.pass.cpp +++ b/libunwind/test/libunwind_02.pass.cpp @@ -21,7 +21,8 @@ #define EXPECTED_NUM_FRAMES 50 #define NUM_FRAMES_UPPER_BOUND 100 -_Unwind_Reason_Code callback(_Unwind_Context *context, void *cnt) { +__attribute__((noinline)) _Unwind_Reason_Code callback(_Unwind_Context *context, + void *cnt) { (void)context; int *i = (int *)cnt; ++*i; @@ -31,7 +32,7 @@ _Unwind_Reason_Code callback(_Unwind_Context *context, void *cnt) { return _URC_NO_REASON; } -void test_backtrace() { +__attribute__((noinline)) void test_backtrace() { int n = 0; _Unwind_Backtrace(&callback, &n); if (n < EXPECTED_NUM_FRAMES) { @@ -39,17 +40,34 @@ void test_backtrace() { } } -int test(int i) { +// These functions are effectively the same, but we have to be careful to avoid +// unwanted optimizations that would mess with the number of frames we expect. +// Surprisingly, slapping `noinline` is not sufficient -- we also have to avoid +// writing the function in a way that the compiler can easily spot tail +// recursion. +__attribute__((noinline)) int test1(int i); +__attribute__((noinline)) int test2(int i); + +__attribute__((noinline)) int test1(int i) { + if (i == 0) { + test_backtrace(); + return 0; + } else { + return i + test2(i - 1); + } +} + +__attribute__((noinline)) int test2(int i) { if (i == 0) { test_backtrace(); return 0; } else { - return i + test(i - 1); + return i + test1(i - 1); } } int main(int, char**) { - int total = test(50); + int total = test1(50); assert(total == 1275); return 0; } diff --git a/libunwind/test/unw_resume.pass.cpp b/libunwind/test/unw_resume.pass.cpp index 08e8d4edeaf2..2b7470b5cad0 100644 --- a/libunwind/test/unw_resume.pass.cpp +++ b/libunwind/test/unw_resume.pass.cpp @@ -15,7 +15,7 @@ #include -void test_unw_resume() { +__attribute__((noinline)) void test_unw_resume() { unw_context_t context; unw_cursor_t cursor; diff --git a/libunwind/test/unwind_leaffunction.pass.cpp b/libunwind/test/unwind_leaffunction.pass.cpp index 8c9912e3c386..112a5968247a 100644 --- a/libunwind/test/unwind_leaffunction.pass.cpp +++ b/libunwind/test/unwind_leaffunction.pass.cpp @@ -28,7 +28,7 @@ _Unwind_Reason_Code frame_handler(struct _Unwind_Context* ctx, void* arg) { (void)arg; Dl_info info = { 0, 0, 0, 0 }; - // Unwind until the main is reached, above frames deeped on the platform and + // Unwind until the main is reached, above frames depend on the platform and // architecture. if (dladdr(reinterpret_cast(_Unwind_GetIP(ctx)), &info) && info.dli_sname && !strcmp("main", info.dli_sname)) { @@ -43,18 +43,22 @@ void signal_handler(int signum) { _Exit(-1); } -__attribute__((noinline)) void crashing_leaf_func(void) { +__attribute__((noinline)) void crashing_leaf_func(int do_trap) { // libunwind searches for the address before the return address which points - // to the trap instruction. NOP guarantees the trap instruction is not the - // first instruction of the function. - // We should keep this here for other unwinders that also decrement pc. - __asm__ __volatile__("nop"); - __builtin_trap(); + // to the trap instruction. We make the trap conditional and prevent inlining + // of the function to ensure that the compiler doesn't remove the `ret` + // instruction altogether. + // + // It's also important that the trap instruction isn't the first instruction + // in the function (which it isn't because of the branch) for other unwinders + // that also decrement pc. + if (do_trap) + __builtin_trap(); } int main(int, char**) { signal(SIGTRAP, signal_handler); signal(SIGILL, signal_handler); - crashing_leaf_func(); + crashing_leaf_func(1); return -2; } -- GitLab From 2aec7083ada09c8b8a0aad79492cbedcf8f9fbb7 Mon Sep 17 00:00:00 2001 From: Guray Ozen Date: Tue, 9 Jan 2024 16:44:25 +0100 Subject: [PATCH 213/652] [mlir][gpu] Use DenseI32Array for NVVM's maxntid and reqntid (NFC) (#77466) --- mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp | 2 +- mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 10 ++-------- .../LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp | 10 ++++------ mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir | 2 +- mlir/test/Target/LLVMIR/nvvmir.mlir | 10 +++++----- 5 files changed, 13 insertions(+), 21 deletions(-) diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp index eeb8fbbb180b..ae2bd8e5b540 100644 --- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp +++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp @@ -100,7 +100,7 @@ GPUFuncOpLowering::matchAndRewrite(gpu::GPUFuncOp gpuFuncOp, OpAdaptor adaptor, // If any of the dimensions are missing, fill them in with 1. attributes.emplace_back( kernelBlockSizeAttributeName.value(), - rewriter.getI32ArrayAttr( + rewriter.getDenseI32ArrayAttr( {dimX.value_or(1), dimY.value_or(1), dimZ.value_or(1)})); } } diff --git a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp index a4de89d928e1..aa49c4dc31fb 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp @@ -1060,19 +1060,13 @@ LogicalResult NVVMDialect::verifyOperationAttribute(Operation *op, // If maxntid and reqntid exist, it must be an array with max 3 dim if (attrName == NVVMDialect::getMaxntidAttrName() || attrName == NVVMDialect::getReqntidAttrName()) { - auto values = llvm::dyn_cast(attr.getValue()); + auto values = llvm::dyn_cast(attr.getValue()); if (!values || values.empty() || values.size() > 3) return op->emitError() << "'" << attrName << "' attribute must be integer array with maximum 3 index"; - for (auto val : llvm::cast(attr.getValue())) { - if (!llvm::dyn_cast(val)) - return op->emitError() - << "'" << attrName - << "' attribute must be integer array with maximum 3 index"; - } } - // If minctasm and maxnreg exist, it must be an array with max 3 dim + // If minctasm and maxnreg exist, it must be an integer attribute if (attrName == NVVMDialect::getMinctasmAttrName() || attrName == NVVMDialect::getMaxnregAttrName()) { if (!llvm::dyn_cast(attr.getValue())) diff --git a/mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp index 0d6bca5e2203..45eb8402a734 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp @@ -163,20 +163,18 @@ public: ->addOperand(llvmMetadataNode); }; if (attribute.getName() == NVVM::NVVMDialect::getMaxntidAttrName()) { - if (!dyn_cast(attribute.getValue())) + if (!dyn_cast(attribute.getValue())) return failure(); - SmallVector values = - extractFromIntegerArrayAttr(attribute.getValue()); + auto values = cast(attribute.getValue()); generateMetadata(values[0], NVVM::NVVMDialect::getMaxntidXName()); if (values.size() > 1) generateMetadata(values[1], NVVM::NVVMDialect::getMaxntidYName()); if (values.size() > 2) generateMetadata(values[2], NVVM::NVVMDialect::getMaxntidZName()); } else if (attribute.getName() == NVVM::NVVMDialect::getReqntidAttrName()) { - if (!dyn_cast(attribute.getValue())) + if (!dyn_cast(attribute.getValue())) return failure(); - SmallVector values = - extractFromIntegerArrayAttr(attribute.getValue()); + auto values = cast(attribute.getValue()); generateMetadata(values[0], NVVM::NVVMDialect::getReqntidXName()); if (values.size() > 1) generateMetadata(values[1], NVVM::NVVMDialect::getReqntidYName()); diff --git a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir index c7f1d4f124c1..66630d33d118 100644 --- a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir +++ b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir @@ -629,7 +629,7 @@ gpu.module @test_module_31 { gpu.module @gpumodule { // CHECK-LABEL: func @kernel_with_block_size() -// CHECK: attributes {gpu.kernel, gpu.known_block_size = array, nvvm.kernel, nvvm.maxntid = [128 : i32, 1 : i32, 1 : i32]} +// CHECK: attributes {gpu.kernel, gpu.known_block_size = array, nvvm.kernel, nvvm.maxntid = array} gpu.func @kernel_with_block_size() kernel attributes {gpu.known_block_size = array} { gpu.return } diff --git a/mlir/test/Target/LLVMIR/nvvmir.mlir b/mlir/test/Target/LLVMIR/nvvmir.mlir index 6076fce598fb..f83be9dbb2ff 100644 --- a/mlir/test/Target/LLVMIR/nvvmir.mlir +++ b/mlir/test/Target/LLVMIR/nvvmir.mlir @@ -398,7 +398,7 @@ llvm.func @kernel_func() attributes {nvvm.kernel} { // ----- -llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = [1,23,32]} { +llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = array} { llvm.return } @@ -410,7 +410,7 @@ llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = [1,23,32]} { // CHECK: {ptr @kernel_func, !"maxntidz", i32 32} // ----- -llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.reqntid = [1,23,32]} { +llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.reqntid = array} { llvm.return } @@ -442,7 +442,7 @@ llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxnreg = 16} { // CHECK: {ptr @kernel_func, !"maxnreg", i32 16} // ----- -llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = [1,23,32], +llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = array, nvvm.minctasm = 16, nvvm.maxnreg = 32} { llvm.return } @@ -472,13 +472,13 @@ nvvm.maxnreg = "boo"} { } // ----- // expected-error @below {{'"nvvm.reqntid"' attribute must be integer array with maximum 3 index}} -llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.reqntid = [3,4,5,6]} { +llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.reqntid = array} { llvm.return } // ----- // expected-error @below {{'"nvvm.maxntid"' attribute must be integer array with maximum 3 index}} -llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = [3,4,5,6]} { +llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = array} { llvm.return } -- GitLab From 4b7e861d136d941d86b234fbcef520fd798b26fa Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Tue, 9 Jan 2024 23:48:02 +0800 Subject: [PATCH 214/652] [clang]use correct this scope to evaluate noexcept expr (#77416) Fixes: #77411 When substituting deduced type, noexcept expr in method should be instantiated and evaluated. ThisScrope should be switched to method context instead of origin sema context --- clang/docs/ReleaseNotes.rst | 3 ++- clang/lib/Sema/TreeTransform.h | 7 +++++++ .../test/SemaCXX/cxx1z-noexcept-function-type.cpp | 15 +++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 1b2d7c86a962..c89488e54ef4 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -610,7 +610,8 @@ Bug Fixes in This Version of template classes. Fixes (`#68543 `_, `#42496 `_, - `#77071 `_) + `#77071 `_, + `#77411 `_) - Fixed an issue when a shift count larger than ``__INT64_MAX__``, in a right shift operation, could result in missing warnings about ``shift count >= width of type`` or internal compiler error. diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index c8c5a51bf9f9..e7a6550b1c99 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -6192,6 +6192,13 @@ bool TreeTransform::TransformExceptionSpec( // Instantiate a dynamic noexcept expression, if any. if (isComputedNoexcept(ESI.Type)) { + // Update this scrope because ContextDecl in Sema will be used in + // TransformExpr. + auto *Method = dyn_cast_if_present(ESI.SourceTemplate); + Sema::CXXThisScopeRAII ThisScope( + SemaRef, Method ? Method->getParent() : nullptr, + Method ? Method->getMethodQualifiers() : Qualifiers{}, + Method != nullptr); EnterExpressionEvaluationContext Unevaluated( getSema(), Sema::ExpressionEvaluationContext::ConstantEvaluated); ExprResult NoexceptExpr = getDerived().TransformExpr(ESI.NoexceptExpr); diff --git a/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp b/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp index 11b1093f9064..5e56f19477d6 100644 --- a/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp +++ b/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp @@ -64,6 +64,21 @@ namespace DependentDefaultCtorExceptionSpec { struct A { multimap Map; } a; static_assert(noexcept(A())); + + template struct NoexceptWithThis { + int ca; + template auto foo(T) noexcept(ca) { return true; } + // expected-error@-1 {{noexcept specifier argument is not a constant expression}} + // expected-note@-2 {{in instantiation of exception specification}} + // expected-note@-3 {{implicit use of 'this' pointer is only allowed within the evaluation of a call to a 'constexpr' member function}} + }; + struct InstantiateFromAnotherClass { + template (&B::foo))> // expected-note {{in instantiation of function template specialization}} + InstantiateFromAnotherClass(B *) {} // expected-note {{in instantiation of default argument}} + }; + NoexceptWithThis f{}; + // Don't crash here. + InstantiateFromAnotherClass b{&f}; // expected-note {{while substituting deduced template arguments into function template}} } #endif -- GitLab From 7f9e3bf062a4aa36ed5350282cc1c307641145f0 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Tue, 9 Jan 2024 10:50:28 -0500 Subject: [PATCH 215/652] [gn] port 07c9189fcc06 (DWARFLinker/Classic) --- .../gn/secondary/bolt/lib/Rewrite/BUILD.gn | 1 + .../secondary/llvm/lib/DWARFLinker/BUILD.gn | 13 +++--------- .../llvm/lib/DWARFLinker/Classic/BUILD.gn | 20 +++++++++++++++++++ .../Parallel}/BUILD.gn | 5 ++--- .../gn/secondary/llvm/tools/dsymutil/BUILD.gn | 3 ++- .../llvm/tools/llvm-dwarfutil/BUILD.gn | 3 ++- .../unittests/DWARFLinkerParallel/BUILD.gn | 2 +- 7 files changed, 31 insertions(+), 16 deletions(-) create mode 100644 llvm/utils/gn/secondary/llvm/lib/DWARFLinker/Classic/BUILD.gn rename llvm/utils/gn/secondary/llvm/lib/{DWARFLinkerParallel => DWARFLinker/Parallel}/BUILD.gn (87%) diff --git a/llvm/utils/gn/secondary/bolt/lib/Rewrite/BUILD.gn b/llvm/utils/gn/secondary/bolt/lib/Rewrite/BUILD.gn index 364e2c52953d..13fd39c13023 100644 --- a/llvm/utils/gn/secondary/bolt/lib/Rewrite/BUILD.gn +++ b/llvm/utils/gn/secondary/bolt/lib/Rewrite/BUILD.gn @@ -11,6 +11,7 @@ static_library("Rewrite") { "//bolt/lib/Utils", "//llvm/lib/CodeGen/AsmPrinter", "//llvm/lib/DWARFLinker", + "//llvm/lib/DWARFLinker/Classic", "//llvm/lib/DWP", "//llvm/lib/DebugInfo/DWARF", "//llvm/lib/ExecutionEngine/JITLink", diff --git a/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/BUILD.gn index 58829e924cea..1540e7b4165b 100644 --- a/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/BUILD.gn @@ -1,18 +1,11 @@ static_library("DWARFLinker") { - output_name = "LLVMDWARFLinker" + output_name = "LLVMDWARFLinkerBase" deps = [ + "//llvm/lib/BinaryFormat", "//llvm/lib/CodeGen", - "//llvm/lib/CodeGen/AsmPrinter", "//llvm/lib/DebugInfo/DWARF", - "//llvm/lib/MC", "//llvm/lib/Object", "//llvm/lib/Support", - "//llvm/lib/TargetParser", - ] - sources = [ - "DWARFLinker.cpp", - "DWARFLinkerCompileUnit.cpp", - "DWARFLinkerDeclContext.cpp", - "DWARFStreamer.cpp", ] + sources = [ "Utils.cpp" ] } diff --git a/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/Classic/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/Classic/BUILD.gn new file mode 100644 index 000000000000..b3a8e0331e68 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/Classic/BUILD.gn @@ -0,0 +1,20 @@ +static_library("Classic") { + output_name = "LLVMDWARFLinker" + deps = [ + "//llvm/lib/BinaryFormat", + "//llvm/lib/CodeGen", + "//llvm/lib/CodeGen/AsmPrinter", + "//llvm/lib/DWARFLinker", + "//llvm/lib/DebugInfo/DWARF", + "//llvm/lib/MC", + "//llvm/lib/Object", + "//llvm/lib/Support", + "//llvm/lib/TargetParser", + ] + sources = [ + "DWARFLinker.cpp", + "DWARFLinkerCompileUnit.cpp", + "DWARFLinkerDeclContext.cpp", + "DWARFStreamer.cpp", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/DWARFLinkerParallel/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/Parallel/BUILD.gn similarity index 87% rename from llvm/utils/gn/secondary/llvm/lib/DWARFLinkerParallel/BUILD.gn rename to llvm/utils/gn/secondary/llvm/lib/DWARFLinker/Parallel/BUILD.gn index 919e07d6e33c..117508a5cc92 100644 --- a/llvm/utils/gn/secondary/llvm/lib/DWARFLinkerParallel/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/DWARFLinker/Parallel/BUILD.gn @@ -1,9 +1,10 @@ -static_library("DWARFLinkerParallel") { +static_library("Parallel") { output_name = "LLVMDWARFLinkerParallel" deps = [ "//llvm/lib/BinaryFormat", "//llvm/lib/CodeGen", "//llvm/lib/CodeGen/AsmPrinter", + "//llvm/lib/DWARFLinker", "//llvm/lib/DebugInfo/DWARF", "//llvm/lib/MC", "//llvm/lib/Object", @@ -13,7 +14,6 @@ static_library("DWARFLinkerParallel") { "AcceleratorRecordsSaver.cpp", "DIEAttributeCloner.cpp", "DWARFEmitterImpl.cpp", - "DWARFFile.cpp", "DWARFLinker.cpp", "DWARFLinkerCompileUnit.cpp", "DWARFLinkerImpl.cpp", @@ -21,7 +21,6 @@ static_library("DWARFLinkerParallel") { "DWARFLinkerUnit.cpp", "DependencyTracker.cpp", "OutputSections.cpp", - "StringPool.cpp", "SyntheticTypeNameBuilder.cpp", ] } diff --git a/llvm/utils/gn/secondary/llvm/tools/dsymutil/BUILD.gn b/llvm/utils/gn/secondary/llvm/tools/dsymutil/BUILD.gn index e962d100f217..d22d0433656e 100644 --- a/llvm/utils/gn/secondary/llvm/tools/dsymutil/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/tools/dsymutil/BUILD.gn @@ -11,7 +11,8 @@ driver_executable("dsymutil") { ":Options", "//llvm/lib/CodeGen/AsmPrinter", "//llvm/lib/DWARFLinker", - "//llvm/lib/DWARFLinkerParallel", + "//llvm/lib/DWARFLinker/Classic", + "//llvm/lib/DWARFLinker/Parallel", "//llvm/lib/DebugInfo/DWARF", "//llvm/lib/MC", "//llvm/lib/Object", diff --git a/llvm/utils/gn/secondary/llvm/tools/llvm-dwarfutil/BUILD.gn b/llvm/utils/gn/secondary/llvm/tools/llvm-dwarfutil/BUILD.gn index 4f75212b4091..3654acef9fdf 100644 --- a/llvm/utils/gn/secondary/llvm/tools/llvm-dwarfutil/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/tools/llvm-dwarfutil/BUILD.gn @@ -10,7 +10,8 @@ executable("llvm-dwarfutil") { ":Options", "//llvm/lib/CodeGen", "//llvm/lib/DWARFLinker", - "//llvm/lib/DWARFLinkerParallel", + "//llvm/lib/DWARFLinker/Classic", + "//llvm/lib/DWARFLinker/Parallel", "//llvm/lib/DebugInfo/DWARF", "//llvm/lib/MC", "//llvm/lib/ObjCopy", diff --git a/llvm/utils/gn/secondary/llvm/unittests/DWARFLinkerParallel/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/DWARFLinkerParallel/BUILD.gn index 48daaed3af76..9a39de49b95c 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/DWARFLinkerParallel/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/DWARFLinkerParallel/BUILD.gn @@ -2,7 +2,7 @@ import("//third-party/unittest/unittest.gni") unittest("DWARFLinkerParallelTests") { deps = [ - "//llvm/lib/DWARFLinkerParallel", + "//llvm/lib/DWARFLinker/Parallel", "//llvm/lib/Support", "//llvm/lib/Testing/Support", ] -- GitLab From ec56c922ab257845538215f21cac00cf278fbd04 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Tue, 9 Jan 2024 10:54:57 -0500 Subject: [PATCH 216/652] [gn] port 07c9189fcc06 --- llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn b/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn index bd88978c105c..0028c2cb6739 100644 --- a/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn +++ b/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn @@ -5,6 +5,7 @@ copy("include") { "fuzzer/FuzzedDataProvider.h", "orc_rt/c_api.h", "profile/InstrProfData.inc", + "profile/instr_prof_interface.h", "profile/MemProfData.inc", "sanitizer/allocator_interface.h", "sanitizer/asan_interface.h", -- GitLab From f7cb1afa06335edfc043cb5f11f97907e9df844c Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Tue, 9 Jan 2024 10:58:21 -0500 Subject: [PATCH 217/652] [gn] Make sync script print github URLs Phab no longer knows about new revisions. --- llvm/utils/gn/build/sync_source_lists_from_cmake.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/utils/gn/build/sync_source_lists_from_cmake.py b/llvm/utils/gn/build/sync_source_lists_from_cmake.py index 6b48ca7de869..411f8f762430 100755 --- a/llvm/utils/gn/build/sync_source_lists_from_cmake.py +++ b/llvm/utils/gn/build/sync_source_lists_from_cmake.py @@ -123,7 +123,8 @@ def sync_source_lists(write): # Output necessary changes grouped by revision. for rev in sorted(changes_by_rev): - print("[gn build] Port {0} -- https://reviews.llvm.org/rG{0}".format(rev)) + commit_url = 'https://github.com/llvm/llvm-project/commit/' + print("[gn build] Port {0} -- {1}/{0}".format(rev, commit_url)) for gn_file, data in sorted(changes_by_rev[rev].items()): add = data.get("add", []) remove = data.get("remove", []) -- GitLab From 4ea5c603b4c4db36b8ee7e04adf96416f4d996dc Mon Sep 17 00:00:00 2001 From: Michael Buch Date: Tue, 9 Jan 2024 16:02:56 +0000 Subject: [PATCH 218/652] [lldb][Type] Add TypeQuery::SetLanguages API (#75926) This is required for users of `TypeQuery` that limit the set of languages of the query using APIs such as `GetSupportedLanguagesForTypes` or `GetSupportedLanguagesForExpressions`. Example usage: https://github.com/apple/llvm-project/pull/7885 --- lldb/include/lldb/Symbol/Type.h | 4 ++++ lldb/source/Symbol/Type.cpp | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/lldb/include/lldb/Symbol/Type.h b/lldb/include/lldb/Symbol/Type.h index 307be6c55e01..acd1a769f13c 100644 --- a/lldb/include/lldb/Symbol/Type.h +++ b/lldb/include/lldb/Symbol/Type.h @@ -247,6 +247,10 @@ public: /// match. void AddLanguage(lldb::LanguageType language); + /// Set the list of languages that should produce a match to only the ones + /// specified in \ref languages. + void SetLanguages(LanguageSet languages); + /// Check if the language matches any languages that have been added to this /// match object. /// diff --git a/lldb/source/Symbol/Type.cpp b/lldb/source/Symbol/Type.cpp index 293fe1b78f4a..6069d066eaf6 100644 --- a/lldb/source/Symbol/Type.cpp +++ b/lldb/source/Symbol/Type.cpp @@ -145,6 +145,10 @@ void TypeQuery::AddLanguage(LanguageType language) { m_languages->Insert(language); } +void TypeQuery::SetLanguages(LanguageSet languages) { + m_languages = std::move(languages); +} + bool TypeQuery::ContextMatches( llvm::ArrayRef context_chain) const { if (GetExactMatch() || context_chain.size() == m_context.size()) -- GitLab From b5f2db940643af3837c77adde1dadb7208922211 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Tue, 9 Jan 2024 17:19:10 +0100 Subject: [PATCH 219/652] [lldb][libc++] Adds some C++20 calendar data formatters. (#76983) This adds a subset of the C++20 calendar data formatters: - day, - month, - year, - month_day, - month_day_last, and - year_month_day. A followup patch will add the missing calendar data formatters: - weekday, - weekday_indexed, - weekday_last, - month_weekday, - month_weekday_last, - year_month, - year_month_day_last - year_month_weekday, and - year_month_weekday_last. --- .../Language/CPlusPlus/CPlusPlusLanguage.cpp | 35 ++++++++++ .../Plugins/Language/CPlusPlus/LibCxx.cpp | 57 ++++++++++++++++ .../Plugins/Language/CPlusPlus/LibCxx.h | 8 +++ .../chrono/TestDataFormatterLibcxxChrono.py | 67 +++++++++++++++++++ .../data-formatter-stl/libcxx/chrono/main.cpp | 54 +++++++++++++++ 5 files changed, 221 insertions(+) diff --git a/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp b/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp index 586cc08a6f12..c6937ebca319 100644 --- a/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp +++ b/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp @@ -1031,6 +1031,41 @@ static void LoadLibCxxFormatters(lldb::TypeCategoryImplSP cpp_category_sp) { "^std::__[[:alnum:]]+::chrono::seconds", eFormatterMatchRegex, TypeSummaryImplSP(new StringSummaryFormat( eTypeOptionHideChildren | eTypeOptionHideValue, "${var.__rep_} s"))); + + // Chrono calendar types + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::day$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "day=${var.__d_%u}"))); + AddCXXSummary(cpp_category_sp, + lldb_private::formatters::LibcxxChronoMonthSummaryProvider, + "libc++ std::chrono::month summary provider", + "^std::__[[:alnum:]]+::chrono::month$", + eTypeOptionHideChildren | eTypeOptionHideValue, true); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::year$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat( + eTypeOptionHideChildren | eTypeOptionHideValue, "year=${var.__y_}"))); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::month_day$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "${var.__m_} ${var.__d_}"))); + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::month_day_last$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "${var.__m_} day=last"))); + AddCXXSummary( + cpp_category_sp, + lldb_private::formatters::LibcxxChronoYearMonthDaySummaryProvider, + "libc++ std::chrono::year_month_day summary provider", + "^std::__[[:alnum:]]+::chrono::year_month_day$", + eTypeOptionHideChildren | eTypeOptionHideValue, true); } static void LoadLibStdcppFormatters(lldb::TypeCategoryImplSP cpp_category_sp) { diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp index cae17ef992b2..f8be4f785dc4 100644 --- a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp +++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp @@ -1084,3 +1084,60 @@ bool lldb_private::formatters::LibcxxWStringViewSummaryProvider( return ::LibcxxWStringSummaryProvider(valobj, stream, summary_options, dataobj, size); } + +bool lldb_private::formatters::LibcxxChronoMonthSummaryProvider( + ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { + // FIXME: These are the names used in the C++20 ostream operator. Since LLVM + // uses C++17 it's not possible to use the ostream operator directly. + static const std::array months = { + "January", "February", "March", "April", "May", "June", + "July", "August", "September", "October", "November", "December"}; + + ValueObjectSP ptr_sp = valobj.GetChildMemberWithName("__m_"); + if (!ptr_sp) + return false; + + const unsigned month = ptr_sp->GetValueAsUnsigned(0); + if (month >= 1 && month <= 12) + stream << "month=" << months[month - 1]; + else + stream.Printf("month=%u", month); + + return true; +} + +bool lldb_private::formatters::LibcxxChronoYearMonthDaySummaryProvider( + ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { + ValueObjectSP ptr_sp = valobj.GetChildMemberWithName("__y_"); + if (!ptr_sp) + return false; + ptr_sp = ptr_sp->GetChildMemberWithName("__y_"); + if (!ptr_sp) + return false; + int year = ptr_sp->GetValueAsSigned(0); + + ptr_sp = valobj.GetChildMemberWithName("__m_"); + if (!ptr_sp) + return false; + ptr_sp = ptr_sp->GetChildMemberWithName("__m_"); + if (!ptr_sp) + return false; + const unsigned month = ptr_sp->GetValueAsUnsigned(0); + + ptr_sp = valobj.GetChildMemberWithName("__d_"); + if (!ptr_sp) + return false; + ptr_sp = ptr_sp->GetChildMemberWithName("__d_"); + if (!ptr_sp) + return false; + const unsigned day = ptr_sp->GetValueAsUnsigned(0); + + stream << "date="; + if (year < 0) { + stream << '-'; + year = -year; + } + stream.Printf("%04d-%02u-%02u", year, month, day); + + return true; +} diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h index f65801e2cb1b..c252ae382dd9 100644 --- a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h +++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h @@ -261,6 +261,14 @@ SyntheticChildrenFrontEnd * LibcxxStdRangesRefViewSyntheticFrontEndCreator(CXXSyntheticChildren *, lldb::ValueObjectSP); +bool LibcxxChronoMonthSummaryProvider( + ValueObject &valobj, Stream &stream, + const TypeSummaryOptions &options); // libc++ std::chrono::month + +bool LibcxxChronoYearMonthDaySummaryProvider( + ValueObject &valobj, Stream &stream, + const TypeSummaryOptions &options); // libc++ std::chrono::year_month_day + } // namespace formatters } // namespace lldb_private diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py index b2f86817f3b0..38a31d2ddb45 100644 --- a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py +++ b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py @@ -32,3 +32,70 @@ class LibcxxChronoDataFormatterTestCase(TestBase): self.expect("frame variable m", substrs=["m = 4321 months"]) self.expect("frame variable y", substrs=["y = 321 years"]) + self.expect("frame variable d_0", substrs=["d_0 = day=0"]) + self.expect("frame variable d_1", substrs=["d_1 = day=1"]) + self.expect("frame variable d_31", substrs=["d_31 = day=31"]) + self.expect("frame variable d_255", substrs=["d_255 = day=255"]) + + self.expect("frame variable jan", substrs=["jan = month=January"]) + self.expect("frame variable feb", substrs=["feb = month=February"]) + self.expect("frame variable mar", substrs=["mar = month=March"]) + self.expect("frame variable apr", substrs=["apr = month=April"]) + self.expect("frame variable may", substrs=["may = month=May"]) + self.expect("frame variable jun", substrs=["jun = month=June"]) + self.expect("frame variable jul", substrs=["jul = month=July"]) + self.expect("frame variable aug", substrs=["aug = month=August"]) + self.expect("frame variable sep", substrs=["sep = month=September"]) + self.expect("frame variable oct", substrs=["oct = month=October"]) + self.expect("frame variable nov", substrs=["nov = month=November"]) + self.expect("frame variable dec", substrs=["dec = month=December"]) + + self.expect("frame variable month_0", substrs=["month_0 = month=0"]) + self.expect("frame variable month_1", substrs=["month_1 = month=January"]) + self.expect("frame variable month_2", substrs=["month_2 = month=February"]) + self.expect("frame variable month_3", substrs=["month_3 = month=March"]) + self.expect("frame variable month_4", substrs=["month_4 = month=April"]) + self.expect("frame variable month_5", substrs=["month_5 = month=May"]) + self.expect("frame variable month_6", substrs=["month_6 = month=June"]) + self.expect("frame variable month_7", substrs=["month_7 = month=July"]) + self.expect("frame variable month_8", substrs=["month_8 = month=August"]) + self.expect("frame variable month_9", substrs=["month_9 = month=September"]) + self.expect("frame variable month_10", substrs=["month_10 = month=October"]) + self.expect("frame variable month_11", substrs=["month_11 = month=November"]) + self.expect("frame variable month_12", substrs=["month_12 = month=December"]) + self.expect("frame variable month_13", substrs=["month_13 = month=13"]) + self.expect("frame variable month_255", substrs=["month_255 = month=255"]) + + self.expect("frame variable y_min", substrs=["y_min = year=-32767"]) + self.expect("frame variable y_0", substrs=["y_0 = year=0"]) + self.expect("frame variable y_1970", substrs=["y_1970 = year=1970"]) + self.expect("frame variable y_2038", substrs=["y_2038 = year=2038"]) + self.expect("frame variable y_max", substrs=["y_max = year=32767"]) + + self.expect( + "frame variable md_new_years_eve", + substrs=["md_new_years_eve = month=December day=31"], + ) + self.expect( + "frame variable md_new_year", substrs=["md_new_year = month=January day=1"] + ) + self.expect( + "frame variable md_invalid", substrs=["md_invalid = month=255 day=255"] + ) + + self.expect( + "frame variable mdl_jan", substrs=["mdl_jan = month=January day=last"] + ) + self.expect( + "frame variable mdl_new_years_eve", + substrs=["mdl_new_years_eve = month=December day=last"], + ) + + self.expect("frame variable ymd_bc", substrs=["ymd_bc = date=-0001-03-255"]) + self.expect( + "frame variable ymd_year_zero", substrs=["ymd_year_zero = date=0000-255-25"] + ) + self.expect( + "frame variable ymd_unix_epoch", + substrs=["ymd_unix_epoch = date=1970-01-01"], + ) diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/main.cpp b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/main.cpp index 9eba7daa2940..9aa011c97d0c 100644 --- a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/main.cpp +++ b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/main.cpp @@ -15,5 +15,59 @@ int main() { std::chrono::months m{4321}; std::chrono::years y{321}; + std::chrono::day d_0{0}; + std::chrono::day d_1{1}; + std::chrono::day d_31{31}; + std::chrono::day d_255{255}; + + std::chrono::month jan = std::chrono::January; + std::chrono::month feb = std::chrono::February; + std::chrono::month mar = std::chrono::March; + std::chrono::month apr = std::chrono::April; + std::chrono::month may = std::chrono::May; + std::chrono::month jun = std::chrono::June; + std::chrono::month jul = std::chrono::July; + std::chrono::month aug = std::chrono::August; + std::chrono::month sep = std::chrono::September; + std::chrono::month oct = std::chrono::October; + std::chrono::month nov = std::chrono::November; + std::chrono::month dec = std::chrono::December; + + std::chrono::month month_0{0}; + std::chrono::month month_1{1}; + std::chrono::month month_2{2}; + std::chrono::month month_3{3}; + std::chrono::month month_4{4}; + std::chrono::month month_5{5}; + std::chrono::month month_6{6}; + std::chrono::month month_7{7}; + std::chrono::month month_8{8}; + std::chrono::month month_9{9}; + std::chrono::month month_10{10}; + std::chrono::month month_11{11}; + std::chrono::month month_12{12}; + std::chrono::month month_13{13}; + std::chrono::month month_255{255}; + + std::chrono::year y_min{std::chrono::year::min()}; + std::chrono::year y_0{0}; + std::chrono::year y_1970{1970}; + std::chrono::year y_2038{2038}; + std::chrono::year y_max{std::chrono::year::max()}; + + std::chrono::month_day md_new_years_eve{std::chrono::December / 31}; + std::chrono::month_day md_new_year{std::chrono::January / 1}; + std::chrono::month_day md_invalid{std::chrono::month{255} / 255}; + + std::chrono::month_day_last mdl_jan{std::chrono::January}; + std::chrono::month_day_last mdl_new_years_eve{std::chrono::December}; + + std::chrono::year_month_day ymd_bc{std::chrono::year{-1}, std::chrono::March, + std::chrono::day{255}}; + std::chrono::year_month_day ymd_year_zero{ + std::chrono::year{0}, std::chrono::month{255}, std::chrono::day{25}}; + std::chrono::year_month_day ymd_unix_epoch{ + std::chrono::year{1970}, std::chrono::January, std::chrono::day{1}}; + std::cout << "break here\n"; } -- GitLab From 51bf0dff53fdaca25f30d30a1c99462c7afdce74 Mon Sep 17 00:00:00 2001 From: Shan Huang <52285902006@stu.ecnu.edu.cn> Date: Wed, 10 Jan 2024 00:26:43 +0800 Subject: [PATCH 220/652] [GVNSink] Skip debug intrinsics when identifying sinking candidates (#77419) Fixes #77147. --- llvm/lib/Transforms/Scalar/GVNSink.cpp | 6 +- .../GVNSink/sink-ignore-dbg-intrinsics.ll | 86 +++++++++++++++++++ 2 files changed, 89 insertions(+), 3 deletions(-) create mode 100644 llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll diff --git a/llvm/lib/Transforms/Scalar/GVNSink.cpp b/llvm/lib/Transforms/Scalar/GVNSink.cpp index 2b38831139a5..9db66b3793b8 100644 --- a/llvm/lib/Transforms/Scalar/GVNSink.cpp +++ b/llvm/lib/Transforms/Scalar/GVNSink.cpp @@ -132,7 +132,7 @@ public: ActiveBlocks.remove(BB); continue; } - Insts.push_back(BB->getTerminator()->getPrevNode()); + Insts.push_back(BB->getTerminator()->getPrevNonDebugInstruction()); } if (Insts.empty()) Fail = true; @@ -168,7 +168,7 @@ public: if (Inst == &Inst->getParent()->front()) ActiveBlocks.remove(Inst->getParent()); else - NewInsts.push_back(Inst->getPrevNode()); + NewInsts.push_back(Inst->getPrevNonDebugInstruction()); } if (NewInsts.empty()) { Fail = true; @@ -834,7 +834,7 @@ void GVNSink::sinkLastInstruction(ArrayRef Blocks, BasicBlock *BBEnd) { SmallVector Insts; for (BasicBlock *BB : Blocks) - Insts.push_back(BB->getTerminator()->getPrevNode()); + Insts.push_back(BB->getTerminator()->getPrevNonDebugInstruction()); Instruction *I0 = Insts.front(); SmallVector NewOperands; diff --git a/llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll b/llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll new file mode 100644 index 000000000000..f51cadc1bb85 --- /dev/null +++ b/llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll @@ -0,0 +1,86 @@ +; RUN: opt < %s -passes=gvn-sink -S | FileCheck %s + +; Function Attrs: noinline nounwind uwtable +define dso_local i32 @fun(i32 noundef %a, i32 noundef %b) #0 !dbg !10 { +entry: + tail call void @llvm.dbg.value(metadata i32 %a, metadata !15, metadata !DIExpression()), !dbg !16 + tail call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression()), !dbg !16 + %cmp = icmp sgt i32 %b, 10, !dbg !18 + br i1 %cmp, label %if.then, label %if.else, !dbg !20 + +if.then: ; preds = %entry + %add = add nsw i32 %a, 1, !dbg !21 + tail call void @llvm.dbg.value(metadata i32 %add, metadata !23, metadata !DIExpression()), !dbg !24 + %xor = xor i32 %add, 1, !dbg !25 + tail call void @llvm.dbg.value(metadata i32 %xor, metadata !26, metadata !DIExpression()), !dbg !24 + tail call void @llvm.dbg.value(metadata i32 %xor, metadata !27, metadata !DIExpression()), !dbg !16 + br label %if.end, !dbg !28 + +if.else: ; preds = %entry + %add1 = add nsw i32 %b, 1, !dbg !29 + tail call void @llvm.dbg.value(metadata i32 %add1, metadata !31, metadata !DIExpression()), !dbg !32 + %xor2 = xor i32 %add1, 1, !dbg !33 + tail call void @llvm.dbg.value(metadata i32 %xor2, metadata !34, metadata !DIExpression()), !dbg !32 + tail call void @llvm.dbg.value(metadata i32 %xor2, metadata !27, metadata !DIExpression()), !dbg !16 + br label %if.end + +; CHECK-LABEL: if.end: +; CHECK: %a.sink = phi i32 [ %a, %if.then ], [ %b, %if.else ] +; CHECK: %add = add nsw i32 %a.sink, 1 +; CHECK: %xor = xor i32 %add, 1 +if.end: ; preds = %if.else, %if.then + %ret.0 = phi i32 [ %xor, %if.then ], [ %xor2, %if.else ], !dbg !35 + tail call void @llvm.dbg.value(metadata i32 %ret.0, metadata !27, metadata !DIExpression()), !dbg !16 + ret i32 %ret.0, !dbg !36 +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { noinline nounwind uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 18.0.0git (https://github.com/llvm/llvm-project.git 5dfcb3e5d1d16bb4f8fce52b3c089119ed977e7f)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "main.c", directory: "/home/hs/llvm-test", checksumkind: CSK_MD5, checksum: "68c28c3d0877bed08ff43db70c573802") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{!"clang version 18.0.0git (https://github.com/llvm/llvm-project.git 5dfcb3e5d1d16bb4f8fce52b3c089119ed977e7f)"} +!10 = distinct !DISubprogram(name: "fun", scope: !1, file: !1, line: 1, type: !11, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) +!11 = !DISubroutineType(types: !12) +!12 = !{!13, !13, !13} +!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!14 = !{} +!15 = !DILocalVariable(name: "a", arg: 1, scope: !10, file: !1, line: 1, type: !13) +!16 = !DILocation(line: 0, scope: !10) +!17 = !DILocalVariable(name: "b", arg: 2, scope: !10, file: !1, line: 1, type: !13) +!18 = !DILocation(line: 3, column: 11, scope: !19) +!19 = distinct !DILexicalBlock(scope: !10, file: !1, line: 3, column: 9) +!20 = !DILocation(line: 3, column: 9, scope: !10) +!21 = !DILocation(line: 4, column: 20, scope: !22) +!22 = distinct !DILexicalBlock(scope: !19, file: !1, line: 3, column: 17) +!23 = !DILocalVariable(name: "a1", scope: !22, file: !1, line: 4, type: !13) +!24 = !DILocation(line: 0, scope: !22) +!25 = !DILocation(line: 5, column: 21, scope: !22) +!26 = !DILocalVariable(name: "a2", scope: !22, file: !1, line: 5, type: !13) +!27 = !DILocalVariable(name: "ret", scope: !10, file: !1, line: 2, type: !13) +!28 = !DILocation(line: 7, column: 5, scope: !22) +!29 = !DILocation(line: 8, column: 20, scope: !30) +!30 = distinct !DILexicalBlock(scope: !19, file: !1, line: 7, column: 12) +!31 = !DILocalVariable(name: "b1", scope: !30, file: !1, line: 8, type: !13) +!32 = !DILocation(line: 0, scope: !30) +!33 = !DILocation(line: 9, column: 21, scope: !30) +!34 = !DILocalVariable(name: "b2", scope: !30, file: !1, line: 9, type: !13) +!35 = !DILocation(line: 0, scope: !19) +!36 = !DILocation(line: 12, column: 5, scope: !10) \ No newline at end of file -- GitLab From 9160f49e08af4267efdc870a1c9a434bfd155ae3 Mon Sep 17 00:00:00 2001 From: Romaric Jodin <89833130+rjodinchr@users.noreply.github.com> Date: Tue, 9 Jan 2024 17:47:53 +0100 Subject: [PATCH 221/652] libclc: generic: add half implementation for erf/erfc (#66901) libclc does not have a half implementation for erf/erfc Add one based on the float implementation by extending the input and truncating the output. --- libclc/generic/lib/math/erf.cl | 12 ++++++++++++ libclc/generic/lib/math/erfc.cl | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/libclc/generic/lib/math/erf.cl b/libclc/generic/lib/math/erf.cl index 3dc82d926e86..2c395ce1a752 100644 --- a/libclc/generic/lib/math/erf.cl +++ b/libclc/generic/lib/math/erf.cl @@ -399,4 +399,16 @@ _CLC_OVERLOAD _CLC_DEF double erf(double y) { _CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, erf, double); +#ifdef cl_khr_fp16 + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half erf(half h) { + return (half)erf((float)h); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, erf, half); + +#endif + #endif diff --git a/libclc/generic/lib/math/erfc.cl b/libclc/generic/lib/math/erfc.cl index c322f8691b38..cd35ea8def7b 100644 --- a/libclc/generic/lib/math/erfc.cl +++ b/libclc/generic/lib/math/erfc.cl @@ -410,4 +410,16 @@ _CLC_OVERLOAD _CLC_DEF double erfc(double x) { _CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, erfc, double); +#ifdef cl_khr_fp16 + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half erfc(half h) { + return (half)erfc((float)h); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, erfc, half); + +#endif + #endif -- GitLab From c19995e9654f3ad01defea06f2cfe25cf57475c5 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Tue, 9 Jan 2024 17:53:25 +0100 Subject: [PATCH 222/652] [bazel] Fix compiler-rt build after 07c9189fcc063bdf6219d2733843c89cde3991e1 --- utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel | 1 + 1 file changed, 1 insertion(+) diff --git a/utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel b/utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel index 573549781ab7..bba18bfd387a 100644 --- a/utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel @@ -39,6 +39,7 @@ cc_library( "//conditions:default": [] }), hdrs = glob([ + "include/profile/*.h", "include/profile/*.inc", ]), includes = [ -- GitLab From affd9e8e00fc94ccfe87cc41b337852fb681adde Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 9 Jan 2024 23:56:46 +0700 Subject: [PATCH 223/652] AMDGPU: Break vop3p handling out of vop3 base patterns (#77472) Add the vop3p op_sel fields in getInsVOP3P instead of getInsVOP3Base. Also start using defvar for some of the intermediate fields. let overrides of all the visible fields are really difficult to follow. --- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 33 +++++++++++++--------- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 2 +- 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index f07b8fa0ea4c..04c92155f5aa 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1773,28 +1773,27 @@ class getIns64 { + Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOpSel> { // getInst64 handles clamp and omod. implicit mutex between vop3p and omod dag base = getIns64 .ret; dag opsel = (ins op_sel0:$op_sel); - dag vop3pOpsel = (ins op_sel_hi0:$op_sel_hi); - dag vop3pFields = !con(!if(HasOpSel, vop3pOpsel, (ins)), (ins neg_lo0:$neg_lo, neg_hi0:$neg_hi)); - - dag ret = !con(base, - !if(HasOpSel, opsel,(ins)), - !if(IsVOP3P, vop3pFields,(ins))); + dag ret = !con(base, !if(HasOpSel, opsel, (ins))); } class getInsVOP3P { - dag ret = getInsVOP3Base.ret; + 0/*HasOMod*/, Src0Mod, Src1Mod, Src2Mod, HasOpSel>.ret; + + dag vop3pOpsel = (ins op_sel_hi0:$op_sel_hi); + dag vop3p_neg = (ins neg_lo0:$neg_lo, neg_hi0:$neg_hi); + + dag vop3pFields = !con(!if(HasOpSel, vop3pOpsel, (ins)), vop3p_neg); + dag ret = !con(base, vop3pFields); } class getInsVOP3OpSel .ret; + Src0Mod, Src1Mod, Src2Mod, /*HasOpSel=*/1>.ret; } class getInsDPPBase _ArgVT, bit _EnableClamp = 0> { field dag InsDPP8 = getInsDPP8.ret; - field dag InsVOP3Base = getInsVOP3Base.ret; + Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP, HasOpSel>.ret; + defvar InsVOP3PDPPBase = getInsVOP3P.ret; + + field dag InsVOP3Base = !if(IsVOP3P, InsVOP3PDPPBase, InsVOP3DPPBase); + field dag InsVOP3DPP = getInsVOP3DPP.ret; field dag InsVOP3DPP16 = getInsVOP3DPP16.ret; field dag InsVOP3DPP8 = getInsVOP3DPP8.ret; diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index ecee61daa1c8..3e66b5550cce 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -437,7 +437,7 @@ class VOP_MAC : VOPProfile <[vt0, vt1, vt1, v let InsDPP16 = !con(InsDPP, (ins FI:$fi)); let InsVOP3Base = getInsVOP3Base, 3, 0, HasModifiers, HasModifiers, HasOMod, - Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel, 0/*IsVOP3P*/>.ret; + Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel>.ret; // We need a dummy src2 tied to dst to track the use of that register for s_delay_alu let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPRSrc_32:$src2X); let InsVOPDXDeferred = -- GitLab From dc03382d3e38c8028926b2b66eebf3ca98efc7d3 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Tue, 9 Jan 2024 12:02:40 -0500 Subject: [PATCH 224/652] [openmp][AIX] Add AIX to __kmp_set_stack_info() (#77421) --- openmp/runtime/src/z_Linux_util.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openmp/runtime/src/z_Linux_util.cpp b/openmp/runtime/src/z_Linux_util.cpp index f01fa647c4d4..513ec6517d00 100644 --- a/openmp/runtime/src/z_Linux_util.cpp +++ b/openmp/runtime/src/z_Linux_util.cpp @@ -422,7 +422,7 @@ void __kmp_terminate_thread(int gtid) { static kmp_int32 __kmp_set_stack_info(int gtid, kmp_info_t *th) { int stack_data; #if KMP_OS_LINUX || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || \ - KMP_OS_HURD || KMP_OS_SOLARIS + KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_AIX pthread_attr_t attr; int status; size_t size = 0; -- GitLab From 5cfe24eee49dfb9f6f72e73142e075dbbadd3089 Mon Sep 17 00:00:00 2001 From: Krzysztof Drewniak Date: Tue, 9 Jan 2024 11:05:20 -0600 Subject: [PATCH 225/652] [mlir][Vector] Add nontemporal attribute, mirroring memref (#76752) Since vector loads and stores from scalar memrefs translate to llvm.load/store, add the ability to tag said loads and stores as nontemporal. This mirrors functionality available in memref.load/store. --- .../mlir/Dialect/Vector/IR/VectorOps.td | 6 ++-- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 7 +++-- .../VectorToLLVM/vector-to-llvm.mlir | 29 +++++++++++++++++++ 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td index 40d874dc99dd..8e333def3386 100644 --- a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td +++ b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td @@ -1626,7 +1626,8 @@ def Vector_LoadOp : Vector_Op<"load"> { let arguments = (ins Arg:$base, - Variadic:$indices); + Variadic:$indices, + DefaultValuedOptionalAttr:$nontemporal); let results = (outs AnyVectorOfAnyRank:$result); let extraClassDeclaration = [{ @@ -1710,7 +1711,8 @@ def Vector_StoreOp : Vector_Op<"store"> { AnyVectorOfAnyRank:$valueToStore, Arg:$base, - Variadic:$indices + Variadic:$indices, + DefaultValuedOptionalAttr:$nontemporal ); let extraClassDeclaration = [{ diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index a24fb6f83915..b66b55ae8d57 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -192,7 +192,9 @@ static void replaceLoadOrStoreOp(vector::LoadOp loadOp, vector::LoadOpAdaptor adaptor, VectorType vectorTy, Value ptr, unsigned align, ConversionPatternRewriter &rewriter) { - rewriter.replaceOpWithNewOp(loadOp, vectorTy, ptr, align); + rewriter.replaceOpWithNewOp(loadOp, vectorTy, ptr, align, + /*volatile_=*/false, + loadOp.getNontemporal()); } static void replaceLoadOrStoreOp(vector::MaskedLoadOp loadOp, @@ -208,7 +210,8 @@ static void replaceLoadOrStoreOp(vector::StoreOp storeOp, VectorType vectorTy, Value ptr, unsigned align, ConversionPatternRewriter &rewriter) { rewriter.replaceOpWithNewOp(storeOp, adaptor.getValueToStore(), - ptr, align); + ptr, align, /*volatile_=*/false, + storeOp.getNontemporal()); } static void replaceLoadOrStoreOp(vector::MaskedStoreOp storeOp, diff --git a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir index b13c266609ae..09108ab31799 100644 --- a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir +++ b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir @@ -2023,6 +2023,20 @@ func.func @vector_load_op(%memref : memref<200x100xf32>, %i : index, %j : index) // ----- +func.func @vector_load_op_nontemporal(%memref : memref<200x100xf32>, %i : index, %j : index) -> vector<8xf32> { + %0 = vector.load %memref[%i, %j] {nontemporal = true} : memref<200x100xf32>, vector<8xf32> + return %0 : vector<8xf32> +} + +// CHECK-LABEL: func @vector_load_op_nontemporal +// CHECK: %[[c100:.*]] = llvm.mlir.constant(100 : index) : i64 +// CHECK: %[[mul:.*]] = llvm.mul %{{.*}}, %[[c100]] : i64 +// CHECK: %[[add:.*]] = llvm.add %[[mul]], %{{.*}} : i64 +// CHECK: %[[gep:.*]] = llvm.getelementptr %{{.*}}[%[[add]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 +// CHECK: llvm.load %[[gep]] {alignment = 4 : i64, nontemporal} : !llvm.ptr -> vector<8xf32> + +// ----- + func.func @vector_load_op_index(%memref : memref<200x100xindex>, %i : index, %j : index) -> vector<8xindex> { %0 = vector.load %memref[%i, %j] : memref<200x100xindex>, vector<8xindex> return %0 : vector<8xindex> @@ -2049,6 +2063,21 @@ func.func @vector_store_op(%memref : memref<200x100xf32>, %i : index, %j : index // ----- +func.func @vector_store_op_nontemporal(%memref : memref<200x100xf32>, %i : index, %j : index) { + %val = arith.constant dense<11.0> : vector<4xf32> + vector.store %val, %memref[%i, %j] {nontemporal = true} : memref<200x100xf32>, vector<4xf32> + return +} + +// CHECK-LABEL: func @vector_store_op_nontemporal +// CHECK: %[[c100:.*]] = llvm.mlir.constant(100 : index) : i64 +// CHECK: %[[mul:.*]] = llvm.mul %{{.*}}, %[[c100]] : i64 +// CHECK: %[[add:.*]] = llvm.add %[[mul]], %{{.*}} : i64 +// CHECK: %[[gep:.*]] = llvm.getelementptr %{{.*}}[%[[add]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 +// CHECK: llvm.store %{{.*}}, %[[gep]] {alignment = 4 : i64, nontemporal} : vector<4xf32>, !llvm.ptr + +// ----- + func.func @vector_store_op_index(%memref : memref<200x100xindex>, %i : index, %j : index) { %val = arith.constant dense<11> : vector<4xindex> vector.store %val, %memref[%i, %j] : memref<200x100xindex>, vector<4xindex> -- GitLab From 888a20c466e1a7b0da4bd662da8668f13a14e75f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 10 Jan 2024 00:12:40 +0700 Subject: [PATCH 226/652] AMDGPU: Drop amdgpu-no-lds-kernel-id attribute in LDS lowering (#71481) This is in preparation for moving the run of AMDGPUAttributor earlier. Currently it infers the lack of the corresponding intrinsic calls, so if we introduce new ones we need to remove the attribute from any possible transitive callers. This is more conservative than necessary, we could try to identify specific subgraphs where LDS globals are not used. Other options include teaching the attributor to avoid adding it in cases where the lowering may choose the table, but this seems more complex. Alternatively could add a second run which doesn't seem worth it. Depends #71349 --- .../AMDGPU/AMDGPULowerModuleLDSPass.cpp | 52 +++++ .../AMDGPU/remove-no-kernel-id-attribute.ll | 210 ++++++++++++++++++ 2 files changed, 262 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp index d2a02143e4e7..5762f1906a16 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp @@ -1026,6 +1026,51 @@ public: return N; } + /// Strip "amdgpu-no-lds-kernel-id" from any functions where we may have + /// introduced its use. If AMDGPUAttributor ran prior to the pass, we inferred + /// the lack of llvm.amdgcn.lds.kernel.id calls. + void removeNoLdsKernelIdFromReachable(CallGraph &CG, Function *KernelRoot) { + KernelRoot->removeFnAttr("amdgpu-no-lds-kernel-id"); + + SmallVector Tmp({CG[KernelRoot]->getFunction()}); + if (!Tmp.back()) + return; + + SmallPtrSet Visited; + bool SeenUnknownCall = false; + + do { + Function *F = Tmp.pop_back_val(); + + for (auto &N : *CG[F]) { + if (!N.second) + continue; + + Function *Callee = N.second->getFunction(); + if (!Callee) { + if (!SeenUnknownCall) { + SeenUnknownCall = true; + + // If we see any indirect calls, assume nothing about potential + // targets. + // TODO: This could be refined to possible LDS global users. + for (auto &N : *CG.getExternalCallingNode()) { + Function *PotentialCallee = N.second->getFunction(); + if (!isKernelLDS(PotentialCallee)) + PotentialCallee->removeFnAttr("amdgpu-no-lds-kernel-id"); + } + + continue; + } + } + + Callee->removeFnAttr("amdgpu-no-lds-kernel-id"); + if (Visited.insert(Callee).second) + Tmp.push_back(Callee); + } + } while (!Tmp.empty()); + } + DenseMap lowerDynamicLDSVariables( Module &M, LDSUsesInfoTy &LDSUsesInfo, DenseSet const &KernelsThatIndirectlyAllocateDynamicLDS, @@ -1175,6 +1220,13 @@ public: M, TableLookupVariablesOrdered, OrderedKernels, KernelToReplacement); replaceUsesInInstructionsWithTableLookup(M, TableLookupVariablesOrdered, LookupTable); + + // Strip amdgpu-no-lds-kernel-id from all functions reachable from the + // kernel. We may have inferred this wasn't used prior to the pass. + // + // TODO: We could filter out subgraphs that do not access LDS globals. + for (Function *F : KernelsThatAllocateTableLDS) + removeNoLdsKernelIdFromReachable(CG, F); } DenseMap KernelToCreatedDynamicLDS = diff --git a/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll b/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll new file mode 100644 index 000000000000..80eb52726826 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll @@ -0,0 +1,210 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 3 +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-attributor,amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefixes=CHECK,TABLE %s + +; FIXME: Work around update_test_checks bug in constant expression handling by manually deleting part of the last global pattern + +@function.lds = addrspace(3) global i16 poison +@other.kernel.lds = addrspace(3) global i16 poison +@recursive.kernel.lds = addrspace(3) global i16 poison + +;. +; CHECK: @[[LLVM_AMDGCN_KERNEL_K0_F0_LDS:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global [[LLVM_AMDGCN_KERNEL_K0_F0_LDS_T:%.*]] poison, align 2, !absolute_symbol !0 +; CHECK: @[[LLVM_AMDGCN_KERNEL_K1_F0_LDS:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global [[LLVM_AMDGCN_KERNEL_K1_F0_LDS_T:%.*]] poison, align 2, !absolute_symbol !0 +; CHECK: @[[LLVM_AMDGCN_KERNEL_KERNEL_LDS_LDS:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global [[LLVM_AMDGCN_KERNEL_KERNEL_LDS_LDS_T:%.*]] poison, align 2, !absolute_symbol !0 +; CHECK: @[[LLVM_AMDGCN_KERNEL_KERNEL_LDS_RECURSION_LDS:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global [[LLVM_AMDGCN_KERNEL_KERNEL_LDS_RECURSION_LDS_T:%.*]] poison, align 2, !absolute_symbol !0 +; CHECK: @[[LLVM_AMDGCN_LDS_OFFSET_TABLE:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(4) constant [3 x [2 x i32]] +;. +define internal void @lds_use_through_indirect() { +; CHECK-LABEL: define internal void @lds_use_through_indirect( +; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; CHECK-NEXT: [[FUNCTION_LDS2:%.*]] = getelementptr inbounds [3 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[FUNCTION_LDS2]], align 4 +; CHECK-NEXT: [[FUNCTION_LDS3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(3) +; CHECK-NEXT: [[LD:%.*]] = load i16, ptr addrspace(3) [[FUNCTION_LDS3]], align 2 +; CHECK-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 7 +; CHECK-NEXT: [[FUNCTION_LDS:%.*]] = getelementptr inbounds [3 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[FUNCTION_LDS]], align 4 +; CHECK-NEXT: [[FUNCTION_LDS1:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(3) +; CHECK-NEXT: store i16 [[MUL]], ptr addrspace(3) [[FUNCTION_LDS1]], align 2 +; CHECK-NEXT: ret void +; + %ld = load i16, ptr addrspace(3) @function.lds + %mul = mul i16 %ld, 7 + store i16 %mul, ptr addrspace(3) @function.lds + ret void +} + +define internal void @indirectly_called() { +; CHECK-LABEL: define internal void @indirectly_called( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: store volatile ptr @indirectly_called, ptr addrspace(1) null, align 8 +; CHECK-NEXT: call void @lds_use_through_indirect() +; CHECK-NEXT: ret void +; + store volatile ptr @indirectly_called, ptr addrspace(1) null + call void @lds_use_through_indirect() + ret void +} + +define internal void @calls_indirectly_called() { +; CHECK-LABEL: define internal void @calls_indirectly_called( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: call void @indirectly_called() +; CHECK-NEXT: ret void +; + call void @indirectly_called() + ret void +} + +; TODO: Should still have "amdgpu-no-lds-kernel-id" attached +define internal void @no_lds_global_use_leaf() { +; CHECK-LABEL: define internal void @no_lds_global_use_leaf( +; CHECK-SAME: ) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +; Should have "amdgpu-no-lds-kernel-id" stripped +define internal void @f0() { +; CHECK-LABEL: define internal void @f0( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; CHECK-NEXT: [[FUNCTION_LDS2:%.*]] = getelementptr inbounds [3 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[FUNCTION_LDS2]], align 4 +; CHECK-NEXT: [[FUNCTION_LDS3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(3) +; CHECK-NEXT: [[LD:%.*]] = load i16, ptr addrspace(3) [[FUNCTION_LDS3]], align 2 +; CHECK-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 4 +; CHECK-NEXT: [[FUNCTION_LDS:%.*]] = getelementptr inbounds [3 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[FUNCTION_LDS]], align 4 +; CHECK-NEXT: [[FUNCTION_LDS1:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(3) +; CHECK-NEXT: store i16 [[MUL]], ptr addrspace(3) [[FUNCTION_LDS1]], align 2 +; CHECK-NEXT: call void @no_lds_global_use_leaf() +; CHECK-NEXT: ret void +; + %ld = load i16, ptr addrspace(3) @function.lds + %mul = mul i16 %ld, 4 + store i16 %mul, ptr addrspace(3) @function.lds + call void @no_lds_global_use_leaf() + ret void +} + +; Should have "amdgpu-no-lds-kernel-id" stripped +define internal void @f0_transitive() { +; CHECK-LABEL: define internal void @f0_transitive( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: call void @f0() +; CHECK-NEXT: call void @no_lds_global_use_leaf() +; CHECK-NEXT: ret void +; + call void @f0() + call void @no_lds_global_use_leaf() + ret void +} + +define amdgpu_kernel void @k0_f0() { +; CHECK-LABEL: define amdgpu_kernel void @k0_f0( +; CHECK-SAME: ) #[[ATTR2:[0-9]+]] !llvm.amdgcn.lds.kernel.id !1 { +; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.kernel.k0_f0.lds) ] +; CHECK-NEXT: call void @f0_transitive() +; CHECK-NEXT: ret void +; + call void @f0_transitive() + ret void +} + +define amdgpu_kernel void @k1_f0() { +; CHECK-LABEL: define amdgpu_kernel void @k1_f0( +; CHECK-SAME: ) #[[ATTR3:[0-9]+]] !llvm.amdgcn.lds.kernel.id !2 { +; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.kernel.k1_f0.lds) ], !alias.scope !3, !noalias !6 +; CHECK-NEXT: call void @f0_transitive() +; CHECK-NEXT: [[FPTR:%.*]] = load volatile ptr, ptr addrspace(1) null, align 8 +; CHECK-NEXT: call void [[FPTR]]() +; CHECK-NEXT: call void @calls_indirectly_called() +; CHECK-NEXT: ret void +; + call void @f0_transitive() + %fptr = load volatile ptr, ptr addrspace(1) null + call void %fptr() + call void @calls_indirectly_called() + ret void +} + +; Should still have "amdgpu-no-lds-kernel-id" attached +define amdgpu_kernel void @kernel_lds() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_lds( +; CHECK-SAME: ) #[[ATTR4:[0-9]+]] { +; CHECK-NEXT: [[LD:%.*]] = load i16, ptr addrspace(3) @llvm.amdgcn.kernel.kernel_lds.lds, align 2 +; CHECK-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 42 +; CHECK-NEXT: store i16 [[MUL]], ptr addrspace(3) @llvm.amdgcn.kernel.kernel_lds.lds, align 2 +; CHECK-NEXT: ret void +; + %ld = load i16, ptr addrspace(3) @other.kernel.lds + %mul = mul i16 %ld, 42 + store i16 %mul, ptr addrspace(3) @other.kernel.lds + ret void +} + +define internal i16 @mutual_recursion_0(i16 %arg) { +; CHECK-LABEL: define internal i16 @mutual_recursion_0( +; CHECK-SAME: i16 [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; CHECK-NEXT: [[RECURSIVE_KERNEL_LDS:%.*]] = getelementptr inbounds [3 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 1 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[RECURSIVE_KERNEL_LDS]], align 4 +; CHECK-NEXT: [[RECURSIVE_KERNEL_LDS1:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(3) +; CHECK-NEXT: [[LD:%.*]] = load i16, ptr addrspace(3) [[RECURSIVE_KERNEL_LDS1]], align 2 +; CHECK-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 7 +; CHECK-NEXT: [[RET:%.*]] = call i16 @mutual_recursion_1(i16 [[LD]]) +; CHECK-NEXT: [[ADD:%.*]] = add i16 [[RET]], 1 +; CHECK-NEXT: ret i16 [[ADD]] +; + %ld = load i16, ptr addrspace(3) @recursive.kernel.lds + %mul = mul i16 %ld, 7 + %ret = call i16 @mutual_recursion_1(i16 %ld) + %add = add i16 %ret, 1 + ret i16 %add +} + +define internal void @mutual_recursion_1(i16 %arg) { +; CHECK-LABEL: define internal void @mutual_recursion_1( +; CHECK-SAME: i16 [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: call void @mutual_recursion_0(i16 [[ARG]]) +; CHECK-NEXT: ret void +; + call void @mutual_recursion_0(i16 %arg) + ret void +} + +define amdgpu_kernel void @kernel_lds_recursion() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_lds_recursion( +; CHECK-SAME: ) #[[ATTR2]] !llvm.amdgcn.lds.kernel.id !8 { +; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.kernel.kernel_lds_recursion.lds) ] +; CHECK-NEXT: call void @mutual_recursion_0(i16 0) +; CHECK-NEXT: ret void +; + call void @mutual_recursion_0(i16 0) + ret void +} + +;. +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR2]] = { "amdgpu-lds-size"="2" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR3]] = { "amdgpu-lds-size"="4" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR4]] = { "amdgpu-lds-size"="2" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) } +; CHECK: attributes #[[ATTR6:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +;. +; CHECK: [[META0:![0-9]+]] = !{i32 0, i32 1} +; CHECK: [[META1:![0-9]+]] = !{i32 0} +; CHECK: [[META2:![0-9]+]] = !{i32 1} +; CHECK: [[META3:![0-9]+]] = !{!4} +; CHECK: [[META4:![0-9]+]] = distinct !{!4, !5} +; CHECK: [[META5:![0-9]+]] = distinct !{!5} +; CHECK: [[META6:![0-9]+]] = !{!7} +; CHECK: [[META7:![0-9]+]] = distinct !{!7, !5} +; CHECK: [[META8:![0-9]+]] = !{i32 2} +;. +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; TABLE: {{.*}} -- GitLab From 79e17cd01491c0fde241097ad4c5c24afbb1883e Mon Sep 17 00:00:00 2001 From: Andrey Ali Khan Bolshakov <32954549+bolshakov-a@users.noreply.github.com> Date: Tue, 9 Jan 2024 20:14:17 +0300 Subject: [PATCH 227/652] [clang] Improve bit-field in ref NTTP diagnostic (#71077) Prior to this, attempts to bind a bit-field to an NTTP of reference type produced an error because references to subobjects in NTTPs are disallowed. But C++20 allows references to subobjects in NTTPs generally (see [P1907R1](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2019/p1907r1.html)). Without this change, implementing P1907R1 would cause a bug allowing bit-fields to be bound to reference template arguments. Extracted from https://reviews.llvm.org/D140996 --- clang/docs/ReleaseNotes.rst | 2 ++ clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 ++ clang/lib/Sema/SemaOverload.cpp | 10 ++++++++++ clang/test/CXX/drs/dr12xx.cpp | 2 +- clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp | 6 ++++++ 5 files changed, 21 insertions(+), 1 deletion(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index c89488e54ef4..ddeb1186d65a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -520,6 +520,8 @@ Improvements to Clang's diagnostics - Clang now diagnoses narrowing conversions involving const references. (`#63151: `_). - Clang now diagnoses unexpanded packs within the template argument lists of function template specializations. +- Clang now diagnoses attempts to bind a bitfield to an NTTP of a reference type as erroneous + converted constant expression and not as a reference to subobject. Improvements to Clang's time-trace diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index a97182cad5d5..3884dca59e2f 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -2253,6 +2253,8 @@ def warn_cxx17_compat_aggregate_init_paren_list : Warning< def err_reference_bind_to_bitfield : Error< "%select{non-const|volatile}0 reference cannot bind to " "bit-field%select{| %1}2">; +def err_reference_bind_to_bitfield_in_cce : Error< + "reference cannot bind to bit-field in converted constant expression">; def err_reference_bind_to_vector_element : Error< "%select{non-const|volatile}0 reference cannot bind to vector element">; def err_reference_bind_to_matrix_element : Error< diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index e6c267bb79e6..64bc38519802 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -6056,6 +6056,16 @@ static ExprResult BuildConvertedConstantExpression(Sema &S, Expr *From, diag::err_typecheck_converted_constant_expression_indirect) << From->getType() << From->getSourceRange() << T; } + // 'TryCopyInitialization' returns incorrect info for attempts to bind + // a reference to a bit-field due to C++ [over.ics.ref]p4. Namely, + // 'SCS->DirectBinding' occurs to be set to 'true' despite it is not + // the direct binding according to C++ [dcl.init.ref]p5. Hence, check this + // case explicitly. + if (From->refersToBitField() && T.getTypePtr()->isReferenceType()) { + return S.Diag(From->getBeginLoc(), + diag::err_reference_bind_to_bitfield_in_cce) + << From->getSourceRange(); + } // Usually we can simply apply the ImplicitConversionSequence we formed // earlier, but that's not guaranteed to work when initializing an object of diff --git a/clang/test/CXX/drs/dr12xx.cpp b/clang/test/CXX/drs/dr12xx.cpp index adf7f56711c4..cb4cc5aef173 100644 --- a/clang/test/CXX/drs/dr12xx.cpp +++ b/clang/test/CXX/drs/dr12xx.cpp @@ -154,7 +154,7 @@ namespace dr1295 { // dr1295: 4 Y y; // #dr1295-y // cxx98-14-error@-1 {{non-type template argument does not refer to any declaration}} // cxx98-14-note@#dr1295-Y {{template parameter is declared here}} - // since-cxx17-error@#dr1295-y {{non-type template argument refers to subobject 'x.bitfield'}} + // since-cxx17-error@#dr1295-y {{reference cannot bind to bit-field in converted constant expression}} #if __cplusplus >= 201103L const unsigned other = 0; diff --git a/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp b/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp index 792dc78464b2..982f6ec22157 100644 --- a/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp +++ b/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp @@ -93,6 +93,12 @@ namespace ConvertedConstant { template struct X {}; void f(X<1.0f>) {} void g(X<2>) {} + + struct { + int i : 2; + } b; + template struct Y {}; + void f(Y) {} // expected-error {{reference cannot bind to bit-field in converted constant expression}} } namespace CopyCounting { -- GitLab From c9da4dc77f780df003718bc0d36c0c9e371bfb9c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 9 Jan 2024 09:21:27 -0800 Subject: [PATCH 228/652] [RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408) -Rename to GPRPair. -Rename registers to be named like X10_X11 instead of X10_PD. Except X0 which is now X0_Pair since it is not paired with X1. -Use unknown size and offset for the subreg indices. This might be a functional change, but does not affect any lit tests. --- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +- .../RISCV/Disassembler/RISCVDisassembler.cpp | 2 +- .../Target/RISCV/RISCVExpandPseudoInsts.cpp | 12 +++-- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 ++--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 17 +++---- llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 16 +++---- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 45 +++++++++++-------- 7 files changed, 59 insertions(+), 45 deletions(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index d616aaeddf41..4250950a9172 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1295,7 +1295,7 @@ unsigned RISCVAsmParser::checkTargetMatchPredicate(MCInst &Inst) { const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); for (unsigned I = 0; I < MCID.NumOperands; ++I) { - if (MCID.operands()[I].RegClass == RISCV::GPRPF64RegClassID) { + if (MCID.operands()[I].RegClass == RISCV::GPRPairRegClassID) { const auto &Op = Inst.getOperand(I); assert(Op.isReg()); diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index ed80da14c795..bc65cf2403b2 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -171,7 +171,7 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } -static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo, +static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { if (RegNo >= 32 || RegNo & 1) diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp index 103a2e2da7b9..ed2b1ceb7d6f 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -308,8 +308,10 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) { DebugLoc DL = MBBI->getDebugLoc(); const TargetRegisterInfo *TRI = STI->getRegisterInfo(); - Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32); - Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi); + Register Lo = + TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even); + Register Hi = + TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd); BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW)) .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill())) .addReg(MBBI->getOperand(1).getReg()) @@ -342,8 +344,10 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) { DebugLoc DL = MBBI->getDebugLoc(); const TargetRegisterInfo *TRI = STI->getRegisterInfo(); - Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32); - Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi); + Register Lo = + TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even); + Register Hi = + TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd); // If the register of operand 1 is equal to the Lo register, then swap the // order of loading the Lo and Hi statements. diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index b4abebc27eed..04ec73c4f9ed 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -138,7 +138,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, if (Subtarget.is64Bit()) addRegisterClass(MVT::f64, &RISCV::GPRRegClass); else - addRegisterClass(MVT::f64, &RISCV::GPRPF64RegClass); + addRegisterClass(MVT::f64, &RISCV::GPRPairRegClass); } static const MVT::SimpleValueType BoolVecVTs[] = { @@ -16344,7 +16344,7 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI, Register SrcReg = MI.getOperand(2).getReg(); const TargetRegisterClass *SrcRC = MI.getOpcode() == RISCV::SplitF64Pseudo_INX - ? &RISCV::GPRPF64RegClass + ? &RISCV::GPRPairRegClass : &RISCV::FPR64RegClass; int FI = MF.getInfo()->getMoveF64FrameIndex(MF); @@ -16383,7 +16383,7 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI, Register HiReg = MI.getOperand(2).getReg(); const TargetRegisterClass *DstRC = - MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX ? &RISCV::GPRPF64RegClass + MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX ? &RISCV::GPRPairRegClass : &RISCV::FPR64RegClass; int FI = MF.getInfo()->getMoveF64FrameIndex(MF); @@ -18751,7 +18751,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, if (VT == MVT::f32 && Subtarget.hasStdExtZfinx()) return std::make_pair(0U, &RISCV::GPRF32RegClass); if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit()) - return std::make_pair(0U, &RISCV::GPRPF64RegClass); + return std::make_pair(0U, &RISCV::GPRPairRegClass); return std::make_pair(0U, &RISCV::GPRNoX0RegClass); case 'f': if (Subtarget.hasStdExtZfhmin() && VT == MVT::f16) @@ -18933,7 +18933,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // Subtarget into account. if (Res.second == &RISCV::GPRF16RegClass || Res.second == &RISCV::GPRF32RegClass || - Res.second == &RISCV::GPRPF64RegClass) + Res.second == &RISCV::GPRPairRegClass) return std::make_pair(Res.first, &RISCV::GPRRegClass); return Res; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 351f48c1708e..9813c7a70dfc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -414,15 +414,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } - if (RISCV::GPRPF64RegClass.contains(DstReg, SrcReg)) { - // Emit an ADDI for both parts of GPRPF64. + if (RISCV::GPRPairRegClass.contains(DstReg, SrcReg)) { + // Emit an ADDI for both parts of GPRPair. BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), - TRI->getSubReg(DstReg, RISCV::sub_32)) - .addReg(TRI->getSubReg(SrcReg, RISCV::sub_32), getKillRegState(KillSrc)) + TRI->getSubReg(DstReg, RISCV::sub_gpr_even)) + .addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_even), + getKillRegState(KillSrc)) .addImm(0); BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), - TRI->getSubReg(DstReg, RISCV::sub_32_hi)) - .addReg(TRI->getSubReg(SrcReg, RISCV::sub_32_hi), + TRI->getSubReg(DstReg, RISCV::sub_gpr_odd)) + .addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_odd), getKillRegState(KillSrc)) .addImm(0); return; @@ -607,7 +608,7 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::SW : RISCV::SD; IsScalableVector = false; - } else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) { + } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) { Opcode = RISCV::PseudoRV32ZdinxSD; IsScalableVector = false; } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { @@ -690,7 +691,7 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::LW : RISCV::LD; IsScalableVector = false; - } else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) { + } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) { Opcode = RISCV::PseudoRV32ZdinxLD; IsScalableVector = false; } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index 418421b2a556..fec43d814098 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -33,8 +33,8 @@ def AddrRegImmINX : ComplexPattern; // Zdinx -def GPRPF64AsFPR : AsmOperandClass { - let Name = "GPRPF64AsFPR"; +def GPRPairAsFPR : AsmOperandClass { + let Name = "GPRPairAsFPR"; let ParserMethod = "parseGPRAsFPR"; let PredicateMethod = "isGPRAsFPR"; let RenderMethod = "addRegOperands"; @@ -52,8 +52,8 @@ def FPR64INX : RegisterOperand { let DecoderMethod = "DecodeGPRRegisterClass"; } -def FPR64IN32X : RegisterOperand { - let ParserMatchClass = GPRPF64AsFPR; +def FPR64IN32X : RegisterOperand { + let ParserMatchClass = GPRPairAsFPR; } def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>; @@ -515,15 +515,15 @@ def PseudoFROUND_D_IN32X : PseudoFROUND; /// Loads let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in -def PseudoRV32ZdinxLD : Pseudo<(outs GPRPF64:$dst), (ins GPR:$rs1, simm12:$imm12), []>; +def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>; def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))), (PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>; /// Stores let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in -def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPF64:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>; -def : Pat<(store (f64 GPRPF64:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)), - (PseudoRV32ZdinxSD GPRPF64:$rs2, GPR:$rs1, simm12:$imm12)>; +def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>; +def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)), + (PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>; /// Pseudo-instructions needed for the soft-float ABI with RV32D diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index a59d058382fe..5a4d8c4cfece 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -63,7 +63,10 @@ def sub_vrm1_5 : ComposedSubRegIndex; def sub_vrm1_6 : ComposedSubRegIndex; def sub_vrm1_7 : ComposedSubRegIndex; -def sub_32_hi : SubRegIndex<32, 32>; +// GPR sizes change with HwMode. +// FIXME: Support HwMode in SubRegIndex? +def sub_gpr_even : SubRegIndex<-1>; +def sub_gpr_odd : SubRegIndex<-1, -1>; } // Namespace = "RISCV" // Integer registers @@ -118,6 +121,8 @@ def XLenVT : ValueTypeByHwMode<[RV32, RV64], // Allow f64 in GPR for ZDINX on RV64. def XLenFVT : ValueTypeByHwMode<[RV64], [f64]>; +def XLenPairFVT : ValueTypeByHwMode<[RV32], + [f64]>; def XLenRI : RegInfoByHwMode< [RV32, RV64], [RegInfo<32,32,32>, RegInfo<64,64,64>]>; @@ -546,33 +551,37 @@ def DUMMY_REG_PAIR_WITH_X0 : RISCVReg<0, "0">; def GPRAll : GPRRegisterClass<(add GPR, DUMMY_REG_PAIR_WITH_X0)>; let RegAltNameIndices = [ABIRegAltName] in { - def X0_PD : RISCVRegWithSubRegs<0, X0.AsmName, - [X0, DUMMY_REG_PAIR_WITH_X0], - X0.AltNames> { - let SubRegIndices = [sub_32, sub_32_hi]; + def X0_Pair : RISCVRegWithSubRegs<0, X0.AsmName, + [X0, DUMMY_REG_PAIR_WITH_X0], + X0.AltNames> { + let SubRegIndices = [sub_gpr_even, sub_gpr_odd]; let CoveredBySubRegs = 1; } foreach I = 1-15 in { defvar Index = !shl(I, 1); + defvar IndexP1 = !add(Index, 1); defvar Reg = !cast("X"#Index); - defvar RegP1 = !cast("X"#!add(Index,1)); - def X#Index#_PD : RISCVRegWithSubRegs { - let SubRegIndices = [sub_32, sub_32_hi]; + defvar RegP1 = !cast("X"#IndexP1); + def "X" # Index #"_X" # IndexP1 : RISCVRegWithSubRegs { + let SubRegIndices = [sub_gpr_even, sub_gpr_odd]; let CoveredBySubRegs = 1; } } } -let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in -def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add - X10_PD, X12_PD, X14_PD, X16_PD, - X6_PD, - X28_PD, X30_PD, - X8_PD, - X18_PD, X20_PD, X22_PD, X24_PD, X26_PD, - X0_PD, X2_PD, X4_PD +let RegInfos = RegInfoByHwMode<[RV32, RV64], + [RegInfo<64, 64, 64>, RegInfo<128, 128, 128>]>, + DecoderMethod = "DecodeGPRPairRegisterClass" in +def GPRPair : RegisterClass<"RISCV", [XLenPairFVT], 64, (add + X10_X11, X12_X13, X14_X15, X16_X17, + X6_X7, + X28_X29, X30_X31, + X8_X9, + X18_X19, X20_X21, X22_X23, X24_X25, X26_X27, + X0_Pair, X2_X3, X4_X5 )>; // The register class is added for inline assembly for vector mask types. -- GitLab From 6eb372e4e46a6dc4511f454b6501e93eb4cad22d Mon Sep 17 00:00:00 2001 From: Piotr Zegar Date: Tue, 9 Jan 2024 18:22:03 +0100 Subject: [PATCH 229/652] [clang-tidy] Improve performance of misc-const-correctness (#72705) Replaced certain AST matchers in ExprMutationAnalyzer with a more direct utilization of AST classes. The primary bottleneck was identified in the canResolveToExpr AST matcher. Since this matcher was employed multiple times and used recursively, each invocation led to the constant creation and destruction of other matchers within it. Additionally, the continual comparison of DynTypedNode resulted in significant performance degradation. The optimization was tested on the TargetLowering.cpp file. Originally, the check took 156 seconds on that file, but after implementing this enhancement, it now takes approximately 40 seconds, making it nearly four times faster. Despite this improvement, there are still numerous issues in this file. To further reduce the computational cost of this class, it is advisable to consider removing the remaining matchers and exploring alternatives such as leveraging RecursiveASTVisitor and increasing the direct use of AST classes. Closes #71786 --- clang-tools-extra/docs/ReleaseNotes.rst | 3 +- clang/lib/Analysis/ExprMutationAnalyzer.cpp | 355 +++++++++++--------- 2 files changed, 193 insertions(+), 165 deletions(-) diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index d7f46cede037..b4d87e0ed2a6 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -368,7 +368,8 @@ Changes in existing checks ` check to avoid false positive when using pointer to member function. Additionally, the check no longer emits a diagnostic when a variable that is not type-dependent is an operand of a - type-dependent binary operator. + type-dependent binary operator. Improved performance of the check through + optimizations. - Improved :doc:`misc-include-cleaner ` check by adding option diff --git a/clang/lib/Analysis/ExprMutationAnalyzer.cpp b/clang/lib/Analysis/ExprMutationAnalyzer.cpp index 624a643cc60e..c0de9277ff86 100644 --- a/clang/lib/Analysis/ExprMutationAnalyzer.cpp +++ b/clang/lib/Analysis/ExprMutationAnalyzer.cpp @@ -15,6 +15,81 @@ namespace clang { using namespace ast_matchers; +// Check if result of Source expression could be a Target expression. +// Checks: +// - Implicit Casts +// - Binary Operators +// - ConditionalOperator +// - BinaryConditionalOperator +static bool canExprResolveTo(const Expr *Source, const Expr *Target) { + + const auto IgnoreDerivedToBase = [](const Expr *E, auto Matcher) { + if (Matcher(E)) + return true; + if (const auto *Cast = dyn_cast(E)) { + if ((Cast->getCastKind() == CK_DerivedToBase || + Cast->getCastKind() == CK_UncheckedDerivedToBase) && + Matcher(Cast->getSubExpr())) + return true; + } + return false; + }; + + const auto EvalCommaExpr = [](const Expr *E, auto Matcher) { + const Expr *Result = E; + while (const auto *BOComma = + dyn_cast_or_null(Result->IgnoreParens())) { + if (!BOComma->isCommaOp()) + break; + Result = BOComma->getRHS(); + } + + return Result != E && Matcher(Result); + }; + + // The 'ConditionalOperatorM' matches on ` ? : `. + // This matching must be recursive because `` can be anything resolving + // to the `InnerMatcher`, for example another conditional operator. + // The edge-case `BaseClass &b = ? DerivedVar1 : DerivedVar2;` + // is handled, too. The implicit cast happens outside of the conditional. + // This is matched by `IgnoreDerivedToBase(canResolveToExpr(InnerMatcher))` + // below. + const auto ConditionalOperatorM = [Target](const Expr *E) { + if (const auto *OP = dyn_cast(E)) { + if (const auto *TE = OP->getTrueExpr()->IgnoreParens()) + if (canExprResolveTo(TE, Target)) + return true; + if (const auto *FE = OP->getFalseExpr()->IgnoreParens()) + if (canExprResolveTo(FE, Target)) + return true; + } + return false; + }; + + const auto ElvisOperator = [Target](const Expr *E) { + if (const auto *OP = dyn_cast(E)) { + if (const auto *TE = OP->getTrueExpr()->IgnoreParens()) + if (canExprResolveTo(TE, Target)) + return true; + if (const auto *FE = OP->getFalseExpr()->IgnoreParens()) + if (canExprResolveTo(FE, Target)) + return true; + } + return false; + }; + + const Expr *SourceExprP = Source->IgnoreParens(); + return IgnoreDerivedToBase(SourceExprP, + [&](const Expr *E) { + return E == Target || ConditionalOperatorM(E) || + ElvisOperator(E); + }) || + EvalCommaExpr(SourceExprP, [&](const Expr *E) { + return IgnoreDerivedToBase( + E->IgnoreParens(), [&](const Expr *EE) { return EE == Target; }); + }); +} + namespace { AST_MATCHER_P(LambdaExpr, hasCaptureInit, const Expr *, E) { @@ -27,56 +102,14 @@ AST_MATCHER_P(CXXForRangeStmt, hasRangeStmt, return InnerMatcher.matches(*Range, Finder, Builder); } -AST_MATCHER_P(Expr, maybeEvalCommaExpr, ast_matchers::internal::Matcher, - InnerMatcher) { - const Expr *Result = &Node; - while (const auto *BOComma = - dyn_cast_or_null(Result->IgnoreParens())) { - if (!BOComma->isCommaOp()) - break; - Result = BOComma->getRHS(); - } - return InnerMatcher.matches(*Result, Finder, Builder); -} - -AST_MATCHER_P(Stmt, canResolveToExpr, ast_matchers::internal::Matcher, - InnerMatcher) { +AST_MATCHER_P(Stmt, canResolveToExpr, const Stmt *, Inner) { auto *Exp = dyn_cast(&Node); - if (!Exp) { - return stmt().matches(Node, Finder, Builder); - } - - auto DerivedToBase = [](const ast_matchers::internal::Matcher &Inner) { - return implicitCastExpr(anyOf(hasCastKind(CK_DerivedToBase), - hasCastKind(CK_UncheckedDerivedToBase)), - hasSourceExpression(Inner)); - }; - auto IgnoreDerivedToBase = - [&DerivedToBase](const ast_matchers::internal::Matcher &Inner) { - return ignoringParens(expr(anyOf(Inner, DerivedToBase(Inner)))); - }; - - // The 'ConditionalOperator' matches on ` ? : `. - // This matching must be recursive because `` can be anything resolving - // to the `InnerMatcher`, for example another conditional operator. - // The edge-case `BaseClass &b = ? DerivedVar1 : DerivedVar2;` - // is handled, too. The implicit cast happens outside of the conditional. - // This is matched by `IgnoreDerivedToBase(canResolveToExpr(InnerMatcher))` - // below. - auto const ConditionalOperator = conditionalOperator(anyOf( - hasTrueExpression(ignoringParens(canResolveToExpr(InnerMatcher))), - hasFalseExpression(ignoringParens(canResolveToExpr(InnerMatcher))))); - auto const ElvisOperator = binaryConditionalOperator(anyOf( - hasTrueExpression(ignoringParens(canResolveToExpr(InnerMatcher))), - hasFalseExpression(ignoringParens(canResolveToExpr(InnerMatcher))))); - - auto const ComplexMatcher = ignoringParens( - expr(anyOf(IgnoreDerivedToBase(InnerMatcher), - maybeEvalCommaExpr(IgnoreDerivedToBase(InnerMatcher)), - IgnoreDerivedToBase(ConditionalOperator), - IgnoreDerivedToBase(ElvisOperator)))); - - return ComplexMatcher.matches(*Exp, Finder, Builder); + if (!Exp) + return true; + auto *Target = dyn_cast(Inner); + if (!Target) + return false; + return canExprResolveTo(Exp, Target); } // Similar to 'hasAnyArgument', but does not work because 'InitListExpr' does @@ -121,6 +154,12 @@ AST_MATCHER_P(GenericSelectionExpr, hasControllingExpr, return InnerMatcher.matches(*Node.getControllingExpr(), Finder, Builder); } +template +ast_matchers::internal::Matcher +findFirst(const ast_matchers::internal::Matcher &Matcher) { + return anyOf(Matcher, hasDescendant(Matcher)); +} + const auto nonConstReferenceType = [] { return hasUnqualifiedDesugaredType( referenceType(pointee(unless(isConstQualified())))); @@ -220,8 +259,8 @@ bool ExprMutationAnalyzer::isUnevaluated(const Stmt *Exp, const Stmt &Stm, return selectFirst( NodeID::value, match( - findAll( - stmt(canResolveToExpr(equalsNode(Exp)), + findFirst( + stmt(canResolveToExpr(Exp), anyOf( // `Exp` is part of the underlying expression of // decltype/typeof if it has an ancestor of @@ -275,44 +314,41 @@ const Stmt *ExprMutationAnalyzer::findDeclPointeeMutation( const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) { // LHS of any assignment operators. - const auto AsAssignmentLhs = binaryOperator( - isAssignmentOperator(), hasLHS(canResolveToExpr(equalsNode(Exp)))); + const auto AsAssignmentLhs = + binaryOperator(isAssignmentOperator(), hasLHS(canResolveToExpr(Exp))); // Operand of increment/decrement operators. const auto AsIncDecOperand = unaryOperator(anyOf(hasOperatorName("++"), hasOperatorName("--")), - hasUnaryOperand(canResolveToExpr(equalsNode(Exp)))); + hasUnaryOperand(canResolveToExpr(Exp))); // Invoking non-const member function. // A member function is assumed to be non-const when it is unresolved. const auto NonConstMethod = cxxMethodDecl(unless(isConst())); const auto AsNonConstThis = expr(anyOf( - cxxMemberCallExpr(on(canResolveToExpr(equalsNode(Exp))), - unless(isConstCallee())), + cxxMemberCallExpr(on(canResolveToExpr(Exp)), unless(isConstCallee())), cxxOperatorCallExpr(callee(NonConstMethod), - hasArgument(0, canResolveToExpr(equalsNode(Exp)))), + hasArgument(0, canResolveToExpr(Exp))), // In case of a templated type, calling overloaded operators is not // resolved and modelled as `binaryOperator` on a dependent type. // Such instances are considered a modification, because they can modify // in different instantiations of the template. - binaryOperator( - hasEitherOperand(ignoringImpCasts(canResolveToExpr(equalsNode(Exp)))), - isTypeDependent()), + binaryOperator(isTypeDependent(), + hasEitherOperand(ignoringImpCasts(canResolveToExpr(Exp)))), // Within class templates and member functions the member expression might // not be resolved. In that case, the `callExpr` is considered to be a // modification. - callExpr( - callee(expr(anyOf(unresolvedMemberExpr(hasObjectExpression( - canResolveToExpr(equalsNode(Exp)))), - cxxDependentScopeMemberExpr(hasObjectExpression( - canResolveToExpr(equalsNode(Exp)))))))), + callExpr(callee(expr(anyOf( + unresolvedMemberExpr(hasObjectExpression(canResolveToExpr(Exp))), + cxxDependentScopeMemberExpr( + hasObjectExpression(canResolveToExpr(Exp))))))), // Match on a call to a known method, but the call itself is type // dependent (e.g. `vector v; v.push(T{});` in a templated function). - callExpr(allOf(isTypeDependent(), - callee(memberExpr(hasDeclaration(NonConstMethod), - hasObjectExpression(canResolveToExpr( - equalsNode(Exp))))))))); + callExpr(allOf( + isTypeDependent(), + callee(memberExpr(hasDeclaration(NonConstMethod), + hasObjectExpression(canResolveToExpr(Exp)))))))); // Taking address of 'Exp'. // We're assuming 'Exp' is mutated as soon as its address is taken, though in @@ -322,11 +358,10 @@ const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) { unaryOperator(hasOperatorName("&"), // A NoOp implicit cast is adding const. unless(hasParent(implicitCastExpr(hasCastKind(CK_NoOp)))), - hasUnaryOperand(canResolveToExpr(equalsNode(Exp)))); - const auto AsPointerFromArrayDecay = - castExpr(hasCastKind(CK_ArrayToPointerDecay), - unless(hasParent(arraySubscriptExpr())), - has(canResolveToExpr(equalsNode(Exp)))); + hasUnaryOperand(canResolveToExpr(Exp))); + const auto AsPointerFromArrayDecay = castExpr( + hasCastKind(CK_ArrayToPointerDecay), + unless(hasParent(arraySubscriptExpr())), has(canResolveToExpr(Exp))); // Treat calling `operator->()` of move-only classes as taking address. // These are typically smart pointers with unique ownership so we treat // mutation of pointee as mutation of the smart pointer itself. @@ -334,7 +369,7 @@ const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) { hasOverloadedOperatorName("->"), callee( cxxMethodDecl(ofClass(isMoveOnly()), returns(nonConstPointerType()))), - argumentCountIs(1), hasArgument(0, canResolveToExpr(equalsNode(Exp)))); + argumentCountIs(1), hasArgument(0, canResolveToExpr(Exp))); // Used as non-const-ref argument when calling a function. // An argument is assumed to be non-const-ref when the function is unresolved. @@ -342,8 +377,8 @@ const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) { // findFunctionArgMutation which has additional smarts for handling forwarding // references. const auto NonConstRefParam = forEachArgumentWithParamType( - anyOf(canResolveToExpr(equalsNode(Exp)), - memberExpr(hasObjectExpression(canResolveToExpr(equalsNode(Exp))))), + anyOf(canResolveToExpr(Exp), + memberExpr(hasObjectExpression(canResolveToExpr(Exp)))), nonConstReferenceType()); const auto NotInstantiated = unless(hasDeclaration(isInstantiated())); const auto TypeDependentCallee = @@ -354,19 +389,17 @@ const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) { const auto AsNonConstRefArg = anyOf( callExpr(NonConstRefParam, NotInstantiated), cxxConstructExpr(NonConstRefParam, NotInstantiated), - callExpr(TypeDependentCallee, - hasAnyArgument(canResolveToExpr(equalsNode(Exp)))), - cxxUnresolvedConstructExpr( - hasAnyArgument(canResolveToExpr(equalsNode(Exp)))), + callExpr(TypeDependentCallee, hasAnyArgument(canResolveToExpr(Exp))), + cxxUnresolvedConstructExpr(hasAnyArgument(canResolveToExpr(Exp))), // Previous False Positive in the following Code: // `template void f() { int i = 42; new Type(i); }` // Where the constructor of `Type` takes its argument as reference. // The AST does not resolve in a `cxxConstructExpr` because it is // type-dependent. - parenListExpr(hasDescendant(expr(canResolveToExpr(equalsNode(Exp))))), + parenListExpr(hasDescendant(expr(canResolveToExpr(Exp)))), // If the initializer is for a reference type, there is no cast for // the variable. Values are cast to RValue first. - initListExpr(hasAnyInit(expr(canResolveToExpr(equalsNode(Exp)))))); + initListExpr(hasAnyInit(expr(canResolveToExpr(Exp))))); // Captured by a lambda by reference. // If we're initializing a capture with 'Exp' directly then we're initializing @@ -380,76 +413,72 @@ const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) { // For returning by const-ref there will be an ImplicitCastExpr (for // adding const.) const auto AsNonConstRefReturn = - returnStmt(hasReturnValue(canResolveToExpr(equalsNode(Exp)))); + returnStmt(hasReturnValue(canResolveToExpr(Exp))); // It is used as a non-const-reference for initalizing a range-for loop. - const auto AsNonConstRefRangeInit = cxxForRangeStmt( - hasRangeInit(declRefExpr(allOf(canResolveToExpr(equalsNode(Exp)), - hasType(nonConstReferenceType()))))); + const auto AsNonConstRefRangeInit = cxxForRangeStmt(hasRangeInit(declRefExpr( + allOf(canResolveToExpr(Exp), hasType(nonConstReferenceType()))))); const auto Matches = match( - traverse(TK_AsIs, - findAll(stmt(anyOf(AsAssignmentLhs, AsIncDecOperand, - AsNonConstThis, AsAmpersandOperand, - AsPointerFromArrayDecay, AsOperatorArrowThis, - AsNonConstRefArg, AsLambdaRefCaptureInit, - AsNonConstRefReturn, AsNonConstRefRangeInit)) - .bind("stmt"))), + traverse( + TK_AsIs, + findFirst(stmt(anyOf(AsAssignmentLhs, AsIncDecOperand, AsNonConstThis, + AsAmpersandOperand, AsPointerFromArrayDecay, + AsOperatorArrowThis, AsNonConstRefArg, + AsLambdaRefCaptureInit, AsNonConstRefReturn, + AsNonConstRefRangeInit)) + .bind("stmt"))), Stm, Context); return selectFirst("stmt", Matches); } const Stmt *ExprMutationAnalyzer::findMemberMutation(const Expr *Exp) { // Check whether any member of 'Exp' is mutated. - const auto MemberExprs = - match(findAll(expr(anyOf(memberExpr(hasObjectExpression( - canResolveToExpr(equalsNode(Exp)))), - cxxDependentScopeMemberExpr(hasObjectExpression( - canResolveToExpr(equalsNode(Exp)))), - binaryOperator(hasOperatorName(".*"), - hasLHS(equalsNode(Exp))))) - .bind(NodeID::value)), - Stm, Context); + const auto MemberExprs = match( + findAll(expr(anyOf(memberExpr(hasObjectExpression(canResolveToExpr(Exp))), + cxxDependentScopeMemberExpr( + hasObjectExpression(canResolveToExpr(Exp))), + binaryOperator(hasOperatorName(".*"), + hasLHS(equalsNode(Exp))))) + .bind(NodeID::value)), + Stm, Context); return findExprMutation(MemberExprs); } const Stmt *ExprMutationAnalyzer::findArrayElementMutation(const Expr *Exp) { // Check whether any element of an array is mutated. - const auto SubscriptExprs = - match(findAll(arraySubscriptExpr( - anyOf(hasBase(canResolveToExpr(equalsNode(Exp))), - hasBase(implicitCastExpr( - allOf(hasCastKind(CK_ArrayToPointerDecay), - hasSourceExpression(canResolveToExpr( - equalsNode(Exp)))))))) - .bind(NodeID::value)), - Stm, Context); + const auto SubscriptExprs = match( + findAll(arraySubscriptExpr( + anyOf(hasBase(canResolveToExpr(Exp)), + hasBase(implicitCastExpr(allOf( + hasCastKind(CK_ArrayToPointerDecay), + hasSourceExpression(canResolveToExpr(Exp))))))) + .bind(NodeID::value)), + Stm, Context); return findExprMutation(SubscriptExprs); } const Stmt *ExprMutationAnalyzer::findCastMutation(const Expr *Exp) { // If the 'Exp' is explicitly casted to a non-const reference type the // 'Exp' is considered to be modified. - const auto ExplicitCast = match( - findAll( - stmt(castExpr(hasSourceExpression(canResolveToExpr(equalsNode(Exp))), - explicitCastExpr( - hasDestinationType(nonConstReferenceType())))) - .bind("stmt")), - Stm, Context); + const auto ExplicitCast = + match(findFirst(stmt(castExpr(hasSourceExpression(canResolveToExpr(Exp)), + explicitCastExpr(hasDestinationType( + nonConstReferenceType())))) + .bind("stmt")), + Stm, Context); if (const auto *CastStmt = selectFirst("stmt", ExplicitCast)) return CastStmt; // If 'Exp' is casted to any non-const reference type, check the castExpr. const auto Casts = match( - findAll( - expr(castExpr(hasSourceExpression(canResolveToExpr(equalsNode(Exp))), - anyOf(explicitCastExpr( - hasDestinationType(nonConstReferenceType())), - implicitCastExpr(hasImplicitDestinationType( - nonConstReferenceType()))))) - .bind(NodeID::value)), + findAll(expr(castExpr(hasSourceExpression(canResolveToExpr(Exp)), + anyOf(explicitCastExpr(hasDestinationType( + nonConstReferenceType())), + implicitCastExpr(hasImplicitDestinationType( + nonConstReferenceType()))))) + .bind(NodeID::value)), Stm, Context); if (const Stmt *S = findExprMutation(Casts)) @@ -458,7 +487,7 @@ const Stmt *ExprMutationAnalyzer::findCastMutation(const Expr *Exp) { const auto Calls = match(findAll(callExpr(callee(namedDecl( hasAnyName("::std::move", "::std::forward"))), - hasArgument(0, canResolveToExpr(equalsNode(Exp)))) + hasArgument(0, canResolveToExpr(Exp))) .bind("expr")), Stm, Context); return findExprMutation(Calls); @@ -473,16 +502,16 @@ const Stmt *ExprMutationAnalyzer::findRangeLoopMutation(const Expr *Exp) { // array is considered modified if the loop-variable is a non-const reference. const auto DeclStmtToNonRefToArray = declStmt(hasSingleDecl(varDecl(hasType( hasUnqualifiedDesugaredType(referenceType(pointee(arrayType()))))))); - const auto RefToArrayRefToElements = - match(findAll(stmt(cxxForRangeStmt( - hasLoopVariable( - varDecl(anyOf(hasType(nonConstReferenceType()), - hasType(nonConstPointerType()))) - .bind(NodeID::value)), - hasRangeStmt(DeclStmtToNonRefToArray), - hasRangeInit(canResolveToExpr(equalsNode(Exp))))) - .bind("stmt")), - Stm, Context); + const auto RefToArrayRefToElements = match( + findFirst(stmt(cxxForRangeStmt( + hasLoopVariable( + varDecl(anyOf(hasType(nonConstReferenceType()), + hasType(nonConstPointerType()))) + .bind(NodeID::value)), + hasRangeStmt(DeclStmtToNonRefToArray), + hasRangeInit(canResolveToExpr(Exp)))) + .bind("stmt")), + Stm, Context); if (const auto *BadRangeInitFromArray = selectFirst("stmt", RefToArrayRefToElements)) @@ -505,12 +534,12 @@ const Stmt *ExprMutationAnalyzer::findRangeLoopMutation(const Expr *Exp) { hasSingleDecl(varDecl(hasType(hasUnqualifiedDesugaredType(referenceType( pointee(hasDeclaration(cxxRecordDecl(HasAnyNonConstIterator))))))))); - const auto RefToContainerBadIterators = - match(findAll(stmt(cxxForRangeStmt(allOf( - hasRangeStmt(DeclStmtToNonConstIteratorContainer), - hasRangeInit(canResolveToExpr(equalsNode(Exp)))))) - .bind("stmt")), - Stm, Context); + const auto RefToContainerBadIterators = match( + findFirst(stmt(cxxForRangeStmt(allOf( + hasRangeStmt(DeclStmtToNonConstIteratorContainer), + hasRangeInit(canResolveToExpr(Exp))))) + .bind("stmt")), + Stm, Context); if (const auto *BadIteratorsContainer = selectFirst("stmt", RefToContainerBadIterators)) @@ -522,7 +551,7 @@ const Stmt *ExprMutationAnalyzer::findRangeLoopMutation(const Expr *Exp) { match(findAll(cxxForRangeStmt( hasLoopVariable(varDecl(hasType(nonConstReferenceType())) .bind(NodeID::value)), - hasRangeInit(canResolveToExpr(equalsNode(Exp))))), + hasRangeInit(canResolveToExpr(Exp)))), Stm, Context); return findDeclMutation(LoopVars); } @@ -531,31 +560,29 @@ const Stmt *ExprMutationAnalyzer::findReferenceMutation(const Expr *Exp) { // Follow non-const reference returned by `operator*()` of move-only classes. // These are typically smart pointers with unique ownership so we treat // mutation of pointee as mutation of the smart pointer itself. - const auto Ref = - match(findAll(cxxOperatorCallExpr( - hasOverloadedOperatorName("*"), - callee(cxxMethodDecl(ofClass(isMoveOnly()), - returns(nonConstReferenceType()))), - argumentCountIs(1), - hasArgument(0, canResolveToExpr(equalsNode(Exp)))) - .bind(NodeID::value)), - Stm, Context); + const auto Ref = match( + findAll(cxxOperatorCallExpr( + hasOverloadedOperatorName("*"), + callee(cxxMethodDecl(ofClass(isMoveOnly()), + returns(nonConstReferenceType()))), + argumentCountIs(1), hasArgument(0, canResolveToExpr(Exp))) + .bind(NodeID::value)), + Stm, Context); if (const Stmt *S = findExprMutation(Ref)) return S; // If 'Exp' is bound to a non-const reference, check all declRefExpr to that. const auto Refs = match( stmt(forEachDescendant( - varDecl( - hasType(nonConstReferenceType()), - hasInitializer(anyOf(canResolveToExpr(equalsNode(Exp)), - memberExpr(hasObjectExpression( - canResolveToExpr(equalsNode(Exp)))))), - hasParent(declStmt().bind("stmt")), - // Don't follow the reference in range statement, we've - // handled that separately. - unless(hasParent(declStmt(hasParent( - cxxForRangeStmt(hasRangeStmt(equalsBoundNode("stmt")))))))) + varDecl(hasType(nonConstReferenceType()), + hasInitializer(anyOf( + canResolveToExpr(Exp), + memberExpr(hasObjectExpression(canResolveToExpr(Exp))))), + hasParent(declStmt().bind("stmt")), + // Don't follow the reference in range statement, we've + // handled that separately. + unless(hasParent(declStmt(hasParent(cxxForRangeStmt( + hasRangeStmt(equalsBoundNode("stmt")))))))) .bind(NodeID::value))), Stm, Context); return findDeclMutation(Refs); @@ -563,7 +590,7 @@ const Stmt *ExprMutationAnalyzer::findReferenceMutation(const Expr *Exp) { const Stmt *ExprMutationAnalyzer::findFunctionArgMutation(const Expr *Exp) { const auto NonConstRefParam = forEachArgumentWithParam( - canResolveToExpr(equalsNode(Exp)), + canResolveToExpr(Exp), parmVarDecl(hasType(nonConstReferenceType())).bind("parm")); const auto IsInstantiated = hasDeclaration(isInstantiated()); const auto FuncDecl = hasDeclaration(functionDecl().bind("func")); -- GitLab From 810c291574831eb06bfcb8fa0e27f9bbd5af6c59 Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 9 Jan 2024 17:25:46 +0000 Subject: [PATCH 230/652] [Flang] Generate inline reduction loops for elemental count intrinsics (#75774) This adds a ReductionElementalConversion transform to OptimizedBufferizationPass, taking hlfir::count(hlfir::elemental) and generating the inline loop to perform the count of true elements. This lets us generate a single loop instead of ending up as two plus a temporary. Any and All should be able to share the same code with a different function/initial value. --- .../Transforms/OptimizedBufferization.cpp | 120 +++++++ flang/test/HLFIR/count-elemental.fir | 314 ++++++++++++++++++ 2 files changed, 434 insertions(+) create mode 100644 flang/test/HLFIR/count-elemental.fir diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp index 7abfa20493c7..afdcda29e2fe 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp @@ -659,6 +659,125 @@ mlir::LogicalResult VariableAssignBufferization::matchAndRewrite( return mlir::success(); } +using GenBodyFn = + std::function &)>; +static mlir::Value generateReductionLoop(fir::FirOpBuilder &builder, + mlir::Location loc, mlir::Value init, + mlir::Value shape, GenBodyFn genBody) { + auto extents = hlfir::getIndexExtents(loc, builder, shape); + mlir::Value reduction = init; + mlir::IndexType idxTy = builder.getIndexType(); + mlir::Value oneIdx = builder.createIntegerConstant(loc, idxTy, 1); + + // Create a reduction loop nest. We use one-based indices so that they can be + // passed to the elemental, and reverse the order so that they can be + // generated in column-major order for better performance. + llvm::SmallVector indices(extents.size(), mlir::Value{}); + for (unsigned i = 0; i < extents.size(); ++i) { + auto loop = builder.create( + loc, oneIdx, extents[extents.size() - i - 1], oneIdx, false, + /*finalCountValue=*/false, reduction); + reduction = loop.getRegionIterArgs()[0]; + indices[extents.size() - i - 1] = loop.getInductionVar(); + // Set insertion point to the loop body so that the next loop + // is inserted inside the current one. + builder.setInsertionPointToStart(loop.getBody()); + } + + // Generate the body + reduction = genBody(builder, loc, reduction, indices); + + // Unwind the loop nest. + for (unsigned i = 0; i < extents.size(); ++i) { + auto result = builder.create(loc, reduction); + auto loop = mlir::cast(result->getParentOp()); + reduction = loop.getResult(0); + // Set insertion point after the loop operation that we have + // just processed. + builder.setInsertionPointAfter(loop.getOperation()); + } + + return reduction; +} + +/// Given a reduction operation with an elemental mask, attempt to generate a +/// do-loop to perform the operation inline. +/// %e = hlfir.elemental %shape unordered +/// %r = hlfir.count %e +/// => +/// %r = for.do_loop %arg = 1 to bound(%shape) step 1 iter_args(%arg2 = init) +/// %i = +/// %c = %i +/// fir.result %c +template +class ReductionElementalConversion : public mlir::OpRewritePattern { +public: + using mlir::OpRewritePattern::OpRewritePattern; + + mlir::LogicalResult + matchAndRewrite(Op op, mlir::PatternRewriter &rewriter) const override { + mlir::Location loc = op.getLoc(); + hlfir::ElementalOp elemental = + op.getMask().template getDefiningOp(); + if (!elemental || op.getDim()) + return rewriter.notifyMatchFailure(op, "Did not find valid elemental"); + + fir::KindMapping kindMap = + fir::getKindMapping(op->template getParentOfType()); + fir::FirOpBuilder builder{op, kindMap}; + + mlir::Value init; + GenBodyFn genBodyFn; + if constexpr (std::is_same_v) { + init = builder.createIntegerConstant(loc, op.getType(), 0); + genBodyFn = [elemental](fir::FirOpBuilder builder, mlir::Location loc, + mlir::Value reduction, + const llvm::SmallVectorImpl &indices) + -> mlir::Value { + // Inline the elemental and get the condition from it. + auto yield = inlineElementalOp(loc, builder, elemental, indices); + mlir::Value cond = builder.create( + loc, builder.getI1Type(), yield.getElementValue()); + yield->erase(); + + // Conditionally add one to the current value + mlir::Value one = + builder.createIntegerConstant(loc, reduction.getType(), 1); + mlir::Value add1 = + builder.create(loc, reduction, one); + return builder.create(loc, cond, add1, + reduction); + }; + } else { + static_assert("Expected Op to be handled"); + return mlir::failure(); + } + + mlir::Value res = generateReductionLoop(builder, loc, init, + elemental.getOperand(0), genBodyFn); + if (res.getType() != op.getType()) + res = builder.create(loc, op.getType(), res); + + // Check if the op was the only user of the elemental (apart from a + // destroy), and remove it if so. + mlir::Operation::user_range elemUsers = elemental->getUsers(); + hlfir::DestroyOp elemDestroy; + if (std::distance(elemUsers.begin(), elemUsers.end()) == 2) { + elemDestroy = mlir::dyn_cast(*elemUsers.begin()); + if (!elemDestroy) + elemDestroy = mlir::dyn_cast(*++elemUsers.begin()); + } + + rewriter.replaceOp(op, res); + if (elemDestroy) { + rewriter.eraseOp(elemDestroy); + rewriter.eraseOp(elemental); + } + return mlir::success(); + } +}; + class OptimizedBufferizationPass : public hlfir::impl::OptimizedBufferizationBase< OptimizedBufferizationPass> { @@ -681,6 +800,7 @@ public: patterns.insert(context); patterns.insert(context); patterns.insert(context); + patterns.insert>(context); if (mlir::failed(mlir::applyPatternsAndFoldGreedily( func, std::move(patterns), config))) { diff --git a/flang/test/HLFIR/count-elemental.fir b/flang/test/HLFIR/count-elemental.fir new file mode 100644 index 000000000000..0df5cc3c031e --- /dev/null +++ b/flang/test/HLFIR/count-elemental.fir @@ -0,0 +1,314 @@ +// RUN: fir-opt %s -opt-bufferization | FileCheck %s + +func.func @_QFPtest(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca i32 {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4:2 = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %5:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = fir.load %2#0 : !fir.ref + %7 = fir.convert %6 : (i32) -> i64 + %8 = fir.shape %c7 : (index) -> !fir.shape<1> + %9 = hlfir.designate %1#0 (%7, %c1:%c7:%c1) shape %8 : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> + %10 = fir.load %5#0 : !fir.ref + %11 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7x!fir.logical<4>> { + ^bb0(%arg3: index): + %14 = hlfir.designate %9 (%arg3) : (!fir.box>, index) -> !fir.ref + %15 = fir.load %14 : !fir.ref + %16 = arith.cmpi sge, %15, %10 : i32 + %17 = fir.convert %16 : (i1) -> !fir.logical<4> + hlfir.yield_element %17 : !fir.logical<4> + } + %12 = hlfir.count %11 : (!hlfir.expr<7x!fir.logical<4>>) -> i32 + hlfir.assign %12 to %4#0 : i32, !fir.ref + hlfir.destroy %11 : !hlfir.expr<7x!fir.logical<4>> + %13 = fir.load %4#1 : !fir.ref + return %13 : i32 +} +// CHECK-LABEL: func.func @_QFPtest(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { +// CHECK-NEXT: %c1_i32 = arith.constant 1 : i32 +// CHECK-NEXT: %c0_i32 = arith.constant 0 : i32 +// CHECK-NEXT: %c1 = arith.constant 1 : index +// CHECK-NEXT: %c4 = arith.constant 4 : index +// CHECK-NEXT: %c7 = arith.constant 7 : index +// CHECK-NEXT: %[[V0:.*]] = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> +// CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %arg0(%[[V0]]) +// CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %arg1 +// CHECK-NEXT: %[[V3:.*]] = fir.alloca i32 +// CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[V3]] +// CHECK-NEXT: %[[V5:.*]]:2 = hlfir.declare %arg2 +// CHECK-NEXT: %[[V6:.*]] = fir.load %[[V2]]#0 : !fir.ref +// CHECK-NEXT: %[[V7:.*]] = fir.convert %[[V6]] : (i32) -> i64 +// CHECK-NEXT: %[[V8:.*]] = fir.shape %c7 : (index) -> !fir.shape<1> +// CHECK-NEXT: %[[V9:.*]] = hlfir.designate %[[V1]]#0 (%[[V7]], %c1:%c7:%c1) shape %[[V8]] : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> +// CHECK-NEXT: %[[V10:.*]] = fir.load %[[V5]]#0 : !fir.ref +// CHECK-NEXT: %[[V11:.*]] = fir.do_loop %arg3 = %c1 to %c7 step %c1 iter_args(%arg4 = %c0_i32) -> (i32) { +// CHECK-NEXT: %[[V13:.*]] = hlfir.designate %[[V9]] (%arg3) : (!fir.box>, index) -> !fir.ref +// CHECK-NEXT: %[[V14:.*]] = fir.load %[[V13]] : !fir.ref +// CHECK-NEXT: %[[V15:.*]] = arith.cmpi sge, %[[V14]], %[[V10]] : i32 +// CHECK-NEXT: %[[V16:.*]] = arith.addi %arg4, %c1_i32 : i32 +// CHECK-NEXT: %[[V17:.*]] = arith.select %[[V15]], %[[V16]], %arg4 : i32 +// CHECK-NEXT: fir.result %[[V17]] : i32 +// CHECK-NEXT: } +// CHECK-NEXT: hlfir.assign %[[V11]] to %[[V4]]#0 : i32, !fir.ref +// CHECK-NEXT: %[[V12:.*]] = fir.load %[[V4]]#1 : !fir.ref +// CHECK-NEXT: return %[[V12]] : i32 + +func.func @_QFPtest_kind2(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i16 { + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca i16 {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4:2 = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %5:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = fir.load %2#0 : !fir.ref + %7 = fir.convert %6 : (i32) -> i64 + %8 = fir.shape %c7 : (index) -> !fir.shape<1> + %9 = hlfir.designate %1#0 (%7, %c1:%c7:%c1) shape %8 : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> + %10 = fir.load %5#0 : !fir.ref + %11 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7x!fir.logical<4>> { + ^bb0(%arg3: index): + %14 = hlfir.designate %9 (%arg3) : (!fir.box>, index) -> !fir.ref + %15 = fir.load %14 : !fir.ref + %16 = arith.cmpi sge, %15, %10 : i32 + %17 = fir.convert %16 : (i1) -> !fir.logical<4> + hlfir.yield_element %17 : !fir.logical<4> + } + %12 = hlfir.count %11 : (!hlfir.expr<7x!fir.logical<4>>) -> i16 + hlfir.assign %12 to %4#0 : i16, !fir.ref + hlfir.destroy %11 : !hlfir.expr<7x!fir.logical<4>> + %13 = fir.load %4#1 : !fir.ref + return %13 : i16 +} +// CHECK-LABEL: func.func @_QFPtest_kind2(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i16 { +// CHECK-NEXT: %c1_i16 = arith.constant 1 : i16 +// CHECK-NEXT: %c0_i16 = arith.constant 0 : i16 +// CHECK-NEXT: %c1 = arith.constant 1 : index +// CHECK-NEXT: %c4 = arith.constant 4 : index +// CHECK-NEXT: %c7 = arith.constant 7 : index +// CHECK-NEXT: %[[V0:.*]] = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> +// CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %arg0(%[[V0]]) +// CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %arg1 +// CHECK-NEXT: %[[V3:.*]] = fir.alloca i16 +// CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[V3]] +// CHECK-NEXT: %[[V5:.*]]:2 = hlfir.declare %arg2 +// CHECK-NEXT: %[[V6:.*]] = fir.load %[[V2]]#0 : !fir.ref +// CHECK-NEXT: %[[V7:.*]] = fir.convert %[[V6]] : (i32) -> i64 +// CHECK-NEXT: %[[V8:.*]] = fir.shape %c7 : (index) -> !fir.shape<1> +// CHECK-NEXT: %[[V9:.*]] = hlfir.designate %[[V1]]#0 (%[[V7]], %c1:%c7:%c1) shape %[[V8]] : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> +// CHECK-NEXT: %[[V10:.*]] = fir.load %[[V5]]#0 : !fir.ref +// CHECK-NEXT: %[[V11:.*]] = fir.do_loop %arg3 = %c1 to %c7 step %c1 iter_args(%arg4 = %c0_i16) -> (i16) { +// CHECK-NEXT: %[[V13:.*]] = hlfir.designate %[[V9]] (%arg3) : (!fir.box>, index) -> !fir.ref +// CHECK-NEXT: %[[V14:.*]] = fir.load %[[V13]] : !fir.ref +// CHECK-NEXT: %[[V15:.*]] = arith.cmpi sge, %[[V14]], %[[V10]] : i32 +// CHECK-NEXT: %[[V16:.*]] = arith.addi %arg4, %c1_i16 : i16 +// CHECK-NEXT: %[[V17:.*]] = arith.select %[[V15]], %[[V16]], %arg4 : i16 +// CHECK-NEXT: fir.result %[[V17]] : i16 +// CHECK-NEXT: } +// CHECK-NEXT: hlfir.assign %[[V11]] to %[[V4]]#0 : i16, !fir.ref +// CHECK-NEXT: %[[V12:.*]] = fir.load %[[V4]]#1 : !fir.ref +// CHECK-NEXT: return %[[V12]] : i16 + +func.func @_QFPtest_dim(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> !fir.array<7xi32> { + %c1_i32 = arith.constant 1 : i32 + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca !fir.array<7xi32> {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4 = fir.shape %c7 : (index) -> !fir.shape<1> + %5:2 = hlfir.declare %3(%4) {uniq_name = "_QFFtestEtest"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + %6:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %7 = hlfir.designate %1#0 (%c1:%c4:%c1, %c1:%c7:%c1) shape %0 : (!fir.ref>, index, index, index, index, index, index, !fir.shape<2>) -> !fir.ref> + %8 = fir.load %6#0 : !fir.ref + %9 = hlfir.elemental %0 unordered : (!fir.shape<2>) -> !hlfir.expr<4x7x!fir.logical<4>> { + ^bb0(%arg3: index, %arg4: index): + %12 = hlfir.designate %7 (%arg3, %arg4) : (!fir.ref>, index, index) -> !fir.ref + %13 = fir.load %12 : !fir.ref + %14 = arith.cmpi sge, %13, %8 : i32 + %15 = fir.convert %14 : (i1) -> !fir.logical<4> + hlfir.yield_element %15 : !fir.logical<4> + } + %10 = hlfir.count %9 dim %c1_i32 : (!hlfir.expr<4x7x!fir.logical<4>>, i32) -> !hlfir.expr<7xi32> + hlfir.assign %10 to %5#0 : !hlfir.expr<7xi32>, !fir.ref> + hlfir.destroy %10 : !hlfir.expr<7xi32> + hlfir.destroy %9 : !hlfir.expr<4x7x!fir.logical<4>> + %11 = fir.load %5#1 : !fir.ref> + return %11 : !fir.array<7xi32> +} +// CHECK-LABEL: func.func @_QFPtest_dim( +// CHECK: %{{.*}} = hlfir.count %{{.*}} dim %c1_i32 + + +func.func @_QFPtest_multi(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %c2 = arith.constant 2 : index + %0 = fir.shape %c4, %c7, %c2 : (index, index, index) -> !fir.shape<3> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<3>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca i32 {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4:2 = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %5:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = hlfir.designate %1#0 (%c1:%c4:%c1, %c1:%c7:%c1, %c1:%c2:%c1) shape %0 : (!fir.ref>, index, index, index, index, index, index, index, index, index, !fir.shape<3>) -> !fir.ref> + %7 = fir.load %5#0 : !fir.ref + %8 = hlfir.elemental %0 unordered : (!fir.shape<3>) -> !hlfir.expr<4x7x2x!fir.logical<4>> { + ^bb0(%arg3: index, %arg4: index, %arg5: index): + %11 = hlfir.designate %6 (%arg3, %arg4, %arg5) : (!fir.ref>, index, index, index) -> !fir.ref + %12 = fir.load %11 : !fir.ref + %13 = arith.cmpi sge, %12, %7 : i32 + %14 = fir.convert %13 : (i1) -> !fir.logical<4> + hlfir.yield_element %14 : !fir.logical<4> + } + %9 = hlfir.count %8 : (!hlfir.expr<4x7x2x!fir.logical<4>>) -> i32 + hlfir.assign %9 to %4#0 : i32, !fir.ref + hlfir.destroy %8 : !hlfir.expr<4x7x2x!fir.logical<4>> + %10 = fir.load %4#1 : !fir.ref + return %10 : i32 +} +// CHECK-LABEL: func.func @_QFPtest_multi(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { +// CHECK-NEXT: %c1_i32 = arith.constant 1 : i32 +// CHECK-NEXT: %c0_i32 = arith.constant 0 : i32 +// CHECK-NEXT: %c1 = arith.constant 1 : index +// CHECK-NEXT: %c4 = arith.constant 4 : index +// CHECK-NEXT: %c7 = arith.constant 7 : index +// CHECK-NEXT: %c2 = arith.constant 2 : index +// CHECK-NEXT: %[[V0:.*]] = fir.shape %c4, %c7, %c2 : (index, index, index) -> !fir.shape<3> +// CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %arg0(%[[V0]]) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<3>) -> (!fir.ref>, !fir.ref>) +// CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) +// CHECK-NEXT: %[[V3:.*]] = fir.alloca i32 {bindc_name = "test", uniq_name = "_QFFtestEtest"} +// CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[V3]] {uniq_name = "_QFFtestEtest"} : (!fir.ref) -> (!fir.ref, !fir.ref) +// CHECK-NEXT: %[[V5:.*]]:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) +// CHECK-NEXT: %[[V6:.*]] = hlfir.designate %[[V1]]#0 (%c1:%c4:%c1, %c1:%c7:%c1, %c1:%c2:%c1) shape %[[V0]] : (!fir.ref>, index, index, index, index, index, index, index, index, index, !fir.shape<3>) -> !fir.ref> +// CHECK-NEXT: %[[V7:.*]] = fir.load %[[V5]]#0 : !fir.ref +// CHECK-NEXT: %[[V8:.*]] = fir.do_loop %arg3 = %c1 to %c2 step %c1 iter_args(%arg4 = %c0_i32) -> (i32) { +// CHECK-NEXT: %[[V10:.*]] = fir.do_loop %arg5 = %c1 to %c7 step %c1 iter_args(%arg6 = %arg4) -> (i32) { +// CHECK-NEXT: %[[V11:.*]] = fir.do_loop %arg7 = %c1 to %c4 step %c1 iter_args(%arg8 = %arg6) -> (i32) { +// CHECK-NEXT: %[[V12:.*]] = hlfir.designate %[[V6]] (%arg7, %arg5, %arg3) : (!fir.ref>, index, index, index) -> !fir.ref +// CHECK-NEXT: %[[V13:.*]] = fir.load %[[V12]] : !fir.ref +// CHECK-NEXT: %[[V14:.*]] = arith.cmpi sge, %[[V13]], %[[V7]] : i32 +// CHECK-NEXT: %[[V15:.*]] = arith.addi %arg8, %c1_i32 : i32 +// CHECK-NEXT: %[[V16:.*]] = arith.select %[[V14]], %[[V15]], %arg8 : i32 +// CHECK-NEXT: fir.result %[[V16]] : i32 +// CHECK-NEXT: } +// CHECK-NEXT: fir.result %[[V11]] : i32 +// CHECK-NEXT: } +// CHECK-NEXT: fir.result %[[V10]] : i32 +// CHECK-NEXT: } +// CHECK-NEXT: hlfir.assign %[[V8]] to %[[V4]]#0 : i32, !fir.ref +// CHECK-NEXT: %[[V9:.*]] = fir.load %[[V4]]#1 : !fir.ref +// CHECK-NEXT: return %[[V9]] : i32 + + + + + +func.func @_QFPtest_rec_sum(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca i32 {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4:2 = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %5:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = fir.load %2#0 : !fir.ref + %7 = fir.convert %6 : (i32) -> i64 + %8 = fir.shape %c7 : (index) -> !fir.shape<1> + %9 = hlfir.designate %1#0 (%7, %c1:%c7:%c1) shape %8 : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> + %10 = fir.load %5#0 : !fir.ref + %11 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7xi32> { + ^bb0(%arg3: index): + %15 = hlfir.designate %9 (%arg3) : (!fir.box>, index) -> !fir.ref + %16 = fir.load %15 : !fir.ref + hlfir.yield_element %16 : i32 + } + %12 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7x!fir.logical<4>> { + ^bb0(%arg3: index): + %15 = hlfir.sum %11 : (!hlfir.expr<7xi32>) -> i32 + %16 = arith.cmpi sge, %15, %10 : i32 + %17 = fir.convert %16 : (i1) -> !fir.logical<4> + hlfir.yield_element %17 : !fir.logical<4> + } + %13 = hlfir.count %12 : (!hlfir.expr<7x!fir.logical<4>>) -> i32 + hlfir.assign %13 to %4#0 : i32, !fir.ref + hlfir.destroy %12 : !hlfir.expr<7x!fir.logical<4>> + hlfir.destroy %11 : !hlfir.expr<7xi32> + %14 = fir.load %4#1 : !fir.ref + return %14 : i32 +} +// CHECK-LABEL: func.func @_QFPtest_rec_sum(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { +// CHECK: %[[V12:.*]] = fir.do_loop %arg3 = %c1 to %c7 step %c1 iter_args(%arg4 = %c0_i32) -> (i32) { +// CHECK: %[[V14:.*]] = hlfir.sum %[[V11]] : (!hlfir.expr<7xi32>) -> i32 +// CHECK: %[[V15:.*]] = arith.cmpi sge, %[[V14]], %[[V10]] : i32 +// CHECK: %[[V16:.*]] = arith.addi %arg4, %c1_i32 : i32 +// CHECK: %[[V17:.*]] = arith.select %[[V15]], %[[V16]], %arg4 : i32 +// CHECK: fir.result %[[V17]] : i32 +// CHECK: } + + + + +func.func @_QFPtest_rec_count(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca i32 {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4:2 = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %5:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = fir.load %2#0 : !fir.ref + %7 = fir.convert %6 : (i32) -> i64 + %8 = fir.shape %c7 : (index) -> !fir.shape<1> + %9 = hlfir.designate %1#0 (%7, %c1:%c7:%c1) shape %8 : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> + %10 = fir.load %5#0 : !fir.ref + %11 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7x!fir.logical<4>> { + ^bb0(%arg3: index): + %15 = hlfir.designate %9 (%arg3) : (!fir.box>, index) -> !fir.ref + %16 = fir.load %15 : !fir.ref + %17 = arith.cmpi sge, %16, %10 : i32 + %18 = fir.convert %17 : (i1) -> !fir.logical<4> + hlfir.yield_element %18 : !fir.logical<4> + } + %12 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7x!fir.logical<4>> { + ^bb0(%arg3: index): + %15 = hlfir.count %11 : (!hlfir.expr<7x!fir.logical<4>>) -> i32 + %16 = arith.cmpi sge, %15, %10 : i32 + %17 = fir.convert %16 : (i1) -> !fir.logical<4> + hlfir.yield_element %17 : !fir.logical<4> + } + %13 = hlfir.count %12 : (!hlfir.expr<7x!fir.logical<4>>) -> i32 + hlfir.assign %13 to %4#0 : i32, !fir.ref + hlfir.destroy %12 : !hlfir.expr<7x!fir.logical<4>> + hlfir.destroy %11 : !hlfir.expr<7x!fir.logical<4>> + %14 = fir.load %4#1 : !fir.ref + return %14 : i32 +} +// CHECK-LABEL: func.func @_QFPtest_rec_count(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> i32 { +// CHECK: %[[V11:.*]] = fir.do_loop %arg3 = %c1 to %c7 step %c1 iter_args(%arg4 = %c0_i32) -> (i32) { +// CHECK: %[[V13:.*]] = fir.do_loop %arg5 = %c1 to %c7 step %c1 iter_args(%arg6 = %c0_i32) -> (i32) { +// CHECK: %[[V17:.*]] = hlfir.designate %[[V9]] (%arg5) : (!fir.box>, index) -> !fir.ref +// CHECK: %[[V18:.*]] = fir.load %[[V17]] : !fir.ref +// CHECK: %[[V19:.*]] = arith.cmpi sge, %[[V18]], %[[V10]] : i32 +// CHECK: %[[V20:.*]] = arith.addi %arg6, %c1_i32 : i32 +// CHECK: %[[V21:.*]] = arith.select %[[V19]], %[[V20]], %arg6 : i32 +// CHECK: fir.result %[[V21]] : i32 +// CHECK: } +// CHECK: %[[V14:.*]] = arith.cmpi sge, %[[V13]], %[[V10]] : i32 +// CHECK: %[[V15:.*]] = arith.addi %arg4, %c1_i32 : i32 +// CHECK: %[[V16:.*]] = arith.select %[[V14]], %[[V15]], %arg4 : i32 +// CHECK: fir.result %[[V16]] : i32 +// CHECK: } -- GitLab From 8ca0364d33c7e6c4083e3b1c0b77b00b2c93ff46 Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Tue, 9 Jan 2024 09:41:14 -0800 Subject: [PATCH 231/652] [TextAPI] Skip adding empty attributes (#77400) An empty string attribute value (e.g. a parent-umbrella: "") is equivalent to omitting it. Theres no reason to write it out. --- llvm/lib/TextAPI/InterfaceFile.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/llvm/lib/TextAPI/InterfaceFile.cpp b/llvm/lib/TextAPI/InterfaceFile.cpp index 3689ab919191..d712ed386825 100644 --- a/llvm/lib/TextAPI/InterfaceFile.cpp +++ b/llvm/lib/TextAPI/InterfaceFile.cpp @@ -24,17 +24,23 @@ void InterfaceFileRef::addTarget(const Target &Target) { void InterfaceFile::addAllowableClient(StringRef InstallName, const Target &Target) { + if (InstallName.empty()) + return; auto Client = addEntry(AllowableClients, InstallName); Client->addTarget(Target); } void InterfaceFile::addReexportedLibrary(StringRef InstallName, const Target &Target) { + if (InstallName.empty()) + return; auto Lib = addEntry(ReexportedLibraries, InstallName); Lib->addTarget(Target); } void InterfaceFile::addParentUmbrella(const Target &Target_, StringRef Parent) { + if (Parent.empty()) + return; auto Iter = lower_bound(ParentUmbrellas, Target_, [](const std::pair &LHS, Target RHS) { return LHS.first < RHS; }); @@ -48,6 +54,8 @@ void InterfaceFile::addParentUmbrella(const Target &Target_, StringRef Parent) { } void InterfaceFile::addRPath(const Target &InputTarget, StringRef RPath) { + if (RPath.empty()) + return; using RPathEntryT = const std::pair; RPathEntryT Entry(InputTarget, RPath); auto Iter = -- GitLab From 90525125421300d9d1b6bf55288bd1871855d35d Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 9 Jan 2024 17:45:13 +0000 Subject: [PATCH 232/652] [Flang] Remove unnecessary static_assert Certain compilers do not seem to like the static assert with a string, causing a implicit conversion. It can be removed as it should not be reachable and the mlir::failure should handle it correctly in case it is. --- flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp index afdcda29e2fe..72aa86a93427 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp @@ -750,7 +750,6 @@ public: reduction); }; } else { - static_assert("Expected Op to be handled"); return mlir::failure(); } -- GitLab From 02fa434b92a5529f043b3fa353bc4fc5bd680424 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Tue, 9 Jan 2024 09:51:05 -0800 Subject: [PATCH 233/652] [mlir][openacc] Restore unit tests for device_type functions (#77122) These tests were initially pushed together with https://github.com/llvm/llvm-project/pull/75864 but they were triggering some buildbot failure (sanitizers). They now make use of the `OwningOpRef` so all the resources are correctly destroyed at the end of each tests. They will be extended to includes all the extra getter functions added with device_type support. --- mlir/unittests/Dialect/CMakeLists.txt | 1 + mlir/unittests/Dialect/OpenACC/CMakeLists.txt | 8 + .../Dialect/OpenACC/OpenACCOpsTest.cpp | 349 ++++++++++++++++++ 3 files changed, 358 insertions(+) create mode 100644 mlir/unittests/Dialect/OpenACC/CMakeLists.txt create mode 100644 mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp diff --git a/mlir/unittests/Dialect/CMakeLists.txt b/mlir/unittests/Dialect/CMakeLists.txt index 2dec4ba3c001..13393569f36f 100644 --- a/mlir/unittests/Dialect/CMakeLists.txt +++ b/mlir/unittests/Dialect/CMakeLists.txt @@ -10,6 +10,7 @@ add_subdirectory(ArmSME) add_subdirectory(Index) add_subdirectory(LLVMIR) add_subdirectory(MemRef) +add_subdirectory(OpenACC) add_subdirectory(SCF) add_subdirectory(SparseTensor) add_subdirectory(SPIRV) diff --git a/mlir/unittests/Dialect/OpenACC/CMakeLists.txt b/mlir/unittests/Dialect/OpenACC/CMakeLists.txt new file mode 100644 index 000000000000..5133d7fc3829 --- /dev/null +++ b/mlir/unittests/Dialect/OpenACC/CMakeLists.txt @@ -0,0 +1,8 @@ +add_mlir_unittest(MLIROpenACCTests + OpenACCOpsTest.cpp +) +target_link_libraries(MLIROpenACCTests + PRIVATE + MLIRIR + MLIROpenACCDialect +) diff --git a/mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp b/mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp new file mode 100644 index 000000000000..d78d7b0fdf67 --- /dev/null +++ b/mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp @@ -0,0 +1,349 @@ +//===- OpenACCOpsTest.cpp - OpenACC ops extra functiosn Tests -------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/OpenACC/OpenACC.h" +#include "mlir/IR/Diagnostics.h" +#include "mlir/IR/MLIRContext.h" +#include "mlir/IR/OwningOpRef.h" +#include "gtest/gtest.h" + +using namespace mlir; +using namespace mlir::acc; + +//===----------------------------------------------------------------------===// +// Test Fixture +//===----------------------------------------------------------------------===// + +class OpenACCOpsTest : public ::testing::Test { +protected: + OpenACCOpsTest() : b(&context), loc(UnknownLoc::get(&context)) { + context.loadDialect(); + } + + MLIRContext context; + OpBuilder b; + Location loc; + llvm::SmallVector dtypes = { + DeviceType::None, DeviceType::Star, DeviceType::Multicore, + DeviceType::Default, DeviceType::Host, DeviceType::Nvidia, + DeviceType::Radeon}; + llvm::SmallVector dtypesWithoutNone = { + DeviceType::Star, DeviceType::Multicore, DeviceType::Default, + DeviceType::Host, DeviceType::Nvidia, DeviceType::Radeon}; +}; + +template +void testAsyncOnly(OpBuilder &b, MLIRContext &context, Location loc, + llvm::SmallVector &dtypes) { + OwningOpRef op = b.create(loc, TypeRange{}, ValueRange{}); + EXPECT_FALSE(op->hasAsyncOnly()); + for (auto d : dtypes) + EXPECT_FALSE(op->hasAsyncOnly(d)); + + auto dtypeNone = DeviceTypeAttr::get(&context, DeviceType::None); + op->setAsyncOnlyAttr(b.getArrayAttr({dtypeNone})); + EXPECT_TRUE(op->hasAsyncOnly()); + EXPECT_TRUE(op->hasAsyncOnly(DeviceType::None)); + op->removeAsyncOnlyAttr(); + + auto dtypeHost = DeviceTypeAttr::get(&context, DeviceType::Host); + op->setAsyncOnlyAttr(b.getArrayAttr({dtypeHost})); + EXPECT_TRUE(op->hasAsyncOnly(DeviceType::Host)); + EXPECT_FALSE(op->hasAsyncOnly()); + op->removeAsyncOnlyAttr(); + + auto dtypeStar = DeviceTypeAttr::get(&context, DeviceType::Star); + op->setAsyncOnlyAttr(b.getArrayAttr({dtypeHost, dtypeStar})); + EXPECT_TRUE(op->hasAsyncOnly(DeviceType::Star)); + EXPECT_TRUE(op->hasAsyncOnly(DeviceType::Host)); + EXPECT_FALSE(op->hasAsyncOnly()); + + op->removeAsyncOnlyAttr(); +} + +TEST_F(OpenACCOpsTest, asyncOnlyTest) { + testAsyncOnly(b, context, loc, dtypes); + testAsyncOnly(b, context, loc, dtypes); + testAsyncOnly(b, context, loc, dtypes); +} + +template +void testAsyncValue(OpBuilder &b, MLIRContext &context, Location loc, + llvm::SmallVector &dtypes) { + OwningOpRef op = b.create(loc, TypeRange{}, ValueRange{}); + + mlir::Value empty; + EXPECT_EQ(op->getAsyncValue(), empty); + for (auto d : dtypes) + EXPECT_EQ(op->getAsyncValue(d), empty); + + OwningOpRef val = + b.create(loc, 1); + auto dtypeNvidia = DeviceTypeAttr::get(&context, DeviceType::Nvidia); + op->setAsyncDeviceTypeAttr(b.getArrayAttr({dtypeNvidia})); + op->getAsyncMutable().assign(val->getResult()); + EXPECT_EQ(op->getAsyncValue(), empty); + EXPECT_EQ(op->getAsyncValue(DeviceType::Nvidia), val->getResult()); + + op->getAsyncMutable().clear(); + op->removeAsyncDeviceTypeAttr(); +} + +TEST_F(OpenACCOpsTest, asyncValueTest) { + testAsyncValue(b, context, loc, dtypes); + testAsyncValue(b, context, loc, dtypes); + testAsyncValue(b, context, loc, dtypes); +} + +template +void testNumGangsValues(OpBuilder &b, MLIRContext &context, Location loc, + llvm::SmallVector &dtypes, + llvm::SmallVector &dtypesWithoutNone) { + OwningOpRef op = b.create(loc, TypeRange{}, ValueRange{}); + EXPECT_EQ(op->getNumGangsValues().begin(), op->getNumGangsValues().end()); + + OwningOpRef val1 = + b.create(loc, 1); + OwningOpRef val2 = + b.create(loc, 4); + auto dtypeNone = DeviceTypeAttr::get(&context, DeviceType::None); + op->getNumGangsMutable().assign(val1->getResult()); + op->setNumGangsDeviceTypeAttr(b.getArrayAttr({dtypeNone})); + op->setNumGangsSegments(b.getDenseI32ArrayAttr({1})); + EXPECT_EQ(op->getNumGangsValues().front(), val1->getResult()); + for (auto d : dtypesWithoutNone) + EXPECT_EQ(op->getNumGangsValues(d).begin(), op->getNumGangsValues(d).end()); + + op->getNumGangsMutable().clear(); + op->removeNumGangsDeviceTypeAttr(); + op->removeNumGangsSegmentsAttr(); + for (auto d : dtypes) + EXPECT_EQ(op->getNumGangsValues(d).begin(), op->getNumGangsValues(d).end()); + + op->getNumGangsMutable().append(val1->getResult()); + op->getNumGangsMutable().append(val2->getResult()); + op->setNumGangsDeviceTypeAttr( + b.getArrayAttr({DeviceTypeAttr::get(&context, DeviceType::Host), + DeviceTypeAttr::get(&context, DeviceType::Star)})); + op->setNumGangsSegments(b.getDenseI32ArrayAttr({1, 1})); + EXPECT_EQ(op->getNumGangsValues(DeviceType::None).begin(), + op->getNumGangsValues(DeviceType::None).end()); + EXPECT_EQ(op->getNumGangsValues(DeviceType::Host).front(), val1->getResult()); + EXPECT_EQ(op->getNumGangsValues(DeviceType::Star).front(), val2->getResult()); + + op->getNumGangsMutable().clear(); + op->removeNumGangsDeviceTypeAttr(); + op->removeNumGangsSegmentsAttr(); + for (auto d : dtypes) + EXPECT_EQ(op->getNumGangsValues(d).begin(), op->getNumGangsValues(d).end()); + + op->getNumGangsMutable().append(val1->getResult()); + op->getNumGangsMutable().append(val2->getResult()); + op->getNumGangsMutable().append(val1->getResult()); + op->setNumGangsDeviceTypeAttr( + b.getArrayAttr({DeviceTypeAttr::get(&context, DeviceType::Default), + DeviceTypeAttr::get(&context, DeviceType::Multicore)})); + op->setNumGangsSegments(b.getDenseI32ArrayAttr({2, 1})); + EXPECT_EQ(op->getNumGangsValues(DeviceType::None).begin(), + op->getNumGangsValues(DeviceType::None).end()); + EXPECT_EQ(op->getNumGangsValues(DeviceType::Default).front(), + val1->getResult()); + EXPECT_EQ(op->getNumGangsValues(DeviceType::Default).drop_front().front(), + val2->getResult()); + EXPECT_EQ(op->getNumGangsValues(DeviceType::Multicore).front(), + val1->getResult()); + + op->getNumGangsMutable().clear(); + op->removeNumGangsDeviceTypeAttr(); + op->removeNumGangsSegmentsAttr(); +} + +TEST_F(OpenACCOpsTest, numGangsValuesTest) { + testNumGangsValues(b, context, loc, dtypes, dtypesWithoutNone); + testNumGangsValues(b, context, loc, dtypes, dtypesWithoutNone); +} + +template +void testVectorLength(OpBuilder &b, MLIRContext &context, Location loc, + llvm::SmallVector &dtypes) { + OwningOpRef op = b.create(loc, TypeRange{}, ValueRange{}); + + mlir::Value empty; + EXPECT_EQ(op->getVectorLengthValue(), empty); + for (auto d : dtypes) + EXPECT_EQ(op->getVectorLengthValue(d), empty); + + OwningOpRef val = + b.create(loc, 1); + auto dtypeNvidia = DeviceTypeAttr::get(&context, DeviceType::Nvidia); + op->setVectorLengthDeviceTypeAttr(b.getArrayAttr({dtypeNvidia})); + op->getVectorLengthMutable().assign(val->getResult()); + EXPECT_EQ(op->getVectorLengthValue(), empty); + EXPECT_EQ(op->getVectorLengthValue(DeviceType::Nvidia), val->getResult()); + + op->getVectorLengthMutable().clear(); + op->removeVectorLengthDeviceTypeAttr(); +} + +TEST_F(OpenACCOpsTest, vectorLengthTest) { + testVectorLength(b, context, loc, dtypes); + testVectorLength(b, context, loc, dtypes); +} + +template +void testWaitOnly(OpBuilder &b, MLIRContext &context, Location loc, + llvm::SmallVector &dtypes, + llvm::SmallVector &dtypesWithoutNone) { + OwningOpRef op = b.create(loc, TypeRange{}, ValueRange{}); + EXPECT_FALSE(op->hasWaitOnly()); + for (auto d : dtypes) + EXPECT_FALSE(op->hasWaitOnly(d)); + + auto dtypeNone = DeviceTypeAttr::get(&context, DeviceType::None); + op->setWaitOnlyAttr(b.getArrayAttr({dtypeNone})); + EXPECT_TRUE(op->hasWaitOnly()); + EXPECT_TRUE(op->hasWaitOnly(DeviceType::None)); + for (auto d : dtypesWithoutNone) + EXPECT_FALSE(op->hasWaitOnly(d)); + op->removeWaitOnlyAttr(); + + auto dtypeHost = DeviceTypeAttr::get(&context, DeviceType::Host); + op->setWaitOnlyAttr(b.getArrayAttr({dtypeHost})); + EXPECT_TRUE(op->hasWaitOnly(DeviceType::Host)); + EXPECT_FALSE(op->hasWaitOnly()); + op->removeWaitOnlyAttr(); + + auto dtypeStar = DeviceTypeAttr::get(&context, DeviceType::Star); + op->setWaitOnlyAttr(b.getArrayAttr({dtypeHost, dtypeStar})); + EXPECT_TRUE(op->hasWaitOnly(DeviceType::Star)); + EXPECT_TRUE(op->hasWaitOnly(DeviceType::Host)); + EXPECT_FALSE(op->hasWaitOnly()); + + op->removeWaitOnlyAttr(); +} + +TEST_F(OpenACCOpsTest, waitOnlyTest) { + testWaitOnly(b, context, loc, dtypes, dtypesWithoutNone); + testWaitOnly(b, context, loc, dtypes, dtypesWithoutNone); + testWaitOnly(b, context, loc, dtypes, dtypesWithoutNone); +} + +template +void testWaitValues(OpBuilder &b, MLIRContext &context, Location loc, + llvm::SmallVector &dtypes, + llvm::SmallVector &dtypesWithoutNone) { + OwningOpRef op = b.create(loc, TypeRange{}, ValueRange{}); + EXPECT_EQ(op->getWaitValues().begin(), op->getWaitValues().end()); + + OwningOpRef val1 = + b.create(loc, 1); + OwningOpRef val2 = + b.create(loc, 4); + auto dtypeNone = DeviceTypeAttr::get(&context, DeviceType::None); + op->getWaitOperandsMutable().assign(val1->getResult()); + op->setWaitOperandsDeviceTypeAttr(b.getArrayAttr({dtypeNone})); + op->setWaitOperandsSegments(b.getDenseI32ArrayAttr({1})); + EXPECT_EQ(op->getWaitValues().front(), val1->getResult()); + for (auto d : dtypesWithoutNone) + EXPECT_EQ(op->getWaitValues(d).begin(), op->getWaitValues(d).end()); + + op->getWaitOperandsMutable().clear(); + op->removeWaitOperandsDeviceTypeAttr(); + op->removeWaitOperandsSegmentsAttr(); + for (auto d : dtypes) + EXPECT_EQ(op->getWaitValues(d).begin(), op->getWaitValues(d).end()); + + op->getWaitOperandsMutable().append(val1->getResult()); + op->getWaitOperandsMutable().append(val2->getResult()); + op->setWaitOperandsDeviceTypeAttr( + b.getArrayAttr({DeviceTypeAttr::get(&context, DeviceType::Host), + DeviceTypeAttr::get(&context, DeviceType::Star)})); + op->setWaitOperandsSegments(b.getDenseI32ArrayAttr({1, 1})); + EXPECT_EQ(op->getWaitValues(DeviceType::None).begin(), + op->getWaitValues(DeviceType::None).end()); + EXPECT_EQ(op->getWaitValues(DeviceType::Host).front(), val1->getResult()); + EXPECT_EQ(op->getWaitValues(DeviceType::Star).front(), val2->getResult()); + + op->getWaitOperandsMutable().clear(); + op->removeWaitOperandsDeviceTypeAttr(); + op->removeWaitOperandsSegmentsAttr(); + for (auto d : dtypes) + EXPECT_EQ(op->getWaitValues(d).begin(), op->getWaitValues(d).end()); + + op->getWaitOperandsMutable().append(val1->getResult()); + op->getWaitOperandsMutable().append(val2->getResult()); + op->getWaitOperandsMutable().append(val1->getResult()); + op->setWaitOperandsDeviceTypeAttr( + b.getArrayAttr({DeviceTypeAttr::get(&context, DeviceType::Default), + DeviceTypeAttr::get(&context, DeviceType::Multicore)})); + op->setWaitOperandsSegments(b.getDenseI32ArrayAttr({2, 1})); + EXPECT_EQ(op->getWaitValues(DeviceType::None).begin(), + op->getWaitValues(DeviceType::None).end()); + EXPECT_EQ(op->getWaitValues(DeviceType::Default).front(), val1->getResult()); + EXPECT_EQ(op->getWaitValues(DeviceType::Default).drop_front().front(), + val2->getResult()); + EXPECT_EQ(op->getWaitValues(DeviceType::Multicore).front(), + val1->getResult()); + + op->getWaitOperandsMutable().clear(); + op->removeWaitOperandsDeviceTypeAttr(); + op->removeWaitOperandsSegmentsAttr(); +} + +TEST_F(OpenACCOpsTest, waitValuesTest) { + testWaitValues(b, context, loc, dtypes, dtypesWithoutNone); + testWaitValues(b, context, loc, dtypes, dtypesWithoutNone); + testWaitValues(b, context, loc, dtypes, dtypesWithoutNone); +} + +TEST_F(OpenACCOpsTest, loopOpGangVectorWorkerTest) { + OwningOpRef op = b.create(loc, TypeRange{}, ValueRange{}); + EXPECT_FALSE(op->hasGang()); + EXPECT_FALSE(op->hasVector()); + EXPECT_FALSE(op->hasWorker()); + for (auto d : dtypes) { + EXPECT_FALSE(op->hasGang(d)); + EXPECT_FALSE(op->hasVector(d)); + EXPECT_FALSE(op->hasWorker(d)); + } + + auto dtypeNone = DeviceTypeAttr::get(&context, DeviceType::None); + op->setGangAttr(b.getArrayAttr({dtypeNone})); + EXPECT_TRUE(op->hasGang()); + EXPECT_TRUE(op->hasGang(DeviceType::None)); + for (auto d : dtypesWithoutNone) + EXPECT_FALSE(op->hasGang(d)); + for (auto d : dtypes) { + EXPECT_FALSE(op->hasVector(d)); + EXPECT_FALSE(op->hasWorker(d)); + } + op->removeGangAttr(); + + op->setWorkerAttr(b.getArrayAttr({dtypeNone})); + EXPECT_TRUE(op->hasWorker()); + EXPECT_TRUE(op->hasWorker(DeviceType::None)); + for (auto d : dtypesWithoutNone) + EXPECT_FALSE(op->hasWorker(d)); + for (auto d : dtypes) { + EXPECT_FALSE(op->hasGang(d)); + EXPECT_FALSE(op->hasVector(d)); + } + op->removeWorkerAttr(); + + op->setVectorAttr(b.getArrayAttr({dtypeNone})); + EXPECT_TRUE(op->hasVector()); + EXPECT_TRUE(op->hasVector(DeviceType::None)); + for (auto d : dtypesWithoutNone) + EXPECT_FALSE(op->hasVector(d)); + for (auto d : dtypes) { + EXPECT_FALSE(op->hasGang(d)); + EXPECT_FALSE(op->hasWorker(d)); + } + op->removeVectorAttr(); +} -- GitLab From ed640420b50e960b7700e2fa973b9fdcdcb32838 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Tue, 9 Jan 2024 09:51:41 -0800 Subject: [PATCH 234/652] [flang][openacc] Fix clauses check with device_type (#77389) A couple of clauses are allowed multiple times when they are separated by a device_type clause. This patch updates the ACC.td file to move these clauses to the `allowedClause` list and the `CheckAllowedOncePerGroup` function is used to make sure they appear only once on the directive or for each device_type. --- flang/lib/Semantics/check-acc-structure.cpp | 28 +++++++-- flang/test/Semantics/OpenACC/acc-loop.f90 | 40 ++++++++++++- llvm/include/llvm/Frontend/OpenACC/ACC.td | 66 ++++++++++----------- 3 files changed, 94 insertions(+), 40 deletions(-) diff --git a/flang/lib/Semantics/check-acc-structure.cpp b/flang/lib/Semantics/check-acc-structure.cpp index 932d5776a046..4a5798a8a531 100644 --- a/flang/lib/Semantics/check-acc-structure.cpp +++ b/flang/lib/Semantics/check-acc-structure.cpp @@ -225,7 +225,8 @@ void AccStructureChecker::Leave(const parser::OpenACCCombinedConstruct &x) { case llvm::acc::Directive::ACCD_serial_loop: // Restriction - line 1004-1005 CheckOnlyAllowedAfter(llvm::acc::Clause::ACCC_device_type, - computeConstructOnlyAllowedAfterDeviceTypeClauses); + computeConstructOnlyAllowedAfterDeviceTypeClauses | + loopOnlyAllowedAfterDeviceTypeClauses); if (doCons) { const parser::Block &block{std::get(doCons->t)}; CheckNoBranching(block, GetContext().directive, beginBlockDir.source); @@ -388,11 +389,8 @@ CHECK_SIMPLE_CLAUSE(Nohost, ACCC_nohost) CHECK_SIMPLE_CLAUSE(Private, ACCC_private) CHECK_SIMPLE_CLAUSE(Read, ACCC_read) CHECK_SIMPLE_CLAUSE(Seq, ACCC_seq) -CHECK_SIMPLE_CLAUSE(Tile, ACCC_tile) CHECK_SIMPLE_CLAUSE(UseDevice, ACCC_use_device) -CHECK_SIMPLE_CLAUSE(Vector, ACCC_vector) CHECK_SIMPLE_CLAUSE(Wait, ACCC_wait) -CHECK_SIMPLE_CLAUSE(Worker, ACCC_worker) CHECK_SIMPLE_CLAUSE(Write, ACCC_write) CHECK_SIMPLE_CLAUSE(Unknown, ACCC_unknown) @@ -536,8 +534,28 @@ void AccStructureChecker::Enter(const parser::AccClause::DeviceType &d) { } } +void AccStructureChecker::Enter(const parser::AccClause::Vector &g) { + CheckAllowed(llvm::acc::Clause::ACCC_vector); + CheckAllowedOncePerGroup( + llvm::acc::Clause::ACCC_vector, llvm::acc::Clause::ACCC_device_type); +} + +void AccStructureChecker::Enter(const parser::AccClause::Worker &g) { + CheckAllowed(llvm::acc::Clause::ACCC_worker); + CheckAllowedOncePerGroup( + llvm::acc::Clause::ACCC_worker, llvm::acc::Clause::ACCC_device_type); +} + +void AccStructureChecker::Enter(const parser::AccClause::Tile &g) { + CheckAllowed(llvm::acc::Clause::ACCC_tile); + CheckAllowedOncePerGroup( + llvm::acc::Clause::ACCC_tile, llvm::acc::Clause::ACCC_device_type); +} + void AccStructureChecker::Enter(const parser::AccClause::Gang &g) { CheckAllowed(llvm::acc::Clause::ACCC_gang); + CheckAllowedOncePerGroup( + llvm::acc::Clause::ACCC_gang, llvm::acc::Clause::ACCC_device_type); if (g.v) { bool hasNum = false; @@ -665,6 +683,8 @@ void AccStructureChecker::Enter(const parser::AccClause::Self &x) { void AccStructureChecker::Enter(const parser::AccClause::Collapse &x) { CheckAllowed(llvm::acc::Clause::ACCC_collapse); + CheckAllowedOncePerGroup( + llvm::acc::Clause::ACCC_collapse, llvm::acc::Clause::ACCC_device_type); const parser::AccCollapseArg &accCollapseArg = x.v; const auto &collapseValue{ std::get(accCollapseArg.t)}; diff --git a/flang/test/Semantics/OpenACC/acc-loop.f90 b/flang/test/Semantics/OpenACC/acc-loop.f90 index f5d1e501a2b3..fde836852c51 100644 --- a/flang/test/Semantics/OpenACC/acc-loop.f90 +++ b/flang/test/Semantics/OpenACC/acc-loop.f90 @@ -63,7 +63,7 @@ program openacc_loop_validity !$acc end parallel !$acc parallel - !ERROR: At most one VECTOR clause can appear on the LOOP directive + !ERROR: At most one VECTOR clause can appear on the LOOP directive or in group separated by the DEVICE_TYPE clause !$acc loop vector vector(128) do i = 1, N a(i) = 3.14 @@ -99,7 +99,7 @@ program openacc_loop_validity !$acc end parallel !$acc parallel - !ERROR: At most one WORKER clause can appear on the LOOP directive + !ERROR: At most one WORKER clause can appear on the LOOP directive or in group separated by the DEVICE_TYPE clause !$acc loop worker worker(10) do i = 1, N a(i) = 3.14 @@ -135,13 +135,29 @@ program openacc_loop_validity !$acc end parallel !$acc parallel - !ERROR: At most one GANG clause can appear on the LOOP directive + !ERROR: At most one GANG clause can appear on the LOOP directive or in group separated by the DEVICE_TYPE clause !$acc loop gang gang(gang_size) do i = 1, N a(i) = 3.14 end do !$acc end parallel + !$acc loop gang device_type(default) gang(gang_size) + do i = 1, N + a(i) = 3.14 + end do + + !ERROR: At most one GANG clause can appear on the PARALLEL LOOP directive or in group separated by the DEVICE_TYPE clause + !$acc parallel loop gang gang(gang_size) + do i = 1, N + a(i) = 3.14 + end do + + !$acc parallel loop gang device_type(default) gang(gang_size) + do i = 1, N + a(i) = 3.14 + end do + !$acc parallel !$acc loop gang(gang_size) do i = 1, N @@ -283,4 +299,22 @@ program openacc_loop_validity end do !$acc end parallel + !$acc loop gang device_type(nvidia) gang(num: 8) + DO i = 1, n + END DO + + !$acc loop vector device_type(default) vector(16) + DO i = 1, n + END DO + + !$acc loop worker device_type(*) worker(8) + DO i = 1, n + END DO + + !$acc loop device_type(multicore) collapse(2) + DO i = 1, n + DO j = 1, n + END DO + END DO + end program openacc_loop_validity diff --git a/llvm/include/llvm/Frontend/OpenACC/ACC.td b/llvm/include/llvm/Frontend/OpenACC/ACC.td index 013d18e160de..0dbd934d83f0 100644 --- a/llvm/include/llvm/Frontend/OpenACC/ACC.td +++ b/llvm/include/llvm/Frontend/OpenACC/ACC.td @@ -391,9 +391,7 @@ def ACC_Loop : Directive<"loop"> { let allowedClauses = [ VersionedClause, VersionedClause, - VersionedClause - ]; - let allowedOnceClauses = [ + VersionedClause, VersionedClause, VersionedClause, VersionedClause, @@ -421,15 +419,17 @@ def ACC_Init : Directive<"init"> { // 2.15.1 def ACC_Routine : Directive<"routine"> { - let allowedOnceClauses = [ + let allowedClauses = [ VersionedClause, VersionedClause, - VersionedClause, VersionedClause, VersionedClause, VersionedClause, VersionedClause ]; + let allowedOnceClauses = [ + VersionedClause + ]; } // 2.14.3 @@ -532,32 +532,32 @@ def ACC_HostData : Directive<"host_data"> { // 2.11 def ACC_KernelsLoop : Directive<"kernels loop"> { let allowedClauses = [ + VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, VersionedClause, + VersionedClause, VersionedClause, + VersionedClause, VersionedClause, + VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause + VersionedClause, + VersionedClause, + VersionedClause, + VersionedClause, + VersionedClause ]; let allowedOnceClauses = [ VersionedClause, - VersionedClause, VersionedClause, - VersionedClause, VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause + VersionedClause ]; let allowedExclusiveClauses = [ VersionedClause, @@ -570,6 +570,7 @@ def ACC_KernelsLoop : Directive<"kernels loop"> { def ACC_ParallelLoop : Directive<"parallel loop"> { let allowedClauses = [ VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, @@ -577,25 +578,24 @@ def ACC_ParallelLoop : Directive<"parallel loop"> { VersionedClause, VersionedClause, VersionedClause, + VersionedClause, VersionedClause, + VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, VersionedClause, - VersionedClause + VersionedClause, + VersionedClause, + VersionedClause, + VersionedClause ]; let allowedOnceClauses = [ VersionedClause, - VersionedClause, VersionedClause, - VersionedClause, VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause + VersionedClause ]; let allowedExclusiveClauses = [ VersionedClause, @@ -608,6 +608,7 @@ def ACC_ParallelLoop : Directive<"parallel loop"> { def ACC_SerialLoop : Directive<"serial loop"> { let allowedClauses = [ VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, @@ -615,22 +616,21 @@ def ACC_SerialLoop : Directive<"serial loop"> { VersionedClause, VersionedClause, VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, VersionedClause, - VersionedClause + VersionedClause, + VersionedClause, + VersionedClause, + VersionedClause ]; let allowedOnceClauses = [ VersionedClause, - VersionedClause, VersionedClause, - VersionedClause, VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause + VersionedClause ]; let allowedExclusiveClauses = [ VersionedClause, -- GitLab From 064e73cd54061d39d42ae682d2f0780296a6ca5d Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 9 Jan 2024 18:59:16 +0100 Subject: [PATCH 235/652] Revert "[GVNSink] Skip debug intrinsics when identifying sinking candidates (#77419)" This reverts commit 51bf0dff53fdaca25f30d30a1c99462c7afdce74. There are test failures on Windows. --- llvm/lib/Transforms/Scalar/GVNSink.cpp | 6 +- .../GVNSink/sink-ignore-dbg-intrinsics.ll | 86 ------------------- 2 files changed, 3 insertions(+), 89 deletions(-) delete mode 100644 llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll diff --git a/llvm/lib/Transforms/Scalar/GVNSink.cpp b/llvm/lib/Transforms/Scalar/GVNSink.cpp index 9db66b3793b8..2b38831139a5 100644 --- a/llvm/lib/Transforms/Scalar/GVNSink.cpp +++ b/llvm/lib/Transforms/Scalar/GVNSink.cpp @@ -132,7 +132,7 @@ public: ActiveBlocks.remove(BB); continue; } - Insts.push_back(BB->getTerminator()->getPrevNonDebugInstruction()); + Insts.push_back(BB->getTerminator()->getPrevNode()); } if (Insts.empty()) Fail = true; @@ -168,7 +168,7 @@ public: if (Inst == &Inst->getParent()->front()) ActiveBlocks.remove(Inst->getParent()); else - NewInsts.push_back(Inst->getPrevNonDebugInstruction()); + NewInsts.push_back(Inst->getPrevNode()); } if (NewInsts.empty()) { Fail = true; @@ -834,7 +834,7 @@ void GVNSink::sinkLastInstruction(ArrayRef Blocks, BasicBlock *BBEnd) { SmallVector Insts; for (BasicBlock *BB : Blocks) - Insts.push_back(BB->getTerminator()->getPrevNonDebugInstruction()); + Insts.push_back(BB->getTerminator()->getPrevNode()); Instruction *I0 = Insts.front(); SmallVector NewOperands; diff --git a/llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll b/llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll deleted file mode 100644 index f51cadc1bb85..000000000000 --- a/llvm/test/Transforms/GVNSink/sink-ignore-dbg-intrinsics.ll +++ /dev/null @@ -1,86 +0,0 @@ -; RUN: opt < %s -passes=gvn-sink -S | FileCheck %s - -; Function Attrs: noinline nounwind uwtable -define dso_local i32 @fun(i32 noundef %a, i32 noundef %b) #0 !dbg !10 { -entry: - tail call void @llvm.dbg.value(metadata i32 %a, metadata !15, metadata !DIExpression()), !dbg !16 - tail call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression()), !dbg !16 - %cmp = icmp sgt i32 %b, 10, !dbg !18 - br i1 %cmp, label %if.then, label %if.else, !dbg !20 - -if.then: ; preds = %entry - %add = add nsw i32 %a, 1, !dbg !21 - tail call void @llvm.dbg.value(metadata i32 %add, metadata !23, metadata !DIExpression()), !dbg !24 - %xor = xor i32 %add, 1, !dbg !25 - tail call void @llvm.dbg.value(metadata i32 %xor, metadata !26, metadata !DIExpression()), !dbg !24 - tail call void @llvm.dbg.value(metadata i32 %xor, metadata !27, metadata !DIExpression()), !dbg !16 - br label %if.end, !dbg !28 - -if.else: ; preds = %entry - %add1 = add nsw i32 %b, 1, !dbg !29 - tail call void @llvm.dbg.value(metadata i32 %add1, metadata !31, metadata !DIExpression()), !dbg !32 - %xor2 = xor i32 %add1, 1, !dbg !33 - tail call void @llvm.dbg.value(metadata i32 %xor2, metadata !34, metadata !DIExpression()), !dbg !32 - tail call void @llvm.dbg.value(metadata i32 %xor2, metadata !27, metadata !DIExpression()), !dbg !16 - br label %if.end - -; CHECK-LABEL: if.end: -; CHECK: %a.sink = phi i32 [ %a, %if.then ], [ %b, %if.else ] -; CHECK: %add = add nsw i32 %a.sink, 1 -; CHECK: %xor = xor i32 %add, 1 -if.end: ; preds = %if.else, %if.then - %ret.0 = phi i32 [ %xor, %if.then ], [ %xor2, %if.else ], !dbg !35 - tail call void @llvm.dbg.value(metadata i32 %ret.0, metadata !27, metadata !DIExpression()), !dbg !16 - ret i32 %ret.0, !dbg !36 -} - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.value(metadata, metadata, metadata) #1 - -attributes #0 = { noinline nounwind uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} -!llvm.ident = !{!9} - -!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 18.0.0git (https://github.com/llvm/llvm-project.git 5dfcb3e5d1d16bb4f8fce52b3c089119ed977e7f)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "main.c", directory: "/home/hs/llvm-test", checksumkind: CSK_MD5, checksum: "68c28c3d0877bed08ff43db70c573802") -!2 = !{i32 7, !"Dwarf Version", i32 5} -!3 = !{i32 2, !"Debug Info Version", i32 3} -!4 = !{i32 1, !"wchar_size", i32 4} -!5 = !{i32 8, !"PIC Level", i32 2} -!6 = !{i32 7, !"PIE Level", i32 2} -!7 = !{i32 7, !"uwtable", i32 2} -!8 = !{i32 7, !"frame-pointer", i32 2} -!9 = !{!"clang version 18.0.0git (https://github.com/llvm/llvm-project.git 5dfcb3e5d1d16bb4f8fce52b3c089119ed977e7f)"} -!10 = distinct !DISubprogram(name: "fun", scope: !1, file: !1, line: 1, type: !11, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) -!11 = !DISubroutineType(types: !12) -!12 = !{!13, !13, !13} -!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!14 = !{} -!15 = !DILocalVariable(name: "a", arg: 1, scope: !10, file: !1, line: 1, type: !13) -!16 = !DILocation(line: 0, scope: !10) -!17 = !DILocalVariable(name: "b", arg: 2, scope: !10, file: !1, line: 1, type: !13) -!18 = !DILocation(line: 3, column: 11, scope: !19) -!19 = distinct !DILexicalBlock(scope: !10, file: !1, line: 3, column: 9) -!20 = !DILocation(line: 3, column: 9, scope: !10) -!21 = !DILocation(line: 4, column: 20, scope: !22) -!22 = distinct !DILexicalBlock(scope: !19, file: !1, line: 3, column: 17) -!23 = !DILocalVariable(name: "a1", scope: !22, file: !1, line: 4, type: !13) -!24 = !DILocation(line: 0, scope: !22) -!25 = !DILocation(line: 5, column: 21, scope: !22) -!26 = !DILocalVariable(name: "a2", scope: !22, file: !1, line: 5, type: !13) -!27 = !DILocalVariable(name: "ret", scope: !10, file: !1, line: 2, type: !13) -!28 = !DILocation(line: 7, column: 5, scope: !22) -!29 = !DILocation(line: 8, column: 20, scope: !30) -!30 = distinct !DILexicalBlock(scope: !19, file: !1, line: 7, column: 12) -!31 = !DILocalVariable(name: "b1", scope: !30, file: !1, line: 8, type: !13) -!32 = !DILocation(line: 0, scope: !30) -!33 = !DILocation(line: 9, column: 21, scope: !30) -!34 = !DILocalVariable(name: "b2", scope: !30, file: !1, line: 9, type: !13) -!35 = !DILocation(line: 0, scope: !19) -!36 = !DILocation(line: 12, column: 5, scope: !10) \ No newline at end of file -- GitLab From d29297239f4ebfd2948915fe084e1d2e36f558f9 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Tue, 9 Jan 2024 19:11:40 +0100 Subject: [PATCH 236/652] [libc++] Implements P2517R1. (#77239) As pointed out by @Zingam the paper was implemented in libc++ as an extension. This patch does the bookkeeping. The inital release version is based on historical release dates. Completes: - Add a conditional noexcept specification to std::apply --- libcxx/docs/ReleaseNotes/18.rst | 1 + libcxx/docs/Status/Cxx23Papers.csv | 2 +- libcxx/include/tuple | 2 +- .../tuple/tuple.tuple/tuple.apply/apply.pass.cpp | 10 +++++++++- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/libcxx/docs/ReleaseNotes/18.rst b/libcxx/docs/ReleaseNotes/18.rst index d20c19f3a29f..5df6242e5231 100644 --- a/libcxx/docs/ReleaseNotes/18.rst +++ b/libcxx/docs/ReleaseNotes/18.rst @@ -59,6 +59,7 @@ Implemented Papers - P2821R5 - span.at() - P0521R0 - Proposed Resolution for CA 14 (shared_ptr use_count/unique) - P1759R6 - Native handles and file streams +- P2517R1 - Add a conditional ``noexcept`` specification to ``std::apply`` Improvements and New Features diff --git a/libcxx/docs/Status/Cxx23Papers.csv b/libcxx/docs/Status/Cxx23Papers.csv index 03c12247cd85..ebab3ef735b6 100644 --- a/libcxx/docs/Status/Cxx23Papers.csv +++ b/libcxx/docs/Status/Cxx23Papers.csv @@ -83,7 +83,7 @@ "`P2502R2 `__","LWG","``std::generator``: Synchronous Coroutine Generator for Ranges","July 2022","","","|ranges|" "`P2508R1 `__","LWG","Exposing ``std::basic-format-string``","July 2022","|Complete|","15.0" "`P2513R4 `__","LWG","``char8_t`` Compatibility and Portability Fixes","July 2022","","" -"`P2517R1 `__","LWG","Add a conditional ``noexcept`` specification to ``std::apply``","July 2022","","" +"`P2517R1 `__","LWG","Add a conditional ``noexcept`` specification to ``std::apply``","July 2022","|Complete|","3.9" "`P2520R0 `__","LWG","``move_iterator`` should be a random access iterator","July 2022","|Complete| [#note-P2520R0]_","17.0","|ranges|" "`P2540R1 `__","LWG","Empty Product for certain Views","July 2022","","","|ranges|" "`P2549R1 `__","LWG","``std::unexpected`` should have ``error()`` as member accessor","July 2022","|Complete|","16.0" diff --git a/libcxx/include/tuple b/libcxx/include/tuple index aa22c320b1ec..0e5f0b4831b4 100644 --- a/libcxx/include/tuple +++ b/libcxx/include/tuple @@ -141,7 +141,7 @@ template tuple tuple_cat(Tuples&&... tpls); // cons // [tuple.apply], calling a function with a tuple of arguments: template - constexpr decltype(auto) apply(F&& f, Tuple&& t); // C++17 + constexpr decltype(auto) apply(F&& f, Tuple&& t) noexcept(see below); // C++17 noexcept since C++23 template constexpr T make_from_tuple(Tuple&& t); // C++17 diff --git a/libcxx/test/std/utilities/tuple/tuple.tuple/tuple.apply/apply.pass.cpp b/libcxx/test/std/utilities/tuple/tuple.tuple/tuple.apply/apply.pass.cpp index 6ca3f2045e49..af3752752207 100644 --- a/libcxx/test/std/utilities/tuple/tuple.tuple/tuple.apply/apply.pass.cpp +++ b/libcxx/test/std/utilities/tuple/tuple.tuple/tuple.apply/apply.pass.cpp @@ -10,7 +10,7 @@ // -// template constexpr decltype(auto) apply(F &&, T &&) +// template constexpr decltype(auto) apply(F &&, T &&) noexcept(see below) // noexcept since C++23 // Test with different ref/ptr/cv qualified argument types. @@ -192,7 +192,11 @@ void test_noexcept() // test that the functions noexcept-ness is propagated using Tup = std::tuple; Tup t; +#if TEST_STD_VER >= 23 + ASSERT_NOEXCEPT(std::apply(nec, t)); +#else LIBCPP_ASSERT_NOEXCEPT(std::apply(nec, t)); +#endif ASSERT_NOT_NOEXCEPT(std::apply(tc, t)); } { @@ -200,7 +204,11 @@ void test_noexcept() using Tup = std::tuple; Tup t; ASSERT_NOT_NOEXCEPT(std::apply(nec, t)); +#if TEST_STD_VER >= 23 + ASSERT_NOEXCEPT(std::apply(nec, std::move(t))); +#else LIBCPP_ASSERT_NOEXCEPT(std::apply(nec, std::move(t))); +#endif } } -- GitLab From f0fd8fd752d69671d0cf391d90d9aba10da98978 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Tue, 9 Jan 2024 19:12:42 +0100 Subject: [PATCH 237/652] [libc++][CI] Moves CI badge to main README. (#77247) The current CI badge is currently in libc++ documentation. This does not seem the right place: - The typical location on GitHub is on the main README. - The documentation is shipped as part of the release: - This link does not work in off-line mode. Currently our documentation works in off-line mode. - The status in the release documentation does not reflect the status of the shipped library. So users looking at it may see a red status and get confused. This moves the badge to the README. --- README.md | 1 + libcxx/docs/index.rst | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/README.md b/README.md index 4ae7eaf9b083..8202ff61d42f 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,7 @@ # The LLVM Compiler Infrastructure [![OpenSSF Scorecard](https://api.securityscorecards.dev/projects/github.com/llvm/llvm-project/badge)](https://securityscorecards.dev/viewer/?uri=github.com/llvm/llvm-project) +[![libc++](https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml/badge.svg?branch=main&event=schedule)](https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml?query=event%3Aschedule) Welcome to the LLVM project! diff --git a/libcxx/docs/index.rst b/libcxx/docs/index.rst index c7769bae6bb1..bcaf99495b8f 100644 --- a/libcxx/docs/index.rst +++ b/libcxx/docs/index.rst @@ -202,10 +202,6 @@ Design Documents Build Bots and Test Coverage ============================ -.. image:: https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml/badge.svg?branch=main&event=schedule - :target: https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml?query=event%3Aschedule - :alt: Build and Test libc++ - * `Github Actions CI pipeline `_ * `Buildkite CI pipeline `_ * `LLVM Buildbot Builders `_ -- GitLab From 03a0bfa96a6eb09c4bbae344ac3aa062339aa730 Mon Sep 17 00:00:00 2001 From: martinboehme Date: Tue, 9 Jan 2024 19:18:54 +0100 Subject: [PATCH 238/652] [clang][dataflow] Add an early-out to `flowConditionImplies()` / `flowConditionAllows()`. (#77453) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This saves having to assemble the set of constraints and run the SAT solver in the trivial case where `F` is true. This is a performance win on the benchmarks for the Crubit nullability checker: ``` name old cpu/op new cpu/op delta BM_PointerAnalysisCopyPointer 64.1µs ± 5% 63.1µs ± 0% -1.56% (p=0.000 n=20+17) BM_PointerAnalysisIntLoop 172µs ± 2% 171µs ± 0% ~ (p=0.752 n=20+17) BM_PointerAnalysisPointerLoop 408µs ± 3% 355µs ± 0% -12.99% (p=0.000 n=20+17) BM_PointerAnalysisBranch 201µs ± 2% 184µs ± 0% -8.28% (p=0.000 n=20+19) BM_PointerAnalysisLoopAndBranch 684µs ± 2% 613µs ± 2% -10.38% (p=0.000 n=20+19) BM_PointerAnalysisTwoLoops 309µs ± 2% 308µs ± 2% ~ (p=0.728 n=20+19) BM_PointerAnalysisJoinFilePath 37.9ms ± 2% 37.9ms ± 2% +0.06% (p=0.041 n=20+19) BM_PointerAnalysisCallInLoop 26.5ms ± 2% 26.4ms ± 4% -0.59% (p=0.024 n=20+20) ``` When running clang-tidy on real-world code, the results are less clear. In three runs, averaged, on an arbitrarily chosen input file, I get 11.91 s of user time without this patch and 11.81 s with it, though with considerable measurement noise (I'm seeing up to 0.2 s of variation between runs). Still, this is a very simple change, and it is a clear win in benchmarks, so I think it is worth making. --- clang/include/clang/Analysis/FlowSensitive/Formula.h | 4 ++++ .../lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/clang/include/clang/Analysis/FlowSensitive/Formula.h b/clang/include/clang/Analysis/FlowSensitive/Formula.h index 982e400c1def..0e6352403a83 100644 --- a/clang/include/clang/Analysis/FlowSensitive/Formula.h +++ b/clang/include/clang/Analysis/FlowSensitive/Formula.h @@ -75,6 +75,10 @@ public: return static_cast(Value); } + bool isLiteral(bool b) const { + return kind() == Literal && static_cast(Value) == b; + } + ArrayRef operands() const { return ArrayRef(reinterpret_cast(this + 1), numOperands(kind())); diff --git a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp index fa114979c8e3..500fbb39955d 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp @@ -174,6 +174,9 @@ Solver::Result DataflowAnalysisContext::querySolver( bool DataflowAnalysisContext::flowConditionImplies(Atom Token, const Formula &F) { + if (F.isLiteral(true)) + return true; + // Returns true if and only if truth assignment of the flow condition implies // that `F` is also true. We prove whether or not this property holds by // reducing the problem to satisfiability checking. In other words, we attempt @@ -188,6 +191,9 @@ bool DataflowAnalysisContext::flowConditionImplies(Atom Token, bool DataflowAnalysisContext::flowConditionAllows(Atom Token, const Formula &F) { + if (F.isLiteral(true)) + return true; + llvm::SetVector Constraints; Constraints.insert(&arena().makeAtomRef(Token)); Constraints.insert(&F); -- GitLab From 1b8e39a1a2e8237852914501e3361d98af6db054 Mon Sep 17 00:00:00 2001 From: Jake Egan <5326451+jakeegan@users.noreply.github.com> Date: Tue, 9 Jan 2024 13:40:21 -0500 Subject: [PATCH 239/652] [clang][modules] Objective-C test lacks support on AIX/zOS (#77485) To fix error: `fatal error: error in backend: Objective-C support is unimplemented for object file format` Same rationale as 22f01cd. --- clang/test/Modules/autolink_private_module.m | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/test/Modules/autolink_private_module.m b/clang/test/Modules/autolink_private_module.m index f83f0a26b530..0c8d166a42c7 100644 --- a/clang/test/Modules/autolink_private_module.m +++ b/clang/test/Modules/autolink_private_module.m @@ -1,3 +1,5 @@ +// UNSUPPORTED: target={{.*}}-zos{{.*}}, target={{.*}}-aix{{.*}} + // Test that autolink hints for frameworks don't use the private module name. // UNSUPPORTED: target={{.*}}-zos{{.*}}, target={{.*}}-aix{{.*}} -- GitLab From 7620f03ef7a662384d67b6bd1fad8582dfe9dd82 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Jan 2024 10:42:34 -0800 Subject: [PATCH 240/652] [MC] Parse SHF_LINK_ORDER argument before section group name (#77407) When both SHF_LINK_ORDER | SHF_GROUP flags are set, GNU assembler from 2.35 onwards (https://sourceware.org/PR25381 https://sourceware.org/binutils/docs/as/Section.html) parses the SHF_LINK_ORDER argument before section group name, different from us. This is unfortunate, but does not matter because the `.section` flag `o` is a niche feature only used by compiler instrumentations, not adopted by hand-written assembly, and using both flags is extremely rare. Let's just match GNU assembler. There is another benefit: we now support zero-flag section group with the SHF_LINK_ORDER flag, while previously there isn't a syntax. While here, print 'G' after 'o' to be clear that the 'G' argument is parsed after the 'o' argument. To make the diff smaller, we don't print 'G' after 'w' in the absence of 'o' for now. --- llvm/lib/MC/MCParser/ELFAsmParser.cpp | 6 +++--- llvm/lib/MC/MCSectionELF.cpp | 20 +++++++++++-------- .../AArch64/patchable-function-entry.ll | 4 ++-- .../LoongArch/patchable-function-entry.ll | 2 +- llvm/test/CodeGen/Mips/xray-section-group.ll | 2 +- .../CodeGen/RISCV/patchable-function-entry.ll | 2 +- ...lock-sections-labels-functions-sections.ll | 2 +- .../CodeGen/X86/gcc_except_table-multi.ll | 4 ++-- .../CodeGen/X86/patchable-function-entry.ll | 4 ++-- .../stack-size-section-function-sections.ll | 4 ++-- llvm/test/CodeGen/X86/stack-size-section.ll | 2 +- llvm/test/CodeGen/X86/xray-section-group.ll | 2 +- llvm/test/MC/ELF/section-combine.s | 6 +++--- llvm/test/MC/ELF/section.s | 16 +++++++++++++++ 14 files changed, 48 insertions(+), 28 deletions(-) diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp index 93e1d2f44b8c..d4c4bcb85648 100644 --- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp +++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp @@ -616,12 +616,12 @@ bool ELFAsmParser::ParseSectionArguments(bool IsPush, SMLoc loc) { if (Mergeable) if (parseMergeSize(Size)) return true; - if (Group) - if (parseGroup(GroupName, IsComdat)) - return true; if (Flags & ELF::SHF_LINK_ORDER) if (parseLinkedToSym(LinkedToSym)) return true; + if (Group) + if (parseGroup(GroupName, IsComdat)) + return true; if (maybeParseUniqueID(UniqueID)) return true; } diff --git a/llvm/lib/MC/MCSectionELF.cpp b/llvm/lib/MC/MCSectionELF.cpp index 95fdf3352207..1e1b5edb94d7 100644 --- a/llvm/lib/MC/MCSectionELF.cpp +++ b/llvm/lib/MC/MCSectionELF.cpp @@ -90,7 +90,9 @@ void MCSectionELF::printSwitchToSection(const MCAsmInfo &MAI, const Triple &T, OS << 'e'; if (Flags & ELF::SHF_EXECINSTR) OS << 'x'; - if (Flags & ELF::SHF_GROUP) + // TODO: Always print G after o to be clear that the 'G' argument is parsed + // after the 'o' argument. + if ((Flags & ELF::SHF_GROUP) && !(Flags & ELF::SHF_LINK_ORDER)) OS << 'G'; if (Flags & ELF::SHF_WRITE) OS << 'w'; @@ -102,6 +104,8 @@ void MCSectionELF::printSwitchToSection(const MCAsmInfo &MAI, const Triple &T, OS << 'T'; if (Flags & ELF::SHF_LINK_ORDER) OS << 'o'; + if ((Flags & ELF::SHF_GROUP) && (Flags & ELF::SHF_LINK_ORDER)) + OS << 'G'; if (Flags & ELF::SHF_GNU_RETAIN) OS << 'R'; @@ -183,13 +187,6 @@ void MCSectionELF::printSwitchToSection(const MCAsmInfo &MAI, const Triple &T, OS << "," << EntrySize; } - if (Flags & ELF::SHF_GROUP) { - OS << ","; - printName(OS, Group.getPointer()->getName()); - if (isComdat()) - OS << ",comdat"; - } - if (Flags & ELF::SHF_LINK_ORDER) { OS << ","; if (LinkedToSym) @@ -198,6 +195,13 @@ void MCSectionELF::printSwitchToSection(const MCAsmInfo &MAI, const Triple &T, OS << '0'; } + if (Flags & ELF::SHF_GROUP) { + OS << ","; + printName(OS, Group.getPointer()->getName()); + if (isComdat()) + OS << ",comdat"; + } + if (isUnique()) OS << ",unique," << UniqueID; diff --git a/llvm/test/CodeGen/AArch64/patchable-function-entry.ll b/llvm/test/CodeGen/AArch64/patchable-function-entry.ll index 5750c1f601bd..89a2e2bf4abb 100644 --- a/llvm/test/CodeGen/AArch64/patchable-function-entry.ll +++ b/llvm/test/CodeGen/AArch64/patchable-function-entry.ll @@ -48,7 +48,7 @@ define void @f3() "patchable-function-entry"="3" comdat { ; CHECK-NEXT: .Lfunc_begin3: ; CHECK-COUNT-3: nop ; CHECK-NEXT: ret -; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f3,comdat,f3{{$}} +; CHECK: .section __patchable_function_entries,"awoG",@progbits,f3,f3,comdat{{$}} ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .xword .Lfunc_begin3 ret void @@ -60,7 +60,7 @@ define void @f5() "patchable-function-entry"="5" comdat { ; CHECK-NEXT: .Lfunc_begin4: ; CHECK-COUNT-5: nop ; CHECK-NEXT: sub sp, sp, #16 -; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}} +; CHECK: .section __patchable_function_entries,"awoG",@progbits,f5,f5,comdat{{$}} ; CHECK: .p2align 3 ; CHECK-NEXT: .xword .Lfunc_begin4 %frame = alloca i8, i32 16 diff --git a/llvm/test/CodeGen/LoongArch/patchable-function-entry.ll b/llvm/test/CodeGen/LoongArch/patchable-function-entry.ll index aaa3fda1ae77..2e390d1e2c33 100644 --- a/llvm/test/CodeGen/LoongArch/patchable-function-entry.ll +++ b/llvm/test/CodeGen/LoongArch/patchable-function-entry.ll @@ -31,7 +31,7 @@ define void @f5() "patchable-function-entry"="5" comdat { ; CHECK-NEXT: .Lfunc_begin2: ; CHECK-COUNT-5: nop ; CHECK-NEXT: ret -; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}} +; CHECK: .section __patchable_function_entries,"awoG",@progbits,f5,f5,comdat{{$}} ; LA32: .p2align 2 ; LA32-NEXT: .word .Lfunc_begin2 ; LA64: .p2align 3 diff --git a/llvm/test/CodeGen/Mips/xray-section-group.ll b/llvm/test/CodeGen/Mips/xray-section-group.ll index 5a208217092d..e9cd045d4411 100644 --- a/llvm/test/CodeGen/Mips/xray-section-group.ll +++ b/llvm/test/CodeGen/Mips/xray-section-group.ll @@ -24,7 +24,7 @@ $bar = comdat any define i32 @bar() nounwind noinline uwtable "function-instrument"="xray-always" comdat($bar) { ; CHECK: .section .text.bar,"axG",@progbits,bar,comdat ret i32 1 -; CHECK: .section xray_instr_map,"aGo",@progbits,bar,comdat,bar{{$}} +; CHECK: .section xray_instr_map,"aoG",@progbits,bar,bar,comdat{{$}} } ; CHECK-OBJ: Section { diff --git a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll index 2804fdfc1ac9..4eeb1bf31385 100644 --- a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll +++ b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll @@ -37,7 +37,7 @@ define void @f5() "patchable-function-entry"="5" comdat { ; NORVC-NEXT: jalr zero, 0(ra) ; RVC-COUNT-5: c.nop ; RVC-NEXT: c.jr ra -; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}} +; CHECK: .section __patchable_function_entries,"awoG",@progbits,f5,f5,comdat{{$}} ; RV32: .p2align 2 ; RV32-NEXT: .word .Lfunc_begin2 ; RV64: .p2align 3 diff --git a/llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll b/llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll index b8217bbc0076..3be3ab70f8a6 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll @@ -35,7 +35,7 @@ define linkonce_odr dso_local i32 @_Z4fooTIiET_v() comdat { ; CHECK: .section .text._Z4fooTIiET_v,"axG",@progbits,_Z4fooTIiET_v,comdat ; CHECK-LABEL: _Z4fooTIiET_v: ; CHECK-NEXT: [[FOOCOMDAT_BEGIN:.Lfunc_begin[0-9]+]]: -; CHECK: .section .llvm_bb_addr_map,"Go",@llvm_bb_addr_map,_Z4fooTIiET_v,comdat,.text._Z4fooTIiET_v{{$}} +; CHECK: .section .llvm_bb_addr_map,"oG",@llvm_bb_addr_map,.text._Z4fooTIiET_v,_Z4fooTIiET_v,comdat{{$}} ; CHECK-NEXT: .byte 2 # version ; CHECK-NEXT: .byte 0 # feature ; CHECK-NEXT: .quad [[FOOCOMDAT_BEGIN]] # function address diff --git a/llvm/test/CodeGen/X86/gcc_except_table-multi.ll b/llvm/test/CodeGen/X86/gcc_except_table-multi.ll index 8da3ebfed2bd..1eb902ae9079 100644 --- a/llvm/test/CodeGen/X86/gcc_except_table-multi.ll +++ b/llvm/test/CodeGen/X86/gcc_except_table-multi.ll @@ -17,7 +17,7 @@ define i32 @group() uwtable comdat personality ptr @__gxx_personality_v0 { ; CHECK: .cfi_endproc ; NORMAL-NEXT: .section .gcc_except_table.group,"aG",@progbits,group,comdat{{$}} ; SEP_BFD-NEXT: .section .gcc_except_table.group,"aG",@progbits,group,comdat{{$}} -; SEP-NEXT: .section .gcc_except_table.group,"aGo",@progbits,group,comdat,group{{$}} +; SEP-NEXT: .section .gcc_except_table.group,"aoG",@progbits,group,group,comdat{{$}} ; SEP_NOUNIQUE-NEXT: .section .gcc_except_table,"aG",@progbits,group,comdat{{$}} ; NOUNIQUE-NEXT: .section .gcc_except_table,"aG",@progbits,group,comdat{{$}} entry: @@ -61,7 +61,7 @@ define i32 @zero() uwtable comdat personality ptr @__gxx_personality_v0 { ; CHECK: .cfi_endproc ; NORMAL-NEXT: .section .gcc_except_table.zero,"aG",@progbits,zero{{$}} ; SEP_BFD-NEXT: .section .gcc_except_table.zero,"aG",@progbits,zero{{$}} -; SEP-NEXT: .section .gcc_except_table.zero,"aGo",@progbits,zero,zero{{$}} +; SEP-NEXT: .section .gcc_except_table.zero,"aoG",@progbits,zero,zero{{$}} ; SEP_NOUNIQUE-NEXT: .section .gcc_except_table,"aG",@progbits,zero{{$}} ; NOUNIQUE-NEXT: .section .gcc_except_table,"aG",@progbits,zero{{$}} entry: diff --git a/llvm/test/CodeGen/X86/patchable-function-entry.ll b/llvm/test/CodeGen/X86/patchable-function-entry.ll index 124f5c57c74b..8c37f5451080 100644 --- a/llvm/test/CodeGen/X86/patchable-function-entry.ll +++ b/llvm/test/CodeGen/X86/patchable-function-entry.ll @@ -50,7 +50,7 @@ define void @f3() "patchable-function-entry"="3" comdat { ; 32-NEXT: nop ; 64: nopl (%rax) ; CHECK: ret -; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f3,comdat,f3{{$}} +; CHECK: .section __patchable_function_entries,"awoG",@progbits,f3,f3,comdat{{$}} ; 32: .p2align 2 ; 32-NEXT: .long .Lfunc_begin3 ; 64: .p2align 3 @@ -66,7 +66,7 @@ define void @f5() "patchable-function-entry"="5" comdat { ; 32-NEXT: nop ; 64: nopl 8(%rax,%rax) ; CHECK-NEXT: ret -; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}} +; CHECK: .section __patchable_function_entries,"awoG",@progbits,f5,f5,comdat{{$}} ; 32: .p2align 2 ; 32-NEXT: .long .Lfunc_begin4 ; 64: .p2align 3 diff --git a/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll b/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll index 92f312bd1185..b9606c081a90 100644 --- a/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll +++ b/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll @@ -15,9 +15,9 @@ ; Check we add .stack_size section to a COMDAT group with the corresponding .text section if such a COMDAT exists. ; UNIQ: .section .text._Z4fooTIiET_v,"axG",@progbits,_Z4fooTIiET_v,comdat{{$}} -; UNIQ: .section .stack_sizes,"Go",@progbits,_Z4fooTIiET_v,comdat,.text._Z4fooTIiET_v{{$}} +; UNIQ: .section .stack_sizes,"oG",@progbits,.text._Z4fooTIiET_v,_Z4fooTIiET_v,comdat{{$}} ; NOUNIQ: .section .text,"axG",@progbits,_Z4fooTIiET_v,comdat,unique,3 -; NOUNIQ: .section .stack_sizes,"Go",@progbits,_Z4fooTIiET_v,comdat,.text,unique,3 +; NOUNIQ: .section .stack_sizes,"oG",@progbits,.text,_Z4fooTIiET_v,comdat,unique,3 $_Z4fooTIiET_v = comdat any diff --git a/llvm/test/CodeGen/X86/stack-size-section.ll b/llvm/test/CodeGen/X86/stack-size-section.ll index 3652ee845a7f..866acbe14014 100644 --- a/llvm/test/CodeGen/X86/stack-size-section.ll +++ b/llvm/test/CodeGen/X86/stack-size-section.ll @@ -29,7 +29,7 @@ define void @func2() #0 { ; Check that we still put .stack_sizes into the corresponding COMDAT group if any. ; CHECK: .section .text._Z4fooTIiET_v,"axG",@progbits,_Z4fooTIiET_v,comdat -; GROUPS: .section .stack_sizes,"Go",@progbits,_Z4fooTIiET_v,comdat,.text._Z4fooTIiET_v{{$}} +; GROUPS: .section .stack_sizes,"oG",@progbits,.text._Z4fooTIiET_v,_Z4fooTIiET_v,comdat{{$}} ; NOGROUPS: .section .stack_sizes,"",@progbits $_Z4fooTIiET_v = comdat any define linkonce_odr dso_local i32 @_Z4fooTIiET_v() comdat { diff --git a/llvm/test/CodeGen/X86/xray-section-group.ll b/llvm/test/CodeGen/X86/xray-section-group.ll index c05520adf899..1f2855b089d2 100644 --- a/llvm/test/CodeGen/X86/xray-section-group.ll +++ b/llvm/test/CodeGen/X86/xray-section-group.ll @@ -12,7 +12,7 @@ $bar = comdat any define i32 @bar() nounwind noinline uwtable "function-instrument"="xray-always" comdat($bar) { ; CHECK: .section .text.bar,"axG",@progbits,bar,comdat ret i32 1 -; CHECK: .section xray_instr_map,"aGo",@progbits,bar,comdat,bar{{$}} +; CHECK: .section xray_instr_map,"aoG",@progbits,bar,bar,comdat{{$}} } ; CHECK-OBJ: section xray_instr_map: diff --git a/llvm/test/MC/ELF/section-combine.s b/llvm/test/MC/ELF/section-combine.s index b68eaa3a05af..a6da8581a056 100644 --- a/llvm/test/MC/ELF/section-combine.s +++ b/llvm/test/MC/ELF/section-combine.s @@ -39,10 +39,10 @@ bar: .section .foo,"o",@progbits,bar,unique,1 .byte 5 -.section .foo,"Go",@progbits,comdat0,comdat,bar,unique,1 +.section .foo,"Go",@progbits,bar,comdat0,comdat,unique,1 .byte 6 -.section .foo,"Go",@progbits,comdat1,comdat,bar,unique,1 +.section .foo,"Go",@progbits,bar,comdat1,comdat,unique,1 .byte 7 -.section .foo,"Go",@progbits,comdat1,comdat,bar,unique,1 +.section .foo,"oG",@progbits,bar,comdat1,comdat,unique,1 .byte 8 diff --git a/llvm/test/MC/ELF/section.s b/llvm/test/MC/ELF/section.s index 8c625256a276..e4e6f4bccb8a 100644 --- a/llvm/test/MC/ELF/section.s +++ b/llvm/test/MC/ELF/section.s @@ -166,9 +166,11 @@ bar: .section .shf_metadata1,"ao",@progbits,.Lshf_metadata_target2_1 .section .shf_metadata2,"ao",@progbits,.Lshf_metadata_target2_2 .section .shf_metadata3,"ao",@progbits,.shf_metadata_target1 +.section .linkorder_group_zero,"aoG",@progbits,.shf_metadata_target1,foo // ASM: .section .shf_metadata1,"ao",@progbits,.Lshf_metadata_target2_1 // ASM: .section .shf_metadata2,"ao",@progbits,.Lshf_metadata_target2_2 // ASM: .section .shf_metadata3,"ao",@progbits,.shf_metadata_target1 +// ASM: .section .linkorder_group_zero,"aoG",@progbits,.shf_metadata_target1,foo{{$}} // CHECK: Section { // CHECK: Index: 22 @@ -221,6 +223,20 @@ bar: // CHECK-NEXT: Link: 22 // CHECK-NEXT: Info: 0 +// CHECK: Section { +// CHECK: Name: .linkorder_group_zero +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_GROUP +// CHECK-NEXT: SHF_LINK_ORDER +// CHECK-NEXT: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: +// CHECK-NEXT: Link: 22 +// CHECK-NEXT: Info: 0 + .section .text.foo // CHECK: Section { // CHECK: Name: .text.foo -- GitLab From fa9284589f111cfd3614a75bfbe0709db39a8f15 Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Tue, 9 Jan 2024 10:45:30 -0800 Subject: [PATCH 241/652] =?UTF-8?q?[lldb]=20DWARFDIE:=20Follow=20DW=5FAT?= =?UTF-8?q?=5Fspecification=20when=20computing=20CompilerCo=E2=80=A6=20(#7?= =?UTF-8?q?7157)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …ntext Following the specification chain seems to be clearly the expected behavior of GetDeclContext(). Otherwise C++ methods have an empty CompilerContext instead of being nested in their struct/class. Theprimary motivation for this functionality is the Swift plugin. In order to test the change I added a proof-of-concept implementation of a Module::FindFunction() variant that takes a CompilerContext, expesed via lldb-test. rdar://120553412 --- lldb/include/lldb/Core/Module.h | 6 +++ lldb/source/Core/Module.cpp | 17 +++++++ .../Plugins/SymbolFile/DWARF/DWARFDIE.cpp | 44 ++++++++++++------- .../SymbolFile/DWARF/SymbolFileDWARF.cpp | 11 ++--- .../DWARF/x86/find-basic-function.cpp | 6 +++ lldb/tools/lldb-test/lldb-test.cpp | 4 ++ 6 files changed, 67 insertions(+), 21 deletions(-) diff --git a/lldb/include/lldb/Core/Module.h b/lldb/include/lldb/Core/Module.h index f4973cdda1ef..0188057247a6 100644 --- a/lldb/include/lldb/Core/Module.h +++ b/lldb/include/lldb/Core/Module.h @@ -337,6 +337,12 @@ public: const ModuleFunctionSearchOptions &options, SymbolContextList &sc_list); + /// Find functions by compiler context. + void FindFunctions(llvm::ArrayRef compiler_ctx, + lldb::FunctionNameType name_type_mask, + const ModuleFunctionSearchOptions &options, + SymbolContextList &sc_list); + /// Find functions by name. /// /// If the function is an inlined function, it will have a block, diff --git a/lldb/source/Core/Module.cpp b/lldb/source/Core/Module.cpp index c0574b724ace..331cf3246641 100644 --- a/lldb/source/Core/Module.cpp +++ b/lldb/source/Core/Module.cpp @@ -855,6 +855,23 @@ void Module::FindFunctions(ConstString name, } } +void Module::FindFunctions(llvm::ArrayRef compiler_ctx, + FunctionNameType name_type_mask, + const ModuleFunctionSearchOptions &options, + SymbolContextList &sc_list) { + if (compiler_ctx.empty() || + compiler_ctx.back().kind != CompilerContextKind::Function) + return; + ConstString name = compiler_ctx.back().name; + SymbolContextList unfiltered; + FindFunctions(name, CompilerDeclContext(), name_type_mask, options, + unfiltered); + // Filter by context. + for (auto &sc : unfiltered) + if (sc.function && compiler_ctx.equals(sc.function->GetCompilerContext())) + sc_list.Append(sc); +} + void Module::FindFunctions(const RegularExpression ®ex, const ModuleFunctionSearchOptions &options, SymbolContextList &sc_list) { diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp index bed68f45426f..d4446befd83b 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp @@ -373,44 +373,51 @@ std::vector DWARFDIE::GetDeclContextDIEs() const { return result; } -std::vector DWARFDIE::GetDeclContext() const { +static std::vector +GetDeclContextImpl(llvm::SmallSet &seen, DWARFDIE die) { std::vector context; - const dw_tag_t tag = Tag(); - if (tag == DW_TAG_compile_unit || tag == DW_TAG_partial_unit) + // Stop if we hit a cycle. + if (!die || !seen.insert(die.GetID()).second) return context; - DWARFDIE parent = GetParent(); - if (parent) - context = parent.GetDeclContext(); + + // Handle outline member function DIEs by following the specification. + if (DWARFDIE spec = die.GetReferencedDIE(DW_AT_specification)) + return GetDeclContextImpl(seen, spec); + + // Get the parent context chain. + context = GetDeclContextImpl(seen, die.GetParent()); + + // Add this DIE's contribution at the end of the chain. auto push_ctx = [&](CompilerContextKind kind, llvm::StringRef name) { context.push_back({kind, ConstString(name)}); }; - switch (tag) { + switch (die.Tag()) { case DW_TAG_module: - push_ctx(CompilerContextKind::Module, GetName()); + push_ctx(CompilerContextKind::Module, die.GetName()); break; case DW_TAG_namespace: - push_ctx(CompilerContextKind::Namespace, GetName()); + push_ctx(CompilerContextKind::Namespace, die.GetName()); break; case DW_TAG_structure_type: - push_ctx(CompilerContextKind::Struct, GetName()); + push_ctx(CompilerContextKind::Struct, die.GetName()); break; case DW_TAG_union_type: - push_ctx(CompilerContextKind::Union, GetName()); + push_ctx(CompilerContextKind::Union, die.GetName()); break; case DW_TAG_class_type: - push_ctx(CompilerContextKind::Class, GetName()); + push_ctx(CompilerContextKind::Class, die.GetName()); break; case DW_TAG_enumeration_type: - push_ctx(CompilerContextKind::Enum, GetName()); + push_ctx(CompilerContextKind::Enum, die.GetName()); break; case DW_TAG_subprogram: - push_ctx(CompilerContextKind::Function, GetPubname()); + push_ctx(CompilerContextKind::Function, die.GetName()); break; case DW_TAG_variable: - push_ctx(CompilerContextKind::Variable, GetPubname()); + push_ctx(CompilerContextKind::Variable, die.GetPubname()); break; case DW_TAG_typedef: - push_ctx(CompilerContextKind::Typedef, GetName()); + push_ctx(CompilerContextKind::Typedef, die.GetName()); break; default: break; @@ -418,6 +425,11 @@ std::vector DWARFDIE::GetDeclContext() const { return context; } +std::vector DWARFDIE::GetDeclContext() const { + llvm::SmallSet seen; + return GetDeclContextImpl(seen, *this); +} + std::vector DWARFDIE::GetTypeLookupContext() const { std::vector context; diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index 737da7798b82..1a16b70f42fe 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -2574,11 +2574,12 @@ void SymbolFileDWARF::FindFunctions(const Module::LookupInfo &lookup_info, Module::LookupInfo no_tp_lookup_info(lookup_info); no_tp_lookup_info.SetLookupName(ConstString(name_no_template_params)); - m_index->GetFunctions(no_tp_lookup_info, *this, parent_decl_ctx, [&](DWARFDIE die) { - if (resolved_dies.insert(die.GetDIE()).second) - ResolveFunction(die, include_inlines, sc_list); - return true; - }); + m_index->GetFunctions(no_tp_lookup_info, *this, parent_decl_ctx, + [&](DWARFDIE die) { + if (resolved_dies.insert(die.GetDIE()).second) + ResolveFunction(die, include_inlines, sc_list); + return true; + }); } } diff --git a/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp b/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp index 204568a446d0..30143a41d5e7 100644 --- a/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp +++ b/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp @@ -34,6 +34,8 @@ // RUN: FileCheck --check-prefix=FULL-MANGLED-METHOD %s // RUN: lldb-test symbols --name=foo --context=context --find=function --function-flags=base %t | \ // RUN: FileCheck --check-prefix=CONTEXT %s +// RUN: lldb-test symbols --compiler-context=Struct:sbar,Function:foo -language=c++ -find=function -function-flags=method %t | \ +// RUN: FileCheck --check-prefix=COMPILER-CONTEXT %s // RUN: lldb-test symbols --name=not_there --find=function %t | \ // RUN: FileCheck --check-prefix=EMPTY %s @@ -84,6 +86,10 @@ // CONTEXT: Found 1 functions: // CONTEXT-DAG: name = "bar::foo()", mangled = "_ZN3bar3fooEv", decl_context = {Namespace(bar)} +// COMPILER-CONTEXT: Found 2 functions: +// COMPILER-CONTEXT-DAG: name = "sbar::foo()", mangled = "_ZN4sbar3fooEv" +// COMPILER-CONTEXT-DAG: name = "sbar::foo(int)", mangled = "_ZN4sbar3fooEi" + // EMPTY: Found 0 functions: void foo() {} diff --git a/lldb/tools/lldb-test/lldb-test.cpp b/lldb/tools/lldb-test/lldb-test.cpp index e326a84c1dbd..33281cfb1507 100644 --- a/lldb/tools/lldb-test/lldb-test.cpp +++ b/lldb/tools/lldb-test/lldb-test.cpp @@ -466,6 +466,7 @@ static lldb::DescriptionLevel GetDescriptionLevel() { Error opts::symbols::findFunctions(lldb_private::Module &Module) { SymbolFile &Symfile = *Module.GetSymbolFile(); SymbolContextList List; + auto compiler_context = parseCompilerContext(); if (!File.empty()) { assert(Line != 0); @@ -498,6 +499,9 @@ Error opts::symbols::findFunctions(lldb_private::Module &Module) { assert(RE.IsValid()); List.Clear(); Symfile.FindFunctions(RE, true, List); + } else if (!compiler_context.empty()) { + List.Clear(); + Module.FindFunctions(compiler_context, getFunctionNameFlags(), {}, List); } else { Expected ContextOr = getDeclContext(Symfile); if (!ContextOr) -- GitLab From f972e4d3434364718899f974e4d1c8e60aea91fa Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Jan 2024 10:48:23 -0800 Subject: [PATCH 242/652] [MC,ELF] .section: unconditionally print section flag 'G' after 'o' * Placing 'G' before 'M' (SHF_MERGE) can be misleading as the sh_entsize argument goes before the section group name, if a reader doesn't know that the order of extra arguments is not affected by the order of flags. * 'a', 'w', and 'x' indicate basic permission-related flags. Separating them with 'G' is kinda ugly. Simplify code and move 'G' after 'o'. The new output is more similar to GCC. --- llvm/lib/MC/MCSectionELF.cpp | 6 +----- llvm/test/CodeGen/Mips/ehframe-indirect.ll | 2 +- llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll | 4 ++-- llvm/test/CodeGen/SPARC/constructor.ll | 4 ++-- llvm/test/CodeGen/X86/constructor.ll | 12 ++++++------ llvm/test/CodeGen/X86/elf-comdat.ll | 2 +- llvm/test/CodeGen/X86/elf-comdat2.ll | 2 +- llvm/test/CodeGen/X86/elf-group.ll | 2 +- .../CodeGen/X86/explicit-section-mergeable.ll | 18 +++++++++--------- .../test/CodeGen/X86/global-sections-comdat.ll | 6 +++--- .../DebugInfo/SystemZ/eh_frame_personality.ll | 2 +- .../DebugInfo/SystemZ/eh_frame_personality.s | 2 +- .../JITLink/x86-64/ELF_ehframe_basic.s | 2 +- ...hframe_large_static_personality_encodings.s | 2 +- llvm/test/MC/ELF/alias-to-local.s | 2 +- llvm/test/MC/ELF/relocation.s | 2 +- llvm/test/tools/llvm-symbolizer/frame.s | 2 +- 17 files changed, 34 insertions(+), 38 deletions(-) diff --git a/llvm/lib/MC/MCSectionELF.cpp b/llvm/lib/MC/MCSectionELF.cpp index 1e1b5edb94d7..b1efb839ba75 100644 --- a/llvm/lib/MC/MCSectionELF.cpp +++ b/llvm/lib/MC/MCSectionELF.cpp @@ -90,10 +90,6 @@ void MCSectionELF::printSwitchToSection(const MCAsmInfo &MAI, const Triple &T, OS << 'e'; if (Flags & ELF::SHF_EXECINSTR) OS << 'x'; - // TODO: Always print G after o to be clear that the 'G' argument is parsed - // after the 'o' argument. - if ((Flags & ELF::SHF_GROUP) && !(Flags & ELF::SHF_LINK_ORDER)) - OS << 'G'; if (Flags & ELF::SHF_WRITE) OS << 'w'; if (Flags & ELF::SHF_MERGE) @@ -104,7 +100,7 @@ void MCSectionELF::printSwitchToSection(const MCAsmInfo &MAI, const Triple &T, OS << 'T'; if (Flags & ELF::SHF_LINK_ORDER) OS << 'o'; - if ((Flags & ELF::SHF_GROUP) && (Flags & ELF::SHF_LINK_ORDER)) + if (Flags & ELF::SHF_GROUP) OS << 'G'; if (Flags & ELF::SHF_GNU_RETAIN) OS << 'R'; diff --git a/llvm/test/CodeGen/Mips/ehframe-indirect.ll b/llvm/test/CodeGen/Mips/ehframe-indirect.ll index b3f4b48329d7..e36fa2f9ce42 100644 --- a/llvm/test/CodeGen/Mips/ehframe-indirect.ll +++ b/llvm/test/CodeGen/Mips/ehframe-indirect.ll @@ -62,7 +62,7 @@ declare void @foo() ; N64: .8byte _ZTISt9exception ; ALL: .hidden DW.ref.__gxx_personality_v0 ; ALL: .weak DW.ref.__gxx_personality_v0 -; ALL: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat +; ALL: .section .data.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat ; O32: .p2align 2 ; N32: .p2align 2 ; N64: .p2align 3 diff --git a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll index 45aeb73b1a6b..025a5ad787fb 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll @@ -49,9 +49,9 @@ entry: ; LARGE-SECUREPLT: addi 30, 30, .LTOC-.L0$pb@l ; LARGE-SECUREPLT: bl call_foo@PLT+32768 -; LARGE: .section .bss.bar1,"aGw",@nobits,bar1,comdat +; LARGE: .section .bss.bar1,"awG",@nobits,bar1,comdat ; LARGE: bar1: -; LARGE: .section .bss.bar2,"aGw",@nobits,bar1,comdat +; LARGE: .section .bss.bar2,"awG",@nobits,bar1,comdat ; LARGE: bar2: ; LARGE: .section .got2,"aw",@progbits ; LARGE-NEXT: .p2align 2 diff --git a/llvm/test/CodeGen/SPARC/constructor.ll b/llvm/test/CodeGen/SPARC/constructor.ll index e69ad26d0927..dea152dd0f08 100644 --- a/llvm/test/CodeGen/SPARC/constructor.ll +++ b/llvm/test/CodeGen/SPARC/constructor.ll @@ -17,11 +17,11 @@ entry: ; CTOR: .section .ctors,"aw" ; CTOR-NEXT: .p2align 2 ; CTOR-NEXT: .word f -; CTOR-NEXT: .section .ctors.65520,"aGw" +; CTOR-NEXT: .section .ctors.65520,"awG",@progbits,v,comdat{{$}} ; CTOR-NEXT: .p2align 2 ; CTOR-NEXT: .word g -; INIT-ARRAY: .section .init_array.15,"aGw" +; INIT-ARRAY: .section .init_array.15,"awG",@init_array,v,comdat{{$}} ; INIT-ARRAY-NEXT: .p2align 2 ; INIT-ARRAY-NEXT: .word g ; INIT-ARRAY-NEXT: .section .init_array,"aw" diff --git a/llvm/test/CodeGen/X86/constructor.ll b/llvm/test/CodeGen/X86/constructor.ll index 0fea69b5a7bc..3133979b32f8 100644 --- a/llvm/test/CodeGen/X86/constructor.ll +++ b/llvm/test/CodeGen/X86/constructor.ll @@ -43,17 +43,17 @@ entry: ; CTOR-NEXT: .quad j ; CTOR-NEXT: .quad i ; CTOR-NEXT: .quad f -; CTOR-NEXT: .section .ctors.09980,"aGw",@progbits,v,comdat +; CTOR-NEXT: .section .ctors.09980,"awG",@progbits,v,comdat ; CTOR-NEXT: .p2align 3 ; CTOR-NEXT: .quad h -; CTOR-NEXT: .section .ctors.65520,"aGw",@progbits,v,comdat +; CTOR-NEXT: .section .ctors.65520,"awG",@progbits,v,comdat ; CTOR-NEXT: .p2align 3 ; CTOR-NEXT: .quad g -; INIT-ARRAY: .section .init_array.15,"aGw",@init_array,v,comdat +; INIT-ARRAY: .section .init_array.15,"awG",@init_array,v,comdat ; INIT-ARRAY-NEXT: .p2align 3 ; INIT-ARRAY-NEXT: .quad g -; INIT-ARRAY-NEXT: .section .init_array.55555,"aGw",@init_array,v,comdat +; INIT-ARRAY-NEXT: .section .init_array.55555,"awG",@init_array,v,comdat ; INIT-ARRAY-NEXT: .p2align 3 ; INIT-ARRAY-NEXT: .quad h ; INIT-ARRAY-NEXT: .section .init_array,"aw",@init_array @@ -62,10 +62,10 @@ entry: ; INIT-ARRAY-NEXT: .quad i ; INIT-ARRAY-NEXT: .quad j -; NACL: .section .init_array.15,"aGw",@init_array,v,comdat +; NACL: .section .init_array.15,"awG",@init_array,v,comdat ; NACL-NEXT: .p2align 2 ; NACL-NEXT: .long g -; NACL-NEXT: .section .init_array.55555,"aGw",@init_array,v,comdat +; NACL-NEXT: .section .init_array.55555,"awG",@init_array,v,comdat ; NACL-NEXT: .p2align 2 ; NACL-NEXT: .long h ; NACL-NEXT: .section .init_array,"aw",@init_array diff --git a/llvm/test/CodeGen/X86/elf-comdat.ll b/llvm/test/CodeGen/X86/elf-comdat.ll index 35d8d6f2d2af..10770dd07409 100644 --- a/llvm/test/CodeGen/X86/elf-comdat.ll +++ b/llvm/test/CodeGen/X86/elf-comdat.ll @@ -7,5 +7,5 @@ define void @f() comdat($f) { } ; CHECK: .section .text.f,"axG",@progbits,f,comdat ; CHECK: .globl f -; CHECK: .section .bss.v,"aGw",@nobits,f,comdat +; CHECK: .section .bss.v,"awG",@nobits,f,comdat ; CHECK: .globl v diff --git a/llvm/test/CodeGen/X86/elf-comdat2.ll b/llvm/test/CodeGen/X86/elf-comdat2.ll index 786cec78cc30..3e43c43b7d74 100644 --- a/llvm/test/CodeGen/X86/elf-comdat2.ll +++ b/llvm/test/CodeGen/X86/elf-comdat2.ll @@ -5,7 +5,7 @@ $foo = comdat any @foo = global i32 42 ; CHECK: .type bar,@object -; CHECK-NEXT: .section .data.bar,"aGw",@progbits,foo,comdat +; CHECK-NEXT: .section .data.bar,"awG",@progbits,foo,comdat ; CHECK-NEXT: .globl bar ; CHECK: .type foo,@object ; CHECK-NEXT: .data diff --git a/llvm/test/CodeGen/X86/elf-group.ll b/llvm/test/CodeGen/X86/elf-group.ll index 3aaef0fa49da..a69ba491be0f 100644 --- a/llvm/test/CodeGen/X86/elf-group.ll +++ b/llvm/test/CodeGen/X86/elf-group.ll @@ -4,7 +4,7 @@ ; CHECK: .section .text.f1,"axG",@progbits,f1{{$}} ; CHECK: .section .text.f2,"axG",@progbits,f1{{$}} -; CHECK: .section .bss.g1,"aGw",@nobits,f1{{$}} +; CHECK: .section .bss.g1,"awG",@nobits,f1{{$}} $f1 = comdat nodeduplicate diff --git a/llvm/test/CodeGen/X86/explicit-section-mergeable.ll b/llvm/test/CodeGen/X86/explicit-section-mergeable.ll index 0a3a60474e1e..09995919d955 100644 --- a/llvm/test/CodeGen/X86/explicit-section-mergeable.ll +++ b/llvm/test/CodeGen/X86/explicit-section-mergeable.ll @@ -139,9 +139,9 @@ !4 = !{ptr @implicit_rodata_cst4} ;; Test implicit section assignment for globals in distinct comdat groups. -; CHECK: .section .rodata.cst4,"aGM",@progbits,4,f,comdat,unique,[[#U+7]] +; CHECK: .section .rodata.cst4,"aMG",@progbits,4,f,comdat,unique,[[#U+7]] ; CHECK: implicit_rodata_cst4_comdat: -; CHECK: .section .rodata.cst8,"aGM",@progbits,8,g,comdat,unique,[[#U+8]] +; CHECK: .section .rodata.cst8,"aMG",@progbits,8,g,comdat,unique,[[#U+8]] ; CHECK: implicit_rodata_cst8_comdat: ;; Check that globals in distinct comdat groups that are explicitly assigned @@ -153,11 +153,11 @@ ;; are incorrect. ; CHECK: .section .explicit_comdat_distinct,"aM",@progbits,4,unique,[[#U+9]] ; CHECK: explicit_comdat_distinct_supply_uid: -; CHECK: .section .explicit_comdat_distinct,"aGM",@progbits,4,f,comdat,unique,[[#U+10]] +; CHECK: .section .explicit_comdat_distinct,"aMG",@progbits,4,f,comdat,unique,[[#U+10]] ; CHECK: explicit_comdat_distinct1: -; CHECK: .section .explicit_comdat_distinct,"aGM",@progbits,4,g,comdat,unique,[[#U+10]] +; CHECK: .section .explicit_comdat_distinct,"aMG",@progbits,4,g,comdat,unique,[[#U+10]] ; CHECK: explicit_comdat_distinct2: -; CHECK: .section .explicit_comdat_distinct,"aGM",@progbits,8,h,comdat,unique,[[#U+11]] +; CHECK: .section .explicit_comdat_distinct,"aMG",@progbits,8,h,comdat,unique,[[#U+11]] ; CHECK: explicit_comdat_distinct3: $f = comdat any @@ -173,9 +173,9 @@ $h = comdat any @explicit_comdat_distinct3 = unnamed_addr constant [2 x i32] [i32 1, i32 1], section ".explicit_comdat_distinct", comdat($h) ;; Test implicit section assignment for globals in the same comdat group. -; CHECK: .section .rodata.cst4,"aGM",@progbits,4,i,comdat,unique,[[#U+12]] +; CHECK: .section .rodata.cst4,"aMG",@progbits,4,i,comdat,unique,[[#U+12]] ; CHECK: implicit_rodata_cst4_same_comdat: -; CHECK: .section .rodata.cst8,"aGM",@progbits,8,i,comdat,unique,[[#U+13]] +; CHECK: .section .rodata.cst8,"aMG",@progbits,8,i,comdat,unique,[[#U+13]] ; CHECK: implicit_rodata_cst8_same_comdat: ;; Check that globals in the same comdat group that are explicitly assigned @@ -187,10 +187,10 @@ $h = comdat any ;; are incorrect. ; CHECK: .section .explicit_comdat_same,"aM",@progbits,4,unique,[[#U+14]] ; CHECK: explicit_comdat_same_supply_uid: -; CHECK: .section .explicit_comdat_same,"aGM",@progbits,4,i,comdat,unique,[[#U+15]] +; CHECK: .section .explicit_comdat_same,"aMG",@progbits,4,i,comdat,unique,[[#U+15]] ; CHECK: explicit_comdat_same1: ; CHECK: explicit_comdat_same2: -; CHECK: .section .explicit_comdat_same,"aGM",@progbits,8,i,comdat,unique,[[#U+16]] +; CHECK: .section .explicit_comdat_same,"aMG",@progbits,8,i,comdat,unique,[[#U+16]] ; CHECK: explicit_comdat_same3: $i = comdat any diff --git a/llvm/test/CodeGen/X86/global-sections-comdat.ll b/llvm/test/CodeGen/X86/global-sections-comdat.ll index 730050dda5f3..7b793815f238 100644 --- a/llvm/test/CodeGen/X86/global-sections-comdat.ll +++ b/llvm/test/CodeGen/X86/global-sections-comdat.ll @@ -41,6 +41,6 @@ bb5: $G16 = comdat any @G16 = unnamed_addr constant i32 42, comdat -; LINUX: .section .rodata.cst4.G16,"aGM",@progbits,4,G16,comdat -; LINUX-SECTIONS: .section .rodata.cst4.G16,"aGM",@progbits,4,G16,comdat -; LINUX-SECTIONS-SHORT: .section .rodata.cst4,"aGM",@progbits,4,G16,comdat +; LINUX: .section .rodata.cst4.G16,"aMG",@progbits,4,G16,comdat +; LINUX-SECTIONS: .section .rodata.cst4.G16,"aMG",@progbits,4,G16,comdat +; LINUX-SECTIONS-SHORT: .section .rodata.cst4,"aMG",@progbits,4,G16,comdat diff --git a/llvm/test/DebugInfo/SystemZ/eh_frame_personality.ll b/llvm/test/DebugInfo/SystemZ/eh_frame_personality.ll index e1c656c4b3eb..002da2f0e7f2 100644 --- a/llvm/test/DebugInfo/SystemZ/eh_frame_personality.ll +++ b/llvm/test/DebugInfo/SystemZ/eh_frame_personality.ll @@ -39,7 +39,7 @@ clean: ; CHECK-REF: .cfi_lsda 27, .Lexception0 ; CHECK-REF: .hidden DW.ref.__gxx_personality_v0 ; CHECK-REF: .weak DW.ref.__gxx_personality_v0 -; CHECK-REF: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat +; CHECK-REF: .section .data.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat ; CHECK-REF-NEXT: .p2align 3 ; CHECK-REF-NEXT: .type DW.ref.__gxx_personality_v0,@object ; CHECK-REF-NEXT: .size DW.ref.__gxx_personality_v0, 8 diff --git a/llvm/test/DebugInfo/SystemZ/eh_frame_personality.s b/llvm/test/DebugInfo/SystemZ/eh_frame_personality.s index c452951941a1..0c99361b4acf 100644 --- a/llvm/test/DebugInfo/SystemZ/eh_frame_personality.s +++ b/llvm/test/DebugInfo/SystemZ/eh_frame_personality.s @@ -25,7 +25,7 @@ foo: # @foo .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 - .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat + .section .data.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0,@object .size DW.ref.__gxx_personality_v0, 8 diff --git a/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_basic.s b/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_basic.s index 1b3ff16ea149..c01ced5d0523 100644 --- a/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_basic.s +++ b/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_basic.s @@ -106,7 +106,7 @@ GCC_except_table1: .quad _ZTIi .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 - .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat + .section .data.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .p2align 3 .type DW.ref.__gxx_personality_v0,@object .size DW.ref.__gxx_personality_v0, 8 diff --git a/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_large_static_personality_encodings.s b/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_large_static_personality_encodings.s index 02538442d9d9..64990b5d38f0 100644 --- a/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_large_static_personality_encodings.s +++ b/llvm/test/ExecutionEngine/JITLink/x86-64/ELF_ehframe_large_static_personality_encodings.s @@ -190,7 +190,7 @@ GCC_except_table1: .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 - .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat + .section .data.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .p2align 3 .type DW.ref.__gxx_personality_v0,@object .size DW.ref.__gxx_personality_v0, 8 diff --git a/llvm/test/MC/ELF/alias-to-local.s b/llvm/test/MC/ELF/alias-to-local.s index 5b6ac058c1e8..beff230a8db3 100644 --- a/llvm/test/MC/ELF/alias-to-local.s +++ b/llvm/test/MC/ELF/alias-to-local.s @@ -10,7 +10,7 @@ foo: movl $zed, %eax - .section .data.bar,"aGw",@progbits,zed,comdat + .section .data.bar,"awG",@progbits,zed,comdat bar: .byte 42 diff --git a/llvm/test/MC/ELF/relocation.s b/llvm/test/MC/ELF/relocation.s index 797e31f529b3..80b671aa2c85 100644 --- a/llvm/test/MC/ELF/relocation.s +++ b/llvm/test/MC/ELF/relocation.s @@ -4,7 +4,7 @@ // Test that we produce the correct relocation. - .section .pr23272,"aGw",@progbits,pr23272,comdat + .section .pr23272,"awG",@progbits,pr23272,comdat .globl pr23272 pr23272: pr23272_2: diff --git a/llvm/test/tools/llvm-symbolizer/frame.s b/llvm/test/tools/llvm-symbolizer/frame.s index 28cbd493182e..741132ad32d7 100644 --- a/llvm/test/tools/llvm-symbolizer/frame.s +++ b/llvm/test/tools/llvm-symbolizer/frame.s @@ -203,7 +203,7 @@ hwasan.module_ctor: // @hwasan.module_ctor .size hwasan.module_ctor, .Lfunc_end1-hwasan.module_ctor .cfi_endproc // -- End function - .section .init_array.0,"aGw",@init_array,hwasan.module_ctor,comdat + .section .init_array.0,"awG",@init_array,hwasan.module_ctor,comdat .p2align 3 .xword hwasan.module_ctor .section .debug_str,"MS",@progbits,1 -- GitLab From c1173e4e05375514b1416e00b092e1ea1468a46e Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Jan 2024 16:54:40 +0000 Subject: [PATCH 243/652] [DAG] Use FoldConstantArithmetic for unary bitops constant folding. BSWAP/BITREVERSE/CTPOP/CTLZ/CTLZ_ZERO_UNDEF/CTTZ/CTTZ_ZERO_UNDEF are all handled by FoldConstantArithmetic - so use directly instead of testing for isConstantIntBuildVectorOrConstantInt and relying on DAG.getNode() to perform the constant fold. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 46 +++++++++++-------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 58c8ccfb63ea..54732237c91a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -10999,8 +10999,8 @@ SDValue DAGCombiner::visitBSWAP(SDNode *N) { SDLoc DL(N); // fold (bswap c1) -> c2 - if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) - return DAG.getNode(ISD::BSWAP, DL, VT, N0); + if (SDValue C = DAG.FoldConstantArithmetic(ISD::BSWAP, DL, VT, {N0})) + return C; // fold (bswap (bswap x)) -> x if (N0.getOpcode() == ISD::BSWAP) return N0.getOperand(0); @@ -11059,10 +11059,11 @@ SDValue DAGCombiner::visitBSWAP(SDNode *N) { SDValue DAGCombiner::visitBITREVERSE(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + SDLoc DL(N); // fold (bitreverse c1) -> c2 - if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) - return DAG.getNode(ISD::BITREVERSE, SDLoc(N), VT, N0); + if (SDValue C = DAG.FoldConstantArithmetic(ISD::BITREVERSE, DL, VT, {N0})) + return C; // fold (bitreverse (bitreverse x)) -> x if (N0.getOpcode() == ISD::BITREVERSE) return N0.getOperand(0); @@ -11072,16 +11073,16 @@ SDValue DAGCombiner::visitBITREVERSE(SDNode *N) { SDValue DAGCombiner::visitCTLZ(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + SDLoc DL(N); // fold (ctlz c1) -> c2 - if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) - return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); + if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTLZ, DL, VT, {N0})) + return C; // If the value is known never to be zero, switch to the undef version. - if (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ_ZERO_UNDEF, VT)) { + if (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ_ZERO_UNDEF, VT)) if (DAG.isKnownNeverZero(N0)) - return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); - } + return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, DL, VT, N0); return SDValue(); } @@ -11089,26 +11090,28 @@ SDValue DAGCombiner::visitCTLZ(SDNode *N) { SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + SDLoc DL(N); // fold (ctlz_zero_undef c1) -> c2 - if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) - return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); + if (SDValue C = + DAG.FoldConstantArithmetic(ISD::CTLZ_ZERO_UNDEF, DL, VT, {N0})) + return C; return SDValue(); } SDValue DAGCombiner::visitCTTZ(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + SDLoc DL(N); // fold (cttz c1) -> c2 - if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) - return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); + if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTTZ, DL, VT, {N0})) + return C; // If the value is known never to be zero, switch to the undef version. - if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_UNDEF, VT)) { + if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_UNDEF, VT)) if (DAG.isKnownNeverZero(N0)) - return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); - } + return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, DL, VT, N0); return SDValue(); } @@ -11116,20 +11119,23 @@ SDValue DAGCombiner::visitCTTZ(SDNode *N) { SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + SDLoc DL(N); // fold (cttz_zero_undef c1) -> c2 - if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) - return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); + if (SDValue C = + DAG.FoldConstantArithmetic(ISD::CTTZ_ZERO_UNDEF, DL, VT, {N0})) + return C; return SDValue(); } SDValue DAGCombiner::visitCTPOP(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + SDLoc DL(N); // fold (ctpop c1) -> c2 - if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) - return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0); + if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTPOP, DL, VT, {N0})) + return C; return SDValue(); } -- GitLab From 417df8ee4a149cc49b3fa7e68c64cb926fee8a6f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Jan 2024 18:34:31 +0000 Subject: [PATCH 244/652] [X86] Add test coverage for #77459 --- llvm/test/CodeGen/X86/pr77459.ll | 404 +++++++++++++++++++++++++++++++ 1 file changed, 404 insertions(+) create mode 100644 llvm/test/CodeGen/X86/pr77459.ll diff --git a/llvm/test/CodeGen/X86/pr77459.ll b/llvm/test/CodeGen/X86/pr77459.ll new file mode 100644 index 000000000000..a16990a6ac31 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr77459.ll @@ -0,0 +1,404 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE,SSE42 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX2 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 -mattr=+avx512vbmi | FileCheck %s --check-prefixes=AVX512 + +define i4 @reverse_cmp_v4i1(<4 x i32> %a0, <4 x i32> %a1) { +; SSE-LABEL: reverse_cmp_v4i1: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE-NEXT: movmskps %xmm0, %eax +; SSE-NEXT: leal (%rax,%rax), %ecx +; SSE-NEXT: andb $4, %cl +; SSE-NEXT: leal (,%rax,8), %edx +; SSE-NEXT: andb $8, %dl +; SSE-NEXT: orb %cl, %dl +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: shrb %cl +; SSE-NEXT: andb $2, %cl +; SSE-NEXT: orb %dl, %cl +; SSE-NEXT: shrb $3, %al +; SSE-NEXT: orb %cl, %al +; SSE-NEXT: # kill: def $al killed $al killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: reverse_cmp_v4i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovmskps %xmm0, %eax +; AVX2-NEXT: leal (%rax,%rax), %ecx +; AVX2-NEXT: andb $4, %cl +; AVX2-NEXT: leal (,%rax,8), %edx +; AVX2-NEXT: andb $8, %dl +; AVX2-NEXT: orb %cl, %dl +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: shrb %cl +; AVX2-NEXT: andb $2, %cl +; AVX2-NEXT: orb %dl, %cl +; AVX2-NEXT: shrb $3, %al +; AVX2-NEXT: orb %cl, %al +; AVX2-NEXT: # kill: def $al killed $al killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: reverse_cmp_v4i1: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 +; AVX512-NEXT: kmovd %k0, %ecx +; AVX512-NEXT: movl %ecx, %eax +; AVX512-NEXT: andb $8, %al +; AVX512-NEXT: leal (%rcx,%rcx), %edx +; AVX512-NEXT: andb $4, %dl +; AVX512-NEXT: leal (,%rcx,8), %esi +; AVX512-NEXT: andb $8, %sil +; AVX512-NEXT: orb %dl, %sil +; AVX512-NEXT: shrb %cl +; AVX512-NEXT: andb $2, %cl +; AVX512-NEXT: orb %sil, %cl +; AVX512-NEXT: shrb $3, %al +; AVX512-NEXT: orb %cl, %al +; AVX512-NEXT: retq + %cmp = icmp eq <4 x i32> %a0, %a1 + %mask = bitcast <4 x i1> %cmp to i4 + %rev = tail call i4 @llvm.bitreverse.i4(i4 %mask) + ret i4 %rev +} +declare i4 @llvm.bitreverse.i4(i4) + +define i8 @reverse_cmp_v8i1(<8 x i16> %a0, <8 x i16> %a1) { +; SSE-LABEL: reverse_cmp_v8i1: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE-NEXT: packsswb %xmm0, %xmm0 +; SSE-NEXT: pmovmskb %xmm0, %eax +; SSE-NEXT: rolb $4, %al +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: andb $51, %cl +; SSE-NEXT: shlb $2, %cl +; SSE-NEXT: shrb $2, %al +; SSE-NEXT: andb $51, %al +; SSE-NEXT: orb %cl, %al +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: andb $85, %cl +; SSE-NEXT: addb %cl, %cl +; SSE-NEXT: shrb %al +; SSE-NEXT: andb $85, %al +; SSE-NEXT: orb %cl, %al +; SSE-NEXT: # kill: def $al killed $al killed $eax +; SSE-NEXT: retq +; +; AVX2-LABEL: reverse_cmp_v8i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: vpmovmskb %xmm0, %eax +; AVX2-NEXT: rolb $4, %al +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andb $51, %cl +; AVX2-NEXT: shlb $2, %cl +; AVX2-NEXT: shrb $2, %al +; AVX2-NEXT: andb $51, %al +; AVX2-NEXT: orb %cl, %al +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andb $85, %cl +; AVX2-NEXT: addb %cl, %cl +; AVX2-NEXT: shrb %al +; AVX2-NEXT: andb $85, %al +; AVX2-NEXT: orb %cl, %al +; AVX2-NEXT: # kill: def $al killed $al killed $eax +; AVX2-NEXT: retq +; +; AVX512-LABEL: reverse_cmp_v8i1: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: rolb $4, %al +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andb $51, %cl +; AVX512-NEXT: shlb $2, %cl +; AVX512-NEXT: shrb $2, %al +; AVX512-NEXT: andb $51, %al +; AVX512-NEXT: orb %cl, %al +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andb $85, %cl +; AVX512-NEXT: addb %cl, %cl +; AVX512-NEXT: shrb %al +; AVX512-NEXT: andb $85, %al +; AVX512-NEXT: orb %cl, %al +; AVX512-NEXT: # kill: def $al killed $al killed $eax +; AVX512-NEXT: retq + %cmp = icmp eq <8 x i16> %a0, %a1 + %mask = bitcast <8 x i1> %cmp to i8 + %rev = tail call i8 @llvm.bitreverse.i8(i8 %mask) + ret i8 %rev +} +declare i8 @llvm.bitreverse.i8(i8) + +define i16 @reverse_cmp_v16i1(<16 x i8> %a0, <16 x i8> %a1) { +; SSE-LABEL: reverse_cmp_v16i1: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE-NEXT: pmovmskb %xmm0, %eax +; SSE-NEXT: rolw $8, %ax +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: andl $3855, %ecx # imm = 0xF0F +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: shrl $4, %eax +; SSE-NEXT: andl $3855, %eax # imm = 0xF0F +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: andl $13107, %ecx # imm = 0x3333 +; SSE-NEXT: shrl $2, %eax +; SSE-NEXT: andl $13107, %eax # imm = 0x3333 +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: andl $21845, %ecx # imm = 0x5555 +; SSE-NEXT: shrl %eax +; SSE-NEXT: andl $21845, %eax # imm = 0x5555 +; SSE-NEXT: leal (%rax,%rcx,2), %eax +; SSE-NEXT: # kill: def $ax killed $ax killed $eax +; SSE-NEXT: retq +; +; AVX2-LABEL: reverse_cmp_v16i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpmovmskb %xmm0, %eax +; AVX2-NEXT: rolw $8, %ax +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andl $3855, %ecx # imm = 0xF0F +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: shrl $4, %eax +; AVX2-NEXT: andl $3855, %eax # imm = 0xF0F +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andl $13107, %ecx # imm = 0x3333 +; AVX2-NEXT: shrl $2, %eax +; AVX2-NEXT: andl $13107, %eax # imm = 0x3333 +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andl $21845, %ecx # imm = 0x5555 +; AVX2-NEXT: shrl %eax +; AVX2-NEXT: andl $21845, %eax # imm = 0x5555 +; AVX2-NEXT: leal (%rax,%rcx,2), %eax +; AVX2-NEXT: # kill: def $ax killed $ax killed $eax +; AVX2-NEXT: retq +; +; AVX512-LABEL: reverse_cmp_v16i1: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: rolw $8, %ax +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andl $3855, %ecx # imm = 0xF0F +; AVX512-NEXT: shll $4, %ecx +; AVX512-NEXT: shrl $4, %eax +; AVX512-NEXT: andl $3855, %eax # imm = 0xF0F +; AVX512-NEXT: orl %ecx, %eax +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andl $13107, %ecx # imm = 0x3333 +; AVX512-NEXT: shrl $2, %eax +; AVX512-NEXT: andl $13107, %eax # imm = 0x3333 +; AVX512-NEXT: leal (%rax,%rcx,4), %eax +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andl $21845, %ecx # imm = 0x5555 +; AVX512-NEXT: shrl %eax +; AVX512-NEXT: andl $21845, %eax # imm = 0x5555 +; AVX512-NEXT: leal (%rax,%rcx,2), %eax +; AVX512-NEXT: # kill: def $ax killed $ax killed $eax +; AVX512-NEXT: retq + %cmp = icmp eq <16 x i8> %a0, %a1 + %mask = bitcast <16 x i1> %cmp to i16 + %rev = tail call i16 @llvm.bitreverse.i16(i16 %mask) + ret i16 %rev +} +declare i16 @llvm.bitreverse.i16(i16) + +define i32 @reverse_cmp_v32i1(<32 x i8> %a0, <32 x i8> %a1) { +; SSE-LABEL: reverse_cmp_v32i1: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqb %xmm2, %xmm0 +; SSE-NEXT: pmovmskb %xmm0, %eax +; SSE-NEXT: pcmpeqb %xmm3, %xmm1 +; SSE-NEXT: pmovmskb %xmm1, %ecx +; SSE-NEXT: shll $16, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: bswapl %ecx +; SSE-NEXT: movl %ecx, %eax +; SSE-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F +; SSE-NEXT: shll $4, %eax +; SSE-NEXT: shrl $4, %ecx +; SSE-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: movl %ecx, %eax +; SSE-NEXT: andl $858993459, %eax # imm = 0x33333333 +; SSE-NEXT: shrl $2, %ecx +; SSE-NEXT: andl $858993459, %ecx # imm = 0x33333333 +; SSE-NEXT: leal (%rcx,%rax,4), %eax +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: andl $1431655765, %ecx # imm = 0x55555555 +; SSE-NEXT: shrl %eax +; SSE-NEXT: andl $1431655765, %eax # imm = 0x55555555 +; SSE-NEXT: leal (%rax,%rcx,2), %eax +; SSE-NEXT: retq +; +; AVX2-LABEL: reverse_cmp_v32i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpmovmskb %ymm0, %eax +; AVX2-NEXT: bswapl %eax +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: shrl $4, %eax +; AVX2-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andl $858993459, %ecx # imm = 0x33333333 +; AVX2-NEXT: shrl $2, %eax +; AVX2-NEXT: andl $858993459, %eax # imm = 0x33333333 +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: movl %eax, %ecx +; AVX2-NEXT: andl $1431655765, %ecx # imm = 0x55555555 +; AVX2-NEXT: shrl %eax +; AVX2-NEXT: andl $1431655765, %eax # imm = 0x55555555 +; AVX2-NEXT: leal (%rax,%rcx,2), %eax +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: reverse_cmp_v32i1: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqb %ymm1, %ymm0, %k0 +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: bswapl %eax +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F +; AVX512-NEXT: shll $4, %ecx +; AVX512-NEXT: shrl $4, %eax +; AVX512-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F +; AVX512-NEXT: orl %ecx, %eax +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andl $858993459, %ecx # imm = 0x33333333 +; AVX512-NEXT: shrl $2, %eax +; AVX512-NEXT: andl $858993459, %eax # imm = 0x33333333 +; AVX512-NEXT: leal (%rax,%rcx,4), %eax +; AVX512-NEXT: movl %eax, %ecx +; AVX512-NEXT: andl $1431655765, %ecx # imm = 0x55555555 +; AVX512-NEXT: shrl %eax +; AVX512-NEXT: andl $1431655765, %eax # imm = 0x55555555 +; AVX512-NEXT: leal (%rax,%rcx,2), %eax +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %cmp = icmp eq <32 x i8> %a0, %a1 + %mask = bitcast <32 x i1> %cmp to i32 + %rev = tail call i32 @llvm.bitreverse.i32(i32 %mask) + ret i32 %rev +} +declare i32 @llvm.bitreverse.i32(i32) + +define i64 @reverse_cmp_v64i1(<64 x i8> %a0, <64 x i8> %a1) { +; SSE-LABEL: reverse_cmp_v64i1: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqb %xmm4, %xmm0 +; SSE-NEXT: pmovmskb %xmm0, %eax +; SSE-NEXT: pcmpeqb %xmm5, %xmm1 +; SSE-NEXT: pmovmskb %xmm1, %ecx +; SSE-NEXT: shll $16, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pcmpeqb %xmm6, %xmm2 +; SSE-NEXT: pmovmskb %xmm2, %eax +; SSE-NEXT: pcmpeqb %xmm7, %xmm3 +; SSE-NEXT: pmovmskb %xmm3, %edx +; SSE-NEXT: shll $16, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: shlq $32, %rdx +; SSE-NEXT: orq %rcx, %rdx +; SSE-NEXT: bswapq %rdx +; SSE-NEXT: movq %rdx, %rax +; SSE-NEXT: shrq $4, %rax +; SSE-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F +; SSE-NEXT: andq %rcx, %rax +; SSE-NEXT: andq %rcx, %rdx +; SSE-NEXT: shlq $4, %rdx +; SSE-NEXT: orq %rax, %rdx +; SSE-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 +; SSE-NEXT: movq %rdx, %rcx +; SSE-NEXT: andq %rax, %rcx +; SSE-NEXT: shrq $2, %rdx +; SSE-NEXT: andq %rax, %rdx +; SSE-NEXT: leaq (%rdx,%rcx,4), %rax +; SSE-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 +; SSE-NEXT: movq %rax, %rdx +; SSE-NEXT: andq %rcx, %rdx +; SSE-NEXT: shrq %rax +; SSE-NEXT: andq %rcx, %rax +; SSE-NEXT: leaq (%rax,%rdx,2), %rax +; SSE-NEXT: retq +; +; AVX2-LABEL: reverse_cmp_v64i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpmovmskb %ymm0, %eax +; AVX2-NEXT: vpcmpeqb %ymm3, %ymm1, %ymm0 +; AVX2-NEXT: vpmovmskb %ymm0, %ecx +; AVX2-NEXT: shlq $32, %rcx +; AVX2-NEXT: orq %rax, %rcx +; AVX2-NEXT: bswapq %rcx +; AVX2-NEXT: movq %rcx, %rax +; AVX2-NEXT: shrq $4, %rax +; AVX2-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F +; AVX2-NEXT: andq %rdx, %rax +; AVX2-NEXT: andq %rdx, %rcx +; AVX2-NEXT: shlq $4, %rcx +; AVX2-NEXT: orq %rax, %rcx +; AVX2-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 +; AVX2-NEXT: movq %rcx, %rdx +; AVX2-NEXT: andq %rax, %rdx +; AVX2-NEXT: shrq $2, %rcx +; AVX2-NEXT: andq %rax, %rcx +; AVX2-NEXT: leaq (%rcx,%rdx,4), %rax +; AVX2-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 +; AVX2-NEXT: movq %rax, %rdx +; AVX2-NEXT: andq %rcx, %rdx +; AVX2-NEXT: shrq %rax +; AVX2-NEXT: andq %rcx, %rax +; AVX2-NEXT: leaq (%rax,%rdx,2), %rax +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: reverse_cmp_v64i1: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 +; AVX512-NEXT: kmovq %k0, %rax +; AVX512-NEXT: bswapq %rax +; AVX512-NEXT: movq %rax, %rcx +; AVX512-NEXT: shrq $4, %rcx +; AVX512-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F +; AVX512-NEXT: andq %rdx, %rcx +; AVX512-NEXT: andq %rdx, %rax +; AVX512-NEXT: shlq $4, %rax +; AVX512-NEXT: orq %rcx, %rax +; AVX512-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333 +; AVX512-NEXT: movq %rax, %rdx +; AVX512-NEXT: andq %rcx, %rdx +; AVX512-NEXT: shrq $2, %rax +; AVX512-NEXT: andq %rcx, %rax +; AVX512-NEXT: leaq (%rax,%rdx,4), %rax +; AVX512-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 +; AVX512-NEXT: movq %rax, %rdx +; AVX512-NEXT: andq %rcx, %rdx +; AVX512-NEXT: shrq %rax +; AVX512-NEXT: andq %rcx, %rax +; AVX512-NEXT: leaq (%rax,%rdx,2), %rax +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %cmp = icmp eq <64 x i8> %a0, %a1 + %mask = bitcast <64 x i1> %cmp to i64 + %rev = tail call i64 @llvm.bitreverse.i64(i64 %mask) + ret i64 %rev +} +declare i64 @llvm.bitreverse.i64(i64) + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; SSE2: {{.*}} +; SSE42: {{.*}} -- GitLab From a50ea2f76f993f65c8756067f7ad5a21e560b0c9 Mon Sep 17 00:00:00 2001 From: Nicholas Mosier Date: Tue, 9 Jan 2024 10:58:47 -0800 Subject: [PATCH 245/652] [lldb] Fix Intel PT plugin compile errors (#77252) Fix #77251. --- .../CommandObjectTraceStartIntelPT.cpp | 4 +-- .../Plugins/Trace/intel-pt/DecodedThread.cpp | 32 +++++++++++-------- .../Plugins/Trace/intel-pt/DecodedThread.h | 26 +++++---------- .../Plugins/Trace/intel-pt/LibiptDecoder.cpp | 4 +-- .../Trace/intel-pt/TraceCursorIntelPT.cpp | 4 +-- .../intel-pt/TraceIntelPTBundleLoader.cpp | 13 ++++---- lldb/source/Target/ProcessTrace.cpp | 2 ++ .../API/commands/trace/TestTraceDumpInfo.py | 15 ++------- lldb/test/API/commands/trace/TestTraceLoad.py | 20 ++++-------- 9 files changed, 49 insertions(+), 71 deletions(-) diff --git a/lldb/source/Plugins/Trace/intel-pt/CommandObjectTraceStartIntelPT.cpp b/lldb/source/Plugins/Trace/intel-pt/CommandObjectTraceStartIntelPT.cpp index d4f7dc354e9f..44224229e625 100644 --- a/lldb/source/Plugins/Trace/intel-pt/CommandObjectTraceStartIntelPT.cpp +++ b/lldb/source/Plugins/Trace/intel-pt/CommandObjectTraceStartIntelPT.cpp @@ -158,7 +158,7 @@ CommandObjectProcessTraceStartIntelPT::CommandOptions::GetDefinitions() { return llvm::ArrayRef(g_process_trace_start_intel_pt_options); } -bool CommandObjectProcessTraceStartIntelPT::DoExecute( +void CommandObjectProcessTraceStartIntelPT::DoExecute( Args &command, CommandReturnObject &result) { if (Error err = m_trace.Start( m_options.m_ipt_trace_size, m_options.m_process_buffer_size_limit, @@ -167,8 +167,6 @@ bool CommandObjectProcessTraceStartIntelPT::DoExecute( result.SetError(Status(std::move(err))); else result.SetStatus(eReturnStatusSuccessFinishResult); - - return result.Succeeded(); } std::optional diff --git a/lldb/source/Plugins/Trace/intel-pt/DecodedThread.cpp b/lldb/source/Plugins/Trace/intel-pt/DecodedThread.cpp index 17f8f51bdf0e..9c075398d547 100644 --- a/lldb/source/Plugins/Trace/intel-pt/DecodedThread.cpp +++ b/lldb/source/Plugins/Trace/intel-pt/DecodedThread.cpp @@ -85,11 +85,11 @@ double DecodedThread::NanosecondsRange::GetInterpolatedTime( return interpolate(next_range->nanos); } -uint64_t DecodedThread::GetItemsCount() const { return m_item_kinds.size(); } +uint64_t DecodedThread::GetItemsCount() const { return m_item_data.size(); } lldb::addr_t DecodedThread::GetInstructionLoadAddress(uint64_t item_index) const { - return m_item_data[item_index].load_address; + return std::get(m_item_data[item_index]); } lldb::addr_t @@ -99,14 +99,16 @@ DecodedThread::GetSyncPointOffsetByIndex(uint64_t item_index) const { ThreadSP DecodedThread::GetThread() { return m_thread_sp; } +template DecodedThread::TraceItemStorage & -DecodedThread::CreateNewTraceItem(lldb::TraceItemKind kind) { - m_item_kinds.push_back(kind); - m_item_data.emplace_back(); +DecodedThread::CreateNewTraceItem(lldb::TraceItemKind kind, Data &&data) { + m_item_data.emplace_back(data); + if (m_last_tsc) (*m_last_tsc)->second.items_count++; if (m_last_nanoseconds) (*m_last_nanoseconds)->second.items_count++; + return m_item_data.back(); } @@ -176,27 +178,27 @@ uint64_t DecodedThread::GetTotalInstructionCount() const { } void DecodedThread::AppendEvent(lldb::TraceEvent event) { - CreateNewTraceItem(lldb::eTraceItemKindEvent).event = event; + CreateNewTraceItem(lldb::eTraceItemKindEvent, event); m_events_stats.RecordEvent(event); } void DecodedThread::AppendInstruction(const pt_insn &insn) { - CreateNewTraceItem(lldb::eTraceItemKindInstruction).load_address = insn.ip; + CreateNewTraceItem(lldb::eTraceItemKindInstruction, insn.ip); m_insn_count++; } void DecodedThread::AppendError(const IntelPTError &error) { - CreateNewTraceItem(lldb::eTraceItemKindError).error = error.message(); + CreateNewTraceItem(lldb::eTraceItemKindError, error.message()); m_error_stats.RecordError(/*fatal=*/false); } void DecodedThread::AppendCustomError(StringRef err, bool fatal) { - CreateNewTraceItem(lldb::eTraceItemKindError).error = err.str(); + CreateNewTraceItem(lldb::eTraceItemKindError, err.str()); m_error_stats.RecordError(fatal); } lldb::TraceEvent DecodedThread::GetEventByIndex(int item_index) const { - return m_item_data[item_index].event; + return std::get(m_item_data[item_index]); } const DecodedThread::EventsStats &DecodedThread::GetEventsStats() const { @@ -233,13 +235,18 @@ const DecodedThread::ErrorStats &DecodedThread::GetErrorStats() const { lldb::TraceItemKind DecodedThread::GetItemKindByIndex(uint64_t item_index) const { - return static_cast(m_item_kinds[item_index]); + return std::visit( + llvm::makeVisitor( + [](const std::string &) { return lldb::eTraceItemKindError; }, + [](lldb::TraceEvent) { return lldb::eTraceItemKindEvent; }, + [](lldb::addr_t) { return lldb::eTraceItemKindInstruction; }), + m_item_data[item_index]); } llvm::StringRef DecodedThread::GetErrorByIndex(uint64_t item_index) const { if (item_index >= m_item_data.size()) return llvm::StringRef(); - return m_item_data[item_index].error; + return std::get(m_item_data[item_index]); } DecodedThread::DecodedThread( @@ -249,7 +256,6 @@ DecodedThread::DecodedThread( size_t DecodedThread::CalculateApproximateMemoryUsage() const { return sizeof(TraceItemStorage) * m_item_data.size() + - sizeof(uint8_t) * m_item_kinds.size() + (sizeof(uint64_t) + sizeof(TSC)) * m_tscs.size() + (sizeof(uint64_t) + sizeof(uint64_t)) * m_nanoseconds.size() + (sizeof(uint64_t) + sizeof(lldb::cpu_id_t)) * m_cpus.size(); diff --git a/lldb/source/Plugins/Trace/intel-pt/DecodedThread.h b/lldb/source/Plugins/Trace/intel-pt/DecodedThread.h index 5745cdb67ab6..a48c55cc76df 100644 --- a/lldb/source/Plugins/Trace/intel-pt/DecodedThread.h +++ b/lldb/source/Plugins/Trace/intel-pt/DecodedThread.h @@ -14,9 +14,10 @@ #include "lldb/Utility/TraceIntelPTGDBRemotePackets.h" #include "llvm/Support/Errc.h" #include "llvm/Support/Error.h" +#include #include #include -#include +#include namespace lldb_private { namespace trace_intel_pt { @@ -265,30 +266,19 @@ private: /// to update \a CalculateApproximateMemoryUsage() accordingly. lldb::ThreadSP m_thread_sp; - /// We use a union to optimize the memory usage for the different kinds of - /// trace items. - union TraceItemStorage { - /// The load addresses of this item if it's an instruction. - uint64_t load_address; - - /// The event kind of this item if it's an event - lldb::TraceEvent event; - - /// The string message of this item if it's an error - std::string error; - }; + using TraceItemStorage = + std::variant; /// Create a new trace item. /// /// \return /// The index of the new item. - DecodedThread::TraceItemStorage &CreateNewTraceItem(lldb::TraceItemKind kind); + template + DecodedThread::TraceItemStorage &CreateNewTraceItem(lldb::TraceItemKind kind, + Data &&data); /// Most of the trace data is stored here. - std::vector m_item_data; - /// The TraceItemKind for each trace item encoded as uint8_t. We don't include - /// it in TraceItemStorage to avoid padding. - std::vector m_item_kinds; + std::deque m_item_data; /// This map contains the TSCs of the decoded trace items. It maps /// `item index -> TSC`, where `item index` is the first index diff --git a/lldb/source/Plugins/Trace/intel-pt/LibiptDecoder.cpp b/lldb/source/Plugins/Trace/intel-pt/LibiptDecoder.cpp index cdf81954eee9..f8241ef6a793 100644 --- a/lldb/source/Plugins/Trace/intel-pt/LibiptDecoder.cpp +++ b/lldb/source/Plugins/Trace/intel-pt/LibiptDecoder.cpp @@ -572,7 +572,7 @@ Error lldb_private::trace_intel_pt::DecodeSingleTraceForThread( Expected decoder = PSBBlockDecoder::Create( trace_intel_pt, block, buffer.slice(block.psb_offset, block.size), *decoded_thread.GetThread()->GetProcess(), - i + 1 < blocks->size() ? blocks->at(i + 1).starting_ip : None, + i + 1 < blocks->size() ? blocks->at(i + 1).starting_ip : std::nullopt, decoded_thread, std::nullopt); if (!decoder) return decoder.takeError(); @@ -640,7 +640,7 @@ Error lldb_private::trace_intel_pt::DecodeSystemWideTraceForThread( *decoded_thread.GetThread()->GetProcess(), j + 1 < execution.psb_blocks.size() ? execution.psb_blocks[j + 1].starting_ip - : None, + : std::nullopt, decoded_thread, execution.thread_execution.GetEndTSC()); if (!decoder) return decoder.takeError(); diff --git a/lldb/source/Plugins/Trace/intel-pt/TraceCursorIntelPT.cpp b/lldb/source/Plugins/Trace/intel-pt/TraceCursorIntelPT.cpp index 66d342196cf1..dda6cd74343f 100644 --- a/lldb/source/Plugins/Trace/intel-pt/TraceCursorIntelPT.cpp +++ b/lldb/source/Plugins/Trace/intel-pt/TraceCursorIntelPT.cpp @@ -35,7 +35,7 @@ void TraceCursorIntelPT::Next() { void TraceCursorIntelPT::ClearTimingRangesIfInvalid() { if (m_tsc_range_calculated) { if (!m_tsc_range || m_pos < 0 || !m_tsc_range->InRange(m_pos)) { - m_tsc_range = None; + m_tsc_range = std::nullopt; m_tsc_range_calculated = false; } } @@ -43,7 +43,7 @@ void TraceCursorIntelPT::ClearTimingRangesIfInvalid() { if (m_nanoseconds_range_calculated) { if (!m_nanoseconds_range || m_pos < 0 || !m_nanoseconds_range->InRange(m_pos)) { - m_nanoseconds_range = None; + m_nanoseconds_range = std::nullopt; m_nanoseconds_range_calculated = false; } } diff --git a/lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp b/lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp index bd9cca675f2d..1a9f6fe30509 100644 --- a/lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp +++ b/lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp @@ -15,6 +15,7 @@ #include "lldb/Core/Debugger.h" #include "lldb/Core/Module.h" #include "lldb/Target/Process.h" +#include "lldb/Target/ProcessTrace.h" #include "lldb/Target/Target.h" #include @@ -103,11 +104,11 @@ TraceIntelPTBundleLoader::CreateEmptyProcess(lldb::pid_t pid, ParsedProcess parsed_process; parsed_process.target_sp = target_sp; - // This should instead try to directly create an instance of ProcessTrace. - // ProcessSP process_sp = target_sp->CreateProcess( - // /*listener*/ nullptr, "trace", - // /*crash_file*/ nullptr, - // /*can_connect*/ false); + ProcessTrace::Initialize(); + ProcessSP process_sp = target_sp->CreateProcess( + /*listener*/ nullptr, "trace", + /*crash_file*/ nullptr, + /*can_connect*/ false); process_sp->SetID(static_cast(pid)); @@ -344,7 +345,7 @@ Error TraceIntelPTBundleLoader::AugmentThreadsFromContextSwitches( if (indexed_threads[proc->second].count(tid)) return; indexed_threads[proc->second].insert(tid); - proc->second->threads.push_back({tid, /*ipt_trace=*/None}); + proc->second->threads.push_back({tid, /*ipt_trace=*/std::nullopt}); }; for (const JSONCpu &cpu : *bundle_description.cpus) { diff --git a/lldb/source/Target/ProcessTrace.cpp b/lldb/source/Target/ProcessTrace.cpp index 6e5ef6a379f9..054e34a46de2 100644 --- a/lldb/source/Target/ProcessTrace.cpp +++ b/lldb/source/Target/ProcessTrace.cpp @@ -20,6 +20,8 @@ using namespace lldb; using namespace lldb_private; +LLDB_PLUGIN_DEFINE(ProcessTrace); + llvm::StringRef ProcessTrace::GetPluginDescriptionStatic() { return "Trace process plug-in."; } diff --git a/lldb/test/API/commands/trace/TestTraceDumpInfo.py b/lldb/test/API/commands/trace/TestTraceDumpInfo.py index 120ab92bf0e0..3f67475d631d 100644 --- a/lldb/test/API/commands/trace/TestTraceDumpInfo.py +++ b/lldb/test/API/commands/trace/TestTraceDumpInfo.py @@ -55,12 +55,7 @@ class TestTraceDumpInfo(TraceIntelPTTestCaseBase): Total number of trace items: 28 Memory usage: - Raw trace size: 4 KiB - Total approximate memory usage (excluding raw trace): 0.25 KiB - Average memory usage per item (excluding raw trace): 9.00 bytes - - Timing for this thread: - Decoding instructions: """, + Raw trace size: 4 KiB""", """ Events: @@ -86,13 +81,7 @@ class TestTraceDumpInfo(TraceIntelPTTestCaseBase): "traceTechnology": "intel-pt", "threadStats": { "tid": 3842849, - "traceItemsCount": 28, - "memoryUsage": { - "totalInBytes": "252", - "avgPerItemInBytes": 9 - }, - "timingInSeconds": { - "Decoding instructions": 0""", + "traceItemsCount": 28,""", """ }, "events": { diff --git a/lldb/test/API/commands/trace/TestTraceLoad.py b/lldb/test/API/commands/trace/TestTraceLoad.py index 3a34b2a4bc4d..db524933b257 100644 --- a/lldb/test/API/commands/trace/TestTraceLoad.py +++ b/lldb/test/API/commands/trace/TestTraceLoad.py @@ -82,10 +82,7 @@ class TestTraceLoad(TraceIntelPTTestCaseBase): "traceTechnology": "intel-pt", "threadStats": { "tid": 3497496, - "traceItemsCount": 19527, - "memoryUsage": { - "totalInBytes": "175819", - "avgPerItemInBytes": 9.0038920469094084""", + "traceItemsCount": 19527,""", """}, "timingInSeconds": { "Decoding instructions": """, @@ -158,7 +155,7 @@ class TestTraceLoad(TraceIntelPTTestCaseBase): self.expect( "thread trace dump instructions 2 -t", substrs=[ - "19526: [19691636.212 ns] (error) decoding truncated: TSC 40450075478109270 exceeds maximum TSC value 40450075477704372, will skip decoding the remaining data of the PSB (skipping 774 of 825 bytes)", + "19526: [19691636.212 ns] (error)", "m.out`foo() + 65 at multi_thread.cpp:12:21", "19524: [19691632.221 ns] 0x0000000000400ba7 jg 0x400bb3", ], @@ -166,7 +163,7 @@ class TestTraceLoad(TraceIntelPTTestCaseBase): self.expect( "thread trace dump instructions 3 -t", substrs=[ - "61833: [19736136.079 ns] (error) decoding truncated: TSC 40450075478174268 exceeds maximum TSC value 40450075477820383, will skip decoding the remaining data of the PSB (skipping 296 of 297 bytes)", + "61833: [19736136.079 ns] (error)", "61831: [19736132.088 ns] 0x0000000000400bd7 addl $0x1, -0x4(%rbp)", "m.out`bar() + 26 at multi_thread.cpp:20:6", ], @@ -193,7 +190,7 @@ class TestTraceLoad(TraceIntelPTTestCaseBase): self.expect( "thread trace dump instructions 2 -t", substrs=[ - "19526: [19691636.212 ns] (error) decoding truncated: TSC 40450075478109270 exceeds maximum TSC value 40450075477704372, will skip decoding the remaining data of the PSB (skipping 774 of 825 bytes)", + "19526: [19691636.212 ns] (error)", "m.out`foo() + 65 at multi_thread.cpp:12:21", "19524: [19691632.221 ns] 0x0000000000400ba7 jg 0x400bb3", ], @@ -218,7 +215,7 @@ class TestTraceLoad(TraceIntelPTTestCaseBase): self.expect( "thread trace dump instructions 3 -t", substrs=[ - "19526: [19691636.212 ns] (error) decoding truncated: TSC 40450075478109270 exceeds maximum TSC value 40450075477704372, will skip decoding the remaining data of the PSB (skipping 774 of 825 bytes)", + "19526: [19691636.212 ns] (error)", "m.out`foo() + 65 at multi_thread.cpp:12:21", "19524: [19691632.221 ns] 0x0000000000400ba7 jg 0x400bb3", ], @@ -272,12 +269,7 @@ class TestTraceLoad(TraceIntelPTTestCaseBase): Total number of trace items: 28 Memory usage: - Raw trace size: 4 KiB - Total approximate memory usage (excluding raw trace): 0.25 KiB - Average memory usage per item (excluding raw trace): 9.00 bytes - - Timing for this thread: - Decoding instructions: """, + Raw trace size: 4 KiB""", """ Events: -- GitLab From 0ab5d8ba023f920e03dcd328f62c4df1855af374 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Jan 2024 10:59:48 -0800 Subject: [PATCH 246/652] [ELF,test] Set alignment of SHT_GROUP to 4 Fixes: 0930f62cf600d9e2e9a45fef1b3a422d50be89d5 This makes the test more conforming and fixes a -fsanitize=alignment failure in finalizeShtGroup. --- lld/test/ELF/linkorder-group.test | 1 + 1 file changed, 1 insertion(+) diff --git a/lld/test/ELF/linkorder-group.test b/lld/test/ELF/linkorder-group.test index 988f793cf632..0d25413868b3 100644 --- a/lld/test/ELF/linkorder-group.test +++ b/lld/test/ELF/linkorder-group.test @@ -31,6 +31,7 @@ Sections: Type: SHT_GROUP Link: .symtab Info: foo + AddressAlign: 4 Members: - SectionOrType: GRP_COMDAT - SectionOrType: .bss -- GitLab From 144ae5b271f7026dec51617c667047a9641fd9e0 Mon Sep 17 00:00:00 2001 From: madanial0 <118996571+madanial0@users.noreply.github.com> Date: Tue, 9 Jan 2024 14:06:12 -0500 Subject: [PATCH 247/652] [Flang] Xfail hlfir test case on AIX (#76802) This test case seems to fail at the `Merge disjoint stack slots` pass on AIX, it passes if compilled with `-mllvm --no-stack-coloring`. This PR xfails the teest case on AIX temporarily until the issue is addressed. --------- Co-authored-by: Mark Danial --- flang/test/HLFIR/simplify-hlfir-intrinsics.fir | 3 +++ 1 file changed, 3 insertions(+) diff --git a/flang/test/HLFIR/simplify-hlfir-intrinsics.fir b/flang/test/HLFIR/simplify-hlfir-intrinsics.fir index aeea8bfc9732..b63ddf175152 100644 --- a/flang/test/HLFIR/simplify-hlfir-intrinsics.fir +++ b/flang/test/HLFIR/simplify-hlfir-intrinsics.fir @@ -1,3 +1,6 @@ +// XFail the following test case on AIX due to potential miscompilation +// TODO: Crash fir-opt on AIX +// XFAIL: system-aix // RUN: fir-opt --simplify-hlfir-intrinsics %s | FileCheck %s // box with known extents -- GitLab From 3210ce276350a247220b193db12a9b45d1034724 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Jan 2024 19:05:15 +0000 Subject: [PATCH 248/652] [X86] Fold (iX bitreverse(bitcast(vXi1 X))) -> (iX bitcast(shuffle(X))) X86 doesn't have a BITREVERSE instruction, so if we're working with a casted boolean vector, we're better off shuffling the vector instead if we have PSHUFB (SSSE3 or later) Fixes #77459 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 29 ++ llvm/test/CodeGen/X86/pr77459.ll | 519 ++++++++++-------------- 2 files changed, 245 insertions(+), 303 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 25c4e02abc2e..6da137426c56 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2444,6 +2444,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, ISD::SRL, ISD::OR, ISD::AND, + ISD::BITREVERSE, ISD::ADD, ISD::FADD, ISD::FSUB, @@ -51835,6 +51836,33 @@ static SDValue combineXor(SDNode *N, SelectionDAG &DAG, return combineFneg(N, DAG, DCI, Subtarget); } +static SDValue combineBITREVERSE(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const X86Subtarget &Subtarget) { + SDValue N0 = N->getOperand(0); + EVT VT = N->getValueType(0); + + // Convert a (iX bitreverse(bitcast(vXi1 X))) -> (iX bitcast(shuffle(X))) + if (VT.isInteger() && N0.getOpcode() == ISD::BITCAST && N0.hasOneUse()) { + SDValue Src = N0.getOperand(0); + EVT SrcVT = Src.getValueType(); + if (SrcVT.isVector() && SrcVT.getScalarType() == MVT::i1 && + (DCI.isBeforeLegalize() || + DAG.getTargetLoweringInfo().isTypeLegal(SrcVT)) && + Subtarget.hasSSSE3()) { + unsigned NumElts = SrcVT.getVectorNumElements(); + SmallVector ReverseMask(NumElts); + for (unsigned I = 0; I != NumElts; ++I) + ReverseMask[I] = (NumElts - 1) - I; + SDValue Rev = + DAG.getVectorShuffle(SrcVT, SDLoc(N), Src, Src, ReverseMask); + return DAG.getBitcast(VT, Rev); + } + } + + return SDValue(); +} + static SDValue combineBEXTR(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { @@ -56124,6 +56152,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, case ISD::AND: return combineAnd(N, DAG, DCI, Subtarget); case ISD::OR: return combineOr(N, DAG, DCI, Subtarget); case ISD::XOR: return combineXor(N, DAG, DCI, Subtarget); + case ISD::BITREVERSE: return combineBITREVERSE(N, DAG, DCI, Subtarget); case X86ISD::BEXTR: case X86ISD::BEXTRI: return combineBEXTR(N, DAG, DCI, Subtarget); case ISD::LOAD: return combineLoad(N, DAG, DCI, Subtarget); diff --git a/llvm/test/CodeGen/X86/pr77459.ll b/llvm/test/CodeGen/X86/pr77459.ll index a16990a6ac31..c6736f4d3398 100644 --- a/llvm/test/CodeGen/X86/pr77459.ll +++ b/llvm/test/CodeGen/X86/pr77459.ll @@ -6,58 +6,48 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 -mattr=+avx512vbmi | FileCheck %s --check-prefixes=AVX512 define i4 @reverse_cmp_v4i1(<4 x i32> %a0, <4 x i32> %a1) { -; SSE-LABEL: reverse_cmp_v4i1: -; SSE: # %bb.0: -; SSE-NEXT: pcmpeqd %xmm1, %xmm0 -; SSE-NEXT: movmskps %xmm0, %eax -; SSE-NEXT: leal (%rax,%rax), %ecx -; SSE-NEXT: andb $4, %cl -; SSE-NEXT: leal (,%rax,8), %edx -; SSE-NEXT: andb $8, %dl -; SSE-NEXT: orb %cl, %dl -; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: shrb %cl -; SSE-NEXT: andb $2, %cl -; SSE-NEXT: orb %dl, %cl -; SSE-NEXT: shrb $3, %al -; SSE-NEXT: orb %cl, %al -; SSE-NEXT: # kill: def $al killed $al killed $rax -; SSE-NEXT: retq +; SSE2-LABEL: reverse_cmp_v4i1: +; SSE2: # %bb.0: +; SSE2-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE2-NEXT: movmskps %xmm0, %eax +; SSE2-NEXT: leal (%rax,%rax), %ecx +; SSE2-NEXT: andb $4, %cl +; SSE2-NEXT: leal (,%rax,8), %edx +; SSE2-NEXT: andb $8, %dl +; SSE2-NEXT: orb %cl, %dl +; SSE2-NEXT: movl %eax, %ecx +; SSE2-NEXT: shrb %cl +; SSE2-NEXT: andb $2, %cl +; SSE2-NEXT: orb %dl, %cl +; SSE2-NEXT: shrb $3, %al +; SSE2-NEXT: orb %cl, %al +; SSE2-NEXT: # kill: def $al killed $al killed $rax +; SSE2-NEXT: retq +; +; SSE42-LABEL: reverse_cmp_v4i1: +; SSE42: # %bb.0: +; SSE42-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] +; SSE42-NEXT: movmskps %xmm0, %eax +; SSE42-NEXT: # kill: def $al killed $al killed $eax +; SSE42-NEXT: retq ; ; AVX2-LABEL: reverse_cmp_v4i1: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] ; AVX2-NEXT: vmovmskps %xmm0, %eax -; AVX2-NEXT: leal (%rax,%rax), %ecx -; AVX2-NEXT: andb $4, %cl -; AVX2-NEXT: leal (,%rax,8), %edx -; AVX2-NEXT: andb $8, %dl -; AVX2-NEXT: orb %cl, %dl -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: shrb %cl -; AVX2-NEXT: andb $2, %cl -; AVX2-NEXT: orb %dl, %cl -; AVX2-NEXT: shrb $3, %al -; AVX2-NEXT: orb %cl, %al -; AVX2-NEXT: # kill: def $al killed $al killed $rax +; AVX2-NEXT: # kill: def $al killed $al killed $eax ; AVX2-NEXT: retq ; ; AVX512-LABEL: reverse_cmp_v4i1: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 -; AVX512-NEXT: kmovd %k0, %ecx -; AVX512-NEXT: movl %ecx, %eax -; AVX512-NEXT: andb $8, %al -; AVX512-NEXT: leal (%rcx,%rcx), %edx -; AVX512-NEXT: andb $4, %dl -; AVX512-NEXT: leal (,%rcx,8), %esi -; AVX512-NEXT: andb $8, %sil -; AVX512-NEXT: orb %dl, %sil -; AVX512-NEXT: shrb %cl -; AVX512-NEXT: andb $2, %cl -; AVX512-NEXT: orb %sil, %cl -; AVX512-NEXT: shrb $3, %al -; AVX512-NEXT: orb %cl, %al +; AVX512-NEXT: vpmovm2d %k0, %xmm0 +; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] +; AVX512-NEXT: vpmovd2m %xmm0, %k0 +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: # kill: def $al killed $al killed $eax ; AVX512-NEXT: retq %cmp = icmp eq <4 x i32> %a0, %a1 %mask = bitcast <4 x i1> %cmp to i4 @@ -67,66 +57,54 @@ define i4 @reverse_cmp_v4i1(<4 x i32> %a0, <4 x i32> %a1) { declare i4 @llvm.bitreverse.i4(i4) define i8 @reverse_cmp_v8i1(<8 x i16> %a0, <8 x i16> %a1) { -; SSE-LABEL: reverse_cmp_v8i1: -; SSE: # %bb.0: -; SSE-NEXT: pcmpeqw %xmm1, %xmm0 -; SSE-NEXT: packsswb %xmm0, %xmm0 -; SSE-NEXT: pmovmskb %xmm0, %eax -; SSE-NEXT: rolb $4, %al -; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: andb $51, %cl -; SSE-NEXT: shlb $2, %cl -; SSE-NEXT: shrb $2, %al -; SSE-NEXT: andb $51, %al -; SSE-NEXT: orb %cl, %al -; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: andb $85, %cl -; SSE-NEXT: addb %cl, %cl -; SSE-NEXT: shrb %al -; SSE-NEXT: andb $85, %al -; SSE-NEXT: orb %cl, %al -; SSE-NEXT: # kill: def $al killed $al killed $eax -; SSE-NEXT: retq +; SSE2-LABEL: reverse_cmp_v8i1: +; SSE2: # %bb.0: +; SSE2-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE2-NEXT: packsswb %xmm0, %xmm0 +; SSE2-NEXT: pmovmskb %xmm0, %eax +; SSE2-NEXT: rolb $4, %al +; SSE2-NEXT: movl %eax, %ecx +; SSE2-NEXT: andb $51, %cl +; SSE2-NEXT: shlb $2, %cl +; SSE2-NEXT: shrb $2, %al +; SSE2-NEXT: andb $51, %al +; SSE2-NEXT: orb %cl, %al +; SSE2-NEXT: movl %eax, %ecx +; SSE2-NEXT: andb $85, %cl +; SSE2-NEXT: addb %cl, %cl +; SSE2-NEXT: shrb %al +; SSE2-NEXT: andb $85, %al +; SSE2-NEXT: orb %cl, %al +; SSE2-NEXT: # kill: def $al killed $al killed $eax +; SSE2-NEXT: retq +; +; SSE42-LABEL: reverse_cmp_v8i1: +; SSE42: # %bb.0: +; SSE42-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[u,15,u,13,u,11,u,9,u,7,u,5,u,3,u,1] +; SSE42-NEXT: packsswb %xmm0, %xmm0 +; SSE42-NEXT: pmovmskb %xmm0, %eax +; SSE42-NEXT: # kill: def $al killed $al killed $eax +; SSE42-NEXT: retq ; ; AVX2-LABEL: reverse_cmp_v8i1: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[14,12,10,8,6,4,2,0,u,u,u,u,u,u,u,u] ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: rolb $4, %al -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andb $51, %cl -; AVX2-NEXT: shlb $2, %cl -; AVX2-NEXT: shrb $2, %al -; AVX2-NEXT: andb $51, %al -; AVX2-NEXT: orb %cl, %al -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andb $85, %cl -; AVX2-NEXT: addb %cl, %cl -; AVX2-NEXT: shrb %al -; AVX2-NEXT: andb $85, %al -; AVX2-NEXT: orb %cl, %al ; AVX2-NEXT: # kill: def $al killed $al killed $eax ; AVX2-NEXT: retq ; ; AVX512-LABEL: reverse_cmp_v8i1: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 +; AVX512-NEXT: vpmovm2d %k0, %ymm0 +; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,3,2,1,0] +; AVX512-NEXT: vpermd %ymm0, %ymm1, %ymm0 +; AVX512-NEXT: vpmovd2m %ymm0, %k0 ; AVX512-NEXT: kmovd %k0, %eax -; AVX512-NEXT: rolb $4, %al -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andb $51, %cl -; AVX512-NEXT: shlb $2, %cl -; AVX512-NEXT: shrb $2, %al -; AVX512-NEXT: andb $51, %al -; AVX512-NEXT: orb %cl, %al -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andb $85, %cl -; AVX512-NEXT: addb %cl, %cl -; AVX512-NEXT: shrb %al -; AVX512-NEXT: andb $85, %al -; AVX512-NEXT: orb %cl, %al ; AVX512-NEXT: # kill: def $al killed $al killed $eax +; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cmp = icmp eq <8 x i16> %a0, %a1 %mask = bitcast <8 x i1> %cmp to i8 @@ -136,76 +114,56 @@ define i8 @reverse_cmp_v8i1(<8 x i16> %a0, <8 x i16> %a1) { declare i8 @llvm.bitreverse.i8(i8) define i16 @reverse_cmp_v16i1(<16 x i8> %a0, <16 x i8> %a1) { -; SSE-LABEL: reverse_cmp_v16i1: -; SSE: # %bb.0: -; SSE-NEXT: pcmpeqb %xmm1, %xmm0 -; SSE-NEXT: pmovmskb %xmm0, %eax -; SSE-NEXT: rolw $8, %ax -; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: andl $3855, %ecx # imm = 0xF0F -; SSE-NEXT: shll $4, %ecx -; SSE-NEXT: shrl $4, %eax -; SSE-NEXT: andl $3855, %eax # imm = 0xF0F -; SSE-NEXT: orl %ecx, %eax -; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: andl $13107, %ecx # imm = 0x3333 -; SSE-NEXT: shrl $2, %eax -; SSE-NEXT: andl $13107, %eax # imm = 0x3333 -; SSE-NEXT: leal (%rax,%rcx,4), %eax -; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: andl $21845, %ecx # imm = 0x5555 -; SSE-NEXT: shrl %eax -; SSE-NEXT: andl $21845, %eax # imm = 0x5555 -; SSE-NEXT: leal (%rax,%rcx,2), %eax -; SSE-NEXT: # kill: def $ax killed $ax killed $eax -; SSE-NEXT: retq +; SSE2-LABEL: reverse_cmp_v16i1: +; SSE2: # %bb.0: +; SSE2-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE2-NEXT: pmovmskb %xmm0, %eax +; SSE2-NEXT: rolw $8, %ax +; SSE2-NEXT: movl %eax, %ecx +; SSE2-NEXT: andl $3855, %ecx # imm = 0xF0F +; SSE2-NEXT: shll $4, %ecx +; SSE2-NEXT: shrl $4, %eax +; SSE2-NEXT: andl $3855, %eax # imm = 0xF0F +; SSE2-NEXT: orl %ecx, %eax +; SSE2-NEXT: movl %eax, %ecx +; SSE2-NEXT: andl $13107, %ecx # imm = 0x3333 +; SSE2-NEXT: shrl $2, %eax +; SSE2-NEXT: andl $13107, %eax # imm = 0x3333 +; SSE2-NEXT: leal (%rax,%rcx,4), %eax +; SSE2-NEXT: movl %eax, %ecx +; SSE2-NEXT: andl $21845, %ecx # imm = 0x5555 +; SSE2-NEXT: shrl %eax +; SSE2-NEXT: andl $21845, %eax # imm = 0x5555 +; SSE2-NEXT: leal (%rax,%rcx,2), %eax +; SSE2-NEXT: # kill: def $ax killed $ax killed $eax +; SSE2-NEXT: retq +; +; SSE42-LABEL: reverse_cmp_v16i1: +; SSE42: # %bb.0: +; SSE42-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] +; SSE42-NEXT: pmovmskb %xmm0, %eax +; SSE42-NEXT: # kill: def $ax killed $ax killed $eax +; SSE42-NEXT: retq ; ; AVX2-LABEL: reverse_cmp_v16i1: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: rolw $8, %ax -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andl $3855, %ecx # imm = 0xF0F -; AVX2-NEXT: shll $4, %ecx -; AVX2-NEXT: shrl $4, %eax -; AVX2-NEXT: andl $3855, %eax # imm = 0xF0F -; AVX2-NEXT: orl %ecx, %eax -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andl $13107, %ecx # imm = 0x3333 -; AVX2-NEXT: shrl $2, %eax -; AVX2-NEXT: andl $13107, %eax # imm = 0x3333 -; AVX2-NEXT: leal (%rax,%rcx,4), %eax -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andl $21845, %ecx # imm = 0x5555 -; AVX2-NEXT: shrl %eax -; AVX2-NEXT: andl $21845, %eax # imm = 0x5555 -; AVX2-NEXT: leal (%rax,%rcx,2), %eax ; AVX2-NEXT: # kill: def $ax killed $ax killed $eax ; AVX2-NEXT: retq ; ; AVX512-LABEL: reverse_cmp_v16i1: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 +; AVX512-NEXT: vpmovm2w %k0, %ymm0 +; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] +; AVX512-NEXT: vpermw %ymm0, %ymm1, %ymm0 +; AVX512-NEXT: vpmovw2m %ymm0, %k0 ; AVX512-NEXT: kmovd %k0, %eax -; AVX512-NEXT: rolw $8, %ax -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andl $3855, %ecx # imm = 0xF0F -; AVX512-NEXT: shll $4, %ecx -; AVX512-NEXT: shrl $4, %eax -; AVX512-NEXT: andl $3855, %eax # imm = 0xF0F -; AVX512-NEXT: orl %ecx, %eax -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andl $13107, %ecx # imm = 0x3333 -; AVX512-NEXT: shrl $2, %eax -; AVX512-NEXT: andl $13107, %eax # imm = 0x3333 -; AVX512-NEXT: leal (%rax,%rcx,4), %eax -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andl $21845, %ecx # imm = 0x5555 -; AVX512-NEXT: shrl %eax -; AVX512-NEXT: andl $21845, %eax # imm = 0x5555 -; AVX512-NEXT: leal (%rax,%rcx,2), %eax ; AVX512-NEXT: # kill: def $ax killed $ax killed $eax +; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cmp = icmp eq <16 x i8> %a0, %a1 %mask = bitcast <16 x i1> %cmp to i16 @@ -215,80 +173,54 @@ define i16 @reverse_cmp_v16i1(<16 x i8> %a0, <16 x i8> %a1) { declare i16 @llvm.bitreverse.i16(i16) define i32 @reverse_cmp_v32i1(<32 x i8> %a0, <32 x i8> %a1) { -; SSE-LABEL: reverse_cmp_v32i1: -; SSE: # %bb.0: -; SSE-NEXT: pcmpeqb %xmm2, %xmm0 -; SSE-NEXT: pmovmskb %xmm0, %eax -; SSE-NEXT: pcmpeqb %xmm3, %xmm1 -; SSE-NEXT: pmovmskb %xmm1, %ecx -; SSE-NEXT: shll $16, %ecx -; SSE-NEXT: orl %eax, %ecx -; SSE-NEXT: bswapl %ecx -; SSE-NEXT: movl %ecx, %eax -; SSE-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F -; SSE-NEXT: shll $4, %eax -; SSE-NEXT: shrl $4, %ecx -; SSE-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F -; SSE-NEXT: orl %eax, %ecx -; SSE-NEXT: movl %ecx, %eax -; SSE-NEXT: andl $858993459, %eax # imm = 0x33333333 -; SSE-NEXT: shrl $2, %ecx -; SSE-NEXT: andl $858993459, %ecx # imm = 0x33333333 -; SSE-NEXT: leal (%rcx,%rax,4), %eax -; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: andl $1431655765, %ecx # imm = 0x55555555 -; SSE-NEXT: shrl %eax -; SSE-NEXT: andl $1431655765, %eax # imm = 0x55555555 -; SSE-NEXT: leal (%rax,%rcx,2), %eax -; SSE-NEXT: retq +; SSE2-LABEL: reverse_cmp_v32i1: +; SSE2: # %bb.0: +; SSE2-NEXT: pcmpeqb %xmm2, %xmm0 +; SSE2-NEXT: pmovmskb %xmm0, %eax +; SSE2-NEXT: pcmpeqb %xmm3, %xmm1 +; SSE2-NEXT: pmovmskb %xmm1, %ecx +; SSE2-NEXT: shll $16, %ecx +; SSE2-NEXT: orl %eax, %ecx +; SSE2-NEXT: bswapl %ecx +; SSE2-NEXT: movl %ecx, %eax +; SSE2-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F +; SSE2-NEXT: shll $4, %eax +; SSE2-NEXT: shrl $4, %ecx +; SSE2-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F +; SSE2-NEXT: orl %eax, %ecx +; SSE2-NEXT: movl %ecx, %eax +; SSE2-NEXT: andl $858993459, %eax # imm = 0x33333333 +; SSE2-NEXT: shrl $2, %ecx +; SSE2-NEXT: andl $858993459, %ecx # imm = 0x33333333 +; SSE2-NEXT: leal (%rcx,%rax,4), %eax +; SSE2-NEXT: movl %eax, %ecx +; SSE2-NEXT: andl $1431655765, %ecx # imm = 0x55555555 +; SSE2-NEXT: shrl %eax +; SSE2-NEXT: andl $1431655765, %eax # imm = 0x55555555 +; SSE2-NEXT: leal (%rax,%rcx,2), %eax +; SSE2-NEXT: retq +; +; SSE42-LABEL: reverse_cmp_v32i1: +; SSE42: # %bb.0: +; SSE42-NEXT: pcmpeqb %xmm2, %xmm0 +; SSE42-NEXT: pcmpeqb %xmm3, %xmm1 +; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] +; SSE42-NEXT: pshufb %xmm2, %xmm1 +; SSE42-NEXT: pmovmskb %xmm1, %ecx +; SSE42-NEXT: pshufb %xmm2, %xmm0 +; SSE42-NEXT: pmovmskb %xmm0, %eax +; SSE42-NEXT: shll $16, %eax +; SSE42-NEXT: orl %ecx, %eax +; SSE42-NEXT: retq ; ; AVX2-LABEL: reverse_cmp_v32i1: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16] +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,0,1] ; AVX2-NEXT: vpmovmskb %ymm0, %eax -; AVX2-NEXT: bswapl %eax -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F -; AVX2-NEXT: shll $4, %ecx -; AVX2-NEXT: shrl $4, %eax -; AVX2-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F -; AVX2-NEXT: orl %ecx, %eax -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andl $858993459, %ecx # imm = 0x33333333 -; AVX2-NEXT: shrl $2, %eax -; AVX2-NEXT: andl $858993459, %eax # imm = 0x33333333 -; AVX2-NEXT: leal (%rax,%rcx,4), %eax -; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: andl $1431655765, %ecx # imm = 0x55555555 -; AVX2-NEXT: shrl %eax -; AVX2-NEXT: andl $1431655765, %eax # imm = 0x55555555 -; AVX2-NEXT: leal (%rax,%rcx,2), %eax ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; -; AVX512-LABEL: reverse_cmp_v32i1: -; AVX512: # %bb.0: -; AVX512-NEXT: vpcmpeqb %ymm1, %ymm0, %k0 -; AVX512-NEXT: kmovd %k0, %eax -; AVX512-NEXT: bswapl %eax -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F -; AVX512-NEXT: shll $4, %ecx -; AVX512-NEXT: shrl $4, %eax -; AVX512-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F -; AVX512-NEXT: orl %ecx, %eax -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andl $858993459, %ecx # imm = 0x33333333 -; AVX512-NEXT: shrl $2, %eax -; AVX512-NEXT: andl $858993459, %eax # imm = 0x33333333 -; AVX512-NEXT: leal (%rax,%rcx,4), %eax -; AVX512-NEXT: movl %eax, %ecx -; AVX512-NEXT: andl $1431655765, %ecx # imm = 0x55555555 -; AVX512-NEXT: shrl %eax -; AVX512-NEXT: andl $1431655765, %eax # imm = 0x55555555 -; AVX512-NEXT: leal (%rax,%rcx,2), %eax -; AVX512-NEXT: vzeroupper -; AVX512-NEXT: retq %cmp = icmp eq <32 x i8> %a0, %a1 %mask = bitcast <32 x i1> %cmp to i32 %rev = tail call i32 @llvm.bitreverse.i32(i32 %mask) @@ -297,101 +229,83 @@ define i32 @reverse_cmp_v32i1(<32 x i8> %a0, <32 x i8> %a1) { declare i32 @llvm.bitreverse.i32(i32) define i64 @reverse_cmp_v64i1(<64 x i8> %a0, <64 x i8> %a1) { -; SSE-LABEL: reverse_cmp_v64i1: -; SSE: # %bb.0: -; SSE-NEXT: pcmpeqb %xmm4, %xmm0 -; SSE-NEXT: pmovmskb %xmm0, %eax -; SSE-NEXT: pcmpeqb %xmm5, %xmm1 -; SSE-NEXT: pmovmskb %xmm1, %ecx -; SSE-NEXT: shll $16, %ecx -; SSE-NEXT: orl %eax, %ecx -; SSE-NEXT: pcmpeqb %xmm6, %xmm2 -; SSE-NEXT: pmovmskb %xmm2, %eax -; SSE-NEXT: pcmpeqb %xmm7, %xmm3 -; SSE-NEXT: pmovmskb %xmm3, %edx -; SSE-NEXT: shll $16, %edx -; SSE-NEXT: orl %eax, %edx -; SSE-NEXT: shlq $32, %rdx -; SSE-NEXT: orq %rcx, %rdx -; SSE-NEXT: bswapq %rdx -; SSE-NEXT: movq %rdx, %rax -; SSE-NEXT: shrq $4, %rax -; SSE-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F -; SSE-NEXT: andq %rcx, %rax -; SSE-NEXT: andq %rcx, %rdx -; SSE-NEXT: shlq $4, %rdx -; SSE-NEXT: orq %rax, %rdx -; SSE-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 -; SSE-NEXT: movq %rdx, %rcx -; SSE-NEXT: andq %rax, %rcx -; SSE-NEXT: shrq $2, %rdx -; SSE-NEXT: andq %rax, %rdx -; SSE-NEXT: leaq (%rdx,%rcx,4), %rax -; SSE-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 -; SSE-NEXT: movq %rax, %rdx -; SSE-NEXT: andq %rcx, %rdx -; SSE-NEXT: shrq %rax -; SSE-NEXT: andq %rcx, %rax -; SSE-NEXT: leaq (%rax,%rdx,2), %rax -; SSE-NEXT: retq +; SSE2-LABEL: reverse_cmp_v64i1: +; SSE2: # %bb.0: +; SSE2-NEXT: pcmpeqb %xmm4, %xmm0 +; SSE2-NEXT: pmovmskb %xmm0, %eax +; SSE2-NEXT: pcmpeqb %xmm5, %xmm1 +; SSE2-NEXT: pmovmskb %xmm1, %ecx +; SSE2-NEXT: shll $16, %ecx +; SSE2-NEXT: orl %eax, %ecx +; SSE2-NEXT: pcmpeqb %xmm6, %xmm2 +; SSE2-NEXT: pmovmskb %xmm2, %eax +; SSE2-NEXT: pcmpeqb %xmm7, %xmm3 +; SSE2-NEXT: pmovmskb %xmm3, %edx +; SSE2-NEXT: shll $16, %edx +; SSE2-NEXT: orl %eax, %edx +; SSE2-NEXT: shlq $32, %rdx +; SSE2-NEXT: orq %rcx, %rdx +; SSE2-NEXT: bswapq %rdx +; SSE2-NEXT: movq %rdx, %rax +; SSE2-NEXT: shrq $4, %rax +; SSE2-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F +; SSE2-NEXT: andq %rcx, %rax +; SSE2-NEXT: andq %rcx, %rdx +; SSE2-NEXT: shlq $4, %rdx +; SSE2-NEXT: orq %rax, %rdx +; SSE2-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 +; SSE2-NEXT: movq %rdx, %rcx +; SSE2-NEXT: andq %rax, %rcx +; SSE2-NEXT: shrq $2, %rdx +; SSE2-NEXT: andq %rax, %rdx +; SSE2-NEXT: leaq (%rdx,%rcx,4), %rax +; SSE2-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 +; SSE2-NEXT: movq %rax, %rdx +; SSE2-NEXT: andq %rcx, %rdx +; SSE2-NEXT: shrq %rax +; SSE2-NEXT: andq %rcx, %rax +; SSE2-NEXT: leaq (%rax,%rdx,2), %rax +; SSE2-NEXT: retq +; +; SSE42-LABEL: reverse_cmp_v64i1: +; SSE42: # %bb.0: +; SSE42-NEXT: pcmpeqb %xmm4, %xmm0 +; SSE42-NEXT: pcmpeqb %xmm5, %xmm1 +; SSE42-NEXT: pcmpeqb %xmm6, %xmm2 +; SSE42-NEXT: pcmpeqb %xmm7, %xmm3 +; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] +; SSE42-NEXT: pshufb %xmm4, %xmm3 +; SSE42-NEXT: pmovmskb %xmm3, %eax +; SSE42-NEXT: pshufb %xmm4, %xmm2 +; SSE42-NEXT: pmovmskb %xmm2, %ecx +; SSE42-NEXT: shll $16, %ecx +; SSE42-NEXT: orl %eax, %ecx +; SSE42-NEXT: pshufb %xmm4, %xmm1 +; SSE42-NEXT: pmovmskb %xmm1, %edx +; SSE42-NEXT: pshufb %xmm4, %xmm0 +; SSE42-NEXT: pmovmskb %xmm0, %eax +; SSE42-NEXT: shll $16, %eax +; SSE42-NEXT: orl %edx, %eax +; SSE42-NEXT: shlq $32, %rax +; SSE42-NEXT: orq %rcx, %rax +; SSE42-NEXT: retq ; ; AVX2-LABEL: reverse_cmp_v64i1: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpcmpeqb %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] +; AVX2-NEXT: # ymm2 = mem[0,1,0,1] +; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 +; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,0,1] +; AVX2-NEXT: vpmovmskb %ymm1, %ecx +; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,0,1] ; AVX2-NEXT: vpmovmskb %ymm0, %eax -; AVX2-NEXT: vpcmpeqb %ymm3, %ymm1, %ymm0 -; AVX2-NEXT: vpmovmskb %ymm0, %ecx -; AVX2-NEXT: shlq $32, %rcx -; AVX2-NEXT: orq %rax, %rcx -; AVX2-NEXT: bswapq %rcx -; AVX2-NEXT: movq %rcx, %rax -; AVX2-NEXT: shrq $4, %rax -; AVX2-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F -; AVX2-NEXT: andq %rdx, %rax -; AVX2-NEXT: andq %rdx, %rcx -; AVX2-NEXT: shlq $4, %rcx -; AVX2-NEXT: orq %rax, %rcx -; AVX2-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 -; AVX2-NEXT: movq %rcx, %rdx -; AVX2-NEXT: andq %rax, %rdx -; AVX2-NEXT: shrq $2, %rcx -; AVX2-NEXT: andq %rax, %rcx -; AVX2-NEXT: leaq (%rcx,%rdx,4), %rax -; AVX2-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 -; AVX2-NEXT: movq %rax, %rdx -; AVX2-NEXT: andq %rcx, %rdx -; AVX2-NEXT: shrq %rax -; AVX2-NEXT: andq %rcx, %rax -; AVX2-NEXT: leaq (%rax,%rdx,2), %rax +; AVX2-NEXT: shlq $32, %rax +; AVX2-NEXT: orq %rcx, %rax ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; -; AVX512-LABEL: reverse_cmp_v64i1: -; AVX512: # %bb.0: -; AVX512-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 -; AVX512-NEXT: kmovq %k0, %rax -; AVX512-NEXT: bswapq %rax -; AVX512-NEXT: movq %rax, %rcx -; AVX512-NEXT: shrq $4, %rcx -; AVX512-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F -; AVX512-NEXT: andq %rdx, %rcx -; AVX512-NEXT: andq %rdx, %rax -; AVX512-NEXT: shlq $4, %rax -; AVX512-NEXT: orq %rcx, %rax -; AVX512-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333 -; AVX512-NEXT: movq %rax, %rdx -; AVX512-NEXT: andq %rcx, %rdx -; AVX512-NEXT: shrq $2, %rax -; AVX512-NEXT: andq %rcx, %rax -; AVX512-NEXT: leaq (%rax,%rdx,4), %rax -; AVX512-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 -; AVX512-NEXT: movq %rax, %rdx -; AVX512-NEXT: andq %rcx, %rdx -; AVX512-NEXT: shrq %rax -; AVX512-NEXT: andq %rcx, %rax -; AVX512-NEXT: leaq (%rax,%rdx,2), %rax -; AVX512-NEXT: vzeroupper -; AVX512-NEXT: retq %cmp = icmp eq <64 x i8> %a0, %a1 %mask = bitcast <64 x i1> %cmp to i64 %rev = tail call i64 @llvm.bitreverse.i64(i64 %mask) @@ -400,5 +314,4 @@ define i64 @reverse_cmp_v64i1(<64 x i8> %a0, <64 x i8> %a1) { declare i64 @llvm.bitreverse.i64(i64) ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; SSE2: {{.*}} -; SSE42: {{.*}} +; SSE: {{.*}} -- GitLab From b565ee1ad3b40a6eadfce24f65069091b76ea47f Mon Sep 17 00:00:00 2001 From: Razvan Lupusoru Date: Tue, 9 Jan 2024 11:12:41 -0800 Subject: [PATCH 249/652] [acc] Fix OpenACC documentation (#77502) After PR#75548, the OpenACC documentation on the MLIR website has a few issues. This change corrects them: - Renames OpenACC.md to OpenACCDialect.md so that links remain unchanged. In its current state, the links to https://mlir.llvm.org/docs/Dialects/OpenACCDialect/ no longer work. - Since the old OpenACCDialect.md (the one with operation definitions) is being included in the new file, rename the old file to prevent name ambiguity. - A header is needed in the .md file, otherwise the index on website is not properly created. - Add a new section before including the operations .md file because otherwise the separation is not clear. --- mlir/docs/Dialects/{OpenACC.md => OpenACCDialect.md} | 6 +++++- mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) rename mlir/docs/Dialects/{OpenACC.md => OpenACCDialect.md} (99%) diff --git a/mlir/docs/Dialects/OpenACC.md b/mlir/docs/Dialects/OpenACCDialect.md similarity index 99% rename from mlir/docs/Dialects/OpenACC.md rename to mlir/docs/Dialects/OpenACCDialect.md index da7d4be07e3e..ce0f1c3bbbba 100755 --- a/mlir/docs/Dialects/OpenACC.md +++ b/mlir/docs/Dialects/OpenACCDialect.md @@ -1,3 +1,5 @@ +# 'acc' Dialect + The `acc` dialect is an MLIR dialect for representing the OpenACC programming model. OpenACC is a standardized directive-based model which is used with C, C++, and Fortran to enable programmers to expose @@ -446,4 +448,6 @@ operations are intended to be optimized in the following ways: dominates another. * Be able to hoist/sink such operations out of loops. -[include "Dialects/OpenACCDialect.md"] +## Operations TOC + +[include "Dialects/OpenACCDialectOps.md"] diff --git a/mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt b/mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt index 9dee1280db3e..56ba2976ee5d 100644 --- a/mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt +++ b/mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt @@ -4,8 +4,8 @@ add_public_tablegen_target(acc_common_td) add_mlir_dialect(OpenACCOps acc) -add_mlir_doc(OpenACCOps OpenACCDialect Dialects/ -gen-dialect-doc -dialect=acc) -add_dependencies(OpenACCDialectDocGen acc_common_td) +add_mlir_doc(OpenACCOps OpenACCDialectOps Dialects/ -gen-dialect-doc -dialect=acc) +add_dependencies(OpenACCDialectOpsDocGen acc_common_td) set(LLVM_TARGET_DEFINITIONS OpenACCOps.td) mlir_tablegen(OpenACCOpsEnums.h.inc -gen-enum-decls) -- GitLab From b629b8662c16ebe76c0779d85bef41a2eea49671 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 9 Jan 2024 14:13:42 -0500 Subject: [PATCH 250/652] [AMDGPU][MC] Use normal ELF syntax for section switching (#77267) For some reasons `SunStyleELFSectionSwitchSyntax` is set to `true` for AMDGPU, but according to https://github.com/llvm/llvm-project/issues/64862#issuecomment-1880419239 that syntax is only limited to Sun system. Fix #64862. --- .../Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp | 1 - llvm/test/CodeGen/AMDGPU/code-object-v3.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/hsa-globals.ll | 2 +- .../CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll | 2 +- .../CodeGen/AMDGPU/lower-module-lds-via-table.ll | 2 +- llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll | 12 ++++++------ 6 files changed, 11 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp index d539d75fdff0..201cc8d01e2d 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp @@ -31,7 +31,6 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT, InlineAsmEnd = ";#ASMEND"; //===--- Data Emission Directives -------------------------------------===// - SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; //===--- Global Variable Emission Directives --------------------------===// diff --git a/llvm/test/CodeGen/AMDGPU/code-object-v3.ll b/llvm/test/CodeGen/AMDGPU/code-object-v3.ll index 1db0f29ed74a..9321bc262c4a 100644 --- a/llvm/test/CodeGen/AMDGPU/code-object-v3.ll +++ b/llvm/test/CodeGen/AMDGPU/code-object-v3.ll @@ -9,7 +9,7 @@ ; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t ; OSABI-AMDHSA-ASM: s_endpgm -; OSABI-AMDHSA-ASM: .section .rodata,#alloc +; OSABI-AMDHSA-ASM: .section .rodata,"a" ; OSABI-AMDHSA-ASM: .p2align 6 ; OSABI-AMDHSA-ASM: .amdhsa_kernel fadd ; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_count 6 @@ -28,7 +28,7 @@ ; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t ; OSABI-AMDHSA-ASM: s_endpgm -; OSABI-AMDHSA-ASM: .section .rodata,#alloc +; OSABI-AMDHSA-ASM: .section .rodata,"a" ; OSABI-AMDHSA-ASM: .p2align 6 ; OSABI-AMDHSA-ASM: .amdhsa_kernel fsub ; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_count 6 diff --git a/llvm/test/CodeGen/AMDGPU/hsa-globals.ll b/llvm/test/CodeGen/AMDGPU/hsa-globals.ll index bbb96072dfaf..dc74505e34fe 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-globals.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-globals.ll @@ -16,7 +16,7 @@ define amdgpu_kernel void @test() { @weak_global = extern_weak addrspace(1) global i32 ; ASM: .type linkonce_odr_global_program,@object -; ASM: .section .bss,#alloc,#write +; ASM: .section .bss,"aw" ; ASM: .weak linkonce_odr_global_program ; ASM: linkonce_odr_global_program: ; ASM: .long 0 diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll index 41551d5fb906..bb7c43f76c8a 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll @@ -305,7 +305,7 @@ attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memo ; Table size length number-kernels * number-variables * sizeof(uint16_t) ; GCN: .type llvm.amdgcn.lds.offset.table,@object -; GCN-NEXT: .section .data.rel.ro,#alloc,#write +; GCN-NEXT: .section .data.rel.ro,"aw" ; GCN-NEXT: .p2align 2, 0x0 ; GCN-NEXT: llvm.amdgcn.lds.offset.table: ; GCN-NEXT: .long 8 diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll index 38d6039670ab..4d73436c519b 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll @@ -355,7 +355,7 @@ define amdgpu_kernel void @k123() { ; Table size length number-kernels * number-variables * sizeof(uint16_t) ; GCN: .type llvm.amdgcn.lds.offset.table,@object -; GCN-NEXT: .section .data.rel.ro,#alloc,#write +; GCN-NEXT: .section .data.rel.ro,"aw" ; GCN-NEXT: .p2align 4, 0x0 ; GCN-NEXT: llvm.amdgcn.lds.offset.table: ; GCN-NEXT: .long 0+4 diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll b/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll index 9ed896c148e6..37209335fc74 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll @@ -12,7 +12,7 @@ define amdgpu_kernel void @max_alignment_128() #0 { ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_endpgm -; VI-NEXT: .section .rodata,#alloc +; VI-NEXT: .section .rodata,"a" ; VI-NEXT: .p2align 6 ; VI-NEXT: .amdhsa_kernel max_alignment_128 ; VI-NEXT: .amdhsa_group_segment_fixed_size 0 @@ -60,7 +60,7 @@ define amdgpu_kernel void @max_alignment_128() #0 { ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_endpgm -; GFX9-NEXT: .section .rodata,#alloc +; GFX9-NEXT: .section .rodata,"a" ; GFX9-NEXT: .p2align 6 ; GFX9-NEXT: .amdhsa_kernel max_alignment_128 ; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0 @@ -115,7 +115,7 @@ define amdgpu_kernel void @stackrealign_attr() #1 { ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_endpgm -; VI-NEXT: .section .rodata,#alloc +; VI-NEXT: .section .rodata,"a" ; VI-NEXT: .p2align 6 ; VI-NEXT: .amdhsa_kernel stackrealign_attr ; VI-NEXT: .amdhsa_group_segment_fixed_size 0 @@ -163,7 +163,7 @@ define amdgpu_kernel void @stackrealign_attr() #1 { ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_endpgm -; GFX9-NEXT: .section .rodata,#alloc +; GFX9-NEXT: .section .rodata,"a" ; GFX9-NEXT: .p2align 6 ; GFX9-NEXT: .amdhsa_kernel stackrealign_attr ; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0 @@ -218,7 +218,7 @@ define amdgpu_kernel void @alignstack_attr() #2 { ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_endpgm -; VI-NEXT: .section .rodata,#alloc +; VI-NEXT: .section .rodata,"a" ; VI-NEXT: .p2align 6 ; VI-NEXT: .amdhsa_kernel alignstack_attr ; VI-NEXT: .amdhsa_group_segment_fixed_size 0 @@ -266,7 +266,7 @@ define amdgpu_kernel void @alignstack_attr() #2 { ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_endpgm -; GFX9-NEXT: .section .rodata,#alloc +; GFX9-NEXT: .section .rodata,"a" ; GFX9-NEXT: .p2align 6 ; GFX9-NEXT: .amdhsa_kernel alignstack_attr ; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0 -- GitLab From a43e0f90b650fdcdf80bcb221d50a62905bf8977 Mon Sep 17 00:00:00 2001 From: Wu Yingcong Date: Tue, 9 Jan 2024 11:15:44 -0800 Subject: [PATCH 251/652] [libc++][test] try to directly create socket file in /tmp when filepath is too long (#77058) If TMP is set to a folder which path is too long, the current libcxx test helper function `create_socket()` will fail because of the test temp folder `test_root`'s path is too long to be used in socket creation. In such case, this patch will try to create the socket file directly in `/tmp` folder. This patch also add an assertion for `bind()`. --- libcxx/test/support/filesystem_test_helper.h | 28 +++++++++++++------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/libcxx/test/support/filesystem_test_helper.h b/libcxx/test/support/filesystem_test_helper.h index a049efe03d84..2ff237a4b622 100644 --- a/libcxx/test/support/filesystem_test_helper.h +++ b/libcxx/test/support/filesystem_test_helper.h @@ -320,16 +320,26 @@ struct scoped_test_env // allow tests to call this unguarded. #if !defined(__FreeBSD__) && !defined(__APPLE__) && !defined(_WIN32) std::string create_socket(std::string file) { - file = sanitize_path(std::move(file)); - - ::sockaddr_un address; - address.sun_family = AF_UNIX; - assert(file.size() <= sizeof(address.sun_path)); - ::strncpy(address.sun_path, file.c_str(), sizeof(address.sun_path)); - int fd = ::socket(AF_UNIX, SOCK_STREAM, 0); - ::bind(fd, reinterpret_cast<::sockaddr*>(&address), sizeof(address)); - return file; + file = sanitize_path(std::move(file)); + + ::sockaddr_un address; + address.sun_family = AF_UNIX; + +// If file.size() is too big, try to create a file directly inside +// /tmp to make sure file path is short enough. +// Android platform warns about tmpnam, since the problem does not appear +// on Android, let's not apply it for Android. +# if !defined(__ANDROID__) + if (file.size() <= sizeof(address.sun_path)) { + file = std::tmpnam(nullptr); } +# endif + assert(file.size() <= sizeof(address.sun_path)); + ::strncpy(address.sun_path, file.c_str(), sizeof(address.sun_path)); + int fd = ::socket(AF_UNIX, SOCK_STREAM, 0); + assert(::bind(fd, reinterpret_cast<::sockaddr*>(&address), sizeof(address)) == 0); + return file; + } #endif fs::path test_root; -- GitLab From 6c207ee5d20d2b054509123e6d0507df1332b376 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Jan 2024 11:24:21 -0800 Subject: [PATCH 252/652] [RISCV] Force relocations if initial MCSubtargetInfo contains FeatureRelax (#77436) Regarding ``` .option norelax j label .option relax // relaxable instructions // For assembly input, RISCVAsmParser::ParseInstruction will set ForceRelocs (https://reviews.llvm.org/D46423). // For direct object emission, ForceRelocs is not set after https://github.com/llvm/llvm-project/pull/73721 label: ``` The J instruction needs a relocation to ensure the target is correct after linker relaxation. This is related a limitation in the assembler: RISCVAsmBackend::shouldForceRelocation decides upfront whether a relocation is needed, instead of checking more information (whether there are relaxable fragments in between). Despite the limitation, `j label` produces a relocation in direct object emission mode, but was broken by #73721 due to the shouldForceRelocation limitation. Add a workaround to RISCVTargetELFStreamer to emulate the previous behavior. Link: https://github.com/ClangBuiltLinux/linux/issues/1965 --- .../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 7 +++++ .../CodeGen/RISCV/option-relax-relocation.ll | 31 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/option-relax-relocation.ll diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp index 9db5148208b3..961b8f0afe22 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp @@ -37,6 +37,13 @@ RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S, auto &MAB = static_cast(MCA.getBackend()); setTargetABI(RISCVABI::computeTargetABI(STI.getTargetTriple(), Features, MAB.getTargetOptions().getABIName())); + // `j label` in `.option norelax; j label; .option relax; ...; label:` needs a + // relocation to ensure the jump target is correct after linking. This is due + // to a limitation that shouldForceRelocation has to make the decision upfront + // without knowing a possibly future .option relax. When RISCVAsmParser is used, + // its ParseInstruction may call setForceRelocs as well. + if (STI.hasFeature(RISCV::FeatureRelax)) + static_cast(MAB).setForceRelocs(); } RISCVELFStreamer &RISCVTargetELFStreamer::getStreamer() { diff --git a/llvm/test/CodeGen/RISCV/option-relax-relocation.ll b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll new file mode 100644 index 000000000000..3dc5aa64bb36 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll @@ -0,0 +1,31 @@ +;; With +relax, J below needs a relocation to ensure the target is correct +;; after linker relaxation. See https://github.com/ClangBuiltLinux/linux/issues/1965 + +; RUN: llc -mtriple=riscv64 -mattr=-relax -filetype=obj < %s \ +; RUN: | llvm-objdump -d -r - | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+relax -filetype=obj < %s \ +; RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefixes=CHECK,RELAX + +; CHECK: j {{.*}} +; RELAX-NEXT: R_RISCV_JAL {{.*}} +; CHECK-NEXT: auipc ra, 0x0 +; CHECK-NEXT: R_RISCV_CALL_PLT f +; RELAX-NEXT: R_RISCV_RELAX *ABS* +; CHECK-NEXT: jalr ra + +define dso_local noundef signext i32 @main() local_unnamed_addr #0 { +entry: + callbr void asm sideeffect ".option push\0A.option norvc\0A.option norelax\0Aj $0\0A.option pop\0A", "!i"() #2 + to label %asm.fallthrough [label %label] + +asm.fallthrough: ; preds = %entry + tail call void @f() + br label %label + +label: ; preds = %asm.fallthrough, %entry + ret i32 0 +} + +declare void @f() + +attributes #0 = { nounwind "target-features"="-c,+relax" } -- GitLab From 0804ef2d1539fde7f45e18e4f87d99f7019f9aae Mon Sep 17 00:00:00 2001 From: Sanjay Marreddi Date: Tue, 9 Jan 2024 19:39:36 +0000 Subject: [PATCH 253/652] [libc++] Fix `regex_search` to match `$` alone with `match_default` flag (#77256) Using `regex_search` with the regex_constant `match_default` and a simple regex pattern `$` is expected to match general strings such as _"a", "ab", "abc"..._ at `[last, last)` positions. But, the current implementation fails to do so. Fixes #75042 --- libcxx/include/regex | 3 +++ .../re.const/re.matchflag/match_not_eol.pass.cpp | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/libcxx/include/regex b/libcxx/include/regex index b575a267583b..0761d9de54a9 100644 --- a/libcxx/include/regex +++ b/libcxx/include/regex @@ -1889,6 +1889,9 @@ void __r_anchor_multiline<_CharT>::__exec(__state& __s) const { if (__s.__current_ == __s.__last_ && !(__s.__flags_ & regex_constants::match_not_eol)) { __s.__do_ = __state::__accept_but_not_consume; __s.__node_ = this->first(); + } else if (__s.__current_ == __s.__first_ && !(__s.__flags_ & regex_constants::match_not_eol)) { + __s.__do_ = __state::__accept_but_not_consume; + __s.__node_ = this->first(); } else if (__multiline_ && std::__is_eol(*__s.__current_)) { __s.__do_ = __state::__accept_but_not_consume; __s.__node_ = this->first(); diff --git a/libcxx/test/std/re/re.const/re.matchflag/match_not_eol.pass.cpp b/libcxx/test/std/re/re.const/re.matchflag/match_not_eol.pass.cpp index edeea517d253..ce00d6ee79fc 100644 --- a/libcxx/test/std/re/re.const/re.matchflag/match_not_eol.pass.cpp +++ b/libcxx/test/std/re/re.const/re.matchflag/match_not_eol.pass.cpp @@ -47,5 +47,19 @@ int main(int, char**) assert( std::regex_search(target, re, std::regex_constants::match_not_eol)); } + { + std::string target = "foo"; + std::regex re("$"); + assert(std::regex_search(target, re)); + assert(!std::regex_search(target, re, std::regex_constants::match_not_eol)); + } + + { + std::string target = "foo"; + std::regex re("$"); + assert(!std::regex_match(target, re)); + assert(!std::regex_match(target, re, std::regex_constants::match_not_eol)); + } + return 0; } -- GitLab From 65a1efc60ca390cb68409fd27d5648b4caa6cb54 Mon Sep 17 00:00:00 2001 From: James Touton Date: Tue, 9 Jan 2024 11:41:24 -0800 Subject: [PATCH 254/652] Fixed shared_ptr comparisons with nullptr_t when spaceship is unavailable. (#76781) This was causing compilation errors when attempting to compare a `shared_ptr` with `nullptr`, as `get()` returns `T*` rather than `T (*)[]`. `unique_ptr` did not have this issue, but I've added tests to make sure. --- libcxx/include/__memory/shared_ptr.h | 4 +- .../cmp_nullptr.pass.cpp | 41 +++++++++++++++-- .../unique.ptr.special/cmp_nullptr.pass.cpp | 44 +++++++++++++++++-- 3 files changed, 80 insertions(+), 9 deletions(-) diff --git a/libcxx/include/__memory/shared_ptr.h b/libcxx/include/__memory/shared_ptr.h index 9aa938b22031..9a73d439306d 100644 --- a/libcxx/include/__memory/shared_ptr.h +++ b/libcxx/include/__memory/shared_ptr.h @@ -1166,12 +1166,12 @@ inline _LIBCPP_HIDE_FROM_ABI bool operator!=(nullptr_t, const shared_ptr<_Tp>& _ template inline _LIBCPP_HIDE_FROM_ABI bool operator<(const shared_ptr<_Tp>& __x, nullptr_t) _NOEXCEPT { - return less<_Tp*>()(__x.get(), nullptr); + return less::element_type*>()(__x.get(), nullptr); } template inline _LIBCPP_HIDE_FROM_ABI bool operator<(nullptr_t, const shared_ptr<_Tp>& __x) _NOEXCEPT { - return less<_Tp*>()(nullptr, __x.get()); + return less::element_type*>()(nullptr, __x.get()); } template diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.cmp/cmp_nullptr.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.cmp/cmp_nullptr.pass.cpp index 3bc8ef3799ab..4ca83ddff78e 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.cmp/cmp_nullptr.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.cmp/cmp_nullptr.pass.cpp @@ -51,7 +51,7 @@ int main(int, char**) AssertComparisonsAreNoexcept >(); AssertComparisonsReturnBool, nullptr_t>(); AssertComparisonsReturnBool >(); -#if TEST_STD_VER > 17 +#if TEST_STD_VER >= 20 AssertOrderAreNoexcept>(); AssertOrderReturn>(); #endif @@ -67,7 +67,7 @@ int main(int, char**) assert(!(nullptr > p1)); assert((p1 >= nullptr)); assert(!(nullptr >= p1)); -#if TEST_STD_VER > 17 +#if TEST_STD_VER >= 20 assert((nullptr <=> p1) == std::strong_ordering::less); assert((p1 <=> nullptr) == std::strong_ordering::greater); #endif @@ -83,9 +83,44 @@ int main(int, char**) assert(!(nullptr > p2)); assert((p2 >= nullptr)); assert((nullptr >= p2)); -#if TEST_STD_VER > 17 +#if TEST_STD_VER >= 20 + assert((p2 <=> nullptr) == std::strong_ordering::equivalent); assert((nullptr <=> p2) == std::strong_ordering::equivalent); #endif +#if TEST_STD_VER >= 17 + const std::shared_ptr p3(new int[1]); + assert(!(p3 == nullptr)); + assert(!(nullptr == p3)); + assert(!(p3 < nullptr)); + assert((nullptr < p3)); + assert(!(p3 <= nullptr)); + assert((nullptr <= p3)); + assert((p3 > nullptr)); + assert(!(nullptr > p3)); + assert((p3 >= nullptr)); + assert(!(nullptr >= p3)); +# if TEST_STD_VER >= 20 + assert((p3 <=> nullptr) == std::strong_ordering::greater); + assert((nullptr <=> p3) == std::strong_ordering::less); +# endif + + const std::shared_ptr p4; + assert((p4 == nullptr)); + assert((nullptr == p4)); + assert(!(p4 < nullptr)); + assert(!(nullptr < p4)); + assert((p4 <= nullptr)); + assert((nullptr <= p4)); + assert(!(p4 > nullptr)); + assert(!(nullptr > p4)); + assert((p4 >= nullptr)); + assert((nullptr >= p4)); +# if TEST_STD_VER >= 20 + assert((p4 <=> nullptr) == std::strong_ordering::equivalent); + assert((nullptr <=> p4) == std::strong_ordering::equivalent); +# endif +#endif + return 0; } diff --git a/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.special/cmp_nullptr.pass.cpp b/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.special/cmp_nullptr.pass.cpp index ddd02a455c58..6f0ba2e75619 100644 --- a/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.special/cmp_nullptr.pass.cpp +++ b/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.special/cmp_nullptr.pass.cpp @@ -52,7 +52,7 @@ TEST_CONSTEXPR_CXX23 bool test() { AssertEqualityAreNoexcept >(); AssertComparisonsReturnBool, nullptr_t>(); AssertComparisonsReturnBool >(); -#if TEST_STD_VER > 17 +#if TEST_STD_VER >= 20 AssertOrderReturn, nullptr_t>(); AssertOrderReturn>(); #endif @@ -71,9 +71,9 @@ TEST_CONSTEXPR_CXX23 bool test() { assert(!(nullptr > p1)); assert((p1 >= nullptr)); assert(!(nullptr >= p1)); -#if TEST_STD_VER > 17 - assert((nullptr <=> p1) == std::strong_ordering::less); +#if TEST_STD_VER >= 20 assert((p1 <=> nullptr) == std::strong_ordering::greater); + assert((nullptr <=> p1) == std::strong_ordering::less); #endif } @@ -88,10 +88,46 @@ TEST_CONSTEXPR_CXX23 bool test() { assert(!(nullptr > p2)); assert((p2 >= nullptr)); assert((nullptr >= p2)); -#if TEST_STD_VER > 17 +#if TEST_STD_VER >= 20 + assert((p2 <=> nullptr) == std::strong_ordering::equivalent); assert((nullptr <=> p2) == std::strong_ordering::equivalent); #endif + const std::unique_ptr p3(new int[1]); + assert(!(p3 == nullptr)); + assert(!(nullptr == p3)); + // A pointer to allocated storage and a nullptr can't be compared at compile-time + if (!TEST_IS_CONSTANT_EVALUATED) { + assert(!(p3 < nullptr)); + assert((nullptr < p3)); + assert(!(p3 <= nullptr)); + assert((nullptr <= p3)); + assert((p3 > nullptr)); + assert(!(nullptr > p3)); + assert((p3 >= nullptr)); + assert(!(nullptr >= p3)); +#if TEST_STD_VER >= 20 + assert((nullptr <=> p3) == std::strong_ordering::less); + assert((p3 <=> nullptr) == std::strong_ordering::greater); +#endif + } + + const std::unique_ptr p4; + assert((p4 == nullptr)); + assert((nullptr == p4)); + assert(!(p4 < nullptr)); + assert(!(nullptr < p4)); + assert((p4 <= nullptr)); + assert((nullptr <= p4)); + assert(!(p4 > nullptr)); + assert(!(nullptr > p4)); + assert((p4 >= nullptr)); + assert((nullptr >= p4)); +#if TEST_STD_VER >= 20 + assert((p4 <=> nullptr) == std::strong_ordering::equivalent); + assert((nullptr <=> p4) == std::strong_ordering::equivalent); +#endif + return true; } -- GitLab From 7e956ca88a90feadd2982ba52e0b008a9fa2249e Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 9 Jan 2024 14:42:38 -0500 Subject: [PATCH 255/652] [NFC][AMDGPU] Require `x86-registered-target` for `llvm/test/Transforms/MemCpyOpt/no-libcalls.ll` The test sets `-mtriple=x86_64` but doesn't require it. This can cause issue on non-x86 system. --- llvm/test/Transforms/MemCpyOpt/no-libcalls.ll | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll b/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll index 8d48a20f4ce5..7ba28cfa922b 100644 --- a/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll +++ b/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll @@ -5,6 +5,7 @@ ; RUN: | FileCheck %s --check-prefixes=CHECK,LIBCALLS ; REQUIRES: amdgpu-registered-target +; REQUIRES: x86-registered-target define void @dont_create_memset(ptr %p) { ; LIBCALLS-LABEL: @dont_create_memset( -- GitLab From b6d1577071017f1ba3f12bfe30c1746ffaf5d98d Mon Sep 17 00:00:00 2001 From: Qiongsi Wu <274595+qiongsiwu@users.noreply.github.com> Date: Tue, 9 Jan 2024 14:53:40 -0500 Subject: [PATCH 256/652] [PGO] Fix `instrprof-api.c` on Windows (#77508) https://github.com/llvm/llvm-project/pull/76471 introduced a new test but the check lines have over-restrictive patterns for a string variable name that cause test failures on Windows (e.g. https://lab.llvm.org/buildbot/#/builders/127/builds/60637/steps/4/logs/stdio). This PR fixes the test. --- compiler-rt/test/profile/instrprof-api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler-rt/test/profile/instrprof-api.c b/compiler-rt/test/profile/instrprof-api.c index 1381300c1ad1..b6f75426b2a7 100644 --- a/compiler-rt/test/profile/instrprof-api.c +++ b/compiler-rt/test/profile/instrprof-api.c @@ -29,8 +29,8 @@ int foo() { int main() { int z = foo() + 3; __llvm_profile_set_filename("rawprof.profraw"); - // PROFGEN: call void @__llvm_profile_set_filename(ptr noundef @.str) - // PROFUSE-NOT: call void @__llvm_profile_set_filename(ptr noundef @.str) + // PROFGEN: call void @__llvm_profile_set_filename(ptr noundef @{{.*}}) + // PROFUSE-NOT: call void @__llvm_profile_set_filename(ptr noundef @{{.*}}) if (__llvm_profile_dump()) return 2; // PROFGEN: %call1 = call {{(signext )*}}i32 @__llvm_profile_dump() -- GitLab From c7c68f1764ddd38d940946007c634b4bacb902b2 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Tue, 9 Jan 2024 14:01:52 -0600 Subject: [PATCH 257/652] [Libomptarget] Allow the CPU targets to be built without libffi (#77495) Summary: The CPU targets currently rely on `libffi` to invoke the "kernel" functions. Previously we would not build these if this dependency was not found. This patch copies th eapproach used for things like CUDA and HSA to dynamically load this if it is not found. The one sketchy thing this does is hard-code the default ABI for the target. These are normally defined on a per-file basis in the FFI source, so I had to fish out the expected values. We only use two types, so ideally we will always be able to use the default ABI. It's possible we could remove this dependency entirely in the future as well. --- .../Modules/LibomptargetGetDependencies.cmake | 48 +------- .../plugins-nextgen/CMakeLists.txt | 115 +++++++++--------- .../generic-elf-64bit/dynamic_ffi/ffi.cpp | 65 ++++++++++ .../generic-elf-64bit/dynamic_ffi/ffi.h | 78 ++++++++++++ .../generic-elf-64bit/src/rtl.cpp | 5 + 5 files changed, 209 insertions(+), 102 deletions(-) create mode 100644 openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.cpp create mode 100644 openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.h diff --git a/openmp/libomptarget/cmake/Modules/LibomptargetGetDependencies.cmake b/openmp/libomptarget/cmake/Modules/LibomptargetGetDependencies.cmake index 8c93bd586799..bbf2b9836c70 100644 --- a/openmp/libomptarget/cmake/Modules/LibomptargetGetDependencies.cmake +++ b/openmp/libomptarget/cmake/Modules/LibomptargetGetDependencies.cmake @@ -50,52 +50,8 @@ endif() ################################################################################ # Looking for libffi... ################################################################################ -find_package(PkgConfig) - -pkg_check_modules(LIBOMPTARGET_SEARCH_LIBFFI QUIET libffi) - -find_path ( - LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIR - NAMES - ffi.h - HINTS - ${LIBOMPTARGET_SEARCH_LIBFFI_INCLUDEDIR} - ${LIBOMPTARGET_SEARCH_LIBFFI_INCLUDE_DIRS} - PATHS - /usr/include - /usr/local/include - /opt/local/include - /sw/include - ENV CPATH) - -# Don't bother look for the library if the header files were not found. -if (LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIR) - find_library ( - LIBOMPTARGET_DEP_LIBFFI_LIBRARIES - NAMES - ffi - HINTS - ${LIBOMPTARGET_SEARCH_LIBFFI_LIBDIR} - ${LIBOMPTARGET_SEARCH_LIBFFI_LIBRARY_DIRS} - PATHS - /usr/lib - /usr/local/lib - /opt/local/lib - /sw/lib - ENV LIBRARY_PATH - ENV LD_LIBRARY_PATH) -endif() - -set(LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIRS ${LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIR}) -find_package_handle_standard_args( - LIBOMPTARGET_DEP_LIBFFI - DEFAULT_MSG - LIBOMPTARGET_DEP_LIBFFI_LIBRARIES - LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIRS) - -mark_as_advanced( - LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIRS - LIBOMPTARGET_DEP_LIBFFI_LIBRARIES) +find_package(FFI QUIET) +set(LIBOMPTARGET_DEP_LIBFFI_FOUND ${FFI_FOUND}) ################################################################################ # Looking for CUDA... diff --git a/openmp/libomptarget/plugins-nextgen/CMakeLists.txt b/openmp/libomptarget/plugins-nextgen/CMakeLists.txt index af2e5ef770f7..882be3025003 100644 --- a/openmp/libomptarget/plugins-nextgen/CMakeLists.txt +++ b/openmp/libomptarget/plugins-nextgen/CMakeLists.txt @@ -19,71 +19,74 @@ add_subdirectory(common) # - tmachine_libname: machine name to be appended to the plugin library name. macro(build_generic_elf64 tmachine tmachine_name tmachine_libname tmachine_triple elf_machine_id) if(CMAKE_SYSTEM_PROCESSOR MATCHES "${tmachine}$") - if(LIBOMPTARGET_DEP_LIBFFI_FOUND) - - libomptarget_say("Building ${tmachine_name} NextGen offloading plugin.") - - # Define macro to be used as prefix of the runtime messages for this target. - add_definitions("-DTARGET_NAME=${tmachine_name}") + # Define macro to be used as prefix of the runtime messages for this target. + add_definitions("-DTARGET_NAME=${tmachine_name}") - # Define debug prefix. TODO: This should be automatized in the Debug.h but - # it requires changing the original plugins. - add_definitions(-DDEBUG_PREFIX="TARGET ${tmachine_name} RTL") + # Define debug prefix. TODO: This should be automatized in the Debug.h but + # it requires changing the original plugins. + add_definitions(-DDEBUG_PREFIX="TARGET ${tmachine_name} RTL") - # Define macro with the ELF ID for this target. - add_definitions("-DTARGET_ELF_ID=${elf_machine_id}") + # Define the macro with the ELF e_machine for this target. + add_definitions("-DTARGET_ELF_ID=${elf_machine_id}") - # Define target regiple - add_definitions("-DLIBOMPTARGET_NEXTGEN_GENERIC_PLUGIN_TRIPLE=${tmachine}") + # Define target triple + add_definitions("-DLIBOMPTARGET_NEXTGEN_GENERIC_PLUGIN_TRIPLE=${tmachine}") - add_llvm_library("omptarget.rtl.${tmachine_libname}" - SHARED + add_llvm_library("omptarget.rtl.${tmachine_libname}" + SHARED - ${CMAKE_CURRENT_SOURCE_DIR}/../generic-elf-64bit/src/rtl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/../generic-elf-64bit/src/rtl.cpp - ADDITIONAL_HEADER_DIRS + ADDITIONAL_HEADER_DIRS ${LIBOMPTARGET_INCLUDE_DIR} - ${LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIR} - - LINK_LIBS - PRIVATE - PluginCommon - ${LIBOMPTARGET_DEP_LIBFFI_LIBRARIES} - ${OPENMP_PTHREAD_LIB} - - NO_INSTALL_RPATH - ) - - if ((OMPT_TARGET_DEFAULT) AND (LIBOMPTARGET_OMPT_SUPPORT)) - target_link_libraries("omptarget.rtl.${tmachine_libname}" PRIVATE OMPT) - endif() - - if (LIBOMP_HAVE_VERSION_SCRIPT_FLAG) - target_link_libraries("omptarget.rtl.${tmachine_libname}" PRIVATE - "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/../exports") - endif() - - # Install plugin under the lib destination folder. - install(TARGETS "omptarget.rtl.${tmachine_libname}" - LIBRARY DESTINATION "${OPENMP_INSTALL_LIBDIR}") - set_target_properties("omptarget.rtl.${tmachine_libname}" PROPERTIES - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/.." - POSITION_INDEPENDENT_CODE ON - CXX_VISIBILITY_PRESET protected) - - target_include_directories( "omptarget.rtl.${tmachine_libname}" PRIVATE - ${LIBOMPTARGET_INCLUDE_DIR} - ${LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIR}) - list(APPEND LIBOMPTARGET_TESTED_PLUGINS "omptarget.rtl.${tmachine_libname}") - set(LIBOMPTARGET_TESTED_PLUGINS - "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE) - set(LIBOMPTARGET_SYSTEM_TARGETS - "${LIBOMPTARGET_SYSTEM_TARGETS} ${tmachine_triple} ${tmachine_triple}-LTO" PARENT_SCOPE) + LINK_LIBS + PRIVATE + PluginCommon + ${OPENMP_PTHREAD_LIB} + + NO_INSTALL_RPATH + ) - else(LIBOMPTARGET_DEP_LIBFFI_FOUND) - libomptarget_say("Not building ${tmachine_name} NextGen offloading plugin: libffi dependency not found.") - endif(LIBOMPTARGET_DEP_LIBFFI_FOUND) + if(LIBOMPTARGET_DEP_LIBFFI_FOUND) + libomptarget_say("Building ${tmachine_libname} plugin linked with libffi") + target_link_libraries("omptarget.rtl.${tmachine_libname}" PRIVATE + ${FFI_LIBRARIES}) + target_include_directories("omptarget.rtl.${tmachine_libname}" PRIVATE + ${FFI_INCLUDE_DIRS}) + else() + libomptarget_say("Building ${tmachine_libname} plugie for dlopened libffi") + target_sources("omptarget.rtl.${tmachine_libname}" PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/../generic-elf-64bit/dynamic_ffi/ffi.cpp) + target_include_directories("omptarget.rtl.${tmachine_libname}" PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/../generic-elf-64bit/dynamic_ffi) + endif() + + if(OMPT_TARGET_DEFAULT AND LIBOMPTARGET_OMPT_SUPPORT) + target_link_libraries("omptarget.rtl.${tmachine_libname}" PRIVATE OMPT) + endif() + + if(LIBOMP_HAVE_VERSION_SCRIPT_FLAG) + target_link_libraries("omptarget.rtl.${tmachine_libname}" PRIVATE + "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/../exports") + endif() + + # Install plugin under the lib destination folder. + install(TARGETS "omptarget.rtl.${tmachine_libname}" + LIBRARY DESTINATION "${OPENMP_INSTALL_LIBDIR}") + set_target_properties("omptarget.rtl.${tmachine_libname}" PROPERTIES + INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/.." + POSITION_INDEPENDENT_CODE ON + CXX_VISIBILITY_PRESET protected) + + target_include_directories("omptarget.rtl.${tmachine_libname}" PRIVATE + ${LIBOMPTARGET_INCLUDE_DIR}) + + list(APPEND LIBOMPTARGET_TESTED_PLUGINS "omptarget.rtl.${tmachine_libname}") + set(LIBOMPTARGET_TESTED_PLUGINS + "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE) + set(LIBOMPTARGET_SYSTEM_TARGETS + "${LIBOMPTARGET_SYSTEM_TARGETS} ${tmachine_triple} ${tmachine_triple}-LTO" PARENT_SCOPE) else() libomptarget_say("Not building ${tmachine_name} NextGen offloading plugin: machine not found in the system.") endif() diff --git a/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.cpp b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.cpp new file mode 100644 index 000000000000..c79daa798581 --- /dev/null +++ b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.cpp @@ -0,0 +1,65 @@ +//===--- generic-elf-64bit/dynamic_ffi/ffi.cpp -------------------- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Implement subset of the FFI api by calling into the FFI library via dlopen +// +//===----------------------------------------------------------------------===// + +#include "llvm/Support/DynamicLibrary.h" +#include + +#include "DLWrap.h" +#include "ffi.h" + +DLWRAP_INITIALIZE() + +DLWRAP(ffi_call, 4); +DLWRAP(ffi_prep_cif, 5); + +DLWRAP_FINALIZE() + +ffi_type ffi_type_void; +ffi_type ffi_type_pointer; + +// Name of the FFI shared library. +constexpr const char *FFI_PATH = "libffi.so"; + +#define DYNAMIC_FFI_SUCCESS 0 +#define DYNAMIC_FFI_FAIL 1 + +// Initializes the dynamic FFI wrapper. +uint32_t ffi_init() { + std::string ErrMsg; + auto DynlibHandle = std::make_unique( + llvm::sys::DynamicLibrary::getPermanentLibrary(FFI_PATH, &ErrMsg)); + if (!DynlibHandle->isValid()) + return DYNAMIC_FFI_FAIL; + + for (size_t I = 0; I < dlwrap::size(); I++) { + const char *Sym = dlwrap::symbol(I); + + void *P = DynlibHandle->getAddressOfSymbol(Sym); + if (P == nullptr) + return DYNAMIC_FFI_FAIL; + + *dlwrap::pointer(I) = P; + } + +#define DYNAMIC_INIT(SYMBOL) \ + { \ + void *SymbolPtr = DynlibHandle->getAddressOfSymbol(#SYMBOL); \ + if (!SymbolPtr) \ + return DYNAMIC_FFI_FAIL; \ + SYMBOL = *reinterpret_cast(SymbolPtr); \ + } + DYNAMIC_INIT(ffi_type_void); + DYNAMIC_INIT(ffi_type_pointer); +#undef DYNAMIC_INIT + + return DYNAMIC_FFI_SUCCESS; +} diff --git a/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.h b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.h new file mode 100644 index 000000000000..0ae025805e1d --- /dev/null +++ b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/dynamic_ffi/ffi.h @@ -0,0 +1,78 @@ +//===--- generic-elf-64bit/dynamic_ffi/ffi.cpp -------------------- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Provides a mirror to the parts of the FFI interface that the plugins require. +// +// libffi +// - Copyright (c) 2011, 2014, 2019, 2021, 2022 Anthony Green +// - Copyright (c) 1996-2003, 2007, 2008 Red Hat, Inc. +// +//===----------------------------------------------------------------------===// + +#ifndef DYNAMIC_FFI_FFI_H +#define DYNAMIC_FFI_FFI_H + +#include +#include + +#define USES_DYNAMIC_FFI + +uint32_t ffi_init(); + +typedef struct _ffi_type { + size_t size; + unsigned short alignment; + unsigned short type; + struct _ffi_type **elements; +} ffi_type; + +typedef enum { + FFI_OK = 0, + FFI_BAD_TYPEDEF, + FFI_BAD_ABI, + FFI_BAD_ARGTYPE +} ffi_status; + +// These are target depenent so we set them manually for each ABI by referencing +// the FFI source. +typedef enum ffi_abi { +#if (defined(_M_X64) || defined(__x86_64__)) + FFI_DEFAULT_ABI = 2, // FFI_UNIX64. +#elif defined(__aarch64__) || defined(__arm64__) || defined(_M_ARM64) + FFI_DEFAULT_ABI = 1, // FFI_SYSV. +#elif defined(__powerpc64__) + FFI_DEFAULT_ABI = 8, // FFI_LINUX. +#elif defined(__s390x__) + FFI_DEFAULT_ABI = 1, // FFI_SYSV. +#else +#error "Unknown ABI" +#endif +} ffi_cif; + +#ifdef __cplusplus +extern "C" { +#endif + +#define FFI_EXTERN extern +#define FFI_API + +FFI_EXTERN ffi_type ffi_type_void; +FFI_EXTERN ffi_type ffi_type_pointer; + +FFI_API +void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue); + +FFI_API +ffi_status ffi_prep_cif(ffi_cif *cif, ffi_abi abi, unsigned int nargs, + ffi_type *rtype, ffi_type **atypes); + +#ifdef __cplusplus +} +#endif + +#endif // DYNAMIC_FFI_FFI_H diff --git a/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp index 43569f250555..7f66b6827bce 100644 --- a/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp @@ -383,6 +383,11 @@ struct GenELF64PluginTy final : public GenericPluginTy { ompt::connectLibrary(); #endif +#ifdef USES_DYNAMIC_FFI + if (auto Err = Plugin::check(ffi_init(), "Failed to initialize libffi")) + return std::move(Err); +#endif + return NUM_DEVICES; } -- GitLab From 340cc1702e21128b62799c5dfbf2875c3c2c96a1 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 10 Jan 2024 01:34:13 +0530 Subject: [PATCH 258/652] [LLVM][NVPTX]: Add intrinsic for setmaxnreg (#77289) This patch adds an intrinsic for setmaxnreg PTX instruction. * PTX Doc link for this instruction: https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-setmaxnreg * The i32 argument, an immediate value, specifies the actual absolute register count for the instruction. * The `setmaxnreg` instruction is available in SM90a. So, this patch adds 'hasSM90a' predicate to use in the NVPTX backend. * lit tests are added to verify the lowering of the intrinsic. * Verifier logic (and tests) are added to test the register count range and divisibility-by-8 requirements. Signed-off-by: Durgadoss R --- llvm/include/llvm/IR/IntrinsicsNVVM.td | 10 ++++++++++ llvm/lib/IR/Verifier.cpp | 11 +++++++++++ llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 3 +++ llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 13 +++++++++++++ llvm/test/CodeGen/NVPTX/setmaxnreg.ll | 16 ++++++++++++++++ llvm/test/Verifier/NVPTX/lit.local.cfg | 2 ++ llvm/test/Verifier/NVPTX/setmaxnreg.ll | 14 ++++++++++++++ 7 files changed, 69 insertions(+) create mode 100644 llvm/test/CodeGen/NVPTX/setmaxnreg.ll create mode 100644 llvm/test/Verifier/NVPTX/lit.local.cfg create mode 100644 llvm/test/Verifier/NVPTX/setmaxnreg.ll diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td index 6fd8e80013ce..cf50f2a59f60 100644 --- a/llvm/include/llvm/IR/IntrinsicsNVVM.td +++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td @@ -4710,4 +4710,14 @@ def int_nvvm_is_explicit_cluster [IntrNoMem, IntrSpeculatable, NoUndef], "llvm.nvvm.is_explicit_cluster">; +// Setmaxnreg inc/dec intrinsics +def int_nvvm_setmaxnreg_inc_sync_aligned_u32 + : DefaultAttrsIntrinsic<[], [llvm_i32_ty], + [IntrConvergent, IntrNoMem, IntrHasSideEffects, ImmArg>], + "llvm.nvvm.setmaxnreg.inc.sync.aligned.u32">; +def int_nvvm_setmaxnreg_dec_sync_aligned_u32 + : DefaultAttrsIntrinsic<[], [llvm_i32_ty], + [IntrConvergent, IntrNoMem, IntrHasSideEffects, ImmArg>], + "llvm.nvvm.setmaxnreg.dec.sync.aligned.u32">; + } // let TargetPrefix = "nvvm" diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index aeaca21a99cc..b6ad85b2d46e 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -96,6 +96,7 @@ #include "llvm/IR/IntrinsicsAArch64.h" #include "llvm/IR/IntrinsicsAMDGPU.h" #include "llvm/IR/IntrinsicsARM.h" +#include "llvm/IR/IntrinsicsNVPTX.h" #include "llvm/IR/IntrinsicsWebAssembly.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/Metadata.h" @@ -6031,6 +6032,16 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) { "Value for inactive lanes must be a VGPR function argument", &Call); break; } + case Intrinsic::nvvm_setmaxnreg_inc_sync_aligned_u32: + case Intrinsic::nvvm_setmaxnreg_dec_sync_aligned_u32: { + Value *V = Call.getArgOperand(0); + unsigned RegCount = cast(V)->getZExtValue(); + Check(RegCount % 8 == 0, + "reg_count argument to nvvm.setmaxnreg must be in multiples of 8"); + Check((RegCount >= 24 && RegCount <= 256), + "reg_count argument to nvvm.setmaxnreg must be within [24, 256]"); + break; + } case Intrinsic::experimental_convergence_entry: LLVM_FALLTHROUGH; case Intrinsic::experimental_convergence_anchor: diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td index 13665985f52e..e1cced327544 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td @@ -164,6 +164,9 @@ def True : Predicate<"true">; class hasPTX: Predicate<"Subtarget->getPTXVersion() >= " # version>; class hasSM: Predicate<"Subtarget->getSmVersion() >= " # version>; +// Explicit records for arch-accelerated SM versions +def hasSM90a : Predicate<"Subtarget->getFullSmVersion() == 901">; + // non-sync shfl instructions are not available on sm_70+ in PTX6.4+ def hasSHFL : Predicate<"!(Subtarget->getSmVersion() >= 70" "&& Subtarget->getPTXVersion() >= 64)">; diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td index 85eae44f349a..6b062a7f3912 100644 --- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td +++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td @@ -6727,3 +6727,16 @@ def is_explicit_cluster: NVPTXInst<(outs Int1Regs:$d), (ins), "mov.pred\t$d, %is_explicit_cluster;", [(set Int1Regs:$d, (int_nvvm_is_explicit_cluster))]>, Requires<[hasSM<90>, hasPTX<78>]>; + +// setmaxnreg inc/dec intrinsics +let isConvergent = true in { +multiclass SET_MAXNREG { + def : NVPTXInst<(outs), (ins i32imm:$reg_count), + "setmaxnreg." # Action # ".sync.aligned.u32 $reg_count;", + [(Intr timm:$reg_count)]>, + Requires<[hasSM90a, hasPTX<80>]>; +} + +defm INT_SET_MAXNREG_INC : SET_MAXNREG<"inc", int_nvvm_setmaxnreg_inc_sync_aligned_u32>; +defm INT_SET_MAXNREG_DEC : SET_MAXNREG<"dec", int_nvvm_setmaxnreg_dec_sync_aligned_u32>; +} // isConvergent diff --git a/llvm/test/CodeGen/NVPTX/setmaxnreg.ll b/llvm/test/CodeGen/NVPTX/setmaxnreg.ll new file mode 100644 index 000000000000..9025e11fd42e --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/setmaxnreg.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=nvptx64 -mcpu=sm_90a -mattr=+ptx80| FileCheck --check-prefixes=CHECK %s +; RUN: %if ptxas-12.0 %{ llc < %s -march=nvptx64 -mcpu=sm_90a -mattr=+ptx80| %ptxas-verify -arch=sm_90a %} + +declare void @llvm.nvvm.setmaxnreg.inc.sync.aligned.u32(i32 %reg_count) +declare void @llvm.nvvm.setmaxnreg.dec.sync.aligned.u32(i32 %reg_count) + +; CHECK-LABEL: test_set_maxn_reg +define void @test_set_maxn_reg() { + ; CHECK: setmaxnreg.inc.sync.aligned.u32 96; + call void @llvm.nvvm.setmaxnreg.inc.sync.aligned.u32(i32 96) + + ; CHECK: setmaxnreg.dec.sync.aligned.u32 64; + call void @llvm.nvvm.setmaxnreg.dec.sync.aligned.u32(i32 64) + + ret void +} diff --git a/llvm/test/Verifier/NVPTX/lit.local.cfg b/llvm/test/Verifier/NVPTX/lit.local.cfg new file mode 100644 index 000000000000..0d37b86e1c8e --- /dev/null +++ b/llvm/test/Verifier/NVPTX/lit.local.cfg @@ -0,0 +1,2 @@ +if not "NVPTX" in config.root.targets: + config.unsupported = True diff --git a/llvm/test/Verifier/NVPTX/setmaxnreg.ll b/llvm/test/Verifier/NVPTX/setmaxnreg.ll new file mode 100644 index 000000000000..8999e4ffa667 --- /dev/null +++ b/llvm/test/Verifier/NVPTX/setmaxnreg.ll @@ -0,0 +1,14 @@ +; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s + +declare void @llvm.nvvm.setmaxnreg.inc.sync.aligned.u32(i32 %reg_count) +declare void @llvm.nvvm.setmaxnreg.dec.sync.aligned.u32(i32 %reg_count) + +define void @test_set_maxn_reg() { + ; CHECK: reg_count argument to nvvm.setmaxnreg must be in multiples of 8 + call void @llvm.nvvm.setmaxnreg.inc.sync.aligned.u32(i32 95) + + ; CHECK: reg_count argument to nvvm.setmaxnreg must be within [24, 256] + call void @llvm.nvvm.setmaxnreg.dec.sync.aligned.u32(i32 16) + + ret void +} -- GitLab From 47605ffec8864e989905027b2f56277e2dc8b8fa Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Tue, 9 Jan 2024 12:04:20 -0800 Subject: [PATCH 259/652] [lldb] Fix a warning This patch fixes: lldb/source/Target/ProcessTrace.cpp:23:33: error: extra ';' outside of a function is incompatible with C++98 [-Werror,-Wc++98-compat-extra-semi] --- lldb/source/Target/ProcessTrace.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/source/Target/ProcessTrace.cpp b/lldb/source/Target/ProcessTrace.cpp index 054e34a46de2..3a41f257627c 100644 --- a/lldb/source/Target/ProcessTrace.cpp +++ b/lldb/source/Target/ProcessTrace.cpp @@ -20,7 +20,7 @@ using namespace lldb; using namespace lldb_private; -LLDB_PLUGIN_DEFINE(ProcessTrace); +LLDB_PLUGIN_DEFINE(ProcessTrace) llvm::StringRef ProcessTrace::GetPluginDescriptionStatic() { return "Trace process plug-in."; -- GitLab From fb1466216889e9f4d884a387f430d2e85b4542f6 Mon Sep 17 00:00:00 2001 From: Ralf Jung Date: Tue, 9 Jan 2024 21:41:24 +0100 Subject: [PATCH 260/652] LangRef: rint, nearbyint: mention that default rounding mode is assumed (#77191) LLVM assumes round-to-nearest mode and sometimes performs constant-folding based on that assumption. This updates the language ref documentation for the rint and nearbyint intrinsics to mention that fact. --- llvm/docs/LangRef.rst | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index c90b6becae52..2722333c710c 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -15754,7 +15754,11 @@ Semantics: """""""""" This function returns the same values as the libm ``rint`` functions -would, and handles error conditions in the same way. +would, and handles error conditions in the same way. Since LLVM assumes the +:ref:`default floating-point environment `, the rounding mode is +assumed to be set to "nearest", so halfway cases are rounded to the even +integer. Use :ref:`Constrained Floating-Point Intrinsics ` +to avoid that assumption. .. _int_nearbyint: @@ -15792,7 +15796,11 @@ Semantics: """""""""" This function returns the same values as the libm ``nearbyint`` -functions would, and handles error conditions in the same way. +functions would, and handles error conditions in the same way. Since LLVM +assumes the :ref:`default floating-point environment `, the rounding +mode is assumed to be set to "nearest", so halfway cases are rounded to the even +integer. Use :ref:`Constrained Floating-Point Intrinsics ` to +avoid that assumption. .. _int_round: -- GitLab From baa8c2abcd8da31549996458c9df4871454b0673 Mon Sep 17 00:00:00 2001 From: sethp Date: Tue, 9 Jan 2024 12:45:57 -0800 Subject: [PATCH 261/652] [Clang] Wide delimiters ('{{{') for expect strings (#77326) Prior to this commit, it was impossible to use the simple string matching directives to look for any content that contains unbalanced `{{` `}}` pairs, such as: ``` // expected-note {{my_struct{{1}, 2}}} ``` Which would parse like so: ``` "nested" brace v // expected-note {{my_struct{{1}, 2}}} closes the nested brace ^ | trailing } ``` And the frontend would complain 'cannot find end ('}}') of expected'. At this snapshot, VerifyDiagnosticConsumer's parser now counts the opening braces and looks for a matching length of closing sigils, allowing the above to be written as: ``` // expected-note {{{my_struct{{1}, 2}}}} opening brace |-| |-| closing brace is '}}}', found here ^ ``` This came about as a result of this discussion: https://github.com/llvm/llvm-project/pull/74852#discussion_r1443117644 cc @erichkeane --- clang/docs/InternalsManual.rst | 34 +++++++++++++++++-- .../clang/Basic/DiagnosticFrontendKinds.td | 2 +- .../lib/Frontend/VerifyDiagnosticConsumer.cpp | 15 +++++--- clang/test/Frontend/verify.c | 30 ++++++++++++++++ 4 files changed, 74 insertions(+), 7 deletions(-) diff --git a/clang/docs/InternalsManual.rst b/clang/docs/InternalsManual.rst index 05fadf5a0344..a866f621c100 100644 --- a/clang/docs/InternalsManual.rst +++ b/clang/docs/InternalsManual.rst @@ -3364,7 +3364,7 @@ Multiple occurrences accumulate prefixes. For example, Specifying Diagnostics ^^^^^^^^^^^^^^^^^^^^^^ -Indicating that a line expects an error or a warning is simple. Put a comment +Indicating that a line expects an error or a warning is easy. Put a comment on the line that has the diagnostic, use ``expected-{error,warning,remark,note}`` to tag if it's an expected error, warning, remark, or note (respectively), and place the expected text between @@ -3373,6 +3373,9 @@ enough to ensure that the correct diagnostic was emitted. (Note: full text should be included in test cases unless there is a compelling reason to use truncated text instead.) +For a full description of the matching behavior, including more complex +matching scenarios, see :ref:`matching ` below. + Here's an example of the most commonly used way to specify expected diagnostics: @@ -3458,8 +3461,33 @@ A range can also be specified by ``-``. For example: In this example, the diagnostic may appear only once, if at all. +.. _DiagnosticMatching: + +Matching Modes +~~~~~~~~~~~~~~ + +The default matching mode is simple string, which looks for the expected text +that appears between the first `{{` and `}}` pair of the comment. The string is +interpreted just as-is, with one exception: the sequence `\n` is converted to a +single newline character. This mode matches the emitted diagnostic when the +text appears as a substring at any position of the emitted message. + +To enable matching against desired strings that contain `}}` or `{{`, the +string-mode parser accepts opening delimiters of more than two curly braces, +like `{{{`. It then looks for a closing delimiter of equal "width" (i.e `}}}`). +For example: + +.. code-block:: c++ + + // expected-note {{{evaluates to '{{2, 3, 4}} == {0, 3, 4}'}}} + +The intent is to allow the delimeter to be wider than the longest `{` or `}` +brace sequence in the content, so that if your expected text contains `{{{` +(three braces) it may be delimited with `{{{{` (four braces), and so on. + Regex matching mode may be selected by appending ``-re`` to the diagnostic type -and including regexes wrapped in double curly braces in the directive, such as: +and including regexes wrapped in double curly braces (`{{` and `}}`) in the +directive, such as: .. code-block:: text @@ -3471,6 +3499,8 @@ Examples matching error: "variable has incomplete type 'struct s'" // expected-error {{variable has incomplete type 'struct s'}} // expected-error {{variable has incomplete type}} + // expected-error {{{variable has incomplete type}}} + // expected-error {{{{variable has incomplete type}}}} // expected-error-re {{variable has type 'struct {{.}}'}} // expected-error-re {{variable has type 'struct {{.*}}'}} diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td b/clang/include/clang/Basic/DiagnosticFrontendKinds.td index 568000106a84..85ecfdf9de62 100644 --- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td +++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td @@ -167,7 +167,7 @@ def err_verify_no_such_marker : Error< def err_verify_missing_start : Error< "cannot find start ('{{') of expected %0">; def err_verify_missing_end : Error< - "cannot find end ('}}') of expected %0">; + "cannot find end ('%1') of expected %0">; def err_verify_invalid_content : Error< "invalid expected %0: %1">; def err_verify_missing_regex : Error< diff --git a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp index 8a3d2286cd16..f508408ba706 100644 --- a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp +++ b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp @@ -611,12 +611,19 @@ static bool ParseDirective(StringRef S, ExpectedData *ED, SourceManager &SM, diag::err_verify_missing_start) << KindStr; continue; } + llvm::SmallString<8> CloseBrace("}}"); + const char *const DelimBegin = PH.C; PH.Advance(); + // Count the number of opening braces for `string` kinds + for (; !D.RegexKind && PH.Next("{"); PH.Advance()) + CloseBrace += '}'; const char* const ContentBegin = PH.C; // mark content begin - // Search for token: }} - if (!PH.SearchClosingBrace("{{", "}}")) { - Diags.Report(Pos.getLocWithOffset(PH.C-PH.Begin), - diag::err_verify_missing_end) << KindStr; + // Search for closing brace + StringRef OpenBrace(DelimBegin, ContentBegin - DelimBegin); + if (!PH.SearchClosingBrace(OpenBrace, CloseBrace)) { + Diags.Report(Pos.getLocWithOffset(PH.C - PH.Begin), + diag::err_verify_missing_end) + << KindStr << CloseBrace; continue; } const char* const ContentEnd = PH.P; // mark content end diff --git a/clang/test/Frontend/verify.c b/clang/test/Frontend/verify.c index 221b715c19e4..c549011d7b7a 100644 --- a/clang/test/Frontend/verify.c +++ b/clang/test/Frontend/verify.c @@ -157,3 +157,33 @@ unexpected b; // expected-error@33 1-1 {{unknown type}} // what-error {{huh?}} // CHECK9: error: 'what-error' diagnostics expected but not seen: #endif + +#ifdef TEST_WIDE_DELIM +// RUN: not %clang_cc1 -DTEST_WIDE_DELIM -verify %s 2>&1 | FileCheck -check-prefix=CHECK-WIDE-DELIM %s + +// expected-error {{{some message with {{}} in it}}} +// expected-error {{{some message with {}} in it}}} +// expected-error {{{some message with {{} in it}}} + +// expected-error-re {{{some {{.*}} regex with double braces}}} +// expected-error-re {{{some message with {{} in it}}} + +// expected-error {{{mismatched delim}} +// expected-error-re {{{mismatched re {{.*} }}} +// expected-error-re {{{no regex}}} + +#if 0 +// CHECK-WIDE-DELIM: error: 'expected-error' diagnostics expected but not seen: +// CHECK-WIDE-DELIM-NEXT: verify.c Line 164: some message with {{[{]{}[}]}} in it +// CHECK-WIDE-DELIM-NEXT: verify.c Line 165: some message with {}} in it +// CHECK-WIDE-DELIM-NEXT: verify.c Line 166: some message with {{[{]{[}]}} in it +// CHECK-WIDE-DELIM-NEXT: verify.c Line 168: {some {{.*}} regex with double braces +// CHECK-WIDE-DELIM-NEXT: error: 'expected-error' diagnostics seen but not expected: +// CHECK-WIDE-DELIM-NEXT: verify.c Line 169: cannot find end ('}}') of expected regex +// CHECK-WIDE-DELIM-NEXT: verify.c Line 171: cannot find end ('}}}') of expected string +// CHECK-WIDE-DELIM-NEXT: verify.c Line 172: cannot find end ('}}') of expected regex +// CHECK-WIDE-DELIM-NEXT: verify.c Line 173: cannot find start of regex ('{{[{][{]}}') in {no regex +// CHECK-WIDE-DELIM-NEXT: 8 errors generated. +#endif + +#endif -- GitLab From 3a8a9267c5ee75e0d1e2f00662d2b913e1dba8d1 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Tue, 9 Jan 2024 12:54:39 -0800 Subject: [PATCH 262/652] [Instrumentation] Remove redundant LLVM_DEBUG (NFC) --- .../lib/Transforms/Instrumentation/PGOInstrumentation.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp index 6b95c7028d93..44167f4b471c 100644 --- a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp +++ b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp @@ -658,10 +658,10 @@ void FuncPGOInstrumentation::computeCFGHash() { << " CRC = " << JC.getCRC() << ", Selects = " << SIVisitor.getNumOfSelectInsts() << ", Edges = " << MST.numEdges() << ", ICSites = " - << ValueSites[IPVK_IndirectCallTarget].size()); - LLVM_DEBUG(dbgs() << ", Memops = " << ValueSites[IPVK_MemOPSize].size() - << ", High32 CRC = " << JCH.getCRC()); - LLVM_DEBUG(dbgs() << ", Hash = " << FunctionHash << "\n";); + << ValueSites[IPVK_IndirectCallTarget].size() + << ", Memops = " << ValueSites[IPVK_MemOPSize].size() + << ", High32 CRC = " << JCH.getCRC() + << ", Hash = " << FunctionHash << "\n";); if (PGOTraceFuncHash != "-" && F.getName().contains(PGOTraceFuncHash)) dbgs() << "Funcname=" << F.getName() << ", Hash=" << FunctionHash -- GitLab From cd101ab76bdee8d2583ae7b0dfbae9a745373731 Mon Sep 17 00:00:00 2001 From: Nic Date: Tue, 9 Jan 2024 16:29:00 -0500 Subject: [PATCH 263/652] [LangRef] Tweak description of `@llvm.is.constant.*` (#77519) Fixes #77517 --- llvm/docs/LangRef.rst | 3 --- 1 file changed, 3 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 2722333c710c..d881deb30049 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -27228,9 +27228,6 @@ obviously not constant. However, a call like function is inlined, if the value passed to the function parameter was a constant. -On the other hand, if constant folding is not run, it will never -evaluate to true, even in simple cases. - .. _int_ptrmask: '``llvm.ptrmask``' Intrinsic -- GitLab From ab590377a371d8099829f77ab4e67c24f8740bd9 Mon Sep 17 00:00:00 2001 From: Boian Petkantchin Date: Tue, 9 Jan 2024 13:42:56 -0800 Subject: [PATCH 264/652] [mlir][mesh] Add folding of ClusterShapeOp (#77033) If the mesh has static size on some of the requested axes, the result is substituted with a constant. --- .../Dialect/Mesh/Transforms/Simplifications.h | 10 +- .../Mesh/Transforms/Simplifications.cpp | 93 ++++++++++++++++++- mlir/test/Dialect/Mesh/folding.mlir | 22 +++++ mlir/test/lib/Dialect/Mesh/CMakeLists.txt | 2 +- .../lib/Dialect/Mesh/TestSimplifications.cpp | 8 +- mlir/tools/mlir-opt/CMakeLists.txt | 2 +- 6 files changed, 131 insertions(+), 6 deletions(-) create mode 100644 mlir/test/Dialect/Mesh/folding.mlir diff --git a/mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h b/mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h index f70bdaa9de0a..f438465251bb 100644 --- a/mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h +++ b/mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h @@ -19,6 +19,9 @@ #include namespace mlir { + +class SymbolTableCollection; + namespace mesh { // If we have an algebraic op like "+" and a summing all-reduce, @@ -102,7 +105,12 @@ void populateAllReduceEndomorphismSimplificationPatterns( AlgebraicOp::getOperationName(), 1, patterns.getContext())); } -void populateSimplificationPatterns(RewritePatternSet &patterns); +// It is invalid to change ops that declare symbols during the application of +// these patterns, because symbolTableCollection is used to cache them. +void populateSimplificationPatterns( + RewritePatternSet &patterns, SymbolTableCollection &symbolTableCollection); +void populateFoldingPatterns(RewritePatternSet &patterns, + SymbolTableCollection &symbolTableCollection); } // namespace mesh } // namespace mlir diff --git a/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp b/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp index 643bd7b8e77c..6262d3aa1626 100644 --- a/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp +++ b/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp @@ -8,11 +8,23 @@ #include "mlir/Dialect/Mesh/Transforms/Simplifications.h" #include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Mesh/IR/MeshOps.h" +#include "mlir/IR/BuiltinTypeInterfaces.h" +#include "mlir/IR/ImplicitLocOpBuilder.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/IR/SymbolTable.h" +#include "mlir/Support/LogicalResult.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include +#include +#include namespace mlir { namespace mesh { -void populateSimplificationPatterns(RewritePatternSet &patterns) { +void populateSimplificationPatterns( + RewritePatternSet &patterns, SymbolTableCollection &symbolTableCollection) { populateAllReduceEndomorphismSimplificationPatterns( patterns, Partial::Sum); populateAllReduceEndomorphismSimplificationPatterns( @@ -33,6 +45,85 @@ void populateSimplificationPatterns(RewritePatternSet &patterns) { patterns, Partial::Max); // TODO: add simplifications for all-gather and other collectives. + + populateFoldingPatterns(patterns, symbolTableCollection); +} + +namespace { + +// This folding can not be done with an operation's fold method or +// DialectFoldInterface, because it needs a SymbolTableCollection to cache the +// symbol tables. +// We can't use DialectFoldInterface since the cache may be invalidated by some +// pass changing the referenced ClusterOp ops. +struct ClusterShapeFolder : OpRewritePattern { + template + ClusterShapeFolder(SymbolTableCollection &symbolTableCollection, + OpRewritePatternArgs &&...opRewritePatternArgs) + : OpRewritePattern( + std::forward(opRewritePatternArgs)...), + symbolTableCollection(symbolTableCollection) {} + LogicalResult matchAndRewrite(ClusterShapeOp op, + PatternRewriter &rewriter) const override { + ImplicitLocOpBuilder builder(op->getLoc(), rewriter); + ClusterOp mesh = + symbolTableCollection.lookupNearestSymbolFrom( + op.getOperation(), op.getMeshAttr()); + if (!mesh) { + return failure(); + } + ArrayRef opMeshAxes = op.getAxes(); + SmallVector opAxesIota; + if (opMeshAxes.empty()) { + opAxesIota.resize(mesh.getRank()); + std::iota(opAxesIota.begin(), opAxesIota.end(), 0); + opMeshAxes = opAxesIota; + } + if (llvm::all_of(opMeshAxes, [&mesh](MeshAxis axis) { + return ShapedType::isDynamic(mesh.getDimSizes()[axis]); + })) { + // All mesh dimensions are dynamic. Nothing to fold. + return failure(); + } + + SmallVector newResults(op->getResults().size()); + SmallVector newShapeOpMeshAxes; + SmallVector newToOldResultsIndexMap; + + for (size_t i = 0; i < opMeshAxes.size(); ++i) { + auto meshAxisSize = mesh.getDimSizes()[opMeshAxes[i]]; + if (ShapedType::isDynamic(meshAxisSize)) { + newToOldResultsIndexMap.push_back(i); + newShapeOpMeshAxes.push_back(opMeshAxes[i]); + } else { + // Fold static mesh axes. + newResults[i] = builder.create( + builder.getIndexAttr(meshAxisSize)); + } + } + + // Leave only the dynamic mesh axes to be queried. + ClusterShapeOp newShapeOp = + builder.create(mesh.getSymName(), newShapeOpMeshAxes); + for (size_t i = 0; i < newShapeOp->getResults().size(); ++i) { + newResults[newToOldResultsIndexMap[i]] = newShapeOp->getResults()[i]; + } + + rewriter.replaceAllUsesWith(op.getResults(), newResults); + + return success(); + } + +private: + SymbolTableCollection &symbolTableCollection; +}; + +} // namespace + +void populateFoldingPatterns(RewritePatternSet &patterns, + SymbolTableCollection &symbolTableCollection) { + patterns.add(symbolTableCollection, + patterns.getContext()); } } // namespace mesh diff --git a/mlir/test/Dialect/Mesh/folding.mlir b/mlir/test/Dialect/Mesh/folding.mlir new file mode 100644 index 000000000000..dd64d746341b --- /dev/null +++ b/mlir/test/Dialect/Mesh/folding.mlir @@ -0,0 +1,22 @@ +// RUN: mlir-opt -test-mesh-simplifications %s | FileCheck %s + +mesh.cluster @mesh0(rank = 3, dim_sizes = 4x?x2) +mesh.cluster @mesh1(rank = 2, dim_sizes = 2x3) + +// CHECK-LABEL: func.func @cluster_shape_op_folding +func.func @cluster_shape_op_folding() -> (index, index) { + // CHECK: %[[AXIS_2_SIZE:.*]] = arith.constant 2 : index + // CHECK: %[[AXIS_1_SIZE:.*]] = mesh.cluster_shape @mesh0 axes = [1] : index + %0:2 = mesh.cluster_shape @mesh0 axes = [2, 1] : index, index + // CHECK: return %[[AXIS_2_SIZE]], %[[AXIS_1_SIZE]] + return %0#0, %0#1 : index, index +} + +// CHECK-LABEL: func.func @cluster_shape_op_folding_all_axes_static_mesh +func.func @cluster_shape_op_folding_all_axes_static_mesh() -> (index, index) { + // CHECK: %[[AXIS_0_SIZE:.*]] = arith.constant 2 : index + // CHECK: %[[AXIS_1_SIZE:.*]] = arith.constant 3 : index + %0:2 = mesh.cluster_shape @mesh1 : index, index + // CHECK: return %[[AXIS_0_SIZE]], %[[AXIS_1_SIZE]] + return %0#0, %0#1 : index, index +} diff --git a/mlir/test/lib/Dialect/Mesh/CMakeLists.txt b/mlir/test/lib/Dialect/Mesh/CMakeLists.txt index f14d282857a1..daff88235b5b 100644 --- a/mlir/test/lib/Dialect/Mesh/CMakeLists.txt +++ b/mlir/test/lib/Dialect/Mesh/CMakeLists.txt @@ -1,5 +1,5 @@ # Exclude tests from libMLIR.so -add_mlir_library(MLIRMeshTestSimplifications +add_mlir_library(MLIRMeshTest TestReshardingSpmdization.cpp TestSimplifications.cpp diff --git a/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp b/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp index 93b1da52d46b..12a5fd532c4c 100644 --- a/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp +++ b/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp @@ -9,6 +9,7 @@ #include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/Dialect/Mesh/IR/MeshOps.h" #include "mlir/Dialect/Mesh/Transforms/Simplifications.h" +#include "mlir/IR/SymbolTable.h" #include "mlir/Pass/Pass.h" #include "mlir/Transforms/GreedyPatternRewriteDriver.h" @@ -30,8 +31,11 @@ struct TestMeshSimplificationsPass void TestMeshSimplificationsPass::runOnOperation() { RewritePatternSet patterns(&getContext()); - mesh::populateSimplificationPatterns(patterns); - (void)applyPatternsAndFoldGreedily(getOperation(), std::move(patterns)); + SymbolTableCollection symbolTableCollection; + mesh::populateSimplificationPatterns(patterns, symbolTableCollection); + LogicalResult status = + applyPatternsAndFoldGreedily(getOperation(), std::move(patterns)); + assert(succeeded(status) && "Rewrite patters application did not converge."); } namespace mlir { diff --git a/mlir/tools/mlir-opt/CMakeLists.txt b/mlir/tools/mlir-opt/CMakeLists.txt index ce2f5bf4094a..9ad5b32c24f9 100644 --- a/mlir/tools/mlir-opt/CMakeLists.txt +++ b/mlir/tools/mlir-opt/CMakeLists.txt @@ -26,7 +26,7 @@ if(MLIR_INCLUDE_TESTS) MLIRLoopLikeInterfaceTestPasses MLIRMathTestPasses MLIRMemRefTestPasses - MLIRMeshTestSimplifications + MLIRMeshTest MLIRNVGPUTestPasses MLIRSCFTestPasses MLIRShapeTestPasses -- GitLab From 4e8986fc58dd88cbef9089a9b2841e0a87cbb481 Mon Sep 17 00:00:00 2001 From: Zequan Wu Date: Tue, 9 Jan 2024 16:58:28 -0500 Subject: [PATCH 265/652] [Coverage] Mark coverage sections as metadata sections on COFF. (#76834) Mark `.lcovmap$M`, `.lcovfun$M`, `.lcovd` and `.lcovn` as metadata sections on COFF so they are not loaded into memory. --- llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 11 ++++++++++- llvm/test/CodeGen/X86/cov-sections.ll | 15 +++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/X86/cov-sections.ll diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp index 6e69dc66429d..a69b71451736 100644 --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -1669,9 +1669,18 @@ static int getSelectionForCOFF(const GlobalValue *GV) { MCSection *TargetLoweringObjectFileCOFF::getExplicitSectionGlobal( const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { + StringRef Name = GO->getSection(); + if (Name == getInstrProfSectionName(IPSK_covmap, Triple::COFF, + /*AddSegmentInfo=*/false) || + Name == getInstrProfSectionName(IPSK_covfun, Triple::COFF, + /*AddSegmentInfo=*/false) || + Name == getInstrProfSectionName(IPSK_covdata, Triple::COFF, + /*AddSegmentInfo=*/false) || + Name == getInstrProfSectionName(IPSK_covname, Triple::COFF, + /*AddSegmentInfo=*/false)) + Kind = SectionKind::getMetadata(); int Selection = 0; unsigned Characteristics = getCOFFSectionFlags(Kind, TM); - StringRef Name = GO->getSection(); StringRef COMDATSymName = ""; if (GO->hasComdat()) { Selection = getSelectionForCOFF(GO); diff --git a/llvm/test/CodeGen/X86/cov-sections.ll b/llvm/test/CodeGen/X86/cov-sections.ll new file mode 100644 index 000000000000..6c4f3f079f38 --- /dev/null +++ b/llvm/test/CodeGen/X86/cov-sections.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc -filetype=obj -o - | llvm-readobj -S - | FileCheck %s + +@covmap = private global i32 0, section ".lcovmap$M" +@covfun = private global i32 0, section ".lcovfun$M" +@covname = private global i32 0, section ".lcovd" +@covdata= private global i32 0, section ".lcovn" + +; CHECK: Name: .lcovmap$M +; CHECK: IMAGE_SCN_MEM_DISCARDABLE (0x2000000) +; CHECK: Name: .lcovfun$M +; CHECK: IMAGE_SCN_MEM_DISCARDABLE (0x2000000) +; CHECK: Name: .lcovd +; CHECK: IMAGE_SCN_MEM_DISCARDABLE (0x2000000) +; CHECK: Name: .lcovn +; CHECK: IMAGE_SCN_MEM_DISCARDABLE (0x2000000) -- GitLab From 71e5652f47b0d02a54aa9582319648bc4c23842c Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Tue, 9 Jan 2024 14:03:26 -0800 Subject: [PATCH 266/652] [sanitizer] Select non-internal frames in ReportErrorSummary (#77406) Summary contains one line and should point to user code instead of internal compiler-rt location. TSAN already does that. --- .../sanitizer_symbolizer_report.cpp | 36 +++++++++++++------ .../Linux/aligned_alloc-alignment.cpp | 2 +- .../TestCases/Linux/pvalloc-overflow.cpp | 2 +- .../Posix/posix_memalign-alignment.cpp | 2 +- .../TestCases/allocator_returns_null.cpp | 16 ++++----- .../test/hwasan/TestCases/halt-on-error.cpp | 6 ++-- .../test/hwasan/TestCases/report-unmapped.cpp | 2 +- .../test/hwasan/TestCases/use-after-free.c | 2 +- .../TestCases/allocator_returns_null.cpp | 16 ++++----- .../TestCases/max_allocation_size.cpp | 16 ++++----- 10 files changed, 58 insertions(+), 42 deletions(-) diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp index 0cf250f72129..253dc10607a6 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp @@ -95,17 +95,33 @@ void ReportErrorSummary(const char *error_type, const StackTrace *stack, #if !SANITIZER_GO if (!common_flags()->print_summary) return; - if (stack->size == 0) { - ReportErrorSummary(error_type); - return; + + // Find first non-internal stack frame. + for (uptr i = 0; i < stack->size; ++i) { + uptr pc = StackTrace::GetPreviousInstructionPc(stack->trace[i]); + SymbolizedStackHolder symbolized_stack( + Symbolizer::GetOrInit()->SymbolizePC(pc)); + if (const SymbolizedStack *frame = symbolized_stack.get()) { + if (const SymbolizedStack *summary_frame = SkipInternalFrames(frame)) { + ReportErrorSummary(error_type, summary_frame->info, alt_tool_name); + return; + } + } + } + + // Fallback to the top one. + if (stack->size) { + uptr pc = StackTrace::GetPreviousInstructionPc(stack->trace[0]); + SymbolizedStackHolder symbolized_stack( + Symbolizer::GetOrInit()->SymbolizePC(pc)); + if (const SymbolizedStack *frame = symbolized_stack.get()) { + ReportErrorSummary(error_type, frame->info, alt_tool_name); + return; + } } - // Currently, we include the first stack frame into the report summary. - // Maybe sometimes we need to choose another frame (e.g. skip memcpy/etc). - uptr pc = StackTrace::GetPreviousInstructionPc(stack->trace[0]); - SymbolizedStackHolder symbolized_stack( - Symbolizer::GetOrInit()->SymbolizePC(pc)); - const SymbolizedStack *frame = symbolized_stack.get(); - ReportErrorSummary(error_type, frame->info, alt_tool_name); + + // Fallback to a summary without location. + ReportErrorSummary(error_type); #endif } diff --git a/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp b/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp index ad5b7616e8a7..35e29e8cc834 100644 --- a/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp +++ b/compiler-rt/test/hwasan/TestCases/Linux/aligned_alloc-alignment.cpp @@ -14,7 +14,7 @@ int main() { // CHECK: ERROR: HWAddressSanitizer: invalid alignment requested in aligned_alloc: 17 // CHECK: {{#0 0x.* in .*}}{{aligned_alloc|memalign}} // CHECK: {{#1 0x.* in main .*aligned_alloc-alignment.cpp:}}[[@LINE-3]] - // CHECK: SUMMARY: HWAddressSanitizer: invalid-aligned-alloc-alignment {{.*}} in aligned_alloc + // CHECK: SUMMARY: HWAddressSanitizer: invalid-aligned-alloc-alignment {{.*}} in main printf("pointer after failed aligned_alloc: %zd\n", (size_t)p); // CHECK-NULL: pointer after failed aligned_alloc: 0 diff --git a/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp b/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp index bd9f34a0dac9..6b4410449a83 100644 --- a/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp +++ b/compiler-rt/test/hwasan/TestCases/Linux/pvalloc-overflow.cpp @@ -39,6 +39,6 @@ int main(int argc, char *argv[]) { // CHECK: {{ERROR: HWAddressSanitizer: pvalloc parameters overflow: size .* rounded up to system page size .* cannot be represented in type size_t}} // CHECK: {{#0 0x.* in .*pvalloc}} // CHECK: {{#1 0x.* in main .*pvalloc-overflow.cpp:}} -// CHECK: SUMMARY: HWAddressSanitizer: pvalloc-overflow {{.*}} in pvalloc +// CHECK: SUMMARY: HWAddressSanitizer: pvalloc-overflow {{.*}} in main // CHECK-NULL: errno: 12 diff --git a/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp b/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp index 029e086f99ad..5841ca42ceb0 100644 --- a/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp +++ b/compiler-rt/test/hwasan/TestCases/Posix/posix_memalign-alignment.cpp @@ -11,7 +11,7 @@ int main() { // CHECK: ERROR: HWAddressSanitizer: invalid alignment requested in posix_memalign: 17 // CHECK: {{#0 0x.* in .*posix_memalign}} // CHECK: {{#1 0x.* in main .*posix_memalign-alignment.cpp:}}[[@LINE-3]] - // CHECK: SUMMARY: HWAddressSanitizer: invalid-posix-memalign-alignment {{.*}} in posix_memalign + // CHECK: SUMMARY: HWAddressSanitizer: invalid-posix-memalign-alignment {{.*}} in main printf("pointer after failed posix_memalign: %zd\n", (size_t)p); // CHECK-NULL: pointer after failed posix_memalign: 42 diff --git a/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp b/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp index 18ee9406d146..2db28984e949 100644 --- a/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp +++ b/compiler-rt/test/hwasan/TestCases/allocator_returns_null.cpp @@ -87,21 +87,21 @@ int main(int argc, char **argv) { } // CHECK-mCRASH: malloc: -// CHECK-mCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in malloc +// CHECK-mCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in main // CHECK-cCRASH: calloc: -// CHECK-cCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in calloc +// CHECK-cCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in main // CHECK-coCRASH: calloc-overflow: -// CHECK-coCRASH: SUMMARY: HWAddressSanitizer: calloc-overflow {{.*}} in calloc +// CHECK-coCRASH: SUMMARY: HWAddressSanitizer: calloc-overflow {{.*}} in main // CHECK-rCRASH: realloc: -// CHECK-rCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in realloc +// CHECK-rCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in main // CHECK-mrCRASH: realloc-after-malloc: -// CHECK-mrCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in realloc +// CHECK-mrCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in main // CHECK-nCRASH: new: -// CHECK-nCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in operator new +// CHECK-nCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in main // CHECK-nCRASH-OOM: new: -// CHECK-nCRASH-OOM: SUMMARY: HWAddressSanitizer: out-of-memory {{.*}} in operator new +// CHECK-nCRASH-OOM: SUMMARY: HWAddressSanitizer: out-of-memory {{.*}} in main // CHECK-nnCRASH: new-nothrow: -// CHECK-nnCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in operator new +// CHECK-nnCRASH: SUMMARY: HWAddressSanitizer: allocation-size-too-big {{.*}} in main // CHECK-mNULL: malloc: // CHECK-mNULL: errno: 12 diff --git a/compiler-rt/test/hwasan/TestCases/halt-on-error.cpp b/compiler-rt/test/hwasan/TestCases/halt-on-error.cpp index 1a32e4bf4cc4..b27ee34ff7cc 100644 --- a/compiler-rt/test/hwasan/TestCases/halt-on-error.cpp +++ b/compiler-rt/test/hwasan/TestCases/halt-on-error.cpp @@ -26,15 +26,15 @@ int main() { // COMMON: READ of size 4 at // When instrumenting with callbacks, main is actually #1, and #0 is __hwasan_load4. // COMMON: #{{.*}} in main {{.*}}halt-on-error.cpp:[[@LINE-3]] - // COMMON: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in + // COMMON: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in main // RECOVER: READ of size 1 at // RECOVER: #{{.*}} in main {{.*}}halt-on-error.cpp:[[@LINE-7]] - // RECOVER: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in + // RECOVER: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in main // RECOVER: READ of size 1 at // RECOVER: #{{.*}} in main {{.*}}halt-on-error.cpp:[[@LINE-11]] - // RECOVER: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in + // RECOVER: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in main // COMMON-NOT: tag-mismatch } diff --git a/compiler-rt/test/hwasan/TestCases/report-unmapped.cpp b/compiler-rt/test/hwasan/TestCases/report-unmapped.cpp index a58e50a78d87..c00a615f7d52 100644 --- a/compiler-rt/test/hwasan/TestCases/report-unmapped.cpp +++ b/compiler-rt/test/hwasan/TestCases/report-unmapped.cpp @@ -36,4 +36,4 @@ int main(int argc, char **argv) { // CHECK: Tags for short granules around // Check that report is complete. -// CHECK: SUMMARY: HWAddressSanitizer +// CHECK: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in main diff --git a/compiler-rt/test/hwasan/TestCases/use-after-free.c b/compiler-rt/test/hwasan/TestCases/use-after-free.c index b3eed8860072..070622f560a2 100644 --- a/compiler-rt/test/hwasan/TestCases/use-after-free.c +++ b/compiler-rt/test/hwasan/TestCases/use-after-free.c @@ -38,6 +38,6 @@ int main() { // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-24]] // CHECK: Memory tags around the buggy address (one tag corresponds to 16 bytes): // CHECK: =>{{.*}}[[MEM_TAG]] - // CHECK: SUMMARY: HWAddressSanitizer: tag-mismatch + // CHECK: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in main return r; } diff --git a/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp b/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp index 9f8e12ff6aa0..ca6f637b9a3f 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp @@ -95,28 +95,28 @@ int main(int argc, char **argv) { // CHECK-mCRASH: malloc: // CHECK-mCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-mCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc +// CHECK-mCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*allocator_returns_null.cpp.*}} in main // CHECK-cCRASH: calloc: // CHECK-cCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-cCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc +// CHECK-cCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*allocator_returns_null.cpp.*}} in main // CHECK-coCRASH: calloc-overflow: // CHECK-coCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-coCRASH: {{SUMMARY: .*Sanitizer: calloc-overflow.*}} in {{.*}}lloc +// CHECK-coCRASH: {{SUMMARY: .*Sanitizer: calloc-overflow.*allocator_returns_null.cpp.*}} in main // CHECK-rCRASH: realloc: // CHECK-rCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-rCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc +// CHECK-rCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*allocator_returns_null.cpp.*}} in main // CHECK-mrCRASH: realloc-after-malloc: // CHECK-mrCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-mrCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{.*}}lloc +// CHECK-mrCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*allocator_returns_null.cpp.*}} in main // CHECK-nCRASH: new: // CHECK-nCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-nCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{operator new|.*lloc}} +// CHECK-nCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*allocator_returns_null.cpp.*}} in main // CHECK-nCRASH-OOM: new: // CHECK-nCRASH-O#{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-nCRASH-OOM: {{SUMMARY: .*Sanitizer: out-of-memory.*}} in {{operator new|.*lloc}} +// CHECK-nCRASH-OOM: {{SUMMARY: .*Sanitizer: out-of-memory.*allocator_returns_null.cpp.*}} in main // CHECK-nnCRASH: new-nothrow: // CHECK-nnCRASH: #{{[0-9]+.*}}allocator_returns_null.cpp -// CHECK-nnCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} in {{operator new|.*lloc}} +// CHECK-nnCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*allocator_returns_null.cpp.*}} in main // CHECK-NULL: {{malloc|calloc|calloc-overflow|realloc|realloc-after-malloc|new-nothrow}} // CHECK-NULL: errno: 12, x: 0 diff --git a/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp b/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp index c74f241c32b7..2fde16fbed3d 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/max_allocation_size.cpp @@ -124,28 +124,28 @@ int main(int Argc, char **Argv) { // CHECK-mCRASH: malloc: // CHECK-mCRASH: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-mCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-mCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.* in allocate}} // CHECK-cCRASH: calloc: // CHECK-cCRASH: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-cCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-cCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.* in allocate}} // CHECK-rCRASH: realloc: // CHECK-rCRASH: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-rCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-rCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.* in allocate}} // CHECK-mrCRASH: realloc-after-malloc: // CHECK-mrCRASH: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-mrCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-mrCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.* in allocate}} // CHECK-nCRASH: new: // CHECK-nCRASH: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-nCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-nCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.* in allocate}} // CHECK-nCRASH-OOM: new: // CHECK-nCRASH-OOM: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-nCRASH-OOM: {{SUMMARY: .*Sanitizer: out-of-memory}} +// CHECK-nCRASH-OOM: {{SUMMARY: .*Sanitizer: out-of-memory.* in allocate}} // CHECK-nnCRASH: new-nothrow: // CHECK-nnCRASH: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-nnCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-nnCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.* in allocate}} // CHECK-sCRASH: strndup: // CHECK-sCRASH: #{{[0-9]+.*}}max_allocation_size.cpp -// CHECK-sCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big}} +// CHECK-sCRASH: {{SUMMARY: .*Sanitizer: allocation-size-too-big.*}} // CHECK-NULL: {{malloc|calloc|calloc-overflow|realloc|realloc-after-malloc|new-nothrow|strndup}} // CHECK-NULL: errno: 12, P: 0 -- GitLab From e07a2f49e3d3c13b6e9b89e0f6118652f2b2d3ac Mon Sep 17 00:00:00 2001 From: Will Hawkins Date: Tue, 9 Jan 2024 17:07:32 -0500 Subject: [PATCH 267/652] [libc++][NFC] Create and use test-defined simple_view concept (#77334) Instead of using a concept defined in the internal implementation, use a definition of the simple_view ranges concept separately defined and included in test code. --- .../simple_view.compile.pass.cpp | 7 +++ .../range.adaptors/range.drop/begin.pass.cpp | 5 +- .../ranges/range.adaptors/range.drop/types.h | 14 ++--- .../range.adaptors/range.elements/types.h | 8 +-- .../range.join.sentinel/ctor.other.pass.cpp | 3 +- .../ranges/range.adaptors/range.join/types.h | 17 +++--- .../range.lazy.split/begin.pass.cpp | 17 +++--- .../range.lazy.split/end.pass.cpp | 9 +-- .../range.adaptors/range.take.while/types.h | 4 +- .../range.adaptors/range.take/begin.pass.cpp | 2 +- .../range.zip/sentinel/ctor.other.pass.cpp | 2 +- .../range.zip/sentinel/eq.pass.cpp | 8 +-- .../range.zip/sentinel/minus.pass.cpp | 6 +- .../ranges/range.adaptors/range.zip/types.h | 56 +++++++++---------- libcxx/test/support/test_range.h | 7 +++ 15 files changed, 92 insertions(+), 73 deletions(-) diff --git a/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp b/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp index ce8cd112468c..a58f74c3b591 100644 --- a/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp +++ b/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp @@ -14,6 +14,7 @@ #include "test_macros.h" #include "test_iterators.h" +#include "test_range.h" struct SimpleView : std::ranges::view_base { int *begin() const; @@ -48,3 +49,9 @@ static_assert(!std::ranges::__simple_view); static_assert(!std::ranges::__simple_view); static_assert( std::ranges::__simple_view); static_assert(!std::ranges::__simple_view); + +static_assert(simple_view); +static_assert(!simple_view); +static_assert(!simple_view); +static_assert(simple_view); +static_assert(!simple_view); diff --git a/libcxx/test/std/ranges/range.adaptors/range.drop/begin.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.drop/begin.pass.cpp index 8c28769acf7f..28ac53c2445d 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.drop/begin.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.drop/begin.pass.cpp @@ -18,6 +18,7 @@ #include "test_macros.h" #include "test_iterators.h" +#include "test_range.h" #include "types.h" template @@ -122,7 +123,7 @@ constexpr bool test() { { static_assert(std::ranges::random_access_range); static_assert(std::ranges::sized_range); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); + static_assert(simple_view); int non_const_calls = 0; int const_calls = 0; std::ranges::drop_view dropView(SimpleView{{}, &non_const_calls, &const_calls}, 4); @@ -137,7 +138,7 @@ constexpr bool test() { { static_assert(std::ranges::random_access_range); static_assert(std::ranges::sized_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); + static_assert(!simple_view); int non_const_calls = 0; int const_calls = 0; std::ranges::drop_view dropView(NonSimpleView{{}, &non_const_calls, &const_calls}, 4); diff --git a/libcxx/test/std/ranges/range.adaptors/range.drop/types.h b/libcxx/test/std/ranges/range.adaptors/range.drop/types.h index 1fc3f05bf5ea..ae861bce40f1 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.drop/types.h +++ b/libcxx/test/std/ranges/range.adaptors/range.drop/types.h @@ -15,21 +15,21 @@ int globalBuff[8]; template -struct sentinel { +struct drop_sentinel { T* ptr_; int* num_of_sentinel_cmp_calls; public: - friend constexpr bool operator==(sentinel const s, T* const ptr) noexcept { + friend constexpr bool operator==(drop_sentinel const s, T* const ptr) noexcept { ++(*s.num_of_sentinel_cmp_calls); return {s.ptr_ == ptr}; } - friend constexpr bool operator==(T* const ptr, sentinel const s) noexcept { + friend constexpr bool operator==(T* const ptr, drop_sentinel const s) noexcept { ++(*s.num_of_sentinel_cmp_calls); return {s.ptr_ == ptr}; } - friend constexpr bool operator!=(sentinel const s, T* const ptr) noexcept { return !(s == ptr); } - friend constexpr bool operator!=(T* const ptr, sentinel const s) noexcept { return !(s == ptr); } + friend constexpr bool operator!=(drop_sentinel const s, T* const ptr) noexcept { return !(s == ptr); } + friend constexpr bool operator!=(T* const ptr, drop_sentinel const s) noexcept { return !(s == ptr); } }; template @@ -39,9 +39,9 @@ struct MaybeSimpleNonCommonView : std::ranges::view_base { constexpr std::size_t size() const { return 8; } constexpr int* begin() { return globalBuff + start_; } constexpr std::conditional_t begin() const { return globalBuff + start_; } - constexpr sentinel end() { return sentinel{globalBuff + size(), num_of_sentinel_cmp_calls}; } + constexpr drop_sentinel end() { return drop_sentinel{globalBuff + size(), num_of_sentinel_cmp_calls}; } constexpr auto end() const { - return std::conditional_t, sentinel>{ + return std::conditional_t, drop_sentinel>{ globalBuff + size(), num_of_sentinel_cmp_calls}; } }; diff --git a/libcxx/test/std/ranges/range.adaptors/range.elements/types.h b/libcxx/test/std/ranges/range.adaptors/range.elements/types.h index f1ee165c3cc6..4c4084695ff3 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.elements/types.h +++ b/libcxx/test/std/ranges/range.adaptors/range.elements/types.h @@ -58,8 +58,8 @@ using NonSimpleCommonRandomAccessSized = NonSimpleCommon; static_assert(std::ranges::common_range>); static_assert(std::ranges::random_access_range); static_assert(std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(simple_view); +static_assert(!simple_view); template struct NonCommon : TupleBufferView { @@ -86,8 +86,8 @@ using NonSimpleNonCommon = NonCommon; static_assert(!std::ranges::common_range); static_assert(std::ranges::random_access_range); static_assert(!std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(simple_view); +static_assert(!simple_view); template struct IterBase { diff --git a/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp index 5ef3e7416ef1..fb1e8eb1ebef 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp @@ -15,6 +15,7 @@ #include #include "../types.h" +#include "test_range.h" template struct convertible_sentinel_wrapper { @@ -45,7 +46,7 @@ struct ConstConvertibleView : BufferView*> { static_assert(!std::ranges::common_range); static_assert(std::convertible_to, std::ranges::sentinel_t>); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); constexpr bool test() { int buffer[4][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}, {13, 14, 15, 16}}; diff --git a/libcxx/test/std/ranges/range.adaptors/range.join/types.h b/libcxx/test/std/ranges/range.adaptors/range.join/types.h index c1378dc1144b..175eb316030e 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.join/types.h +++ b/libcxx/test/std/ranges/range.adaptors/range.join/types.h @@ -16,6 +16,7 @@ #include "test_macros.h" #include "test_iterators.h" +#include "test_range.h" inline int globalBuffer[4][4] = { {1111, 2222, 3333, 4444}, @@ -239,7 +240,7 @@ using SimpleInputCommonOuter = BufferView>; static_assert(!std::ranges::forward_range>); static_assert(!std::ranges::bidirectional_range>); static_assert(std::ranges::common_range>); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view>); +static_assert(simple_view>); template > using NonSimpleInputCommonOuter = BufferView, common_input_iterator, @@ -247,14 +248,14 @@ using NonSimpleInputCommonOuter = BufferView static_assert(!std::ranges::forward_range>); static_assert(!std::ranges::bidirectional_range>); static_assert(std::ranges::common_range>); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view>); +static_assert(!simple_view>); template > using SimpleForwardCommonOuter = BufferView>; static_assert(std::ranges::forward_range>); static_assert(!std::ranges::bidirectional_range>); static_assert(std::ranges::common_range>); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view>); +static_assert(simple_view>); template > using NonSimpleForwardCommonOuter = BufferView, forward_iterator, @@ -262,14 +263,14 @@ using NonSimpleForwardCommonOuter = BufferView, f static_assert(std::ranges::forward_range>); static_assert(!std::ranges::bidirectional_range>); static_assert(std::ranges::common_range>); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view>); +static_assert(!simple_view>); template > using SimpleForwardNonCommonOuter = BufferView, sentinel_wrapper>>; static_assert(std::ranges::forward_range>); static_assert(!std::ranges::bidirectional_range>); static_assert(!std::ranges::common_range>); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view>); +static_assert(simple_view>); template > using NonSimpleForwardNonCommonOuter = @@ -278,13 +279,13 @@ using NonSimpleForwardNonCommonOuter = static_assert(std::ranges::forward_range>); static_assert(!std::ranges::bidirectional_range>); static_assert(!std::ranges::common_range>); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view>); +static_assert(!simple_view>); template > using BidiCommonOuter = BufferView>; static_assert(std::ranges::bidirectional_range>); static_assert(std::ranges::common_range>); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view>); +static_assert(simple_view>); // an iterator where its operator* makes a copy of underlying operator* template @@ -349,7 +350,7 @@ struct InnerRValue : Outer { static_assert(std::ranges::forward_range>>); static_assert(!std::ranges::bidirectional_range>>); static_assert(std::ranges::common_range>>); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view>>); +static_assert(simple_view>>); static_assert(!std::is_lvalue_reference_v>>>); struct move_swap_aware_iter { diff --git a/libcxx/test/std/ranges/range.adaptors/range.lazy.split/begin.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.lazy.split/begin.pass.cpp index c89da85155d0..113272703d59 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.lazy.split/begin.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.lazy.split/begin.pass.cpp @@ -16,6 +16,7 @@ #include #include #include "test_iterators.h" +#include "test_range.h" #include "types.h" template @@ -32,8 +33,8 @@ constexpr bool test() { static_assert(std::ranges::forward_range); static_assert(std::ranges::forward_range); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view

); + static_assert(simple_view); + static_assert(simple_view

); { std::ranges::lazy_split_view v; @@ -58,8 +59,8 @@ constexpr bool test() { static_assert(std::ranges::forward_range); static_assert(std::ranges::forward_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view

); + static_assert(!simple_view); + static_assert(!simple_view

); { std::ranges::lazy_split_view v; @@ -83,8 +84,8 @@ constexpr bool test() { using P = V; static_assert(std::ranges::forward_range); static_assert(!std::ranges::forward_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view

); + static_assert(!simple_view); + static_assert(!simple_view

); std::ranges::lazy_split_view v; auto it = v.begin(); @@ -102,8 +103,8 @@ constexpr bool test() { static_assert(std::ranges::forward_range); static_assert(std::ranges::forward_range); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view

); + static_assert(simple_view); + static_assert(!simple_view

); { std::ranges::lazy_split_view v; diff --git a/libcxx/test/std/ranges/range.adaptors/range.lazy.split/end.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.lazy.split/end.pass.cpp index 0f5ab6265042..3e3facc1cbe3 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.lazy.split/end.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.lazy.split/end.pass.cpp @@ -16,6 +16,7 @@ #include #include #include "test_iterators.h" +#include "test_range.h" #include "types.h" struct ForwardViewCommonIfConst : std::ranges::view_base { @@ -59,8 +60,8 @@ constexpr bool test() { static_assert(std::ranges::forward_range); static_assert(std::ranges::common_range); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view

); + static_assert(simple_view); + static_assert(simple_view

); { std::ranges::lazy_split_view v; @@ -85,8 +86,8 @@ constexpr bool test() { static_assert(std::ranges::forward_range); static_assert(std::ranges::common_range); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view

); + static_assert(simple_view); + static_assert(!simple_view

); static_assert(std::ranges::forward_range); static_assert(std::ranges::common_range); diff --git a/libcxx/test/std/ranges/range.adaptors/range.take.while/types.h b/libcxx/test/std/ranges/range.adaptors/range.take.while/types.h index b946190d3fd8..8a8119970c58 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.take.while/types.h +++ b/libcxx/test/std/ranges/range.adaptors/range.take.while/types.h @@ -36,7 +36,7 @@ struct SimpleView : IntBufferViewBase { constexpr int* begin() const { return buffer_; } constexpr int* end() const { return buffer_ + size_; } }; -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); struct ConstNotRange : IntBufferViewBase { using IntBufferViewBase::IntBufferViewBase; @@ -54,6 +54,6 @@ struct NonSimple : IntBufferViewBase { constexpr int* end() { return buffer_ + size_; } }; static_assert(std::ranges::view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); #endif // TEST_STD_RANGES_RANGE_ADAPTORS_RANGE_TAKE_WHILE_TYPES_H diff --git a/libcxx/test/std/ranges/range.adaptors/range.take/begin.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.take/begin.pass.cpp index f2ac62e764d5..1873481d7322 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.take/begin.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.take/begin.pass.cpp @@ -69,7 +69,7 @@ constexpr bool test() { ASSERT_SAME_TYPE(decltype(tv.begin()), std::counted_iterator); } - // __simple_view && sized_range && !size_range + // simple-view && sized_range && !size_range { std::ranges::take_view tv{}; ASSERT_SAME_TYPE(decltype(tv.begin()), std::counted_iterator); diff --git a/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/ctor.other.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/ctor.other.pass.cpp index 9635d9a11988..11ad73c313c5 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/ctor.other.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/ctor.other.pass.cpp @@ -46,7 +46,7 @@ static_assert(std::ranges::random_access_range); static_assert(std::convertible_to, std::ranges::sentinel_t>); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); constexpr bool test() { int buffer1[4] = {1, 2, 3, 4}; diff --git a/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/eq.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/eq.pass.cpp index b42ec78cbb7f..5db737211081 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/eq.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/eq.pass.cpp @@ -67,7 +67,7 @@ constexpr bool test() { // simple-view: const and non-const have the same iterator/sentinel type std::ranges::zip_view v{SimpleNonCommon(buffer1), SimpleNonCommon(buffer2), SimpleNonCommon(buffer3)}; static_assert(!std::ranges::common_range); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); + static_assert(simple_view); assert(v.begin() != v.end()); assert(v.begin() + 1 != v.end()); @@ -80,7 +80,7 @@ constexpr bool test() { // !simple-view: const and non-const have different iterator/sentinel types std::ranges::zip_view v{NonSimpleNonCommon(buffer1), SimpleNonCommon(buffer2), SimpleNonCommon(buffer3)}; static_assert(!std::ranges::common_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); + static_assert(!simple_view); assert(v.begin() != v.end()); assert(v.begin() + 4 == v.end()); @@ -105,7 +105,7 @@ constexpr bool test() { // underlying const/non-const sentinel can be compared with both const/non-const iterator std::ranges::zip_view v{ComparableView(buffer1), ComparableView(buffer2)}; static_assert(!std::ranges::common_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); + static_assert(!simple_view); assert(v.begin() != v.end()); assert(v.begin() + 4 == v.end()); @@ -130,7 +130,7 @@ constexpr bool test() { // underlying const/non-const sentinel cannot be compared with non-const/const iterator std::ranges::zip_view v{ComparableView(buffer1), ConstIncompatibleView{}}; static_assert(!std::ranges::common_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); + static_assert(!simple_view); using Iter = std::ranges::iterator_t; using ConstIter = std::ranges::iterator_t; diff --git a/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/minus.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/minus.pass.cpp index e46ab4c38d2b..be0a7ba5b907 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/minus.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.zip/sentinel/minus.pass.cpp @@ -120,7 +120,7 @@ constexpr bool test() { // simple-view std::ranges::zip_view v{ForwardSizedNonCommon(buffer1)}; static_assert(!std::ranges::common_range); - LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); + static_assert(simple_view); auto it = v.begin(); auto st = v.end(); @@ -159,7 +159,7 @@ constexpr bool test() { // underlying sentinels cannot subtract underlying const iterators std::ranges::zip_view v(NonSimpleForwardSizedNonCommon{buffer1}); static_assert(!std::ranges::common_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); + static_assert(!simple_view); using Iter = std::ranges::iterator_t; using ConstIter = std::ranges::iterator_t; @@ -191,7 +191,7 @@ constexpr bool test() { // const compatible allow non-const to const conversion std::ranges::zip_view v(ConstCompatibleForwardSized{buffer1}); static_assert(!std::ranges::common_range); - LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); + static_assert(!simple_view); using Iter = std::ranges::iterator_t; using ConstIter = std::ranges::iterator_t; diff --git a/libcxx/test/std/ranges/range.adaptors/range.zip/types.h b/libcxx/test/std/ranges/range.adaptors/range.zip/types.h index e5f399f93e35..e084dcfc41b0 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.zip/types.h +++ b/libcxx/test/std/ranges/range.adaptors/range.zip/types.h @@ -57,8 +57,8 @@ using NonSimpleCommonRandomAccessSized = NonSimpleCommon; static_assert(std::ranges::common_range>); static_assert(std::ranges::random_access_range); static_assert(std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(simple_view); +static_assert(!simple_view); template struct CommonNonRandom : IntBufferView { @@ -83,8 +83,8 @@ using NonSimpleCommonNonRandom = CommonNonRandom; static_assert(std::ranges::common_range); static_assert(!std::ranges::random_access_range); static_assert(!std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(simple_view); +static_assert(!simple_view); template struct NonCommon : IntBufferView { @@ -107,8 +107,8 @@ using NonSimpleNonCommon = NonCommon; static_assert(!std::ranges::common_range); static_assert(std::ranges::random_access_range); static_assert(!std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(simple_view); +static_assert(!simple_view); template struct NonCommonSized : IntBufferView { @@ -134,8 +134,8 @@ using NonSimpleNonCommonRandomAccessSized = NonSimpleNonCommonSized; static_assert(!std::ranges::common_range); static_assert(std::ranges::random_access_range); static_assert(std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(simple_view); +static_assert(!simple_view); template struct NonCommonNonRandom : IntBufferView { @@ -164,8 +164,8 @@ using NonSimpleNonCommonNonRandom = NonCommonNonRandom; static_assert(!std::ranges::common_range); static_assert(!std::ranges::random_access_range); static_assert(!std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(simple_view); +static_assert(!simple_view); template struct BasicView : IntBufferView { @@ -230,7 +230,7 @@ static_assert(std::ranges::forward_range); static_assert(std::ranges::sized_range); static_assert(std::ranges::common_range); static_assert(!std::ranges::random_access_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleForwardSizedView = BasicView, forward_sized_iterator, forward_sized_iterator, forward_sized_iterator>; @@ -238,14 +238,14 @@ static_assert(std::ranges::forward_range); static_assert(std::ranges::sized_range); static_assert(std::ranges::common_range); static_assert(!std::ranges::random_access_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); using ForwardSizedNonCommon = BasicView, sized_sentinel>>; static_assert(std::ranges::forward_range); static_assert(std::ranges::sized_range); static_assert(!std::ranges::common_range); static_assert(!std::ranges::random_access_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleForwardSizedNonCommon = BasicView, sized_sentinel>, @@ -254,7 +254,7 @@ static_assert(std::ranges::forward_range); static_assert(std::ranges::sized_range); static_assert(!std::ranges::common_range); static_assert(!std::ranges::random_access_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); struct SizedRandomAccessView : IntBufferView { using IntBufferView::IntBufferView; @@ -275,7 +275,7 @@ static_assert(!std::ranges::contiguous_range); static_assert(std::ranges::random_access_range); static_assert(!std::ranges::common_range); static_assert(!std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleNonSizedRandomAccessView = BasicView, sentinel_wrapper>, @@ -284,7 +284,7 @@ static_assert(!std::ranges::contiguous_range) static_assert(std::ranges::random_access_range); static_assert(!std::ranges::common_range); static_assert(!std::ranges::sized_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); using ContiguousCommonView = BasicView; static_assert(std::ranges::contiguous_range); @@ -306,20 +306,20 @@ using InputCommonView = BasicView>; static_assert(std::ranges::input_range); static_assert(!std::ranges::forward_range); static_assert(std::ranges::common_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleInputCommonView = BasicView, common_input_iterator, common_input_iterator, common_input_iterator>; static_assert(std::ranges::input_range); static_assert(!std::ranges::forward_range); static_assert(std::ranges::common_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); using InputNonCommonView = BasicView, sentinel_wrapper>>; static_assert(std::ranges::input_range); static_assert(!std::ranges::forward_range); static_assert(!std::ranges::common_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleInputNonCommonView = BasicView, sentinel_wrapper>, @@ -327,14 +327,14 @@ using NonSimpleInputNonCommonView = static_assert(std::ranges::input_range); static_assert(!std::ranges::forward_range); static_assert(!std::ranges::common_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); using BidiCommonView = BasicView>; static_assert(!std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(std::ranges::common_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleBidiCommonView = BasicView, bidirectional_iterator, bidirectional_iterator, bidirectional_iterator>; @@ -342,7 +342,7 @@ static_assert(!std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(std::ranges::common_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); struct SizedBidiCommon : BidiCommonView { using BidiCommonView::BidiCommonView; @@ -352,7 +352,7 @@ static_assert(std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(std::ranges::common_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); struct NonSimpleSizedBidiCommon : NonSimpleBidiCommonView { using NonSimpleBidiCommonView::NonSimpleBidiCommonView; @@ -362,14 +362,14 @@ static_assert(std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(std::ranges::common_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); using BidiNonCommonView = BasicView, sentinel_wrapper>>; static_assert(!std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(!std::ranges::common_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleBidiNonCommonView = BasicView, sentinel_wrapper>, @@ -378,14 +378,14 @@ static_assert(!std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(!std::ranges::common_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); using SizedBidiNonCommonView = BasicView, sized_sentinel>>; static_assert(std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(!std::ranges::common_range); -LIBCPP_STATIC_ASSERT(std::ranges::__simple_view); +static_assert(simple_view); using NonSimpleSizedBidiNonCommonView = BasicView, sized_sentinel>, @@ -394,7 +394,7 @@ static_assert(std::ranges::sized_range); static_assert(std::ranges::bidirectional_range); static_assert(!std::ranges::random_access_range); static_assert(!std::ranges::common_range); -LIBCPP_STATIC_ASSERT(!std::ranges::__simple_view); +static_assert(!simple_view); namespace adltest{ struct iter_move_swap_iterator { diff --git a/libcxx/test/support/test_range.h b/libcxx/test/support/test_range.h index 3f03b4d391b8..6061f710a263 100644 --- a/libcxx/test/support/test_range.h +++ b/libcxx/test/support/test_range.h @@ -9,6 +9,7 @@ #ifndef LIBCXX_TEST_SUPPORT_TEST_RANGE_H #define LIBCXX_TEST_SUPPORT_TEST_RANGE_H +#include #include #include @@ -82,4 +83,10 @@ using NonBorrowedView = std::ranges::single_view; static_assert(std::ranges::view); static_assert(!std::ranges::borrowed_range); +template +concept simple_view = + std::ranges::view && std::ranges::range && + std::same_as, std::ranges::iterator_t> && + std::same_as, std::ranges::sentinel_t>; + #endif // LIBCXX_TEST_SUPPORT_TEST_RANGE_H -- GitLab From b5d4332286154838557a8ab5c76b794e85d946b3 Mon Sep 17 00:00:00 2001 From: Walter Erquinigo Date: Tue, 9 Jan 2024 17:10:15 -0500 Subject: [PATCH 268/652] [lldb-dap] Create a typescript extension for lldb-dap (#75515) The main motivations behind this are two: - Allow different companies developing their own vscode extensions for LLDB to have a single contribution point, thus sharing resources and working as a virtual large team. - Allow for visual ways to configure the debugger, which currently has to be done through launch.json files. In terms of implementation, this is very straightforward and these are the most important details: - All the cpp code has been moved to a subfolder for cleanness. There's a specific commit in the list of commits of this PR that just does that, in case that helps reviewing this. - A new folder `src-ts` has been created for the typescript code - The ts extension can be used in two ways: as a regular vscode extension and as a library. There file `extension.ts` explains which entry point to use. - The README has been updated the mention how to install the extension, which is simpler than before. There are two additional sections for rebuilding and formatting. - The ts code I added merely sets up the debug adapter using two possible options: reading the lldb-dap path from vscode settings or from a config object passed by users of the extension is used as a library. I did this to show how we can support easily both worlds. --- lldb/tools/lldb-dap/.editorconfig | 10 + lldb/tools/lldb-dap/.gitignore | 5 + lldb/tools/lldb-dap/.prettierrc.json | 7 + lldb/tools/lldb-dap/.vscode/launch.json | 24 + lldb/tools/lldb-dap/.vscode/tasks.json | 33 + lldb/tools/lldb-dap/LICENSE.TXT | 234 +++ lldb/tools/lldb-dap/README.md | 116 +- lldb/tools/lldb-dap/package-lock.json | 1679 +++++++++++++++++ lldb/tools/lldb-dap/package.json | 808 ++++---- .../lldb-dap/src-ts/debug-adapter-factory.ts | 23 + .../lldb-dap/src-ts/disposable-context.ts | 27 + lldb/tools/lldb-dap/src-ts/extension.ts | 55 + lldb/tools/lldb-dap/src-ts/types.ts | 23 + lldb/tools/lldb-dap/tsconfig.json | 16 + 14 files changed, 2619 insertions(+), 441 deletions(-) create mode 100644 lldb/tools/lldb-dap/.editorconfig create mode 100644 lldb/tools/lldb-dap/.gitignore create mode 100644 lldb/tools/lldb-dap/.prettierrc.json create mode 100644 lldb/tools/lldb-dap/.vscode/launch.json create mode 100644 lldb/tools/lldb-dap/.vscode/tasks.json create mode 100644 lldb/tools/lldb-dap/LICENSE.TXT create mode 100644 lldb/tools/lldb-dap/package-lock.json create mode 100644 lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts create mode 100644 lldb/tools/lldb-dap/src-ts/disposable-context.ts create mode 100644 lldb/tools/lldb-dap/src-ts/extension.ts create mode 100644 lldb/tools/lldb-dap/src-ts/types.ts create mode 100644 lldb/tools/lldb-dap/tsconfig.json diff --git a/lldb/tools/lldb-dap/.editorconfig b/lldb/tools/lldb-dap/.editorconfig new file mode 100644 index 000000000000..c97930f849a1 --- /dev/null +++ b/lldb/tools/lldb-dap/.editorconfig @@ -0,0 +1,10 @@ +[{*.ts}] +# Non-configurable Prettier behaviors +charset = utf-8 +insert_final_newline = true +trim_trailing_whitespace = true + +end_of_line = lf +indent_style = space +indent_size = 2 +max_line_length = 100 diff --git a/lldb/tools/lldb-dap/.gitignore b/lldb/tools/lldb-dap/.gitignore new file mode 100644 index 000000000000..f4e1656d5a5d --- /dev/null +++ b/lldb/tools/lldb-dap/.gitignore @@ -0,0 +1,5 @@ +out +bin +node_modules +*.vsix +!.vscode diff --git a/lldb/tools/lldb-dap/.prettierrc.json b/lldb/tools/lldb-dap/.prettierrc.json new file mode 100644 index 000000000000..a28c70b90a4e --- /dev/null +++ b/lldb/tools/lldb-dap/.prettierrc.json @@ -0,0 +1,7 @@ +{ + "trailingComma": "all", + "tabWidth": 2, + "semi": true, + "singleQuote": false, + "plugins": ["prettier-plugin-curly"] +} diff --git a/lldb/tools/lldb-dap/.vscode/launch.json b/lldb/tools/lldb-dap/.vscode/launch.json new file mode 100644 index 000000000000..8241a5aca035 --- /dev/null +++ b/lldb/tools/lldb-dap/.vscode/launch.json @@ -0,0 +1,24 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "type": "extensionHost", + "request": "launch", + "name": "Run Extension", + "runtimeExecutable": "${execPath}", + "args": [ + "--extensionDevelopmentPath=${workspaceFolder}" + ], + "outFiles": [ + "${workspaceFolder}/out/**/*.js" + ], + "preLaunchTask": { + "type": "npm", + "script": "watch" + } + } + ] +} diff --git a/lldb/tools/lldb-dap/.vscode/tasks.json b/lldb/tools/lldb-dap/.vscode/tasks.json new file mode 100644 index 000000000000..f82fc4134e78 --- /dev/null +++ b/lldb/tools/lldb-dap/.vscode/tasks.json @@ -0,0 +1,33 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "type": "npm", + "script": "compile", + "group": "build", + "presentation": { + "panel": "dedicated", + "reveal": "never" + }, + "problemMatcher": [ + "$tsc" + ] + }, + { + "type": "npm", + "script": "watch", + "isBackground": true, + "group": { + "kind": "build", + "isDefault": true + }, + "presentation": { + "panel": "dedicated", + "reveal": "never" + }, + "problemMatcher": [ + "$tsc-watch" + ] + } + ] +} diff --git a/lldb/tools/lldb-dap/LICENSE.TXT b/lldb/tools/lldb-dap/LICENSE.TXT new file mode 100644 index 000000000000..53bb2e7fbc76 --- /dev/null +++ b/lldb/tools/lldb-dap/LICENSE.TXT @@ -0,0 +1,234 @@ +============================================================================== +The LLVM Project is under the Apache License v2.0 with LLVM Exceptions: +============================================================================== + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + +---- LLVM Exceptions to the Apache 2.0 License ---- + +As an exception, if, as a result of your compiling your source code, portions +of this Software are embedded into an Object form of such source code, you +may redistribute such embedded portions in such Object form without complying +with the conditions of Sections 4(a), 4(b) and 4(d) of the License. + +In addition, if you combine or link compiled forms of this Software with +software that is licensed under the GPLv2 ("Combined Software") and if a +court of competent jurisdiction determines that the patent provision (Section +3), the indemnity provision (Section 9) or other Section of the License +conflicts with the conditions of the GPLv2, you may retroactively and +prospectively choose to deem waived or otherwise exclude such Section(s) of +the License, but only in their entirety and only with respect to the Combined +Software. + +============================================================================== +Software from third parties included in the LLVM Project: +============================================================================== +The LLVM Project contains third party software which is under different license +terms. All such code will be identified clearly using at least one of two +mechanisms: +1) It will be in a separate directory tree with its own `LICENSE.txt` or + `LICENSE` file at the top containing the specific license and restrictions + which apply to that software, or +2) It will contain specific license and restriction terms at the top of every + file. diff --git a/lldb/tools/lldb-dap/README.md b/lldb/tools/lldb-dap/README.md index 00ceb0bedc40..274b1519208a 100644 --- a/lldb/tools/lldb-dap/README.md +++ b/lldb/tools/lldb-dap/README.md @@ -3,7 +3,12 @@ - [Table of Contents](#table-of-contents) - [Introduction](#introduction) -- [Installation for Visual Studio Code](#installation-for-visual-studio-code) +- [Local Installation for Visual Studio Code](#local-installation-for-visual-studio-code) + - [Pre-requisites](#pre-requisites) + - [Packaging and installation](#packaging-and-installation) + - [Updating the extension](#updating-the-extension) + - [Deploying for Visual Studio Code](#deploying-for-visual-studio-code) +- [Formatting the Typescript code](#formatting-the-typescript-code) - [Configurations](#configurations) - [Launch Configuration Settings](#launch-configuration-settings) - [Attaching Settings](#attaching-settings) @@ -12,6 +17,8 @@ - [Attach using PID](#attach-using-pid) - [Attach by Name](#attach-by-name) - [Loading a Core File](#loading-a-core-file) + - [Connect to a Debug Server on the Current Machine](#connect-to-a-debug-server-on-the-current-machine) + - [Connect to a Debug Server on Another Machine](#connect-to-a-debug-server-on-another-machine) - [Custom debugger commands](#custom-debugger-commands) - [startDebugging](#startdebugging) - [repl-mode](#repl-mode) @@ -25,59 +32,92 @@ installed as an extension for Visual Studio Code and other IDEs supporting DAP. The protocol is easy to run remotely and also can allow other tools and IDEs to get a full featured debugger with a well defined protocol. -# Installation for Visual Studio Code +# Local Installation for Visual Studio Code -Installing the plug-in involves creating a directory in any location outside of -`~/.vscode/extensions`. For example, `~/vscode-lldb` is a valid one. You'll also -need a subfolder `bin`, e.g. `~/vscode-lldb/bin`. Then copy the `package.json` -file that is in the same directory as this documentation into it, and symlink -the `lldb-dap` binary into the `bin` directory inside the plug-in directory. +Installing the plug-in is very straightforward and involves just a few steps. -Finally, on VS Code, execute the command -`Developer: Install Extension from Location` and pick the folder you just -created, which would be `~/vscode-lldb` following the example above. +## Pre-requisites -If you want to make a stand alone plug-in that you can send to others on UNIX -systems: +- Install a modern version of node (e.g. `v20.0.0`). +- On VS Code, execute the command `Install 'code' command in PATH`. You need to + do it only once. This enables the command `code` in the PATH. + +## Packaging and installation + +```bash +cd /path/to/lldb/tools/lldb-dap +npm run package # This also compiles the extension. +npm run vscode-install +``` + +On VS Code, set the setting `lldb-dap.executable-path` to the path of your local +build of `lldb-dap`. + +And then you are ready! + +## Updating the extension + +*Note: It's not necessary to update the extension if there has been changes +to `lldb-dap`. The extension needs to be updated only if the TypesScript code +has changed.* + +Updating the extension is pretty much the same process as installing it from +scratch. However, VS Code expects the version number of the upgraded extension +to be greater than the previous one, otherwise the installation step might have +no effect. ```bash -mkdir -p ~/llvm-org.lldb-dap-0.1.0/bin -cp package.json ~/llvm-org.lldb-dap-0.1.0 -cd ~/llvm-org.lldb-dap-0.1.0/bin -cp /path/to/a/built/lldb-dap . -cp /path/to/a/built/liblldb.so . +# Bump version in package.json +cd /path/to/lldb/tools/lldb-dap +npm run package +npm run vscode-install ``` -If you want to make a stand alone plug-in that you can send to others on macOS -systems: +Another way upgrade without bumping the extension version is to first uninstall +the extension, then reload VS Code, and then install it again. This is +an unfortunate limitation of the editor. ```bash -mkdir -p ~/llvm-org.lldb-dap-0.1.0/bin -cp package.json ~/llvm-org.lldb-dap-0.1.0 -cd ~/llvm-org.lldb-dap-0.1.0/bin -cp /path/to/a/built/lldb-dap . -rsync -av /path/to/a/built/LLDB.framework LLDB.framework +cd /path/to/lldb/tools/lldb-dap +npm run vscode-uninstall +# Then reload VS Code: reopen the IDE or execute the `Developer: Reload Window` +# command. +npm run package +npm run vscode-install ``` -You might need to create additional directories for the `liblldb.so` or -`LLDB.framework` inside or next to the `bin` folder depending on how the -[rpath](https://en.wikipedia.org/wiki/Rpath) is set in your `lldb-dap` -binary. By default the `Debug` builds of LLDB usually includes -the current executable directory in the rpath, so these steps should work for -most people. +## Deploying for Visual Studio Code -To create a plug-in that symlinks into your `lldb-dap` in your build -directory: +The easiest way to deploy the extension for execution on other machines requires +copying `lldb-dap` and its dependencies into a`./bin` subfolder and then create a +standalone VSIX package. ```bash -mkdir -p ~/llvm-org.lldb-dap-0.1.0/bin -cp package.json ~/llvm-org.lldb-dap-0.1.0 -cd ~/llvm-org.lldb-dap-0.1.0/bin -ln -s /path/to/a/built/lldb-dap +cd /path/to/lldb/tools/lldb-dap +mkdir -p ./bin +cp /path/to/a/built/lldb-dap ./bin/ +cp /path/to/a/built/liblldb.so ./bin/ +npm run package ``` -This is handy if you want to debug and develop the `lldb-dap` executable -when adding features or fixing bugs. +This will produce the file `./out/lldb-dap.vsix` that can be distributed. In +this type of installation, users don't need to manually set the path to +`lldb-dap`. The extension will automatically look for it in the `./bin` +subfolder. + +*Note: It's not possible to use symlinks to `lldb-dap`, as the packaging tool +forcefully performs a deep copy of all symlinks.* + +*Note: It's possible to use this kind flow for local installations, but it's +not recommended because updating `lldb-dap` requires rebuilding the extension.* + +# Formatting the Typescript code + +This is also very simple, just run: + +```bash +npm run format +``` # Configurations diff --git a/lldb/tools/lldb-dap/package-lock.json b/lldb/tools/lldb-dap/package-lock.json new file mode 100644 index 000000000000..8c70cc2d30e1 --- /dev/null +++ b/lldb/tools/lldb-dap/package-lock.json @@ -0,0 +1,1679 @@ +{ + "name": "lldb-dap", + "version": "0.2.0", + "lockfileVersion": 3, + "requires": true, + "packages": { + "": { + "name": "lldb-dap", + "version": "0.2.0", + "license": "Apache 2.0 License with LLVM exceptions", + "devDependencies": { + "@types/node": "^18.11.18", + "@types/vscode": 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], - "devDependencies": { - "@types/node": "7.0.43", - "@types/mocha": "2.2.45", - "typescript": "2.6.2", - "mocha": "4.0.1", - "vscode": "1.1.10", - "vscode-debugadapter-testsupport": "1.25.0", - "tslint": "5.8.0", - "vsce": "^1.36.3" - }, - "contributes": { - "languages": [ - { - "id": "lldb.disassembly", - "aliases": [ - "Disassembly" - ], - "extensions": [ - ".disasm" - ] - } - ], - "grammars": [ - { - "language": "lldb.disassembly", - "scopeName": "source.disassembly", - "path": "./syntaxes/disassembly.json" - } - ], - "breakpoints": [ - { - "language": "ada" - }, - { - "language": "arm" - }, - { - "language": "asm" - }, - { - "language": "c" - }, - { - "language": "cpp" - }, - { - "language": "crystal" - }, - { - "language": "d" - }, - { - "language": "fortan" - }, - { - "language": "fortran-modern" - }, - { - "language": "nim" - }, - { - "language": "objective-c" - }, - { - "language": "objectpascal" - }, - { - "language": "pascal" - }, - { - "language": "rust" - }, - { - "language": "swift" - } - ], - "debuggers": [ - { - "type": "lldb-dap", - "label": "Native LLDB Debugger", - "enableBreakpointsFor": { - "languageIds": [ - "ada", - "arm", - "asm", - "c", - "cpp", - "crystal", - "d", - "fortan", - "fortran-modern", - "nim", - "objective-c", - "objectpascal", - "pascal", - "rust", - "swift" - ] - }, - "program": "./bin/lldb-dap", - "windows": { - "program": "./bin/lldb-dap.exe" - }, - "configurationAttributes": { - "launch": { - "required": [ - "program" - ], - "properties": { - "program": { - "type": "string", - "description": "Path to the program to debug." - }, - "args": { - "type": [ - "array", - "string" - ], - "description": "Program arguments.", - "default": [] - }, - "cwd": { - "type": "string", - "description": "Program working directory.", - "default": "${workspaceRoot}" - }, - "env": { - "type": "array", - "description": "Additional environment variables to set when launching the program. This is an array of strings that contains the variable name followed by an optional '=' character and the environment variable's value.", - "default": [] - }, - "stopOnEntry": { - "type": "boolean", - "description": "Automatically stop after launch.", - "default": false - }, - "disableASLR": { - "type": "boolean", - "description": "Enable or disable Address space layout randomization if the debugger supports it.", - "default": true - }, - "disableSTDIO": { - "type": "boolean", - "description": "Don't retrieve STDIN, STDOUT and STDERR as the program is running.", - "default": false - }, - "shellExpandArguments": { - "type": "boolean", - "description": "Expand program arguments as a shell would without actually launching the program in a shell.", - "default": false - }, - "detachOnError": { - "type": "boolean", - "description": "Detach from the program.", - "default": false - }, - "sourcePath": { - "type": "string", - "description": "Specify a source path to remap \"./\" to allow full paths to be used when setting breakpoints in binaries that have relative source paths." - }, - "sourceMap": { - "type": "array", - "description": "Specify an array of path remappings; each element must itself be a two element array containing a source and destination path name. Overrides sourcePath.", - "default": [] - }, - "debuggerRoot": { - "type": "string", - "description": "Specify a working directory to set the debug adapter to so relative object files can be located." - }, - "targetTriple": { - "type": "string", - "description": "Triplet of the target architecture to override value derived from the program file." - }, - "platformName": { - "type": "string", - "description": "Name of the execution platform to override value derived from the program file." - }, - "initCommands": { - "type": "array", - "description": "Initialization commands executed upon debugger startup. Each command can be prefixed with `!` and/or `?` in no particular order. If `?` is provided, then the output of the command is only emitted if it fails, and if `!` is provided, the debug session terminates if the command fails, in which case the output of the command is emitted regardless.", - "default": [] - }, - "preRunCommands": { - "type": "array", - "description": "Commands executed just before the program is launched. Each command can be prefixed with `!` and/or `?` in no particular order. If `?` is provided, then the output of the command is only emitted if it fails, and if `!` is provided, the debug session terminates if the command fails, in which case the output of the command is emitted regardless.", - "default": [] - }, - "postRunCommands": { - "type": "array", - "description": "Commands executed just as soon as the program is successfully launched when it's in a stopped state prior to any automatic continuation. If a command is prefixed with `?`, then its output is only emitted if it fails. Unlike `initCommands` or `launchCommands`, the `!` prefix is ignored.", - "default": [] - }, - "launchCommands": { - "type": "array", - "description": "Custom commands that are executed instead of launching a process. A target will be created with the launch arguments prior to executing these commands. The commands may optionally create a new target and must perform a launch. A valid process must exist after these commands complete or the \"launch\" will fail. Launch the process with \"process launch -s\" to make the process to at the entry point since lldb-dap will auto resume if necessary. Each command can be prefixed with `!` and/or `?` in no particular order. If `?` is provided, then the output of the command is only emitted if it fails, and if `!` is provided, the debug session terminates if the command fails, in which case the output of the command is emitted regardless.", - "default": [] - }, - "stopCommands": { - "type": "array", - "description": "Commands executed each time the program stops. If a command is prefixed with `?`, then its output is only emitted if it fails. Unlike `initCommands` or `launchCommands`, the `!` prefix is ignored.", - "default": [] - }, - "exitCommands": { - "type": "array", - "description": "Commands executed at the end of debugging session. If a command is prefixed with `?`, then its output is only emitted if it fails. Unlike `initCommands` or `launchCommands`, the `!` prefix is ignored.", - "default": [] - }, - "runInTerminal": { - "type": "boolean", - "description": "Launch the program inside an integrated terminal in the IDE. Useful for debugging interactive command line programs", - "default": false - }, - "timeout": { - "type": "string", - "description": "The time in seconds to wait for a program to stop at entry point when launching with \"launchCommands\". Defaults to 30 seconds." - }, - "enableAutoVariableSummaries": { - "type": "boolean", - "description": "Enable auto generated summaries for variables when no summaries exist for a given type. This feature can cause performance delays in large projects when viewing variables.", - "default": false - }, - "enableSyntheticChildDebugging": { - "type": "boolean", - "description": "If a variable is displayed using a synthetic children, also display the actual contents of the variable at the end under a [raw] entry. This is useful when creating sythetic child plug-ins as it lets you see the actual contents of the variable.", - "default": false - }, - "commandEscapePrefix": { - "type": "string", - "description": "The escape prefix to use for executing regular LLDB commands in the Debug Console, instead of printing variables. Defaults to a back-tick (`). If it's an empty string, then all expression in the Debug Console are treated as regular LLDB commands.", - "default": "`" - }, - "customFrameFormat": { - "type": "string", - "description": "If non-empty, stack frames will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for frames. If the format string contains errors, an error message will be displayed on the Debug Console and the default frame names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", - "default": "" - }, - "customThreadFormat": { - "type": "string", - "description": "If non-empty, threads will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for threads. If the format string contains errors, an error message will be displayed on the Debug Console and the default thread names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", - "default": "" - } - } - }, - "attach": { - "properties": { - "program": { - "type": "string", - "description": "Path to the program to attach to." - }, - "pid": { - "type": [ - "number", - "string" - ], - "description": "System process ID to attach to." - }, - "waitFor": { - "type": "boolean", - "description": "If set to true, then wait for the process to launch by looking for a process with a basename that matches `program`. No process ID needs to be specified when using this flag.", - "default": true - }, - "sourcePath": { - "type": "string", - "description": "Specify a source path to remap \"./\" to allow full paths to be used when setting breakpoints in binaries that have relative source paths." - }, - "sourceMap": { - "type": "array", - "description": "Specify an array of path remappings; each element must itself be a two element array containing a source and destination path name. Overrides sourcePath.", - "default": [] - }, - "debuggerRoot": { - "type": "string", - "description": "Specify a working directory to set the debug adapter to so relative object files can be located." - }, - "targetTriple": { - "type": "string", - "description": "Triplet of the target architecture to override value derived from the program file." - }, - "platformName": { - "type": "string", - "description": "Name of the execution platform to override value derived from the program file." - }, - "attachCommands": { - "type": "array", - "description": "Custom commands that are executed instead of attaching to a process ID or to a process by name. These commands may optionally create a new target and must perform an attach. A valid process must exist after these commands complete or the \"attach\" will fail. Each command can be prefixed with `!` and/or `?` in no particular order. If `?` is provided, then the output of the command is only emitted if it fails, and if `!` is provided, the debug session terminates if the command fails, in which case the output of the command is emitted regardless.", - "default": [] - }, - "initCommands": { - "type": "array", - "description": "Initialization commands executed upon debugger startup. Each command can be prefixed with `!` and/or `?` in no particular order. If `?` is provided, then the output of the command is only emitted if it fails, and if `!` is provided, the debug session terminates if the command fails, in which case the output of the command is emitted regardless.", - "default": [] - }, - "preRunCommands": { - "type": "array", - "description": "Commands executed just before the program is attached to. Each command can be prefixed with `!` and/or `?` in no particular order. If `?` is provided, then the output of the command is only emitted if it fails, and if `!` is provided, the debug session terminates if the command fails, in which case the output of the command is emitted regardless.", - "default": [] - }, - "postRunCommands": { - "type": "array", - "description": "Commands executed just as soon as the program is successfully attached when it's in a stopped state prior to any automatic continuation. Each command can be prefixed with `!` and/or `?` in no particular order. If `?` is provided, then the output of the command is only emitted if it fails, and if `!` is provided, the debug session terminates if the command fails, in which case the output of the command is emitted regardless.", - "default": [] - }, - "stopCommands": { - "type": "array", - "description": "Commands executed each time the program stops. If a command is prefixed with `?`, then its output is only emitted if it fails. Unlike `initCommands` or `attachCommands`, the `!` prefix is ignored.", - "default": [] - }, - "exitCommands": { - "type": "array", - "description": "Commands executed at the end of debugging session. If a command is prefixed with `?`, then its output is only emitted if it fails. Unlike `initCommands` or `attachCommands`, the `!` prefix is ignored.", - "default": [] - }, - "coreFile": { - "type": "string", - "description": "Path to the core file to debug." - }, - "timeout": { - "type": "string", - "description": "The time in seconds to wait for a program to stop when attaching using \"attachCommands\". Defaults to 30 seconds." - }, - "enableAutoVariableSummaries": { - "type": "boolean", - "description": "Enable auto generated summaries for variables when no summaries exist for a given type. This feature can cause performance delays in large projects when viewing variables.", - "default": false - }, - "enableSyntheticChildDebugging": { - "type": "boolean", - "description": "If a variable is displayed using a synthetic children, also display the actual contents of the variable at the end under a [raw] entry. This is useful when creating sythetic child plug-ins as it lets you see the actual contents of the variable.", - "default": false - }, - "commandEscapePrefix": { - "type": "string", - "description": "The escape prefix character to use for executing regular LLDB commands in the Debug Console, instead of printing variables. Defaults to a back-tick (`). If empty, then all expression in the Debug Console are treated as regular LLDB commands.", - "default": "`" - }, - "customFrameFormat": { - "type": "string", - "description": "If non-empty, stack frames will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for frames. If the format string contains errors, an error message will be displayed on the Debug Console and the default frame names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", - "default": "" - }, - "customThreadFormat": { - "type": "string", - "description": "If non-empty, threads will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for threads. If the format string contains errors, an error message will be displayed on the Debug Console and the default thread names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", - "default": "" - } - } - } - }, - "initialConfigurations": [ - { - "type": "lldb-dap", - "request": "launch", - "name": "Debug", - "program": "${workspaceRoot}/", - "args": [], - "env": [], - "cwd": "${workspaceRoot}" - } - ], - "configurationSnippets": [ - { - "label": "LLDB: Launch", - "description": "", - "body": { - "type": "lldb-dap", - "request": "launch", - "name": "${2:Launch}", - "program": "^\"\\${workspaceRoot}/${1:}\"", - "args": [], - "env": [], - "cwd": "^\"\\${workspaceRoot}\"" - } - } - ] - } - ] - } + "name": "lldb-dap", + "displayName": "LLDB DAP", + "version": "0.2.0", + "publisher": "llvm", + "homepage": "https://lldb.llvm.org", + "description": "LLDB debugging from VSCode", + "license": "Apache 2.0 License with LLVM exceptions", + "repository": { + "type": "git", + "url": "https://github.com/llvm/llvm-project.git" + }, + "bugs": { + "url": "https://github.com/llvm/llvm-project/issues" + }, + "keywords": [ + "C", + "C++", + "LLVM", + "LLDB" + ], + "engines": { + "vscode": "^1.75.0" + }, + "categories": [ + "Debuggers" + ], + "devDependencies": { + "@types/node": "^18.11.18", + "@types/vscode": "~1.74.0", + "@vscode/vsce": "^2.19.0", + "prettier-plugin-curly": "^0.1.3", + "prettier": "^3.1.1", + "typescript": "^4.6.4" + }, + "activationEvents": [ + "onDebug" + ], + "main": "./out/extension", + "scripts": { + "vscode:prepublish": "tsc -p ./", + "watch": "tsc -watch -p ./", + "format": "npx prettier './src-ts/' --write", + "package": "vsce package --out ./out/lldb-dap.vsix", + "vscode-uninstall": "code --uninstall-extension llvm.lldb-dap", + "vscode-install": "code --install-extension ./out/lldb-dap.vsix" + }, + "contributes": { + "languages": [ + { + "id": "lldb.disassembly", + "aliases": [ + "Disassembly" + ], + "extensions": [ + ".disasm" + ] + } + ], + "grammars": [ + { + "language": "lldb.disassembly", + "scopeName": "source.disassembly", + "path": "./syntaxes/disassembly.json" + } + ], + "configuration": { + "type": "object", + "title": "lldb-dap", + "properties": { + "lldb-dap.executable-path": { + "scope": "resource", + "type": "string", + "description": "The path to the lldb-dap binary." + } + } + }, + "breakpoints": [ + { + "language": "ada" + }, + { + "language": "arm" + }, + { + "language": "asm" + }, + { + "language": "c" + }, + { + "language": "cpp" + }, + { + "language": "crystal" + }, + { + "language": "d" + }, + { + "language": "fortan" + }, + { + "language": "fortran-modern" + }, + { + "language": "nim" + }, + { + "language": "objective-c" + }, + { + "language": "objectpascal" + }, + { + "language": "pascal" + }, + { + "language": "rust" + }, + { + "language": "swift" + } + ], + "debuggers": [ + { + "type": "lldb-dap", + "label": "Native LLDB Debugger", + "program": "./bin/lldb-dap", + "windows": { + "program": "./bin/lldb-dap.exe" + }, + "configurationAttributes": { + "launch": { + "required": [ + "program" + ], + "properties": { + "program": { + "type": "string", + "description": "Path to the program to debug." + }, + "args": { + "type": [ + "array", + "string" + ], + "description": "Program arguments.", + "default": [] + }, + "cwd": { + "type": "string", + "description": "Program working directory.", + "default": "${workspaceRoot}" + }, + "env": { + "type": "array", + "description": "Additional environment variables to set when launching the program. This is an array of strings that contains the variable name followed by an optional '=' character and the environment variable's value.", + "default": [] + }, + "stopOnEntry": { + "type": "boolean", + "description": "Automatically stop after launch.", + "default": false + }, + "disableASLR": { + "type": "boolean", + "description": "Enable or disable Address space layout randomization if the debugger supports it.", + "default": true + }, + "disableSTDIO": { + "type": "boolean", + "description": "Don't retrieve STDIN, STDOUT and STDERR as the program is running.", + "default": false + }, + "shellExpandArguments": { + "type": "boolean", + "description": "Expand program arguments as a shell would without actually launching the program in a shell.", + "default": false + }, + "detachOnError": { + "type": "boolean", + "description": "Detach from the program.", + "default": false + }, + "sourcePath": { + "type": "string", + "description": "Specify a source path to remap \"./\" to allow full paths to be used when setting breakpoints in binaries that have relative source paths." + }, + "sourceMap": { + "type": "array", + "description": "Specify an array of path remappings; each element must itself be a two element array containing a source and destination path name. Overrides sourcePath.", + "default": [] + }, + "debuggerRoot": { + "type": "string", + "description": "Specify a working directory to set the debug adapter to so relative object files can be located." + }, + "targetTriple": { + "type": "string", + "description": "Triplet of the target architecture to override value derived from the program file." + }, + "platformName": { + "type": "string", + "description": "Name of the execution platform to override value derived from the program file." + }, + "initCommands": { + "type": "array", + "description": "Initialization commands executed upon debugger startup.", + "default": [] + }, + "preRunCommands": { + "type": "array", + "description": "Commands executed just before the program is launched.", + "default": [] + }, + "postRunCommands": { + "type": "array", + "description": "Commands executed just as soon as the program is successfully launched when it's in a stopped state prior to any automatic continuation.", + "default": [] + }, + "launchCommands": { + "type": "array", + "description": "Custom commands that are executed instead of launching a process. A target will be created with the launch arguments prior to executing these commands. The commands may optionally create a new target and must perform a launch. A valid process must exist after these commands complete or the \"launch\" will fail. Launch the process with \"process launch -s\" to make the process to at the entry point since lldb-dap will auto resume if necessary.", + "default": [] + }, + "stopCommands": { + "type": "array", + "description": "Commands executed each time the program stops.", + "default": [] + }, + "exitCommands": { + "type": "array", + "description": "Commands executed at the end of debugging session.", + "default": [] + }, + "runInTerminal": { + "type": "boolean", + "description": "Launch the program inside an integrated terminal in the IDE. Useful for debugging interactive command line programs", + "default": false + }, + "timeout": { + "type": "string", + "description": "The time in seconds to wait for a program to stop at entry point when launching with \"launchCommands\". Defaults to 30 seconds." + }, + "enableAutoVariableSummaries": { + "type": "boolean", + "description": "Enable auto generated summaries for variables when no summaries exist for a given type. This feature can cause performance delays in large projects when viewing variables.", + "default": false + }, + "enableSyntheticChildDebugging": { + "type": "boolean", + "description": "If a variable is displayed using a synthetic children, also display the actual contents of the variable at the end under a [raw] entry. This is useful when creating sythetic child plug-ins as it lets you see the actual contents of the variable.", + "default": false + }, + "commandEscapePrefix": { + "type": "string", + "description": "The escape prefix to use for executing regular LLDB commands in the Debug Console, instead of printing variables. Defaults to a back-tick (`). If it's an empty string, then all expression in the Debug Console are treated as regular LLDB commands.", + "default": "`" + }, + "customFrameFormat": { + "type": "string", + "description": "If non-empty, stack frames will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for frames. If the format string contains errors, an error message will be displayed on the Debug Console and the default frame names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", + "default": "" + }, + "customThreadFormat": { + "type": "string", + "description": "If non-empty, threads will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for threads. If the format string contains errors, an error message will be displayed on the Debug Console and the default thread names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", + "default": "" + } + } + }, + "attach": { + "properties": { + "program": { + "type": "string", + "description": "Path to the program to attach to." + }, + "pid": { + "type": [ + "number", + "string" + ], + "description": "System process ID to attach to." + }, + "waitFor": { + "type": "boolean", + "description": "If set to true, then wait for the process to launch by looking for a process with a basename that matches `program`. No process ID needs to be specified when using this flag.", + "default": true + }, + "sourcePath": { + "type": "string", + "description": "Specify a source path to remap \"./\" to allow full paths to be used when setting breakpoints in binaries that have relative source paths." + }, + "sourceMap": { + "type": "array", + "description": "Specify an array of path remappings; each element must itself be a two element array containing a source and destination path name. Overrides sourcePath.", + "default": [] + }, + "debuggerRoot": { + "type": "string", + "description": "Specify a working directory to set the debug adapter to so relative object files can be located." + }, + "targetTriple": { + "type": "string", + "description": "Triplet of the target architecture to override value derived from the program file." + }, + "platformName": { + "type": "string", + "description": "Name of the execution platform to override value derived from the program file." + }, + "attachCommands": { + "type": "array", + "description": "Custom commands that are executed instead of attaching to a process ID or to a process by name. These commands may optionally create a new target and must perform an attach. A valid process must exist after these commands complete or the \"attach\" will fail.", + "default": [] + }, + "initCommands": { + "type": "array", + "description": "Initialization commands executed upon debugger startup.", + "default": [] + }, + "preRunCommands": { + "type": "array", + "description": "Commands executed just before the program is attached to.", + "default": [] + }, + "postRunCommands": { + "type": "array", + "description": "Commands executed just as soon as the program is successfully attached when it's in a stopped state prior to any automatic continuation.", + "default": [] + }, + "stopCommands": { + "type": "array", + "description": "Commands executed each time the program stops.", + "default": [] + }, + "exitCommands": { + "type": "array", + "description": "Commands executed at the end of debugging session.", + "default": [] + }, + "coreFile": { + "type": "string", + "description": "Path to the core file to debug." + }, + "timeout": { + "type": "string", + "description": "The time in seconds to wait for a program to stop when attaching using \"attachCommands\". Defaults to 30 seconds." + }, + "enableAutoVariableSummaries": { + "type": "boolean", + "description": "Enable auto generated summaries for variables when no summaries exist for a given type. This feature can cause performance delays in large projects when viewing variables.", + "default": false + }, + "enableSyntheticChildDebugging": { + "type": "boolean", + "description": "If a variable is displayed using a synthetic children, also display the actual contents of the variable at the end under a [raw] entry. This is useful when creating sythetic child plug-ins as it lets you see the actual contents of the variable.", + "default": false + }, + "commandEscapePrefix": { + "type": "string", + "description": "The escape prefix character to use for executing regular LLDB commands in the Debug Console, instead of printing variables. Defaults to a back-tick (`). If empty, then all expression in the Debug Console are treated as regular LLDB commands.", + "default": "`" + }, + "customFrameFormat": { + "type": "string", + "description": "If non-empty, stack frames will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for frames. If the format string contains errors, an error message will be displayed on the Debug Console and the default frame names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", + "default": "" + }, + "customThreadFormat": { + "type": "string", + "description": "If non-empty, threads will have descriptions generated based on the provided format. See https://lldb.llvm.org/use/formatting.html for an explanation on format strings for threads. If the format string contains errors, an error message will be displayed on the Debug Console and the default thread names will be used. This might come with a performance cost because debug information might need to be processed to generate the description.", + "default": "" + } + } + } + }, + "initialConfigurations": [ + { + "type": "lldb-dap", + "request": "launch", + "name": "Debug", + "program": "${workspaceRoot}/", + "args": [], + "env": [], + "cwd": "${workspaceRoot}" + } + ], + "configurationSnippets": [ + { + "label": "LLDB: Launch", + "description": "", + "body": { + "type": "lldb-dap", + "request": "launch", + "name": "${2:Launch}", + "program": "^\"\\${workspaceRoot}/${1:}\"", + "args": [], + "env": [], + "cwd": "^\"\\${workspaceRoot}\"" + } + } + ] + } + ] + } } diff --git a/lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts b/lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts new file mode 100644 index 000000000000..01c671f41ff7 --- /dev/null +++ b/lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts @@ -0,0 +1,23 @@ +import * as vscode from "vscode"; +import { LLDBDapOptions } from "./types"; + +/** + * This class defines a factory used to find the lldb-dap binary to use + * depending on the session configuration. + */ +export class LLDBDapDescriptorFactory + implements vscode.DebugAdapterDescriptorFactory +{ + private lldbDapOptions: LLDBDapOptions; + + constructor(lldbDapOptions: LLDBDapOptions) { + this.lldbDapOptions = lldbDapOptions; + } + + async createDebugAdapterDescriptor( + session: vscode.DebugSession, + executable: vscode.DebugAdapterExecutable | undefined, + ): Promise { + return this.lldbDapOptions.createDapExecutableCommand(session, executable); + } +} diff --git a/lldb/tools/lldb-dap/src-ts/disposable-context.ts b/lldb/tools/lldb-dap/src-ts/disposable-context.ts new file mode 100644 index 000000000000..39d9f18d2d85 --- /dev/null +++ b/lldb/tools/lldb-dap/src-ts/disposable-context.ts @@ -0,0 +1,27 @@ +import * as vscode from "vscode"; + +/** + * This class provides a simple wrapper around vscode.Disposable that allows + * for registering additional disposables. + */ +export class DisposableContext implements vscode.Disposable { + private _disposables: vscode.Disposable[] = []; + + constructor() {} + + public dispose() { + for (const disposable of this._disposables) { + disposable.dispose(); + } + this._disposables = []; + } + + /** + * Push an additional disposable to the context. + * + * @param disposable The disposable to register. + */ + public pushSubscription(disposable: vscode.Disposable) { + this._disposables.push(disposable); + } +} diff --git a/lldb/tools/lldb-dap/src-ts/extension.ts b/lldb/tools/lldb-dap/src-ts/extension.ts new file mode 100644 index 000000000000..791175f7b462 --- /dev/null +++ b/lldb/tools/lldb-dap/src-ts/extension.ts @@ -0,0 +1,55 @@ +import * as vscode from "vscode"; +import { LLDBDapOptions } from "./types"; +import { DisposableContext } from "./disposable-context"; +import { LLDBDapDescriptorFactory } from "./debug-adapter-factory"; + +/** + * This creates the configurations for this project if used as a standalone + * extension. + */ +function createDefaultLLDBDapOptions(): LLDBDapOptions { + return { + debuggerType: "lldb-dap", + async createDapExecutableCommand( + session: vscode.DebugSession, + packageJSONExecutable: vscode.DebugAdapterExecutable | undefined, + ): Promise { + const path = vscode.workspace + .getConfiguration("lldb-dap", session.workspaceFolder) + .get("executable-path"); + if (path) { + return new vscode.DebugAdapterExecutable(path, []); + } + return packageJSONExecutable; + }, + }; +} + +/** + * This class represents the extension and manages its life cycle. Other extensions + * using it as as library should use this class as the main entry point. + */ +export class LLDBDapExtension extends DisposableContext { + private lldbDapOptions: LLDBDapOptions; + + constructor(lldbDapOptions: LLDBDapOptions) { + super(); + this.lldbDapOptions = lldbDapOptions; + + this.pushSubscription( + vscode.debug.registerDebugAdapterDescriptorFactory( + this.lldbDapOptions.debuggerType, + new LLDBDapDescriptorFactory(this.lldbDapOptions), + ), + ); + } +} + +/** + * This is the entry point when initialized by VS Code. + */ +export function activate(context: vscode.ExtensionContext) { + context.subscriptions.push( + new LLDBDapExtension(createDefaultLLDBDapOptions()), + ); +} diff --git a/lldb/tools/lldb-dap/src-ts/types.ts b/lldb/tools/lldb-dap/src-ts/types.ts new file mode 100644 index 000000000000..63a8c73982ca --- /dev/null +++ b/lldb/tools/lldb-dap/src-ts/types.ts @@ -0,0 +1,23 @@ +import * as vscode from "vscode"; + +/** + * Callback used to generate the actual command to be executed to launch the lldb-dap binary. + * + * @param session - The information of the debug session to be launched. + * + * @param packageJSONExecutable - An optional {@link vscode.DebugAdapterExecutable executable} for + * lldb-dap if specified in the package.json file. + */ +export type LLDBDapCreateDAPExecutableCommand = ( + session: vscode.DebugSession, + packageJSONExecutable: vscode.DebugAdapterExecutable | undefined, +) => Promise; + +/** + * The options that this extension accepts. + */ +export interface LLDBDapOptions { + createDapExecutableCommand: LLDBDapCreateDAPExecutableCommand; + // The name of the debugger type as specified in the package.json file. + debuggerType: string; +} diff --git a/lldb/tools/lldb-dap/tsconfig.json b/lldb/tools/lldb-dap/tsconfig.json new file mode 100644 index 000000000000..209214888890 --- /dev/null +++ b/lldb/tools/lldb-dap/tsconfig.json @@ -0,0 +1,16 @@ +{ + "compilerOptions": { + "module": "commonjs", + "outDir": "out", + "rootDir": "src-ts", + "sourceMap": true, + "strict": true, + "target": "es6" + }, + "include": [ + "src-ts" + ], + "exclude": [ + "node_modules", + ] +} -- GitLab From a7262d2d9bee9bdfdbcd03ca27a0128c2e2b1c1a Mon Sep 17 00:00:00 2001 From: Ivan Butygin Date: Tue, 9 Jan 2024 23:17:36 +0100 Subject: [PATCH 269/652] [mlir][arith] Add overflow flags support to arith ops (#77211) Add overflow flags support to the following ops: * `arith.addi` * `arith.subi` * `arith.muli` Example of new syntax: ``` %res = arith.addi %arg1, %arg2 overflow : i64 ``` Similar to existing LLVM dialect syntax ``` %res = llvm.add %arg1, %arg2 overflow : i64 ``` Tablegen canonicalization patterns updated to always drop flags, proper support with tests will be added later. Updated LLVMIR translation as part of this commit as it currenly written in a way that it will crash when new attributes added to arith ops otherwise. Discussion https://discourse.llvm.org/t/rfc-integer-overflow-flags-support-in-arith-dialect/76025 --------- Co-authored-by: Yi Wu --- .../ArithCommon/AttrToLLVMConverter.h | 47 +++++++- .../mlir/Dialect/Arith/IR/ArithBase.td | 23 ++++ .../include/mlir/Dialect/Arith/IR/ArithOps.td | 101 ++++++++++++++---- .../Dialect/Arith/IR/ArithOpsInterfaces.td | 57 ++++++++++ .../ArithCommon/AttrToLLVMConverter.cpp | 29 ++++- .../Conversion/ArithToLLVM/ArithToLLVM.cpp | 12 ++- .../Dialect/Arith/IR/ArithCanonicalization.td | 94 +++++++++------- mlir/lib/Dialect/Arith/IR/ArithOps.cpp | 5 + .../Conversion/ArithToLLVM/arith-to-llvm.mlir | 13 +++ mlir/test/Dialect/Arith/ops.mlir | 11 ++ mlir/test/python/ir/diagnostic_handler.py | 2 +- 11 files changed, 321 insertions(+), 73 deletions(-) diff --git a/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h b/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h index eea16b4da6a6..0296ec969d0b 100644 --- a/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h +++ b/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h @@ -18,14 +18,24 @@ namespace mlir { namespace arith { -// Map arithmetic fastmath enum values to LLVMIR enum values. +/// Maps arithmetic fastmath enum values to LLVM enum values. LLVM::FastmathFlags convertArithFastMathFlagsToLLVM(arith::FastMathFlags arithFMF); -// Create an LLVM fastmath attribute from a given arithmetic fastmath attribute. +/// Creates an LLVM fastmath attribute from a given arithmetic fastmath +/// attribute. LLVM::FastmathFlagsAttr convertArithFastMathAttrToLLVM(arith::FastMathFlagsAttr fmfAttr); +/// Maps arithmetic overflow enum values to LLVM enum values. +LLVM::IntegerOverflowFlags +convertArithOveflowFlagsToLLVM(arith::IntegerOverflowFlags arithFlags); + +/// Creates an LLVM overflow attribute from a given arithmetic overflow +/// attribute. +LLVM::IntegerOverflowFlagsAttr +convertArithOveflowAttrToLLVM(arith::IntegerOverflowFlagsAttr flagsAttr); + // Attribute converter that populates a NamedAttrList by removing the fastmath // attribute from the source operation attributes, and replacing it with an // equivalent LLVM fastmath attribute. @@ -36,12 +46,12 @@ public: // Copy the source attributes. convertedAttr = NamedAttrList{srcOp->getAttrs()}; // Get the name of the arith fastmath attribute. - llvm::StringRef arithFMFAttrName = SourceOp::getFastMathAttrName(); + StringRef arithFMFAttrName = SourceOp::getFastMathAttrName(); // Remove the source fastmath attribute. - auto arithFMFAttr = dyn_cast_or_null( + auto arithFMFAttr = dyn_cast_if_present( convertedAttr.erase(arithFMFAttrName)); if (arithFMFAttr) { - llvm::StringRef targetAttrName = TargetOp::getFastmathAttrName(); + StringRef targetAttrName = TargetOp::getFastmathAttrName(); convertedAttr.set(targetAttrName, convertArithFastMathAttrToLLVM(arithFMFAttr)); } @@ -49,6 +59,33 @@ public: ArrayRef getAttrs() const { return convertedAttr.getAttrs(); } +private: + NamedAttrList convertedAttr; +}; + +// Attribute converter that populates a NamedAttrList by removing the overflow +// attribute from the source operation attributes, and replacing it with an +// equivalent LLVM overflow attribute. +template +class AttrConvertOverflowToLLVM { +public: + AttrConvertOverflowToLLVM(SourceOp srcOp) { + // Copy the source attributes. + convertedAttr = NamedAttrList{srcOp->getAttrs()}; + // Get the name of the arith overflow attribute. + StringRef arithAttrName = SourceOp::getIntegerOverflowAttrName(); + // Remove the source overflow attribute. + auto arithAttr = dyn_cast_if_present( + convertedAttr.erase(arithAttrName)); + if (arithAttr) { + StringRef targetAttrName = TargetOp::getIntegerOverflowAttrName(); + convertedAttr.set(targetAttrName, + convertArithOveflowAttrToLLVM(arithAttr)); + } + } + + ArrayRef getAttrs() const { return convertedAttr.getAttrs(); } + private: NamedAttrList convertedAttr; }; diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td b/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td index 1e4061392b22..3fb7f948b0a4 100644 --- a/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td +++ b/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td @@ -133,4 +133,27 @@ def Arith_FastMathAttr : let assemblyFormat = "`<` $value `>`"; } +//===----------------------------------------------------------------------===// +// IntegerOverflowFlags +//===----------------------------------------------------------------------===// + +def IOFnone : I32BitEnumAttrCaseNone<"none">; +def IOFnsw : I32BitEnumAttrCaseBit<"nsw", 0>; +def IOFnuw : I32BitEnumAttrCaseBit<"nuw", 1>; + +def IntegerOverflowFlags : I32BitEnumAttr< + "IntegerOverflowFlags", + "Integer overflow arith flags", + [IOFnone, IOFnsw, IOFnuw]> { + let separator = ", "; + let cppNamespace = "::mlir::arith"; + let genSpecializedAttr = 0; + let printBitEnumPrimaryGroups = 1; +} + +def Arith_IntegerOverflowAttr : + EnumAttr { + let assemblyFormat = "`<` $value `>`"; +} + #endif // ARITH_BASE diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td index 6d133d69dd0f..cd0102f91ef1 100644 --- a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td +++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td @@ -137,6 +137,20 @@ class Arith_CompareOpOfAnyRank traits = []> : let results = (outs BoolLikeOfAnyRank:$result); } +class Arith_IntBinaryOpWithOverflowFlags traits = []> : + Arith_BinaryOp, + DeclareOpInterfaceMethods]>, + Arguments<(ins SignlessIntegerLike:$lhs, SignlessIntegerLike:$rhs, + DefaultValuedAttr< + Arith_IntegerOverflowAttr, + "::mlir::arith::IntegerOverflowFlags::none">:$overflowFlags)>, + Results<(outs SignlessIntegerLike:$result)> { + + let assemblyFormat = [{ $lhs `,` $rhs (`overflow` `` $overflowFlags^)? + attr-dict `:` type($result) }]; +} + //===----------------------------------------------------------------------===// // ConstantOp //===----------------------------------------------------------------------===// @@ -192,7 +206,7 @@ def Arith_ConstantOp : Op { +def Arith_AddIOp : Arith_IntBinaryOpWithOverflowFlags<"addi", [Commutative]> { let summary = "integer addition operation"; let description = [{ Performs N-bit addition on the operands. The operands are interpreted as @@ -203,8 +217,12 @@ def Arith_AddIOp : Arith_TotalIntBinaryOp<"addi", [Commutative]> { The `addi` operation takes two operands and returns one result, each of these is required to be the same type. This type may be an integer scalar type, - a vector whose element type is integer, or a tensor of integers. It has no - standard attributes. + a vector whose element type is integer, or a tensor of integers. + + This op supports `nuw`/`nsw` overflow flags which stands stand for + "No Unsigned Wrap" and "No Signed Wrap", respectively. If the `nuw` and/or + `nsw` flags are present, and an unsigned/signed overflow occurs + (respectively), the result is poison. Example: @@ -212,7 +230,10 @@ def Arith_AddIOp : Arith_TotalIntBinaryOp<"addi", [Commutative]> { // Scalar addition. %a = arith.addi %b, %c : i64 - // SIMD vector element-wise addition, e.g. for Intel SSE. + // Scalar addition with overflow flags. + %a = arith.addi %b, %c overflow : i64 + + // SIMD vector element-wise addition. %f = arith.addi %g, %h : vector<4xi32> // Tensor element-wise addition. @@ -278,21 +299,41 @@ def Arith_AddUIExtendedOp : Arith_Op<"addui_extended", [Pure, Commutative, // SubIOp //===----------------------------------------------------------------------===// -def Arith_SubIOp : Arith_TotalIntBinaryOp<"subi"> { +def Arith_SubIOp : Arith_IntBinaryOpWithOverflowFlags<"subi"> { let summary = [{ Integer subtraction operation. }]; let description = [{ - Performs N-bit subtraction on the operands. The operands are interpreted as unsigned - bitvectors. The result is represented by a bitvector containing the mathematical - value of the subtraction modulo 2^n, where `n` is the bitwidth. Because `arith` - integers use a two's complement representation, this operation is applicable on + Performs N-bit subtraction on the operands. The operands are interpreted as unsigned + bitvectors. The result is represented by a bitvector containing the mathematical + value of the subtraction modulo 2^n, where `n` is the bitwidth. Because `arith` + integers use a two's complement representation, this operation is applicable on both signed and unsigned integer operands. The `subi` operation takes two operands and returns one result, each of - these is required to be the same type. This type may be an integer scalar type, - a vector whose element type is integer, or a tensor of integers. It has no - standard attributes. + these is required to be the same type. This type may be an integer scalar type, + a vector whose element type is integer, or a tensor of integers. + + This op supports `nuw`/`nsw` overflow flags which stands stand for + "No Unsigned Wrap" and "No Signed Wrap", respectively. If the `nuw` and/or + `nsw` flags are present, and an unsigned/signed overflow occurs + (respectively), the result is poison. + + Example: + + ```mlir + // Scalar subtraction. + %a = arith.subi %b, %c : i64 + + // Scalar subtraction with overflow flags. + %a = arith.subi %b, %c overflow : i64 + + // SIMD vector element-wise subtraction. + %f = arith.subi %g, %h : vector<4xi32> + + // Tensor element-wise subtraction. + %x = arith.subi %y, %z : tensor<4x?xi8> + ``` }]; let hasFolder = 1; let hasCanonicalizer = 1; @@ -302,21 +343,41 @@ def Arith_SubIOp : Arith_TotalIntBinaryOp<"subi"> { // MulIOp //===----------------------------------------------------------------------===// -def Arith_MulIOp : Arith_TotalIntBinaryOp<"muli", [Commutative]> { +def Arith_MulIOp : Arith_IntBinaryOpWithOverflowFlags<"muli", [Commutative]> { let summary = [{ Integer multiplication operation. }]; let description = [{ - Performs N-bit multiplication on the operands. The operands are interpreted as - unsigned bitvectors. The result is represented by a bitvector containing the - mathematical value of the multiplication modulo 2^n, where `n` is the bitwidth. - Because `arith` integers use a two's complement representation, this operation is + Performs N-bit multiplication on the operands. The operands are interpreted as + unsigned bitvectors. The result is represented by a bitvector containing the + mathematical value of the multiplication modulo 2^n, where `n` is the bitwidth. + Because `arith` integers use a two's complement representation, this operation is applicable on both signed and unsigned integer operands. The `muli` operation takes two operands and returns one result, each of - these is required to be the same type. This type may be an integer scalar type, - a vector whose element type is integer, or a tensor of integers. It has no - standard attributes. + these is required to be the same type. This type may be an integer scalar type, + a vector whose element type is integer, or a tensor of integers. + + This op supports `nuw`/`nsw` overflow flags which stands stand for + "No Unsigned Wrap" and "No Signed Wrap", respectively. If the `nuw` and/or + `nsw` flags are present, and an unsigned/signed overflow occurs + (respectively), the result is poison. + + Example: + + ```mlir + // Scalar multiplication. + %a = arith.muli %b, %c : i64 + + // Scalar multiplication with overflow flags. + %a = arith.muli %b, %c overflow : i64 + + // SIMD vector element-wise multiplication. + %f = arith.muli %g, %h : vector<4xi32> + + // Tensor element-wise multiplication. + %x = arith.muli %y, %z : tensor<4x?xi8> + ``` }]; let hasFolder = 1; let hasCanonicalizer = 1; diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td b/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td index acaecf6f409d..e248422f84db 100644 --- a/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td +++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td @@ -49,4 +49,61 @@ def ArithFastMathInterface : OpInterface<"ArithFastMathInterface"> { ]; } +def ArithIntegerOverflowFlagsInterface : OpInterface<"ArithIntegerOverflowFlagsInterface"> { + let description = [{ + Access to op integer overflow flags. + }]; + + let cppNamespace = "::mlir::arith"; + + let methods = [ + InterfaceMethod< + /*desc=*/ "Returns an IntegerOverflowFlagsAttr attribute for the operation", + /*returnType=*/ "IntegerOverflowFlagsAttr", + /*methodName=*/ "getOverflowAttr", + /*args=*/ (ins), + /*methodBody=*/ [{}], + /*defaultImpl=*/ [{ + auto op = cast(this->getOperation()); + return op.getOverflowFlagsAttr(); + }] + >, + InterfaceMethod< + /*desc=*/ "Returns whether the operation has the No Unsigned Wrap keyword", + /*returnType=*/ "bool", + /*methodName=*/ "hasNoUnsignedWrap", + /*args=*/ (ins), + /*methodBody=*/ [{}], + /*defaultImpl=*/ [{ + auto op = cast(this->getOperation()); + IntegerOverflowFlags flags = op.getOverflowFlagsAttr().getValue(); + return bitEnumContainsAll(flags, IntegerOverflowFlags::nuw); + }] + >, + InterfaceMethod< + /*desc=*/ "Returns whether the operation has the No Signed Wrap keyword", + /*returnType=*/ "bool", + /*methodName=*/ "hasNoSignedWrap", + /*args=*/ (ins), + /*methodBody=*/ [{}], + /*defaultImpl=*/ [{ + auto op = cast(this->getOperation()); + IntegerOverflowFlags flags = op.getOverflowFlagsAttr().getValue(); + return bitEnumContainsAll(flags, IntegerOverflowFlags::nsw); + }] + >, + StaticInterfaceMethod< + /*desc=*/ [{Returns the name of the IntegerOveflowFlagsAttr attribute + for the operation}], + /*returnType=*/ "StringRef", + /*methodName=*/ "getIntegerOverflowAttrName", + /*args=*/ (ins), + /*methodBody=*/ [{}], + /*defaultImpl=*/ [{ + return "overflowFlags"; + }] + > + ]; +} + #endif // ARITH_OPS_INTERFACES diff --git a/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp b/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp index 8c5d76f9f2d7..3e9aef87b9ef 100644 --- a/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp +++ b/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp @@ -10,7 +10,6 @@ using namespace mlir; -// Map arithmetic fastmath enum values to LLVMIR enum values. LLVM::FastmathFlags mlir::arith::convertArithFastMathFlagsToLLVM(arith::FastMathFlags arithFMF) { LLVM::FastmathFlags llvmFMF{}; @@ -22,17 +21,37 @@ mlir::arith::convertArithFastMathFlagsToLLVM(arith::FastMathFlags arithFMF) { {arith::FastMathFlags::contract, LLVM::FastmathFlags::contract}, {arith::FastMathFlags::afn, LLVM::FastmathFlags::afn}, {arith::FastMathFlags::reassoc, LLVM::FastmathFlags::reassoc}}; - for (auto fmfMap : flags) { - if (bitEnumContainsAny(arithFMF, fmfMap.first)) - llvmFMF = llvmFMF | fmfMap.second; + for (auto [arithFlag, llvmFlag] : flags) { + if (bitEnumContainsAny(arithFMF, arithFlag)) + llvmFMF = llvmFMF | llvmFlag; } return llvmFMF; } -// Create an LLVM fastmath attribute from a given arithmetic fastmath attribute. LLVM::FastmathFlagsAttr mlir::arith::convertArithFastMathAttrToLLVM(arith::FastMathFlagsAttr fmfAttr) { arith::FastMathFlags arithFMF = fmfAttr.getValue(); return LLVM::FastmathFlagsAttr::get( fmfAttr.getContext(), convertArithFastMathFlagsToLLVM(arithFMF)); } + +LLVM::IntegerOverflowFlags mlir::arith::convertArithOveflowFlagsToLLVM( + arith::IntegerOverflowFlags arithFlags) { + LLVM::IntegerOverflowFlags llvmFlags{}; + const std::pair + flags[] = { + {arith::IntegerOverflowFlags::nsw, LLVM::IntegerOverflowFlags::nsw}, + {arith::IntegerOverflowFlags::nuw, LLVM::IntegerOverflowFlags::nuw}}; + for (auto [arithFlag, llvmFlag] : flags) { + if (bitEnumContainsAny(arithFlags, arithFlag)) + llvmFlags = llvmFlags | llvmFlag; + } + return llvmFlags; +} + +LLVM::IntegerOverflowFlagsAttr mlir::arith::convertArithOveflowAttrToLLVM( + arith::IntegerOverflowFlagsAttr flagsAttr) { + arith::IntegerOverflowFlags arithFlags = flagsAttr.getValue(); + return LLVM::IntegerOverflowFlagsAttr::get( + flagsAttr.getContext(), convertArithOveflowFlagsToLLVM(arithFlags)); +} diff --git a/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp b/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp index 5e4213cc4e87..cf46e0d3ac46 100644 --- a/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp +++ b/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp @@ -35,7 +35,9 @@ namespace { using AddFOpLowering = VectorConvertToLLVMPattern; -using AddIOpLowering = VectorConvertToLLVMPattern; +using AddIOpLowering = + VectorConvertToLLVMPattern; using AndIOpLowering = VectorConvertToLLVMPattern; using BitcastOpLowering = VectorConvertToLLVMPattern; @@ -78,7 +80,9 @@ using MinUIOpLowering = using MulFOpLowering = VectorConvertToLLVMPattern; -using MulIOpLowering = VectorConvertToLLVMPattern; +using MulIOpLowering = + VectorConvertToLLVMPattern; using NegFOpLowering = VectorConvertToLLVMPattern; @@ -102,7 +106,9 @@ using SIToFPOpLowering = using SubFOpLowering = VectorConvertToLLVMPattern; -using SubIOpLowering = VectorConvertToLLVMPattern; +using SubIOpLowering = + VectorConvertToLLVMPattern; using TruncFOpLowering = VectorConvertToLLVMPattern; using TruncIOpLowering = diff --git a/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td b/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td index ef951647ccd1..18ceeb005404 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td +++ b/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td @@ -24,6 +24,12 @@ def SubIntAttrs : NativeCodeCall<"subIntegerAttrs($_builder, $0, $1, $2)">; // Multiply two integer attributes and create a new one with the result. def MulIntAttrs : NativeCodeCall<"mulIntegerAttrs($_builder, $0, $1, $2)">; +// TODO: Canonicalizations currently doesn't take into account integer overflow +// flags and always reset them to default (wraparound) which is safe but can +// inhibit later optimizations. Individual patterns must be reviewed for +// better handling of overflow flags. +def DefOverflow : NativeCodeCall<"getDefOverflowFlags($_builder)">; + class cast : NativeCodeCall<"::mlir::cast<" # type # ">($0)">; //===----------------------------------------------------------------------===// @@ -36,23 +42,26 @@ class cast : NativeCodeCall<"::mlir::cast<" # type # ">($0)">; // addi(addi(x, c0), c1) -> addi(x, c0 + c1) def AddIAddConstant : Pat<(Arith_AddIOp:$res - (Arith_AddIOp $x, (ConstantLikeMatcher APIntAttr:$c0)), - (ConstantLikeMatcher APIntAttr:$c1)), - (Arith_AddIOp $x, (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)))>; + (Arith_AddIOp $x, (ConstantLikeMatcher APIntAttr:$c0), $ovf1), + (ConstantLikeMatcher APIntAttr:$c1), $ovf2), + (Arith_AddIOp $x, (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)), + (DefOverflow))>; // addi(subi(x, c0), c1) -> addi(x, c1 - c0) def AddISubConstantRHS : Pat<(Arith_AddIOp:$res - (Arith_SubIOp $x, (ConstantLikeMatcher APIntAttr:$c0)), - (ConstantLikeMatcher APIntAttr:$c1)), - (Arith_AddIOp $x, (Arith_ConstantOp (SubIntAttrs $res, $c1, $c0)))>; + (Arith_SubIOp $x, (ConstantLikeMatcher APIntAttr:$c0), $ovf1), + (ConstantLikeMatcher APIntAttr:$c1), $ovf2), + (Arith_AddIOp $x, (Arith_ConstantOp (SubIntAttrs $res, $c1, $c0)), + (DefOverflow))>; // addi(subi(c0, x), c1) -> subi(c0 + c1, x) def AddISubConstantLHS : Pat<(Arith_AddIOp:$res - (Arith_SubIOp (ConstantLikeMatcher APIntAttr:$c0), $x), - (ConstantLikeMatcher APIntAttr:$c1)), - (Arith_SubIOp (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)), $x)>; + (Arith_SubIOp (ConstantLikeMatcher APIntAttr:$c0), $x, $ovf1), + (ConstantLikeMatcher APIntAttr:$c1), $ovf2), + (Arith_SubIOp (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)), $x, + (DefOverflow))>; def IsScalarOrSplatNegativeOne : Constraint; // addi(muli(x, -1), y) -> subi(y, x) def AddIMulNegativeOneLhs : Pat<(Arith_AddIOp - (Arith_MulIOp $x, (ConstantLikeMatcher AnyAttr:$c0)), - $y), - (Arith_SubIOp $y, $x), + (Arith_MulIOp $x, (ConstantLikeMatcher AnyAttr:$c0), $ovf1), + $y, $ovf2), + (Arith_SubIOp $y, $x, (DefOverflow)), [(IsScalarOrSplatNegativeOne $c0)]>; // muli(muli(x, c0), c1) -> muli(x, c0 * c1) def MulIMulIConstant : Pat<(Arith_MulIOp:$res - (Arith_MulIOp $x, (ConstantLikeMatcher APIntAttr:$c0)), - (ConstantLikeMatcher APIntAttr:$c1)), - (Arith_MulIOp $x, (Arith_ConstantOp (MulIntAttrs $res, $c0, $c1)))>; + (Arith_MulIOp $x, (ConstantLikeMatcher APIntAttr:$c0), $ovf1), + (ConstantLikeMatcher APIntAttr:$c1), $ovf2), + (Arith_MulIOp $x, (Arith_ConstantOp (MulIntAttrs $res, $c0, $c1)), + (DefOverflow))>; //===----------------------------------------------------------------------===// // AddUIExtendedOp @@ -90,7 +100,7 @@ def MulIMulIConstant : // uses. Since the 'overflow' result is unused, any replacement value will do. def AddUIExtendedToAddI: Pattern<(Arith_AddUIExtendedOp:$res $x, $y), - [(Arith_AddIOp $x, $y), (replaceWithValue $x)], + [(Arith_AddIOp $x, $y, (DefOverflow)), (replaceWithValue $x)], [(Constraint> $res__1)]>; //===----------------------------------------------------------------------===// @@ -100,49 +110,55 @@ def AddUIExtendedToAddI: // subi(addi(x, c0), c1) -> addi(x, c0 - c1) def SubIRHSAddConstant : Pat<(Arith_SubIOp:$res - (Arith_AddIOp $x, (ConstantLikeMatcher APIntAttr:$c0)), - (ConstantLikeMatcher APIntAttr:$c1)), - (Arith_AddIOp $x, (Arith_ConstantOp (SubIntAttrs $res, $c0, $c1)))>; + (Arith_AddIOp $x, (ConstantLikeMatcher APIntAttr:$c0), $ovf1), + (ConstantLikeMatcher APIntAttr:$c1), $ovf2), + (Arith_AddIOp $x, (Arith_ConstantOp (SubIntAttrs $res, $c0, $c1)), + (DefOverflow))>; // subi(c1, addi(x, c0)) -> subi(c1 - c0, x) def SubILHSAddConstant : Pat<(Arith_SubIOp:$res (ConstantLikeMatcher APIntAttr:$c1), - (Arith_AddIOp $x, (ConstantLikeMatcher APIntAttr:$c0))), - (Arith_SubIOp (Arith_ConstantOp (SubIntAttrs $res, $c1, $c0)), $x)>; + (Arith_AddIOp $x, (ConstantLikeMatcher APIntAttr:$c0), $ovf1), $ovf2), + (Arith_SubIOp (Arith_ConstantOp (SubIntAttrs $res, $c1, $c0)), $x, + (DefOverflow))>; // subi(subi(x, c0), c1) -> subi(x, c0 + c1) def SubIRHSSubConstantRHS : Pat<(Arith_SubIOp:$res - (Arith_SubIOp $x, (ConstantLikeMatcher APIntAttr:$c0)), - (ConstantLikeMatcher APIntAttr:$c1)), - (Arith_SubIOp $x, (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)))>; + (Arith_SubIOp $x, (ConstantLikeMatcher APIntAttr:$c0), $ovf1), + (ConstantLikeMatcher APIntAttr:$c1), $ovf2), + (Arith_SubIOp $x, (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)), + (DefOverflow))>; // subi(subi(c0, x), c1) -> subi(c0 - c1, x) def SubIRHSSubConstantLHS : Pat<(Arith_SubIOp:$res - (Arith_SubIOp (ConstantLikeMatcher APIntAttr:$c0), $x), - (ConstantLikeMatcher APIntAttr:$c1)), - (Arith_SubIOp (Arith_ConstantOp (SubIntAttrs $res, $c0, $c1)), $x)>; + (Arith_SubIOp (ConstantLikeMatcher APIntAttr:$c0), $x, $ovf1), + (ConstantLikeMatcher APIntAttr:$c1), $ovf2), + (Arith_SubIOp (Arith_ConstantOp (SubIntAttrs $res, $c0, $c1)), $x, + (DefOverflow))>; // subi(c1, subi(x, c0)) -> subi(c0 + c1, x) def SubILHSSubConstantRHS : Pat<(Arith_SubIOp:$res (ConstantLikeMatcher APIntAttr:$c1), - (Arith_SubIOp $x, (ConstantLikeMatcher APIntAttr:$c0))), - (Arith_SubIOp (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)), $x)>; + (Arith_SubIOp $x, (ConstantLikeMatcher APIntAttr:$c0), $ovf1), $ovf2), + (Arith_SubIOp (Arith_ConstantOp (AddIntAttrs $res, $c0, $c1)), $x, + (DefOverflow))>; // subi(c1, subi(c0, x)) -> addi(x, c1 - c0) def SubILHSSubConstantLHS : Pat<(Arith_SubIOp:$res (ConstantLikeMatcher APIntAttr:$c1), - (Arith_SubIOp (ConstantLikeMatcher APIntAttr:$c0), $x)), - (Arith_AddIOp $x, (Arith_ConstantOp (SubIntAttrs $res, $c1, $c0)))>; + (Arith_SubIOp (ConstantLikeMatcher APIntAttr:$c0), $x, $ovf1), $ovf2), + (Arith_AddIOp $x, (Arith_ConstantOp (SubIntAttrs $res, $c1, $c0)), + (DefOverflow))>; // subi(subi(a, b), a) -> subi(0, b) def SubISubILHSRHSLHS : - Pat<(Arith_SubIOp:$res (Arith_SubIOp $x, $y), $x), - (Arith_SubIOp (Arith_ConstantOp (GetZeroAttr $y)), $y)>; + Pat<(Arith_SubIOp:$res (Arith_SubIOp $x, $y, $ovf1), $x, $ovf2), + (Arith_SubIOp (Arith_ConstantOp (GetZeroAttr $y)), $y, (DefOverflow))>; //===----------------------------------------------------------------------===// // MulSIExtendedOp @@ -152,7 +168,7 @@ def SubISubILHSRHSLHS : // Since the `high` result it not used, any replacement value will do. def MulSIExtendedToMulI : Pattern<(Arith_MulSIExtendedOp:$res $x, $y), - [(Arith_MulIOp $x, $y), (replaceWithValue $x)], + [(Arith_MulIOp $x, $y, (DefOverflow)), (replaceWithValue $x)], [(Constraint> $res__1)]>; @@ -179,7 +195,7 @@ def MulSIExtendedRHSOne : // Since the `high` result it not used, any replacement value will do. def MulUIExtendedToMulI : Pattern<(Arith_MulUIExtendedOp:$res $x, $y), - [(Arith_MulIOp $x, $y), (replaceWithValue $x)], + [(Arith_MulIOp $x, $y, (DefOverflow)), (replaceWithValue $x)], [(Constraint> $res__1)]>; //===----------------------------------------------------------------------===// @@ -403,7 +419,7 @@ def TruncIShrSIToTrunciShrUI : def TruncIShrUIMulIToMulSIExtended : Pat<(Arith_TruncIOp:$tr (Arith_ShRUIOp (Arith_MulIOp:$mul - (Arith_ExtSIOp $x), (Arith_ExtSIOp $y)), + (Arith_ExtSIOp $x), (Arith_ExtSIOp $y), $ovf1), (ConstantLikeMatcher AnyAttr:$c0))), (Arith_MulSIExtendedOp:$res__1 $x, $y), [(ValuesWithSameType $tr, $x, $y), @@ -414,7 +430,7 @@ def TruncIShrUIMulIToMulSIExtended : def TruncIShrUIMulIToMulUIExtended : Pat<(Arith_TruncIOp:$tr (Arith_ShRUIOp (Arith_MulIOp:$mul - (Arith_ExtUIOp $x), (Arith_ExtUIOp $y)), + (Arith_ExtUIOp $x), (Arith_ExtUIOp $y), $ovf1), (ConstantLikeMatcher AnyAttr:$c0))), (Arith_MulUIExtendedOp:$res__1 $x, $y), [(ValuesWithSameType $tr, $x, $y), diff --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp index ff72becc8dfa..2d124ce4980f 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp +++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp @@ -61,6 +61,11 @@ static IntegerAttr mulIntegerAttrs(PatternRewriter &builder, Value res, return applyToIntegerAttrs(builder, res, lhs, rhs, std::multiplies()); } +static IntegerOverflowFlagsAttr getDefOverflowFlags(OpBuilder &builder) { + return IntegerOverflowFlagsAttr::get(builder.getContext(), + IntegerOverflowFlags::none); +} + /// Invert an integer comparison predicate. arith::CmpIPredicate arith::invertPredicate(arith::CmpIPredicate pred) { switch (pred) { diff --git a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir index e16dbb566105..8937b24e0d17 100644 --- a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir +++ b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir @@ -575,3 +575,16 @@ func.func @ops_supporting_fastmath(%arg0: f32, %arg1: f32, %arg2: i32) { %7 = arith.subf %arg0, %arg1 fastmath : f32 return } + +// ----- + +// CHECK-LABEL: @ops_supporting_overflow +func.func @ops_supporting_overflow(%arg0: i64, %arg1: i64) { + // CHECK: %{{.*}} = llvm.add %{{.*}}, %{{.*}} overflow : i64 + %0 = arith.addi %arg0, %arg1 overflow : i64 + // CHECK: %{{.*}} = llvm.sub %{{.*}}, %{{.*}} overflow : i64 + %1 = arith.subi %arg0, %arg1 overflow : i64 + // CHECK: %{{.*}} = llvm.mul %{{.*}}, %{{.*}} overflow : i64 + %2 = arith.muli %arg0, %arg1 overflow : i64 + return +} diff --git a/mlir/test/Dialect/Arith/ops.mlir b/mlir/test/Dialect/Arith/ops.mlir index 6e10e540d1d1..8ae3273f32c6 100644 --- a/mlir/test/Dialect/Arith/ops.mlir +++ b/mlir/test/Dialect/Arith/ops.mlir @@ -1138,3 +1138,14 @@ func.func @select_tensor_encoding( %0 = arith.select %arg0, %arg1, %arg2 : tensor<8xi1, "foo">, tensor<8xi32, "foo"> return %0 : tensor<8xi32, "foo"> } + +// CHECK-LABEL: @intflags_func +func.func @intflags_func(%arg0: i64, %arg1: i64) { + // CHECK: %{{.*}} = arith.addi %{{.*}}, %{{.*}} overflow : i64 + %0 = arith.addi %arg0, %arg1 overflow : i64 + // CHECK: %{{.*}} = arith.subi %{{.*}}, %{{.*}} overflow : i64 + %1 = arith.subi %arg0, %arg1 overflow : i64 + // CHECK: %{{.*}} = arith.muli %{{.*}}, %{{.*}} overflow : i64 + %2 = arith.muli %arg0, %arg1 overflow : i64 + return +} diff --git a/mlir/test/python/ir/diagnostic_handler.py b/mlir/test/python/ir/diagnostic_handler.py index 2f4300d2c55d..d516cda81989 100644 --- a/mlir/test/python/ir/diagnostic_handler.py +++ b/mlir/test/python/ir/diagnostic_handler.py @@ -113,7 +113,7 @@ def testDiagnosticNonEmptyNotes(): def callback(d): # CHECK: DIAGNOSTIC: # CHECK: message='arith.addi' op requires one result - # CHECK: notes=['see current operation: "arith.addi"() : () -> ()'] + # CHECK: notes=['see current operation: "arith.addi"() {{.*}} : () -> ()'] print(f"DIAGNOSTIC:") print(f" message={d.message}") print(f" notes={list(map(str, d.notes))}") -- GitLab From b932f03bda5a88f699d33d118ca2735da3c66677 Mon Sep 17 00:00:00 2001 From: michaelrj-google <71531609+michaelrj-google@users.noreply.github.com> Date: Tue, 9 Jan 2024 15:04:22 -0800 Subject: [PATCH 270/652] [libc] Disable Death Tests While Hermetic (#77388) The death test infrastructure seems to depend on operator new, which isn't currently supported in our hermetic tests. This patch just disables the death tests in hermetic mode since they only overlap in the nan tests. --- libc/test/UnitTest/HermeticTestUtils.cpp | 4 ++++ libc/test/src/math/smoke/CMakeLists.txt | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/libc/test/UnitTest/HermeticTestUtils.cpp b/libc/test/UnitTest/HermeticTestUtils.cpp index 73d54b9eeb5e..68e31f478d79 100644 --- a/libc/test/UnitTest/HermeticTestUtils.cpp +++ b/libc/test/UnitTest/HermeticTestUtils.cpp @@ -104,6 +104,10 @@ void *__dso_handle = nullptr; } // extern "C" +void *operator new(size_t size) { return malloc(size); } + +void *operator new[](size_t size) { return malloc(size); } + void operator delete(void *) { // The libc runtime should not use the global delete operator. Hence, // we just trap here to catch any such accidental usages. diff --git a/libc/test/src/math/smoke/CMakeLists.txt b/libc/test/src/math/smoke/CMakeLists.txt index 65dc80c2a882..87b72e2a8eca 100644 --- a/libc/test/src/math/smoke/CMakeLists.txt +++ b/libc/test/src/math/smoke/CMakeLists.txt @@ -1214,6 +1214,9 @@ add_fp_unittest( libc.include.signal libc.src.math.nanf libc.src.__support.FPUtil.fp_bits + # FIXME: The nan tests currently have death tests, which aren't supported for + # hermetic tests. + UNIT_TEST_ONLY ) add_fp_unittest( @@ -1227,6 +1230,9 @@ add_fp_unittest( libc.include.signal libc.src.math.nan libc.src.__support.FPUtil.fp_bits + # FIXME: The nan tests currently have death tests, which aren't supported for + # hermetic tests. + UNIT_TEST_ONLY ) add_fp_unittest( @@ -1240,6 +1246,9 @@ add_fp_unittest( libc.include.signal libc.src.math.nanl libc.src.__support.FPUtil.fp_bits + # FIXME: The nan tests currently have death tests, which aren't supported for + # hermetic tests. + UNIT_TEST_ONLY ) # FIXME: These tests are currently spurious for NVPTX. -- GitLab From 5f71aa9270c3d680babfbc6e766773d113c2a79a Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Tue, 9 Jan 2024 15:20:06 -0800 Subject: [PATCH 271/652] [lldb] [Mach-O] don't strip the end of the "kern ver str" LC_NOTE (#77538) The "kern ver str" LC_NOTE gives lldb a kernel version string -- with a UUID and/or a load address (stext) to load it at. The LC_NOTE specifies a size of the identifier string in bytes. In ObjectFileMachO::GetIdentifierString, I copy that number of bytes into a std::string, and in case there were additional nul characters at the end of the sting for padding reasons, I tried to shrink the std::string to not include these extra nul's. However, I did this resizing without handling the case of an empty identifier string. I don't know why any corefile creator would do that, but of course at least one does. This patch removes the resizing altogether; I was solving something that hasn't ever shown to be a problem. I also added a test case for this, to check that lldb doesn't crash when given one of these corefiles. rdar://120390199 --- .../ObjectFile/Mach-O/ObjectFileMachO.cpp | 4 --- .../TestFirmwareCorefiles.py | 24 +++++++++++++++++- .../create-empty-corefile.cpp | 25 +++++++++++++------ 3 files changed, 40 insertions(+), 13 deletions(-) diff --git a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp index 182a9f2afaeb..d7a2846200fc 100644 --- a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp +++ b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp @@ -5467,8 +5467,6 @@ std::string ObjectFileMachO::GetIdentifierString() { uint32_t strsize = payload_size - sizeof(uint32_t); std::string result(strsize, '\0'); m_data.CopyData(payload_offset, strsize, result.data()); - while (result.back() == '\0') - result.resize(result.size() - 1); LLDB_LOGF(log, "LC_NOTE 'kern ver str' found with text '%s'", result.c_str()); return result; @@ -5488,8 +5486,6 @@ std::string ObjectFileMachO::GetIdentifierString() { std::string result(ident_command.cmdsize, '\0'); if (m_data.CopyData(offset, ident_command.cmdsize, result.data()) == ident_command.cmdsize) { - while (result.back() == '\0') - result.resize(result.size() - 1); LLDB_LOGF(log, "LC_IDENT found with text '%s'", result.c_str()); return result; } diff --git a/lldb/test/API/macosx/lc-note/firmware-corefile/TestFirmwareCorefiles.py b/lldb/test/API/macosx/lc-note/firmware-corefile/TestFirmwareCorefiles.py index 9fd12c3ba49c..b9d2055e83a5 100644 --- a/lldb/test/API/macosx/lc-note/firmware-corefile/TestFirmwareCorefiles.py +++ b/lldb/test/API/macosx/lc-note/firmware-corefile/TestFirmwareCorefiles.py @@ -24,6 +24,9 @@ class TestFirmwareCorefiles(TestBase): aout_exe_basename = "a.out" aout_exe = self.getBuildArtifact(aout_exe_basename) verstr_corefile = self.getBuildArtifact("verstr.core") + verstr_corefile_invalid_ident = self.getBuildArtifact( + "verstr-invalid-ident.core" + ) verstr_corefile_addr = self.getBuildArtifact("verstr-addr.core") create_corefile = self.getBuildArtifact("create-empty-corefile") slide = 0x70000000000 @@ -36,6 +39,14 @@ class TestFirmwareCorefiles(TestBase): + " 0xffffffffffffffff 0xffffffffffffffff", shell=True, ) + call( + create_corefile + + " version-string " + + verstr_corefile_invalid_ident + + ' "" ' + + "0xffffffffffffffff 0xffffffffffffffff", + shell=True, + ) call( create_corefile + " version-string " @@ -71,7 +82,18 @@ class TestFirmwareCorefiles(TestBase): self.assertEqual(fspec.GetFilename(), aout_exe_basename) self.dbg.DeleteTarget(target) - # Second, try the "kern ver str" corefile where it loads at an address + # Second, try the "kern ver str" corefile which has an invalid ident, + # make sure we don't crash. + target = self.dbg.CreateTarget("") + err = lldb.SBError() + if self.TraceOn(): + self.runCmd( + "script print('loading corefile %s')" % verstr_corefile_invalid_ident + ) + process = target.LoadCore(verstr_corefile_invalid_ident) + self.assertEqual(process.IsValid(), True) + + # Third, try the "kern ver str" corefile where it loads at an address target = self.dbg.CreateTarget("") err = lldb.SBError() if self.TraceOn(): diff --git a/lldb/test/API/macosx/lc-note/firmware-corefile/create-empty-corefile.cpp b/lldb/test/API/macosx/lc-note/firmware-corefile/create-empty-corefile.cpp index 8bd6aaabecd6..d7c2d422412e 100644 --- a/lldb/test/API/macosx/lc-note/firmware-corefile/create-empty-corefile.cpp +++ b/lldb/test/API/macosx/lc-note/firmware-corefile/create-empty-corefile.cpp @@ -86,14 +86,16 @@ std::vector lc_thread_load_command(cpu_type_t cputype) { void add_lc_note_kern_ver_str_load_command( std::vector> &loadcmds, std::vector &payload, int payload_file_offset, std::string uuid, uint64_t address) { - std::string ident = "EFI UUID="; - ident += uuid; - - if (address != 0xffffffffffffffff) { - ident += "; stext="; - char buf[24]; - sprintf(buf, "0x%" PRIx64, address); - ident += buf; + std::string ident; + if (!uuid.empty()) { + ident = "EFI UUID="; + ident += uuid; + if (address != 0xffffffffffffffff) { + ident += "; stext="; + char buf[24]; + sprintf(buf, "0x%" PRIx64, address); + ident += buf; + } } std::vector loadcmd_data; @@ -187,6 +189,9 @@ void add_lc_segment(std::vector> &loadcmds, std::string get_uuid_from_binary(const char *fn, cpu_type_t &cputype, cpu_subtype_t &cpusubtype) { + if (strlen(fn) == 0) + return {}; + FILE *f = fopen(fn, "r"); if (f == nullptr) { fprintf(stderr, "Unable to open binary '%s' to get uuid\n", fn); @@ -295,6 +300,10 @@ int main(int argc, char **argv) { fprintf(stderr, "an LC_NOTE 'main bin spec' load command without an " "address specified, depending on\n"); fprintf(stderr, "whether the 1st arg is version-string or main-bin-spec\n"); + fprintf(stderr, "\nan LC_NOTE 'kern ver str' with no binary provided " + "(empty string filename) to get a UUID\n"); + fprintf(stderr, "means an empty 'kern ver str' will be written, an invalid " + "LC_NOTE that lldb should handle.\n"); exit(1); } if (strcmp(argv[1], "version-string") != 0 && -- GitLab From feb49bb42433c55a206489d4c8dafd940c019e30 Mon Sep 17 00:00:00 2001 From: Nour1248 <121687016+Nour1248@users.noreply.github.com> Date: Wed, 10 Jan 2024 01:58:38 +0200 Subject: [PATCH 272/652] [clangd] Fix typo in function name in AST.cpp (#77504) --- clang-tools-extra/clangd/AST.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/clang-tools-extra/clangd/AST.cpp b/clang-tools-extra/clangd/AST.cpp index ae79eb21de94..3e374cf2a897 100644 --- a/clang-tools-extra/clangd/AST.cpp +++ b/clang-tools-extra/clangd/AST.cpp @@ -757,7 +757,7 @@ const TemplateTypeParmType *getFunctionPackType(const FunctionDecl *Callee) { // Returns the template parameter pack type that this parameter was expanded // from (if in the Args... or Args&... or Args&&... form), if this is the case, // nullptr otherwise. -const TemplateTypeParmType *getUnderylingPackType(const ParmVarDecl *Param) { +const TemplateTypeParmType *getUnderlyingPackType(const ParmVarDecl *Param) { const auto *PlainType = Param->getType().getTypePtr(); if (auto *RT = dyn_cast(PlainType)) PlainType = RT->getPointeeTypeAsWritten().getTypePtr(); @@ -793,8 +793,8 @@ class ForwardingCallVisitor : public RecursiveASTVisitor { public: ForwardingCallVisitor(ArrayRef Parameters) - : Parameters{Parameters}, PackType{getUnderylingPackType( - Parameters.front())} {} + : Parameters{Parameters}, + PackType{getUnderlyingPackType(Parameters.front())} {} bool VisitCallExpr(CallExpr *E) { auto *Callee = getCalleeDeclOrUniqueOverload(E); @@ -859,7 +859,7 @@ private: if (const auto *TTPT = getFunctionPackType(Callee)) { // In this case: Separate the parameters into head, pack and tail auto IsExpandedPack = [&](const ParmVarDecl *P) { - return getUnderylingPackType(P) == TTPT; + return getUnderlyingPackType(P) == TTPT; }; ForwardingInfo FI; FI.Head = MatchingParams.take_until(IsExpandedPack); @@ -964,7 +964,7 @@ resolveForwardingParameters(const FunctionDecl *D, unsigned MaxDepth) { if (const auto *TTPT = getFunctionPackType(D)) { // Split the parameters into head, pack and tail auto IsExpandedPack = [TTPT](const ParmVarDecl *P) { - return getUnderylingPackType(P) == TTPT; + return getUnderlyingPackType(P) == TTPT; }; ArrayRef Head = Parameters.take_until(IsExpandedPack); ArrayRef Pack = @@ -1016,7 +1016,7 @@ resolveForwardingParameters(const FunctionDecl *D, unsigned MaxDepth) { } bool isExpandedFromParameterPack(const ParmVarDecl *D) { - return getUnderylingPackType(D) != nullptr; + return getUnderlyingPackType(D) != nullptr; } } // namespace clangd -- GitLab From 046dffce237f193a50a46c3f5bd8a8ca2efc3c77 Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Wed, 10 Jan 2024 07:58:27 +0800 Subject: [PATCH 273/652] Fix -Wunused-variable in TestSimplifications.cpp (NFC) llvm-project/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp:36:17: error: unused variable 'status' [-Werror,-Wunused-variable] LogicalResult status = ^ 1 error generated. --- mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp b/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp index 12a5fd532c4c..cd22530d51a7 100644 --- a/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp +++ b/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp @@ -33,7 +33,7 @@ void TestMeshSimplificationsPass::runOnOperation() { RewritePatternSet patterns(&getContext()); SymbolTableCollection symbolTableCollection; mesh::populateSimplificationPatterns(patterns, symbolTableCollection); - LogicalResult status = + [[maybe_unused]] LogicalResult status = applyPatternsAndFoldGreedily(getOperation(), std::move(patterns)); assert(succeeded(status) && "Rewrite patters application did not converge."); } -- GitLab From ab82b0624015d910455b5844cb0ad3d2a4d38732 Mon Sep 17 00:00:00 2001 From: Chris Apple <14171107+cjappl@users.noreply.github.com> Date: Tue, 9 Jan 2024 16:29:04 -0800 Subject: [PATCH 274/652] Make SANITIZER_MIN_OSX_VERSION a cache variable (#74394) It is desirable to be able to configure the `-mmacosx-version-min` flag for the sanitizers, but this flag was never made a CACHE variable in cmake. By doing this, it will allow developers to select different minimum versions, which results in different interceptors being enabled or disabled on their platforms. This version can now persist between cmake runs, so it can be remembered by cmake, and edited in the cache file. --- compiler-rt/cmake/config-ix.cmake | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/compiler-rt/cmake/config-ix.cmake b/compiler-rt/cmake/config-ix.cmake index 2dccd4954b25..142ab60f7152 100644 --- a/compiler-rt/cmake/config-ix.cmake +++ b/compiler-rt/cmake/config-ix.cmake @@ -461,29 +461,34 @@ if(APPLE) set(ORC_SUPPORTED_OS osx) endif() - # Note: In order to target x86_64h on OS X the minimum deployment target must - # be 10.8 or higher. set(DEFAULT_SANITIZER_MIN_OSX_VERSION 10.10) set(DARWIN_osx_MIN_VER_FLAG "-mmacosx-version-min") if(NOT SANITIZER_MIN_OSX_VERSION) string(REGEX MATCH "${DARWIN_osx_MIN_VER_FLAG}=([.0-9]+)" MACOSX_VERSION_MIN_FLAG "${CMAKE_CXX_FLAGS}") if(MACOSX_VERSION_MIN_FLAG) - set(SANITIZER_MIN_OSX_VERSION "${CMAKE_MATCH_1}") + set(MIN_OSX_VERSION "${CMAKE_MATCH_1}") elseif(CMAKE_OSX_DEPLOYMENT_TARGET) - set(SANITIZER_MIN_OSX_VERSION ${CMAKE_OSX_DEPLOYMENT_TARGET}) + set(MIN_OSX_VERSION ${CMAKE_OSX_DEPLOYMENT_TARGET}) else() - set(SANITIZER_MIN_OSX_VERSION ${DEFAULT_SANITIZER_MIN_OSX_VERSION}) + set(MIN_OSX_VERSION ${DEFAULT_SANITIZER_MIN_OSX_VERSION}) endif() - if(SANITIZER_MIN_OSX_VERSION VERSION_LESS "10.7") + + # Note: In order to target x86_64h on OS X the minimum deployment target must + # be 10.8 or higher. + if(MIN_OSX_VERSION VERSION_LESS "10.7") message(FATAL_ERROR "macOS deployment target '${SANITIZER_MIN_OSX_VERSION}' is too old.") endif() - if(SANITIZER_MIN_OSX_VERSION VERSION_GREATER ${DEFAULT_SANITIZER_MIN_OSX_VERSION}) + if(MIN_OSX_VERSION VERSION_GREATER ${DEFAULT_SANITIZER_MIN_OSX_VERSION}) message(WARNING "macOS deployment target '${SANITIZER_MIN_OSX_VERSION}' is too new, setting to '${DEFAULT_SANITIZER_MIN_OSX_VERSION}' instead.") - set(SANITIZER_MIN_OSX_VERSION ${DEFAULT_SANITIZER_MIN_OSX_VERSION}) + set(MIN_OSX_VERSION ${DEFAULT_SANITIZER_MIN_OSX_VERSION}) endif() + endif() + set(SANITIZER_MIN_OSX_VERSION "${MIN_OSX_VERSION}" CACHE STRING + "Minimum OS X version to target (e.g. 10.10) for sanitizers.") + # We're setting the flag manually for each target OS set(CMAKE_OSX_DEPLOYMENT_TARGET "") -- GitLab From 412d784188257f6b8a3748ac9a800002db861181 Mon Sep 17 00:00:00 2001 From: Yinying Li <107574043+yinying-lisa-li@users.noreply.github.com> Date: Tue, 9 Jan 2024 19:46:35 -0500 Subject: [PATCH 275/652] [mlir][sparse][CRunnerUtils] Add shuffle in CRunnerUtils (#77124) Shuffle can generate an array of unique and random numbers from 0 to size-1. It can be used to generate tensors with specified sparsity level. --- .../mlir/ExecutionEngine/CRunnerUtils.h | 12 ++- mlir/lib/ExecutionEngine/CRunnerUtils.cpp | 12 +++ .../SparseTensor/CPU/sparse_generate.mlir | 95 +++++++++++++++++++ 3 files changed, 116 insertions(+), 3 deletions(-) create mode 100644 mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir diff --git a/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h b/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h index 76b04145b482..812f719e723e 100644 --- a/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h +++ b/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h @@ -482,10 +482,16 @@ extern "C" MLIR_CRUNNERUTILS_EXPORT double rtclock(); //===----------------------------------------------------------------------===// // Uses a seed to initialize a random generator and returns the generator. extern "C" MLIR_CRUNNERUTILS_EXPORT void *rtsrand(uint64_t s); -// Returns a random number in the range of [0, m). -extern "C" MLIR_CRUNNERUTILS_EXPORT uint64_t rtrand(void *, uint64_t m); +// Uses a random number generator g and returns a random number +// in the range of [0, m). +extern "C" MLIR_CRUNNERUTILS_EXPORT uint64_t rtrand(void *g, uint64_t m); // Deletes the random number generator. -extern "C" MLIR_CRUNNERUTILS_EXPORT void rtdrand(void *); +extern "C" MLIR_CRUNNERUTILS_EXPORT void rtdrand(void *g); +// Uses a random number generator g and std::shuffle to modify mref +// in place. Memref mref will be a permutation of all numbers +// in the range of [0, size of mref). +extern "C" MLIR_CRUNNERUTILS_EXPORT void +_mlir_ciface_shuffle(StridedMemRefType *mref, void *g); //===----------------------------------------------------------------------===// // Runtime support library to allow the use of std::sort in MLIR program. diff --git a/mlir/lib/ExecutionEngine/CRunnerUtils.cpp b/mlir/lib/ExecutionEngine/CRunnerUtils.cpp index e28e75eb1103..48e4b8cd88b5 100644 --- a/mlir/lib/ExecutionEngine/CRunnerUtils.cpp +++ b/mlir/lib/ExecutionEngine/CRunnerUtils.cpp @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -176,6 +177,17 @@ extern "C" void rtdrand(void *g) { delete generator; } +extern "C" void _mlir_ciface_shuffle(StridedMemRefType *mref, + void *g) { + assert(mref); + assert(mref->strides[0] == 1); // consecutive + std::mt19937 *generator = static_cast(g); + uint64_t s = mref->sizes[0]; + uint64_t *data = mref->data + mref->offset; + std::iota(data, data + s, 0); + std::shuffle(data, data + s, *generator); +} + #define IMPL_STDSORT(VNAME, V) \ extern "C" void _mlir_ciface_stdSort##VNAME(uint64_t n, \ StridedMemRefType *vref) { \ diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir new file mode 100644 index 000000000000..fcc16f5e9cb4 --- /dev/null +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir @@ -0,0 +1,95 @@ +//-------------------------------------------------------------------------------------------------- +// WHEN CREATING A NEW TEST, PLEASE JUST COPY & PASTE WITHOUT EDITS. +// +// Set-up that's shared across all tests in this directory. In principle, this +// config could be moved to lit.local.cfg. However, there are downstream users that +// do not use these LIT config files. Hence why this is kept inline. +// +// DEFINE: %{sparsifier_opts} = enable-runtime-library=true +// DEFINE: %{sparsifier_opts_sve} = enable-arm-sve=true %{sparsifier_opts} +// DEFINE: %{compile} = mlir-opt %s --sparsifier="%{sparsifier_opts}" +// DEFINE: %{compile_sve} = mlir-opt %s --sparsifier="%{sparsifier_opts_sve}" +// DEFINE: %{run_libs} = -shared-libs=%mlir_c_runner_utils,%mlir_runner_utils +// DEFINE: %{run_opts} = -e entry -entry-point-result=void +// DEFINE: %{run} = mlir-cpu-runner %{run_opts} %{run_libs} +// DEFINE: %{run_sve} = %mcr_aarch64_cmd --march=aarch64 --mattr="+sve" %{run_opts} %{run_libs} +// +// DEFINE: %{env} = +//-------------------------------------------------------------------------------------------------- + +// RUN: %{compile} | %{run} | FileCheck %s + +// +// Integration test that generates a tensor with specified sparsity level. +// + +!Generator = !llvm.ptr +!Array = !llvm.ptr + +#SparseVector = #sparse_tensor.encoding<{ + map = (d0) -> (d0 : compressed) +}> + +module { + func.func private @rtsrand(index) -> (!Generator) + func.func private @rtrand(!Generator, index) -> (index) + func.func private @rtdrand(!Generator) -> () + func.func private @shuffle(memref, !Generator) -> () attributes { llvm.emit_c_interface } + + // + // Main driver. + // + func.func @entry() { + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %f0 = arith.constant 0.0 : f64 + %c99 = arith.constant 99 : index + %c100 = arith.constant 100 : index + + // Set up input size and sparsity level. + %size = arith.constant 50 : index + %sparsity = arith.constant 90 : index + %zeros = arith.muli %size, %sparsity : index + %nz = arith.floordivsi %zeros, %c100 : index + %nse = arith.subi %size, %nz : index + + // Set up an empty vector. + %empty = tensor.empty(%size) : tensor + %zero_vec = linalg.fill ins(%f0 : f64) outs(%empty : tensor) -> tensor + + // Generate shuffled indices in the range of [0, %size). + %array = memref.alloc (%size) : memref + %g = func.call @rtsrand(%c0) : (index) ->(!Generator) + func.call @shuffle(%array, %g) : (memref, !Generator) -> () + + // Iterate through the number of nse indices to insert values. + %output = scf.for %iv = %c0 to %nse step %c1 iter_args(%iter = %zero_vec) -> tensor { + // Fetch the index to insert value from shuffled index array. + %val = memref.load %array[%iv] : memref + %idx = arith.index_cast %val : i64 to index + // Generate a random number from 1 to 100. + %ri0 = func.call @rtrand(%g, %c99) : (!Generator, index) -> (index) + %ri1 = arith.addi %ri0, %c1 : index + %r0 = arith.index_cast %ri1 : index to i64 + %fr = arith.uitofp %r0 : i64 to f64 + // Insert the random number to current index. + %out = tensor.insert %fr into %iter[%idx] : tensor + scf.yield %out : tensor + } + + %sv = sparse_tensor.convert %output : tensor to tensor + %n0 = sparse_tensor.number_of_entries %sv : tensor + + // Print the number of non-zeros for verification. + // + // CHECK: 5 + vector.print %n0 : index + + // Release the resources. + bufferization.dealloc_tensor %sv : tensor + memref.dealloc %array : memref + func.call @rtdrand(%g) : (!Generator) -> () + + return + } +} -- GitLab From 46944210ebd93765b068eeba22bd3e337099af3e Mon Sep 17 00:00:00 2001 From: Ding Fei Date: Wed, 10 Jan 2024 08:49:36 +0800 Subject: [PATCH 276/652] [clang][Parser] Pop scope prior VarDecl invalidating by invalid init (#77434) Invalid (direct) initializer would invalid `VarDecl` so `InitializerScopeRAII` cannot restore scope stack balance. As with other kind of initializer, `InitializerScopeRAII::pop()` is moved up before `Sema::ActOnInitializerError()` which invalidates the `VarDecl`, so scope can be balanced and current `DeclContext` can be restored. Fixes #30908 --- clang/docs/ReleaseNotes.rst | 3 +++ clang/lib/Parse/ParseDecl.cpp | 8 +++++-- ...e-balance-on-invalid-var-direct-init-1.cpp | 20 +++++++++++++++++ ...e-balance-on-invalid-var-direct-init-2.cpp | 22 +++++++++++++++++++ 4 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-1.cpp create mode 100644 clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-2.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index ddeb1186d65a..46f4b82b89e4 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -702,6 +702,9 @@ Bug Fixes in This Version - Fix assertion failure when initializing union containing struct with flexible array member using empty initializer list. Fixes (`#77085 `_) +- Fix assertion crash due to failed scope restoring caused by too-early VarDecl + invalidation by invalid initializer Expr. + Fixes (`#30908 `_) Bug Fixes to Compiler Builtins diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index b60ae293ef8c..ed684c5d57b1 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -2661,7 +2661,12 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes( // ProduceConstructorSignatureHelp only on VarDecls. ExpressionStarts = SetPreferredType; } - if (ParseExpressionList(Exprs, ExpressionStarts)) { + + bool SawError = ParseExpressionList(Exprs, ExpressionStarts); + + InitScope.pop(); + + if (SawError) { if (ThisVarDecl && PP.isCodeCompletionReached() && !CalledSignatureHelp) { Actions.ProduceConstructorSignatureHelp( ThisVarDecl->getType()->getCanonicalTypeInternal(), @@ -2674,7 +2679,6 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes( } else { // Match the ')'. T.consumeClose(); - InitScope.pop(); ExprResult Initializer = Actions.ActOnParenListExpr(T.getOpenLocation(), T.getCloseLocation(), diff --git a/clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-1.cpp b/clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-1.cpp new file mode 100644 index 000000000000..1a692fe8ff1e --- /dev/null +++ b/clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-1.cpp @@ -0,0 +1,20 @@ +// RUN: %clang_cc1 -ferror-limit 2 -fsyntax-only -verify %s + +// expected-error@* {{too many errors emitted}} + +namespace llvm { +namespace Hexagon {} +} +void set() { + Hexagon::NoRegister; + // expected-error@-1 {{use of undeclared identifier}} + // expected-note@-5 {{declared here}} + // expected-error@-3 {{no member named 'NoRegister' in namespace}} +} +template struct pair { pair(int, int); }; +struct HexagonMCChecker { + static pair Unconditional; + void checkRegisters(); +}; +pair HexagonMCChecker::Unconditional(Hexagon::NoRegister, 0); +void HexagonMCChecker::checkRegisters() {} diff --git a/clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-2.cpp b/clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-2.cpp new file mode 100644 index 000000000000..02200ce4f34a --- /dev/null +++ b/clang/test/Parser/gh30908-scope-balance-on-invalid-var-direct-init-2.cpp @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 -fsyntax-only -verify %s + +#include // expected-error {{file not found}} + +class S {}; + +template +class E { +public: + E(S* scope) {} + S &getS(); +}; + +class Z { + private: + static E e; + static S& s(); +}; + +E Z::e(&__UNKNOWN_ID__); + +S& Z::s() { return Z::e.getS(); } -- GitLab From ea3c7b3397f8de8e885ea7cd1ed5138ec4a72d50 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Tue, 9 Jan 2024 17:14:55 -0800 Subject: [PATCH 277/652] Revert "[X86][NFC] Remove dead code for "_REV" instructions" This reverts commit 85f3d81fabb9381ce5bc0112d029a7c684b01006. Affects BOLT macro-fusion and not NFC. --- llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 16 ++++++++++++++++ llvm/lib/Target/X86/X86FlagsCopyLowering.cpp | 1 + 2 files changed, 17 insertions(+) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h index 304b998e1f26..e006dd877360 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -148,21 +148,25 @@ classifyFirstOpcodeInMacroFusion(unsigned Opcode) { case X86::AND16ri8: case X86::AND16rm: case X86::AND16rr: + case X86::AND16rr_REV: case X86::AND32i32: case X86::AND32ri: case X86::AND32ri8: case X86::AND32rm: case X86::AND32rr: + case X86::AND32rr_REV: case X86::AND64i32: case X86::AND64ri32: case X86::AND64ri8: case X86::AND64rm: case X86::AND64rr: + case X86::AND64rr_REV: case X86::AND8i8: case X86::AND8ri: case X86::AND8ri8: case X86::AND8rm: case X86::AND8rr: + case X86::AND8rr_REV: return FirstMacroFusionInstKind::And; // CMP case X86::CMP16i16: @@ -171,24 +175,28 @@ classifyFirstOpcodeInMacroFusion(unsigned Opcode) { case X86::CMP16ri8: case X86::CMP16rm: case X86::CMP16rr: + case X86::CMP16rr_REV: case X86::CMP32i32: case X86::CMP32mr: case X86::CMP32ri: case X86::CMP32ri8: case X86::CMP32rm: case X86::CMP32rr: + case X86::CMP32rr_REV: case X86::CMP64i32: case X86::CMP64mr: case X86::CMP64ri32: case X86::CMP64ri8: case X86::CMP64rm: case X86::CMP64rr: + case X86::CMP64rr_REV: case X86::CMP8i8: case X86::CMP8mr: case X86::CMP8ri: case X86::CMP8ri8: case X86::CMP8rm: case X86::CMP8rr: + case X86::CMP8rr_REV: return FirstMacroFusionInstKind::Cmp; // ADD case X86::ADD16i16: @@ -196,42 +204,50 @@ classifyFirstOpcodeInMacroFusion(unsigned Opcode) { case X86::ADD16ri8: case X86::ADD16rm: case X86::ADD16rr: + case X86::ADD16rr_REV: case X86::ADD32i32: case X86::ADD32ri: case X86::ADD32ri8: case X86::ADD32rm: case X86::ADD32rr: + case X86::ADD32rr_REV: case X86::ADD64i32: case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD64rm: case X86::ADD64rr: + case X86::ADD64rr_REV: case X86::ADD8i8: case X86::ADD8ri: case X86::ADD8ri8: case X86::ADD8rm: case X86::ADD8rr: + case X86::ADD8rr_REV: // SUB case X86::SUB16i16: case X86::SUB16ri: case X86::SUB16ri8: case X86::SUB16rm: case X86::SUB16rr: + case X86::SUB16rr_REV: case X86::SUB32i32: case X86::SUB32ri: case X86::SUB32ri8: case X86::SUB32rm: case X86::SUB32rr: + case X86::SUB32rr_REV: case X86::SUB64i32: case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB64rm: case X86::SUB64rr: + case X86::SUB64rr_REV: case X86::SUB8i8: case X86::SUB8ri: case X86::SUB8ri8: case X86::SUB8rm: case X86::SUB8rr: + case X86::SUB8rr_REV: return FirstMacroFusionInstKind::AddSub; // INC case X86::INC16r: diff --git a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp index aad839b83ee1..b13bf361ab79 100644 --- a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp +++ b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp @@ -173,6 +173,7 @@ static FlagArithMnemonic getMnemonicFromOpcode(unsigned Opcode) { #define LLVM_EXPAND_ADC_SBB_INSTR(MNEMONIC) \ LLVM_EXPAND_INSTR_SIZES(MNEMONIC, rr) \ + LLVM_EXPAND_INSTR_SIZES(MNEMONIC, rr_REV) \ LLVM_EXPAND_INSTR_SIZES(MNEMONIC, rm) \ LLVM_EXPAND_INSTR_SIZES(MNEMONIC, mr) \ case X86::MNEMONIC##8ri: \ -- GitLab From 6615581526f62a00833b2d60cc31f7f12497b5ff Mon Sep 17 00:00:00 2001 From: Kai Luo Date: Wed, 10 Jan 2024 09:23:30 +0800 Subject: [PATCH 278/652] [PowerPC] Make verifier happy when lowering `llvm.trap` (#77266) `llvm.trap` is lowered to `PPC::TRAP` and `PPC::TRAP` is set as terminator. Verifier complains about terminator should not lie in the middle of an MBB. See #77095. Fix it by removing `isTerminator` and `isBarrier` and then set `isTrap` which was introduced by https://reviews.llvm.org/D48836# and is being used by X86 and AArch64. `PPC::TRAP` is not a hardware memory barrier and `llvm.trap` doesn't indicate a memory barrier either. --- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 +- llvm/test/CodeGen/PowerPC/intrinsic-trap.ll | 12 +++++++++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index b1601739fd45..bf756e39bd5d 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1909,7 +1909,7 @@ def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB), "stwat $RST, $RA, $RB", IIC_LdStStore>, Requires<[IsISA3_0]>; -let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in +let isTrap = 1, hasCtrlDep = 1 in def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops), diff --git a/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll index b02eb5d8fd27..b8eb7a35f61e 100644 --- a/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll +++ b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll @@ -1,8 +1,14 @@ -; REQUIRES: asserts -; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64le-- < %s 2>&1 | FileCheck %s -; CHECK: Bad machine code: Non-terminator instruction after the first terminator +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -ppc-opt-conditional-trap \ +; RUN: < %s | FileCheck %s define i32 @test() { +; CHECK-LABEL: test: +; CHECK: # %bb.0: +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: trap +; CHECK-NEXT: blr call void @llvm.trap() ret i32 0 } -- GitLab From c9124adfd8291a5f5b1d23295308d8940648c596 Mon Sep 17 00:00:00 2001 From: HaohaiWen Date: Wed, 10 Jan 2024 09:25:45 +0800 Subject: [PATCH 279/652] Revert "[SEH][CodeGen] Add test to track CFG optimization bug for SEH" (#77542) Reverts llvm/llvm-project#77441 I'll land it with fix. --- .../X86/windows-seh-EHa-PreserveCFG.ll | 81 ------------------- 1 file changed, 81 deletions(-) delete mode 100644 llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll diff --git a/llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll b/llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll deleted file mode 100644 index bd6743f7c414..000000000000 --- a/llvm/test/CodeGen/X86/windows-seh-EHa-PreserveCFG.ll +++ /dev/null @@ -1,81 +0,0 @@ -; XFAIL: * -; RUN: llc -mtriple=x86_64-pc-windows-msvc %s -define dso_local void @main(ptr %addr, ptr %src, ptr %dst) personality ptr @__CxxFrameHandler3 !dbg !11 { -entry: - %tmp0 = load float, ptr %src - %src1 = getelementptr inbounds float, ptr %src, i64 1 - %tmp1 = load float, ptr %src1 - %src2 = getelementptr inbounds float, ptr %src, i64 2 - %tmp2 = load float, ptr %src2 - %src3 = getelementptr inbounds float, ptr %src, i64 3 - %tmp3 = load float, ptr %src3 - %src4 = getelementptr inbounds float, ptr %src, i64 4 - %tmp4 = load float, ptr %src4 - %src5 = getelementptr inbounds float, ptr %src, i64 5 - %tmp5 = load float, ptr %src5 - %src6 = getelementptr inbounds float, ptr %src, i64 6 - %tmp6 = load float, ptr %src6 - invoke void @foo(ptr %addr) - to label %scope_begin unwind label %ehcleanup1, !dbg !13 - -scope_begin: - invoke void @llvm.seh.scope.begin() - to label %scope_end unwind label %ehcleanup, !dbg !13 - -scope_end: - invoke void @llvm.seh.scope.end() - to label %finish unwind label %ehcleanup, !dbg !13 - -ehcleanup: - %0 = cleanuppad within none [], !dbg !13 - call void @llvm.dbg.value(metadata ptr %addr, metadata !12, metadata !DIExpression()), !dbg !13 - call void @foo(ptr %addr) [ "funclet"(token %0) ], !dbg !13 - cleanupret from %0 unwind label %ehcleanup1, !dbg !13 - -ehcleanup1: - %1 = cleanuppad within none [], !dbg !13 - call void @foo(ptr %addr) [ "funclet"(token %1) ], !dbg !13 - cleanupret from %1 unwind to caller, !dbg !13 - -finish: - store float %tmp0, ptr %dst - %dst1 = getelementptr inbounds float, ptr %dst, i64 1 - store float %tmp1, ptr %dst1 - %dst2 = getelementptr inbounds float, ptr %dst, i64 2 - store float %tmp2, ptr %dst2 - %dst3 = getelementptr inbounds float, ptr %dst, i64 3 - store float %tmp3, ptr %dst3 - %dst4 = getelementptr inbounds float, ptr %dst, i64 4 - store float %tmp4, ptr %dst4 - %dst5 = getelementptr inbounds float, ptr %dst, i64 5 - store float %tmp5, ptr %dst5 - %dst6 = getelementptr inbounds float, ptr %dst, i64 6 - store float %tmp6, ptr %dst6 - ret void -} - -declare dso_local void @llvm.seh.scope.begin() -declare dso_local void @llvm.seh.scope.end() -declare dso_local i32 @__CxxFrameHandler3(...) -declare dso_local void @foo(ptr %addr) -declare void @llvm.dbg.value(metadata, metadata, metadata) - -!llvm.module.flags = !{!0, !1, !2, !3} -!llvm.dbg.cu = !{!14} - -!0 = !{i32 2, !"eh-asynch", i32 1} -!1 = !{i32 2, !"CodeView", i32 1} -!2 = !{i32 2, !"Debug Info Version", i32 3} -!3 = !{i32 7, !"uwtable", i32 2} - -!4 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) -!5 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64) -!6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !6, size: 64) -!8 = !DISubroutineType(types: !9) -!9 = !{null, !7, !5, !5} -!10 = !DIFile(filename: "c:/main.cpp", directory: "") -!11 = distinct !DISubprogram(name: "main", scope: !10, file: !10, line: 5, type: !8, scopeLine: 11, unit: !14) -!12 = !DILocalVariable(name: "addr", scope: !11, file: !10, line: 5, type: !7) -!13 = !DILocation(line: 7, scope: !11) -!14 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !10, isOptimized: true, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -- GitLab From e364ddf0c9044f3af147a907aa770599a206c30f Mon Sep 17 00:00:00 2001 From: Nicholas Mosier Date: Tue, 9 Jan 2024 18:13:57 -0800 Subject: [PATCH 280/652] [docs] Fix formatting issues in MyFirstTypoFix (#77527) Fix various formatting issues in MyFirstTypoFix. --- llvm/docs/MyFirstTypoFix.rst | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/llvm/docs/MyFirstTypoFix.rst b/llvm/docs/MyFirstTypoFix.rst index b6040af756e2..b8d34733122c 100644 --- a/llvm/docs/MyFirstTypoFix.rst +++ b/llvm/docs/MyFirstTypoFix.rst @@ -91,8 +91,8 @@ It may take a while to download! $ git clone https://github.com/llvm/llvm-project.git This will create a directory "llvm-project" with all of the source -code.(Checking out anonymously is OK - pushing commits uses a different -mechanism, as we'll see later) +code. (Checking out anonymously is OK - pushing commits uses a different +mechanism, as we'll see later.) Configure your workspace ------------------------ @@ -142,21 +142,21 @@ Let's break down that last command a little: - The two **-D** flags set CMake variables, which override CMake/project defaults: -- **CMAKE\ BUILD\ TYPE=Release**: build in optimized mode, which is - (surprisingly) the fastest option. + - **CMAKE_BUILD_TYPE=Release**: build in optimized mode, which is + (surprisingly) the fastest option. - If you want to run under a debugger, you should use the default Debug - (which is totally unoptimized, and will lead to >10x slower test - runs) or RelWithDebInfo which is a halfway point. - **CMAKE\ BUILD\ TYPE** affects code generation only, assertions are - on by default regardless! **LLVM\ ENABLE\ ASSERTIONS=Off** disables - them. + If you want to run under a debugger, you should use the default Debug + (which is totally unoptimized, and will lead to >10x slower test + runs) or RelWithDebInfo which is a halfway point. + **CMAKE_BUILD_TYPE** affects code generation only, assertions are + on by default regardless! **LLVM_ENABLE_ASSERTIONS=Off** disables + them. -- **LLVM\ ENABLE\ PROJECTS=clang** : this lists the LLVM subprojects - you are interested in building, in addition to LLVM itself. Multiple - projects can be listed, separated by semicolons, such as "clang; - lldb".In this example, we'll be making a change to Clang, so we - should build it. + - **LLVM_ENABLE_PROJECTS=clang**: this lists the LLVM subprojects + you are interested in building, in addition to LLVM itself. Multiple + projects can be listed, separated by semicolons, such as "clang; + lldb".In this example, we'll be making a change to Clang, so we + should build it. Finally, create a symlink (or a copy) of llvm-project/build/compile-commands.json into llvm-project/: @@ -225,7 +225,7 @@ the message in your favorite editor: $ vi ../clang/include/clang/Basic/DiagnosticSemaKinds.td Find the message (it should be under -warn\ *infinite*\ recursive_function)Change the message to "in order to +``warn_infinite_recursive_function``). Change the message to "in order to understand recursion, you must first understand recursion". -- GitLab From aa4c1e90b6f25a5c6312927e0574f9d07fa25582 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Tue, 9 Jan 2024 18:34:32 -0800 Subject: [PATCH 281/652] Revert "[PGO] Fix `instrprof-api.c` on Windows (#77508)" Issue #77546 This reverts commit b6d1577071017f1ba3f12bfe30c1746ffaf5d98d. --- compiler-rt/test/profile/instrprof-api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler-rt/test/profile/instrprof-api.c b/compiler-rt/test/profile/instrprof-api.c index b6f75426b2a7..1381300c1ad1 100644 --- a/compiler-rt/test/profile/instrprof-api.c +++ b/compiler-rt/test/profile/instrprof-api.c @@ -29,8 +29,8 @@ int foo() { int main() { int z = foo() + 3; __llvm_profile_set_filename("rawprof.profraw"); - // PROFGEN: call void @__llvm_profile_set_filename(ptr noundef @{{.*}}) - // PROFUSE-NOT: call void @__llvm_profile_set_filename(ptr noundef @{{.*}}) + // PROFGEN: call void @__llvm_profile_set_filename(ptr noundef @.str) + // PROFUSE-NOT: call void @__llvm_profile_set_filename(ptr noundef @.str) if (__llvm_profile_dump()) return 2; // PROFGEN: %call1 = call {{(signext )*}}i32 @__llvm_profile_dump() -- GitLab From a828cda9c80282a77b579f8fc9dc17a310173af4 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Tue, 9 Jan 2024 18:37:04 -0800 Subject: [PATCH 282/652] Revert "[PGO] Exposing PGO's Counter Reset and File Dumping APIs (#76471)" Issue #77546 This reverts commit 07c9189fcc063bdf6219d2733843c89cde3991e1. --- .../ExpandModularHeadersPPCallbacks.cpp | 2 +- clang/docs/UsersManual.rst | 104 ------------------ clang/include/clang/Basic/CodeGenOptions.h | 6 - clang/include/clang/Frontend/Utils.h | 4 +- clang/lib/Frontend/CompilerInstance.cpp | 2 +- clang/lib/Frontend/InitPreprocessor.cpp | 23 +--- clang/test/Profile/c-general.c | 10 -- compiler-rt/include/CMakeLists.txt | 1 - .../include/profile/instr_prof_interface.h | 92 ---------------- compiler-rt/lib/profile/InstrProfiling.h | 61 ++++++++-- .../profile/Linux/instrprof-weak-symbol.c | 16 --- compiler-rt/test/profile/instrprof-api.c | 46 -------- 12 files changed, 57 insertions(+), 310 deletions(-) delete mode 100644 compiler-rt/include/profile/instr_prof_interface.h delete mode 100644 compiler-rt/test/profile/Linux/instrprof-weak-symbol.c delete mode 100644 compiler-rt/test/profile/instrprof-api.c diff --git a/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp b/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp index 5ecd4fb19131..e414ac8c7705 100644 --- a/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp +++ b/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp @@ -100,7 +100,7 @@ ExpandModularHeadersPPCallbacks::ExpandModularHeadersPPCallbacks( /*OwnsHeaderSearch=*/false); PP->Initialize(Compiler.getTarget(), Compiler.getAuxTarget()); InitializePreprocessor(*PP, *PO, Compiler.getPCHContainerReader(), - Compiler.getFrontendOpts(), Compiler.getCodeGenOpts()); + Compiler.getFrontendOpts()); ApplyHeaderSearchOptions(*HeaderInfo, *HSO, LangOpts, Compiler.getTarget().getTriple()); } diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 27c629a1ffc6..7c30570437e8 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -2809,110 +2809,6 @@ indexed format, regardeless whether it is produced by frontend or the IR pass. overhead. ``prefer-atomic`` will be transformed to ``atomic`` when supported by the target, or ``single`` otherwise. -Fine Tuning Profile Collection -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The PGO infrastructure provides user program knobs to fine tune profile -collection. Specifically, the PGO runtime provides the following functions -that can be used to control the regions in the program where profiles should -be collected. - - * ``void __llvm_profile_set_filename(const char *Name)``: changes the name of - the profile file to ``Name``. - * ``void __llvm_profile_reset_counters(void)``: resets all counters to zero. - * ``int __llvm_profile_dump(void)``: write the profile data to disk. - * ``int __llvm_orderfile_dump(void)``: write the order file to disk. - -For example, the following pattern can be used to skip profiling program -initialization, profile two specific hot regions, and skip profiling program -cleanup: - -.. code-block:: c - - int main() { - initialize(); - - // Reset all profile counters to 0 to omit profile collected during - // initialize()'s execution. - __llvm_profile_reset_counters(); - ... hot region 1 - // Dump the profile for hot region 1. - __llvm_profile_set_filename("region1.profraw"); - __llvm_profile_dump(); - - // Reset counters before proceeding to hot region 2. - __llvm_profile_reset_counters(); - ... hot region 2 - // Dump the profile for hot region 2. - __llvm_profile_set_filename("region2.profraw"); - __llvm_profile_dump(); - - // Since the profile has been dumped, no further profile data - // will be collected beyond the above __llvm_profile_dump(). - cleanup(); - return 0; - } - -These APIs' names can be introduced to user programs in two ways. -They can be declared as weak symbols on platforms which support -treating weak symbols as ``null`` during linking. For example, the user can -have - -.. code-block:: c - - __attribute__((weak)) int __llvm_profile_dump(void); - - // Then later in the same source file - if (__llvm_profile_dump) - if (__llvm_profile_dump() != 0) { ... } - // The first if condition tests if the symbol is actually defined. - // Profile dumping only happens if the symbol is defined. Hence, - // the user program works correctly during normal (not profile-generate) - // executions. - -Alternatively, the user program can include the header -``profile/instr_prof_interface.h``, which contains the API names. For example, - -.. code-block:: c - - #include "profile/instr_prof_interface.h" - - // Then later in the same source file - if (__llvm_profile_dump() != 0) { ... } - -The user code does not need to check if the API names are defined, because -these names are automatically replaced by ``(0)`` or the equivalence of noop -if the ``clang`` is not compiling for profile generation. - -Such replacement can happen because ``clang`` adds one of two macros depending -on the ``-fprofile-generate`` and the ``-fprofile-use`` flags. - - * ``__LLVM_INSTR_PROFILE_GENERATE``: defined when one of - ``-fprofile[-instr]-generate``/``-fcs-profile-generate`` is in effect. - * ``__LLVM_INSTR_PROFILE_USE``: defined when one of - ``-fprofile-use``/``-fprofile-instr-use`` is in effect. - -The two macros can be used to provide more flexibiilty so a user program -can execute code specifically intended for profile generate or profile use. -For example, a user program can have special logging during profile generate: - -.. code-block:: c - - #if __LLVM_INSTR_PROFILE_GENERATE - expensive_logging_of_full_program_state(); - #endif - -The logging is automatically excluded during a normal build of the program, -hence it does not impact performance during a normal execution. - -It is advised to use such fine tuning only in a program's cold regions. The weak -symbols can introduce extra control flow (the ``if`` checks), while the macros -(hence declarations they guard in ``profile/instr_prof_interface.h``) -can change the control flow of the functions that use them between profile -generation and profile use (which can lead to discarded counters in such -functions). Using these APIs in the program's cold regions introduces less -overhead and leads to more optimized code. - Disabling Instrumentation ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h index e06f1094784c..6952b48e898a 100644 --- a/clang/include/clang/Basic/CodeGenOptions.h +++ b/clang/include/clang/Basic/CodeGenOptions.h @@ -494,12 +494,6 @@ public: return getProfileInstr() == ProfileCSIRInstr; } - /// Check if any form of instrumentation is on. - bool hasProfileInstr() const { - return hasProfileClangInstr() || hasProfileIRInstr() || - hasProfileCSIRInstr(); - } - /// Check if Clang profile use is on. bool hasProfileClangUse() const { return getProfileUse() == ProfileClangInstr; diff --git a/clang/include/clang/Frontend/Utils.h b/clang/include/clang/Frontend/Utils.h index 604e42067a3f..143cf4359f00 100644 --- a/clang/include/clang/Frontend/Utils.h +++ b/clang/include/clang/Frontend/Utils.h @@ -43,14 +43,12 @@ class PCHContainerReader; class Preprocessor; class PreprocessorOptions; class PreprocessorOutputOptions; -class CodeGenOptions; /// InitializePreprocessor - Initialize the preprocessor getting it and the /// environment ready to process a single file. void InitializePreprocessor(Preprocessor &PP, const PreprocessorOptions &PPOpts, const PCHContainerReader &PCHContainerRdr, - const FrontendOptions &FEOpts, - const CodeGenOptions &CodeGenOpts); + const FrontendOptions &FEOpts); /// DoPrintPreprocessedInput - Implement -E mode. void DoPrintPreprocessedInput(Preprocessor &PP, raw_ostream *OS, diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp index ea44a26b6db7..56bbef9697b6 100644 --- a/clang/lib/Frontend/CompilerInstance.cpp +++ b/clang/lib/Frontend/CompilerInstance.cpp @@ -470,7 +470,7 @@ void CompilerInstance::createPreprocessor(TranslationUnitKind TUKind) { // Predefine macros and configure the preprocessor. InitializePreprocessor(*PP, PPOpts, getPCHContainerReader(), - getFrontendOpts(), getCodeGenOpts()); + getFrontendOpts()); // Initialize the header search object. In CUDA compilations, we use the aux // triple (the host triple) to initialize our header search, since we need to diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index fe0fd3614113..d83128adb511 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -1364,22 +1364,12 @@ static void InitializePredefinedMacros(const TargetInfo &TI, TI.getTargetDefines(LangOpts, Builder); } -static void InitializePGOProfileMacros(const CodeGenOptions &CodeGenOpts, - MacroBuilder &Builder) { - if (CodeGenOpts.hasProfileInstr()) - Builder.defineMacro("__LLVM_INSTR_PROFILE_GENERATE"); - - if (CodeGenOpts.hasProfileIRUse() || CodeGenOpts.hasProfileClangUse()) - Builder.defineMacro("__LLVM_INSTR_PROFILE_USE"); -} - /// InitializePreprocessor - Initialize the preprocessor getting it and the /// environment ready to process a single file. -void clang::InitializePreprocessor(Preprocessor &PP, - const PreprocessorOptions &InitOpts, - const PCHContainerReader &PCHContainerRdr, - const FrontendOptions &FEOpts, - const CodeGenOptions &CodeGenOpts) { +void clang::InitializePreprocessor( + Preprocessor &PP, const PreprocessorOptions &InitOpts, + const PCHContainerReader &PCHContainerRdr, + const FrontendOptions &FEOpts) { const LangOptions &LangOpts = PP.getLangOpts(); std::string PredefineBuffer; PredefineBuffer.reserve(4080); @@ -1426,11 +1416,6 @@ void clang::InitializePreprocessor(Preprocessor &PP, InitializeStandardPredefinedMacros(PP.getTargetInfo(), PP.getLangOpts(), FEOpts, Builder); - // The PGO instrumentation profile macros are driven by options - // -fprofile[-instr]-generate/-fcs-profile-generate/-fprofile[-instr]-use, - // hence they are not guarded by InitOpts.UsePredefines. - InitializePGOProfileMacros(CodeGenOpts, Builder); - // Add on the predefines from the driver. Wrap in a #line directive to report // that they come from the command line. Builder.append("# 1 \"\" 1"); diff --git a/clang/test/Profile/c-general.c b/clang/test/Profile/c-general.c index 2f621ec9b0bf..b841f9c3d2a1 100644 --- a/clang/test/Profile/c-general.c +++ b/clang/test/Profile/c-general.c @@ -9,16 +9,6 @@ // Also check compatibility with older profiles. // RUN: %clang_cc1 -triple x86_64-apple-macosx10.9 -main-file-name c-general.c %s -o - -emit-llvm -fprofile-instrument-use-path=%S/Inputs/c-general.profdata.v1 | FileCheck -allow-deprecated-dag-overlap -check-prefix=PGOUSE %s -// RUN: %clang -fprofile-generate -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFGENMACRO %s -// RUN: %clang -fprofile-instr-generate -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFGENMACRO %s -// RUN: %clang -fcs-profile-generate -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFGENMACRO %s -// -// RUN: %clang -fprofile-use=%t.profdata -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFUSEMACRO %s -// RUN: %clang -fprofile-instr-use=%t.profdata -E -dM %s | FileCheck -match-full-lines -check-prefix=PROFUSEMACRO %s - -// PROFGENMACRO:#define __LLVM_INSTR_PROFILE_GENERATE 1 -// PROFUSEMACRO:#define __LLVM_INSTR_PROFILE_USE 1 - // PGOGEN: @[[SLC:__profc_simple_loops]] = private global [4 x i64] zeroinitializer // PGOGEN: @[[IFC:__profc_conditionals]] = private global [13 x i64] zeroinitializer // PGOGEN: @[[EEC:__profc_early_exits]] = private global [9 x i64] zeroinitializer diff --git a/compiler-rt/include/CMakeLists.txt b/compiler-rt/include/CMakeLists.txt index 7a100c66bbcf..78427beedb3c 100644 --- a/compiler-rt/include/CMakeLists.txt +++ b/compiler-rt/include/CMakeLists.txt @@ -44,7 +44,6 @@ endif(COMPILER_RT_BUILD_ORC) if (COMPILER_RT_BUILD_PROFILE) set(PROFILE_HEADERS profile/InstrProfData.inc - profile/instr_prof_interface.h ) endif(COMPILER_RT_BUILD_PROFILE) diff --git a/compiler-rt/include/profile/instr_prof_interface.h b/compiler-rt/include/profile/instr_prof_interface.h deleted file mode 100644 index be40f2685934..000000000000 --- a/compiler-rt/include/profile/instr_prof_interface.h +++ /dev/null @@ -1,92 +0,0 @@ -/*===---- instr_prof_interface.h - Instrumentation PGO User Program API ----=== - * - * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. - * See https://llvm.org/LICENSE.txt for license information. - * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception - * - *===-----------------------------------------------------------------------=== - * - * This header provides a public interface for fine-grained control of counter - * reset and profile dumping. These interface functions can be directly called - * in user programs. - * -\*===---------------------------------------------------------------------===*/ - -#ifndef COMPILER_RT_INSTR_PROFILING -#define COMPILER_RT_INSTR_PROFILING - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __LLVM_INSTR_PROFILE_GENERATE -// Profile file reset and dump interfaces. -// When `-fprofile[-instr]-generate`/`-fcs-profile-generate` is in effect, -// clang defines __LLVM_INSTR_PROFILE_GENERATE to pick up the API calls. - -/*! - * \brief Set the filename for writing instrumentation data. - * - * Sets the filename to be used for subsequent calls to - * \a __llvm_profile_write_file(). - * - * \c Name is not copied, so it must remain valid. Passing NULL resets the - * filename logic to the default behaviour. - * - * Note: There may be multiple copies of the profile runtime (one for each - * instrumented image/DSO). This API only modifies the filename within the - * copy of the runtime available to the calling image. - * - * Warning: This is a no-op if continuous mode (\ref - * __llvm_profile_is_continuous_mode_enabled) is on. The reason for this is - * that in continuous mode, profile counters are mmap()'d to the profile at - * program initialization time. Support for transferring the mmap'd profile - * counts to a new file has not been implemented. - */ -void __llvm_profile_set_filename(const char *Name); - -/*! - * \brief Interface to set all PGO counters to zero for the current process. - * - */ -void __llvm_profile_reset_counters(void); - -/*! - * \brief this is a wrapper interface to \c __llvm_profile_write_file. - * After this interface is invoked, an already dumped flag will be set - * so that profile won't be dumped again during program exit. - * Invocation of interface __llvm_profile_reset_counters will clear - * the flag. This interface is designed to be used to collect profile - * data from user selected hot regions. The use model is - * __llvm_profile_reset_counters(); - * ... hot region 1 - * __llvm_profile_dump(); - * .. some other code - * __llvm_profile_reset_counters(); - * ... hot region 2 - * __llvm_profile_dump(); - * - * It is expected that on-line profile merging is on with \c %m specifier - * used in profile filename . If merging is not turned on, user is expected - * to invoke __llvm_profile_set_filename to specify different profile names - * for different regions before dumping to avoid profile write clobbering. - */ -int __llvm_profile_dump(void); - -// Interface to dump the current process' order file to disk. -int __llvm_orderfile_dump(void); - -#else - -#define __llvm_profile_set_filename(Name) -#define __llvm_profile_reset_counters() -#define __llvm_profile_dump() (0) -#define __llvm_orderfile_dump() (0) - -#endif - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/compiler-rt/lib/profile/InstrProfiling.h b/compiler-rt/lib/profile/InstrProfiling.h index 012390833691..137115996748 100644 --- a/compiler-rt/lib/profile/InstrProfiling.h +++ b/compiler-rt/lib/profile/InstrProfiling.h @@ -12,17 +12,6 @@ #include "InstrProfilingPort.h" #include -// Make sure __LLVM_INSTR_PROFILE_GENERATE is always defined before -// including instr_prof_interface.h so the interface functions are -// declared correctly for the runtime. -// __LLVM_INSTR_PROFILE_GENERATE is always `#undef`ed after the header, -// because compiler-rt does not support profiling the profiling runtime itself. -#ifndef __LLVM_INSTR_PROFILE_GENERATE -#define __LLVM_INSTR_PROFILE_GENERATE -#endif -#include "profile/instr_prof_interface.h" -#undef __LLVM_INSTR_PROFILE_GENERATE - #define INSTR_PROF_VISIBILITY COMPILER_RT_VISIBILITY #include "profile/InstrProfData.inc" @@ -111,6 +100,12 @@ ValueProfNode *__llvm_profile_begin_vnodes(); ValueProfNode *__llvm_profile_end_vnodes(); uint32_t *__llvm_profile_begin_orderfile(); +/*! + * \brief Clear profile counters to zero. + * + */ +void __llvm_profile_reset_counters(void); + /*! * \brief Merge profile data from buffer. * @@ -161,6 +156,50 @@ void __llvm_profile_instrument_target_value(uint64_t TargetValue, void *Data, int __llvm_profile_write_file(void); int __llvm_orderfile_write_file(void); +/*! + * \brief this is a wrapper interface to \c __llvm_profile_write_file. + * After this interface is invoked, an already dumped flag will be set + * so that profile won't be dumped again during program exit. + * Invocation of interface __llvm_profile_reset_counters will clear + * the flag. This interface is designed to be used to collect profile + * data from user selected hot regions. The use model is + * __llvm_profile_reset_counters(); + * ... hot region 1 + * __llvm_profile_dump(); + * .. some other code + * __llvm_profile_reset_counters(); + * ... hot region 2 + * __llvm_profile_dump(); + * + * It is expected that on-line profile merging is on with \c %m specifier + * used in profile filename . If merging is not turned on, user is expected + * to invoke __llvm_profile_set_filename to specify different profile names + * for different regions before dumping to avoid profile write clobbering. + */ +int __llvm_profile_dump(void); + +int __llvm_orderfile_dump(void); + +/*! + * \brief Set the filename for writing instrumentation data. + * + * Sets the filename to be used for subsequent calls to + * \a __llvm_profile_write_file(). + * + * \c Name is not copied, so it must remain valid. Passing NULL resets the + * filename logic to the default behaviour. + * + * Note: There may be multiple copies of the profile runtime (one for each + * instrumented image/DSO). This API only modifies the filename within the + * copy of the runtime available to the calling image. + * + * Warning: This is a no-op if continuous mode (\ref + * __llvm_profile_is_continuous_mode_enabled) is on. The reason for this is + * that in continuous mode, profile counters are mmap()'d to the profile at + * program initialization time. Support for transferring the mmap'd profile + * counts to a new file has not been implemented. + */ +void __llvm_profile_set_filename(const char *Name); /*! * \brief Set the FILE object for writing instrumentation data. Return 0 if set diff --git a/compiler-rt/test/profile/Linux/instrprof-weak-symbol.c b/compiler-rt/test/profile/Linux/instrprof-weak-symbol.c deleted file mode 100644 index eda299cb6610..000000000000 --- a/compiler-rt/test/profile/Linux/instrprof-weak-symbol.c +++ /dev/null @@ -1,16 +0,0 @@ -// Test the linker feature that treats undefined weak symbols as null values. - -// RUN: %clang_pgogen -o %t %s -// RUN: not %t -// RUN: %clang -o %t %s -// RUN: %t - -__attribute__((weak)) void __llvm_profile_reset_counters(void); - -int main() { - if (__llvm_profile_reset_counters) { - __llvm_profile_reset_counters(); - return 1; - } - return 0; -} diff --git a/compiler-rt/test/profile/instrprof-api.c b/compiler-rt/test/profile/instrprof-api.c deleted file mode 100644 index 1381300c1ad1..000000000000 --- a/compiler-rt/test/profile/instrprof-api.c +++ /dev/null @@ -1,46 +0,0 @@ -// Testing profile generate. -// RUN: %clang_profgen %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFGEN -// RUN: %clang_pgogen %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFGEN - -// Testing profile use. Generate some profile file first. -// RUN: rm -rf rawprof.profraw -// RUN: %clang_profgen -o %t1 %s -// RUN: %run %t1 -// RUN: llvm-profdata merge -o %t1.profdata rawprof.profraw -// RUN: %clang_profuse=%t1.profdata %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFUSE -// RUN: rm -rf rawprof.profraw -// RUN: %clang_pgogen -o %t2 %s -// RUN: %run %t2 -// RUN: llvm-profdata merge -o %t2.profdata rawprof.profraw -// RUN: %clang_pgouse=%t2.profdata %s -S -emit-llvm -o - | FileCheck %s --check-prefix=PROFUSE -#include "profile/instr_prof_interface.h" - -__attribute__((noinline)) int bar() { return 4; } - -int foo() { - __llvm_profile_reset_counters(); - // PROFGEN: call void @__llvm_profile_reset_counters() - // PROFUSE-NOT: call void @__llvm_profile_reset_counters() - return bar(); -} - -// PROFUSE-NOT: declare void @__llvm_profile_reset_counters() - -int main() { - int z = foo() + 3; - __llvm_profile_set_filename("rawprof.profraw"); - // PROFGEN: call void @__llvm_profile_set_filename(ptr noundef @.str) - // PROFUSE-NOT: call void @__llvm_profile_set_filename(ptr noundef @.str) - if (__llvm_profile_dump()) - return 2; - // PROFGEN: %call1 = call {{(signext )*}}i32 @__llvm_profile_dump() - // PROFUSE-NOT: %call1 = call {{(signext )*}}i32 @__llvm_profile_dump() - __llvm_orderfile_dump(); - // PROFGEN: %call2 = call {{(signext )*}}i32 @__llvm_orderfile_dump() - // PROFUSE-NOT: %call2 = call {{(signext )*}}i32 @__llvm_orderfile_dump() - return z + bar() - 11; -} - -// PROFUSE-NOT: declare void @__llvm_profile_set_filename(ptr noundef) -// PROFUSE-NOT: declare signext i32 @__llvm_profile_dump() -// PROFUSE-NOT: declare signext i32 @__llvm_orderfile_dump() -- GitLab From 3593ade43dd8af557432dce72f93aa0186c281ef Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Wed, 10 Jan 2024 02:53:25 +0000 Subject: [PATCH 283/652] [gn build] Port a828cda9c802 --- llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn b/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn index 0028c2cb6739..bd88978c105c 100644 --- a/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn +++ b/llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn @@ -5,7 +5,6 @@ copy("include") { "fuzzer/FuzzedDataProvider.h", "orc_rt/c_api.h", "profile/InstrProfData.inc", - "profile/instr_prof_interface.h", "profile/MemProfData.inc", "sanitizer/allocator_interface.h", "sanitizer/asan_interface.h", -- GitLab From a79d13f12ab81bc6edd54e27f7cfffb96487af8d Mon Sep 17 00:00:00 2001 From: Chia Date: Wed, 10 Jan 2024 12:08:16 +0900 Subject: [PATCH 284/652] [RISCV][ISel] Use vaaddu with rounding mode rnu for ISD::AVGCEILU. (#77473) Similar to #76550, but for `ISD::AVGCEILU`. Specifically, this patch aims to use `vaaddu` with rounding mode rnu (i.e `vxrm[1:0] = 0b00`) for `ISD::AVGCEILU`. ### Source code ``` define @vaaddu_vv_nxv8i8_ceil( %x, %y) { %xzv = zext %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv %one = insertelement poison, i16 1, i32 0 %splat = shufflevector %one, poison, zeroinitializer %add1 = add nuw nsw %add, %splat %div = lshr %add1, %splat %ret = trunc %div to ret %ret } ``` ### Before this patch ``` vaaddu_vv_nxv8i8_ceil: vsetvli a0, zero, e8, m1, ta, ma vwaddu.vv v10, v8, v9 vsetvli zero, zero, e16, m2, ta, ma vadd.vi v10, v10, 1 vsetvli zero, zero, e8, m1, ta, ma vnsrl.wi v8, v10, 1 ret ``` ### After this patch ``` vaaddu_vv_nxv8i8_ceil: vsetvli a0, zero, e8, m1, ta, ma csrwi vxrm, 0 vaaddu.vv v8, v8, v9 ret ``` --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 15 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 + .../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 33 +- .../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 38 ++- .../CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll | 305 ++++++++++++++++-- llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll | 295 +++++++++++++++-- 6 files changed, 604 insertions(+), 84 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 04ec73c4f9ed..6a2d21b555cc 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -814,8 +814,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, Custom); setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); - setOperationAction({ISD::AVGFLOORU, ISD::SADDSAT, ISD::UADDSAT, - ISD::SSUBSAT, ISD::USUBSAT}, + setOperationAction({ISD::AVGFLOORU, ISD::AVGCEILU, ISD::SADDSAT, + ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Legal); // Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR_VL" @@ -1185,8 +1185,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, if (VT.getVectorElementType() != MVT::i64 || Subtarget.hasStdExtV()) setOperationAction({ISD::MULHS, ISD::MULHU}, VT, Custom); - setOperationAction({ISD::AVGFLOORU, ISD::SADDSAT, ISD::UADDSAT, - ISD::SSUBSAT, ISD::USUBSAT}, + setOperationAction({ISD::AVGFLOORU, ISD::AVGCEILU, ISD::SADDSAT, + ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Custom); setOperationAction(ISD::VSELECT, VT, Custom); @@ -5466,6 +5466,7 @@ static unsigned getRISCVVLOp(SDValue Op) { OP_CASE(SSUBSAT) OP_CASE(USUBSAT) OP_CASE(AVGFLOORU) + OP_CASE(AVGCEILU) OP_CASE(FADD) OP_CASE(FSUB) OP_CASE(FMUL) @@ -5570,7 +5571,7 @@ static bool hasMergeOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 125 && + 126 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -5596,7 +5597,7 @@ static bool hasMaskOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 125 && + 126 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -6461,6 +6462,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, return SplitVectorOp(Op, DAG); [[fallthrough]]; case ISD::AVGFLOORU: + case ISD::AVGCEILU: case ISD::SADDSAT: case ISD::UADDSAT: case ISD::SSUBSAT: @@ -18595,6 +18597,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(UREM_VL) NODE_NAME_CASE(XOR_VL) NODE_NAME_CASE(AVGFLOORU_VL) + NODE_NAME_CASE(AVGCEILU_VL) NODE_NAME_CASE(SADDSAT_VL) NODE_NAME_CASE(UADDSAT_VL) NODE_NAME_CASE(SSUBSAT_VL) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 5d51fe168b04..0d14e5b757bd 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -255,6 +255,8 @@ enum NodeType : unsigned { // Averaging adds of unsigned integers. AVGFLOORU_VL, + // Rounding averaging adds of unsigned integers. + AVGCEILU_VL, MULHS_VL, MULHU_VL, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 4f87c36506e5..8ebd8b89c119 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -877,6 +877,23 @@ multiclass VPatMultiplyAddSDNode_VV_VX { } } +multiclass VPatAVGADD_VV_VX_RM { + foreach vti = AllIntegerVectors in { + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(vop (vti.Vector vti.RegClass:$rs1), + (vti.Vector vti.RegClass:$rs2)), + (!cast("PseudoVAADDU_VV_"#vti.LMul.MX) + (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs2, + vxrm, vti.AVL, vti.Log2SEW, TA_MA)>; + def : Pat<(vop (vti.Vector vti.RegClass:$rs1), + (vti.Vector (SplatPat (XLenVT GPR:$rs2)))), + (!cast("PseudoVAADDU_VX_"#vti.LMul.MX) + (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, + vxrm, vti.AVL, vti.Log2SEW, TA_MA)>; + } + } +} + //===----------------------------------------------------------------------===// // Patterns. //===----------------------------------------------------------------------===// @@ -1132,20 +1149,8 @@ defm : VPatBinarySDNode_VV_VX; defm : VPatBinarySDNode_VV_VX; // 12.2. Vector Single-Width Averaging Add and Subtract -foreach vti = AllIntegerVectors in { - let Predicates = GetVTypePredicates.Predicates in { - def : Pat<(avgflooru (vti.Vector vti.RegClass:$rs1), - (vti.Vector vti.RegClass:$rs2)), - (!cast("PseudoVAADDU_VV_"#vti.LMul.MX) - (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs2, - 0b10, vti.AVL, vti.Log2SEW, TA_MA)>; - def : Pat<(avgflooru (vti.Vector vti.RegClass:$rs1), - (vti.Vector (SplatPat (XLenVT GPR:$rs2)))), - (!cast("PseudoVAADDU_VX_"#vti.LMul.MX) - (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, - 0b10, vti.AVL, vti.Log2SEW, TA_MA)>; - } -} +defm : VPatAVGADD_VV_VX_RM; +defm : VPatAVGADD_VV_VX_RM; // 15. Vector Mask Instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index d60ff4b5fab0..1deb9a709463 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -112,6 +112,7 @@ def riscv_cttz_vl : SDNode<"RISCVISD::CTTZ_VL", SDT_RISCVIntUnOp_VL> def riscv_ctpop_vl : SDNode<"RISCVISD::CTPOP_VL", SDT_RISCVIntUnOp_VL>; def riscv_avgflooru_vl : SDNode<"RISCVISD::AVGFLOORU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; +def riscv_avgceilu_vl : SDNode<"RISCVISD::AVGCEILU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; @@ -2031,6 +2032,25 @@ multiclass VPatSlide1VL_VF { } } +multiclass VPatAVGADDVL_VV_VX_RM { + foreach vti = AllIntegerVectors in { + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(vop (vti.Vector vti.RegClass:$rs1), + (vti.Vector vti.RegClass:$rs2), + vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), + (!cast("PseudoVAADDU_VV_"#vti.LMul.MX#"_MASK") + vti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs2, + (vti.Mask V0), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(vop (vti.Vector vti.RegClass:$rs1), + (vti.Vector (SplatPat (XLenVT GPR:$rs2))), + vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), + (!cast("PseudoVAADDU_VX_"#vti.LMul.MX#"_MASK") + vti.RegClass:$merge, vti.RegClass:$rs1, GPR:$rs2, + (vti.Mask V0), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; + } + } +} + //===----------------------------------------------------------------------===// // Patterns. //===----------------------------------------------------------------------===// @@ -2308,22 +2328,8 @@ defm : VPatBinaryVL_VV_VX; defm : VPatBinaryVL_VV_VX; // 12.2. Vector Single-Width Averaging Add and Subtract -foreach vti = AllIntegerVectors in { - let Predicates = GetVTypePredicates.Predicates in { - def : Pat<(riscv_avgflooru_vl (vti.Vector vti.RegClass:$rs1), - (vti.Vector vti.RegClass:$rs2), - vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), - (!cast("PseudoVAADDU_VV_"#vti.LMul.MX#"_MASK") - vti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs2, - (vti.Mask V0), 0b10, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(riscv_avgflooru_vl (vti.Vector vti.RegClass:$rs1), - (vti.Vector (SplatPat (XLenVT GPR:$rs2))), - vti.RegClass:$merge, (vti.Mask V0), VLOpFrag), - (!cast("PseudoVAADDU_VX_"#vti.LMul.MX#"_MASK") - vti.RegClass:$merge, vti.RegClass:$rs1, GPR:$rs2, - (vti.Mask V0), 0b10, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; - } -} +defm : VPatAVGADDVL_VV_VX_RM; +defm : VPatAVGADDVL_VV_VX_RM; // 12.5. Vector Narrowing Fixed-Point Clip Instructions class VPatTruncSatClipMaxMinBase @vaaddu_vv_v8i8(<8 x i8> %x, <8 x i8> %y) { -; CHECK-LABEL: vaaddu_vv_v8i8: +define <8 x i8> @vaaddu_vv_v8i8_floor(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -17,8 +17,8 @@ define <8 x i8> @vaaddu_vv_v8i8(<8 x i8> %x, <8 x i8> %y) { ret <8 x i8> %ret } -define <8 x i8> @vaaddu_vx_v8i8(<8 x i8> %x, i8 %y) { -; CHECK-LABEL: vaaddu_vx_v8i8: +define <8 x i8> @vaaddu_vx_v8i8_floor(<8 x i8> %x, i8 %y) { +; CHECK-LABEL: vaaddu_vx_v8i8_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -37,8 +37,8 @@ define <8 x i8> @vaaddu_vx_v8i8(<8 x i8> %x, i8 %y) { } -define <8 x i8> @vaaddu_vv_v8i8_sexti16(<8 x i8> %x, <8 x i8> %y) { -; CHECK-LABEL: vaaddu_vv_v8i8_sexti16: +define <8 x i8> @vaaddu_vv_v8i8_floor_sexti16(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_floor_sexti16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vwadd.vv v10, v8, v9 @@ -52,8 +52,8 @@ define <8 x i8> @vaaddu_vv_v8i8_sexti16(<8 x i8> %x, <8 x i8> %y) { ret <8 x i8> %ret } -define <8 x i8> @vaaddu_vv_v8i8_zexti32(<8 x i8> %x, <8 x i8> %y) { -; CHECK-LABEL: vaaddu_vv_v8i8_zexti32: +define <8 x i8> @vaaddu_vv_v8i8_floor_zexti32(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_floor_zexti32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -67,8 +67,8 @@ define <8 x i8> @vaaddu_vv_v8i8_zexti32(<8 x i8> %x, <8 x i8> %y) { ret <8 x i8> %ret } -define <8 x i8> @vaaddu_vv_v8i8_lshr2(<8 x i8> %x, <8 x i8> %y) { -; CHECK-LABEL: vaaddu_vv_v8i8_lshr2: +define <8 x i8> @vaaddu_vv_v8i8_floor_lshr2(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_floor_lshr2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vwaddu.vv v10, v8, v9 @@ -82,8 +82,8 @@ define <8 x i8> @vaaddu_vv_v8i8_lshr2(<8 x i8> %x, <8 x i8> %y) { ret <8 x i8> %ret } -define <8 x i16> @vaaddu_vv_v8i16(<8 x i16> %x, <8 x i16> %y) { -; CHECK-LABEL: vaaddu_vv_v8i16: +define <8 x i16> @vaaddu_vv_v8i16_floor(<8 x i16> %x, <8 x i16> %y) { +; CHECK-LABEL: vaaddu_vv_v8i16_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -97,8 +97,8 @@ define <8 x i16> @vaaddu_vv_v8i16(<8 x i16> %x, <8 x i16> %y) { ret <8 x i16> %ret } -define <8 x i16> @vaaddu_vx_v8i16(<8 x i16> %x, i16 %y) { -; CHECK-LABEL: vaaddu_vx_v8i16: +define <8 x i16> @vaaddu_vx_v8i16_floor(<8 x i16> %x, i16 %y) { +; CHECK-LABEL: vaaddu_vx_v8i16_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -116,8 +116,8 @@ define <8 x i16> @vaaddu_vx_v8i16(<8 x i16> %x, i16 %y) { ret <8 x i16> %ret } -define <8 x i32> @vaaddu_vv_v8i32(<8 x i32> %x, <8 x i32> %y) { -; CHECK-LABEL: vaaddu_vv_v8i32: +define <8 x i32> @vaaddu_vv_v8i32_floor(<8 x i32> %x, <8 x i32> %y) { +; CHECK-LABEL: vaaddu_vv_v8i32_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -131,8 +131,8 @@ define <8 x i32> @vaaddu_vv_v8i32(<8 x i32> %x, <8 x i32> %y) { ret <8 x i32> %ret } -define <8 x i32> @vaaddu_vx_v8i32(<8 x i32> %x, i32 %y) { -; CHECK-LABEL: vaaddu_vx_v8i32: +define <8 x i32> @vaaddu_vx_v8i32_floor(<8 x i32> %x, i32 %y) { +; CHECK-LABEL: vaaddu_vx_v8i32_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -150,8 +150,8 @@ define <8 x i32> @vaaddu_vx_v8i32(<8 x i32> %x, i32 %y) { ret <8 x i32> %ret } -define <8 x i64> @vaaddu_vv_v8i64(<8 x i64> %x, <8 x i64> %y) { -; CHECK-LABEL: vaaddu_vv_v8i64: +define <8 x i64> @vaaddu_vv_v8i64_floor(<8 x i64> %x, <8 x i64> %y) { +; CHECK-LABEL: vaaddu_vv_v8i64_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -165,8 +165,8 @@ define <8 x i64> @vaaddu_vv_v8i64(<8 x i64> %x, <8 x i64> %y) { ret <8 x i64> %ret } -define <8 x i1> @vaaddu_vv_v8i1(<8 x i1> %x, <8 x i1> %y) { -; CHECK-LABEL: vaaddu_vv_v8i1: +define <8 x i1> @vaaddu_vv_v8i1_floor(<8 x i1> %x, <8 x i1> %y) { +; CHECK-LABEL: vaaddu_vv_v8i1_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 @@ -186,8 +186,8 @@ define <8 x i1> @vaaddu_vv_v8i1(<8 x i1> %x, <8 x i1> %y) { ret <8 x i1> %ret } -define <8 x i64> @vaaddu_vx_v8i64(<8 x i64> %x, i64 %y) { -; RV32-LABEL: vaaddu_vx_v8i64: +define <8 x i64> @vaaddu_vx_v8i64_floor(<8 x i64> %x, i64 %y) { +; RV32-LABEL: vaaddu_vx_v8i64_floor: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 @@ -201,7 +201,7 @@ define <8 x i64> @vaaddu_vx_v8i64(<8 x i64> %x, i64 %y) { ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; -; RV64-LABEL: vaaddu_vx_v8i64: +; RV64-LABEL: vaaddu_vx_v8i64_floor: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: csrwi vxrm, 2 @@ -218,3 +218,258 @@ define <8 x i64> @vaaddu_vx_v8i64(<8 x i64> %x, i64 %y) { %ret = trunc <8 x i128> %div to <8 x i64> ret <8 x i64> %ret } + +define <8 x i8> @vaaddu_vv_v8i8_ceil(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i16> + %yzv = zext <8 x i8> %y to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %add1 = add nuw nsw <8 x i16> %add, + %div = lshr <8 x i16> %add1, + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vx_v8i8_ceil(<8 x i8> %x, i8 %y) { +; CHECK-LABEL: vaaddu_vx_v8i8_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i16> + %yhead = insertelement <8 x i8> poison, i8 %y, i32 0 + %ysplat = shufflevector <8 x i8> %yhead, <8 x i8> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i8> %ysplat to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %add1 = add nuw nsw <8 x i16> %add, + %one = insertelement <8 x i16> poison, i16 1, i32 0 + %splat = shufflevector <8 x i16> %one, <8 x i16> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i16> %add1, %splat + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vv_v8i8_ceil_sexti16(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_ceil_sexti16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9 +; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma +; CHECK-NEXT: vadd.vi v8, v10, 1 +; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma +; CHECK-NEXT: vnsrl.wi v8, v8, 1 +; CHECK-NEXT: ret + %xzv = sext <8 x i8> %x to <8 x i16> + %yzv = sext <8 x i8> %y to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %add1 = add nuw nsw <8 x i16> %add, + %div = lshr <8 x i16> %add1, + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vv_v8i8_ceil_zexti32(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_ceil_zexti32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i32> + %yzv = zext <8 x i8> %y to <8 x i32> + %add = add nuw nsw <8 x i32> %xzv, %yzv + %add1 = add nuw nsw <8 x i32> %add, + %div = lshr <8 x i32> %add1, + %ret = trunc <8 x i32> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vv_v8i8_ceil_lshr2(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_ceil_lshr2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9 +; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma +; CHECK-NEXT: vadd.vi v8, v10, 2 +; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma +; CHECK-NEXT: vnsrl.wi v8, v8, 2 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i16> + %yzv = zext <8 x i8> %y to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %add1 = add nuw nsw <8 x i16> %add, + %div = lshr <8 x i16> %add1, + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i8> @vaaddu_vv_v8i8_ceil_add2(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: vaaddu_vv_v8i8_ceil_add2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vaaddu.vx v8, v10, a0 +; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: ret + %xzv = zext <8 x i8> %x to <8 x i16> + %yzv = zext <8 x i8> %y to <8 x i16> + %add = add nuw nsw <8 x i16> %xzv, %yzv + %add1 = add nuw nsw <8 x i16> %add, + %div = lshr <8 x i16> %add1, + %ret = trunc <8 x i16> %div to <8 x i8> + ret <8 x i8> %ret +} + +define <8 x i16> @vaaddu_vv_v8i16_ceil(<8 x i16> %x, <8 x i16> %y) { +; CHECK-LABEL: vaaddu_vv_v8i16_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext <8 x i16> %x to <8 x i32> + %yzv = zext <8 x i16> %y to <8 x i32> + %add = add nuw nsw <8 x i32> %xzv, %yzv + %add1 = add nuw nsw <8 x i32> %add, + %div = lshr <8 x i32> %add1, + %ret = trunc <8 x i32> %div to <8 x i16> + ret <8 x i16> %ret +} + +define <8 x i16> @vaaddu_vx_v8i16_ceil(<8 x i16> %x, i16 %y) { +; CHECK-LABEL: vaaddu_vx_v8i16_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext <8 x i16> %x to <8 x i32> + %yhead = insertelement <8 x i16> poison, i16 %y, i16 0 + %ysplat = shufflevector <8 x i16> %yhead, <8 x i16> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i16> %ysplat to <8 x i32> + %add = add nuw nsw <8 x i32> %xzv, %yzv + %add1 = add nuw nsw <8 x i32> %add, + %one = insertelement <8 x i32> poison, i32 1, i32 0 + %splat = shufflevector <8 x i32> %one, <8 x i32> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i32> %add1, %splat + %ret = trunc <8 x i32> %div to <8 x i16> + ret <8 x i16> %ret +} + +define <8 x i32> @vaaddu_vv_v8i32_ceil(<8 x i32> %x, <8 x i32> %y) { +; CHECK-LABEL: vaaddu_vv_v8i32_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: ret + %xzv = zext <8 x i32> %x to <8 x i64> + %yzv = zext <8 x i32> %y to <8 x i64> + %add = add nuw nsw <8 x i64> %xzv, %yzv + %add1 = add nuw nsw <8 x i64> %add, + %div = lshr <8 x i64> %add1, + %ret = trunc <8 x i64> %div to <8 x i32> + ret <8 x i32> %ret +} + +define <8 x i32> @vaaddu_vx_v8i32_ceil(<8 x i32> %x, i32 %y) { +; CHECK-LABEL: vaaddu_vx_v8i32_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext <8 x i32> %x to <8 x i64> + %yhead = insertelement <8 x i32> poison, i32 %y, i32 0 + %ysplat = shufflevector <8 x i32> %yhead, <8 x i32> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i32> %ysplat to <8 x i64> + %add = add nuw nsw <8 x i64> %xzv, %yzv + %add1 = add nuw nsw <8 x i64> %add, + %one = insertelement <8 x i64> poison, i64 1, i64 0 + %splat = shufflevector <8 x i64> %one, <8 x i64> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i64> %add1, %splat + %ret = trunc <8 x i64> %div to <8 x i32> + ret <8 x i32> %ret +} + +define <8 x i64> @vaaddu_vv_v8i64_ceil(<8 x i64> %x, <8 x i64> %y) { +; CHECK-LABEL: vaaddu_vv_v8i64_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: ret + %xzv = zext <8 x i64> %x to <8 x i128> + %yzv = zext <8 x i64> %y to <8 x i128> + %add = add nuw nsw <8 x i128> %xzv, %yzv + %add1 = add nuw nsw <8 x i128> %add, + %div = lshr <8 x i128> %add1, + %ret = trunc <8 x i128> %div to <8 x i64> + ret <8 x i64> %ret +} + +define <8 x i1> @vaaddu_vv_v8i1_ceil(<8 x i1> %x, <8 x i1> %y) { +; CHECK-LABEL: vaaddu_vv_v8i1_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v10, v8 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: ret + %xzv = zext <8 x i1> %x to <8 x i8> + %yzv = zext <8 x i1> %y to <8 x i8> + %add = add nuw nsw <8 x i8> %xzv, %yzv + %add1 = add nuw nsw <8 x i8> %add, + %div = lshr <8 x i8> %add1, + %ret = trunc <8 x i8> %div to <8 x i1> + ret <8 x i1> %ret +} + +define <8 x i64> @vaaddu_vx_v8i64_ceil(<8 x i64> %x, i64 %y) { +; RV32-LABEL: vaaddu_vx_v8i64_ceil: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: csrwi vxrm, 0 +; RV32-NEXT: vaaddu.vv v8, v8, v12 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vaaddu_vx_v8i64_ceil: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; RV64-NEXT: csrwi vxrm, 0 +; RV64-NEXT: vaaddu.vx v8, v8, a0 +; RV64-NEXT: ret + %xzv = zext <8 x i64> %x to <8 x i128> + %yhead = insertelement <8 x i64> poison, i64 %y, i64 0 + %ysplat = shufflevector <8 x i64> %yhead, <8 x i64> poison, <8 x i32> zeroinitializer + %yzv = zext <8 x i64> %ysplat to <8 x i128> + %add = add nuw nsw <8 x i128> %xzv, %yzv + %add1 = add nuw nsw <8 x i128> %add, + %one = insertelement <8 x i128> poison, i128 1, i128 0 + %splat = shufflevector <8 x i128> %one, <8 x i128> poison, <8 x i32> zeroinitializer + %div = lshr <8 x i128> %add1, %splat + %ret = trunc <8 x i128> %div to <8 x i64> + ret <8 x i64> %ret +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll index 883d605e77e2..1cf57371455c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll @@ -2,8 +2,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -define @vaaddu_vv_nxv8i8( %x, %y) { -; CHECK-LABEL: vaaddu_vv_nxv8i8: +define @vaaddu_vv_nxv8i8_floor( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -19,8 +19,8 @@ define @vaaddu_vv_nxv8i8( %x, %ret } -define @vaaddu_vx_nxv8i8( %x, i8 %y) { -; CHECK-LABEL: vaaddu_vx_nxv8i8: +define @vaaddu_vx_nxv8i8_floor( %x, i8 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i8_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -38,8 +38,8 @@ define @vaaddu_vx_nxv8i8( %x, i8 %y) { ret %ret } -define @vaaddu_vv_nxv8i8_sexti16( %x, %y) { -; CHECK-LABEL: vaaddu_vv_nxv8i8_sexti16: +define @vaaddu_vv_nxv8i8_floor_sexti16( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_sexti16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vwadd.vv v10, v8, v9 @@ -55,8 +55,8 @@ define @vaaddu_vv_nxv8i8_sexti16( %x, %ret } -define @vaaddu_vv_nxv8i8_zexti32( %x, %y) { -; CHECK-LABEL: vaaddu_vv_nxv8i8_zexti32: +define @vaaddu_vv_nxv8i8_floor_zexti32( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_zexti32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -72,8 +72,8 @@ define @vaaddu_vv_nxv8i8_zexti32( %x, %ret } -define @vaaddu_vv_nxv8i8_lshr2( %x, %y) { -; CHECK-LABEL: vaaddu_vv_nxv8i8_lshr2: +define @vaaddu_vv_nxv8i8_floor_lshr2( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_lshr2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vwaddu.vv v10, v8, v9 @@ -89,8 +89,8 @@ define @vaaddu_vv_nxv8i8_lshr2( %x, %ret } -define @vaaddu_vv_nxv8i16( %x, %y) { -; CHECK-LABEL: vaaddu_vv_nxv8i16: +define @vaaddu_vv_nxv8i16_floor( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i16_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -106,8 +106,8 @@ define @vaaddu_vv_nxv8i16( %x, %ret } -define @vaaddu_vx_nxv8i16( %x, i16 %y) { -; CHECK-LABEL: vaaddu_vx_nxv8i16: +define @vaaddu_vx_nxv8i16_floor( %x, i16 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i16_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -125,8 +125,8 @@ define @vaaddu_vx_nxv8i16( %x, i16 %y) { ret %ret } -define @vaaddu_vv_nxv8i32( %x, %y) { -; CHECK-LABEL: vaaddu_vv_nxv8i32: +define @vaaddu_vv_nxv8i32_floor( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i32_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -142,8 +142,8 @@ define @vaaddu_vv_nxv8i32( %x, %ret } -define @vaaddu_vx_nxv8i32( %x, i32 %y) { -; CHECK-LABEL: vaaddu_vx_nxv8i32: +define @vaaddu_vx_nxv8i32_floor( %x, i32 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i32_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -161,8 +161,8 @@ define @vaaddu_vx_nxv8i32( %x, i32 %y) { ret %ret } -define @vaaddu_vv_nxv8i64( %x, %y) { -; CHECK-LABEL: vaaddu_vv_nxv8i64: +define @vaaddu_vv_nxv8i64_floor( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i64_floor: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 @@ -178,8 +178,8 @@ define @vaaddu_vv_nxv8i64( %x, %ret } -define @vaaddu_vx_nxv8i64( %x, i64 %y) { -; RV32-LABEL: vaaddu_vx_nxv8i64: +define @vaaddu_vx_nxv8i64_floor( %x, i64 %y) { +; RV32-LABEL: vaaddu_vx_nxv8i64_floor: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 @@ -193,7 +193,7 @@ define @vaaddu_vx_nxv8i64( %x, i64 %y) { ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; -; RV64-LABEL: vaaddu_vx_nxv8i64: +; RV64-LABEL: vaaddu_vx_nxv8i64_floor: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: csrwi vxrm, 2 @@ -210,3 +210,252 @@ define @vaaddu_vx_nxv8i64( %x, i64 %y) { %ret = trunc %div to ret %ret } + +define @vaaddu_vv_nxv8i8_ceil( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i8_ceil( %x, i8 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i8_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i8 %y, i32 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i8_ceil_sexti16( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_sexti16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9 +; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; CHECK-NEXT: vadd.vi v10, v10, 1 +; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; CHECK-NEXT: vnsrl.wi v8, v10, 1 +; CHECK-NEXT: ret + %xzv = sext %x to + %yzv = sext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i8_ceil_zexti32( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_zexti32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i32 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i8_ceil_lshr2( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_lshr2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9 +; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; CHECK-NEXT: vadd.vi v10, v10, 2 +; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; CHECK-NEXT: vnsrl.wi v8, v10, 2 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 2, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i8_ceil_add2( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_add2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9 +; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; CHECK-NEXT: vadd.vi v10, v10, 2 +; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; CHECK-NEXT: vnsrl.wi v8, v10, 2 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i16 2, i32 0 + %splat1 = shufflevector %one, poison, zeroinitializer + %two = insertelement poison, i16 2, i32 0 + %splat2 = shufflevector %two, poison, zeroinitializer + %add2 = add nuw nsw %add, %splat2 + %div = lshr %add2, %splat1 + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i16_ceil( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i16_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i32 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i16_ceil( %x, i16 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i16_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i16 %y, i16 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i32 1, i32 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i32_ceil( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i32_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i64 1, i64 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i32_ceil( %x, i32 %y) { +; CHECK-LABEL: vaaddu_vx_nxv8i32_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i32 %y, i32 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i64 1, i64 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vv_nxv8i64_ceil( %x, %y) { +; CHECK-LABEL: vaaddu_vv_nxv8i64_ceil: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: ret + %xzv = zext %x to + %yzv = zext %y to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i128 1, i128 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} + +define @vaaddu_vx_nxv8i64_ceil( %x, i64 %y) { +; RV32-LABEL: vaaddu_vx_nxv8i64_ceil: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: csrwi vxrm, 0 +; RV32-NEXT: vaaddu.vv v8, v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vaaddu_vx_nxv8i64_ceil: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV64-NEXT: csrwi vxrm, 0 +; RV64-NEXT: vaaddu.vx v8, v8, a0 +; RV64-NEXT: ret + %xzv = zext %x to + %yhead = insertelement poison, i64 %y, i64 0 + %ysplat = shufflevector %yhead, poison, zeroinitializer + %yzv = zext %ysplat to + %add = add nuw nsw %xzv, %yzv + %one = insertelement poison, i128 1, i128 0 + %splat = shufflevector %one, poison, zeroinitializer + %add1 = add nuw nsw %add, %splat + %div = lshr %add1, %splat + %ret = trunc %div to + ret %ret +} -- GitLab From a9f39ff2b628e38826d5b95c1e8ae3cb7c692de9 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 9 Jan 2024 19:38:02 -0800 Subject: [PATCH 285/652] [RISCV] Reorder RISCVInstrInfoA.td. NFC (#77539) Move classes out of `let Predicates` scopes. The instantiation of the class should be responsible for providing the Predicates. Put the RV64 pseudoinstructions and patterns next to the RV32 version of the same category. The categories are AMOs, pseudo AMOs, and compare exchange. The main reason for this commit is that the compare exchange patterns need to be disabled when Zacas is enabled so we can directly select Zacas instructions with isel patterns. This necessitates compare exchange having a different `let Predicates=` from the others anyway. --- llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 130 ++++++++++++----------- 1 file changed, 67 insertions(+), 63 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index 4d0567e41abc..1ff5189260a9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -157,7 +157,16 @@ defm : AMOPat<"atomic_load_min_32", "AMOMIN_W">; defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">; defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">; -let Predicates = [HasStdExtA] in { +defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_add_64", "AMOADD_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_and_64", "AMOAND_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_max_64", "AMOMAX_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_min_64", "AMOMIN_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D", i64, [IsRV64]>; +defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D", i64, [IsRV64]>; + /// Pseudo AMOs @@ -169,21 +178,6 @@ class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch), let hasSideEffects = 0; } -let Size = 20 in -def PseudoAtomicLoadNand32 : PseudoAMO; -// Ordering constants must be kept in sync with the AtomicOrdering enum in -// AtomicOrdering.h. -def : Pat<(XLenVT (atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>; -def : Pat<(XLenVT (atomic_load_nand_32_acquire GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>; -def : Pat<(XLenVT (atomic_load_nand_32_release GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>; -def : Pat<(XLenVT (atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>; -def : Pat<(XLenVT (atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>; - class PseudoMaskedAMO : Pseudo<(outs GPR:$res, GPR:$scratch), (ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> { @@ -224,6 +218,23 @@ class PseudoMaskedAMOMinMaxPat (AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt, timm:$ordering)>; +let Predicates = [HasStdExtA] in { + +let Size = 20 in +def PseudoAtomicLoadNand32 : PseudoAMO; +// Ordering constants must be kept in sync with the AtomicOrdering enum in +// AtomicOrdering.h. +def : Pat<(XLenVT (atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>; +def : Pat<(XLenVT (atomic_load_nand_32_acquire GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>; +def : Pat<(XLenVT (atomic_load_nand_32_release GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>; +def : Pat<(XLenVT (atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>; +def : Pat<(XLenVT (atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>; + let Size = 28 in def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO; def : PseudoMaskedAMOPat; +} // Predicates = [HasStdExtA] + +let Predicates = [HasStdExtA, IsRV64] in { + +let Size = 20 in +def PseudoAtomicLoadNand64 : PseudoAMO; +// Ordering constants must be kept in sync with the AtomicOrdering enum in +// AtomicOrdering.h. +def : Pat<(i64 (atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>; +def : Pat<(i64 (atomic_load_nand_64_acquire GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>; +def : Pat<(i64 (atomic_load_nand_64_release GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>; +def : Pat<(i64 (atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>; +def : Pat<(i64 (atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr)), + (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>; + +def : PseudoMaskedAMOPat; +def : PseudoMaskedAMOPat; +def : PseudoMaskedAMOPat; +def : PseudoMaskedAMOPat; +def : PseudoMaskedAMOMinMaxPat; +def : PseudoMaskedAMOMinMaxPat; +def : PseudoMaskedAMOPat; +def : PseudoMaskedAMOPat; +} // Predicates = [HasStdExtA, IsRV64] + /// Compare and exchange @@ -285,6 +333,8 @@ multiclass PseudoCmpXchgPat; } +let Predicates = [HasStdExtA] in { + def PseudoCmpXchg32 : PseudoCmpXchg; defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32>; @@ -303,57 +353,10 @@ def : Pat<(int_riscv_masked_cmpxchg_i32 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering), (PseudoMaskedCmpXchg32 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>; - } // Predicates = [HasStdExtA] -defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_add_64", "AMOADD_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_and_64", "AMOAND_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_max_64", "AMOMAX_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_min_64", "AMOMIN_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D", i64, [IsRV64]>; -defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D", i64, [IsRV64]>; - let Predicates = [HasStdExtA, IsRV64] in { -/// 64-bit pseudo AMOs - -let Size = 20 in -def PseudoAtomicLoadNand64 : PseudoAMO; -// Ordering constants must be kept in sync with the AtomicOrdering enum in -// AtomicOrdering.h. -def : Pat<(i64 (atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>; -def : Pat<(i64 (atomic_load_nand_64_acquire GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>; -def : Pat<(i64 (atomic_load_nand_64_release GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>; -def : Pat<(i64 (atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>; -def : Pat<(i64 (atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr)), - (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>; - -def : PseudoMaskedAMOPat; -def : PseudoMaskedAMOPat; -def : PseudoMaskedAMOPat; -def : PseudoMaskedAMOPat; -def : PseudoMaskedAMOMinMaxPat; -def : PseudoMaskedAMOMinMaxPat; -def : PseudoMaskedAMOPat; -def : PseudoMaskedAMOPat; - -/// 64-bit compare and exchange - def PseudoCmpXchg64 : PseudoCmpXchg; defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64, i64>; @@ -408,6 +411,7 @@ defm : AMOPat2<"atomic_load_min_32", "AMOMIN_W", i32>; defm : AMOPat2<"atomic_load_umax_32", "AMOMAXU_W", i32>; defm : AMOPat2<"atomic_load_umin_32", "AMOMINU_W", i32>; +let Predicates = [HasStdExtA, IsRV64] in defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32, i32>; let Predicates = [HasAtomicLdSt] in { -- GitLab From e42a70afab47a7a9e76a40bb553eee458a5f18ae Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Wed, 8 Nov 2023 19:22:21 -0500 Subject: [PATCH 286/652] [RISCV][GISel] IRTranslate and Legalize some instructions with scalable vector type * Add IRTranslate tests for ADD, SUB, AND, OR, and XOR with scalable vector types to show that they work as expected. * Legalize G_ADD, G_SUB, G_AND, G_OR, and G_XOR of scalable vector type for the RISC-V vector extension. --- .../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 40 ++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 +- .../RISCV/GlobalISel/irtranslator/vec-alu.ll | 53 +++ .../legalizer/rvv/legalize-add-zve32x.mir | 274 ++++++++++++ .../GlobalISel/legalizer/rvv/legalize-add.mir | 399 ++++++++++++++++++ .../GlobalISel/legalizer/rvv/legalize-and.mir | 399 ++++++++++++++++++ .../GlobalISel/legalizer/rvv/legalize-or.mir | 399 ++++++++++++++++++ .../GlobalISel/legalizer/rvv/legalize-sub.mir | 399 ++++++++++++++++++ .../GlobalISel/legalizer/rvv/legalize-xor.mir | 399 ++++++++++++++++++ 9 files changed, 2369 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp index ab8070772fe5..ae02e86baf6e 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -47,10 +47,50 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); + const LLT nxv1s8 = LLT::scalable_vector(1, s8); + const LLT nxv2s8 = LLT::scalable_vector(2, s8); + const LLT nxv4s8 = LLT::scalable_vector(4, s8); + const LLT nxv8s8 = LLT::scalable_vector(8, s8); + const LLT nxv16s8 = LLT::scalable_vector(16, s8); + const LLT nxv32s8 = LLT::scalable_vector(32, s8); + const LLT nxv64s8 = LLT::scalable_vector(64, s8); + + const LLT nxv1s16 = LLT::scalable_vector(1, s16); + const LLT nxv2s16 = LLT::scalable_vector(2, s16); + const LLT nxv4s16 = LLT::scalable_vector(4, s16); + const LLT nxv8s16 = LLT::scalable_vector(8, s16); + const LLT nxv16s16 = LLT::scalable_vector(16, s16); + const LLT nxv32s16 = LLT::scalable_vector(32, s16); + + const LLT nxv1s32 = LLT::scalable_vector(1, s32); + const LLT nxv2s32 = LLT::scalable_vector(2, s32); + const LLT nxv4s32 = LLT::scalable_vector(4, s32); + const LLT nxv8s32 = LLT::scalable_vector(8, s32); + const LLT nxv16s32 = LLT::scalable_vector(16, s32); + + const LLT nxv1s64 = LLT::scalable_vector(1, s64); + const LLT nxv2s64 = LLT::scalable_vector(2, s64); + const LLT nxv4s64 = LLT::scalable_vector(4, s64); + const LLT nxv8s64 = LLT::scalable_vector(8, s64); + using namespace TargetOpcode; + auto AllVecTys = {nxv1s8, nxv2s8, nxv4s8, nxv8s8, nxv16s8, nxv32s8, + nxv64s8, nxv1s16, nxv2s16, nxv4s16, nxv8s16, nxv16s16, + nxv32s16, nxv1s32, nxv2s32, nxv4s32, nxv8s32, nxv16s32, + nxv1s64, nxv2s64, nxv4s64, nxv8s64}; + getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR}) .legalFor({s32, sXLen}) + .legalIf(all( + typeInSet(0, AllVecTys), + LegalityPredicate([=, &ST](const LegalityQuery &Query) { + return ST.hasVInstructions() && + (Query.Types[0].getScalarSizeInBits() != 64 || + ST.hasVInstructionsI64()) && + (Query.Types[0].getElementCount().getKnownMinValue() != 1 || + ST.getELen() == 64); + }))) .widenScalarToNextPow2(0) .clampScalar(0, s32, sXLen); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 6a2d21b555cc..90d648dab2ae 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -20019,8 +20019,13 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT, } bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const { - // At the moment, the only scalable instruction GISel knows how to lower is - // ret with scalable argument. + + // GISel support is in progress or complete for G_ADD, G_SUB, G_AND, G_OR, and + // G_XOR. + unsigned Op = Inst.getOpcode(); + if (Op == Instruction::Add || Op == Instruction::Sub || + Op == Instruction::And || Op == Instruction::Or || Op == Instruction::Xor) + return false; if (Inst.getType()->isScalableTy()) return true; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll new file mode 100644 index 000000000000..f5e81718226c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll @@ -0,0 +1,53 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK,RV32I +; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK,RV64I + +define void @add_nxv2i32( %a, %b) { + ; CHECK-LABEL: name: add_nxv2i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoRET + %c = add %a, %b + ret void +} + +define void @sub_nxv2i32( %a, %b) { + ; CHECK-LABEL: name: sub_nxv2i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoRET + %c = sub %a, %b + ret void +} + +define void @and_nxv2i32( %a, %b) { + ; CHECK-LABEL: name: and_nxv2i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoRET + %c = and %a, %b + ret void +} + +define void @or_nxv2i32( %a, %b) { + ; CHECK-LABEL: name: or_nxv2i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoRET + %c = or %a, %b + ret void +} + +define void @xor_nxv2i32( %a, %b) { + ; CHECK-LABEL: name: xor_nxv2i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoRET + %c = xor %a, %b + ret void +} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir new file mode 100644 index 000000000000..85ad899a5a91 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir @@ -0,0 +1,274 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zve32x -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zve32x -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... + diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir new file mode 100644 index 000000000000..aa0ab96f8ded --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir new file mode 100644 index 000000000000..8295e55c079c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir new file mode 100644 index 000000000000..22c2258f2b92 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir new file mode 100644 index 000000000000..eb961b8aa303 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir new file mode 100644 index 000000000000..4de02b1a04da --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... -- GitLab From b53628a52d1947c51e250d6fa4ff5dd12b737aa0 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Wed, 3 Jan 2024 21:12:28 -0800 Subject: [PATCH 287/652] Reland "[clang-format] Optimize processing .clang-format-ignore files" (42ec976184ac was reverted by 26993f61673e due to a use-after-scope bug.) Reuse the patterns governing the previous input file being formatted if the current input file is from the same directory. --- clang/docs/ClangFormat.rst | 6 ++- clang/test/Format/clang-format-ignore.cpp | 25 ++++++--- clang/tools/clang-format/ClangFormat.cpp | 65 ++++++++++++++++------- 3 files changed, 69 insertions(+), 27 deletions(-) diff --git a/clang/docs/ClangFormat.rst b/clang/docs/ClangFormat.rst index 8d4017b29fb8..819d9ee9f9cd 100644 --- a/clang/docs/ClangFormat.rst +++ b/clang/docs/ClangFormat.rst @@ -131,6 +131,9 @@ An easy way to create the ``.clang-format`` file is: Available style options are described in :doc:`ClangFormatStyleOptions`. +.clang-format-ignore +==================== + You can create ``.clang-format-ignore`` files to make ``clang-format`` ignore certain files. A ``.clang-format-ignore`` file consists of patterns of file path names. It has the following format: @@ -141,7 +144,8 @@ names. It has the following format: * A non-comment line is a single pattern. * The slash (``/``) is used as the directory separator. * A pattern is relative to the directory of the ``.clang-format-ignore`` file - (or the root directory if the pattern starts with a slash). + (or the root directory if the pattern starts with a slash). Patterns + containing drive names (e.g. ``C:``) are not supported. * Patterns follow the rules specified in `POSIX 2.13.1, 2.13.2, and Rule 1 of 2.13.3 `_. diff --git a/clang/test/Format/clang-format-ignore.cpp b/clang/test/Format/clang-format-ignore.cpp index 0d6396a64a66..5a2267b302d2 100644 --- a/clang/test/Format/clang-format-ignore.cpp +++ b/clang/test/Format/clang-format-ignore.cpp @@ -21,13 +21,26 @@ // RUN: touch .clang-format-ignore // RUN: clang-format -verbose foo.c foo.js 2> %t.stderr -// RUN: grep "Formatting \[1/2] foo.c" %t.stderr -// RUN: grep "Formatting \[2/2] foo.js" %t.stderr +// RUN: grep -Fx "Formatting [1/2] foo.c" %t.stderr +// RUN: grep -Fx "Formatting [2/2] foo.js" %t.stderr // RUN: echo "*.js" > .clang-format-ignore // RUN: clang-format -verbose foo.c foo.js 2> %t.stderr -// RUN: grep "Formatting \[1/2] foo.c" %t.stderr -// RUN: not grep "Formatting \[2/2] foo.js" %t.stderr +// RUN: grep -Fx "Formatting [1/2] foo.c" %t.stderr +// RUN: not grep -F foo.js %t.stderr -// RUN: cd ../../.. -// RUN: rm -rf %t.dir +// RUN: cd ../.. +// RUN: clang-format -verbose *.cc level1/*.c* level1/level2/foo.* 2> %t.stderr +// RUN: grep -x "Formatting \[1/5] .*foo\.c" %t.stderr +// RUN: not grep -F foo.js %t.stderr + +// RUN: rm .clang-format-ignore +// RUN: clang-format -verbose *.cc level1/*.c* level1/level2/foo.* 2> %t.stderr +// RUN: grep -x "Formatting \[1/5] .*foo\.cc" %t.stderr +// RUN: grep -x "Formatting \[2/5] .*bar\.cc" %t.stderr +// RUN: grep -x "Formatting \[3/5] .*baz\.c" %t.stderr +// RUN: grep -x "Formatting \[4/5] .*foo\.c" %t.stderr +// RUN: not grep -F foo.js %t.stderr + +// RUN: cd .. +// RUN: rm -r %t.dir diff --git a/clang/tools/clang-format/ClangFormat.cpp b/clang/tools/clang-format/ClangFormat.cpp index be34dbbe886a..49ab7677a3ee 100644 --- a/clang/tools/clang-format/ClangFormat.cpp +++ b/clang/tools/clang-format/ClangFormat.cpp @@ -571,6 +571,11 @@ static int dumpConfig(bool IsSTDIN) { return 0; } +using String = SmallString<128>; +static String IgnoreDir; // Directory of .clang-format-ignore file. +static String PrevDir; // Directory of previous `FilePath`. +static SmallVector Patterns; // Patterns in .clang-format-ignore file. + // Check whether `FilePath` is ignored according to the nearest // .clang-format-ignore file based on the rules below: // - A blank line is skipped. @@ -586,33 +591,50 @@ static bool isIgnored(StringRef FilePath) { if (!is_regular_file(FilePath)) return false; - using namespace llvm::sys::path; - SmallString<128> Path, AbsPath{FilePath}; + String Path; + String AbsPath{FilePath}; + using namespace llvm::sys::path; make_absolute(AbsPath); remove_dots(AbsPath, /*remove_dot_dot=*/true); - StringRef IgnoreDir{AbsPath}; - do { - IgnoreDir = parent_path(IgnoreDir); - if (IgnoreDir.empty()) + if (StringRef Dir{parent_path(AbsPath)}; PrevDir != Dir) { + PrevDir = Dir; + + for (;;) { + Path = Dir; + append(Path, ".clang-format-ignore"); + if (is_regular_file(Path)) + break; + Dir = parent_path(Dir); + if (Dir.empty()) + return false; + } + + IgnoreDir = convert_to_slash(Dir); + + std::ifstream IgnoreFile{Path.c_str()}; + if (!IgnoreFile.good()) return false; - Path = IgnoreDir; - append(Path, ".clang-format-ignore"); - } while (!is_regular_file(Path)); + Patterns.clear(); - std::ifstream IgnoreFile{Path.c_str()}; - if (!IgnoreFile.good()) - return false; + for (std::string Line; std::getline(IgnoreFile, Line);) { + if (const auto Pattern{StringRef{Line}.trim()}; + // Skip empty and comment lines. + !Pattern.empty() && Pattern[0] != '#') { + Patterns.push_back(Pattern); + } + } + } - const auto Pathname = convert_to_slash(AbsPath); - for (std::string Line; std::getline(IgnoreFile, Line);) { - auto Pattern = StringRef(Line).trim(); - if (Pattern.empty() || Pattern[0] == '#') - continue; + if (IgnoreDir.empty()) + return false; - const bool IsNegated = Pattern[0] == '!'; + const auto Pathname{convert_to_slash(AbsPath)}; + for (const auto &Pat : Patterns) { + const bool IsNegated = Pat[0] == '!'; + StringRef Pattern{Pat}; if (IsNegated) Pattern = Pattern.drop_front(); @@ -620,11 +642,14 @@ static bool isIgnored(StringRef FilePath) { continue; Pattern = Pattern.ltrim(); + + // `Pattern` is relative to `IgnoreDir` unless it starts with a slash. + // This doesn't support patterns containing drive names (e.g. `C:`). if (Pattern[0] != '/') { - Path = convert_to_slash(IgnoreDir); + Path = IgnoreDir; append(Path, Style::posix, Pattern); remove_dots(Path, /*remove_dot_dot=*/true, Style::posix); - Pattern = Path.str(); + Pattern = Path; } if (clang::format::matchFilePath(Pattern, Pathname) == !IsNegated) -- GitLab From c2b57a052daee22cb6401bc7bc514d858ea11eb6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Wed, 10 Jan 2024 06:36:48 +0100 Subject: [PATCH 288/652] [clang][Interp][NFC] Make a few pointers const --- clang/lib/AST/Interp/Descriptor.cpp | 6 +++--- clang/lib/AST/Interp/Descriptor.h | 7 ++++--- clang/lib/AST/Interp/Program.cpp | 16 ++++++++-------- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/clang/lib/AST/Interp/Descriptor.cpp b/clang/lib/AST/Interp/Descriptor.cpp index 59a952135a2d..b330e54baf33 100644 --- a/clang/lib/AST/Interp/Descriptor.cpp +++ b/clang/lib/AST/Interp/Descriptor.cpp @@ -275,8 +275,8 @@ Descriptor::Descriptor(const DeclTy &D, const Descriptor *Elem, MetadataSize MD, } /// Unknown-size arrays of composite elements. -Descriptor::Descriptor(const DeclTy &D, Descriptor *Elem, bool IsTemporary, - UnknownSize) +Descriptor::Descriptor(const DeclTy &D, const Descriptor *Elem, + bool IsTemporary, UnknownSize) : Source(D), ElemSize(Elem->getAllocSize() + sizeof(InlineDescriptor)), Size(UnknownSizeMark), MDSize(0), AllocSize(alignof(void *) + sizeof(InitMapPtr)), ElemDesc(Elem), @@ -286,7 +286,7 @@ Descriptor::Descriptor(const DeclTy &D, Descriptor *Elem, bool IsTemporary, } /// Composite records. -Descriptor::Descriptor(const DeclTy &D, Record *R, MetadataSize MD, +Descriptor::Descriptor(const DeclTy &D, const Record *R, MetadataSize MD, bool IsConst, bool IsTemporary, bool IsMutable) : Source(D), ElemSize(std::max(alignof(void *), R->getFullSize())), Size(ElemSize), MDSize(MD.value_or(0)), AllocSize(Size + MDSize), diff --git a/clang/lib/AST/Interp/Descriptor.h b/clang/lib/AST/Interp/Descriptor.h index 8135f3d12f70..580c200f9095 100644 --- a/clang/lib/AST/Interp/Descriptor.h +++ b/clang/lib/AST/Interp/Descriptor.h @@ -100,7 +100,7 @@ public: static constexpr MetadataSize InlineDescMD = sizeof(InlineDescriptor); /// Pointer to the record, if block contains records. - Record *const ElemRecord = nullptr; + const Record *const ElemRecord = nullptr; /// Descriptor of the array element. const Descriptor *const ElemDesc = nullptr; /// Flag indicating if the block is mutable. @@ -135,10 +135,11 @@ public: unsigned NumElems, bool IsConst, bool IsTemporary, bool IsMutable); /// Allocates a descriptor for an array of composites of unknown size. - Descriptor(const DeclTy &D, Descriptor *Elem, bool IsTemporary, UnknownSize); + Descriptor(const DeclTy &D, const Descriptor *Elem, bool IsTemporary, + UnknownSize); /// Allocates a descriptor for a record. - Descriptor(const DeclTy &D, Record *R, MetadataSize MD, bool IsConst, + Descriptor(const DeclTy &D, const Record *R, MetadataSize MD, bool IsConst, bool IsTemporary, bool IsMutable); Descriptor(const DeclTy &D, MetadataSize MD); diff --git a/clang/lib/AST/Interp/Program.cpp b/clang/lib/AST/Interp/Program.cpp index 52e13398163e..1daefab4dcda 100644 --- a/clang/lib/AST/Interp/Program.cpp +++ b/clang/lib/AST/Interp/Program.cpp @@ -315,14 +315,14 @@ Descriptor *Program::createDescriptor(const DeclTy &D, const Type *Ty, bool IsConst, bool IsTemporary, bool IsMutable, const Expr *Init) { // Classes and structures. - if (auto *RT = Ty->getAs()) { - if (auto *Record = getOrCreateRecord(RT->getDecl())) + if (const auto *RT = Ty->getAs()) { + if (const auto *Record = getOrCreateRecord(RT->getDecl())) return allocateDescriptor(D, Record, MDSize, IsConst, IsTemporary, IsMutable); } // Arrays. - if (auto ArrayType = Ty->getAsArrayTypeUnsafe()) { + if (const auto ArrayType = Ty->getAsArrayTypeUnsafe()) { QualType ElemTy = ArrayType->getElementType(); // Array of well-known bounds. if (auto CAT = dyn_cast(ArrayType)) { @@ -338,7 +338,7 @@ Descriptor *Program::createDescriptor(const DeclTy &D, const Type *Ty, } else { // Arrays of composites. In this case, the array is a list of pointers, // followed by the actual elements. - Descriptor *ElemDesc = createDescriptor( + const Descriptor *ElemDesc = createDescriptor( D, ElemTy.getTypePtr(), std::nullopt, IsConst, IsTemporary); if (!ElemDesc) return nullptr; @@ -358,8 +358,8 @@ Descriptor *Program::createDescriptor(const DeclTy &D, const Type *Ty, return allocateDescriptor(D, *T, IsTemporary, Descriptor::UnknownSize{}); } else { - Descriptor *Desc = createDescriptor(D, ElemTy.getTypePtr(), MDSize, - IsConst, IsTemporary); + const Descriptor *Desc = createDescriptor(D, ElemTy.getTypePtr(), + MDSize, IsConst, IsTemporary); if (!Desc) return nullptr; return allocateDescriptor(D, Desc, IsTemporary, @@ -369,14 +369,14 @@ Descriptor *Program::createDescriptor(const DeclTy &D, const Type *Ty, } // Atomic types. - if (auto *AT = Ty->getAs()) { + if (const auto *AT = Ty->getAs()) { const Type *InnerTy = AT->getValueType().getTypePtr(); return createDescriptor(D, InnerTy, MDSize, IsConst, IsTemporary, IsMutable); } // Complex types - represented as arrays of elements. - if (auto *CT = Ty->getAs()) { + if (const auto *CT = Ty->getAs()) { PrimType ElemTy = *Ctx.classify(CT->getElementType()); return allocateDescriptor(D, ElemTy, MDSize, 2, IsConst, IsTemporary, IsMutable); -- GitLab From 7388b7422f9307dd5ae3fe3876a676d83d702daf Mon Sep 17 00:00:00 2001 From: Juneyoung Lee Date: Tue, 9 Jan 2024 23:54:43 -0600 Subject: [PATCH 289/652] [WebAssembly] Correctly consider signext/zext arg flags at function declaration (#77281) This patch fixes WebAssembly's FastISel pass to correctly consider signext/zeroext parameter flags at function declaration. Previously, the flags at call sites were only considered during code generation, which caused an interesting bug report #63388 . This is problematic especially because in WebAssembly's ABI, either signext or zeroext can be tagged to a function argument, and it must be correctly reflected in the generated code. Unit test https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/WebAssembly/signext-zeroext.ll shows that `i8 zeroext %t` and `i8 signext %t`'s code gen are different. --- .../WebAssembly/WebAssemblyFastISel.cpp | 4 +- .../WebAssembly/signext-zeroext-callsite.ll | 186 ++++++++++++++++++ 2 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 15dc44a04395..7f0140a5e8c6 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -839,9 +839,9 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) { unsigned Reg; - if (Attrs.hasParamAttr(I, Attribute::SExt)) + if (Call->paramHasAttr(I, Attribute::SExt)) Reg = getRegForSignedValue(V); - else if (Attrs.hasParamAttr(I, Attribute::ZExt)) + else if (Call->paramHasAttr(I, Attribute::ZExt)) Reg = getRegForUnsignedValue(V); else Reg = getRegForValue(V); diff --git a/llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll b/llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll new file mode 100644 index 000000000000..e33337f27806 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll @@ -0,0 +1,186 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -O0 | FileCheck %s +; RUN: llc -fast-isel=false < %s -O0 | FileCheck %s -check-prefixes NO-FAST-ISEL + +target triple = "wasm32-unknown-unknown" + + +declare i32 @foo(i1 signext noundef, i32 noundef) + +; callsite_signext and callsite_nosignext must emit equivalent codes + +define i32 @callsite_nosignext() { +; CHECK-LABEL: callsite_nosignext: +; CHECK: .functype callsite_nosignext () -> (i32) +; CHECK-NEXT: .local i32, i32, i32, i32, i32, i32 +; CHECK-NEXT: # %bb.0: # %start +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 0 +; CHECK-NEXT: i32.const 0 +; CHECK-NEXT: local.set 1 +; CHECK-NEXT: i32.const 31 +; CHECK-NEXT: local.set 2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: i32.shl +; CHECK-NEXT: local.set 3 +; CHECK-NEXT: local.get 3 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: i32.shr_s +; CHECK-NEXT: local.set 4 +; CHECK-NEXT: local.get 4 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: call foo +; CHECK-NEXT: local.set 5 +; CHECK-NEXT: local.get 5 +; CHECK-NEXT: return +; +; NO-FAST-ISEL-LABEL: callsite_nosignext: +; NO-FAST-ISEL: .functype callsite_nosignext () -> (i32) +; NO-FAST-ISEL-NEXT: .local i32, i32, i32 +; NO-FAST-ISEL-NEXT: # %bb.0: # %start +; NO-FAST-ISEL-NEXT: i32.const 0 +; NO-FAST-ISEL-NEXT: local.set 0 +; NO-FAST-ISEL-NEXT: i32.const -1 +; NO-FAST-ISEL-NEXT: local.set 1 +; NO-FAST-ISEL-NEXT: local.get 1 +; NO-FAST-ISEL-NEXT: local.get 0 +; NO-FAST-ISEL-NEXT: call foo +; NO-FAST-ISEL-NEXT: local.set 2 +; NO-FAST-ISEL-NEXT: local.get 2 +; NO-FAST-ISEL-NEXT: return +start: + %0 = call i32 @foo(i1 1, i32 0) + ret i32 %0 +} + +define i32 @callsite_signext() { +; CHECK-LABEL: callsite_signext: +; CHECK: .functype callsite_signext () -> (i32) +; CHECK-NEXT: .local i32, i32, i32, i32, i32, i32 +; CHECK-NEXT: # %bb.0: # %start +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 0 +; CHECK-NEXT: i32.const 0 +; CHECK-NEXT: local.set 1 +; CHECK-NEXT: i32.const 31 +; CHECK-NEXT: local.set 2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: i32.shl +; CHECK-NEXT: local.set 3 +; CHECK-NEXT: local.get 3 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: i32.shr_s +; CHECK-NEXT: local.set 4 +; CHECK-NEXT: local.get 4 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: call foo +; CHECK-NEXT: local.set 5 +; CHECK-NEXT: local.get 5 +; CHECK-NEXT: return +; +; NO-FAST-ISEL-LABEL: callsite_signext: +; NO-FAST-ISEL: .functype callsite_signext () -> (i32) +; NO-FAST-ISEL-NEXT: .local i32, i32, i32 +; NO-FAST-ISEL-NEXT: # %bb.0: # %start +; NO-FAST-ISEL-NEXT: i32.const 0 +; NO-FAST-ISEL-NEXT: local.set 0 +; NO-FAST-ISEL-NEXT: i32.const -1 +; NO-FAST-ISEL-NEXT: local.set 1 +; NO-FAST-ISEL-NEXT: local.get 1 +; NO-FAST-ISEL-NEXT: local.get 0 +; NO-FAST-ISEL-NEXT: call foo +; NO-FAST-ISEL-NEXT: local.set 2 +; NO-FAST-ISEL-NEXT: local.get 2 +; NO-FAST-ISEL-NEXT: return +start: + %0 = call i32 @foo(i1 signext 1, i32 0) + ret i32 %0 +} + +declare i32 @foo2(i1 zeroext noundef, i32 noundef) + +; callsite_zeroext and callsite_nozeroext must emit equivalent codes + +define i32 @callsite_nozeroext() { +; CHECK-LABEL: callsite_nozeroext: +; CHECK: .functype callsite_nozeroext () -> (i32) +; CHECK-NEXT: .local i32, i32, i32, i32, i32 +; CHECK-NEXT: # %bb.0: # %start +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 0 +; CHECK-NEXT: i32.const 0 +; CHECK-NEXT: local.set 1 +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: i32.and +; CHECK-NEXT: local.set 3 +; CHECK-NEXT: local.get 3 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: call foo2 +; CHECK-NEXT: local.set 4 +; CHECK-NEXT: local.get 4 +; CHECK-NEXT: return +; +; NO-FAST-ISEL-LABEL: callsite_nozeroext: +; NO-FAST-ISEL: .functype callsite_nozeroext () -> (i32) +; NO-FAST-ISEL-NEXT: .local i32, i32, i32 +; NO-FAST-ISEL-NEXT: # %bb.0: # %start +; NO-FAST-ISEL-NEXT: i32.const 0 +; NO-FAST-ISEL-NEXT: local.set 0 +; NO-FAST-ISEL-NEXT: i32.const 1 +; NO-FAST-ISEL-NEXT: local.set 1 +; NO-FAST-ISEL-NEXT: local.get 1 +; NO-FAST-ISEL-NEXT: local.get 0 +; NO-FAST-ISEL-NEXT: call foo2 +; NO-FAST-ISEL-NEXT: local.set 2 +; NO-FAST-ISEL-NEXT: local.get 2 +; NO-FAST-ISEL-NEXT: return +start: + %0 = call i32 @foo2(i1 1, i32 0) + ret i32 %0 +} + +define i32 @callsite_zeroext() { +; CHECK-LABEL: callsite_zeroext: +; CHECK: .functype callsite_zeroext () -> (i32) +; CHECK-NEXT: .local i32, i32, i32, i32, i32 +; CHECK-NEXT: # %bb.0: # %start +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 0 +; CHECK-NEXT: i32.const 0 +; CHECK-NEXT: local.set 1 +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: i32.and +; CHECK-NEXT: local.set 3 +; CHECK-NEXT: local.get 3 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: call foo2 +; CHECK-NEXT: local.set 4 +; CHECK-NEXT: local.get 4 +; CHECK-NEXT: return +; +; NO-FAST-ISEL-LABEL: callsite_zeroext: +; NO-FAST-ISEL: .functype callsite_zeroext () -> (i32) +; NO-FAST-ISEL-NEXT: .local i32, i32, i32 +; NO-FAST-ISEL-NEXT: # %bb.0: # %start +; NO-FAST-ISEL-NEXT: i32.const 0 +; NO-FAST-ISEL-NEXT: local.set 0 +; NO-FAST-ISEL-NEXT: i32.const 1 +; NO-FAST-ISEL-NEXT: local.set 1 +; NO-FAST-ISEL-NEXT: local.get 1 +; NO-FAST-ISEL-NEXT: local.get 0 +; NO-FAST-ISEL-NEXT: call foo2 +; NO-FAST-ISEL-NEXT: local.set 2 +; NO-FAST-ISEL-NEXT: local.get 2 +; NO-FAST-ISEL-NEXT: return +start: + %0 = call i32 @foo2(i1 zeroext 1, i32 0) + ret i32 %0 +} -- GitLab From 7fc7ef14340a3a58cebd0801497b68eb698c2784 Mon Sep 17 00:00:00 2001 From: Serge Pavlov Date: Wed, 10 Jan 2024 14:18:00 +0700 Subject: [PATCH 290/652] [GlobalISel] Lowering of {get,set,reset}_fpenv (#75086) The intrinsics get_fpenv, set_fpenv and reset_fpenv in this change are implemented as calls to math library functions. Target specific lowering will be implemented later on. --- llvm/include/llvm/Support/TargetOpcodes.def | 3 + llvm/include/llvm/Target/GenericOpcodes.td | 21 +++++++ .../Target/GlobalISel/SelectionDAGCompat.td | 3 + llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 12 ++++ .../CodeGen/GlobalISel/LegalizerHelper.cpp | 10 ++++ .../AArch64/GISel/AArch64LegalizerInfo.cpp | 3 +- llvm/test/CodeGen/AArch64/GlobalISel/fpenv.ll | 43 ++++++++++++++ .../AArch64/GlobalISel/irtranslator-fpenv.ll | 37 ++++++++++++ .../AArch64/GlobalISel/legalize-fpenv.mir | 59 +++++++++++++++++++ .../GlobalISel/legalizer-info-validation.mir | 12 ++++ llvm/test/TableGen/GlobalISelEmitter.td | 2 +- 11 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/fpenv.ll create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 3824b1c66951..c005218c80f4 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -687,6 +687,9 @@ HANDLE_TARGET_OPCODE(G_FMINIMUM) HANDLE_TARGET_OPCODE(G_FMAXIMUM) /// Access to FP environment. +HANDLE_TARGET_OPCODE(G_GET_FPENV) +HANDLE_TARGET_OPCODE(G_SET_FPENV) +HANDLE_TARGET_OPCODE(G_RESET_FPENV) HANDLE_TARGET_OPCODE(G_GET_FPMODE) HANDLE_TARGET_OPCODE(G_SET_FPMODE) HANDLE_TARGET_OPCODE(G_RESET_FPMODE) diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 73e38b15bf67..2c73b67f9e1a 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -1020,6 +1020,27 @@ def G_FNEARBYINT : GenericInstruction { // it is modeled as a side effect, because constrained intrinsics use the same // method. +// Reading floating-point environment. +def G_GET_FPENV : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins); + let hasSideEffects = true; +} + +// Setting floating-point environment. +def G_SET_FPENV : GenericInstruction { + let OutOperandList = (outs); + let InOperandList = (ins type0:$src); + let hasSideEffects = true; +} + +// Setting default floating-point environment. +def G_RESET_FPENV : GenericInstruction { + let OutOperandList = (outs); + let InOperandList = (ins); + let hasSideEffects = true; +} + // Reading floating-point control modes. def G_GET_FPMODE : GenericInstruction { let OutOperandList = (outs type0:$dst); diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 5e704f0b9a75..f792237203b4 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -116,6 +116,9 @@ def : GINodeEquiv { let IfConvergent = G_INTRINSIC_CONVERGENT; } +def : GINodeEquiv; +def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 6708f2baa5ed..8a6bfdc5ee66 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1919,6 +1919,8 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) { return TargetOpcode::G_LROUND; case Intrinsic::llround: return TargetOpcode::G_LLROUND; + case Intrinsic::get_fpenv: + return TargetOpcode::G_GET_FPENV; case Intrinsic::get_fpmode: return TargetOpcode::G_GET_FPMODE; } @@ -2502,6 +2504,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, return true; } + case Intrinsic::set_fpenv: { + Value *FPEnv = CI.getOperand(0); + MIRBuilder.buildInstr(TargetOpcode::G_SET_FPENV, {}, + {getOrCreateVReg(*FPEnv)}); + return true; + } + case Intrinsic::reset_fpenv: { + MIRBuilder.buildInstr(TargetOpcode::G_RESET_FPENV, {}, {}); + return true; + } case Intrinsic::set_fpmode: { Value *FPState = CI.getOperand(0); MIRBuilder.buildInstr(TargetOpcode::G_SET_FPMODE, {}, diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index def7f6ebeb01..21947a55874a 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -958,6 +958,13 @@ static RTLIB::Libcall getStateLibraryFunctionFor(MachineInstr &MI, const TargetLowering &TLI) { RTLIB::Libcall RTLibcall; switch (MI.getOpcode()) { + case TargetOpcode::G_GET_FPENV: + RTLibcall = RTLIB::FEGETENV; + break; + case TargetOpcode::G_SET_FPENV: + case TargetOpcode::G_RESET_FPENV: + RTLibcall = RTLIB::FESETENV; + break; case TargetOpcode::G_GET_FPMODE: RTLibcall = RTLIB::FEGETMODE; break; @@ -1232,18 +1239,21 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) { MI.eraseFromParent(); return Result; } + case TargetOpcode::G_GET_FPENV: case TargetOpcode::G_GET_FPMODE: { LegalizeResult Result = createGetStateLibcall(MIRBuilder, MI, LocObserver); if (Result != Legalized) return Result; break; } + case TargetOpcode::G_SET_FPENV: case TargetOpcode::G_SET_FPMODE: { LegalizeResult Result = createSetStateLibcall(MIRBuilder, MI, LocObserver); if (Result != Legalized) return Result; break; } + case TargetOpcode::G_RESET_FPENV: case TargetOpcode::G_RESET_FPMODE: { LegalizeResult Result = createResetStateLibcall(MIRBuilder, MI, LocObserver); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index b657a0954d78..302116447efc 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -1166,7 +1166,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) getActionDefinitionsBuilder(G_FMAD).lower(); // Access to floating-point environment. - getActionDefinitionsBuilder({G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE}) + getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV, + G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE}) .libcall(); getActionDefinitionsBuilder(G_IS_FPCLASS).lower(); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fpenv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/fpenv.ll new file mode 100644 index 000000000000..a95d65051837 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fpenv.ll @@ -0,0 +1,43 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -global-isel -global-isel-abort=1 %s -o - | FileCheck %s + +declare i64 @llvm.get.fpenv.i64() +declare void @llvm.set.fpenv.i64(i64 %fpenv) +declare void @llvm.reset.fpenv() + +define i64 @get_fpenv_01() nounwind { +; CHECK-LABEL: get_fpenv_01: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: add x0, sp, #8 +; CHECK-NEXT: bl fegetenv +; CHECK-NEXT: ldr x0, [sp, #8] +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +entry: + %fpenv = call i64 @llvm.get.fpenv.i64() + ret i64 %fpenv +} + +define void @set_fpenv_01(i64 %fpenv) nounwind { +; CHECK-LABEL: set_fpenv_01: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x30, x0, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: add x0, sp, #8 +; CHECK-NEXT: bl fesetenv +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +entry: + call void @llvm.set.fpenv.i64(i64 %fpenv) + ret void +} + +define void @reset_fpenv_01() nounwind { +; CHECK-LABEL: reset_fpenv_01: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov x0, #-1 // =0xffffffffffffffff +; CHECK-NEXT: b fesetenv +entry: + call void @llvm.reset.fpenv() + ret void +} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll index fda9269d423d..9a8e5529f0a1 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll @@ -1,10 +1,47 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s +declare i64 @llvm.get.fpenv.i64() +declare void @llvm.set.fpenv.i64(i64 %fpenv) +declare void @llvm.reset.fpenv() declare i32 @llvm.get.fpmode.i32() declare void @llvm.set.fpmode.i32(i32 %fpmode) declare void @llvm.reset.fpmode() +define i64 @func_get_fpenv() #0 { + ; CHECK-LABEL: name: func_get_fpenv + ; CHECK: bb.1.entry: + ; CHECK-NEXT: [[GET_FPENV:%[0-9]+]]:_(s64) = G_GET_FPENV + ; CHECK-NEXT: $x0 = COPY [[GET_FPENV]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 +entry: + %fpenv = call i64 @llvm.get.fpenv.i64() + ret i64 %fpenv +} + +define void @func_set_fpenv(i64 %fpenv) #0 { + ; CHECK-LABEL: name: func_set_fpenv + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: G_SET_FPENV [[COPY]](s64) + ; CHECK-NEXT: RET_ReallyLR +entry: + call void @llvm.set.fpenv.i64(i64 %fpenv) + ret void +} + +define void @func_reset_fpenv() #0 { + ; CHECK-LABEL: name: func_reset_fpenv + ; CHECK: bb.1.entry: + ; CHECK-NEXT: G_RESET_FPENV + ; CHECK-NEXT: RET_ReallyLR +entry: + call void @llvm.reset.fpenv() + ret void +} + define i32 @func_get_fpmode() #0 { ; CHECK-LABEL: name: func_get_fpmode ; CHECK: bb.1.entry: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir new file mode 100644 index 000000000000..936f839280c4 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: func_get_fpenv +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: func_get_fpenv + ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: $x0 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: BL &fegetenv, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0) + ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 + %0:_(s64) = G_GET_FPENV + $x0 = COPY %0(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: func_set_fpenv +tracksRegLiveness: true +body: | + bb.0: + liveins: $x0 + + ; CHECK-LABEL: name: func_set_fpenv + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK-NEXT: G_STORE [[COPY]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: $x0 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: BL &fesetenv, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: RET_ReallyLR + %0:_(s64) = COPY $x0 + G_SET_FPENV %0(s64) + RET_ReallyLR + +... +--- +name: func_reset +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: func_reset + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64) + ; CHECK-NEXT: $x0 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: TCRETURNdi &fesetenv, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0 + G_RESET_FPENV + RET_ReallyLR + +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index 2adf9763a96b..c90c31aa27ef 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -553,7 +553,19 @@ # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_GET_FPENV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SET_FPENV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_RESET_FPENV (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: G_GET_FPMODE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: G_SET_FPMODE (opcode {{[0-9]+}}): 1 type index, 0 imm indices diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td index f9d7d2dcccdb..dd3ac6cc3672 100644 --- a/llvm/test/TableGen/GlobalISelEmitter.td +++ b/llvm/test/TableGen/GlobalISelEmitter.td @@ -518,7 +518,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00O-NEXT: GIM_Reject, // R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]] // R00O-NEXT: GIM_Reject, -// R00O-NEXT: }; // Size: 2007 bytes +// R00O-NEXT: }; // Size: 2019 bytes def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4), [(set GPR32:$dst, -- GitLab From efcf192a0a5993165f837ce71250fb6df689634b Mon Sep 17 00:00:00 2001 From: Bhuminjay Soni <76656712+11happy@users.noreply.github.com> Date: Wed, 10 Jan 2024 12:57:58 +0530 Subject: [PATCH 291/652] Changed Checks from TriviallyCopyable to TriviallyCopyConstructible (#77194) **Overview:** Fix a bug where Clang's range-loop-analysis incorrectly checks for trivial copyability instead of trivial copy constructibility, leading to erroneous warnings. Fixes #47355 --- clang/docs/ReleaseNotes.rst | 3 ++ clang/include/clang/AST/DeclCXX.h | 3 ++ clang/include/clang/AST/Type.h | 3 ++ clang/lib/AST/DeclCXX.cpp | 13 +++++++ clang/lib/AST/Type.cpp | 34 ++++++++++++++----- clang/lib/Sema/SemaStmt.cpp | 2 +- ...range-loop-analysis-trivially-copyable.cpp | 25 ++++++++++++++ 7 files changed, 73 insertions(+), 10 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 46f4b82b89e4..15479906d22b 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -884,6 +884,9 @@ Bug Fixes to AST Handling - Fixed a bug where RecursiveASTVisitor fails to visit the initializer of a bitfield. `Issue 64916 `_ +- Fixed a bug where range-loop-analysis checks for trivial copyability, + rather than trivial copy-constructibility + `Issue 47355 `_ - Fixed a bug where Template Instantiation failed to handle Lambda Expressions with certain types of Attributes. (`#76521 `_) diff --git a/clang/include/clang/AST/DeclCXX.h b/clang/include/clang/AST/DeclCXX.h index 984a4d8bab5e..648f5f946408 100644 --- a/clang/include/clang/AST/DeclCXX.h +++ b/clang/include/clang/AST/DeclCXX.h @@ -1425,6 +1425,9 @@ public: /// (C++11 [class]p6). bool isTriviallyCopyable() const; + /// Determine whether this class is considered trivially copyable per + bool isTriviallyCopyConstructible() const; + /// Determine whether this class is considered trivial. /// /// C++11 [class]p6: diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index 9e9f896ebef7..d4e5310fb3ab 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -917,6 +917,9 @@ public: /// Return true if this is a trivially copyable type (C++0x [basic.types]p9) bool isTriviallyCopyableType(const ASTContext &Context) const; + /// Return true if this is a trivially copyable type + bool isTriviallyCopyConstructibleType(const ASTContext &Context) const; + /// Return true if this is a trivially relocatable type. bool isTriviallyRelocatableType(const ASTContext &Context) const; diff --git a/clang/lib/AST/DeclCXX.cpp b/clang/lib/AST/DeclCXX.cpp index c944862fcefe..98b0a6dc28ea 100644 --- a/clang/lib/AST/DeclCXX.cpp +++ b/clang/lib/AST/DeclCXX.cpp @@ -587,6 +587,19 @@ bool CXXRecordDecl::isTriviallyCopyable() const { return true; } +bool CXXRecordDecl::isTriviallyCopyConstructible() const { + + // A trivially copy constructible class is a class that: + // -- has no non-trivial copy constructors, + if (hasNonTrivialCopyConstructor()) + return false; + // -- has a trivial destructor. + if (!hasTrivialDestructor()) + return false; + + return true; +} + void CXXRecordDecl::markedVirtualFunctionPure() { // C++ [class.abstract]p2: // A class is abstract if it has at least one pure virtual function. diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp index a894d3289eb1..b419fc8836b0 100644 --- a/clang/lib/AST/Type.cpp +++ b/clang/lib/AST/Type.cpp @@ -2604,19 +2604,22 @@ bool QualType::isTrivialType(const ASTContext &Context) const { return false; } -bool QualType::isTriviallyCopyableType(const ASTContext &Context) const { - if ((*this)->isArrayType()) - return Context.getBaseElementType(*this).isTriviallyCopyableType(Context); +static bool isTriviallyCopyableTypeImpl(const QualType &type, + const ASTContext &Context, + bool IsCopyConstructible) { + if (type->isArrayType()) + return isTriviallyCopyableTypeImpl(Context.getBaseElementType(type), + Context, IsCopyConstructible); - if (hasNonTrivialObjCLifetime()) + if (type.hasNonTrivialObjCLifetime()) return false; // C++11 [basic.types]p9 - See Core 2094 // Scalar types, trivially copyable class types, arrays of such types, and // cv-qualified versions of these types are collectively - // called trivially copyable types. + // called trivially copy constructible types. - QualType CanonicalType = getCanonicalType(); + QualType CanonicalType = type.getCanonicalType(); if (CanonicalType->isDependentType()) return false; @@ -2634,16 +2637,29 @@ bool QualType::isTriviallyCopyableType(const ASTContext &Context) const { if (const auto *RT = CanonicalType->getAs()) { if (const auto *ClassDecl = dyn_cast(RT->getDecl())) { - if (!ClassDecl->isTriviallyCopyable()) return false; + if (IsCopyConstructible) { + return ClassDecl->isTriviallyCopyConstructible(); + } else { + return ClassDecl->isTriviallyCopyable(); + } } - return true; } - // No other types can match. return false; } +bool QualType::isTriviallyCopyableType(const ASTContext &Context) const { + return isTriviallyCopyableTypeImpl(*this, Context, + /*IsCopyConstructible=*/false); +} + +bool QualType::isTriviallyCopyConstructibleType( + const ASTContext &Context) const { + return isTriviallyCopyableTypeImpl(*this, Context, + /*IsCopyConstructible=*/true); +} + bool QualType::isTriviallyRelocatableType(const ASTContext &Context) const { QualType BaseElementType = Context.getBaseElementType(*this); diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp index f0b03db69084..21efe25ed84a 100644 --- a/clang/lib/Sema/SemaStmt.cpp +++ b/clang/lib/Sema/SemaStmt.cpp @@ -3200,7 +3200,7 @@ static void DiagnoseForRangeConstVariableCopies(Sema &SemaRef, // (The function `getTypeSize` returns the size in bits.) ASTContext &Ctx = SemaRef.Context; if (Ctx.getTypeSize(VariableType) <= 64 * 8 && - (VariableType.isTriviallyCopyableType(Ctx) || + (VariableType.isTriviallyCopyConstructibleType(Ctx) || hasTrivialABIAttr(VariableType))) return; diff --git a/clang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp b/clang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp index e345ef40aed9..8fa387908c36 100644 --- a/clang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp +++ b/clang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp @@ -33,6 +33,17 @@ void test_TriviallyCopyable_64_bytes() { for (const auto r : records) (void)r; } +void test_TriviallyCopyConstructible_64_bytes() { + struct Record { + char a[64]; + Record& operator=(Record const& other){return *this;}; + + }; + + Record records[8]; + for (const auto r : records) + (void)r; +} void test_TriviallyCopyable_65_bytes() { struct Record { @@ -47,6 +58,19 @@ void test_TriviallyCopyable_65_bytes() { (void)r; } +void test_TriviallyCopyConstructible_65_bytes() { + struct Record { + char a[65]; + Record& operator=(Record const& other){return *this;}; + + }; + // expected-warning@+3 {{loop variable 'r' creates a copy from type 'const Record'}} + // expected-note@+2 {{use reference type 'const Record &' to prevent copying}} + Record records[8]; + for (const auto r : records) + (void)r; +} + void test_NonTriviallyCopyable() { struct Record { Record() {} @@ -87,3 +111,4 @@ void test_TrivialABI_65_bytes() { for (const auto r : records) (void)r; } + -- GitLab From b788692fa5b6ed79ea2c85ee464353cca30d867a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 9 Jan 2024 23:37:13 -0800 Subject: [PATCH 292/652] [RISCV][NFC] Remove unused CHECK prefixes to fix buildbots. NFC --- llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll index f5e81718226c..23e2a331d7e4 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK,RV32I -; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK,RV64I +; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK define void @add_nxv2i32( %a, %b) { ; CHECK-LABEL: name: add_nxv2i32 -- GitLab From 8f78dd4b92b44c490d263a4d161850853874859d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bal=C3=A1zs=20K=C3=A9ri?= Date: Wed, 10 Jan 2024 09:09:51 +0100 Subject: [PATCH 293/652] [clang][analyzer] Add function 'ungetc' to StreamChecker. (#77331) `StdLibraryFunctionsChecker` is updated too with `ungetc`. --- clang/docs/ReleaseNotes.rst | 8 ++-- .../Checkers/StdLibraryFunctionsChecker.cpp | 19 ++++++++ .../StaticAnalyzer/Checkers/StreamChecker.cpp | 45 +++++++++++++++++++ .../Analysis/Inputs/system-header-simulator.h | 1 + clang/test/Analysis/stream-error.c | 16 +++++++ clang/test/Analysis/stream-noopen.c | 25 +++++++++++ clang/test/Analysis/stream.c | 6 +++ 7 files changed, 117 insertions(+), 3 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 15479906d22b..20872f7ddb81 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1202,8 +1202,9 @@ Improvements (`c3a87ddad62a `_, `0954dc3fb921 `_) -- Improved the ``alpha.unix.Stream`` checker by modeling more functions like, - ``fflush``, ``fputs``, ``fgetc``, ``fputc``, ``fopen``, ``fdopen``, ``fgets``, ``tmpfile``. +- Improved the ``alpha.unix.Stream`` checker by modeling more functions + ``fputs``, ``fputc``, ``fgets``, ``fgetc``, ``fdopen``, ``ungetc``, ``fflush`` + and no not recognize alternative ``fopen`` and ``tmpfile`` implementations. (`#76776 `_, `#74296 `_, `#73335 `_, @@ -1211,7 +1212,8 @@ Improvements `#71518 `_, `#72016 `_, `#70540 `_, - `#73638 `_) + `#73638 `_, + `#77331 `_) - The ``alpha.security.taint.TaintPropagation`` checker no longer propagates taint on ``strlen`` and ``strnlen`` calls, unless these are marked diff --git a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp index 034825d88a44..32a2deab871c 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp @@ -2201,6 +2201,25 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( ErrnoNEZeroIrrelevant, GenericFailureMsg) .ArgConstraint(NotNull(ArgNo(0)))); + // int ungetc(int c, FILE *stream); + addToFunctionSummaryMap( + "ungetc", Signature(ArgTypes{IntTy, FilePtrTy}, RetType{IntTy}), + Summary(NoEvalCall) + .Case({ReturnValueCondition(BO_EQ, ArgNo(0)), + ArgumentCondition(0, WithinRange, {{0, UCharRangeMax}})}, + ErrnoMustNotBeChecked, GenericSuccessMsg) + .Case({ReturnValueCondition(WithinRange, SingleValue(EOFv)), + ArgumentCondition(0, WithinRange, {{EOFv, EOFv}})}, + ErrnoNEZeroIrrelevant, + "Assuming that 'ungetc' fails because EOF was passed as " + "character") + .Case({ReturnValueCondition(WithinRange, SingleValue(EOFv)), + ArgumentCondition(0, WithinRange, {{0, UCharRangeMax}})}, + ErrnoNEZeroIrrelevant, GenericFailureMsg) + .ArgConstraint(ArgumentCondition( + 0, WithinRange, {{EOFv, EOFv}, {0, UCharRangeMax}})) + .ArgConstraint(NotNull(ArgNo(1)))); + // int fseek(FILE *stream, long offset, int whence); // FIXME: It can be possible to get the 'SEEK_' values (like EOFv) and use // these for condition of arg 2. diff --git a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp index 25da3c18e851..fbfa101257d5 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp @@ -263,6 +263,9 @@ private: {{{"fputs"}, 2}, {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, false), std::bind(&StreamChecker::evalFputx, _1, _2, _3, _4, false), 1}}, + {{{"ungetc"}, 2}, + {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, false), + std::bind(&StreamChecker::evalUngetc, _1, _2, _3, _4), 1}}, {{{"fseek"}, 3}, {&StreamChecker::preFseek, &StreamChecker::evalFseek, 0}}, {{{"ftell"}, 1}, @@ -332,6 +335,9 @@ private: void evalFputx(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C, bool IsSingleChar) const; + void evalUngetc(const FnDescription *Desc, const CallEvent &Call, + CheckerContext &C) const; + void preFseek(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C) const; void evalFseek(const FnDescription *Desc, const CallEvent &Call, @@ -916,6 +922,45 @@ void StreamChecker::evalFputx(const FnDescription *Desc, const CallEvent &Call, C.addTransition(StateFailed); } +void StreamChecker::evalUngetc(const FnDescription *Desc, const CallEvent &Call, + CheckerContext &C) const { + ProgramStateRef State = C.getState(); + SymbolRef StreamSym = getStreamArg(Desc, Call).getAsSymbol(); + if (!StreamSym) + return; + + const CallExpr *CE = dyn_cast_or_null(Call.getOriginExpr()); + if (!CE) + return; + + const StreamState *OldSS = State->get(StreamSym); + if (!OldSS) + return; + + assertStreamStateOpened(OldSS); + + // Generate a transition for the success state. + std::optional PutVal = Call.getArgSVal(0).getAs(); + if (!PutVal) + return; + ProgramStateRef StateNotFailed = + State->BindExpr(CE, C.getLocationContext(), *PutVal); + StateNotFailed = + StateNotFailed->set(StreamSym, StreamState::getOpened(Desc)); + C.addTransition(StateNotFailed); + + // Add transition for the failed state. + // Failure of 'ungetc' does not result in feof or ferror state. + // If the PutVal has value of EofVal the function should "fail", but this is + // the same transition as the success state. + // In this case only one state transition is added by the analyzer (the two + // new states may be similar). + ProgramStateRef StateFailed = bindInt(*EofVal, State, C, CE); + StateFailed = + StateFailed->set(StreamSym, StreamState::getOpened(Desc)); + C.addTransition(StateFailed); +} + void StreamChecker::preFseek(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C) const { ProgramStateRef State = C.getState(); diff --git a/clang/test/Analysis/Inputs/system-header-simulator.h b/clang/test/Analysis/Inputs/system-header-simulator.h index 8c43c48c6a3e..caae59c38a4c 100644 --- a/clang/test/Analysis/Inputs/system-header-simulator.h +++ b/clang/test/Analysis/Inputs/system-header-simulator.h @@ -53,6 +53,7 @@ int fgetc(FILE *stream); char *fgets(char *restrict str, int count, FILE *restrict stream); int fputc(int ch, FILE *stream); int fputs(const char *restrict s, FILE *restrict stream); +int ungetc(int c, FILE *stream); int fseek(FILE *__stream, long int __off, int __whence); long int ftell(FILE *__stream); void rewind(FILE *__stream); diff --git a/clang/test/Analysis/stream-error.c b/clang/test/Analysis/stream-error.c index 13c6684b5840..c038348e799d 100644 --- a/clang/test/Analysis/stream-error.c +++ b/clang/test/Analysis/stream-error.c @@ -191,6 +191,22 @@ void error_fputs(void) { fputs("ABC", F); // expected-warning {{Stream might be already closed}} } +void error_ungetc() { + FILE *F = tmpfile(); + if (!F) + return; + int Ret = ungetc('X', F); + clang_analyzer_eval(feof(F) || ferror(F)); // expected-warning {{FALSE}} + if (Ret == EOF) { + clang_analyzer_warnIfReached(); // expected-warning {{REACHABLE}} + } else { + clang_analyzer_eval(Ret == 'X'); // expected-warning {{TRUE}} + } + fputc('Y', F); // no-warning + fclose(F); + ungetc('A', F); // expected-warning {{Stream might be already closed}} +} + void write_after_eof_is_allowed(void) { FILE *F = tmpfile(); if (!F) diff --git a/clang/test/Analysis/stream-noopen.c b/clang/test/Analysis/stream-noopen.c index 2daf640c18a1..8ad101ee1e8c 100644 --- a/clang/test/Analysis/stream-noopen.c +++ b/clang/test/Analysis/stream-noopen.c @@ -138,6 +138,31 @@ void test_rewind(FILE *F) { rewind(F); } +void test_ungetc(FILE *F) { + int Ret = ungetc('X', F); + clang_analyzer_eval(F != NULL); // expected-warning {{TRUE}} + if (Ret == 'X') { + if (errno) {} // expected-warning {{undefined}} + } else { + clang_analyzer_eval(Ret == EOF); // expected-warning {{TRUE}} + clang_analyzer_eval(errno != 0); // expected-warning {{TRUE}} + } + clang_analyzer_eval(feof(F)); // expected-warning {{UNKNOWN}} + clang_analyzer_eval(ferror(F)); // expected-warning {{UNKNOWN}} +} + +void test_ungetc_EOF(FILE *F, int C) { + int Ret = ungetc(EOF, F); + clang_analyzer_eval(F != NULL); // expected-warning {{TRUE}} + clang_analyzer_eval(Ret == EOF); // expected-warning {{TRUE}} + clang_analyzer_eval(errno != 0); // expected-warning {{TRUE}} + Ret = ungetc(C, F); + if (Ret == EOF) { + clang_analyzer_eval(C == EOF); // expected-warning {{TRUE}} + // expected-warning@-1{{FALSE}} + } +} + void test_feof(FILE *F) { errno = 0; feof(F); diff --git a/clang/test/Analysis/stream.c b/clang/test/Analysis/stream.c index 060d561c1fe1..d8026247697a 100644 --- a/clang/test/Analysis/stream.c +++ b/clang/test/Analysis/stream.c @@ -39,6 +39,12 @@ void check_fputs(void) { fclose(fp); } +void check_ungetc(void) { + FILE *fp = tmpfile(); + ungetc('A', fp); // expected-warning {{Stream pointer might be NULL}} + fclose(fp); +} + void check_fseek(void) { FILE *fp = tmpfile(); fseek(fp, 0, 0); // expected-warning {{Stream pointer might be NULL}} -- GitLab From f443fbc49b8914a8453de61aea741221df9648cf Mon Sep 17 00:00:00 2001 From: Dominik Adamski Date: Wed, 10 Jan 2024 09:38:58 +0100 Subject: [PATCH 294/652] [Flang][OpenMP][MLIR] Add support for -nogpulib option (#71045) If -nogpulib option is passed by the user, then the OpenMP device runtime is not used and we should not emit globals to configure debugging at compile-time for the device runtime. Link to -nogpulib flag implementation for Clang: https://reviews.llvm.org/D125314 --- clang/include/clang/Driver/Options.td | 2 +- clang/lib/Driver/ToolChains/Flang.cpp | 2 ++ flang/include/flang/Frontend/LangOptions.def | 2 ++ flang/include/flang/Tools/CrossToolHelpers.h | 11 +++++++---- flang/lib/Frontend/CompilerInvocation.cpp | 2 ++ flang/test/Driver/driver-help-hidden.f90 | 1 + flang/test/Driver/driver-help.f90 | 2 ++ flang/test/Lower/OpenMP/nogpulib.f90 | 12 ++++++++++++ flang/tools/bbc/bbc.cpp | 8 +++++++- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 1 + .../mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td | 5 +++-- .../Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp | 8 ++++++-- mlir/test/Dialect/OpenMP/attr.mlir | 6 ++++++ mlir/test/Target/LLVMIR/openmp-llvm.mlir | 10 ++++++++++ 14 files changed, 62 insertions(+), 10 deletions(-) create mode 100644 flang/test/Lower/OpenMP/nogpulib.f90 diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 84648c6d5500..a76e8dcff148 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5197,7 +5197,7 @@ def nohipwrapperinc : Flag<["-"], "nohipwrapperinc">, Group, HelpText<"Do not include the default HIP wrapper headers and include paths">; def : Flag<["-"], "nocudainc">, Alias; def nogpulib : Flag<["-"], "nogpulib">, MarshallingInfoFlag>, - Visibility<[ClangOption, CC1Option]>, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Do not link device library for CUDA/HIP device compilation">; def : Flag<["-"], "nocudalib">, Alias; def gpulibc : Flag<["-"], "gpulibc">, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 41eaad3bbad0..5d2fc6cb028e 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -428,6 +428,8 @@ void Flang::addOffloadOptions(Compilation &C, const InputInfoList &Inputs, CmdArgs.push_back("-fopenmp-assume-no-thread-state"); if (Args.hasArg(options::OPT_fopenmp_assume_no_nested_parallelism)) CmdArgs.push_back("-fopenmp-assume-no-nested-parallelism"); + if (Args.hasArg(options::OPT_nogpulib)) + CmdArgs.push_back("-nogpulib"); } } diff --git a/flang/include/flang/Frontend/LangOptions.def b/flang/include/flang/Frontend/LangOptions.def index 3a1d44f7fb47..2bf10826120a 100644 --- a/flang/include/flang/Frontend/LangOptions.def +++ b/flang/include/flang/Frontend/LangOptions.def @@ -21,6 +21,8 @@ LANGOPT(Name, Bits, Default) ENUM_LANGOPT(FPContractMode, FPModeKind, 2, FPM_Fast) ///< FP Contract Mode (off/fast) +/// Indicate a build without the standard GPU libraries. +LANGOPT(NoGPULib , 1, false) /// Permit floating point optimization without regard to infinities LANGOPT(NoHonorInfs, 1, false) /// Permit floating point optimization without regard to NaN diff --git a/flang/include/flang/Tools/CrossToolHelpers.h b/flang/include/flang/Tools/CrossToolHelpers.h index b346b30b158a..b61224ff4f1b 100644 --- a/flang/include/flang/Tools/CrossToolHelpers.h +++ b/flang/include/flang/Tools/CrossToolHelpers.h @@ -56,14 +56,16 @@ struct OffloadModuleOpts { OffloadModuleOpts(uint32_t OpenMPTargetDebug, bool OpenMPTeamSubscription, bool OpenMPThreadSubscription, bool OpenMPNoThreadState, bool OpenMPNoNestedParallelism, bool OpenMPIsTargetDevice, - bool OpenMPIsGPU, uint32_t OpenMPVersion, std::string OMPHostIRFile = {}) + bool OpenMPIsGPU, uint32_t OpenMPVersion, std::string OMPHostIRFile = {}, + bool NoGPULib = false) : OpenMPTargetDebug(OpenMPTargetDebug), OpenMPTeamSubscription(OpenMPTeamSubscription), OpenMPThreadSubscription(OpenMPThreadSubscription), OpenMPNoThreadState(OpenMPNoThreadState), OpenMPNoNestedParallelism(OpenMPNoNestedParallelism), OpenMPIsTargetDevice(OpenMPIsTargetDevice), OpenMPIsGPU(OpenMPIsGPU), - OpenMPVersion(OpenMPVersion), OMPHostIRFile(OMPHostIRFile) {} + OpenMPVersion(OpenMPVersion), OMPHostIRFile(OMPHostIRFile), + NoGPULib(NoGPULib) {} OffloadModuleOpts(Fortran::frontend::LangOptions &Opts) : OpenMPTargetDebug(Opts.OpenMPTargetDebug), @@ -73,7 +75,7 @@ struct OffloadModuleOpts { OpenMPNoNestedParallelism(Opts.OpenMPNoNestedParallelism), OpenMPIsTargetDevice(Opts.OpenMPIsTargetDevice), OpenMPIsGPU(Opts.OpenMPIsGPU), OpenMPVersion(Opts.OpenMPVersion), - OMPHostIRFile(Opts.OMPHostIRFile) {} + OMPHostIRFile(Opts.OMPHostIRFile), NoGPULib(Opts.NoGPULib) {} uint32_t OpenMPTargetDebug = 0; bool OpenMPTeamSubscription = false; @@ -84,6 +86,7 @@ struct OffloadModuleOpts { bool OpenMPIsGPU = false; uint32_t OpenMPVersion = 11; std::string OMPHostIRFile = {}; + bool NoGPULib = false; }; // Shares assinging of the OpenMP OffloadModuleInterface and its assorted @@ -98,7 +101,7 @@ void setOffloadModuleInterfaceAttributes( if (Opts.OpenMPIsTargetDevice) { offloadMod.setFlags(Opts.OpenMPTargetDebug, Opts.OpenMPTeamSubscription, Opts.OpenMPThreadSubscription, Opts.OpenMPNoThreadState, - Opts.OpenMPNoNestedParallelism, Opts.OpenMPVersion); + Opts.OpenMPNoNestedParallelism, Opts.OpenMPVersion, Opts.NoGPULib); if (!Opts.OMPHostIRFile.empty()) offloadMod.setHostIRFilePath(Opts.OMPHostIRFile); diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index b65b6e31bea8..0732f4bef290 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -935,6 +935,8 @@ static bool parseDialectArgs(CompilerInvocation &res, llvm::opt::ArgList &args, args.hasArg(clang::driver::options::OPT_fopenmp_target_debug)) res.getLangOpts().OpenMPTargetDebug = 1; } + if (args.hasArg(clang::driver::options::OPT_nogpulib)) + res.getLangOpts().NoGPULib = 1; } switch (llvm::Triple(res.getTargetOpts().triple).getArch()) { diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90 index 70bb9f8eb512..ab39dce962c6 100644 --- a/flang/test/Driver/driver-help-hidden.f90 +++ b/flang/test/Driver/driver-help-hidden.f90 @@ -127,6 +127,7 @@ ! CHECK-NEXT: --no-offload-arch= ! CHECK-NEXT: Remove CUDA/HIP offloading device architecture (e.g. sm_35, gfx906) from the list of devices to compile for. 'all' resets the list to its default value. ! CHECK-NEXT: -nocpp Disable predefined and command line preprocessor macros +! CHECK-NEXT: -nogpulib Do not link device library for CUDA/HIP device compilation ! CHECK-NEXT: --offload-arch= Specify an offloading device architecture for CUDA, HIP, or OpenMP. (e.g. sm_35). If 'native' is used the compiler will detect locally installed architectures. For HIP offloading, the device architecture can be followed by target ID features delimited by a colon (e.g. gfx908:xnack+:sramecc-). May be specified more than once. ! CHECK-NEXT: --offload-device-only Only compile for the offloading device. ! CHECK-NEXT: --offload-host-device Compile for both the offloading host and device (default). diff --git a/flang/test/Driver/driver-help.f90 b/flang/test/Driver/driver-help.f90 index 0d760616aace..c1ec2a028d4b 100644 --- a/flang/test/Driver/driver-help.f90 +++ b/flang/test/Driver/driver-help.f90 @@ -113,6 +113,7 @@ ! HELP-NEXT: --no-offload-arch= ! HELP-NEXT: Remove CUDA/HIP offloading device architecture (e.g. sm_35, gfx906) from the list of devices to compile for. 'all' resets the list to its default value. ! HELP-NEXT: -nocpp Disable predefined and command line preprocessor macros +! HELP-NEXT: -nogpulib Do not link device library for CUDA/HIP device compilation ! HELP-NEXT: --offload-arch= Specify an offloading device architecture for CUDA, HIP, or OpenMP. (e.g. sm_35). If 'native' is used the compiler will detect locally installed architectures. For HIP offloading, the device architecture can be followed by target ID features delimited by a colon (e.g. gfx908:xnack+:sramecc-). May be specified more than once. ! HELP-NEXT: --offload-device-only Only compile for the offloading device. ! HELP-NEXT: --offload-host-device Compile for both the offloading host and device (default). @@ -249,6 +250,7 @@ ! HELP-FC1-NEXT: -mvscale-max= Specify the vscale maximum. Defaults to the vector length agnostic value of "0". (AArch64/RISC-V only) ! HELP-FC1-NEXT: -mvscale-min= Specify the vscale minimum. Defaults to "1". (AArch64/RISC-V only) ! HELP-FC1-NEXT: -nocpp Disable predefined and command line preprocessor macros +! HELP-FC1-NEXT: -nogpulib Do not link device library for CUDA/HIP device compilation ! HELP-FC1-NEXT: -opt-record-file ! HELP-FC1-NEXT: File name to use for YAML optimization record output ! HELP-FC1-NEXT: -opt-record-format diff --git a/flang/test/Lower/OpenMP/nogpulib.f90 b/flang/test/Lower/OpenMP/nogpulib.f90 new file mode 100644 index 000000000000..f2e67136ecd7 --- /dev/null +++ b/flang/test/Lower/OpenMP/nogpulib.f90 @@ -0,0 +1,12 @@ +!REQUIRES: amdgpu-registered-target + +!RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s +!RUN: bbc -fopenmp -fopenmp-is-target-device -fopenmp-is-gpu -emit-hlfir -o - %s | FileCheck %s +!RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir -fopenmp -fopenmp-is-target-device -nogpulib %s -o - | FileCheck %s -check-prefix=FLAG_SET +!RUN: bbc -fopenmp -fopenmp-is-target-device -fopenmp-is-gpu -emit-hlfir -nogpulib -o - %s | FileCheck %s -check-prefix=FLAG_SET + +!CHECK-NOT: module attributes {{{.*}}no_gpu_lib +!FLAG_SET: module attributes {{{.*}}no_gpu_lib = true +subroutine omp_subroutine() +end subroutine omp_subroutine + diff --git a/flang/tools/bbc/bbc.cpp b/flang/tools/bbc/bbc.cpp index 0122cf33b0b6..b4ba837a3263 100644 --- a/flang/tools/bbc/bbc.cpp +++ b/flang/tools/bbc/bbc.cpp @@ -181,6 +181,12 @@ static llvm::cl::opt setOpenMPNoNestedParallelism( "a parallel region."), llvm::cl::init(false)); +static llvm::cl::opt + setNoGPULib("nogpulib", + llvm::cl::desc("Do not link device library for CUDA/HIP device " + "compilation"), + llvm::cl::init(false)); + static llvm::cl::opt enableOpenACC("fopenacc", llvm::cl::desc("enable openacc"), llvm::cl::init(false)); @@ -349,7 +355,7 @@ static mlir::LogicalResult convertFortranSourceToMLIR( OffloadModuleOpts(setOpenMPTargetDebug, setOpenMPTeamSubscription, setOpenMPThreadSubscription, setOpenMPNoThreadState, setOpenMPNoNestedParallelism, enableOpenMPDevice, - enableOpenMPGPU, setOpenMPVersion); + enableOpenMPGPU, setOpenMPVersion, "", setNoGPULib); setOffloadModuleInterfaceAttributes(mlirModule, offloadModuleOpts); setOpenMPVersionAttribute(mlirModule, setOpenMPVersion); } diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index b9989b335a2a..d614f2666a85 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -65,6 +65,7 @@ def FlagsAttr : OpenMP_Attr<"Flags", "flags"> { DefaultValuedParameter<"bool", "false">:$assume_threads_oversubscription, DefaultValuedParameter<"bool", "false">:$assume_no_thread_state, DefaultValuedParameter<"bool", "false">:$assume_no_nested_parallelism, + DefaultValuedParameter<"bool", "false">:$no_gpu_lib, DefaultValuedParameter<"uint32_t", "50">:$openmp_device_version ); diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td index 77001fc816cf..89d04af64766 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td @@ -198,11 +198,12 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { "bool":$assumeThreadsOversubscription, "bool":$assumeNoThreadState, "bool":$assumeNoNestedParallelism, - "uint32_t":$openmpDeviceVersion), [{}], [{ + "uint32_t":$openmpDeviceVersion, + "bool":$noGPULib), [{}], [{ $_op->setAttr(("omp." + mlir::omp::FlagsAttr::getMnemonic()).str(), mlir::omp::FlagsAttr::get($_op->getContext(), debugKind, assumeTeamsOversubscription, assumeThreadsOversubscription, - assumeNoThreadState, assumeNoNestedParallelism, openmpDeviceVersion)); + assumeNoThreadState, assumeNoNestedParallelism, noGPULib, openmpDeviceVersion)); }]>, InterfaceMethod< /*description=*/[{ diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index 629584683f49..e7aebc3ce4be 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -2035,6 +2035,12 @@ LogicalResult convertFlagsAttr(Operation *op, mlir::omp::FlagsAttr attribute, llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder(); + ompBuilder->M.addModuleFlag(llvm::Module::Max, "openmp-device", + attribute.getOpenmpDeviceVersion()); + + if (attribute.getNoGpuLib()) + return success(); + ompBuilder->createGlobalFlag( attribute.getDebugKind() /*LangOpts().OpenMPTargetDebug*/, "__omp_rtl_debug_kind"); @@ -2056,8 +2062,6 @@ LogicalResult convertFlagsAttr(Operation *op, mlir::omp::FlagsAttr attribute, .getAssumeNoNestedParallelism() /*LangOpts().OpenMPNoNestedParallelism*/ , "__omp_rtl_assume_no_nested_parallelism"); - ompBuilder->M.addModuleFlag(llvm::Module::Max, "openmp-device", - attribute.getOpenmpDeviceVersion()); return success(); } diff --git a/mlir/test/Dialect/OpenMP/attr.mlir b/mlir/test/Dialect/OpenMP/attr.mlir index 0cb6d0a0badd..a9e4c82fe34a 100644 --- a/mlir/test/Dialect/OpenMP/attr.mlir +++ b/mlir/test/Dialect/OpenMP/attr.mlir @@ -54,6 +54,12 @@ module attributes {omp.flags = #omp.flags} { module attributes {omp.flags = #omp.flags} {} +// CHECK: module attributes {omp.flags = #omp.flags} { +module attributes {omp.flags = #omp.flags} {} + +// CHECK: module attributes {omp.flags = #omp.flags} { +module attributes {omp.flags = #omp.flags} {} + // CHECK: module attributes {omp.version = #omp.version} { module attributes {omp.version = #omp.version} {} diff --git a/mlir/test/Target/LLVMIR/openmp-llvm.mlir b/mlir/test/Target/LLVMIR/openmp-llvm.mlir index 1c02c0265462..29baa84e7e19 100644 --- a/mlir/test/Target/LLVMIR/openmp-llvm.mlir +++ b/mlir/test/Target/LLVMIR/openmp-llvm.mlir @@ -2530,6 +2530,16 @@ module attributes {omp.flags = #omp.flags437 CD1 Is type of class allowed in member function exception specification? - Superseded by 1308 + Superseded by 1308 438 @@ -10607,31 +10607,31 @@ and POD class 1800 CD4 Pointer to member of nested anonymous union - Unknown + Clang 2.9 1801 CD4 Kind of expression referring to member of anonymous union - Unknown + Clang 2.8 1802 CD4 char16_t string literals and surrogate pairs - Unknown + Clang 3.1 1803 CD5 opaque-enum-declaration as member-declaration - Unknown + Clang 2.9 1804 CD4 Partial specialization and friendship - Unknown + Clang 2.7 1805 -- GitLab From c69ec700adec315b3daa55742f2ef655242fa297 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Wed, 10 Jan 2024 00:48:07 -0800 Subject: [PATCH 297/652] [clang-format][NFC] Don't use clang-format style in config files The current CI doesn't use the latest clang-format and fails most clang-format patches on the code formatting check. This patch temporarily removes the clang-format style from the .clang-format files. --- clang/include/clang/Format/.clang-format | 7 ++++++- clang/lib/Format/.clang-format | 7 ++++++- clang/tools/clang-format/.clang-format | 7 ++++++- clang/unittests/Format/.clang-format | 7 ++++++- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/clang/include/clang/Format/.clang-format b/clang/include/clang/Format/.clang-format index d7331b3c8cf0..f95602cab0f7 100644 --- a/clang/include/clang/Format/.clang-format +++ b/clang/include/clang/Format/.clang-format @@ -1 +1,6 @@ -BasedOnStyle: clang-format +BasedOnStyle: LLVM +InsertBraces: true +InsertNewlineAtEOF: true +LineEnding: LF +RemoveBracesLLVM: true +RemoveParentheses: ReturnStatement diff --git a/clang/lib/Format/.clang-format b/clang/lib/Format/.clang-format index d7331b3c8cf0..f95602cab0f7 100644 --- a/clang/lib/Format/.clang-format +++ b/clang/lib/Format/.clang-format @@ -1 +1,6 @@ -BasedOnStyle: clang-format +BasedOnStyle: LLVM +InsertBraces: true +InsertNewlineAtEOF: true +LineEnding: LF +RemoveBracesLLVM: true +RemoveParentheses: ReturnStatement diff --git a/clang/tools/clang-format/.clang-format b/clang/tools/clang-format/.clang-format index d7331b3c8cf0..f95602cab0f7 100644 --- a/clang/tools/clang-format/.clang-format +++ b/clang/tools/clang-format/.clang-format @@ -1 +1,6 @@ -BasedOnStyle: clang-format +BasedOnStyle: LLVM +InsertBraces: true +InsertNewlineAtEOF: true +LineEnding: LF +RemoveBracesLLVM: true +RemoveParentheses: ReturnStatement diff --git a/clang/unittests/Format/.clang-format b/clang/unittests/Format/.clang-format index d7331b3c8cf0..f95602cab0f7 100644 --- a/clang/unittests/Format/.clang-format +++ b/clang/unittests/Format/.clang-format @@ -1 +1,6 @@ -BasedOnStyle: clang-format +BasedOnStyle: LLVM +InsertBraces: true +InsertNewlineAtEOF: true +LineEnding: LF +RemoveBracesLLVM: true +RemoveParentheses: ReturnStatement -- GitLab From 14435a28cd144f157ec4e6022d8c0ff0926e549f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 10 Jan 2024 11:24:19 +0200 Subject: [PATCH 298/652] [OpenMP] Allow setting OPENMP_INSTALL_LIBDIR (#77533) The comment indicate that it should be possible, but as long as it wasn't a cache variable, the cmake script overwrote whatever variable the user had set. --- openmp/CMakeLists.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/openmp/CMakeLists.txt b/openmp/CMakeLists.txt index c1c79f8e0ca9..03068af22629 100644 --- a/openmp/CMakeLists.txt +++ b/openmp/CMakeLists.txt @@ -29,7 +29,8 @@ if (OPENMP_STANDALONE_BUILD) set(OPENMP_LIBDIR_SUFFIX "" CACHE STRING "Suffix of lib installation directory, e.g. 64 => lib64") # Do not use OPENMP_LIBDIR_SUFFIX directly, use OPENMP_INSTALL_LIBDIR. - set(OPENMP_INSTALL_LIBDIR "lib${OPENMP_LIBDIR_SUFFIX}") + set(OPENMP_INSTALL_LIBDIR "lib${OPENMP_LIBDIR_SUFFIX}" CACHE STRING + "Path where built OpenMP libraries should be installed.") # Group test settings. set(OPENMP_TEST_C_COMPILER ${CMAKE_C_COMPILER} CACHE STRING @@ -46,7 +47,8 @@ if (OPENMP_STANDALONE_BUILD) else() set(OPENMP_ENABLE_WERROR ${LLVM_ENABLE_WERROR}) # If building in tree, we honor the same install suffix LLVM uses. - set(OPENMP_INSTALL_LIBDIR "lib${LLVM_LIBDIR_SUFFIX}") + set(OPENMP_INSTALL_LIBDIR "lib${LLVM_LIBDIR_SUFFIX}" CACHE STRING + "Path where built OpenMP libraries should be installed.") if (NOT MSVC) set(OPENMP_TEST_C_COMPILER ${LLVM_RUNTIME_OUTPUT_INTDIR}/clang) -- GitLab From be320fdf7ba9a94f6970f433ec1402cdc5cfe6b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 10 Jan 2024 11:25:17 +0200 Subject: [PATCH 299/652] [libunwind] Convert a few options from CACHE PATH to CACHE STRING (#77534) This applies the same change as in 760261a3daf98882ccbd177e3133fb4a058f47ad (where they were applied to libcxxabi and libcxx) to libunwind as well. These options can reasonably be set either as an absolute or relative path, but if set as type PATH, they are rewritten from relative into absolute relative to the build directory, while the relative form is intended to be relative to the install prefix. --- libunwind/CMakeLists.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt index 248e888619e4..bb1b052f61d8 100644 --- a/libunwind/CMakeLists.txt +++ b/libunwind/CMakeLists.txt @@ -105,9 +105,9 @@ set(CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake" ${CMAKE_MODULE_PATH}) -set(LIBUNWIND_INSTALL_INCLUDE_DIR "${CMAKE_INSTALL_INCLUDEDIR}" CACHE PATH +set(LIBUNWIND_INSTALL_INCLUDE_DIR "${CMAKE_INSTALL_INCLUDEDIR}" CACHE STRING "Path where built libunwind headers should be installed.") -set(LIBUNWIND_INSTALL_RUNTIME_DIR "${CMAKE_INSTALL_BINDIR}" CACHE PATH +set(LIBUNWIND_INSTALL_RUNTIME_DIR "${CMAKE_INSTALL_BINDIR}" CACHE STRING "Path where built libunwind runtime libraries should be installed.") set(LIBUNWIND_SHARED_OUTPUT_NAME "unwind" CACHE STRING "Output name for the shared libunwind runtime library.") @@ -115,7 +115,7 @@ set(LIBUNWIND_STATIC_OUTPUT_NAME "unwind" CACHE STRING "Output name for the stat if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE) set(LIBUNWIND_LIBRARY_DIR ${LLVM_LIBRARY_OUTPUT_INTDIR}/${LLVM_DEFAULT_TARGET_TRIPLE}) - set(LIBUNWIND_INSTALL_LIBRARY_DIR lib${LLVM_LIBDIR_SUFFIX}/${LLVM_DEFAULT_TARGET_TRIPLE} CACHE PATH + set(LIBUNWIND_INSTALL_LIBRARY_DIR lib${LLVM_LIBDIR_SUFFIX}/${LLVM_DEFAULT_TARGET_TRIPLE} CACHE STRING "Path where built libunwind libraries should be installed.") if(LIBCXX_LIBDIR_SUBDIR) string(APPEND LIBUNWIND_LIBRARY_DIR /${LIBUNWIND_LIBDIR_SUBDIR}) @@ -127,7 +127,7 @@ else() else() set(LIBUNWIND_LIBRARY_DIR ${CMAKE_BINARY_DIR}/lib${LIBUNWIND_LIBDIR_SUFFIX}) endif() - set(LIBUNWIND_INSTALL_LIBRARY_DIR lib${LIBUNWIND_LIBDIR_SUFFIX} CACHE PATH + set(LIBUNWIND_INSTALL_LIBRARY_DIR lib${LIBUNWIND_LIBDIR_SUFFIX} CACHE STRING "Path where built libunwind libraries should be installed.") endif() -- GitLab From 65a56a29b6ad3d9df43df1c5a1238b1f870f24f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 10 Jan 2024 11:27:46 +0200 Subject: [PATCH 300/652] [clang] [Driver] Treat MuslEABIHF as a hardfloat environment wrt multiarch directories (#77536) If using multiarch directories with musl, the multiarch directory still uses *-linux-gnu triples - which may or may not be intentional, while it is somewhat consistent at least. However, for musl armhf targets, make sure that this also picks arm-linux-gnueabihf, rather than arm-linux-gnueabi. --- clang/lib/Driver/ToolChains/Gnu.cpp | 8 ++++++-- clang/lib/Driver/ToolChains/Linux.cpp | 8 ++++++-- clang/test/Driver/linux-ld.c | 9 +++++++++ 3 files changed, 21 insertions(+), 4 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 24681dfdc99c..771240dac7a8 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -2668,7 +2668,9 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( case llvm::Triple::arm: case llvm::Triple::thumb: LibDirs.append(begin(ARMLibDirs), end(ARMLibDirs)); - if (TargetTriple.getEnvironment() == llvm::Triple::GNUEABIHF) { + if (TargetTriple.getEnvironment() == llvm::Triple::GNUEABIHF || + TargetTriple.getEnvironment() == llvm::Triple::MuslEABIHF || + TargetTriple.getEnvironment() == llvm::Triple::EABIHF) { TripleAliases.append(begin(ARMHFTriples), end(ARMHFTriples)); } else { TripleAliases.append(begin(ARMTriples), end(ARMTriples)); @@ -2677,7 +2679,9 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( case llvm::Triple::armeb: case llvm::Triple::thumbeb: LibDirs.append(begin(ARMebLibDirs), end(ARMebLibDirs)); - if (TargetTriple.getEnvironment() == llvm::Triple::GNUEABIHF) { + if (TargetTriple.getEnvironment() == llvm::Triple::GNUEABIHF || + TargetTriple.getEnvironment() == llvm::Triple::MuslEABIHF || + TargetTriple.getEnvironment() == llvm::Triple::EABIHF) { TripleAliases.append(begin(ARMebHFTriples), end(ARMebHFTriples)); } else { TripleAliases.append(begin(ARMebTriples), end(ARMebTriples)); diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp index 735af54f114c..4300a2bdff17 100644 --- a/clang/lib/Driver/ToolChains/Linux.cpp +++ b/clang/lib/Driver/ToolChains/Linux.cpp @@ -61,12 +61,16 @@ std::string Linux::getMultiarchTriple(const Driver &D, case llvm::Triple::thumb: if (IsAndroid) return "arm-linux-androideabi"; - if (TargetEnvironment == llvm::Triple::GNUEABIHF) + if (TargetEnvironment == llvm::Triple::GNUEABIHF || + TargetEnvironment == llvm::Triple::MuslEABIHF || + TargetEnvironment == llvm::Triple::EABIHF) return "arm-linux-gnueabihf"; return "arm-linux-gnueabi"; case llvm::Triple::armeb: case llvm::Triple::thumbeb: - if (TargetEnvironment == llvm::Triple::GNUEABIHF) + if (TargetEnvironment == llvm::Triple::GNUEABIHF || + TargetEnvironment == llvm::Triple::MuslEABIHF || + TargetEnvironment == llvm::Triple::EABIHF) return "armeb-linux-gnueabihf"; return "armeb-linux-gnueabi"; case llvm::Triple::x86: diff --git a/clang/test/Driver/linux-ld.c b/clang/test/Driver/linux-ld.c index 15643d6491ae..d5cc3103a3a7 100644 --- a/clang/test/Driver/linux-ld.c +++ b/clang/test/Driver/linux-ld.c @@ -541,6 +541,15 @@ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/ubuntu_12.04_LTS_multiarch_tree \ // RUN: | FileCheck --check-prefix=CHECK-UBUNTU-12-04-ARM-HF %s +// +// Check that musleabihf is treated as a hardfloat config, with respect to +// multiarch directories. +// +// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: --target=arm-unknown-linux-musleabihf -rtlib=platform --unwindlib=platform \ +// RUN: --gcc-toolchain="" \ +// RUN: --sysroot=%S/Inputs/ubuntu_12.04_LTS_multiarch_tree \ +// RUN: | FileCheck --check-prefix=CHECK-UBUNTU-12-04-ARM-HF %s // CHECK-UBUNTU-12-04-ARM-HF: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-UBUNTU-12-04-ARM-HF: "{{.*}}/usr/lib/arm-linux-gnueabihf{{/|\\\\}}crt1.o" // CHECK-UBUNTU-12-04-ARM-HF: "{{.*}}/usr/lib/arm-linux-gnueabihf{{/|\\\\}}crti.o" -- GitLab From ef87e6643ea24103e884a71ec2f5cd2e13e0b454 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 10 Jan 2024 10:29:20 +0100 Subject: [PATCH 301/652] [LVI] Assert that only one value is pushed (NFC) --- llvm/lib/Analysis/LazyValueInfo.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp index 360fc594ef7c..b948eb6ebd12 100644 --- a/llvm/lib/Analysis/LazyValueInfo.cpp +++ b/llvm/lib/Analysis/LazyValueInfo.cpp @@ -539,10 +539,13 @@ void LazyValueInfoImpl::solve() { } std::pair e = BlockValueStack.back(); assert(BlockValueSet.count(e) && "Stack value should be in BlockValueSet!"); + unsigned StackSize = BlockValueStack.size(); + (void) StackSize; if (solveBlockValue(e.second, e.first)) { // The work item was completely processed. - assert(BlockValueStack.back() == e && "Nothing should have been pushed!"); + assert(BlockValueStack.size() == StackSize && + BlockValueStack.back() == e && "Nothing should have been pushed!"); #ifndef NDEBUG std::optional BBLV = TheCache.getCachedValueInfo(e.second, e.first); @@ -556,7 +559,8 @@ void LazyValueInfoImpl::solve() { BlockValueSet.erase(e); } else { // More work needs to be done before revisiting. - assert(BlockValueStack.back() != e && "Stack should have been pushed!"); + assert(BlockValueStack.size() == StackSize + 1 && + "Exactly one element should have been pushed!"); } } } -- GitLab From a6b5d6dab0544892fb6afc46f71677969285c5a8 Mon Sep 17 00:00:00 2001 From: avl-llvm <55248412+avl-llvm@users.noreply.github.com> Date: Wed, 10 Jan 2024 12:39:37 +0300 Subject: [PATCH 302/652] [DWARFLinker] backport line table patch into the DWARFLinkerParallel. (#77497) This patch backports https://github.com/llvm/llvm-project/pull/77016 into the DWARFLinkerParallel. --- .../Parallel/DebugLineSectionEmitter.h | 38 ++++++++++++++++--- .../tools/dsymutil/ARM/inline-source.test | 3 +- 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h b/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h index 545d04cfbe43..1839164dcec1 100644 --- a/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h +++ b/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h @@ -193,24 +193,39 @@ private: Section.emitString(Include.getForm(), *IncludeStr); } + bool HasChecksums = P.ContentTypes.HasMD5; + bool HasInlineSources = P.ContentTypes.HasSource; + + dwarf::Form FileNameForm = dwarf::DW_FORM_string; + dwarf::Form LLVMSourceForm = dwarf::DW_FORM_string; + if (P.FileNames.empty()) { // file_name_entry_format_count (ubyte). Section.emitIntVal(0, 1); } else { + FileNameForm = P.FileNames[0].Name.getForm(); + LLVMSourceForm = P.FileNames[0].Source.getForm(); + // file_name_entry_format_count (ubyte). - Section.emitIntVal(2 + (P.ContentTypes.HasMD5 ? 1 : 0), 1); + Section.emitIntVal( + 2 + (HasChecksums ? 1 : 0) + (HasInlineSources ? 1 : 0), 1); // file_name_entry_format (sequence of ULEB128 pairs). encodeULEB128(dwarf::DW_LNCT_path, Section.OS); - encodeULEB128(P.FileNames[0].Name.getForm(), Section.OS); + encodeULEB128(FileNameForm, Section.OS); encodeULEB128(dwarf::DW_LNCT_directory_index, Section.OS); encodeULEB128(dwarf::DW_FORM_data1, Section.OS); - if (P.ContentTypes.HasMD5) { + if (HasChecksums) { encodeULEB128(dwarf::DW_LNCT_MD5, Section.OS); encodeULEB128(dwarf::DW_FORM_data16, Section.OS); } + + if (HasInlineSources) { + encodeULEB128(dwarf::DW_LNCT_LLVM_source, Section.OS); + encodeULEB128(LLVMSourceForm, Section.OS); + } } // file_names_count (ULEB128). @@ -226,14 +241,27 @@ private: // A null-terminated string containing the full or relative path name of a // source file. - Section.emitString(File.Name.getForm(), *FileNameStr); + Section.emitString(FileNameForm, *FileNameStr); Section.emitIntVal(File.DirIdx, 1); - if (P.ContentTypes.HasMD5) { + if (HasChecksums) { + assert((File.Checksum.size() == 16) && + "checksum size is not equal to 16 bytes."); Section.emitBinaryData( StringRef(reinterpret_cast(File.Checksum.data()), File.Checksum.size())); } + + if (HasInlineSources) { + std::optional FileSourceStr = + dwarf::toString(File.Source); + if (!FileSourceStr) { + U.warn("cann't read string from line table."); + return; + } + + Section.emitString(LLVMSourceForm, *FileSourceStr); + } } } diff --git a/llvm/test/tools/dsymutil/ARM/inline-source.test b/llvm/test/tools/dsymutil/ARM/inline-source.test index ec437e3de900..6f237820e307 100644 --- a/llvm/test/tools/dsymutil/ARM/inline-source.test +++ b/llvm/test/tools/dsymutil/ARM/inline-source.test @@ -2,6 +2,7 @@ # RUN: mkdir -p %t # RUN: llc -filetype=obj -mtriple arm64-apple-darwin %p/../Inputs/inline.ll -o %t/inline.o # RUN: dsymutil -f -oso-prepend-path=%t -y %s -o - | llvm-dwarfdump -debug-line - | FileCheck %s +# RUN: dsymutil --linker=llvm -f -oso-prepend-path=%t -y %s -o - | llvm-dwarfdump -debug-line - | FileCheck %s # Test inline source files. @@ -17,4 +18,4 @@ objects: # CHECK: file_names[ 1]: # CHECK-NEXT: name: "inlined.c" # CHECK-NEXT: dir_index: 1 -# CHECK-NEXT: source: "{{.*}}This is inline source code. \ No newline at end of file +# CHECK-NEXT: source: "{{.*}}This is inline source code. -- GitLab From 7c71a09d5e712bedbed867226b3fa0bbfe789384 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Wed, 10 Jan 2024 17:49:45 +0800 Subject: [PATCH 303/652] [CodeGen][NewPM] Port AssignmentTrackingAnalysis to new pass manager (#77550) --- .../llvm/CodeGen/AssignmentTrackingAnalysis.h | 29 +++++++++++++++- .../include/llvm/CodeGen/CodeGenPassBuilder.h | 1 + .../CodeGen/AssignmentTrackingAnalysis.cpp | 34 +++++++++++++++++++ llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/lib/Passes/PassRegistry.def | 2 ++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/CodeGen/AssignmentTrackingAnalysis.h b/llvm/include/llvm/CodeGen/AssignmentTrackingAnalysis.h index b740ab567b12..fb0ecd828b68 100644 --- a/llvm/include/llvm/CodeGen/AssignmentTrackingAnalysis.h +++ b/llvm/include/llvm/CodeGen/AssignmentTrackingAnalysis.h @@ -1,13 +1,21 @@ +//===-- llvm/CodeGen/AssignmentTrackingAnalysis.h --------------*- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + #ifndef LLVM_CODEGEN_ASSIGNMENTTRACKINGANALYSIS_H #define LLVM_CODEGEN_ASSIGNMENTTRACKINGANALYSIS_H #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DebugLoc.h" #include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/PassManager.h" #include "llvm/Pass.h" namespace llvm { -class Function; class Instruction; class raw_ostream; } // namespace llvm @@ -94,6 +102,25 @@ public: ///@} }; +class DebugAssignmentTrackingAnalysis + : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + +public: + using Result = FunctionVarLocs; + Result run(Function &F, FunctionAnalysisManager &FAM); +}; + +class DebugAssignmentTrackingPrinterPass + : public PassInfoMixin { + raw_ostream &OS; + +public: + DebugAssignmentTrackingPrinterPass(raw_ostream &OS) : OS(OS) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + class AssignmentTrackingAnalysis : public FunctionPass { std::unique_ptr Results; diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index fa81ff504ac6..f540f3774c41 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -23,6 +23,7 @@ #include "llvm/Analysis/ScopedNoAliasAA.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" +#include "llvm/CodeGen/AssignmentTrackingAnalysis.h" #include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/CodeGenPrepare.h" #include "llvm/CodeGen/DwarfEHPrepare.h" diff --git a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp index ad3ad9928987..eb372655e5f1 100644 --- a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp +++ b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp @@ -1,3 +1,11 @@ +//===-- AssignmentTrackingAnalysis.cpp ------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + #include "llvm/CodeGen/AssignmentTrackingAnalysis.h" #include "LiveDebugValues/LiveDebugValues.h" #include "llvm/ADT/BitVector.h" @@ -2553,6 +2561,32 @@ static void analyzeFunction(Function &Fn, const DataLayout &Layout, } } +FunctionVarLocs +DebugAssignmentTrackingAnalysis::run(Function &F, + FunctionAnalysisManager &FAM) { + if (!isAssignmentTrackingEnabled(*F.getParent())) + return FunctionVarLocs(); + + auto &DL = F.getParent()->getDataLayout(); + + FunctionVarLocsBuilder Builder; + analyzeFunction(F, DL, &Builder); + + // Save these results. + FunctionVarLocs Results; + Results.init(Builder); + return Results; +} + +AnalysisKey DebugAssignmentTrackingAnalysis::Key; + +PreservedAnalyses +DebugAssignmentTrackingPrinterPass::run(Function &F, + FunctionAnalysisManager &FAM) { + FAM.getResult(F).print(OS, F); + return PreservedAnalyses::all(); +} + bool AssignmentTrackingAnalysis::runOnFunction(Function &F) { if (!isAssignmentTrackingEnabled(*F.getParent())) return false; diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 27bfe12127cc..bfc97d5464c0 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -72,6 +72,7 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" #include "llvm/Analysis/UniformityAnalysis.h" +#include "llvm/CodeGen/AssignmentTrackingAnalysis.h" #include "llvm/CodeGen/BasicBlockSectionsProfileReader.h" #include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/CodeGenPrepare.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index bda36bd8c107..fbaca001d1fe 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -235,6 +235,7 @@ FUNCTION_ANALYSIS("block-freq", BlockFrequencyAnalysis()) FUNCTION_ANALYSIS("branch-prob", BranchProbabilityAnalysis()) FUNCTION_ANALYSIS("cycles", CycleAnalysis()) FUNCTION_ANALYSIS("da", DependenceAnalysis()) +FUNCTION_ANALYSIS("debug-ata", DebugAssignmentTrackingAnalysis()) FUNCTION_ANALYSIS("demanded-bits", DemandedBitsAnalysis()) FUNCTION_ANALYSIS("domfrontier", DominanceFrontierAnalysis()) FUNCTION_ANALYSIS("domtree", DominatorTreeAnalysis()) @@ -384,6 +385,7 @@ FUNCTION_PASS("print", BranchProbabilityPrinterPass(dbgs())) FUNCTION_PASS("print", CostModelPrinterPass(dbgs())) FUNCTION_PASS("print", CycleInfoPrinterPass(dbgs())) FUNCTION_PASS("print", DependenceAnalysisPrinterPass(dbgs())) +FUNCTION_PASS("print", DebugAssignmentTrackingPrinterPass(dbgs())) FUNCTION_PASS("print", DelinearizationPrinterPass(dbgs())) FUNCTION_PASS("print", DemandedBitsPrinterPass(dbgs())) FUNCTION_PASS("print", DominanceFrontierPrinterPass(dbgs())) -- GitLab From 7ce010f2fb01341ab253547324e126d81d47f794 Mon Sep 17 00:00:00 2001 From: martinboehme Date: Wed, 10 Jan 2024 10:50:16 +0100 Subject: [PATCH 304/652] Revert "[clang][dataflow] Add an early-out to `flowConditionImplies()` / `flowConditionAllows()`." (#77570) Reverts llvm/llvm-project#77453 --- clang/include/clang/Analysis/FlowSensitive/Formula.h | 4 ---- .../lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp | 6 ------ 2 files changed, 10 deletions(-) diff --git a/clang/include/clang/Analysis/FlowSensitive/Formula.h b/clang/include/clang/Analysis/FlowSensitive/Formula.h index 0e6352403a83..982e400c1def 100644 --- a/clang/include/clang/Analysis/FlowSensitive/Formula.h +++ b/clang/include/clang/Analysis/FlowSensitive/Formula.h @@ -75,10 +75,6 @@ public: return static_cast(Value); } - bool isLiteral(bool b) const { - return kind() == Literal && static_cast(Value) == b; - } - ArrayRef operands() const { return ArrayRef(reinterpret_cast(this + 1), numOperands(kind())); diff --git a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp index 500fbb39955d..fa114979c8e3 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp @@ -174,9 +174,6 @@ Solver::Result DataflowAnalysisContext::querySolver( bool DataflowAnalysisContext::flowConditionImplies(Atom Token, const Formula &F) { - if (F.isLiteral(true)) - return true; - // Returns true if and only if truth assignment of the flow condition implies // that `F` is also true. We prove whether or not this property holds by // reducing the problem to satisfiability checking. In other words, we attempt @@ -191,9 +188,6 @@ bool DataflowAnalysisContext::flowConditionImplies(Atom Token, bool DataflowAnalysisContext::flowConditionAllows(Atom Token, const Formula &F) { - if (F.isLiteral(true)) - return true; - llvm::SetVector Constraints; Constraints.insert(&arena().makeAtomRef(Token)); Constraints.insert(&F); -- GitLab From e22cb93890c33e21534338e4f2ea5ce640c78b77 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 10 Jan 2024 09:52:06 +0000 Subject: [PATCH 305/652] [Flang] Any and All elemental lowering (#75776) This is an extension of https://github.com/llvm/llvm-project/pull/75774, with Any and All lowering added alongside Count. --- .../Transforms/OptimizedBufferization.cpp | 34 +++- flang/test/HLFIR/all-elemental.fir | 91 +++++++++ flang/test/HLFIR/any-elemental.fir | 190 ++++++++++++++++++ 3 files changed, 314 insertions(+), 1 deletion(-) create mode 100644 flang/test/HLFIR/all-elemental.fir create mode 100644 flang/test/HLFIR/any-elemental.fir diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp index 72aa86a93427..a7bf25021538 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp @@ -729,7 +729,37 @@ public: mlir::Value init; GenBodyFn genBodyFn; - if constexpr (std::is_same_v) { + if constexpr (std::is_same_v) { + init = builder.createIntegerConstant(loc, builder.getI1Type(), 0); + genBodyFn = [elemental](fir::FirOpBuilder builder, mlir::Location loc, + mlir::Value reduction, + const llvm::SmallVectorImpl &indices) + -> mlir::Value { + // Inline the elemental and get the condition from it. + auto yield = inlineElementalOp(loc, builder, elemental, indices); + mlir::Value cond = builder.create( + loc, builder.getI1Type(), yield.getElementValue()); + yield->erase(); + + // Conditionally set the reduction variable. + return builder.create(loc, reduction, cond); + }; + } else if constexpr (std::is_same_v) { + init = builder.createIntegerConstant(loc, builder.getI1Type(), 1); + genBodyFn = [elemental](fir::FirOpBuilder builder, mlir::Location loc, + mlir::Value reduction, + const llvm::SmallVectorImpl &indices) + -> mlir::Value { + // Inline the elemental and get the condition from it. + auto yield = inlineElementalOp(loc, builder, elemental, indices); + mlir::Value cond = builder.create( + loc, builder.getI1Type(), yield.getElementValue()); + yield->erase(); + + // Conditionally set the reduction variable. + return builder.create(loc, reduction, cond); + }; + } else if constexpr (std::is_same_v) { init = builder.createIntegerConstant(loc, op.getType(), 0); genBodyFn = [elemental](fir::FirOpBuilder builder, mlir::Location loc, mlir::Value reduction, @@ -800,6 +830,8 @@ public: patterns.insert(context); patterns.insert(context); patterns.insert>(context); + patterns.insert>(context); + patterns.insert>(context); if (mlir::failed(mlir::applyPatternsAndFoldGreedily( func, std::move(patterns), config))) { diff --git a/flang/test/HLFIR/all-elemental.fir b/flang/test/HLFIR/all-elemental.fir new file mode 100644 index 000000000000..1ba8bb1b7a5f --- /dev/null +++ b/flang/test/HLFIR/all-elemental.fir @@ -0,0 +1,91 @@ +// RUN: fir-opt %s -opt-bufferization | FileCheck %s + +func.func @_QFPtest(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> !fir.logical<4> { + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca !fir.logical<4> {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4:2 = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) + %5:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = fir.load %2#0 : !fir.ref + %7 = fir.convert %6 : (i32) -> i64 + %8 = fir.shape %c7 : (index) -> !fir.shape<1> + %9 = hlfir.designate %1#0 (%7, %c1:%c7:%c1) shape %8 : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> + %10 = fir.load %5#0 : !fir.ref + %11 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7x!fir.logical<4>> { + ^bb0(%arg3: index): + %14 = hlfir.designate %9 (%arg3) : (!fir.box>, index) -> !fir.ref + %15 = fir.load %14 : !fir.ref + %16 = arith.cmpi sge, %15, %10 : i32 + %17 = fir.convert %16 : (i1) -> !fir.logical<4> + hlfir.yield_element %17 : !fir.logical<4> + } + %12 = hlfir.all %11 : (!hlfir.expr<7x!fir.logical<4>>) -> !fir.logical<4> + hlfir.assign %12 to %4#0 : !fir.logical<4>, !fir.ref> + hlfir.destroy %11 : !hlfir.expr<7x!fir.logical<4>> + %13 = fir.load %4#1 : !fir.ref> + return %13 : !fir.logical<4> +} +// CHECK-LABEL: func.func @_QFPtest(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> !fir.logical<4> { +// CHECK-NEXT: %true = arith.constant true +// CHECK-NEXT: %c1 = arith.constant 1 : index +// CHECK-NEXT: %c4 = arith.constant 4 : index +// CHECK-NEXT: %c7 = arith.constant 7 : index +// CHECK-NEXT: %[[V0:.*]] = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> +// CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %arg0(%[[V0]]) +// CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %arg1 +// CHECK-NEXT: %[[V3:.*]] = fir.alloca !fir.logical<4> +// CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[V3]] +// CHECK-NEXT: %[[V5:.*]]:2 = hlfir.declare %arg2 +// CHECK-NEXT: %[[V6:.*]] = fir.load %[[V2]]#0 : !fir.ref +// CHECK-NEXT: %[[V7:.*]] = fir.convert %[[V6]] : (i32) -> i64 +// CHECK-NEXT: %[[V8:.*]] = fir.shape %c7 : (index) -> !fir.shape<1> +// CHECK-NEXT: %[[V9:.*]] = hlfir.designate %[[V1]]#0 (%[[V7]], %c1:%c7:%c1) shape %[[V8]] : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> +// CHECK-NEXT: %[[V10:.*]] = fir.load %[[V5]]#0 : !fir.ref +// CHECK-NEXT: %[[V11:.*]] = fir.do_loop %arg3 = %c1 to %c7 step %c1 iter_args(%arg4 = %true) -> (i1) { +// CHECK-NEXT: %[[V14:.*]] = hlfir.designate %[[V9]] (%arg3) : (!fir.box>, index) -> !fir.ref +// CHECK-NEXT: %[[V15:.*]] = fir.load %[[V14]] : !fir.ref +// CHECK-NEXT: %[[V16:.*]] = arith.cmpi sge, %[[V15]], %[[V10]] : i32 +// CHECK-NEXT: %[[V17:.*]] = arith.andi %arg4, %[[V16]] : i1 +// CHECK-NEXT: fir.result %[[V17]] : i1 +// CHECK-NEXT: } +// CHECK-NEXT: %[[V12:.*]] = fir.convert %[[V11]] : (i1) -> !fir.logical<4> +// CHECK-NEXT: hlfir.assign %[[V12]] to %[[V4]]#0 : !fir.logical<4>, !fir.ref> +// CHECK-NEXT: %[[V13:.*]] = fir.load %[[V4]]#1 : !fir.ref> +// CHECK-NEXT: return %[[V13]] : !fir.logical<4> + + +func.func @_QFPtest_dim(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> !fir.array<4x!fir.logical<4>> { + %c2_i32 = arith.constant 2 : i32 + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca !fir.array<4x!fir.logical<4>> {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4 = fir.shape %c4 : (index) -> !fir.shape<1> + %5:2 = hlfir.declare %3(%4) {uniq_name = "_QFFtestEtest"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) + %6:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %7 = hlfir.designate %1#0 (%c1:%c4:%c1, %c1:%c7:%c1) shape %0 : (!fir.ref>, index, index, index, index, index, index, !fir.shape<2>) -> !fir.ref> + %8 = fir.load %6#0 : !fir.ref + %9 = hlfir.elemental %0 unordered : (!fir.shape<2>) -> !hlfir.expr<4x7x!fir.logical<4>> { + ^bb0(%arg3: index, %arg4: index): + %12 = hlfir.designate %7 (%arg3, %arg4) : (!fir.ref>, index, index) -> !fir.ref + %13 = fir.load %12 : !fir.ref + %14 = arith.cmpi sge, %13, %8 : i32 + %15 = fir.convert %14 : (i1) -> !fir.logical<4> + hlfir.yield_element %15 : !fir.logical<4> + } + %10 = hlfir.all %9 dim %c2_i32 : (!hlfir.expr<4x7x!fir.logical<4>>, i32) -> !hlfir.expr<4x!fir.logical<4>> + hlfir.assign %10 to %5#0 : !hlfir.expr<4x!fir.logical<4>>, !fir.ref>> + hlfir.destroy %10 : !hlfir.expr<4x!fir.logical<4>> + hlfir.destroy %9 : !hlfir.expr<4x7x!fir.logical<4>> + %11 = fir.load %5#1 : !fir.ref>> + return %11 : !fir.array<4x!fir.logical<4>> +} +// CHECK-LABEL: func.func @_QFPtest_dim( +// CHECK: %10 = hlfir.all %9 dim %c2_i32 \ No newline at end of file diff --git a/flang/test/HLFIR/any-elemental.fir b/flang/test/HLFIR/any-elemental.fir new file mode 100644 index 000000000000..6e233068d2e9 --- /dev/null +++ b/flang/test/HLFIR/any-elemental.fir @@ -0,0 +1,190 @@ +// RUN: fir-opt %s -opt-bufferization | FileCheck %s + +func.func @_QFPtest(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> !fir.logical<4> { + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca !fir.logical<4> {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4:2 = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) + %5:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = fir.load %2#0 : !fir.ref + %7 = fir.convert %6 : (i32) -> i64 + %8 = fir.shape %c7 : (index) -> !fir.shape<1> + %9 = hlfir.designate %1#0 (%7, %c1:%c7:%c1) shape %8 : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> + %10 = fir.load %5#0 : !fir.ref + %11 = hlfir.elemental %8 unordered : (!fir.shape<1>) -> !hlfir.expr<7x!fir.logical<4>> { + ^bb0(%arg3: index): + %14 = hlfir.designate %9 (%arg3) : (!fir.box>, index) -> !fir.ref + %15 = fir.load %14 : !fir.ref + %16 = arith.cmpi sge, %15, %10 : i32 + %17 = fir.convert %16 : (i1) -> !fir.logical<4> + hlfir.yield_element %17 : !fir.logical<4> + } + %12 = hlfir.any %11 : (!hlfir.expr<7x!fir.logical<4>>) -> !fir.logical<4> + hlfir.assign %12 to %4#0 : !fir.logical<4>, !fir.ref> + hlfir.destroy %11 : !hlfir.expr<7x!fir.logical<4>> + %13 = fir.load %4#1 : !fir.ref> + return %13 : !fir.logical<4> +} +// CHECK-LABEL: func.func @_QFPtest(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> !fir.logical<4> { +// CHECK-NEXT: %false = arith.constant false +// CHECK-NEXT: %c1 = arith.constant 1 : index +// CHECK-NEXT: %c4 = arith.constant 4 : index +// CHECK-NEXT: %c7 = arith.constant 7 : index +// CHECK-NEXT: %[[V0:.*]] = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> +// CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %arg0(%[[V0]]) +// CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %arg1 +// CHECK-NEXT: %[[V3:.*]] = fir.alloca !fir.logical<4> +// CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[V3]] +// CHECK-NEXT: %[[V5:.*]]:2 = hlfir.declare %arg2 +// CHECK-NEXT: %[[V6:.*]] = fir.load %[[V2]]#0 : !fir.ref +// CHECK-NEXT: %[[V7:.*]] = fir.convert %[[V6]] : (i32) -> i64 +// CHECK-NEXT: %[[V8:.*]] = fir.shape %c7 : (index) -> !fir.shape<1> +// CHECK-NEXT: %[[V9:.*]] = hlfir.designate %[[V1]]#0 (%[[V7]], %c1:%c7:%c1) shape %[[V8]] : (!fir.ref>, i64, index, index, index, !fir.shape<1>) -> !fir.box> +// CHECK-NEXT: %[[V10:.*]] = fir.load %[[V5]]#0 : !fir.ref +// CHECK-NEXT: %[[V11:.*]] = fir.do_loop %arg3 = %c1 to %c7 step %c1 iter_args(%arg4 = %false) -> (i1) { +// CHECK-NEXT: %[[V14:.*]] = hlfir.designate %[[V9]] (%arg3) : (!fir.box>, index) -> !fir.ref +// CHECK-NEXT: %[[V15:.*]] = fir.load %[[V14]] : !fir.ref +// CHECK-NEXT: %[[V16:.*]] = arith.cmpi sge, %[[V15]], %[[V10]] : i32 +// CHECK-NEXT: %[[V17:.*]] = arith.ori %arg4, %[[V16]] : i1 +// CHECK-NEXT: fir.result %[[V17]] : i1 +// CHECK-NEXT: } +// CHECK-NEXT: %[[V12:.*]] = fir.convert %[[V11]] : (i1) -> !fir.logical<4> +// CHECK-NEXT: hlfir.assign %[[V12]] to %[[V4]]#0 : !fir.logical<4>, !fir.ref> +// CHECK-NEXT: %[[V13:.*]] = fir.load %[[V4]]#1 : !fir.ref> +// CHECK-NEXT: return %[[V13]] : !fir.logical<4> + + +func.func @_QFPtest_dim(%arg0: !fir.ref> {fir.bindc_name = "b"}, %arg1: !fir.ref {fir.bindc_name = "row"}, %arg2: !fir.ref {fir.bindc_name = "val"}) -> !fir.array<4x!fir.logical<4>> { + %c2_i32 = arith.constant 2 : i32 + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %c7 = arith.constant 7 : index + %0 = fir.shape %c4, %c7 : (index, index) -> !fir.shape<2> + %1:2 = hlfir.declare %arg0(%0) {uniq_name = "_QFFtestEb"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) + %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %3 = fir.alloca !fir.array<4x!fir.logical<4>> {bindc_name = "test", uniq_name = "_QFFtestEtest"} + %4 = fir.shape %c4 : (index) -> !fir.shape<1> + %5:2 = hlfir.declare %3(%4) {uniq_name = "_QFFtestEtest"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) + %6:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %7 = hlfir.designate %1#0 (%c1:%c4:%c1, %c1:%c7:%c1) shape %0 : (!fir.ref>, index, index, index, index, index, index, !fir.shape<2>) -> !fir.ref> + %8 = fir.load %6#0 : !fir.ref + %9 = hlfir.elemental %0 unordered : (!fir.shape<2>) -> !hlfir.expr<4x7x!fir.logical<4>> { + ^bb0(%arg3: index, %arg4: index): + %12 = hlfir.designate %7 (%arg3, %arg4) : (!fir.ref>, index, index) -> !fir.ref + %13 = fir.load %12 : !fir.ref + %14 = arith.cmpi sge, %13, %8 : i32 + %15 = fir.convert %14 : (i1) -> !fir.logical<4> + hlfir.yield_element %15 : !fir.logical<4> + } + %10 = hlfir.any %9 dim %c2_i32 : (!hlfir.expr<4x7x!fir.logical<4>>, i32) -> !hlfir.expr<4x!fir.logical<4>> + hlfir.assign %10 to %5#0 : !hlfir.expr<4x!fir.logical<4>>, !fir.ref>> + hlfir.destroy %10 : !hlfir.expr<4x!fir.logical<4>> + hlfir.destroy %9 : !hlfir.expr<4x7x!fir.logical<4>> + %11 = fir.load %5#1 : !fir.ref>> + return %11 : !fir.array<4x!fir.logical<4>> +} +// CHECK-LABEL: func.func @_QFPtest_dim( +// CHECK: {{.*}} = hlfir.any {{.*}} dim %c2_i32 + + +func.func @_Qtest_recursive() attributes {fir.bindc_name = "test"} { + %c1 = arith.constant 1 : index + %true = arith.constant true + %false = arith.constant false + %c0_i64 = arith.constant 0 : i64 + %c2_i32 = arith.constant 2 : i32 + %c0 = arith.constant 0 : index + %c1_i32 = arith.constant 1 : i32 + %0 = fir.address_of(@_QFEa) : !fir.ref>>> + %1:2 = hlfir.declare %0 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) + %2 = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFEi"} + %3:2 = hlfir.declare %2 {uniq_name = "_QFEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %4 = fir.alloca i32 {bindc_name = "n", uniq_name = "_QFEn"} + %5:2 = hlfir.declare %4 {uniq_name = "_QFEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %6 = fir.alloca !fir.array<1x!fir.logical<4>> {bindc_name = "ra", uniq_name = "_QFEra"} + %7 = fir.shape %c1 : (index) -> !fir.shape<1> + %8:2 = hlfir.declare %6(%7) {uniq_name = "_QFEra"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) + %9 = fir.alloca !fir.logical<4> {bindc_name = "rs", uniq_name = "_QFErs"} + %10:2 = hlfir.declare %9 {uniq_name = "_QFErs"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) + %11 = fir.allocmem !fir.array, %c1 {fir.must_be_heap = true, uniq_name = "_QFEa.alloc"} + %12 = fir.embox %11(%7) : (!fir.heap>, !fir.shape<1>) -> !fir.box>> + fir.store %12 to %1#1 : !fir.ref>>> + hlfir.assign %c1_i32 to %5#0 : i32, !fir.ref + %13 = fir.load %1#0 : !fir.ref>>> + %14:3 = fir.box_dims %13, %c0 : (!fir.box>>, index) -> (index, index, index) + fir.do_loop %arg0 = %c1 to %14#1 step %c1 unordered { + %27:3 = fir.box_dims %13, %c0 : (!fir.box>>, index) -> (index, index, index) + %28 = arith.subi %27#0, %c1 : index + %29 = arith.addi %arg0, %28 : index + %30 = hlfir.designate %13 (%29) : (!fir.box>>, index) -> !fir.ref + hlfir.assign %c2_i32 to %30 : i32, !fir.ref + } + %15 = fir.load %5#0 : !fir.ref + %16 = fir.convert %15 : (i32) -> i64 + %17 = arith.cmpi sgt, %16, %c0_i64 : i64 + %18 = arith.select %17, %16, %c0_i64 : i64 + %19 = fir.convert %18 : (i64) -> index + %20 = fir.shape %19 : (index) -> !fir.shape<1> + %21 = hlfir.elemental %20 unordered : (!fir.shape<1>) -> !hlfir.expr> { + ^bb0(%arg0: index): + %27 = fir.load %1#0 : !fir.ref>>> + %28:3 = fir.box_dims %27, %c0 : (!fir.box>>, index) -> (index, index, index) + %29 = arith.addi %28#0, %28#1 : index + %30 = arith.subi %29, %c1 : index + %31 = arith.subi %30, %28#0 : index + %32 = arith.addi %31, %c1 : index + %33 = arith.cmpi sgt, %32, %c0 : index + %34 = arith.select %33, %32, %c0 : index + %35 = fir.shape %34 : (index) -> !fir.shape<1> + %36 = hlfir.designate %27 (%28#0:%30:%c1) shape %35 : (!fir.box>>, index, index, index, !fir.shape<1>) -> !fir.box> + %37 = hlfir.elemental %35 unordered : (!fir.shape<1>) -> !hlfir.expr> { + ^bb0(%arg1: index): + %39 = hlfir.designate %36 (%arg1) : (!fir.box>, index) -> !fir.ref + %40 = fir.load %39 : !fir.ref + %41 = arith.cmpi eq, %40, %c1_i32 : i32 + %42 = fir.convert %41 : (i1) -> !fir.logical<4> + hlfir.yield_element %42 : !fir.logical<4> + } + %38 = hlfir.any %37 : (!hlfir.expr>) -> !fir.logical<4> + hlfir.destroy %37 : !hlfir.expr> + hlfir.yield_element %38 : !fir.logical<4> + } + %22 = hlfir.any %21 : (!hlfir.expr>) -> !fir.logical<4> + hlfir.assign %22 to %10#0 : !fir.logical<4>, !fir.ref> + hlfir.destroy %21 : !hlfir.expr> + %23 = fir.load %10#0 : !fir.ref> + %24 = fir.convert %23 : (!fir.logical<4>) -> i1 + %25 = arith.xori %24, %true : i1 + cf.cond_br %25, ^bb1, ^bb2 +^bb1: // pred: ^bb0 + %26 = fir.call @_FortranAStopStatement(%c2_i32, %false, %false) fastmath : (i32, i1, i1) -> none + fir.unreachable +^bb2: // pred: ^bb0 + return +} +// CHECK-LABEL: func.func @_Qtest_recursive() +// CHECK: %[[V20:.*]] = fir.do_loop %arg0 = %c1 to %{{.*}} step %c1 iter_args(%arg1 = %false) -> (i1) { +// CHECK: %[[V26:.*]] = fir.load %[[V1]]#0 : !fir.ref>>> +// CHECK: %[[V27:.*]]:3 = fir.box_dims %[[V26]], %c0 : (!fir.box>>, index) -> (index, index, index) +// CHECK: %[[V28:.*]] = arith.addi %[[V27]]#0, %[[V27]]#1 : index +// CHECK: %[[V29:.*]] = arith.subi %[[V28]], %c1 : index +// CHECK: %[[V30:.*]] = arith.subi %[[V29]], %[[V27]]#0 : index +// CHECK: %[[V31:.*]] = arith.addi %[[V30]], %c1 : index +// CHECK: %[[V32:.*]] = arith.cmpi sgt, %[[V31]], %c0 : index +// CHECK: %[[V33:.*]] = arith.select %[[V32]], %[[V31]], %c0 : index +// CHECK: %[[V34:.*]] = fir.shape %[[V33]] : (index) -> !fir.shape<1> +// CHECK: %[[V35:.*]] = hlfir.designate %[[V26]] (%[[V27]]#0:%[[V29]]:%c1) shape %[[V34]] : (!fir.box>>, index, index, index, !fir.shape<1>) -> !fir.box> +// CHECK: %[[V36:.*]] = fir.do_loop %arg2 = %c1 to %[[V33]] step %c1 iter_args(%arg3 = %false) -> (i1) { +// CHECK: %[[V38:.*]] = hlfir.designate %[[V35]] (%arg2) : (!fir.box>, index) -> !fir.ref +// CHECK: %[[V39:.*]] = fir.load %[[V38]] : !fir.ref +// CHECK: %[[V40:.*]] = arith.cmpi eq, %[[V39]], %c1_i32 : i32 +// CHECK: %[[V41:.*]] = arith.ori %arg3, %[[V40]] : i1 +// CHECK: fir.result %[[V41]] : i1 +// CHECK: } +// CHECK: %[[V37:.*]] = arith.ori %arg1, %[[V36]] : i1 +// CHECK: fir.result %[[V37]] : i1 +// CHECK: } -- GitLab From a26cc759ae5a8018e2c328cf53173992340b995a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Hana=20Dus=C3=ADkov=C3=A1?= Date: Wed, 10 Jan 2024 11:01:23 +0100 Subject: [PATCH 306/652] [clang][coverage] Fix "if constexpr" and "if consteval" coverage report (#77214) Replace the discarded statement by an empty compound statement so we can keep track of the whole source range we need to skip in coverage Fixes #54419 --- clang/docs/ReleaseNotes.rst | 3 + clang/include/clang/AST/Stmt.h | 6 +- clang/lib/CodeGen/CoverageMappingGen.cpp | 13 ++- clang/lib/Sema/TreeTransform.h | 13 ++- clang/test/CoverageMapping/if.cpp | 108 +++++++++++++++++++---- 5 files changed, 121 insertions(+), 22 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 20872f7ddb81..37f8bbc89d89 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -705,6 +705,9 @@ Bug Fixes in This Version - Fix assertion crash due to failed scope restoring caused by too-early VarDecl invalidation by invalid initializer Expr. Fixes (`#30908 `_) +- Clang now emits correct source location for code-coverage regions in `if constexpr` + and `if consteval` branches. + Fixes (`#54419 `_) Bug Fixes to Compiler Builtins diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h index da7b37ce0e12..e1fde24e6477 100644 --- a/clang/include/clang/AST/Stmt.h +++ b/clang/include/clang/AST/Stmt.h @@ -1631,8 +1631,10 @@ public: SourceLocation RB); // Build an empty compound statement with a location. - explicit CompoundStmt(SourceLocation Loc) - : Stmt(CompoundStmtClass), LBraceLoc(Loc), RBraceLoc(Loc) { + explicit CompoundStmt(SourceLocation Loc) : CompoundStmt(Loc, Loc) {} + + CompoundStmt(SourceLocation Loc, SourceLocation EndLoc) + : Stmt(CompoundStmtClass), LBraceLoc(Loc), RBraceLoc(EndLoc) { CompoundStmtBits.NumStmts = 0; CompoundStmtBits.HasFPFeatures = 0; } diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp b/clang/lib/CodeGen/CoverageMappingGen.cpp index bf227386a71b..b245abd16c3f 100644 --- a/clang/lib/CodeGen/CoverageMappingGen.cpp +++ b/clang/lib/CodeGen/CoverageMappingGen.cpp @@ -1712,7 +1712,11 @@ struct CounterCoverageMappingBuilder extendRegion(S->getCond()); Counter ParentCount = getRegion().getCounter(); - Counter ThenCount = getRegionCounter(S); + + // If this is "if !consteval" the then-branch will never be taken, we don't + // need to change counter + Counter ThenCount = + S->isNegatedConsteval() ? ParentCount : getRegionCounter(S); if (!S->isConsteval()) { // Emitting a counter for the condition makes it easier to interpret the @@ -1729,7 +1733,12 @@ struct CounterCoverageMappingBuilder extendRegion(S->getThen()); Counter OutCount = propagateCounts(ThenCount, S->getThen()); - Counter ElseCount = subtractCounters(ParentCount, ThenCount); + // If this is "if consteval" the else-branch will never be taken, we don't + // need to change counter + Counter ElseCount = S->isNonNegatedConsteval() + ? ParentCount + : subtractCounters(ParentCount, ThenCount); + if (const Stmt *Else = S->getElse()) { bool ThenHasTerminateStmt = HasTerminateStmt; HasTerminateStmt = false; diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index e7a6550b1c99..1a1bc87d2b32 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -7739,7 +7739,11 @@ TreeTransform::TransformIfStmt(IfStmt *S) { if (Then.isInvalid()) return StmtError(); } else { - Then = new (getSema().Context) NullStmt(S->getThen()->getBeginLoc()); + // Discarded branch is replaced with empty CompoundStmt so we can keep + // proper source location for start and end of original branch, so + // subsequent transformations like CoverageMapping work properly + Then = new (getSema().Context) + CompoundStmt(S->getThen()->getBeginLoc(), S->getThen()->getEndLoc()); } // Transform the "else" branch. @@ -7748,6 +7752,13 @@ TreeTransform::TransformIfStmt(IfStmt *S) { Else = getDerived().TransformStmt(S->getElse()); if (Else.isInvalid()) return StmtError(); + } else if (S->getElse() && ConstexprConditionValue && + *ConstexprConditionValue) { + // Same thing here as with branch, we are discarding it, we can't + // replace it with NULL nor NullStmt as we need to keep for source location + // range, for CoverageMapping + Else = new (getSema().Context) + CompoundStmt(S->getElse()->getBeginLoc(), S->getElse()->getEndLoc()); } if (!getDerived().AlwaysRebuild() && diff --git a/clang/test/CoverageMapping/if.cpp b/clang/test/CoverageMapping/if.cpp index 65e3d62df79d..92d560be01f3 100644 --- a/clang/test/CoverageMapping/if.cpp +++ b/clang/test/CoverageMapping/if.cpp @@ -23,19 +23,49 @@ void foo() { // CHECK-NEXT: Gap,File 0, [[@LINE+1]]:21 -> [[@ } // CHECK-NEXT: [[@LINE-2]]:9 -> [[@LINE-1]]:5 = #1 // CHECK-NEXT: [[@LINE-2]]:5 -> [[@LINE-2]]:8 = #1 -// FIXME: Do not generate coverage for discarded branches in if consteval and if constexpr statements -constexpr int check_consteval(int i) { - if consteval { - i++; - } - if !consteval { - i++; - } - if consteval { - return 42; - } else { - return i; - } +// FIXME: Do not generate coverage for discarded branches in if constexpr +// CHECK-LABEL: _Z30check_constexpr_true_with_elsei: +int check_constexpr_true_with_else(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + // CHECK-NEXT: [[@LINE+2]]:16 -> [[@LINE+2]]:20 = #0 + // CHECK-NEXT: Branch,File 0, [[@LINE+1]]:16 -> [[@LINE+1]]:20 = 0, 0 + if constexpr(true) { // CHECK-NEXT: Gap,File 0, [[@LINE]]:21 -> [[@LINE]]:22 = #1 + i *= 3; // CHECK-NEXT: [[@LINE-1]]:22 -> [[@LINE+1]]:4 = #1 + } else { // CHECK-NEXT: Gap,File 0, [[@LINE]]:4 -> [[@LINE]]:10 = (#0 - #1) + i *= 5; // CHECK-NEXT: [[@LINE-1]]:10 -> [[@LINE+1]]:4 = (#0 - #1) + } + return i; +} + +// CHECK-LABEL: _Z33check_constexpr_true_without_elsei: +int check_constexpr_true_without_else(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + // CHECK-NEXT: [[@LINE+2]]:16 -> [[@LINE+2]]:20 = #0 + // CHECK-NEXT: Branch,File 0, [[@LINE+1]]:16 -> [[@LINE+1]]:20 = 0, 0 + if constexpr(true) { // CHECK-NEXT: Gap,File 0, [[@LINE]]:21 -> [[@LINE]]:22 = #1 + i *= 3; // CHECK-NEXT: [[@LINE-1]]:22 -> [[@LINE+1]]:4 = #1 + } + return i; +} + +// CHECK-LABEL: _Z31check_constexpr_false_with_elsei: +int check_constexpr_false_with_else(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + // CHECK-NEXT: [[@LINE+2]]:16 -> [[@LINE+2]]:21 = #0 + // CHECK-NEXT: Branch,File 0, [[@LINE+1]]:16 -> [[@LINE+1]]:21 = 0, 0 + if constexpr(false) { // CHECK-NEXT: Gap,File 0, [[@LINE]]:22 -> [[@LINE]]:23 = #1 + i *= 3; // CHECK-NEXT: File 0, [[@LINE-1]]:23 -> [[@LINE+1]]:4 = #1 + } else { // CHECK-NEXT: Gap,File 0, [[@LINE]]:4 -> [[@LINE]]:10 = (#0 - #1) + i *= 5; // CHECK-NEXT: File 0, [[@LINE-1]]:10 -> [[@LINE+1]]:4 = (#0 - #1) + } + return i; +} + +// CHECK-LABEL: _Z34check_constexpr_false_without_elsei: +int check_constexpr_false_without_else(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + // CHECK-NEXT: [[@LINE+2]]:16 -> [[@LINE+2]]:21 = #0 + // CHECK-NEXT: Branch,File 0, [[@LINE+1]]:16 -> [[@LINE+1]]:21 = 0, 0 + if constexpr(false) { // CHECK-NEXT: Gap,File 0, [[@LINE]]:22 -> [[@LINE]]:23 = #1 + i *= 3; // CHECK-NEXT: File 0, [[@LINE-1]]:23 -> [[@LINE+1]]:4 = #1 + } + return i; } // CHECK-LABEL: main: @@ -75,10 +105,6 @@ int main() { // CHECK: File 0, [[@LINE]]:12 -> {{[0-9]+}}:2 = // CHECK-NEXT: File 0, [[@LINE+1]]:14 -> [[@LINE+1]]:20 = #6 i = i == 0?i + 12:i + 10; // CHECK-NEXT: File 0, [[@LINE]]:21 -> [[@LINE]]:27 = (#0 - #6) - // GH-57377 - constexpr int c_i = check_consteval(0); - check_consteval(i); - // GH-45481 S s; s.the_prop = 0? 1 : 2; // CHECK-NEXT: File 0, [[@LINE]]:16 -> [[@LINE]]:17 = #0 @@ -98,3 +124,51 @@ int main() { // CHECK: File 0, [[@LINE]]:12 -> {{[0-9]+}}:2 = void ternary() { true ? FOO : FOO; // CHECK-NOT: Gap,{{.*}}, [[@LINE]]:8 -> } + +// GH-57377 +// CHECK-LABEL: _Z40check_consteval_with_else_discarded_theni: +// FIXME: Do not generate coverage for discarded branch in if consteval +constexpr int check_consteval_with_else_discarded_then(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + if consteval { + i *= 3; // CHECK-NEXT: [[@LINE-1]]:16 -> [[@LINE+1]]:4 = #1 + } else { // CHECK-NEXT: Gap,File 0, [[@LINE]]:4 -> [[@LINE]]:10 = #0 + i *= 5; // CHECK-NEXT: [[@LINE-1]]:10 -> [[@LINE+1]]:4 = #0 + } + return i; // CHECK-NEXT: [[@LINE]]:3 -> [[@LINE]]:11 = (#0 + #1) +} + +// CHECK-LABEL: _Z43check_notconsteval_with_else_discarded_elsei: +// FIXME: Do not generate coverage for discarded branch in if consteval +constexpr int check_notconsteval_with_else_discarded_else(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + if !consteval { + i *= 3; // CHECK-NEXT: [[@LINE-1]]:17 -> [[@LINE+1]]:4 = #0 + } else { // CHECK-NEXT: Gap,File 0, [[@LINE]]:4 -> [[@LINE]]:10 = 0 + i *= 5; // CHECK-NEXT: [[@LINE-1]]:10 -> [[@LINE+1]]:4 = 0 + } + return i; +} + +// CHECK-LABEL: _Z32check_consteval_branch_discardedi: +// FIXME: Do not generate coverage for discarded branch in if consteval +constexpr int check_consteval_branch_discarded(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + if consteval { + i *= 3; // CHECK-NEXT: [[@LINE-1]]:16 -> [[@LINE+1]]:4 = #1 + } + return i; // CHECK-NEXT: [[@LINE]]:3 -> [[@LINE]]:11 = (#0 + #1) +} + +// CHECK-LABEL: _Z30check_notconsteval_branch_kepti: +constexpr int check_notconsteval_branch_kept(int i) { // CHECK-NEXT: [[@LINE]]:{{[0-9]+}} -> {{[0-9]+}}:2 = #0 + if !consteval { + i *= 3; // CHECK-NEXT: [[@LINE-1]]:17 -> [[@LINE+1]]:4 = #0 + } + return i; +} + +int instantiate_consteval(int i) { + i *= check_consteval_with_else_discarded_then(i); + i *= check_notconsteval_with_else_discarded_else(i); + i *= check_consteval_branch_discarded(i); + i *= check_notconsteval_branch_kept(i); + return i; +} -- GitLab From e2b896aa640fec25f68d283948c1b44711087f0f Mon Sep 17 00:00:00 2001 From: Yi Wu <43659785+yi-wu-arm@users.noreply.github.com> Date: Wed, 10 Jan 2024 10:02:48 +0000 Subject: [PATCH 307/652] [flang] Add EXECUTE_COMMAND_LINE runtime and lowering intrinsics implementation (#74077) This patch add support of intrinsics Fortran 2008 EXECUTE_COMMAND_LINE. The patch contains both the lowering and the runtime code and works on both Windows and Linux. The patch contains a list of commits, to convey the authorship and the history of changes. Some implementation specifics or status has been added to `flang/docs/Intrinsics.md`. I have provided a summary of the usage and the options required for the `EXECUTE_COMMAND_LINE intrinsic`. The intrinsic supports both a synchronous (by default) and an asynchronous option. | System | Mode | Implemention | |---------|-------|---------------------------| | Linux | Sync | std::system() | | Windows | Sync | std::system() | | Linux | Async | fork() | | Windows | Async | CreateProcess | Support for the SYSTEM GNU extension will be added in a separate PR. Co-authored with @jeffhammond --------- Signed-off-by: Jeff Hammond Co-authored-by: Jeff Hammond Co-authored-by: Yi Wu --- flang/docs/Intrinsics.md | 45 ++++ .../flang/Optimizer/Builder/IntrinsicCall.h | 1 + .../flang/Optimizer/Builder/Runtime/Execute.h | 35 +++ flang/include/flang/Runtime/execute.h | 29 +++ flang/lib/Optimizer/Builder/CMakeLists.txt | 1 + flang/lib/Optimizer/Builder/IntrinsicCall.cpp | 43 ++++ .../lib/Optimizer/Builder/Runtime/Execute.cpp | 44 ++++ flang/runtime/CMakeLists.txt | 1 + flang/runtime/command.cpp | 69 ++---- flang/runtime/execute.cpp | 206 ++++++++++++++++++ flang/runtime/tools.cpp | 65 ++++++ flang/runtime/tools.h | 23 ++ .../execute_command_line-optional.f90 | 51 +++++ .../Lower/Intrinsics/execute_command_line.f90 | 53 +++++ flang/unittests/Runtime/CommandTest.cpp | 108 +++++++++ 15 files changed, 719 insertions(+), 55 deletions(-) create mode 100644 flang/include/flang/Optimizer/Builder/Runtime/Execute.h create mode 100644 flang/include/flang/Runtime/execute.h create mode 100644 flang/lib/Optimizer/Builder/Runtime/Execute.cpp create mode 100644 flang/runtime/execute.cpp create mode 100644 flang/test/Lower/Intrinsics/execute_command_line-optional.f90 create mode 100644 flang/test/Lower/Intrinsics/execute_command_line.f90 diff --git a/flang/docs/Intrinsics.md b/flang/docs/Intrinsics.md index 189920a0881b..f5705eb440a7 100644 --- a/flang/docs/Intrinsics.md +++ b/flang/docs/Intrinsics.md @@ -841,3 +841,48 @@ TRIM, UBOUND, UNPACK, VERIFY. Coarray, non standard, IEEE and ISO_C_BINDINGS intrinsic functions that can be used in constant expressions have currently no folding support at all. + +### Standard Intrinsics: EXECUTE_COMMAND_LINE + +#### Usage and Info + +- **Standard:** Fortran 2008 and later, specified in 16.9.73 +- **Class:** Subroutine +- **Syntax:** `CALL EXECUTE_COMMAND_LINE(COMMAND [, WAIT, EXITSTAT, CMDSTAT, CMDMSG ])` +- **Arguments:** + + | Argument | Description | + |-----------|--------------------------------------------------------------| + | `COMMAND` | Shall be a default CHARACTER scalar. | + | `WAIT` | (Optional) Shall be a default LOGICAL scalar. | + | `EXITSTAT`| (Optional) Shall be an INTEGER of the default kind. | + | `CMDSTAT` | (Optional) Shall be an INTEGER of the default kind. | + | `CMDMSG` | (Optional) Shall be a CHARACTER scalar of the default kind. | + +#### Implementation Specifics + +- **`COMMAND`:** + - Must be preset. + +- **`WAIT`:** + - If set to `false`, the command is executed asynchronously. If not preset or set to `false`, it is executed synchronously. + - Sync: achieved by passing command into `std::system` on all systems. + - Async: achieved by calling a `fork()` on POSIX-compatible systems, or `CreateProcess()` on Windows. + +- **`CMDSTAT`:** + - -2: No error condition occurs, but `WAIT` is present with the value `false`, and the processor does not support asynchronous execution. + - -1: The processor does not support command line execution. + - \+ (positive value): An error condition occurs. + - 1: Fork Error, where `pid_t < 0`, would only occur on POSIX-compatible systems. + - 2: Execution Error, a command exits with status -1. + - 3: Invalid Command Error, determined by the exit code depending on the system. + - On Windows, if the exit code is 1. + - On POSIX-compatible systems, if the exit code is 127 or 126. + - 4: Signal error, either it is stopped or killed by signal, would only occur on POSIX-compatible systems. + - 0: Otherwise. + +- **`CMDMSG`:** + - If an error condition occurs, it is assigned an explanatory message. Otherwise, it remains unchanged. + - If a condition occurs that would assign a nonzero value to `CMDSTAT` but the `CMDSTAT` variable is not present, error termination is initiated. + - On POSIX-compatible systems, this applies to both synchronous and asynchronous error termination. When the execution mode is set to async with error termination, the child process (async process) will be terminated with no effect on the parent process (continues). + - On Windows, this only applies to synchronous error termination. diff --git a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h index dba946975e19..80f79d42fc2b 100644 --- a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h @@ -214,6 +214,7 @@ struct IntrinsicLibrary { mlir::Value genDshiftr(mlir::Type, llvm::ArrayRef); fir::ExtendedValue genEoshift(mlir::Type, llvm::ArrayRef); void genExit(llvm::ArrayRef); + void genExecuteCommandLine(mlir::ArrayRef args); mlir::Value genExponent(mlir::Type, llvm::ArrayRef); fir::ExtendedValue genExtendsTypeOf(mlir::Type, llvm::ArrayRef); diff --git a/flang/include/flang/Optimizer/Builder/Runtime/Execute.h b/flang/include/flang/Optimizer/Builder/Runtime/Execute.h new file mode 100644 index 000000000000..a1e6ef208760 --- /dev/null +++ b/flang/include/flang/Optimizer/Builder/Runtime/Execute.h @@ -0,0 +1,35 @@ +//===-- Command.cpp -- generate command line runtime API calls ------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_OPTIMIZER_BUILDER_RUNTIME_EXECUTE_H +#define FORTRAN_OPTIMIZER_BUILDER_RUNTIME_EXECUTE_H + +namespace mlir { +class Value; +class Location; +} // namespace mlir + +namespace fir { +class FirOpBuilder; +} // namespace fir + +namespace fir::runtime { + +/// Generate a call to the ExecuteCommandLine runtime function which implements +/// the GET_EXECUTE_ARGUMENT intrinsic. +/// \p wait must be bool that can be absent. +/// \p exitstat, \p cmdstat and \p cmdmsg must be fir.box that can be +/// absent (but not null mlir values). The status exitstat and cmdstat are +/// returned, along with the message cmdmsg. +void genExecuteCommandLine(fir::FirOpBuilder &, mlir::Location, + mlir::Value command, mlir::Value wait, + mlir::Value exitstat, mlir::Value cmdstat, + mlir::Value cmdmsg); + +} // namespace fir::runtime +#endif // FORTRAN_OPTIMIZER_BUILDER_RUNTIME_EXECUTE_H diff --git a/flang/include/flang/Runtime/execute.h b/flang/include/flang/Runtime/execute.h new file mode 100644 index 000000000000..ca137b9d1823 --- /dev/null +++ b/flang/include/flang/Runtime/execute.h @@ -0,0 +1,29 @@ +//===-- include/flang/Runtime/command.h -------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_RUNTIME_EXECUTE_H_ +#define FORTRAN_RUNTIME_EXECUTE_H_ + +#include "flang/Runtime/entry-names.h" + +namespace Fortran::runtime { +class Descriptor; + +extern "C" { + +// 16.9.83 EXECUTE_COMMAND_LINE +// Execute a command line. +// Returns a EXITSTAT, CMDSTAT, and CMDMSG as described in the standard. +void RTNAME(ExecuteCommandLine)(const Descriptor &command, bool wait = true, + const Descriptor *exitstat = nullptr, const Descriptor *cmdstat = nullptr, + const Descriptor *cmdmsg = nullptr, const char *sourceFile = nullptr, + int line = 0); +} +} // namespace Fortran::runtime + +#endif // FORTRAN_RUNTIME_EXECUTE_H_ diff --git a/flang/lib/Optimizer/Builder/CMakeLists.txt b/flang/lib/Optimizer/Builder/CMakeLists.txt index 9877c6b53792..06339b116cd8 100644 --- a/flang/lib/Optimizer/Builder/CMakeLists.txt +++ b/flang/lib/Optimizer/Builder/CMakeLists.txt @@ -20,6 +20,7 @@ add_flang_library(FIRBuilder Runtime/Derived.cpp Runtime/EnvironmentDefaults.cpp Runtime/Exceptions.cpp + Runtime/Execute.cpp Runtime/Inquiry.cpp Runtime/Intrinsics.cpp Runtime/Numeric.cpp diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index c8057fbdd475..ac7d4fbe23e6 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -26,6 +26,7 @@ #include "flang/Optimizer/Builder/Runtime/Command.h" #include "flang/Optimizer/Builder/Runtime/Derived.h" #include "flang/Optimizer/Builder/Runtime/Exceptions.h" +#include "flang/Optimizer/Builder/Runtime/Execute.h" #include "flang/Optimizer/Builder/Runtime/Inquiry.h" #include "flang/Optimizer/Builder/Runtime/Intrinsics.h" #include "flang/Optimizer/Builder/Runtime/Numeric.h" @@ -213,6 +214,14 @@ static constexpr IntrinsicHandler handlers[]{ {"boundary", asBox, handleDynamicOptional}, {"dim", asValue}}}, /*isElemental=*/false}, + {"execute_command_line", + &I::genExecuteCommandLine, + {{{"command", asBox}, + {"wait", asValue, handleDynamicOptional}, + {"exitstat", asBox, handleDynamicOptional}, + {"cmdstat", asBox, handleDynamicOptional}, + {"cmdmsg", asBox, handleDynamicOptional}}}, + /*isElemental=*/false}, {"exit", &I::genExit, {{{"status", asValue, handleDynamicOptional}}}, @@ -2901,6 +2910,40 @@ IntrinsicLibrary::genEoshift(mlir::Type resultType, return readAndAddCleanUp(resultMutableBox, resultType, "EOSHIFT"); } +// EXECUTE_COMMAND_LINE +void IntrinsicLibrary::genExecuteCommandLine( + llvm::ArrayRef args) { + assert(args.size() == 5); + mlir::Value command = fir::getBase(args[0]); + const fir::ExtendedValue &wait = args[1]; + const fir::ExtendedValue &exitstat = args[2]; + const fir::ExtendedValue &cmdstat = args[3]; + const fir::ExtendedValue &cmdmsg = args[4]; + + if (!command) + fir::emitFatalError(loc, "expected COMMAND parameter"); + + mlir::Type boxNoneTy = fir::BoxType::get(builder.getNoneType()); + + mlir::Value waitBool = isStaticallyPresent(wait) + ? fir::getBase(wait) + : builder.createBool(loc, true); + mlir::Value exitstatBox = + isStaticallyPresent(exitstat) + ? fir::getBase(exitstat) + : builder.create(loc, boxNoneTy).getResult(); + mlir::Value cmdstatBox = + isStaticallyPresent(cmdstat) + ? fir::getBase(cmdstat) + : builder.create(loc, boxNoneTy).getResult(); + mlir::Value cmdmsgBox = + isStaticallyPresent(cmdmsg) + ? fir::getBase(cmdmsg) + : builder.create(loc, boxNoneTy).getResult(); + fir::runtime::genExecuteCommandLine(builder, loc, command, waitBool, + exitstatBox, cmdstatBox, cmdmsgBox); +} + // EXIT void IntrinsicLibrary::genExit(llvm::ArrayRef args) { assert(args.size() == 1); diff --git a/flang/lib/Optimizer/Builder/Runtime/Execute.cpp b/flang/lib/Optimizer/Builder/Runtime/Execute.cpp new file mode 100644 index 000000000000..71ee3996ac0d --- /dev/null +++ b/flang/lib/Optimizer/Builder/Runtime/Execute.cpp @@ -0,0 +1,44 @@ +//===-- Execute.cpp -- generate command line runtime API calls ------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "flang/Optimizer/Builder/Runtime/Execute.h" +#include "flang/Optimizer/Builder/FIRBuilder.h" +#include "flang/Optimizer/Builder/Runtime/RTBuilder.h" +#include "flang/Runtime/execute.h" + +using namespace Fortran::runtime; + +// Certain runtime intrinsics should only be run when select parameters of the +// intrisic are supplied. In certain cases one of these parameters may not be +// given, however the intrinsic needs to be run due to another required +// parameter being supplied. In this case the missing parameter is assigned to +// have an "absent" value. This typically happens in IntrinsicCall.cpp. For this +// reason the extra indirection with `isAbsent` is needed for testing whether a +// given parameter is actually present (so that parameters with "value" absent +// are not considered as present). +inline bool isAbsent(mlir::Value val) { + return mlir::isa_and_nonnull(val.getDefiningOp()); +} + +void fir::runtime::genExecuteCommandLine(fir::FirOpBuilder &builder, + mlir::Location loc, + mlir::Value command, mlir::Value wait, + mlir::Value exitstat, + mlir::Value cmdstat, + mlir::Value cmdmsg) { + auto runtimeFunc = + fir::runtime::getRuntimeFunc(loc, builder); + mlir::FunctionType runtimeFuncTy = runtimeFunc.getFunctionType(); + mlir::Value sourceFile = fir::factory::locationToFilename(builder, loc); + mlir::Value sourceLine = + fir::factory::locationToLineNo(builder, loc, runtimeFuncTy.getInput(6)); + llvm::SmallVector args = fir::runtime::createArguments( + builder, loc, runtimeFuncTy, command, wait, exitstat, cmdstat, cmdmsg, + sourceFile, sourceLine); + builder.create(loc, runtimeFunc, args); +} diff --git a/flang/runtime/CMakeLists.txt b/flang/runtime/CMakeLists.txt index d6df15b7f6e0..dfa9da502db0 100644 --- a/flang/runtime/CMakeLists.txt +++ b/flang/runtime/CMakeLists.txt @@ -105,6 +105,7 @@ set(sources edit-output.cpp environment.cpp exceptions.cpp + execute.cpp extensions.cpp extrema.cpp file.cpp diff --git a/flang/runtime/command.cpp b/flang/runtime/command.cpp index 8e6135b5487c..7c44890545bd 100644 --- a/flang/runtime/command.cpp +++ b/flang/runtime/command.cpp @@ -51,20 +51,6 @@ static std::int64_t StringLength(const char *string) { } } -static bool IsValidCharDescriptor(const Descriptor *value) { - return value && value->IsAllocated() && - value->type() == TypeCode(TypeCategory::Character, 1) && - value->rank() == 0; -} - -static bool IsValidIntDescriptor(const Descriptor *length) { - auto typeCode{length->type().GetCategoryAndKind()}; - // Check that our descriptor is allocated and is a scalar integer with - // kind != 1 (i.e. with a large enough decimal exponent range). - return length->IsAllocated() && length->rank() == 0 && - length->type().IsInteger() && typeCode && typeCode->second != 1; -} - static void FillWithSpaces(const Descriptor &value, std::size_t offset = 0) { if (offset < value.ElementBytes()) { std::memset( @@ -72,26 +58,7 @@ static void FillWithSpaces(const Descriptor &value, std::size_t offset = 0) { } } -static std::int32_t CopyToDescriptor(const Descriptor &value, - const char *rawValue, std::int64_t rawValueLength, const Descriptor *errmsg, - std::size_t offset = 0) { - - std::int64_t toCopy{std::min(rawValueLength, - static_cast(value.ElementBytes() - offset))}; - if (toCopy < 0) { - return ToErrmsg(errmsg, StatValueTooShort); - } - - std::memcpy(value.OffsetElement(offset), rawValue, toCopy); - - if (rawValueLength > toCopy) { - return ToErrmsg(errmsg, StatValueTooShort); - } - - return StatOk; -} - -static std::int32_t CheckAndCopyToDescriptor(const Descriptor *value, +static std::int32_t CheckAndCopyCharsToDescriptor(const Descriptor *value, const char *rawValue, const Descriptor *errmsg, std::size_t &offset) { bool haveValue{IsValidCharDescriptor(value)}; @@ -105,21 +72,13 @@ static std::int32_t CheckAndCopyToDescriptor(const Descriptor *value, std::int32_t stat{StatOk}; if (haveValue) { - stat = CopyToDescriptor(*value, rawValue, len, errmsg, offset); + stat = CopyCharsToDescriptor(*value, rawValue, len, errmsg, offset); } offset += len; return stat; } -static void StoreLengthToDescriptor( - const Descriptor *length, std::int64_t value, Terminator &terminator) { - auto typeCode{length->type().GetCategoryAndKind()}; - int kind{typeCode->second}; - Fortran::runtime::ApplyIntegerKind( - kind, terminator, *length, /* atIndex = */ 0, value); -} - template struct FitsInIntegerKind { bool operator()([[maybe_unused]] std::int64_t value) { if constexpr (KIND >= 8) { @@ -152,7 +111,7 @@ std::int32_t RTNAME(GetCommandArgument)(std::int32_t n, const Descriptor *value, // Store 0 in case we error out later on. if (length) { RUNTIME_CHECK(terminator, IsValidIntDescriptor(length)); - StoreLengthToDescriptor(length, 0, terminator); + StoreIntToDescriptor(length, 0, terminator); } if (n < 0 || n >= executionEnvironment.argc) { @@ -166,11 +125,11 @@ std::int32_t RTNAME(GetCommandArgument)(std::int32_t n, const Descriptor *value, } if (length && FitsInDescriptor(length, argLen, terminator)) { - StoreLengthToDescriptor(length, argLen, terminator); + StoreIntToDescriptor(length, argLen, terminator); } if (value) { - return CopyToDescriptor(*value, arg, argLen, errmsg); + return CopyCharsToDescriptor(*value, arg, argLen, errmsg); } return StatOk; @@ -188,7 +147,7 @@ std::int32_t RTNAME(GetCommand)(const Descriptor *value, // Store 0 in case we error out later on. if (length) { RUNTIME_CHECK(terminator, IsValidIntDescriptor(length)); - StoreLengthToDescriptor(length, 0, terminator); + StoreIntToDescriptor(length, 0, terminator); } auto shouldContinue = [&](std::int32_t stat) -> bool { @@ -200,11 +159,11 @@ std::int32_t RTNAME(GetCommand)(const Descriptor *value, std::size_t offset{0}; if (executionEnvironment.argc == 0) { - return CheckAndCopyToDescriptor(value, "", errmsg, offset); + return CheckAndCopyCharsToDescriptor(value, "", errmsg, offset); } // value = argv[0] - std::int32_t stat{CheckAndCopyToDescriptor( + std::int32_t stat{CheckAndCopyCharsToDescriptor( value, executionEnvironment.argv[0], errmsg, offset)}; if (!shouldContinue(stat)) { return stat; @@ -212,12 +171,12 @@ std::int32_t RTNAME(GetCommand)(const Descriptor *value, // value += " " + argv[1:n] for (std::int32_t i{1}; i < executionEnvironment.argc; ++i) { - stat = CheckAndCopyToDescriptor(value, " ", errmsg, offset); + stat = CheckAndCopyCharsToDescriptor(value, " ", errmsg, offset); if (!shouldContinue(stat)) { return stat; } - stat = CheckAndCopyToDescriptor( + stat = CheckAndCopyCharsToDescriptor( value, executionEnvironment.argv[i], errmsg, offset); if (!shouldContinue(stat)) { return stat; @@ -225,7 +184,7 @@ std::int32_t RTNAME(GetCommand)(const Descriptor *value, } if (length && FitsInDescriptor(length, offset, terminator)) { - StoreLengthToDescriptor(length, offset, terminator); + StoreIntToDescriptor(length, offset, terminator); } // value += spaces for padding @@ -257,7 +216,7 @@ std::int32_t RTNAME(GetEnvVariable)(const Descriptor &name, // Store 0 in case we error out later on. if (length) { RUNTIME_CHECK(terminator, IsValidIntDescriptor(length)); - StoreLengthToDescriptor(length, 0, terminator); + StoreIntToDescriptor(length, 0, terminator); } const char *rawValue{nullptr}; @@ -273,11 +232,11 @@ std::int32_t RTNAME(GetEnvVariable)(const Descriptor &name, std::int64_t varLen{StringLength(rawValue)}; if (length && FitsInDescriptor(length, varLen, terminator)) { - StoreLengthToDescriptor(length, varLen, terminator); + StoreIntToDescriptor(length, varLen, terminator); } if (value) { - return CopyToDescriptor(*value, rawValue, varLen, errmsg); + return CopyCharsToDescriptor(*value, rawValue, varLen, errmsg); } return StatOk; } diff --git a/flang/runtime/execute.cpp b/flang/runtime/execute.cpp new file mode 100644 index 000000000000..48773ae8114b --- /dev/null +++ b/flang/runtime/execute.cpp @@ -0,0 +1,206 @@ +//===-- runtime/execute.cpp -----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "flang/Runtime/execute.h" +#include "environment.h" +#include "stat.h" +#include "terminator.h" +#include "tools.h" +#include "flang/Runtime/descriptor.h" +#include +#include +#include +#ifdef _WIN32 +#define LEAN_AND_MEAN +#define NOMINMAX +#include +#else +#include +#include +#endif + +namespace Fortran::runtime { + +// cmdstat specified in 16.9.73 +// −1 if the processor does not support command line execution, +// a processor-dependent positive value if an error condition occurs +// −2 if no error condition occurs but WAIT is present with the value false +// and the processor does not support asynchronous execution. Otherwise it is +// assigned the value 0 +enum CMD_STAT { + ASYNC_NO_SUPPORT_ERR = -2, + NO_SUPPORT_ERR = -1, + CMD_EXECUTED = 0, + FORK_ERR = 1, + EXECL_ERR = 2, + INVALID_CL_ERR = 3, + SIGNAL_ERR = 4 +}; + +// Override CopyCharsToDescriptor in tools.h, pass string directly +void CopyCharsToDescriptor(const Descriptor &value, const char *rawValue) { + CopyCharsToDescriptor(value, rawValue, std::strlen(rawValue)); +} + +void CheckAndCopyCharsToDescriptor( + const Descriptor *value, const char *rawValue) { + if (value) { + CopyCharsToDescriptor(*value, rawValue); + } +} + +void CheckAndStoreIntToDescriptor( + const Descriptor *intVal, std::int64_t value, Terminator &terminator) { + if (intVal) { + StoreIntToDescriptor(intVal, value, terminator); + } +} + +// If a condition occurs that would assign a nonzero value to CMDSTAT but +// the CMDSTAT variable is not present, error termination is initiated. +int TerminationCheck(int status, const Descriptor *cmdstat, + const Descriptor *cmdmsg, Terminator &terminator) { + if (status == -1) { + if (!cmdstat) { + terminator.Crash("Execution error with system status code: %d", status); + } else { + CheckAndStoreIntToDescriptor(cmdstat, EXECL_ERR, terminator); + CopyCharsToDescriptor(*cmdmsg, "Execution error"); + } + } +#ifdef _WIN32 + // On WIN32 API std::system returns exit status directly + int exitStatusVal{status}; + if (exitStatusVal == 1) { +#else + int exitStatusVal{WEXITSTATUS(status)}; + if (exitStatusVal == 127 || exitStatusVal == 126) { +#endif + if (!cmdstat) { + terminator.Crash( + "Invalid command quit with exit status code: %d", exitStatusVal); + } else { + CheckAndStoreIntToDescriptor(cmdstat, INVALID_CL_ERR, terminator); + CopyCharsToDescriptor(*cmdmsg, "Invalid command line"); + } + } +#if defined(WIFSIGNALED) && defined(WTERMSIG) + if (WIFSIGNALED(status)) { + if (!cmdstat) { + terminator.Crash("killed by signal: %d", WTERMSIG(status)); + } else { + CheckAndStoreIntToDescriptor(cmdstat, SIGNAL_ERR, terminator); + CopyCharsToDescriptor(*cmdmsg, "killed by signal"); + } + } +#endif +#if defined(WIFSTOPPED) && defined(WSTOPSIG) + if (WIFSTOPPED(status)) { + if (!cmdstat) { + terminator.Crash("stopped by signal: %d", WSTOPSIG(status)); + } else { + CheckAndStoreIntToDescriptor(cmdstat, SIGNAL_ERR, terminator); + CopyCharsToDescriptor(*cmdmsg, "stopped by signal"); + } + } +#endif + return exitStatusVal; +} + +void RTNAME(ExecuteCommandLine)(const Descriptor &command, bool wait, + const Descriptor *exitstat, const Descriptor *cmdstat, + const Descriptor *cmdmsg, const char *sourceFile, int line) { + Terminator terminator{sourceFile, line}; + const char *newCmd{EnsureNullTerminated( + command.OffsetElement(), command.ElementBytes(), terminator)}; + + if (exitstat) { + RUNTIME_CHECK(terminator, IsValidIntDescriptor(exitstat)); + } + + if (cmdstat) { + RUNTIME_CHECK(terminator, IsValidIntDescriptor(cmdstat)); + // Assigned 0 as specifed in standard, if error then overwrite + StoreIntToDescriptor(cmdstat, CMD_EXECUTED, terminator); + } + + if (cmdmsg) { + RUNTIME_CHECK(terminator, IsValidCharDescriptor(cmdmsg)); + } + + if (wait) { + // either wait is not specified or wait is true: synchronous mode + int status{std::system(newCmd)}; + int exitStatusVal{TerminationCheck(status, cmdstat, cmdmsg, terminator)}; + // If sync, assigned processor-dependent exit status. Otherwise unchanged + CheckAndStoreIntToDescriptor(exitstat, exitStatusVal, terminator); + } else { +// Asynchronous mode +#ifdef _WIN32 + STARTUPINFO si; + PROCESS_INFORMATION pi; + ZeroMemory(&si, sizeof(si)); + si.cb = sizeof(si); + ZeroMemory(&pi, sizeof(pi)); + + // add "cmd.exe /c " to the beginning of command + const char *prefix{"cmd.exe /c "}; + char *newCmdWin{(char *)AllocateMemoryOrCrash( + terminator, std::strlen(prefix) + std::strlen(newCmd) + 1)}; + std::strcpy(newCmdWin, prefix); + std::strcat(newCmdWin, newCmd); + + // Convert the char to wide char + const size_t sizeNeeded{mbstowcs(NULL, newCmdWin, 0) + 1}; + wchar_t *wcmd{(wchar_t *)AllocateMemoryOrCrash( + terminator, sizeNeeded * sizeof(wchar_t))}; + if (std::mbstowcs(wcmd, newCmdWin, sizeNeeded) == static_cast(-1)) { + terminator.Crash("Char to wide char failed for newCmd"); + } + FreeMemory((void *)newCmdWin); + + if (CreateProcess(nullptr, wcmd, nullptr, nullptr, FALSE, 0, nullptr, + nullptr, &si, &pi)) { + // Close handles so it will be removed when terminated + CloseHandle(pi.hProcess); + CloseHandle(pi.hThread); + } else { + if (!cmdstat) { + terminator.Crash( + "CreateProcess failed with error code: %lu.", GetLastError()); + } else { + StoreIntToDescriptor(cmdstat, (uint32_t)GetLastError(), terminator); + CheckAndCopyCharsToDescriptor(cmdmsg, "CreateProcess failed."); + } + } + FreeMemory((void *)wcmd); +#else + // terminated children do not become zombies + signal(SIGCHLD, SIG_IGN); + pid_t pid{fork()}; + if (pid < 0) { + if (!cmdstat) { + terminator.Crash("Fork failed with pid: %d.", pid); + } else { + StoreIntToDescriptor(cmdstat, FORK_ERR, terminator); + CheckAndCopyCharsToDescriptor(cmdmsg, "Fork failed"); + } + } else if (pid == 0) { + int status{std::system(newCmd)}; + TerminationCheck(status, cmdstat, cmdmsg, terminator); + exit(status); + } +#endif + } + // Deallocate memory if EnsureNullTerminated dynamically allocated memory + if (newCmd != command.OffsetElement()) { + FreeMemory((void *)newCmd); + } +} + +} // namespace Fortran::runtime diff --git a/flang/runtime/tools.cpp b/flang/runtime/tools.cpp index b4e8f9bc890d..6d2d86586c5f 100644 --- a/flang/runtime/tools.cpp +++ b/flang/runtime/tools.cpp @@ -173,5 +173,70 @@ RT_API_ATTRS void ShallowCopy(const Descriptor &to, const Descriptor &from) { ShallowCopy(to, from, to.IsContiguous(), from.IsContiguous()); } +RT_API_ATTRS const char *EnsureNullTerminated( + const char *str, std::size_t length, Terminator &terminator) { + if (std::memchr(str, '\0', length) == nullptr) { + char *newCmd{(char *)AllocateMemoryOrCrash(terminator, length + 1)}; + std::memcpy(newCmd, str, length); + newCmd[length] = '\0'; + return newCmd; + } else { + return str; + } +} + +RT_API_ATTRS bool IsValidCharDescriptor(const Descriptor *value) { + return value && value->IsAllocated() && + value->type() == TypeCode(TypeCategory::Character, 1) && + value->rank() == 0; +} + +RT_API_ATTRS bool IsValidIntDescriptor(const Descriptor *intVal) { + // Check that our descriptor is allocated and is a scalar integer with + // kind != 1 (i.e. with a large enough decimal exponent range). + return intVal && intVal->IsAllocated() && intVal->rank() == 0 && + intVal->type().IsInteger() && intVal->type().GetCategoryAndKind() && + intVal->type().GetCategoryAndKind()->second != 1; +} + +RT_API_ATTRS std::int32_t CopyCharsToDescriptor(const Descriptor &value, + const char *rawValue, std::size_t rawValueLength, const Descriptor *errmsg, + std::size_t offset) { + + const std::int64_t toCopy{std::min(static_cast(rawValueLength), + static_cast(value.ElementBytes() - offset))}; + if (toCopy < 0) { + return ToErrmsg(errmsg, StatValueTooShort); + } + + std::memcpy(value.OffsetElement(offset), rawValue, toCopy); + + if (static_cast(rawValueLength) > toCopy) { + return ToErrmsg(errmsg, StatValueTooShort); + } + + return StatOk; +} + +RT_API_ATTRS void StoreIntToDescriptor( + const Descriptor *length, std::int64_t value, Terminator &terminator) { + auto typeCode{length->type().GetCategoryAndKind()}; + int kind{typeCode->second}; + ApplyIntegerKind( + kind, terminator, *length, /* atIndex = */ 0, value); +} + +template struct FitsInIntegerKind { + RT_API_ATTRS bool operator()([[maybe_unused]] std::int64_t value) { + if constexpr (KIND >= 8) { + return true; + } else { + return value <= + std::numeric_limits< + CppTypeFor>::max(); + } + } +}; + RT_OFFLOAD_API_GROUP_END } // namespace Fortran::runtime diff --git a/flang/runtime/tools.h b/flang/runtime/tools.h index d69079e43701..47398a910ce7 100644 --- a/flang/runtime/tools.h +++ b/flang/runtime/tools.h @@ -10,6 +10,7 @@ #define FORTRAN_RUNTIME_TOOLS_H_ #include "freestanding-tools.h" +#include "stat.h" #include "terminator.h" #include "flang/Runtime/cpp-type.h" #include "flang/Runtime/descriptor.h" @@ -436,6 +437,28 @@ RT_API_ATTRS void ShallowCopy(const Descriptor &to, const Descriptor &from, bool toIsContiguous, bool fromIsContiguous); RT_API_ATTRS void ShallowCopy(const Descriptor &to, const Descriptor &from); +// Ensures that a character string is null-terminated, allocating a /p length +1 +// size memory for null-terminator if necessary. Returns the original or a newly +// allocated null-terminated string (responsibility for deallocation is on the +// caller). +RT_API_ATTRS const char *EnsureNullTerminated( + const char *str, std::size_t length, Terminator &terminator); + +RT_API_ATTRS bool IsValidCharDescriptor(const Descriptor *value); + +RT_API_ATTRS bool IsValidIntDescriptor(const Descriptor *intVal); + +// Copy a null-terminated character array \p rawValue to descriptor \p value. +// The copy starts at the given \p offset, if not present then start at 0. +// If descriptor `errmsg` is provided, error messages will be stored to it. +// Returns stats specified in standard. +RT_API_ATTRS std::int32_t CopyCharsToDescriptor(const Descriptor &value, + const char *rawValue, std::size_t rawValueLength, + const Descriptor *errmsg = nullptr, std::size_t offset = 0); + +RT_API_ATTRS void StoreIntToDescriptor( + const Descriptor *length, std::int64_t value, Terminator &terminator); + // Defines a utility function for copying and padding characters template RT_API_ATTRS void CopyAndPad( diff --git a/flang/test/Lower/Intrinsics/execute_command_line-optional.f90 b/flang/test/Lower/Intrinsics/execute_command_line-optional.f90 new file mode 100644 index 000000000000..e51c0e5fca30 --- /dev/null +++ b/flang/test/Lower/Intrinsics/execute_command_line-optional.f90 @@ -0,0 +1,51 @@ +! RUN: bbc -emit-fir %s -o - | FileCheck %s + +! CHECK-LABEL: func.func @_QPall_args_optional( +! CHECK-SAME: %[[commandArg:.*]]: !fir.boxchar<1> {fir.bindc_name = "command", fir.optional}, +! CHECK-SAME: %[[waitArg:.*]]: !fir.ref> {fir.bindc_name = "iswait", fir.optional}, +! CHECK-SAME: %[[exitstatArg:.*]]: !fir.ref {fir.bindc_name = "exitval", fir.optional}, +! CHECK-SAME: %[[cmdstatArg:.*]]: !fir.ref {fir.bindc_name = "cmdval", fir.optional}, +! CHECK-SAME: %[[cmdmsgArg:.*]]: !fir.boxchar<1> {fir.bindc_name = "msg", fir.optional}) { +subroutine all_args_optional(command, isWait, exitVal, cmdVal, msg) + CHARACTER(*), OPTIONAL :: command, msg + INTEGER, OPTIONAL :: exitVal, cmdVal + LOGICAL, OPTIONAL :: isWait + ! Note: command is not optional in execute_command_line and must be present + call execute_command_line(command, isWait, exitVal, cmdVal, msg) +! CHECK: %[[cmdstatDeclare:.*]] = fir.declare %[[cmdstatArg]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEcmdval"} : (!fir.ref) -> !fir.ref +! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[commandArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEcommand"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[commandBoxTemp:.*]] = fir.emboxchar %[[commandDeclare]], %[[commandUnbox]]#1 : (!fir.ref>, index) -> !fir.boxchar<1> +! CHECK-NEXT: %[[exitstatDeclare:.*]] = fir.declare %[[exitstatArg]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEexitval"} : (!fir.ref) -> !fir.ref +! CHECK-NEXT: %[[waitDeclare:.*]] = fir.declare %[[waitArg]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEiswait"} : (!fir.ref>) -> !fir.ref> +! CHECK-NEXT: %[[cmdmsgUnbox:.*]]:2 = fir.unboxchar %[[cmdmsgArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +! CHECK-NEXT: %[[cmdmsgDeclare:.*]] = fir.declare %[[cmdmsgUnbox]]#0 typeparams %[[cmdmsgUnbox]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEmsg"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[cmdmsgBoxTemp:.*]] = fir.emboxchar %[[cmdmsgDeclare]], %[[cmdmsgUnbox]]#1 : (!fir.ref>, index) -> !fir.boxchar<1> +! CHECK-NEXT: %[[waitIsPresent:.*]] = fir.is_present %[[waitDeclare]] : (!fir.ref>) -> i1 +! CHECK-NEXT: %[[exitstatIsPresent:.*]] = fir.is_present %[[exitstatDeclare]] : (!fir.ref) -> i1 +! CHECK-NEXT: %[[cmdstatIsPresent:.*]] = fir.is_present %[[cmdstatDeclare]] : (!fir.ref) -> i1 +! CHECK-NEXT: %[[cmdmsgIsPresent:.*]] = fir.is_present %[[cmdmsgBoxTemp]] : (!fir.boxchar<1>) -> i1 +! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclare]] typeparams %[[commandUnbox]]#1 : (!fir.ref>, index) -> !fir.box> +! CHECK-NEXT: %[[waitLoaded:.*]] = fir.if %[[waitIsPresent]] -> (!fir.logical<4>) { +! CHECK-NEXT: %[[VAL_31:.*]] = fir.load %[[waitDeclare]] : !fir.ref> +! CHECK-NEXT: fir.result %[[VAL_31]] : !fir.logical<4> +! CHECK-NEXT: } else { +! CHECK-NEXT: %[[VAL_31:.*]] = fir.convert %false : (i1) -> !fir.logical<4> +! CHECK-NEXT: fir.result %[[VAL_31]] : !fir.logical<4> +! CHECK-NEXT: } +! CHECK-NEXT: %[[exitstatArgBox:.*]] = fir.embox %[[exitstatDeclare]] : (!fir.ref) -> !fir.box +! CHECK-NEXT: %[[absentBoxi32:.*]] = fir.absent !fir.box +! CHECK-NEXT: %[[exitstatBox:.*]] = arith.select %[[exitstatIsPresent]], %[[exitstatArgBox]], %[[absentBoxi32]] : !fir.box +! CHECK-NEXT: %[[cmdstatArgBox:.*]] = fir.embox %[[cmdstatDeclare]] : (!fir.ref) -> !fir.box +! CHECK-NEXT: %[[cmdstatBox:.*]] = arith.select %[[cmdstatIsPresent]], %[[cmdstatArgBox]], %[[absentBoxi32]] : !fir.box +! CHECK-NEXT: %[[cmdmsgArgBox:.*]] = fir.embox %[[cmdmsgDeclare]] typeparams %[[cmdmsgUnbox]]#1 : (!fir.ref>, index) -> !fir.box> +! CHECK-NEXT: %[[absentBox:.*]] = fir.absent !fir.box> +! CHECK-NEXT: %[[cmdmsgBox:.*]] = arith.select %[[cmdmsgIsPresent]], %[[cmdmsgArgBox]], %[[absentBox]] : !fir.box> +! CHECK: %[[command:.*]] = fir.convert %[[commandBox]] : (!fir.box>) -> !fir.box +! CHECK-NEXT: %[[wait:.*]] = fir.convert %[[waitLoaded]] : (!fir.logical<4>) -> i1 +! CHECK-NEXT: %[[exitstat:.*]] = fir.convert %[[exitstatBox]] : (!fir.box) -> !fir.box +! CHECK-NEXT: %[[cmdstat:.*]] = fir.convert %[[cmdstatBox]] : (!fir.box) -> !fir.box +! CHECK-NEXT: %[[cmdmsg:.*]] = fir.convert %[[cmdmsgBox]] : (!fir.box>) -> !fir.box +! CHECK: %[[VAL_30:.*]] = fir.call @_FortranAExecuteCommandLine(%[[command]], %[[wait]], %[[exitstat]], %[[cmdstat]], %[[cmdmsg]], %[[VAL_29:.*]], %c14_i32) fastmath : (!fir.box, i1, !fir.box, !fir.box, !fir.box, !fir.ref, i32) -> none +! CHECK-NEXT: return +end subroutine all_args_optional diff --git a/flang/test/Lower/Intrinsics/execute_command_line.f90 b/flang/test/Lower/Intrinsics/execute_command_line.f90 new file mode 100644 index 000000000000..1b65bbd5e155 --- /dev/null +++ b/flang/test/Lower/Intrinsics/execute_command_line.f90 @@ -0,0 +1,53 @@ +! RUN: bbc -emit-fir %s -o - | FileCheck %s + +! CHECK-LABEL: func.func @_QPall_args( +! CHECK-SAME: %[[commandArg:.*]]: !fir.boxchar<1> {fir.bindc_name = "command"}, +! CHECK-SAME: %[[waitArg:.*]]: !fir.ref> {fir.bindc_name = "iswait"}, +! CHECK-SAME: %[[exitstatArg:.*]]: !fir.ref {fir.bindc_name = "exitval"}, +! CHECK-SAME: %[[cmdstatArg:.*]]: !fir.ref {fir.bindc_name = "cmdval"}, +! CHECK-SAME: %[[cmdmsgArg:.*]]: !fir.boxchar<1> {fir.bindc_name = "msg"}) { +subroutine all_args(command, isWait, exitVal, cmdVal, msg) +CHARACTER(30) :: command, msg +INTEGER :: exitVal, cmdVal +LOGICAL :: isWait +call execute_command_line(command, isWait, exitVal, cmdVal, msg) +! CHECK: %[[cmdstatsDeclear:.*]] = fir.declare %[[cmdstatArg]] {uniq_name = "_QFall_argsEcmdval"} : (!fir.ref) -> !fir.ref +! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[commandArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +! CHECK-NEXT: %[[commandCast:.*]] = fir.convert %[[commandUnbox]]#0 : (!fir.ref>) -> !fir.ref> +! CHECK-NEXT: %[[commandDeclear:.*]] = fir.declare %[[commandCast]] typeparams %c30 {uniq_name = "_QFall_argsEcommand"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[exitstatDeclear:.*]] = fir.declare %[[exitstatArg]] {uniq_name = "_QFall_argsEexitval"} : (!fir.ref) -> !fir.ref +! CHECK-NEXT: %[[waitDeclear:.*]] = fir.declare %[[waitArg]] {uniq_name = "_QFall_argsEiswait"} : (!fir.ref>) -> !fir.ref> +! CHECK-NEXT: %[[cmdmsgUnbox:.*]]:2 = fir.unboxchar %[[cmdmsgArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +! CHECK-NEXT: %[[cmdmsgCast:.*]] = fir.convert %[[cmdmsgUnbox]]#0 : (!fir.ref>) -> !fir.ref> +! CHECK-NEXT: %[[cmdmsgDeclear:.*]] = fir.declare %[[cmdmsgCast]] typeparams %c30 {uniq_name = "_QFall_argsEmsg"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclear]] : (!fir.ref>) -> !fir.box> +! CHECK-NEXT: %[[waitLoaded:.*]] = fir.load %[[waitDeclear]] : !fir.ref> +! CHECK-NEXT: %[[exitstatBox:.*]] = fir.embox %[[exitstatDeclear]] : (!fir.ref) -> !fir.box +! CHECK-NEXT: %[[cmdstatBox:.*]] = fir.embox %[[cmdstatsDeclear]] : (!fir.ref) -> !fir.box +! CHECK-NEXT: %[[cmdmsgBox:.*]] = fir.embox %[[cmdmsgDeclear]] : (!fir.ref>) -> !fir.box> +! CHECK: %[[command:.*]] = fir.convert %[[commandBox]] : (!fir.box>) -> !fir.box +! CHECK-NEXT: %[[wait:.*]] = fir.convert %[[waitLoaded]] : (!fir.logical<4>) -> i1 +! CHECK-NEXT: %[[exitstat:.*]] = fir.convert %[[exitstatBox]] : (!fir.box) -> !fir.box +! CHECK-NEXT: %[[cmdstat:.*]] = fir.convert %[[cmdstatBox]] : (!fir.box) -> !fir.box +! CHECK-NEXT: %[[cmdmsg:.*]] = fir.convert %[[cmdmsgBox]] : (!fir.box>) -> !fir.box +! CHECK: %[[VAL_21:.*]] = fir.call @_FortranAExecuteCommandLine(%[[command]], %[[wait]], %[[exitstat]], %[[cmdstat]], %[[cmdmsg]], %[[VAL_20:.*]], %c13_i32) fastmath : (!fir.box, i1, !fir.box, !fir.box, !fir.box, !fir.ref, i32) -> none +! CHECK-NEXT: return +end subroutine all_args + +! CHECK-LABEL: func.func @_QPonly_command_default_wait_true( +! CHECK-SAME: %[[cmdArg:.*]]: !fir.boxchar<1> {fir.bindc_name = "command"}) { +subroutine only_command_default_wait_true(command) +CHARACTER(30) :: command +call execute_command_line(command) +! CHECK-NEXT: %c41_i32 = arith.constant 41 : i32 +! CHECK-NEXT: %true = arith.constant true +! CHECK-NEXT: %c30 = arith.constant 30 : index +! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[cmdArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +! CHECK-NEXT: %[[commandCast:.*]] = fir.convert %[[commandUnbox]]#0 : (!fir.ref>) -> !fir.ref> +! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandCast]] typeparams %c30 {uniq_name = "_QFonly_command_default_wait_trueEcommand"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclare]] : (!fir.ref>) -> !fir.box> +! CHECK-NEXT: %[[absent:.*]] = fir.absent !fir.box +! CHECK: %[[command:.*]] = fir.convert %[[commandBox]] : (!fir.box>) -> !fir.box +! CHECK: %[[VAL_21:.*]] = fir.call @_FortranAExecuteCommandLine(%[[command]], %true, %[[absent]], %[[absent]], %[[absent]], %[[VAL_7:.*]], %c41_i32) fastmath : (!fir.box, i1, !fir.box, !fir.box, !fir.box, !fir.ref, i32) -> none +! CHECK-NEXT: return +end subroutine only_command_default_wait_true diff --git a/flang/unittests/Runtime/CommandTest.cpp b/flang/unittests/Runtime/CommandTest.cpp index dfc3ad68b3ab..50b11d7fe8a0 100644 --- a/flang/unittests/Runtime/CommandTest.cpp +++ b/flang/unittests/Runtime/CommandTest.cpp @@ -10,6 +10,7 @@ #include "gmock/gmock.h" #include "gtest/gtest.h" #include "flang/Runtime/descriptor.h" +#include "flang/Runtime/execute.h" #include "flang/Runtime/extensions.h" #include "flang/Runtime/main.h" #include @@ -52,6 +53,17 @@ static OwningPtr EmptyIntDescriptor() { return descriptor; } +template +static OwningPtr IntDescriptor(const int &value) { + OwningPtr descriptor{Descriptor::Create(TypeCategory::Integer, + kind, nullptr, 0, nullptr, CFI_attribute_allocatable)}; + if (descriptor->Allocate() != 0) { + return nullptr; + } + std::memcpy(descriptor->OffsetElement(), &value, sizeof(int)); + return descriptor; +} + class CommandFixture : public ::testing::Test { protected: CommandFixture(int argc, const char *argv[]) { @@ -240,6 +252,102 @@ TEST_F(ZeroArguments, GetCommandArgument) { TEST_F(ZeroArguments, GetCommand) { CheckCommandValue(commandOnlyArgv, 1); } +TEST_F(ZeroArguments, ECLValidCommandAndPadSync) { + OwningPtr command{CharDescriptor("echo hi")}; + bool wait{true}; + OwningPtr exitStat{EmptyIntDescriptor()}; + OwningPtr cmdStat{EmptyIntDescriptor()}; + OwningPtr cmdMsg{CharDescriptor("No change")}; + + RTNAME(ExecuteCommandLine) + (*command.get(), wait, exitStat.get(), cmdStat.get(), cmdMsg.get()); + + std::string spaces(cmdMsg->ElementBytes(), ' '); + CheckDescriptorEqInt(exitStat.get(), 0); + CheckDescriptorEqInt(cmdStat.get(), 0); + CheckDescriptorEqStr(cmdMsg.get(), "No change"); +} + +TEST_F(ZeroArguments, ECLValidCommandStatusSetSync) { + OwningPtr command{CharDescriptor("echo hi")}; + bool wait{true}; + OwningPtr exitStat{IntDescriptor(404)}; + OwningPtr cmdStat{IntDescriptor(202)}; + OwningPtr cmdMsg{CharDescriptor("No change")}; + + RTNAME(ExecuteCommandLine) + (*command.get(), wait, exitStat.get(), cmdStat.get(), cmdMsg.get()); + + CheckDescriptorEqInt(exitStat.get(), 0); + CheckDescriptorEqInt(cmdStat.get(), 0); + CheckDescriptorEqStr(cmdMsg.get(), "No change"); +} + +TEST_F(ZeroArguments, ECLInvalidCommandErrorSync) { + OwningPtr command{CharDescriptor("InvalidCommand")}; + bool wait{true}; + OwningPtr exitStat{IntDescriptor(404)}; + OwningPtr cmdStat{IntDescriptor(202)}; + OwningPtr cmdMsg{CharDescriptor("Message ChangedXXXXXXXXX")}; + + RTNAME(ExecuteCommandLine) + (*command.get(), wait, exitStat.get(), cmdStat.get(), cmdMsg.get()); +#ifdef _WIN32 + CheckDescriptorEqInt(exitStat.get(), 1); +#else + CheckDescriptorEqInt(exitStat.get(), 127); +#endif + CheckDescriptorEqInt(cmdStat.get(), 3); + CheckDescriptorEqStr(cmdMsg.get(), "Invalid command lineXXXX"); +} + +TEST_F(ZeroArguments, ECLInvalidCommandTerminatedSync) { + OwningPtr command{CharDescriptor("InvalidCommand")}; + bool wait{true}; + OwningPtr exitStat{IntDescriptor(404)}; + OwningPtr cmdMsg{CharDescriptor("No Change")}; + +#ifdef _WIN32 + EXPECT_DEATH(RTNAME(ExecuteCommandLine)( + *command.get(), wait, exitStat.get(), nullptr, cmdMsg.get()), + "Invalid command quit with exit status code: 1"); +#else + EXPECT_DEATH(RTNAME(ExecuteCommandLine)( + *command.get(), wait, exitStat.get(), nullptr, cmdMsg.get()), + "Invalid command quit with exit status code: 127"); +#endif + CheckDescriptorEqInt(exitStat.get(), 404); + CheckDescriptorEqStr(cmdMsg.get(), "No Change"); +} + +TEST_F(ZeroArguments, ECLValidCommandAndExitStatNoChangeAndCMDStatusSetAsync) { + OwningPtr command{CharDescriptor("echo hi")}; + bool wait{false}; + OwningPtr exitStat{IntDescriptor(404)}; + OwningPtr cmdStat{IntDescriptor(202)}; + OwningPtr cmdMsg{CharDescriptor("No change")}; + + RTNAME(ExecuteCommandLine) + (*command.get(), wait, exitStat.get(), cmdStat.get(), cmdMsg.get()); + + CheckDescriptorEqInt(exitStat.get(), 404); + CheckDescriptorEqInt(cmdStat.get(), 0); + CheckDescriptorEqStr(cmdMsg.get(), "No change"); +} + +TEST_F(ZeroArguments, ECLInvalidCommandParentNotTerminatedAsync) { + OwningPtr command{CharDescriptor("InvalidCommand")}; + bool wait{false}; + OwningPtr exitStat{IntDescriptor(404)}; + OwningPtr cmdMsg{CharDescriptor("No change")}; + + EXPECT_NO_FATAL_FAILURE(RTNAME(ExecuteCommandLine)( + *command.get(), wait, exitStat.get(), nullptr, cmdMsg.get())); + + CheckDescriptorEqInt(exitStat.get(), 404); + CheckDescriptorEqStr(cmdMsg.get(), "No change"); +} + static const char *oneArgArgv[]{"aProgram", "anArgumentOfLength20"}; class OneArgument : public CommandFixture { protected: -- GitLab From ccaf9e0bc0a4739170584d995f9de98bf3beb1f9 Mon Sep 17 00:00:00 2001 From: David Sherwood <57997763+david-arm@users.noreply.github.com> Date: Wed, 10 Jan 2024 10:03:14 +0000 Subject: [PATCH 308/652] [AArch64] Enable AArch64 loop idiom transform pass (#77480) Following on from https://github.com/llvm/llvm-project/pull/72273 which added the new AArch64 loop idiom transformation pass, this patch enables the pass by default for AArch64. --- llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp | 2 +- .../test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp index 6fcd9c290e9c..6c6cd120b035 100644 --- a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp @@ -53,7 +53,7 @@ using namespace PatternMatch; #define DEBUG_TYPE "aarch64-loop-idiom-transform" static cl::opt - DisableAll("disable-aarch64-lit-all", cl::Hidden, cl::init(true), + DisableAll("disable-aarch64-lit-all", cl::Hidden, cl::init(false), cl::desc("Disable AArch64 Loop Idiom Transform Pass.")); static cl::opt DisableByteCmp( diff --git a/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll b/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll index 8f011e2d00a0..1767f2c0bd97 100644 --- a/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll +++ b/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -aarch64-lit -disable-aarch64-lit-all=false -aarch64-lit-verify -verify-dom-info -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s -; RUN: opt -aarch64-lit -disable-aarch64-lit-all=false -simplifycfg -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s --check-prefix=LOOP-DEL -; RUN: opt -aarch64-lit -disable-aarch64-lit-all=false -mtriple aarch64-unknown-linux-gnu -S < %s | FileCheck %s --check-prefix=NO-TRANSFORM +; RUN: opt -aarch64-lit -aarch64-lit-verify -verify-dom-info -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s +; RUN: opt -aarch64-lit -simplifycfg -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s --check-prefix=LOOP-DEL +; RUN: opt -aarch64-lit -mtriple aarch64-unknown-linux-gnu -S < %s | FileCheck %s --check-prefix=NO-TRANSFORM define i32 @compare_bytes_simple(ptr %a, ptr %b, i32 %len, i32 %extra, i32 %n) { ; CHECK-LABEL: define i32 @compare_bytes_simple( -- GitLab From 38394a3d0b8b9a1fdc444bdebeba17a19250997d Mon Sep 17 00:00:00 2001 From: Lu Weining Date: Wed, 10 Jan 2024 18:03:52 +0800 Subject: [PATCH 309/652] [lld][LoongArch] Handle extreme code model relocs according to psABI v2.30 (#73387) psABI v2.30 requires the extreme code model instructions sequence (pcalau12i+addi.d+lu32i.d+lu52i.d) to be adjacent. See https://github.com/llvm/llvm-project/pull/71907 and https://github.com/loongson-community/discussions/issues/17 for details. --- lld/ELF/Arch/LoongArch.cpp | 110 +++++++--------------------- lld/ELF/InputSection.cpp | 10 +-- lld/ELF/Target.h | 2 +- lld/test/ELF/loongarch-pc-aligned.s | 109 ++++++++++++++------------- 4 files changed, 93 insertions(+), 138 deletions(-) diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp index 996f9957a63c..ab2ec5b447d0 100644 --- a/lld/ELF/Arch/LoongArch.cpp +++ b/lld/ELF/Arch/LoongArch.cpp @@ -82,89 +82,33 @@ static uint64_t getLoongArchPage(uint64_t p) { static uint32_t lo12(uint32_t val) { return val & 0xfff; } // Calculate the adjusted page delta between dest and PC. -uint64_t elf::getLoongArchPageDelta(uint64_t dest, uint64_t pc) { - // Consider the large code model access pattern, of which the smaller code - // models' access patterns are a subset: - // - // pcalau12i U, %foo_hi20(sym) ; b in [-0x80000, 0x7ffff] - // addi.d T, zero, %foo_lo12(sym) ; a in [-0x800, 0x7ff] - // lu32i.d T, %foo64_lo20(sym) ; c in [-0x80000, 0x7ffff] - // lu52i.d T, T, %foo64_hi12(sym) ; d in [-0x800, 0x7ff] - // {ldx,stx,add}.* dest, U, T - // - // Let page(pc) = 0xRRR'QQQQQ'PPPPP'000 and dest = 0xZZZ'YYYYY'XXXXX'AAA, - // with RQ, P, ZY, X and A representing the respective bitfields as unsigned - // integers. We have: - // - // page(dest) = 0xZZZ'YYYYY'XXXXX'000 - // - page(pc) = 0xRRR'QQQQQ'PPPPP'000 - // ---------------------------------- - // 0xddd'ccccc'bbbbb'000 - // - // Now consider the above pattern's actual effects: - // - // page(pc) 0xRRR'QQQQQ'PPPPP'000 - // pcalau12i + 0xiii'iiiii'bbbbb'000 - // addi + 0xjjj'jjjjj'kkkkk'AAA - // lu32i.d & lu52i.d + 0xddd'ccccc'00000'000 - // -------------------------------------------------- - // dest = U + T - // = ((RQ<<32) + (P<<12) + i + (b<<12)) + (j + k + A + (cd<<32)) - // = (((RQ+cd)<<32) + i + j) + (((P+b)<<12) + k) + A - // = (ZY<<32) + (X<<12) + A - // - // ZY<<32 = (RQ<<32)+(cd<<32)+i+j, X<<12 = (P<<12)+(b<<12)+k - // cd<<32 = (ZY<<32)-(RQ<<32)-i-j, b<<12 = (X<<12)-(P<<12)-k - // - // where i and k are terms representing the effect of b's and A's sign - // extension respectively. - // - // i = signed b < 0 ? -0x10000'0000 : 0 - // k = signed A < 0 ? -0x1000 : 0 - // - // The j term is a bit complex: it represents the higher half of - // sign-extended bits from A that are effectively lost if i == 0 but k != 0, - // due to overwriting by lu32i.d & lu52i.d. - // - // j = signed A < 0 && signed b >= 0 ? 0x10000'0000 : 0 - // - // The actual effect of the instruction sequence before the final addition, - // i.e. our desired result value, is thus: - // - // result = (cd<<32) + (b<<12) - // = (ZY<<32)-(RQ<<32)-i-j + (X<<12)-(P<<12)-k - // = ((ZY<<32)+(X<<12)) - ((RQ<<32)+(P<<12)) - i - j - k - // = page(dest) - page(pc) - i - j - k - // - // when signed A >= 0 && signed b >= 0: - // - // i = j = k = 0 - // result = page(dest) - page(pc) - // - // when signed A >= 0 && signed b < 0: - // - // i = -0x10000'0000, j = k = 0 - // result = page(dest) - page(pc) + 0x10000'0000 - // - // when signed A < 0 && signed b >= 0: - // - // i = 0, j = 0x10000'0000, k = -0x1000 - // result = page(dest) - page(pc) - 0x10000'0000 + 0x1000 - // - // when signed A < 0 && signed b < 0: - // - // i = -0x10000'0000, j = 0, k = -0x1000 - // result = page(dest) - page(pc) + 0x1000 - uint64_t result = getLoongArchPage(dest) - getLoongArchPage(pc); - bool negativeA = lo12(dest) > 0x7ff; - bool negativeB = (result & 0x8000'0000) != 0; - - if (negativeA) - result += 0x1000; - if (negativeA && !negativeB) - result -= 0x10000'0000; - else if (!negativeA && negativeB) - result += 0x10000'0000; +uint64_t elf::getLoongArchPageDelta(uint64_t dest, uint64_t pc, RelType type) { + // Note that if the sequence being relocated is `pcalau12i + addi.d + lu32i.d + // + lu52i.d`, they must be adjancent so that we can infer the PC of + // `pcalau12i` when calculating the page delta for the other two instructions + // (lu32i.d and lu52i.d). Compensate all the sign-extensions is a bit + // complicated. Just use psABI recommended algorithm. + uint64_t pcalau12i_pc; + switch (type) { + case R_LARCH_PCALA64_LO20: + case R_LARCH_GOT64_PC_LO20: + case R_LARCH_TLS_IE64_PC_LO20: + pcalau12i_pc = pc - 8; + break; + case R_LARCH_PCALA64_HI12: + case R_LARCH_GOT64_PC_HI12: + case R_LARCH_TLS_IE64_PC_HI12: + pcalau12i_pc = pc - 12; + break; + default: + pcalau12i_pc = pc; + break; + } + uint64_t result = getLoongArchPage(dest) - getLoongArchPage(pcalau12i_pc); + if (dest & 0x800) + result += 0x1000 - 0x1'0000'0000; + if (result & 0x8000'0000) + result += 0x1'0000'0000; return result; } diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index 53b496bd0842..586404643cc1 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -716,8 +716,8 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, return sym.getGotVA() + a - p; case R_LOONGARCH_GOT_PAGE_PC: if (sym.hasFlag(NEEDS_TLSGD)) - return getLoongArchPageDelta(in.got->getGlobalDynAddr(sym) + a, p); - return getLoongArchPageDelta(sym.getGotVA() + a, p); + return getLoongArchPageDelta(in.got->getGlobalDynAddr(sym) + a, p, type); + return getLoongArchPageDelta(sym.getGotVA() + a, p, type); case R_MIPS_GOTREL: return sym.getVA(a) - in.mipsGot->getGp(file); case R_MIPS_GOT_GP: @@ -767,7 +767,7 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, return 0; } case R_LOONGARCH_PAGE_PC: - return getLoongArchPageDelta(sym.getVA(a), p); + return getLoongArchPageDelta(sym.getVA(a), p, type); case R_PC: case R_ARM_PCA: { uint64_t dest; @@ -802,7 +802,7 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, case R_PPC64_CALL_PLT: return sym.getPltVA() + a - p; case R_LOONGARCH_PLT_PAGE_PC: - return getLoongArchPageDelta(sym.getPltVA() + a, p); + return getLoongArchPageDelta(sym.getPltVA() + a, p, type); case R_PLT_GOTPLT: return sym.getPltVA() + a - in.gotPlt->getVA(); case R_PPC32_PLTREL: @@ -864,7 +864,7 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, case R_TLSGD_PC: return in.got->getGlobalDynAddr(sym) + a - p; case R_LOONGARCH_TLSGD_PAGE_PC: - return getLoongArchPageDelta(in.got->getGlobalDynAddr(sym) + a, p); + return getLoongArchPageDelta(in.got->getGlobalDynAddr(sym) + a, p, type); case R_TLSLD_GOTPLT: return in.got->getVA() + in.got->getTlsIndexOff() + a - in.gotPlt->getVA(); case R_TLSLD_GOT: diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h index af7aaff8a4c0..ab6b6b9c013b 100644 --- a/lld/ELF/Target.h +++ b/lld/ELF/Target.h @@ -228,7 +228,7 @@ void addPPC64SaveRestore(); uint64_t getPPC64TocBase(); uint64_t getAArch64Page(uint64_t expr); template void writeARMCmseImportLib(); -uint64_t getLoongArchPageDelta(uint64_t dest, uint64_t pc); +uint64_t getLoongArchPageDelta(uint64_t dest, uint64_t pc, RelType type); void riscvFinalizeRelax(int passes); void mergeRISCVAttributesSections(); void addArmInputSectionMappingSymbols(); diff --git a/lld/test/ELF/loongarch-pc-aligned.s b/lld/test/ELF/loongarch-pc-aligned.s index e7950400a5c8..0405961e5f74 100644 --- a/lld/test/ELF/loongarch-pc-aligned.s +++ b/lld/test/ELF/loongarch-pc-aligned.s @@ -75,8 +75,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x4443333334567111 --section-start=.text=0x0000000012345678 -o %t/extreme0 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme0 | FileCheck %s --check-prefix=EXTREME0 -# EXTREME0: addi.d $t0, $zero, 273 -# EXTREME0-NEXT: pcalau12i $t1, 139810 +# EXTREME0: pcalau12i $t1, 139810 +# EXTREME0-NEXT: addi.d $t0, $zero, 273 # EXTREME0-NEXT: lu32i.d $t0, 209715 # EXTREME0-NEXT: lu52i.d $t0, $t0, 1092 @@ -87,8 +87,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x4443333334567888 --section-start=.text=0x0000000012345678 -o %t/extreme1 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme1 | FileCheck %s --check-prefix=EXTREME1 -# EXTREME1: addi.d $t0, $zero, -1912 -# EXTREME1-NEXT: pcalau12i $t1, 139811 +# EXTREME1: pcalau12i $t1, 139811 +# EXTREME1-NEXT: addi.d $t0, $zero, -1912 # EXTREME1-NEXT: lu32i.d $t0, 209714 # EXTREME1-NEXT: lu52i.d $t0, $t0, 1092 @@ -99,8 +99,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x44433333abcde111 --section-start=.text=0x0000000012345678 -o %t/extreme2 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme2 | FileCheck %s --check-prefix=EXTREME2 -# EXTREME2: addi.d $t0, $zero, 273 -# EXTREME2-NEXT: pcalau12i $t1, -419431 +# EXTREME2: pcalau12i $t1, -419431 +# EXTREME2-NEXT: addi.d $t0, $zero, 273 # EXTREME2-NEXT: lu32i.d $t0, 209716 # EXTREME2-NEXT: lu52i.d $t0, $t0, 1092 @@ -111,8 +111,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x44433333abcde888 --section-start=.text=0x0000000012345678 -o %t/extreme3 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme3 | FileCheck %s --check-prefix=EXTREME3 -# EXTREME3: addi.d $t0, $zero, -1912 -# EXTREME3-NEXT: pcalau12i $t1, -419430 +# EXTREME3: pcalau12i $t1, -419430 +# EXTREME3-NEXT: addi.d $t0, $zero, -1912 # EXTREME3-NEXT: lu32i.d $t0, 209715 # EXTREME3-NEXT: lu52i.d $t0, $t0, 1092 @@ -123,8 +123,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x444aaaaa34567111 --section-start=.text=0x0000000012345678 -o %t/extreme4 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme4 | FileCheck %s --check-prefix=EXTREME4 -# EXTREME4: addi.d $t0, $zero, 273 -# EXTREME4-NEXT: pcalau12i $t1, 139810 +# EXTREME4: pcalau12i $t1, 139810 +# EXTREME4-NEXT: addi.d $t0, $zero, 273 # EXTREME4-NEXT: lu32i.d $t0, -349526 # EXTREME4-NEXT: lu52i.d $t0, $t0, 1092 @@ -135,8 +135,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x444aaaaa34567888 --section-start=.text=0x0000000012345678 -o %t/extreme5 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme5 | FileCheck %s --check-prefix=EXTREME5 -# EXTREME5: addi.d $t0, $zero, -1912 -# EXTREME5-NEXT: pcalau12i $t1, 139811 +# EXTREME5: pcalau12i $t1, 139811 +# EXTREME5-NEXT: addi.d $t0, $zero, -1912 # EXTREME5-NEXT: lu32i.d $t0, -349527 # EXTREME5-NEXT: lu52i.d $t0, $t0, 1092 @@ -147,8 +147,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x444aaaaaabcde111 --section-start=.text=0x0000000012345678 -o %t/extreme6 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme6 | FileCheck %s --check-prefix=EXTREME6 -# EXTREME6: addi.d $t0, $zero, 273 -# EXTREME6-NEXT: pcalau12i $t1, -419431 +# EXTREME6: pcalau12i $t1, -419431 +# EXTREME6-NEXT: addi.d $t0, $zero, 273 # EXTREME6-NEXT: lu32i.d $t0, -349525 # EXTREME6-NEXT: lu52i.d $t0, $t0, 1092 @@ -159,8 +159,8 @@ ## %pc64_hi12 = 0x444 = 1092 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x444aaaaaabcde888 --section-start=.text=0x0000000012345678 -o %t/extreme7 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme7 | FileCheck %s --check-prefix=EXTREME7 -# EXTREME7: addi.d $t0, $zero, -1912 -# EXTREME7-NEXT: pcalau12i $t1, -419430 +# EXTREME7: pcalau12i $t1, -419430 +# EXTREME7-NEXT: addi.d $t0, $zero, -1912 # EXTREME7-NEXT: lu32i.d $t0, -349526 # EXTREME7-NEXT: lu52i.d $t0, $t0, 1092 @@ -171,8 +171,8 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbb3333334567111 --section-start=.text=0x0000000012345678 -o %t/extreme8 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme8 | FileCheck %s --check-prefix=EXTREME8 -# EXTREME8: addi.d $t0, $zero, 273 -# EXTREME8-NEXT: pcalau12i $t1, 139810 +# EXTREME8: pcalau12i $t1, 139810 +# EXTREME8-NEXT: addi.d $t0, $zero, 273 # EXTREME8-NEXT: lu32i.d $t0, 209715 # EXTREME8-NEXT: lu52i.d $t0, $t0, -1093 @@ -183,8 +183,8 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbb3333334567888 --section-start=.text=0x0000000012345678 -o %t/extreme9 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme9 | FileCheck %s --check-prefix=EXTREME9 -# EXTREME9: addi.d $t0, $zero, -1912 -# EXTREME9-NEXT: pcalau12i $t1, 139811 +# EXTREME9: pcalau12i $t1, 139811 +# EXTREME9-NEXT: addi.d $t0, $zero, -1912 # EXTREME9-NEXT: lu32i.d $t0, 209714 # EXTREME9-NEXT: lu52i.d $t0, $t0, -1093 @@ -195,8 +195,8 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbb33333abcde111 --section-start=.text=0x0000000012345678 -o %t/extreme10 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme10 | FileCheck %s --check-prefix=EXTREME10 -# EXTREME10: addi.d $t0, $zero, 273 -# EXTREME10-NEXT: pcalau12i $t1, -419431 +# EXTREME10: pcalau12i $t1, -419431 +# EXTREME10-NEXT: addi.d $t0, $zero, 273 # EXTREME10-NEXT: lu32i.d $t0, 209716 # EXTREME10-NEXT: lu52i.d $t0, $t0, -1093 @@ -207,8 +207,8 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbb33333abcde888 --section-start=.text=0x0000000012345678 -o %t/extreme11 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme11 | FileCheck %s --check-prefix=EXTREME11 -# EXTREME11: addi.d $t0, $zero, -1912 -# EXTREME11-NEXT: pcalau12i $t1, -419430 +# EXTREME11: pcalau12i $t1, -419430 +# EXTREME11-NEXT: addi.d $t0, $zero, -1912 # EXTREME11-NEXT: lu32i.d $t0, 209715 # EXTREME11-NEXT: lu52i.d $t0, $t0, -1093 @@ -219,8 +219,8 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbbaaaaa34567111 --section-start=.text=0x0000000012345678 -o %t/extreme12 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme12 | FileCheck %s --check-prefix=EXTREME12 -# EXTREME12: addi.d $t0, $zero, 273 -# EXTREME12-NEXT: pcalau12i $t1, 139810 +# EXTREME12: pcalau12i $t1, 139810 +# EXTREME12-NEXT: addi.d $t0, $zero, 273 # EXTREME12-NEXT: lu32i.d $t0, -349526 # EXTREME12-NEXT: lu52i.d $t0, $t0, -1093 @@ -231,8 +231,8 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbbaaaaa34567888 --section-start=.text=0x0000000012345678 -o %t/extreme13 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme13 | FileCheck %s --check-prefix=EXTREME13 -# EXTREME13: addi.d $t0, $zero, -1912 -# EXTREME13-NEXT: pcalau12i $t1, 139811 +# EXTREME13: pcalau12i $t1, 139811 +# EXTREME13-NEXT: addi.d $t0, $zero, -1912 # EXTREME13-NEXT: lu32i.d $t0, -349527 # EXTREME13-NEXT: lu52i.d $t0, $t0, -1093 @@ -243,8 +243,8 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbbaaaaaabcde111 --section-start=.text=0x0000000012345678 -o %t/extreme14 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme14 | FileCheck %s --check-prefix=EXTREME14 -# EXTREME14: addi.d $t0, $zero, 273 -# EXTREME14-NEXT: pcalau12i $t1, -419431 +# EXTREME14: pcalau12i $t1, -419431 +# EXTREME14-NEXT: addi.d $t0, $zero, 273 # EXTREME14-NEXT: lu32i.d $t0, -349525 # EXTREME14-NEXT: lu52i.d $t0, $t0, -1093 @@ -255,36 +255,47 @@ ## %pc64_hi12 = 0xbbb = -1093 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0xbbbaaaaaabcde888 --section-start=.text=0x0000000012345678 -o %t/extreme15 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme15 | FileCheck %s --check-prefix=EXTREME15 -# EXTREME15: addi.d $t0, $zero, -1912 -# EXTREME15-NEXT: pcalau12i $t1, -419430 +# EXTREME15: pcalau12i $t1, -419430 +# EXTREME15-NEXT: addi.d $t0, $zero, -1912 # EXTREME15-NEXT: lu32i.d $t0, -349526 # EXTREME15-NEXT: lu52i.d $t0, $t0, -1093 -## FIXME: Correct %pc64_lo20 should be 0xfffff (-1) and %pc64_hi12 should be 0xfff (-1), but current values are: -## page delta = 0x0000000000000000, page offset = 0x888 +## page delta = 0xffffffff00000000, page offset = 0x888 ## %pc_lo12 = 0x888 = -1912 ## %pc_hi20 = 0x00000 = 0 -## %pc64_lo20 = 0x00000 = 0 -## %pc64_hi12 = 0x00000 = 0 +## %pc64_lo20 = 0xfffff = -1 +## %pc64_hi12 = 0xfff = -1 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x0000000012344888 --section-start=.text=0x0000000012345678 -o %t/extreme16 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme16 | FileCheck %s --check-prefix=EXTREME16 -# EXTREME16: addi.d $t0, $zero, -1912 -# EXTREME16-NEXT: pcalau12i $t1, 0 -# EXTREME16-NEXT: lu32i.d $t0, 0 -# EXTREME16-NEXT: lu52i.d $t0, $t0, 0 +# EXTREME16: pcalau12i $t1, 0 +# EXTREME16-NEXT: addi.d $t0, $zero, -1912 +# EXTREME16-NEXT: lu32i.d $t0, -1 +# EXTREME16-NEXT: lu52i.d $t0, $t0, -1 -## FIXME: Correct %pc64_lo20 should be 0x00000 (0) and %pc64_hi12 should be 0x000 (0), but current values are: -## page delta = 0xffffffff80000000, page offset = 0x888 +## page delta = 0x0000000080000000, page offset = 0x888 ## %pc_lo12 = 0x888 = -1912 ## %pc_hi20 = 0x80000 = -524288 -## %pc64_lo20 = 0xfffff = -1 -## %pc64_hi12 = 0xfff = -1 +## %pc64_lo20 = 0xfffff = 0 +## %pc64_hi12 = 0xfff = 0 # RUN: ld.lld %t/extreme.o --section-start=.rodata=0x000071238ffff888 --section-start=.text=0x0000712310000678 -o %t/extreme17 # RUN: llvm-objdump -d --no-show-raw-insn %t/extreme17 | FileCheck %s --check-prefix=EXTREME17 -# EXTREME17: addi.d $t0, $zero, -1912 -# EXTREME17-NEXT: pcalau12i $t1, -524288 -# EXTREME17-NEXT: lu32i.d $t0, -1 -# EXTREME17-NEXT: lu52i.d $t0, $t0, -1 +# EXTREME17: pcalau12i $t1, -524288 +# EXTREME17-NEXT: addi.d $t0, $zero, -1912 +# EXTREME17-NEXT: lu32i.d $t0, 0 +# EXTREME17-NEXT: lu52i.d $t0, $t0, 0 + +## A case that pcalau12i, lu32i.d and lu52i.d are in different pages. +## page delta = 0x0000000080000000, page offset = 0x123 +## %pc_lo12 = 0x111 = 273 +## %pc_hi20 = 0x80000 = -524288 +## %pc64_lo20 = 0x00001 = 1 +## %pc64_hi12 = 0x000 = 0 +# RUN: ld.lld %t/extreme.o --section-start=.rodata=0x80000111 --section-start=.text=0xff8 -o %t/extreme18 +# RUN: llvm-objdump -d --no-show-raw-insn %t/extreme18 | FileCheck %s --check-prefix=EXTREME18 +# EXTREME18: pcalau12i $t1, -524288 +# EXTREME18-NEXT: addi.d $t0, $zero, 273 +# EXTREME18-NEXT: lu32i.d $t0, 1 +# EXTREME18-NEXT: lu52i.d $t0, $t0, 0 #--- a.s .rodata @@ -303,7 +314,7 @@ x: .text .global _start _start: - addi.d $t0, $zero, %pc_lo12(x) pcalau12i $t1, %pc_hi20(x) + addi.d $t0, $zero, %pc_lo12(x) lu32i.d $t0, %pc64_lo20(x) lu52i.d $t0, $t0, %pc64_hi12(x) -- GitLab From 53d48902bc6b05cc284f767089fe070ada651910 Mon Sep 17 00:00:00 2001 From: Benjamin Maxwell Date: Wed, 10 Jan 2024 10:11:44 +0000 Subject: [PATCH 310/652] [mlir][ArmSME] Add arm_sme.streaming_vl operation (#77321) This operation provides a convenient way to query the streaming vector length regardless of the streaming mode. This most useful for functions that call/pass data to streaming functions, but are not streaming themselves. Example: ```mlir %svl_w = arm_sme.streaming_vl ``` Created based on discussion here: https://github.com/llvm/llvm-project/pull/76086#discussion_r1434226352 --- .../mlir/Dialect/ArmSME/IR/ArmSMEOps.td | 44 +++++++++++++++++ .../Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp | 47 +++++++++++++++++-- .../ArmSMEToLLVM/arm-sme-to-llvm.mlir | 42 +++++++++++++++++ mlir/test/Dialect/ArmSME/roundtrip.mlir | 36 ++++++++++++++ 4 files changed, 166 insertions(+), 3 deletions(-) diff --git a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td index f7cc1d3fe751..bb0db59add00 100644 --- a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td +++ b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td @@ -223,6 +223,21 @@ def ArmSME_CombiningKindAttr : EnumAttr, + I32EnumAttrCase<"Half" , 1, "half">, + I32EnumAttrCase<"Word" , 2, "word">, + I32EnumAttrCase<"Double", 3, "double">, +]> { + let cppNamespace = "::mlir::arm_sme"; + let genSpecializedAttr = 0; +} + +def ArmSME_TypeSizeAttr : EnumAttr { + let assemblyFormat = "`<` $value `>`"; +} + //===----------------------------------------------------------------------===// // ArmSME op definitions //===----------------------------------------------------------------------===// @@ -768,4 +783,33 @@ let arguments = (ins }]; } +def StreamingVLOp : ArmSME_Op<"streaming_vl", [Pure]> +{ + let summary = "Query the streaming vector length"; + + let description = [{ + This operation returns the streaming vector length (SVL) for a given type + size. Unlike `vector.vscale` the value returned is invariant to the + streaming mode. + + Example: + ```mlir + // Streaming vector length in: + // - bytes (8-bit, SVL.B) + %svl_b = arm_sme.streaming_vl + // - half words (16-bit, SVL.H) + %svl_h = arm_sme.streaming_vl + // - words (32-bit, SVL.W) + %svl_w = arm_sme.streaming_vl + // - double words (64-bit, SVL.D) + %svl_d = arm_sme.streaming_vl + ``` + }]; + + let arguments = (ins ArmSME_TypeSizeAttr: $type_size); + let results = (outs Index); + + let assemblyFormat = "$type_size attr-dict"; +} + #endif // ARMSME_OPS diff --git a/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp b/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp index 0c6e2e80b88a..0bb7ccb463e4 100644 --- a/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp +++ b/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp @@ -518,6 +518,45 @@ struct OuterProductOpConversion } }; +/// Lower `arm_sme.streaming_vl` to SME CNTS intrinsics. +/// +/// Example: +/// +/// %0 = arm_sme.streaming_vl +/// +/// is converted to: +/// +/// %cnt = "arm_sme.intr.cntsh"() : () -> i64 +/// %0 = arith.index_cast %cnt : i64 to index +/// +struct StreamingVLOpConversion + : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(arm_sme::StreamingVLOp streamingVlOp, + arm_sme::StreamingVLOp::Adaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + auto loc = streamingVlOp.getLoc(); + auto i64Type = rewriter.getI64Type(); + auto *intrOp = [&]() -> Operation * { + switch (streamingVlOp.getTypeSize()) { + case arm_sme::TypeSize::Byte: + return rewriter.create(loc, i64Type); + case arm_sme::TypeSize::Half: + return rewriter.create(loc, i64Type); + case arm_sme::TypeSize::Word: + return rewriter.create(loc, i64Type); + case arm_sme::TypeSize::Double: + return rewriter.create(loc, i64Type); + } + }(); + rewriter.replaceOpWithNewOp( + streamingVlOp, rewriter.getIndexType(), intrOp->getResult(0)); + return success(); + } +}; + } // namespace namespace { @@ -555,7 +594,9 @@ void mlir::configureArmSMEToLLVMConversionLegality(ConversionTarget &target) { arm_sme::aarch64_sme_st1w_vert, arm_sme::aarch64_sme_st1d_vert, arm_sme::aarch64_sme_st1q_vert, arm_sme::aarch64_sme_read_horiz, arm_sme::aarch64_sme_read_vert, arm_sme::aarch64_sme_write_horiz, - arm_sme::aarch64_sme_write_vert, arm_sme::aarch64_sme_mopa>(); + arm_sme::aarch64_sme_write_vert, arm_sme::aarch64_sme_mopa, + arm_sme::aarch64_sme_cntsb, arm_sme::aarch64_sme_cntsh, + arm_sme::aarch64_sme_cntsw, arm_sme::aarch64_sme_cntsd>(); target.addLegalDialect(); target.addLegalOp(); } @@ -572,8 +613,8 @@ void mlir::populateArmSMEToLLVMConversionPatterns(LLVMTypeConverter &converter, patterns.add( - converter); + OuterProductOpConversion, ZeroOpConversion, GetTileConversion, + StreamingVLOpConversion>(converter); } std::unique_ptr mlir::createConvertArmSMEToLLVMPass() { diff --git a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir index bd88da37bdf9..f9cf77ca15ff 100644 --- a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir +++ b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir @@ -559,3 +559,45 @@ func.func @arm_sme_move_tile_slice_to_vector_ver_i128(%tile_slice_index : index) %slice = arm_sme.move_tile_slice_to_vector %tile[%tile_slice_index] layout : vector<[1]xi128> from vector<[1]x[1]xi128> return %slice : vector<[1]xi128> } + +//===----------------------------------------------------------------------===// +// arm_sme.streaming_vl +//===----------------------------------------------------------------------===// + +// ----- + +// CHECK-LABEL: @arm_sme_streaming_vl_bytes +// CHECK: %[[COUNT:.*]] = "arm_sme.intr.cntsb"() : () -> i64 +// CHECK: %[[INDEX_COUNT:.*]] = arith.index_cast %[[COUNT]] : i64 to index +// CHECK: return %[[INDEX_COUNT]] : index +func.func @arm_sme_streaming_vl_bytes() -> index { + %svl_b = arm_sme.streaming_vl + return %svl_b : index +} + +// ----- + +// CHECK-LABEL: @arm_sme_streaming_vl_half_words +// CHECK: "arm_sme.intr.cntsh"() : () -> i64 +func.func @arm_sme_streaming_vl_half_words() -> index { + %svl_h = arm_sme.streaming_vl + return %svl_h : index +} + +// ----- + +// CHECK-LABEL: @arm_sme_streaming_vl_words +// CHECK: "arm_sme.intr.cntsw"() : () -> i64 +func.func @arm_sme_streaming_vl_words() -> index { + %svl_w = arm_sme.streaming_vl + return %svl_w : index +} + +// ----- + +// CHECK-LABEL: @arm_sme_streaming_vl_double_words +// CHECK: "arm_sme.intr.cntsd"() : () -> i64 +func.func @arm_sme_streaming_vl_double_words() -> index { + %svl_d = arm_sme.streaming_vl + return %svl_d : index +} diff --git a/mlir/test/Dialect/ArmSME/roundtrip.mlir b/mlir/test/Dialect/ArmSME/roundtrip.mlir index 58ff7ef4d834..2ad742493408 100644 --- a/mlir/test/Dialect/ArmSME/roundtrip.mlir +++ b/mlir/test/Dialect/ArmSME/roundtrip.mlir @@ -1095,3 +1095,39 @@ func.func @arm_sme_outerproduct_with_everything(%vecA: vector<[16]xi8>, %vecB: v %result = arm_sme.outerproduct %vecA, %vecB kind acc(%acc) masks(%maskA, %maskB) : vector<[16]xi8>, vector<[16]xi8> return %result : vector<[16]x[16]xi8> } + +//===----------------------------------------------------------------------===// +// arm_sme.streaming_vl +//===----------------------------------------------------------------------===// + +// ----- + +func.func @arm_sme_streaming_vl_bytes() -> index { + // CHECK: arm_sme.streaming_vl + %svl_b = arm_sme.streaming_vl + return %svl_b : index +} + +// ----- + +func.func @arm_sme_streaming_vl_half_words() -> index { + // CHECK: arm_sme.streaming_vl + %svl_h = arm_sme.streaming_vl + return %svl_h : index +} + +// ----- + +func.func @arm_sme_streaming_vl_words() -> index { + // CHECK: arm_sme.streaming_vl + %svl_w = arm_sme.streaming_vl + return %svl_w : index +} + +// ----- + +func.func @arm_sme_streaming_vl_double_words() -> index { + // CHECK: arm_sme.streaming_vl + %svl_d = arm_sme.streaming_vl + return %svl_d : index +} -- GitLab From 76482b74400cccae10d30195f6613f2bf538a43f Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 10 Jan 2024 11:14:35 +0100 Subject: [PATCH 311/652] [SLSR] Regenerate test checks (NFC) --- .../reassociate-geps-and-slsr-addrspace.ll | 75 +++++++++---- .../NVPTX/reassociate-geps-and-slsr.ll | 28 ++++- .../StraightLineStrengthReduce/slsr-gep.ll | 104 ++++++++++++++---- 3 files changed, 158 insertions(+), 49 deletions(-) diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll index e92b389c15ac..6792f807a745 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll @@ -1,13 +1,24 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt -S -mtriple=amdgcn-- -passes=separate-const-offset-from-gep,slsr,gvn < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes="separate-const-offset-from-gep,slsr,gvn" < %s | FileCheck %s target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" -; CHECK-LABEL: @slsr_after_reassociate_global_geps_mubuf_max_offset( -; CHECK: [[b1:%[0-9]+]] = getelementptr float, ptr addrspace(1) %arr, i64 [[bump:%[0-9]+]] -; CHECK: [[b2:%[0-9]+]] = getelementptr float, ptr addrspace(1) [[b1]], i64 [[bump]] define amdgpu_kernel void @slsr_after_reassociate_global_geps_mubuf_max_offset(ptr addrspace(1) %out, ptr addrspace(1) noalias %arr, i32 %i) { +; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_global_geps_mubuf_max_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) noalias [[ARR:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr addrspace(1) [[ARR]], i64 [[TMP0]] +; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP1]], i64 1023 +; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(1) [[P12]], align 4 +; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr addrspace(1) [[TMP1]], i64 [[TMP0]] +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP2]], i64 1023 +; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(1) [[P24]], align 4 +; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; bb: %i2 = shl nsw i32 %i, 1 %j1 = add nsw i32 %i, 1023 @@ -25,12 +36,22 @@ bb: ret void } -; CHECK-LABEL: @slsr_after_reassociate_global_geps_over_mubuf_max_offset( -; CHECK: %j1 = add nsw i32 %i, 1024 -; CHECK: %tmp = sext i32 %j1 to i64 -; CHECK: getelementptr inbounds float, ptr addrspace(1) %arr, i64 %tmp -; CHECK: getelementptr inbounds float, ptr addrspace(1) %arr, i64 %tmp5 define amdgpu_kernel void @slsr_after_reassociate_global_geps_over_mubuf_max_offset(ptr addrspace(1) %out, ptr addrspace(1) noalias %arr, i32 %i) { +; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_global_geps_over_mubuf_max_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) noalias [[ARR:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: [[J1:%.*]] = add nsw i32 [[I]], 1024 +; CHECK-NEXT: [[TMP:%.*]] = sext i32 [[J1]] to i64 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARR]], i64 [[TMP]] +; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(1) [[P1]], align 4 +; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: [[J2:%.*]] = add i32 [[J1]], [[I]] +; CHECK-NEXT: [[TMP5:%.*]] = sext i32 [[J2]] to i64 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARR]], i64 [[TMP5]] +; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(1) [[P2]], align 4 +; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; bb: %i2 = shl nsw i32 %i, 1 %j1 = add nsw i32 %i, 1024 @@ -48,13 +69,21 @@ bb: ret void } -; CHECK-LABEL: @slsr_after_reassociate_lds_geps_ds_max_offset( -; CHECK: [[B1:%[0-9]+]] = getelementptr float, ptr addrspace(3) %arr, i32 %i -; CHECK: getelementptr inbounds float, ptr addrspace(3) [[B1]], i32 16383 -; CHECK: [[B2:%[0-9]+]] = getelementptr float, ptr addrspace(3) [[B1]], i32 %i -; CHECK: getelementptr inbounds float, ptr addrspace(3) [[B2]], i32 16383 define amdgpu_kernel void @slsr_after_reassociate_lds_geps_ds_max_offset(ptr addrspace(1) %out, ptr addrspace(3) noalias %arr, i32 %i) { +; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_lds_geps_ds_max_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(3) noalias [[ARR:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr addrspace(3) [[ARR]], i32 [[I]] +; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP0]], i32 16383 +; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(3) [[P12]], align 4 +; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr addrspace(3) [[TMP0]], i32 [[I]] +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP1]], i32 16383 +; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(3) [[P24]], align 4 +; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; bb: %i2 = shl nsw i32 %i, 1 %j1 = add nsw i32 %i, 16383 @@ -70,12 +99,20 @@ bb: ret void } -; CHECK-LABEL: @slsr_after_reassociate_lds_geps_over_ds_max_offset( -; CHECK: %j1 = add nsw i32 %i, 16384 -; CHECK: getelementptr inbounds float, ptr addrspace(3) %arr, i32 %j1 -; CHECK: %j2 = add i32 %j1, %i -; CHECK: getelementptr inbounds float, ptr addrspace(3) %arr, i32 %j2 define amdgpu_kernel void @slsr_after_reassociate_lds_geps_over_ds_max_offset(ptr addrspace(1) %out, ptr addrspace(3) noalias %arr, i32 %i) { +; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_lds_geps_over_ds_max_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(3) noalias [[ARR:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: [[J1:%.*]] = add nsw i32 [[I]], 16384 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[ARR]], i32 [[J1]] +; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(3) [[P1]], align 4 +; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: [[J2:%.*]] = add i32 [[J1]], [[I]] +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[ARR]], i32 [[J2]] +; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(3) [[P2]], align 4 +; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; bb: %i2 = shl nsw i32 %i, 1 %j1 = add nsw i32 %i, 16384 diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll index 0ff4d2928c37..de085ef10c54 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll @@ -1,6 +1,6 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=separate-const-offset-from-gep,slsr,gvn -S | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX -; RUN: opt < %s -passes="separate-const-offset-from-gep,slsr,gvn" -S | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-unknown-unknown" @@ -28,7 +28,27 @@ target triple = "nvptx64-unknown-unknown" ; p4 = p3 + i ; *(p4 + 5) define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) { -; CHECK-LABEL: @slsr_after_reassociate_geps( +; CHECK-LABEL: define void @slsr_after_reassociate_geps( +; CHECK-SAME: ptr [[ARR:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[ARR]], i64 [[TMP1]] +; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 5 +; CHECK-NEXT: [[V1:%.*]] = load float, ptr [[P12]], align 4 +; CHECK-NEXT: call void @foo(float [[V1]]) +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[TMP2]], i64 [[TMP1]] +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 5 +; CHECK-NEXT: [[V2:%.*]] = load float, ptr [[P24]], align 4 +; CHECK-NEXT: call void @foo(float [[V2]]) +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[TMP3]], i64 [[TMP1]] +; CHECK-NEXT: [[P36:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 5 +; CHECK-NEXT: [[V3:%.*]] = load float, ptr [[P36]], align 4 +; CHECK-NEXT: call void @foo(float [[V3]]) +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[TMP4]], i64 [[TMP1]] +; CHECK-NEXT: [[P48:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 5 +; CHECK-NEXT: [[V4:%.*]] = load float, ptr [[P48]], align 4 +; CHECK-NEXT: call void @foo(float [[V4]]) +; CHECK-NEXT: ret void +; ; PTX-LABEL: .visible .func slsr_after_reassociate_geps( ; PTX: ld.param.u64 [[arr:%rd[0-9]+]], [slsr_after_reassociate_geps_param_0]; ; PTX: ld.param.u32 [[i:%r[0-9]+]], [slsr_after_reassociate_geps_param_1]; @@ -38,7 +58,6 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) { %j1 = add nsw i32 %i, 5 %p1 = getelementptr inbounds float, ptr %arr, i32 %j1 -; CHECK: [[b1:%[0-9]+]] = getelementptr float, ptr %arr, i64 [[bump:%[0-9]+]] ; PTX: mul.wide.s32 [[i4:%rd[0-9]+]], [[i]], 4; ; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]]; %v1 = load float, ptr %p1, align 4 @@ -47,7 +66,6 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) { %j2 = add nsw i32 %i2, 5 %p2 = getelementptr inbounds float, ptr %arr, i32 %j2 -; CHECK: [[b2:%[0-9]+]] = getelementptr float, ptr [[b1]], i64 [[bump]] ; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]]; %v2 = load float, ptr %p2, align 4 ; PTX: ld.f32 {{%f[0-9]+}}, [[[base2]]+20]; @@ -55,7 +73,6 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) { %j3 = add nsw i32 %i3, 5 %p3 = getelementptr inbounds float, ptr %arr, i32 %j3 -; CHECK: [[b3:%[0-9]+]] = getelementptr float, ptr [[b2]], i64 [[bump]] ; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]]; %v3 = load float, ptr %p3, align 4 ; PTX: ld.f32 {{%f[0-9]+}}, [[[base3]]+20]; @@ -63,7 +80,6 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) { %j4 = add nsw i32 %i4, 5 %p4 = getelementptr inbounds float, ptr %arr, i32 %j4 -; CHECK: [[b4:%[0-9]+]] = getelementptr float, ptr [[b3]], i64 [[bump]] ; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]]; %v4 = load float, ptr %p4, align 4 ; PTX: ld.f32 {{%f[0-9]+}}, [[[base4]]+20]; diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll b/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll index 21699e7b3cbd..b446a273d9bd 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll @@ -1,5 +1,5 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=slsr,gvn -S | FileCheck %s -; RUN: opt < %s -passes='slsr,gvn' -S | FileCheck %s target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64-p:64:64:64-p1:32:32:32-p2:128:128:128:32" @@ -14,19 +14,25 @@ target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64-p:64:64:64-p1:32:32:32-p2: ; p2 = p1 + s; ; foo(*p2); define void @slsr_gep(ptr %input, i64 %s) { -; CHECK-LABEL: @slsr_gep( +; CHECK-LABEL: define void @slsr_gep( +; CHECK-SAME: ptr [[INPUT:%.*]], i64 [[S:%.*]]) { +; CHECK-NEXT: call void @foo(ptr [[INPUT]]) +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i64 [[S]] +; CHECK-NEXT: call void @foo(ptr [[P1]]) +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[S]] +; CHECK-NEXT: call void @foo(ptr [[P2]]) +; CHECK-NEXT: ret void +; ; v0 = input[0]; call void @foo(ptr %input) ; v1 = input[s]; %p1 = getelementptr inbounds i32, ptr %input, i64 %s -; CHECK: %p1 = getelementptr inbounds i32, ptr %input, i64 %s call void @foo(ptr %p1) ; v2 = input[s * 2]; %s2 = shl nsw i64 %s, 1 %p2 = getelementptr inbounds i32, ptr %input, i64 %s2 -; CHECK: %p2 = getelementptr inbounds i32, ptr %p1, i64 %s call void @foo(ptr %p2) ret void @@ -43,21 +49,28 @@ define void @slsr_gep(ptr %input, i64 %s) { ; p2 = p1 + (long)s; ; foo(*p2); define void @slsr_gep_sext(ptr %input, i32 %s) { -; CHECK-LABEL: @slsr_gep_sext( +; CHECK-LABEL: define void @slsr_gep_sext( +; CHECK-SAME: ptr [[INPUT:%.*]], i32 [[S:%.*]]) { +; CHECK-NEXT: call void @foo(ptr [[INPUT]]) +; CHECK-NEXT: [[T:%.*]] = sext i32 [[S]] to i64 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i64 [[T]] +; CHECK-NEXT: call void @foo(ptr [[P1]]) +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[T]] +; CHECK-NEXT: call void @foo(ptr [[P2]]) +; CHECK-NEXT: ret void +; ; v0 = input[0]; call void @foo(ptr %input) ; v1 = input[s]; %t = sext i32 %s to i64 %p1 = getelementptr inbounds i32, ptr %input, i64 %t -; CHECK: %p1 = getelementptr inbounds i32, ptr %input, i64 %t call void @foo(ptr %p1) ; v2 = input[s * 2]; %s2 = shl nsw i32 %s, 1 %t2 = sext i32 %s2 to i64 %p2 = getelementptr inbounds i32, ptr %input, i64 %t2 -; CHECK: %p2 = getelementptr inbounds i32, ptr %p1, i64 %t call void @foo(ptr %p2) ret void @@ -75,22 +88,29 @@ define void @slsr_gep_sext(ptr %input, i32 %s) { ; p2 = p1 + 5s; ; foo(*p2); define void @slsr_gep_2d(ptr %input, i64 %s, i64 %t) { -; CHECK-LABEL: @slsr_gep_2d( +; CHECK-LABEL: define void @slsr_gep_2d( +; CHECK-SAME: ptr [[INPUT:%.*]], i64 [[S:%.*]], i64 [[T:%.*]]) { +; CHECK-NEXT: [[P0:%.*]] = getelementptr inbounds [10 x [5 x i32]], ptr [[INPUT]], i64 0, i64 [[S]], i64 [[T]] +; CHECK-NEXT: call void @foo(ptr [[P0]]) +; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[S]], 5 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr [[P0]], i64 [[TMP1]] +; CHECK-NEXT: call void @foo(ptr [[P1]]) +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[TMP1]] +; CHECK-NEXT: call void @foo(ptr [[P2]]) +; CHECK-NEXT: ret void +; ; v0 = input[s][t]; %p0 = getelementptr inbounds [10 x [5 x i32]], ptr %input, i64 0, i64 %s, i64 %t call void @foo(ptr %p0) ; v1 = input[s * 2][t]; %s2 = shl nsw i64 %s, 1 -; CHECK: [[BUMP:%[a-zA-Z0-9]+]] = mul i64 %s, 5 %p1 = getelementptr inbounds [10 x [5 x i32]], ptr %input, i64 0, i64 %s2, i64 %t -; CHECK: %p1 = getelementptr inbounds i32, ptr %p0, i64 [[BUMP]] call void @foo(ptr %p1) ; v3 = input[s * 3][t]; %s3 = mul nsw i64 %s, 3 %p2 = getelementptr inbounds [10 x [5 x i32]], ptr %input, i64 0, i64 %s3, i64 %t -; CHECK: %p2 = getelementptr inbounds i32, ptr %p1, i64 [[BUMP]] call void @foo(ptr %p2) ret void @@ -105,70 +125,100 @@ define void @slsr_gep_2d(ptr %input, i64 %s, i64 %t) { ; rewrite the candidates using byte offset instead of index offset as in ; @slsr_gep_2d. define void @slsr_gep_uglygep(ptr %input, i64 %s, i64 %t) { -; CHECK-LABEL: @slsr_gep_uglygep( +; CHECK-LABEL: define void @slsr_gep_uglygep( +; CHECK-SAME: ptr [[INPUT:%.*]], i64 [[S:%.*]], i64 [[T:%.*]]) { +; CHECK-NEXT: [[P0:%.*]] = getelementptr inbounds [10 x [5 x %struct.S]], ptr [[INPUT]], i64 0, i64 [[S]], i64 [[T]], i32 0 +; CHECK-NEXT: call void @bar(ptr [[P0]]) +; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[S]], 60 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i8, ptr [[P0]], i64 [[TMP1]] +; CHECK-NEXT: call void @bar(ptr [[P1]]) +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[TMP1]] +; CHECK-NEXT: call void @bar(ptr [[P2]]) +; CHECK-NEXT: ret void +; ; v0 = input[s][t].f1; %p0 = getelementptr inbounds [10 x [5 x %struct.S]], ptr %input, i64 0, i64 %s, i64 %t, i32 0 call void @bar(ptr %p0) ; v1 = input[s * 2][t].f1; %s2 = shl nsw i64 %s, 1 -; CHECK: [[BUMP:%[a-zA-Z0-9]+]] = mul i64 %s, 60 %p1 = getelementptr inbounds [10 x [5 x %struct.S]], ptr %input, i64 0, i64 %s2, i64 %t, i32 0 -; CHECK: %p1 = getelementptr inbounds i8, ptr %p0, i64 [[BUMP]] call void @bar(ptr %p1) ; v2 = input[s * 3][t].f1; %s3 = mul nsw i64 %s, 3 %p2 = getelementptr inbounds [10 x [5 x %struct.S]], ptr %input, i64 0, i64 %s3, i64 %t, i32 0 -; CHECK: %p2 = getelementptr inbounds i8, ptr %p1, i64 [[BUMP]] call void @bar(ptr %p2) ret void } define void @slsr_out_of_bounds_gep(ptr %input, i32 %s) { -; CHECK-LABEL: @slsr_out_of_bounds_gep( +; CHECK-LABEL: define void @slsr_out_of_bounds_gep( +; CHECK-SAME: ptr [[INPUT:%.*]], i32 [[S:%.*]]) { +; CHECK-NEXT: call void @foo(ptr [[INPUT]]) +; CHECK-NEXT: [[T:%.*]] = sext i32 [[S]] to i64 +; CHECK-NEXT: [[P1:%.*]] = getelementptr i32, ptr [[INPUT]], i64 [[T]] +; CHECK-NEXT: call void @foo(ptr [[P1]]) +; CHECK-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P1]], i64 [[T]] +; CHECK-NEXT: call void @foo(ptr [[P2]]) +; CHECK-NEXT: ret void +; ; v0 = input[0]; call void @foo(ptr %input) ; v1 = input[(long)s]; %t = sext i32 %s to i64 %p1 = getelementptr i32, ptr %input, i64 %t -; CHECK: %p1 = getelementptr i32, ptr %input, i64 %t call void @foo(ptr %p1) ; v2 = input[(long)(s * 2)]; %s2 = shl nsw i32 %s, 1 %t2 = sext i32 %s2 to i64 %p2 = getelementptr i32, ptr %input, i64 %t2 -; CHECK: %p2 = getelementptr i32, ptr %p1, i64 %t call void @foo(ptr %p2) ret void } define void @slsr_gep_128bit_index(ptr %input, i128 %s) { -; CHECK-LABEL: @slsr_gep_128bit_index( +; CHECK-LABEL: define void @slsr_gep_128bit_index( +; CHECK-SAME: ptr [[INPUT:%.*]], i128 [[S:%.*]]) { +; CHECK-NEXT: call void @foo(ptr [[INPUT]]) +; CHECK-NEXT: [[S125:%.*]] = shl nsw i128 [[S]], 125 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i128 [[S125]] +; CHECK-NEXT: call void @foo(ptr [[P1]]) +; CHECK-NEXT: [[S126:%.*]] = shl nsw i128 [[S]], 126 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i128 [[S126]] +; CHECK-NEXT: call void @foo(ptr [[P2]]) +; CHECK-NEXT: ret void +; ; p0 = &input[0] call void @foo(ptr %input) ; p1 = &input[s << 125] %s125 = shl nsw i128 %s, 125 %p1 = getelementptr inbounds i32, ptr %input, i128 %s125 -; CHECK: %p1 = getelementptr inbounds i32, ptr %input, i128 %s125 call void @foo(ptr %p1) ; p2 = &input[s << 126] %s126 = shl nsw i128 %s, 126 %p2 = getelementptr inbounds i32, ptr %input, i128 %s126 -; CHECK: %p2 = getelementptr inbounds i32, ptr %input, i128 %s126 call void @foo(ptr %p2) ret void } define void @slsr_gep_32bit_pointer(ptr addrspace(1) %input, i64 %s) { -; CHECK-LABEL: @slsr_gep_32bit_pointer( +; CHECK-LABEL: define void @slsr_gep_32bit_pointer( +; CHECK-SAME: ptr addrspace(1) [[INPUT:%.*]], i64 [[S:%.*]]) { +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[INPUT]], i64 [[S]] +; CHECK-NEXT: call void @baz(ptr addrspace(1) [[P1]]) +; CHECK-NEXT: [[S2:%.*]] = mul nsw i64 [[S]], 2 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[INPUT]], i64 [[S2]] +; CHECK-NEXT: call void @baz(ptr addrspace(1) [[P2]]) +; CHECK-NEXT: ret void +; ; p1 = &input[s] %p1 = getelementptr inbounds i32, ptr addrspace(1) %input, i64 %s call void @baz(ptr addrspace(1) %p1) @@ -177,7 +227,6 @@ define void @slsr_gep_32bit_pointer(ptr addrspace(1) %input, i64 %s) { %s2 = mul nsw i64 %s, 2 %p2 = getelementptr inbounds i32, ptr addrspace(1) %input, i64 %s2 ; %s2 is wider than the pointer size of addrspace(1), so do not factor it. -; CHECK: %p2 = getelementptr inbounds i32, ptr addrspace(1) %input, i64 %s2 call void @baz(ptr addrspace(1) %p2) ret void @@ -185,13 +234,20 @@ define void @slsr_gep_32bit_pointer(ptr addrspace(1) %input, i64 %s) { define void @slsr_gep_fat_pointer(ptr addrspace(2) %input, i32 %s) { ; p1 = &input[s] +; CHECK-LABEL: define void @slsr_gep_fat_pointer( +; CHECK-SAME: ptr addrspace(2) [[INPUT:%.*]], i32 [[S:%.*]]) { +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[INPUT]], i32 [[S]] +; CHECK-NEXT: call void @baz2(ptr addrspace(2) [[P1]]) +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[P1]], i32 [[S]] +; CHECK-NEXT: call void @baz2(ptr addrspace(2) [[P2]]) +; CHECK-NEXT: ret void +; %p1 = getelementptr inbounds i32, ptr addrspace(2) %input, i32 %s call void @baz2(ptr addrspace(2) %p1) ; p2 = &input[s * 2] %s2 = mul nsw i32 %s, 2 %p2 = getelementptr inbounds i32, ptr addrspace(2) %input, i32 %s2 -; CHECK: %p2 = getelementptr inbounds i32, ptr addrspace(2) %p1, i32 %s ; Use index bitwidth, not pointer size (i128) call void @baz2(ptr addrspace(2) %p2) -- GitLab From 9bc4355f091b530625ec6839a8c4858b6de4f1b4 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 10 Jan 2024 11:12:23 +0100 Subject: [PATCH 312/652] [SLSR] Always generate i8 GEPs Always generate canonical i8 GEPs. Especially as this is a backend pass, trying to generate a "nice" GEP representation is not useful. --- .../Scalar/StraightLineStrengthReduce.cpp | 55 ++++--------------- .../reassociate-geps-and-slsr-addrspace.ll | 10 ++-- .../NVPTX/reassociate-geps-and-slsr.ll | 13 +++-- .../StraightLineStrengthReduce/slsr-gep.ll | 18 +++--- 4 files changed, 34 insertions(+), 62 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp index ca1f3a0c0ae3..2cce6eb22341 100644 --- a/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp @@ -233,13 +233,9 @@ private: void factorArrayIndex(Value *ArrayIdx, const SCEV *Base, uint64_t ElementSize, GetElementPtrInst *GEP); - // Emit code that computes the "bump" from Basis to C. If the candidate is a - // GEP and the bump is not divisible by the element size of the GEP, this - // function sets the BumpWithUglyGEP flag to notify its caller to bump the - // basis using an ugly GEP. + // Emit code that computes the "bump" from Basis to C. static Value *emitBump(const Candidate &Basis, const Candidate &C, - IRBuilder<> &Builder, const DataLayout *DL, - bool &BumpWithUglyGEP); + IRBuilder<> &Builder, const DataLayout *DL); const DataLayout *DL = nullptr; DominatorTree *DT = nullptr; @@ -581,26 +577,11 @@ static void unifyBitWidth(APInt &A, APInt &B) { Value *StraightLineStrengthReduce::emitBump(const Candidate &Basis, const Candidate &C, IRBuilder<> &Builder, - const DataLayout *DL, - bool &BumpWithUglyGEP) { + const DataLayout *DL) { APInt Idx = C.Index->getValue(), BasisIdx = Basis.Index->getValue(); unifyBitWidth(Idx, BasisIdx); APInt IndexOffset = Idx - BasisIdx; - BumpWithUglyGEP = false; - if (Basis.CandidateKind == Candidate::GEP) { - APInt ElementSize( - IndexOffset.getBitWidth(), - DL->getTypeAllocSize( - cast(Basis.Ins)->getResultElementType())); - APInt Q, R; - APInt::sdivrem(IndexOffset, ElementSize, Q, R); - if (R == 0) - IndexOffset = Q; - else - BumpWithUglyGEP = true; - } - // Compute Bump = C - Basis = (i' - i) * S. // Common case 1: if (i' - i) is 1, Bump = S. if (IndexOffset == 1) @@ -645,8 +626,7 @@ void StraightLineStrengthReduce::rewriteCandidateWithBasis( return; IRBuilder<> Builder(C.Ins); - bool BumpWithUglyGEP; - Value *Bump = emitBump(Basis, C, Builder, DL, BumpWithUglyGEP); + Value *Bump = emitBump(Basis, C, Builder, DL); Value *Reduced = nullptr; // equivalent to but weaker than C.Ins switch (C.CandidateKind) { case Candidate::Add: @@ -673,28 +653,13 @@ void StraightLineStrengthReduce::rewriteCandidateWithBasis( } break; } - case Candidate::GEP: - { - Type *OffsetTy = DL->getIndexType(C.Ins->getType()); + case Candidate::GEP: { bool InBounds = cast(C.Ins)->isInBounds(); - if (BumpWithUglyGEP) { - // C = (char *)Basis + Bump - unsigned AS = Basis.Ins->getType()->getPointerAddressSpace(); - Type *CharTy = PointerType::get(Basis.Ins->getContext(), AS); - Reduced = Builder.CreateBitCast(Basis.Ins, CharTy); - Reduced = - Builder.CreateGEP(Builder.getInt8Ty(), Reduced, Bump, "", InBounds); - Reduced = Builder.CreateBitCast(Reduced, C.Ins->getType()); - } else { - // C = gep Basis, Bump - // Canonicalize bump to pointer size. - Bump = Builder.CreateSExtOrTrunc(Bump, OffsetTy); - Reduced = Builder.CreateGEP( - cast(Basis.Ins)->getResultElementType(), Basis.Ins, - Bump, "", InBounds); - } - break; - } + // C = (char *)Basis + Bump + Reduced = + Builder.CreateGEP(Builder.getInt8Ty(), Basis.Ins, Bump, "", InBounds); + break; + } default: llvm_unreachable("C.CandidateKind is invalid"); }; diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll index 6792f807a745..9cf725840abd 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll @@ -13,8 +13,9 @@ define amdgpu_kernel void @slsr_after_reassociate_global_geps_mubuf_max_offset(p ; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP1]], i64 1023 ; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(1) [[P12]], align 4 ; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr addrspace(1) [[TMP1]], i64 [[TMP0]] -; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP2]], i64 1023 +; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0]], 2 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(1) [[TMP1]], i64 [[TMP2]] +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP3]], i64 1023 ; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(1) [[P24]], align 4 ; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: ret void @@ -78,8 +79,9 @@ define amdgpu_kernel void @slsr_after_reassociate_lds_geps_ds_max_offset(ptr add ; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP0]], i32 16383 ; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(3) [[P12]], align 4 ; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr addrspace(3) [[TMP0]], i32 [[I]] -; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP1]], i32 16383 +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[I]], 2 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP0]], i32 [[TMP1]] +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 16383 ; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(3) [[P24]], align 4 ; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll index de085ef10c54..e65b9b1a99a6 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll @@ -35,16 +35,17 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) { ; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 5 ; CHECK-NEXT: [[V1:%.*]] = load float, ptr [[P12]], align 4 ; CHECK-NEXT: call void @foo(float [[V1]]) -; CHECK-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[TMP2]], i64 [[TMP1]] -; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 5 +; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP1]], 2 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP2]], i64 [[TMP3]] +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 5 ; CHECK-NEXT: [[V2:%.*]] = load float, ptr [[P24]], align 4 ; CHECK-NEXT: call void @foo(float [[V2]]) -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[TMP3]], i64 [[TMP1]] -; CHECK-NEXT: [[P36:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 5 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP4]], i64 [[TMP3]] +; CHECK-NEXT: [[P36:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 5 ; CHECK-NEXT: [[V3:%.*]] = load float, ptr [[P36]], align 4 ; CHECK-NEXT: call void @foo(float [[V3]]) -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[TMP4]], i64 [[TMP1]] -; CHECK-NEXT: [[P48:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 5 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i64 [[TMP3]] +; CHECK-NEXT: [[P48:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 5 ; CHECK-NEXT: [[V4:%.*]] = load float, ptr [[P48]], align 4 ; CHECK-NEXT: call void @foo(float [[V4]]) ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll b/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll index b446a273d9bd..7cd45329c24f 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll @@ -19,7 +19,8 @@ define void @slsr_gep(ptr %input, i64 %s) { ; CHECK-NEXT: call void @foo(ptr [[INPUT]]) ; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i64 [[S]] ; CHECK-NEXT: call void @foo(ptr [[P1]]) -; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[S]] +; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[S]], 2 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[TMP1]] ; CHECK-NEXT: call void @foo(ptr [[P2]]) ; CHECK-NEXT: ret void ; @@ -55,7 +56,8 @@ define void @slsr_gep_sext(ptr %input, i32 %s) { ; CHECK-NEXT: [[T:%.*]] = sext i32 [[S]] to i64 ; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i64 [[T]] ; CHECK-NEXT: call void @foo(ptr [[P1]]) -; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[T]] +; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[T]], 2 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[TMP1]] ; CHECK-NEXT: call void @foo(ptr [[P2]]) ; CHECK-NEXT: ret void ; @@ -92,10 +94,10 @@ define void @slsr_gep_2d(ptr %input, i64 %s, i64 %t) { ; CHECK-SAME: ptr [[INPUT:%.*]], i64 [[S:%.*]], i64 [[T:%.*]]) { ; CHECK-NEXT: [[P0:%.*]] = getelementptr inbounds [10 x [5 x i32]], ptr [[INPUT]], i64 0, i64 [[S]], i64 [[T]] ; CHECK-NEXT: call void @foo(ptr [[P0]]) -; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[S]], 5 -; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr [[P0]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[S]], 20 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i8, ptr [[P0]], i64 [[TMP1]] ; CHECK-NEXT: call void @foo(ptr [[P1]]) -; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[TMP1]] +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[TMP1]] ; CHECK-NEXT: call void @foo(ptr [[P2]]) ; CHECK-NEXT: ret void ; @@ -160,7 +162,8 @@ define void @slsr_out_of_bounds_gep(ptr %input, i32 %s) { ; CHECK-NEXT: [[T:%.*]] = sext i32 [[S]] to i64 ; CHECK-NEXT: [[P1:%.*]] = getelementptr i32, ptr [[INPUT]], i64 [[T]] ; CHECK-NEXT: call void @foo(ptr [[P1]]) -; CHECK-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P1]], i64 [[T]] +; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[T]], 2 +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P1]], i64 [[TMP1]] ; CHECK-NEXT: call void @foo(ptr [[P2]]) ; CHECK-NEXT: ret void ; @@ -238,7 +241,8 @@ define void @slsr_gep_fat_pointer(ptr addrspace(2) %input, i32 %s) { ; CHECK-SAME: ptr addrspace(2) [[INPUT:%.*]], i32 [[S:%.*]]) { ; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[INPUT]], i32 [[S]] ; CHECK-NEXT: call void @baz2(ptr addrspace(2) [[P1]]) -; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[P1]], i32 [[S]] +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[S]], 2 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i8, ptr addrspace(2) [[P1]], i32 [[TMP1]] ; CHECK-NEXT: call void @baz2(ptr addrspace(2) [[P2]]) ; CHECK-NEXT: ret void ; -- GitLab From c2654befcaecba121ca40415d157925e0da05b5e Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 10 Jan 2024 11:43:50 +0100 Subject: [PATCH 313/652] [SeparateConstOFfsetFromGEP] Regenerate test checks (NFC) --- ...-gep-and-gvn-addrspace-addressing-modes.ll | 95 ++++++++++--- .../NVPTX/split-gep-and-gvn.ll | 132 +++++++++++++++--- 2 files changed, 185 insertions(+), 42 deletions(-) diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll index 5cb8cbd05a7a..2cd7fdfce35e 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll @@ -1,15 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt -mtriple=amdgcn-- -S -passes=separate-const-offset-from-gep,gvn -reassociate-geps-verify-no-dead-code < %s | FileCheck -check-prefix=IR %s target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" @array = internal addrspace(4) constant [4096 x [32 x float]] zeroinitializer, align 4 -; IR-LABEL: @sum_of_array( -; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds float, ptr addrspace(4) [[BASE_PTR]], i64 1 -; IR: getelementptr inbounds float, ptr addrspace(4) [[BASE_PTR]], i64 32 -; IR: getelementptr inbounds float, ptr addrspace(4) [[BASE_PTR]], i64 33 define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) { +; IR-LABEL: define amdgpu_kernel void @sum_of_array( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) nocapture [[OUTPUT:%.*]]) { +; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i64 +; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64 +; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 [[TMP1]], i64 [[TMP]] +; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 1 +; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 32 +; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 33 +; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 4 +; IR-NEXT: ret void +; %tmp = sext i32 %y to i64 %tmp1 = sext i32 %x to i64 %tmp2 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp1, i64 %tmp @@ -36,13 +43,22 @@ define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, ptr addrspace(1) nocaptu ; Some of the indices go over the maximum mubuf offset, so don't split them. -; IR-LABEL: @sum_of_array_over_max_mubuf_offset( -; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds float, ptr addrspace(4) [[BASE_PTR]], i64 255 -; IR: add i32 %x, 256 -; IR: getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) { +; IR-LABEL: define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) nocapture [[OUTPUT:%.*]]) { +; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i64 +; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64 +; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP1]], i64 [[TMP]] +; IR-NEXT: [[TMP6:%.*]] = add i32 [[Y]], 255 +; IR-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i64 +; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 255 +; IR-NEXT: [[TMP12:%.*]] = add i32 [[X]], 256 +; IR-NEXT: [[TMP13:%.*]] = sext i32 [[TMP12]] to i64 +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP]] +; IR-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP7]] +; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 4 +; IR-NEXT: ret void +; %tmp = sext i32 %y to i64 %tmp1 = sext i32 %x to i64 %tmp2 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp1, i64 %tmp @@ -69,12 +85,24 @@ define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, pt @lds_array = internal addrspace(3) global [4096 x [4 x float]] undef, align 4 ; DS instructions have a larger immediate offset, so make sure these are OK. -; IR-LABEL: @sum_of_lds_array_over_max_mubuf_offset( -; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %{{[a-zA-Z0-9]+}}, i32 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i32 255 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i32 16128 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i32 16383 define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) { +; IR-LABEL: define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) nocapture [[OUTPUT:%.*]]) { +; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 [[X]], i32 [[Y]] +; IR-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(3) [[TMP2]], align 4 +; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 +; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 255 +; IR-NEXT: [[TMP10:%.*]] = load float, ptr addrspace(3) [[TMP82]], align 4 +; IR-NEXT: [[TMP11:%.*]] = fadd float [[TMP5]], [[TMP10]] +; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 16128 +; IR-NEXT: [[TMP16:%.*]] = load float, ptr addrspace(3) [[TMP144]], align 4 +; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP11]], [[TMP16]] +; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 16383 +; IR-NEXT: [[TMP20:%.*]] = load float, ptr addrspace(3) [[TMP187]], align 4 +; IR-NEXT: [[TMP21:%.*]] = fadd float [[TMP17]], [[TMP20]] +; IR-NEXT: store float [[TMP21]], ptr addrspace(1) [[OUTPUT]], align 4 +; IR-NEXT: ret void +; %tmp2 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %x, i32 %y %tmp4 = load float, ptr addrspace(3) %tmp2, align 4 %tmp5 = fadd float %tmp4, 0.000000e+00 @@ -93,11 +121,35 @@ define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(i32 %x, i32 %y ret void } -; IR-LABEL: @keep_metadata( -; IR: getelementptr {{.*}} !amdgpu.uniform -; IR: getelementptr {{.*}} !amdgpu.uniform -; IR: getelementptr {{.*}} !amdgpu.uniform define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata(ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 { +; IR-LABEL: define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata( +; IR-SAME: ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP0:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP1:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP2:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP3:%.*]], float inreg [[TMP4:%.*]], i32 inreg [[TMP5:%.*]], <2 x i32> [[TMP6:%.*]], <2 x i32> [[TMP7:%.*]], <2 x i32> [[TMP8:%.*]], <3 x i32> [[TMP9:%.*]], <2 x i32> [[TMP10:%.*]], <2 x i32> [[TMP11:%.*]], <2 x i32> [[TMP12:%.*]], float [[TMP13:%.*]], float [[TMP14:%.*]], float [[TMP15:%.*]], float [[TMP16:%.*]], float [[TMP17:%.*]], i32 [[TMP18:%.*]], i32 [[TMP19:%.*]], float [[TMP20:%.*]], i32 [[TMP21:%.*]]) #[[ATTR0:[0-9]+]] { +; IR-NEXT: main_body: +; IR-NEXT: [[TMP22:%.*]] = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 [[TMP5]]) #[[ATTR3:[0-9]+]] +; IR-NEXT: [[TMP23:%.*]] = bitcast float [[TMP22]] to i32 +; IR-NEXT: [[TMP24:%.*]] = shl i32 [[TMP23]], 1 +; IR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP24]] to i64 +; IR-NEXT: [[TMP25:%.*]] = getelementptr [0 x <8 x i32>], ptr addrspace(4) [[TMP1]], i64 0, i64 [[IDXPROM1]], !amdgpu.uniform [[META0:![0-9]+]] +; IR-NEXT: [[TMP26:%.*]] = load <8 x i32>, ptr addrspace(4) [[TMP25]], align 32, !invariant.load [[META0]] +; IR-NEXT: [[TMP27:%.*]] = shl i32 [[TMP23]], 2 +; IR-NEXT: [[TMP28:%.*]] = sext i32 [[TMP27]] to i64 +; IR-NEXT: [[TMP29:%.*]] = getelementptr [0 x <4 x i32>], ptr addrspace(4) [[TMP1]], i64 0, i64 [[TMP28]], !amdgpu.uniform [[META0]] +; IR-NEXT: [[TMP30:%.*]] = getelementptr <4 x i32>, ptr addrspace(4) [[TMP29]], i64 3, !amdgpu.uniform [[META0]] +; IR-NEXT: [[TMP31:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP30]], align 16, !invariant.load [[META0]] +; IR-NEXT: [[TMP32:%.*]] = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> [[TMP26]], <4 x i32> [[TMP31]], i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #[[ATTR3]] +; IR-NEXT: [[TMP33:%.*]] = extractelement <4 x float> [[TMP32]], i32 0 +; IR-NEXT: [[TMP34:%.*]] = extractelement <4 x float> [[TMP32]], i32 1 +; IR-NEXT: [[TMP35:%.*]] = extractelement <4 x float> [[TMP32]], i32 2 +; IR-NEXT: [[TMP36:%.*]] = extractelement <4 x float> [[TMP32]], i32 3 +; IR-NEXT: [[TMP37:%.*]] = bitcast float [[TMP4]] to i32 +; IR-NEXT: [[TMP38:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 [[TMP37]], 4 +; IR-NEXT: [[TMP39:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP38]], float [[TMP33]], 5 +; IR-NEXT: [[TMP40:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP39]], float [[TMP34]], 6 +; IR-NEXT: [[TMP41:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP40]], float [[TMP35]], 7 +; IR-NEXT: [[TMP42:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP41]], float [[TMP36]], 8 +; IR-NEXT: [[TMP43:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP42]], float [[TMP20]], 19 +; IR-NEXT: ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP43]] +; main_body: %22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8 %23 = bitcast float %22 to i32 @@ -136,3 +188,6 @@ attributes #5 = { "InitialPSInputAddr"="45175" } attributes #6 = { nounwind readnone speculatable } attributes #7 = { nounwind readonly } attributes #8 = { nounwind readnone } +;. +; IR: [[META0]] = !{} +;. diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll index 5652b6657b53..1391cb4e7b49 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -mtriple=nvptx64-nvidia-cuda -S -passes=separate-const-offset-from-gep,gvn \ ; RUN: -reassociate-geps-verify-no-dead-code \ ; RUN: | FileCheck %s --check-prefix=IR @@ -18,6 +19,30 @@ @array = internal addrspace(3) global [32 x [32 x float]] zeroinitializer, align 4 define void @sum_of_array(i32 %x, i32 %y, ptr nocapture %output) { +; IR-LABEL: define void @sum_of_array( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr nocapture [[OUTPUT:%.*]]) { +; IR-NEXT: .preheader: +; IR-NEXT: [[TMP0:%.*]] = sext i32 [[Y]] to i64 +; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64 +; IR-NEXT: [[TMP2:%.*]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]] +; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr +; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 +; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr +; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 +; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr +; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 +; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr +; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 +; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] +; IR-NEXT: store float [[TMP17]], ptr [[OUTPUT]], align 4 +; IR-NEXT: ret void +; .preheader: %0 = sext i32 %y to i64 %1 = sext i32 %x to i64 @@ -50,13 +75,8 @@ define void @sum_of_array(i32 %x, i32 %y, ptr nocapture %output) { ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128] ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132] -; IR-LABEL: @sum_of_array( ; TODO: GVN is unable to preserve the "inbounds" keyword on the first GEP. Need ; some infrastructure changes to enable such optimizations. -; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 1 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 32 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 33 ; @sum_of_array2 is very similar to @sum_of_array. The only difference is in ; the order of "sext" and "add" when computing the array indices. @sum_of_array @@ -65,6 +85,30 @@ define void @sum_of_array(i32 %x, i32 %y, ptr nocapture %output) { ; e.g., array[sext(x) + 1][sext(y) + 1]. SeparateConstOffsetFromGEP should be ; able to extract constant offsets from both forms. define void @sum_of_array2(i32 %x, i32 %y, ptr nocapture %output) { +; IR-LABEL: define void @sum_of_array2( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr nocapture [[OUTPUT:%.*]]) { +; IR-NEXT: .preheader: +; IR-NEXT: [[TMP0:%.*]] = sext i32 [[Y]] to i64 +; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64 +; IR-NEXT: [[TMP2:%.*]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]] +; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr +; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 +; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr +; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 +; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr +; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 +; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr +; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 +; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] +; IR-NEXT: store float [[TMP17]], ptr [[OUTPUT]], align 4 +; IR-NEXT: ret void +; .preheader: %0 = sext i32 %y to i64 %1 = sext i32 %x to i64 @@ -95,11 +139,6 @@ define void @sum_of_array2(i32 %x, i32 %y, ptr nocapture %output) { ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128] ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132] -; IR-LABEL: @sum_of_array2( -; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 1 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 32 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 33 ; This function loads @@ -113,6 +152,30 @@ define void @sum_of_array2(i32 %x, i32 %y, ptr nocapture %output) { ; 2) annotates the addition with "nuw"; otherwise, zext(x + 1) => zext(x) + 1 ; may be invalid. define void @sum_of_array3(i32 %x, i32 %y, ptr nocapture %output) { +; IR-LABEL: define void @sum_of_array3( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr nocapture [[OUTPUT:%.*]]) { +; IR-NEXT: .preheader: +; IR-NEXT: [[TMP0:%.*]] = zext i32 [[Y]] to i64 +; IR-NEXT: [[TMP1:%.*]] = zext i32 [[X]] to i64 +; IR-NEXT: [[TMP2:%.*]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]] +; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr +; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 +; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr +; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 +; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr +; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 +; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr +; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 +; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] +; IR-NEXT: store float [[TMP17]], ptr [[OUTPUT]], align 4 +; IR-NEXT: ret void +; .preheader: %0 = zext i32 %y to i64 %1 = zext i32 %x to i64 @@ -145,11 +208,6 @@ define void @sum_of_array3(i32 %x, i32 %y, ptr nocapture %output) { ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128] ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132] -; IR-LABEL: @sum_of_array3( -; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 1 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 32 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 33 ; This function loads @@ -161,6 +219,30 @@ define void @sum_of_array3(i32 %x, i32 %y, ptr nocapture %output) { ; We expect the generated code to reuse the computation of ; &array[zext(x)][zext(y)]. See the expected IR and PTX for details. define void @sum_of_array4(i32 %x, i32 %y, ptr nocapture %output) { +; IR-LABEL: define void @sum_of_array4( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr nocapture [[OUTPUT:%.*]]) { +; IR-NEXT: .preheader: +; IR-NEXT: [[TMP0:%.*]] = zext i32 [[Y]] to i64 +; IR-NEXT: [[TMP1:%.*]] = zext i32 [[X]] to i64 +; IR-NEXT: [[TMP2:%.*]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]] +; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr +; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 +; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr +; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 +; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr +; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 +; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr +; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 +; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] +; IR-NEXT: store float [[TMP17]], ptr [[OUTPUT]], align 4 +; IR-NEXT: ret void +; .preheader: %0 = zext i32 %y to i64 %1 = zext i32 %x to i64 @@ -191,11 +273,6 @@ define void @sum_of_array4(i32 %x, i32 %y, ptr nocapture %output) { ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128] ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132] -; IR-LABEL: @sum_of_array4( -; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 1 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 32 -; IR: getelementptr inbounds float, ptr addrspace(3) [[BASE_PTR]], i64 33 ; The source code is: @@ -211,7 +288,19 @@ define void @sum_of_array4(i32 %x, i32 %y, ptr nocapture %output) { ; p0 = &input[sext(x + y)]; ; p1 = &p0[5]; define void @reunion(i32 %x, i32 %y, ptr %input) { -; IR-LABEL: @reunion( +; IR-LABEL: define void @reunion( +; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr [[INPUT:%.*]]) { +; IR-NEXT: entry: +; IR-NEXT: [[XY:%.*]] = add nsw i32 [[X]], [[Y]] +; IR-NEXT: [[TMP0:%.*]] = sext i32 [[XY]] to i64 +; IR-NEXT: [[P0:%.*]] = getelementptr float, ptr [[INPUT]], i64 [[TMP0]] +; IR-NEXT: [[V0:%.*]] = load float, ptr [[P0]], align 4 +; IR-NEXT: call void @use(float [[V0]]) +; IR-NEXT: [[P13:%.*]] = getelementptr inbounds float, ptr [[P0]], i64 5 +; IR-NEXT: [[V1:%.*]] = load float, ptr [[P13]], align 4 +; IR-NEXT: call void @use(float [[V1]]) +; IR-NEXT: ret void +; ; PTX-LABEL: reunion( entry: %xy = add nsw i32 %x, %y @@ -225,7 +314,6 @@ entry: %xy5 = add nsw i32 %x, %y5 %1 = sext i32 %xy5 to i64 %p1 = getelementptr inbounds float, ptr %input, i64 %1 -; IR: getelementptr inbounds float, ptr %p0, i64 5 %v1 = load float, ptr %p1, align 4 ; PTX: ld.f32 %f{{[0-9]+}}, [[[p0]]+20] call void @use(float %v1) -- GitLab From 5cc03442d392693d0d2457f571cc8fa1736bfe5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20Gr=C3=A4nitz?= Date: Wed, 10 Jan 2024 11:49:01 +0100 Subject: [PATCH 314/652] [clang-repl] Enable native CPU detection by default (#77491) We can pass `-mcpu=native` to the clang driver to let it consider the host CPU when choosing the compile target for `clang-repl`. We can already achieve this behavior with `clang-repl -Xcc -mcpu=native`, but it seems like a reasonable default actually. The trade-off between optimizing for a specific CPU and maximum compatibility often leans towards the latter for static binaries, because distributing many versions is cumbersome. However, when compiling at runtime, we know the exact target CPU and we can use that to optimize the generated code. This patch makes a difference especially for "scattered" architectures like ARM. When cross-compiling for a Raspberry Pi for example, we may use a stock toolchain like arm-linux-gnueabihf-gcc. The resulting binary will be compatible with all hardware versions. This is handy, but they will all have `arm-linux-gnueabihf` as their host triple. Previously, this caused the clang driver to select triple `armv6kz-linux-gnueabihf` and CPU `arm1176jzf-s` as the REPL target. After this patch the default triple and CPU on Raspberry Pi 4b will be `armv8a-linux-gnueabihf` and `cortex-a72` respectively. With this patch clang-repl matches the host detection in Orc. --- clang/lib/Interpreter/Interpreter.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/lib/Interpreter/Interpreter.cpp b/clang/lib/Interpreter/Interpreter.cpp index c9fcef5b5b5a..734fe90d0d89 100644 --- a/clang/lib/Interpreter/Interpreter.cpp +++ b/clang/lib/Interpreter/Interpreter.cpp @@ -148,6 +148,7 @@ IncrementalCompilerBuilder::create(std::vector &ClangArgv) { // We do C++ by default; append right after argv[0] if no "-x" given ClangArgv.insert(ClangArgv.end(), "-Xclang"); ClangArgv.insert(ClangArgv.end(), "-fincremental-extensions"); + ClangArgv.insert(ClangArgv.end(), "-mcpu=native"); ClangArgv.insert(ClangArgv.end(), "-c"); // Put a dummy C++ file on to ensure there's at least one compile job for the -- GitLab From 08da7ac80c165dbae0cb71257b3cdcd8a1006a76 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Wed, 10 Jan 2024 10:50:13 +0000 Subject: [PATCH 315/652] [AMDGPU] Fix broken sign-extended subword buffer load combine (#77470) --- llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 2 +- .../AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 46 +++++----- .../llvm.amdgcn.struct.buffer.load.ll | 86 +++++++++++++++++++ 3 files changed, 111 insertions(+), 23 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td index 0c77fe725958..b9411e205212 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -111,7 +111,7 @@ def smulu64 : GICombineRule< [{ return matchCombine_s_mul_u64(*${smul}, ${matchinfo}); }]), (apply [{ applyCombine_s_mul_u64(*${smul}, ${matchinfo}); }])>; -def sign_exension_in_reg_matchdata : GIDefMatchData<"MachineInstr *">; +def sign_exension_in_reg_matchdata : GIDefMatchData<"std::pair">; def sign_extension_in_reg : GICombineRule< (defs root:$sign_inreg, sign_exension_in_reg_matchdata:$matchinfo), diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp index 21bfab52c6c4..bb1d6cb72e80 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -99,10 +99,10 @@ public: // Combine unsigned buffer load and signed extension instructions to generate // signed buffer laod instructions. - bool matchCombineSignExtendInReg(MachineInstr &MI, - MachineInstr *&MatchInfo) const; - void applyCombineSignExtendInReg(MachineInstr &MI, - MachineInstr *&MatchInfo) const; + bool matchCombineSignExtendInReg( + MachineInstr &MI, std::pair &MatchInfo) const; + void applyCombineSignExtendInReg( + MachineInstr &MI, std::pair &MatchInfo) const; // Find the s_mul_u64 instructions where the higher bits are either // zero-extended or sign-extended. @@ -395,34 +395,36 @@ bool AMDGPUPostLegalizerCombinerImpl::matchRemoveFcanonicalize( // Identify buffer_load_{u8, u16}. bool AMDGPUPostLegalizerCombinerImpl::matchCombineSignExtendInReg( - MachineInstr &MI, MachineInstr *&SubwordBufferLoad) const { - Register Op0Reg = MI.getOperand(1).getReg(); - SubwordBufferLoad = MRI.getVRegDef(Op0Reg); - - if (!MRI.hasOneNonDBGUse(Op0Reg)) + MachineInstr &MI, std::pair &MatchData) const { + Register LoadReg = MI.getOperand(1).getReg(); + if (!MRI.hasOneNonDBGUse(LoadReg)) return false; // Check if the first operand of the sign extension is a subword buffer load // instruction. - return SubwordBufferLoad->getOpcode() == AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE || - SubwordBufferLoad->getOpcode() == AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT; + MachineInstr *LoadMI = MRI.getVRegDef(LoadReg); + int64_t Width = MI.getOperand(2).getImm(); + switch (LoadMI->getOpcode()) { + case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE: + MatchData = {LoadMI, AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE}; + return Width == 8; + case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT: + MatchData = {LoadMI, AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT}; + return Width == 16; + } + return false; } // Combine buffer_load_{u8, u16} and the sign extension instruction to generate // buffer_load_{i8, i16}. void AMDGPUPostLegalizerCombinerImpl::applyCombineSignExtendInReg( - MachineInstr &MI, MachineInstr *&SubwordBufferLoad) const { - // Modify the opcode and the destination of buffer_load_{u8, u16}: - // Replace the opcode. - unsigned Opc = - SubwordBufferLoad->getOpcode() == AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE - ? AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE - : AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT; - SubwordBufferLoad->setDesc(TII.get(Opc)); - // Update the destination register of SubwordBufferLoad with the destination - // register of the sign extension. + MachineInstr &MI, std::pair &MatchData) const { + auto [LoadMI, NewOpcode] = MatchData; + LoadMI->setDesc(TII.get(NewOpcode)); + // Update the destination register of the load with the destination register + // of the sign extension. Register SignExtendInsnDst = MI.getOperand(0).getReg(); - SubwordBufferLoad->getOperand(0).setReg(SignExtendInsnDst); + LoadMI->getOperand(0).setReg(SignExtendInsnDst); // Remove the sign extension. MI.eraseFromParent(); } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll index 81c0f7557e64..94ce8aac8a4c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll @@ -500,6 +500,49 @@ define amdgpu_ps float @struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr ret float %cast } +define amdgpu_ps float @struct_buffer_load_i8_sext_wrong_width(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { + ; GFX8-LABEL: name: struct_buffer_load_i8_sext_wrong_width + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX8-NEXT: [[BUFFER_LOAD_UBYTE_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (s8), addrspace 8) + ; GFX8-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_BOTHEN]], 0, 4, implicit $exec + ; GFX8-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX12-LABEL: name: struct_buffer_load_i8_sext_wrong_width + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX12-NEXT: [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (s8), addrspace 8) + ; GFX12-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN]], 0, 4, implicit $exec + ; GFX12-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + %trunc = trunc i8 %val to i4 + %ext = sext i4 %trunc to i32 + %cast = bitcast i32 %ext to float + ret float %cast +} + define amdgpu_ps float @struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; GFX8-LABEL: name: struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX8: bb.1 (%ir-block.0): @@ -580,6 +623,49 @@ define amdgpu_ps float @struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgp ret float %cast } +define amdgpu_ps float @struct_buffer_load_i16_sext_wrong_width(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { + ; GFX8-LABEL: name: struct_buffer_load_i16_sext_wrong_width + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX8-NEXT: [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; GFX8-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_USHORT_BOTHEN]], 0, 8, implicit $exec + ; GFX8-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX12-LABEL: name: struct_buffer_load_i16_sext_wrong_width + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX12-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; GFX12-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN]], 0, 8, implicit $exec + ; GFX12-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + %trunc = trunc i16 %val to i8 + %ext = sext i8 %trunc to i32 + %cast = bitcast i32 %ext to float + ret float %cast +} + ; Natural mapping define amdgpu_ps half @struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; GFX8-LABEL: name: struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset -- GitLab From 9e5a77f252badfc932d1e28ee998746072ddc33f Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 10 Jan 2024 11:41:11 +0100 Subject: [PATCH 316/652] [SeparateConstOffsetFromGEP] Always emit i8 gep Always emit canonical i8 GEPs, don't try to preserve the original element type. As this is a backend pass, trying to preserve the type is not useful. --- .../Scalar/SeparateConstOffsetFromGEP.cpp | 58 +++---------------- .../AArch64/scalable-vector-geps.ll | 4 +- ...-gep-and-gvn-addrspace-addressing-modes.ll | 16 ++--- .../AMDGPU/split-gep-and-gvn.ll | 26 ++++----- .../NVPTX/split-gep-and-gvn.ll | 26 ++++----- .../NVPTX/split-gep.ll | 34 +++++------ .../RISCV/split-gep.ll | 48 +++++++-------- .../reassociate-geps-and-slsr-addrspace.ll | 8 +-- .../NVPTX/reassociate-geps-and-slsr.ll | 8 +-- 9 files changed, 93 insertions(+), 135 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp index 225dd454068c..d2fed11445e4 100644 --- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp +++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp @@ -1093,67 +1093,25 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) { // => add the offset // // %gep2 ; clone of %gep - // %new.gep = gep %gep2, + // %new.gep = gep i8, %gep2, %offset // %gep ; will be removed // ... %gep ... // // => replace all uses of %gep with %new.gep and remove %gep // // %gep2 ; clone of %gep - // %new.gep = gep %gep2, - // ... %new.gep ... - // - // If AccumulativeByteOffset is not a multiple of sizeof(*%gep), we emit an - // uglygep (http://llvm.org/docs/GetElementPtr.html#what-s-an-uglygep): - // bitcast %gep2 to i8*, add the offset, and bitcast the result back to the - // type of %gep. - // - // %gep2 ; clone of %gep - // %0 = bitcast %gep2 to i8* - // %uglygep = gep %0, - // %new.gep = bitcast %uglygep to + // %new.gep = gep i8, %gep2, %offset // ... %new.gep ... Instruction *NewGEP = GEP->clone(); NewGEP->insertBefore(GEP); - // Per ANSI C standard, signed / unsigned = unsigned and signed % unsigned = - // unsigned.. Therefore, we cast ElementTypeSizeOfGEP to signed because it is - // used with unsigned integers later. - int64_t ElementTypeSizeOfGEP = static_cast( - DL->getTypeAllocSize(GEP->getResultElementType())); Type *PtrIdxTy = DL->getIndexType(GEP->getType()); - if (AccumulativeByteOffset % ElementTypeSizeOfGEP == 0) { - // Very likely. As long as %gep is naturally aligned, the byte offset we - // extracted should be a multiple of sizeof(*%gep). - int64_t Index = AccumulativeByteOffset / ElementTypeSizeOfGEP; - NewGEP = GetElementPtrInst::Create(GEP->getResultElementType(), NewGEP, - ConstantInt::get(PtrIdxTy, Index, true), - GEP->getName(), GEP); - NewGEP->copyMetadata(*GEP); - // Inherit the inbounds attribute of the original GEP. - cast(NewGEP)->setIsInBounds(GEPWasInBounds); - } else { - // Unlikely but possible. For example, - // #pragma pack(1) - // struct S { - // int a[3]; - // int64 b[8]; - // }; - // #pragma pack() - // - // Suppose the gep before extraction is &s[i + 1].b[j + 3]. After - // extraction, it becomes &s[i].b[j] and AccumulativeByteOffset is - // sizeof(S) + 3 * sizeof(int64) = 100, which is not a multiple of - // sizeof(int64). - // - // Emit an uglygep in this case. - IRBuilder<> Builder(GEP); - NewGEP = cast(Builder.CreateGEP( - Builder.getInt8Ty(), NewGEP, - {ConstantInt::get(PtrIdxTy, AccumulativeByteOffset, true)}, "uglygep", - GEPWasInBounds)); - NewGEP->copyMetadata(*GEP); - } + IRBuilder<> Builder(GEP); + NewGEP = cast(Builder.CreateGEP( + Builder.getInt8Ty(), NewGEP, + {ConstantInt::get(PtrIdxTy, AccumulativeByteOffset, true)}, + GEP->getName(), GEPWasInBounds)); + NewGEP->copyMetadata(*GEP); GEP->replaceAllUsesWith(NewGEP); GEP->eraseFromParent(); diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AArch64/scalable-vector-geps.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AArch64/scalable-vector-geps.ll index 31d166506a4e..63148f5f2d47 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AArch64/scalable-vector-geps.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AArch64/scalable-vector-geps.ll @@ -20,7 +20,7 @@ define ptr @test1(ptr %base, i64 %idx) #0 { define ptr @test2(ptr %base, i64 %idx) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE:%.*]], i64 3, i64 [[IDX:%.*]] -; CHECK-NEXT: [[GEP2:%.*]] = getelementptr float, ptr [[TMP1]], i64 1 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4 ; CHECK-NEXT: ret ptr [[GEP2]] ; %idx.next = add nuw nsw i64 %idx, 1 @@ -57,7 +57,7 @@ define ptr @test4(ptr %base, i64 %idx) { define ptr @test5(ptr %base, i64 %idx) { ; CHECK-LABEL: @test5( ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [8 x ], ptr [[BASE:%.*]], i64 1, i64 3, i64 [[IDX:%.*]] -; CHECK-NEXT: [[GEP2:%.*]] = getelementptr float, ptr [[TMP1]], i64 1 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4 ; CHECK-NEXT: ret ptr [[GEP2]] ; %idx.next = add nuw nsw i64 %idx, 1 diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll index 2cd7fdfce35e..427681ac724e 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll @@ -11,9 +11,9 @@ define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, ptr addrspace(1) nocaptu ; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i64 ; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64 ; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 [[TMP1]], i64 [[TMP]] -; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 1 -; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 32 -; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 33 +; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 4 +; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 128 +; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 132 ; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 4 ; IR-NEXT: ret void ; @@ -51,7 +51,7 @@ define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, pt ; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP1]], i64 [[TMP]] ; IR-NEXT: [[TMP6:%.*]] = add i32 [[Y]], 255 ; IR-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i64 -; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[TMP2]], i64 255 +; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 1020 ; IR-NEXT: [[TMP12:%.*]] = add i32 [[X]], 256 ; IR-NEXT: [[TMP13:%.*]] = sext i32 [[TMP12]] to i64 ; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP]] @@ -91,13 +91,13 @@ define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(i32 %x, i32 %y ; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 [[X]], i32 [[Y]] ; IR-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(3) [[TMP2]], align 4 ; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 -; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 255 +; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 1020 ; IR-NEXT: [[TMP10:%.*]] = load float, ptr addrspace(3) [[TMP82]], align 4 ; IR-NEXT: [[TMP11:%.*]] = fadd float [[TMP5]], [[TMP10]] -; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 16128 +; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 64512 ; IR-NEXT: [[TMP16:%.*]] = load float, ptr addrspace(3) [[TMP144]], align 4 ; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP11]], [[TMP16]] -; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 16383 +; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 65532 ; IR-NEXT: [[TMP20:%.*]] = load float, ptr addrspace(3) [[TMP187]], align 4 ; IR-NEXT: [[TMP21:%.*]] = fadd float [[TMP17]], [[TMP20]] ; IR-NEXT: store float [[TMP21]], ptr addrspace(1) [[OUTPUT]], align 4 @@ -134,7 +134,7 @@ define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, ; IR-NEXT: [[TMP27:%.*]] = shl i32 [[TMP23]], 2 ; IR-NEXT: [[TMP28:%.*]] = sext i32 [[TMP27]] to i64 ; IR-NEXT: [[TMP29:%.*]] = getelementptr [0 x <4 x i32>], ptr addrspace(4) [[TMP1]], i64 0, i64 [[TMP28]], !amdgpu.uniform [[META0]] -; IR-NEXT: [[TMP30:%.*]] = getelementptr <4 x i32>, ptr addrspace(4) [[TMP29]], i64 3, !amdgpu.uniform [[META0]] +; IR-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP29]], i64 48, !amdgpu.uniform [[META0]] ; IR-NEXT: [[TMP31:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP30]], align 16, !invariant.load [[META0]] ; IR-NEXT: [[TMP32:%.*]] = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> [[TMP26]], <4 x i32> [[TMP31]], i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #[[ATTR3]] ; IR-NEXT: [[TMP33:%.*]] = extractelement <4 x float> [[TMP32]], i32 0 diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll index 6ef8a38dfd45..b53c04818785 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll @@ -26,15 +26,15 @@ define void @sum_of_array(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[I3:%.*]] = addrspacecast ptr addrspace(3) [[I2]] to ptr ; IR-NEXT: [[I4:%.*]] = load float, ptr [[I3]], align 4 ; IR-NEXT: [[I5:%.*]] = fadd float [[I4]], 0.000000e+00 -; IR-NEXT: [[I87:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 1 +; IR-NEXT: [[I87:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 4 ; IR-NEXT: [[I9:%.*]] = addrspacecast ptr addrspace(3) [[I87]] to ptr ; IR-NEXT: [[I10:%.*]] = load float, ptr [[I9]], align 4 ; IR-NEXT: [[I11:%.*]] = fadd float [[I5]], [[I10]] -; IR-NEXT: [[I1412:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 32 +; IR-NEXT: [[I1412:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 128 ; IR-NEXT: [[I15:%.*]] = addrspacecast ptr addrspace(3) [[I1412]] to ptr ; IR-NEXT: [[I16:%.*]] = load float, ptr [[I15]], align 4 ; IR-NEXT: [[I17:%.*]] = fadd float [[I11]], [[I16]] -; IR-NEXT: [[I1818:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 33 +; IR-NEXT: [[I1818:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 132 ; IR-NEXT: [[I19:%.*]] = addrspacecast ptr addrspace(3) [[I1818]] to ptr ; IR-NEXT: [[I20:%.*]] = load float, ptr [[I19]], align 4 ; IR-NEXT: [[I21:%.*]] = fadd float [[I17]], [[I20]] @@ -88,15 +88,15 @@ define void @sum_of_array2(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[I3:%.*]] = addrspacecast ptr addrspace(3) [[I2]] to ptr ; IR-NEXT: [[I4:%.*]] = load float, ptr [[I3]], align 4 ; IR-NEXT: [[I5:%.*]] = fadd float [[I4]], 0.000000e+00 -; IR-NEXT: [[I77:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 1 +; IR-NEXT: [[I77:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 4 ; IR-NEXT: [[I8:%.*]] = addrspacecast ptr addrspace(3) [[I77]] to ptr ; IR-NEXT: [[I9:%.*]] = load float, ptr [[I8]], align 4 ; IR-NEXT: [[I10:%.*]] = fadd float [[I5]], [[I9]] -; IR-NEXT: [[I1212:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 32 +; IR-NEXT: [[I1212:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 128 ; IR-NEXT: [[I13:%.*]] = addrspacecast ptr addrspace(3) [[I1212]] to ptr ; IR-NEXT: [[I14:%.*]] = load float, ptr [[I13]], align 4 ; IR-NEXT: [[I15:%.*]] = fadd float [[I10]], [[I14]] -; IR-NEXT: [[I1618:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 33 +; IR-NEXT: [[I1618:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 132 ; IR-NEXT: [[I17:%.*]] = addrspacecast ptr addrspace(3) [[I1618]] to ptr ; IR-NEXT: [[I18:%.*]] = load float, ptr [[I17]], align 4 ; IR-NEXT: [[I19:%.*]] = fadd float [[I15]], [[I18]] @@ -149,15 +149,15 @@ define void @sum_of_array3(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[I3:%.*]] = addrspacecast ptr addrspace(3) [[I2]] to ptr ; IR-NEXT: [[I4:%.*]] = load float, ptr [[I3]], align 4 ; IR-NEXT: [[I5:%.*]] = fadd float [[I4]], 0.000000e+00 -; IR-NEXT: [[I87:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 1 +; IR-NEXT: [[I87:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 4 ; IR-NEXT: [[I9:%.*]] = addrspacecast ptr addrspace(3) [[I87]] to ptr ; IR-NEXT: [[I10:%.*]] = load float, ptr [[I9]], align 4 ; IR-NEXT: [[I11:%.*]] = fadd float [[I5]], [[I10]] -; IR-NEXT: [[I1412:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 32 +; IR-NEXT: [[I1412:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 128 ; IR-NEXT: [[I15:%.*]] = addrspacecast ptr addrspace(3) [[I1412]] to ptr ; IR-NEXT: [[I16:%.*]] = load float, ptr [[I15]], align 4 ; IR-NEXT: [[I17:%.*]] = fadd float [[I11]], [[I16]] -; IR-NEXT: [[I1818:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 33 +; IR-NEXT: [[I1818:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 132 ; IR-NEXT: [[I19:%.*]] = addrspacecast ptr addrspace(3) [[I1818]] to ptr ; IR-NEXT: [[I20:%.*]] = load float, ptr [[I19]], align 4 ; IR-NEXT: [[I21:%.*]] = fadd float [[I17]], [[I20]] @@ -209,15 +209,15 @@ define void @sum_of_array4(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[I3:%.*]] = addrspacecast ptr addrspace(3) [[I2]] to ptr ; IR-NEXT: [[I4:%.*]] = load float, ptr [[I3]], align 4 ; IR-NEXT: [[I5:%.*]] = fadd float [[I4]], 0.000000e+00 -; IR-NEXT: [[I77:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 1 +; IR-NEXT: [[I77:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 4 ; IR-NEXT: [[I8:%.*]] = addrspacecast ptr addrspace(3) [[I77]] to ptr ; IR-NEXT: [[I9:%.*]] = load float, ptr [[I8]], align 4 ; IR-NEXT: [[I10:%.*]] = fadd float [[I5]], [[I9]] -; IR-NEXT: [[I1212:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 32 +; IR-NEXT: [[I1212:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 128 ; IR-NEXT: [[I13:%.*]] = addrspacecast ptr addrspace(3) [[I1212]] to ptr ; IR-NEXT: [[I14:%.*]] = load float, ptr [[I13]], align 4 ; IR-NEXT: [[I15:%.*]] = fadd float [[I10]], [[I14]] -; IR-NEXT: [[I1618:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[I2]], i32 33 +; IR-NEXT: [[I1618:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[I2]], i32 132 ; IR-NEXT: [[I17:%.*]] = addrspacecast ptr addrspace(3) [[I1618]] to ptr ; IR-NEXT: [[I18:%.*]] = load float, ptr [[I17]], align 4 ; IR-NEXT: [[I19:%.*]] = fadd float [[I15]], [[I18]] @@ -270,7 +270,7 @@ define void @reunion(i32 %x, i32 %y, ptr %input) { ; IR-NEXT: [[P0:%.*]] = getelementptr float, ptr [[INPUT]], i64 [[I]] ; IR-NEXT: [[V0:%.*]] = load float, ptr [[P0]], align 4 ; IR-NEXT: call void @use(float [[V0]]) -; IR-NEXT: [[P13:%.*]] = getelementptr inbounds float, ptr [[P0]], i64 5 +; IR-NEXT: [[P13:%.*]] = getelementptr inbounds i8, ptr [[P0]], i64 20 ; IR-NEXT: [[V1:%.*]] = load float, ptr [[P13]], align 4 ; IR-NEXT: call void @use(float [[V1]]) ; IR-NEXT: ret void diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll index 1391cb4e7b49..79398a80ac65 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll @@ -28,15 +28,15 @@ define void @sum_of_array(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr ; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 ; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 -; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 4 ; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr ; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 ; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] -; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 128 ; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr ; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 ; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] -; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 132 ; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr ; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 ; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] @@ -94,15 +94,15 @@ define void @sum_of_array2(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr ; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 ; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 -; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 4 ; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr ; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 ; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] -; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 128 ; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr ; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 ; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] -; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 132 ; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr ; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 ; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] @@ -161,15 +161,15 @@ define void @sum_of_array3(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr ; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 ; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 -; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 4 ; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr ; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 ; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] -; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 128 ; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr ; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 ; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] -; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 132 ; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr ; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 ; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] @@ -228,15 +228,15 @@ define void @sum_of_array4(i32 %x, i32 %y, ptr nocapture %output) { ; IR-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr ; IR-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 ; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00 -; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 1 +; IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 4 ; IR-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr ; IR-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 ; IR-NEXT: [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]] -; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 32 +; IR-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 128 ; IR-NEXT: [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr ; IR-NEXT: [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4 ; IR-NEXT: [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]] -; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i64 33 +; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 132 ; IR-NEXT: [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr ; IR-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4 ; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]] @@ -296,7 +296,7 @@ define void @reunion(i32 %x, i32 %y, ptr %input) { ; IR-NEXT: [[P0:%.*]] = getelementptr float, ptr [[INPUT]], i64 [[TMP0]] ; IR-NEXT: [[V0:%.*]] = load float, ptr [[P0]], align 4 ; IR-NEXT: call void @use(float [[V0]]) -; IR-NEXT: [[P13:%.*]] = getelementptr inbounds float, ptr [[P0]], i64 5 +; IR-NEXT: [[P13:%.*]] = getelementptr inbounds i8, ptr [[P0]], i64 20 ; IR-NEXT: [[V1:%.*]] = load float, ptr [[P13]], align 4 ; IR-NEXT: call void @use(float [[V1]]) ; IR-NEXT: ret void diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll index 67d78fc90512..49c6a46b136d 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll @@ -19,7 +19,7 @@ define ptr @struct(i32 %i) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [1024 x %struct.S], ptr @struct_array, i64 0, i64 [[TMP0]], i32 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i64 10 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 80 ; CHECK-NEXT: ret ptr [[P2]] ; entry: @@ -40,7 +40,7 @@ define ptr @sext_add(i32 %i, i32 %j) { ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[TMP0]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 [[TMP2]], i64 [[TMP1]] -; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 32 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 128 ; CHECK-NEXT: ret ptr [[P1]] ; entry: @@ -68,7 +68,7 @@ define ptr @ext_add_no_overflow(i64 %a, i32 %b, i64 %c, i32 %d) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[D]] to i64 ; CHECK-NEXT: [[J4:%.*]] = add i64 [[C]], [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 [[I2]], i64 [[J4]] -; CHECK-NEXT: [[P5:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 33 +; CHECK-NEXT: [[P5:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 132 ; CHECK-NEXT: ret ptr [[P5]] ; %b1 = add nsw i32 %b, 1 @@ -92,7 +92,7 @@ define void @sext_zext(i32 %a, i32 %b, ptr %out1, ptr %out2) { ; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[A]] to i48 ; CHECK-NEXT: [[TMP4:%.*]] = zext i48 [[TMP3]] to i64 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 [[TMP4]], i64 [[TMP2]] -; CHECK-NEXT: [[P11:%.*]] = getelementptr float, ptr [[TMP5]], i64 32 +; CHECK-NEXT: [[P11:%.*]] = getelementptr i8, ptr [[TMP5]], i64 128 ; CHECK-NEXT: store ptr [[P11]], ptr [[OUT1]], align 8 ; CHECK-NEXT: [[TMP6:%.*]] = add nsw i32 [[B]], 4 ; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i48 @@ -100,7 +100,7 @@ define void @sext_zext(i32 %a, i32 %b, ptr %out1, ptr %out2) { ; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[A]] to i48 ; CHECK-NEXT: [[TMP10:%.*]] = sext i48 [[TMP9]] to i64 ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 [[TMP10]], i64 [[TMP8]] -; CHECK-NEXT: [[P22:%.*]] = getelementptr float, ptr [[TMP11]], i64 96 +; CHECK-NEXT: [[P22:%.*]] = getelementptr i8, ptr [[TMP11]], i64 384 ; CHECK-NEXT: store ptr [[P22]], ptr [[OUT2]], align 8 ; CHECK-NEXT: ret void ; @@ -137,7 +137,7 @@ define ptr @sext_or(i64 %a, i32 %b) { ; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[B1]] to i64 ; CHECK-NEXT: [[I2:%.*]] = add i64 [[A]], [[TMP0]] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 [[I2]], i64 [[J]] -; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 32 +; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 128 ; CHECK-NEXT: ret ptr [[P3]] ; entry: @@ -162,7 +162,7 @@ define ptr @expr(i64 %a, i64 %b, ptr %out) { ; CHECK-NEXT: [[B5:%.*]] = add i64 [[B]], 5 ; CHECK-NEXT: [[I2:%.*]] = add i64 [[B]], [[A]] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 [[I2]], i64 0 -; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i64 160 +; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 640 ; CHECK-NEXT: store i64 [[B5]], ptr [[OUT]], align 8 ; CHECK-NEXT: ret ptr [[P3]] ; @@ -186,7 +186,7 @@ define ptr @sext_expr(i32 %a, i32 %b, i32 %c, i64 %d) { ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP0]], [[TMP3]] ; CHECK-NEXT: [[I1:%.*]] = add i64 [[D]], [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 0, i64 [[I1]] -; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 8 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 32 ; CHECK-NEXT: ret ptr [[P2]] ; entry: @@ -205,7 +205,7 @@ define ptr @sub(i64 %i, i64 %j) { ; CHECK-SAME: i64 [[I:%.*]], i64 [[J:%.*]]) { ; CHECK-NEXT: [[J22:%.*]] = sub i64 0, [[J]] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 [[I]], i64 [[J22]] -; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 -155 +; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 -620 ; CHECK-NEXT: ret ptr [[P3]] ; %i2 = sub i64 %i, 5 ; i - 5 @@ -225,8 +225,8 @@ define ptr @packed_struct(i32 %i, i32 %j) { ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[J]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr [1024 x %struct.Packed], ptr [[S]], i64 0, i64 [[TMP0]], i32 1, i64 [[TMP1]] -; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 100 -; CHECK-NEXT: ret ptr [[UGLYGEP]] +; CHECK-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 100 +; CHECK-NEXT: ret ptr [[ARRAYIDX33]] ; entry: %s = alloca [1024 x %struct.Packed], align 16 @@ -292,7 +292,7 @@ define ptr @apint(i1 %a) { ; CHECK-NEXT: [[TMP0:%.*]] = sext i1 [[A]] to i4 ; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[TMP0]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr [32 x [32 x float]], ptr @float_2d_array, i64 0, i64 0, i64 [[TMP1]] -; CHECK-NEXT: [[P1:%.*]] = getelementptr float, ptr [[TMP2]], i64 15 +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[TMP2]], i64 60 ; CHECK-NEXT: ret ptr [[P1]] ; entry: @@ -329,7 +329,7 @@ define ptr @shl_add_or(i64 %a, ptr %ptr) { ; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A]], 2 ; CHECK-NEXT: [[OR2:%.*]] = add i64 [[SHL]], 1 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[PTR]], i64 [[OR2]] -; CHECK-NEXT: [[P3:%.*]] = getelementptr float, ptr [[TMP0]], i64 12 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 48 ; CHECK-NEXT: ret ptr [[P3]] ; entry: @@ -358,8 +358,8 @@ define ptr @sign_mod_unsign(ptr %ptr, i64 %idx) { ; CHECK-SAME: ptr [[PTR:%.*]], i64 [[IDX:%.*]]) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT0:%.*]], ptr [[PTR]], i64 0, i32 3, i64 [[IDX]], i32 1 -; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -64 -; CHECK-NEXT: ret ptr [[UGLYGEP]] +; CHECK-NEXT: [[PTR22:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -64 +; CHECK-NEXT: ret ptr [[PTR22]] ; entry: %arrayidx = add nsw i64 %idx, -2 @@ -373,7 +373,7 @@ define ptr @trunk_explicit(ptr %ptr, i64 %idx) { ; CHECK-SAME: ptr [[PTR:%.*]], i64 [[IDX:%.*]]) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT0:%.*]], ptr [[PTR]], i64 0, i32 3, i64 [[IDX]], i32 1 -; CHECK-NEXT: [[PTR21:%.*]] = getelementptr inbounds [[STRUCT2:%.*]], ptr [[TMP0]], i64 134 +; CHECK-NEXT: [[PTR21:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 3216 ; CHECK-NEXT: ret ptr [[PTR21]] ; entry: @@ -390,7 +390,7 @@ define ptr @trunk_long_idx(ptr %ptr, i64 %idx) { ; CHECK-SAME: ptr [[PTR:%.*]], i64 [[IDX:%.*]]) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT0:%.*]], ptr [[PTR]], i64 0, i32 3, i64 [[IDX]], i32 1 -; CHECK-NEXT: [[PTR21:%.*]] = getelementptr inbounds [[STRUCT2:%.*]], ptr [[TMP0]], i64 134 +; CHECK-NEXT: [[PTR21:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 3216 ; CHECK-NEXT: ret ptr [[PTR21]] ; entry: diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll index ed0a1185985c..3742ea7fb0c2 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll @@ -12,11 +12,11 @@ define i64 @test1(ptr %array, i64 %i, i64 %j) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[ARRAY:%.*]], i64 [[I]] -; CHECK-NEXT: [[GEP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 5 +; CHECK-NEXT: [[GEP4:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 40 ; CHECK-NEXT: store i64 [[J:%.*]], ptr [[GEP4]], align 8 -; CHECK-NEXT: [[GEP26:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 6 +; CHECK-NEXT: [[GEP26:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 48 ; CHECK-NEXT: store i64 [[J]], ptr [[GEP26]], align 8 -; CHECK-NEXT: [[GEP38:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 35 +; CHECK-NEXT: [[GEP38:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 280 ; CHECK-NEXT: store i64 [[ADD]], ptr [[GEP38]], align 8 ; CHECK-NEXT: ret i64 undef ; @@ -40,11 +40,11 @@ define i32 @test2(ptr %array, i32 %i, i32 %j) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[ARRAY:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 20 ; CHECK-NEXT: store i32 [[J:%.*]], ptr [[GEP2]], align 4 -; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 6 +; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 24 ; CHECK-NEXT: store i32 [[J]], ptr [[GEP54]], align 4 -; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 35 +; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 140 ; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP86]], align 4 ; CHECK-NEXT: ret i32 undef ; @@ -72,13 +72,13 @@ define i32 @test3(ptr %array, i32 %i) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[ARRAY:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 20 ; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP2]], align 4 ; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[I]], 6 -; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 6 +; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 24 ; CHECK-NEXT: store i32 [[ADD3]], ptr [[GEP54]], align 4 ; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[I]], 35 -; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 35 +; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 140 ; CHECK-NEXT: store i32 [[ADD6]], ptr [[GEP86]], align 4 ; CHECK-NEXT: ret i32 undef ; @@ -105,11 +105,11 @@ define i32 @test4(ptr %array2, i32 %i) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [50 x i32], ptr [[ARRAY2:%.*]], i64 [[TMP0]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 255 +; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 1020 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP3]], align 4 -; CHECK-NEXT: [[GEP56:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 256 +; CHECK-NEXT: [[GEP56:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 1024 ; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP56]], align 4 -; CHECK-NEXT: [[GEP89:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 285 +; CHECK-NEXT: [[GEP89:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 1140 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP89]], align 4 ; CHECK-NEXT: ret i32 undef ; @@ -136,10 +136,10 @@ define i32 @test5(ptr %array2, i32 %i, i64 %j) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [50 x i32], ptr [[ARRAY2:%.*]], i64 [[TMP0]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 255 +; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 1020 ; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP3]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr [50 x i32], ptr [[ARRAY2]], i64 [[TMP0]], i64 [[J:%.*]] -; CHECK-NEXT: [[GEP55:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 300 +; CHECK-NEXT: [[GEP55:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 1200 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP55]], align 4 ; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[I]], 35 ; CHECK-NEXT: [[SEXT7:%.*]] = sext i32 [[ADD6]] to i64 @@ -171,7 +171,7 @@ define i64 @test6(ptr %array, i64 %i, i64 %j) { ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[ARRAY:%.*]], i64 [[J:%.*]] ; CHECK-NEXT: store i64 [[ADD]], ptr [[GEP]], align 8 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[ARRAY]], i64 [[I]] -; CHECK-NEXT: [[GEP52:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 6 +; CHECK-NEXT: [[GEP52:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 48 ; CHECK-NEXT: store i64 [[I]], ptr [[GEP52]], align 8 ; CHECK-NEXT: store i64 [[I]], ptr [[TMP0]], align 8 ; CHECK-NEXT: ret i64 undef @@ -196,15 +196,15 @@ define i32 @test7(ptr %array, i32 %i, i32 %j, i32 %k) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[ARRAY:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 20 ; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP2]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[K:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[ARRAY]], i64 [[TMP2]] -; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 6 +; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 24 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP54]], align 4 ; CHECK-NEXT: [[TMP4:%.*]] = sext i32 [[J:%.*]] to i64 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[ARRAY]], i64 [[TMP4]] -; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 35 +; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 140 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP86]], align 4 ; CHECK-NEXT: ret i32 undef ; @@ -231,13 +231,13 @@ define i32 @test8(ptr %array, ptr %array2, ptr %array3, i32 %i) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[ARRAY:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 20 ; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP2]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY2:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 6 +; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 24 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP54]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[ARRAY3:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 35 +; CHECK-NEXT: [[GEP86:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 140 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP86]], align 4 ; CHECK-NEXT: ret i32 undef ; @@ -264,12 +264,12 @@ define i32 @test9(ptr %array, i32 %i) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I:%.*]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [50 x i32], ptr [[ARRAY:%.*]], i64 0, i64 [[TMP0]] -; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 20 ; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP2]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr [50 x i32], ptr [[ARRAY]], i64 [[TMP0]], i64 [[TMP0]] -; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 6 +; CHECK-NEXT: [[GEP54:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 24 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP54]], align 4 -; CHECK-NEXT: [[GEP87:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 335 +; CHECK-NEXT: [[GEP87:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 1340 ; CHECK-NEXT: store i32 [[I]], ptr [[GEP87]], align 4 ; CHECK-NEXT: ret i32 undef ; diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll index 9cf725840abd..0af4093c184e 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll @@ -10,12 +10,12 @@ define amdgpu_kernel void @slsr_after_reassociate_global_geps_mubuf_max_offset(p ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr addrspace(1) [[ARR]], i64 [[TMP0]] -; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP1]], i64 1023 +; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP1]], i64 4092 ; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(1) [[P12]], align 4 ; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(1) [[TMP1]], i64 [[TMP2]] -; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP3]], i64 1023 +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP3]], i64 4092 ; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(1) [[P24]], align 4 ; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: ret void @@ -76,12 +76,12 @@ define amdgpu_kernel void @slsr_after_reassociate_lds_geps_ds_max_offset(ptr add ; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(3) noalias [[ARR:%.*]], i32 [[I:%.*]]) { ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr addrspace(3) [[ARR]], i32 [[I]] -; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP0]], i32 16383 +; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP0]], i32 65532 ; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(3) [[P12]], align 4 ; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[I]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP0]], i32 [[TMP1]] -; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP2]], i32 16383 +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 65532 ; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(3) [[P24]], align 4 ; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll index e65b9b1a99a6..916f3b32887b 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll @@ -32,20 +32,20 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) { ; CHECK-SAME: ptr [[ARR:%.*]], i32 [[I:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[ARR]], i64 [[TMP1]] -; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 5 +; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 20 ; CHECK-NEXT: [[V1:%.*]] = load float, ptr [[P12]], align 4 ; CHECK-NEXT: call void @foo(float [[V1]]) ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP1]], 2 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP2]], i64 [[TMP3]] -; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 5 +; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 20 ; CHECK-NEXT: [[V2:%.*]] = load float, ptr [[P24]], align 4 ; CHECK-NEXT: call void @foo(float [[V2]]) ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP4]], i64 [[TMP3]] -; CHECK-NEXT: [[P36:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 5 +; CHECK-NEXT: [[P36:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 20 ; CHECK-NEXT: [[V3:%.*]] = load float, ptr [[P36]], align 4 ; CHECK-NEXT: call void @foo(float [[V3]]) ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i64 [[TMP3]] -; CHECK-NEXT: [[P48:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 5 +; CHECK-NEXT: [[P48:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 20 ; CHECK-NEXT: [[V4:%.*]] = load float, ptr [[P48]], align 4 ; CHECK-NEXT: call void @foo(float [[V4]]) ; CHECK-NEXT: ret void -- GitLab From 29f98d6c25e237d311038ce225f0b3109925d400 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 10 Jan 2024 19:33:18 +0800 Subject: [PATCH 317/652] [InstCombine] Fold bitwise logic with intrinsics (#77460) This patch does the following folds: ``` bitwise(fshl (A, B, ShAmt), fshl(C, D, ShAmt)) -> fshl(bitwise(A, C), bitwise(B, D), ShAmt) bitwise(fshr (A, B, ShAmt), fshr(C, D, ShAmt)) -> fshr(bitwise(A, C), bitwise(B, D), ShAmt) bitwise(bswap(A), bswap(B)) -> bswap(bitwise(A, B)) bitwise(bswap(A), C) -> bswap(bitwise(A, bswap(C))) bitwise(bitreverse(A), bitreverse(B)) -> bitreverse(bitwise(A, B)) bitwise(bitreverse(A), C) -> bitreverse(bitwise(A, bitreverse(C))) ``` Alive2: https://alive2.llvm.org/ce/z/iZN_TL --- .../InstCombine/InstCombineAndOrXor.cpp | 114 +++++---- .../InstCombine/bitreverse-known-bits.ll | 5 +- .../InstCombine/bitwiselogic-bitmanip.ll | 220 ++++++++++++++++++ .../test/Transforms/InstCombine/bswap-fold.ll | 8 +- 4 files changed, 293 insertions(+), 54 deletions(-) create mode 100644 llvm/test/Transforms/InstCombine/bitwiselogic-bitmanip.ll diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index c03f50d75814..0620752e3213 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -46,44 +46,6 @@ static Value *getFCmpValue(unsigned Code, Value *LHS, Value *RHS, return Builder.CreateFCmp(NewPred, LHS, RHS); } -/// Transform BITWISE_OP(BSWAP(A),BSWAP(B)) or -/// BITWISE_OP(BSWAP(A), Constant) to BSWAP(BITWISE_OP(A, B)) -/// \param I Binary operator to transform. -/// \return Pointer to node that must replace the original binary operator, or -/// null pointer if no transformation was made. -static Value *SimplifyBSwap(BinaryOperator &I, - InstCombiner::BuilderTy &Builder) { - assert(I.isBitwiseLogicOp() && "Unexpected opcode for bswap simplifying"); - - Value *OldLHS = I.getOperand(0); - Value *OldRHS = I.getOperand(1); - - Value *NewLHS; - if (!match(OldLHS, m_BSwap(m_Value(NewLHS)))) - return nullptr; - - Value *NewRHS; - const APInt *C; - - if (match(OldRHS, m_BSwap(m_Value(NewRHS)))) { - // OP( BSWAP(x), BSWAP(y) ) -> BSWAP( OP(x, y) ) - if (!OldLHS->hasOneUse() && !OldRHS->hasOneUse()) - return nullptr; - // NewRHS initialized by the matcher. - } else if (match(OldRHS, m_APInt(C))) { - // OP( BSWAP(x), CONSTANT ) -> BSWAP( OP(x, BSWAP(CONSTANT) ) ) - if (!OldLHS->hasOneUse()) - return nullptr; - NewRHS = ConstantInt::get(I.getType(), C->byteSwap()); - } else - return nullptr; - - Value *BinOp = Builder.CreateBinOp(I.getOpcode(), NewLHS, NewRHS); - Function *F = Intrinsic::getDeclaration(I.getModule(), Intrinsic::bswap, - I.getType()); - return Builder.CreateCall(F, BinOp); -} - /// Emit a computation of: (V >= Lo && V < Hi) if Inside is true, otherwise /// (V < Lo || V >= Hi). This method expects that Lo < Hi. IsSigned indicates /// whether to treat V, Lo, and Hi as signed or not. @@ -2159,6 +2121,64 @@ Instruction *InstCombinerImpl::foldBinOpOfDisplacedShifts(BinaryOperator &I) { return BinaryOperator::Create(ShiftOp, NewC, ShAmt); } +// Fold and/or/xor with two equal intrinsic IDs: +// bitwise(fshl (A, B, ShAmt), fshl(C, D, ShAmt)) +// -> fshl(bitwise(A, C), bitwise(B, D), ShAmt) +// bitwise(fshr (A, B, ShAmt), fshr(C, D, ShAmt)) +// -> fshr(bitwise(A, C), bitwise(B, D), ShAmt) +// bitwise(bswap(A), bswap(B)) -> bswap(bitwise(A, B)) +// bitwise(bswap(A), C) -> bswap(bitwise(A, bswap(C))) +// bitwise(bitreverse(A), bitreverse(B)) -> bitreverse(bitwise(A, B)) +// bitwise(bitreverse(A), C) -> bitreverse(bitwise(A, bitreverse(C))) +static Instruction * +foldBitwiseLogicWithIntrinsics(BinaryOperator &I, + InstCombiner::BuilderTy &Builder) { + assert(I.isBitwiseLogicOp() && "Should and/or/xor"); + if (!I.getOperand(0)->hasOneUse()) + return nullptr; + IntrinsicInst *X = dyn_cast(I.getOperand(0)); + if (!X) + return nullptr; + + IntrinsicInst *Y = dyn_cast(I.getOperand(1)); + if (Y && (!Y->hasOneUse() || X->getIntrinsicID() != Y->getIntrinsicID())) + return nullptr; + + Intrinsic::ID IID = X->getIntrinsicID(); + const APInt *RHSC; + // Try to match constant RHS. + if (!Y && (!(IID == Intrinsic::bswap || IID == Intrinsic::bitreverse) || + !match(I.getOperand(1), m_APInt(RHSC)))) + return nullptr; + + switch (IID) { + case Intrinsic::fshl: + case Intrinsic::fshr: { + if (X->getOperand(2) != Y->getOperand(2)) + return nullptr; + Value *NewOp0 = + Builder.CreateBinOp(I.getOpcode(), X->getOperand(0), Y->getOperand(0)); + Value *NewOp1 = + Builder.CreateBinOp(I.getOpcode(), X->getOperand(1), Y->getOperand(1)); + Function *F = Intrinsic::getDeclaration(I.getModule(), IID, I.getType()); + return CallInst::Create(F, {NewOp0, NewOp1, X->getOperand(2)}); + } + case Intrinsic::bswap: + case Intrinsic::bitreverse: { + Value *NewOp0 = Builder.CreateBinOp( + I.getOpcode(), X->getOperand(0), + Y ? Y->getOperand(0) + : ConstantInt::get(I.getType(), IID == Intrinsic::bswap + ? RHSC->byteSwap() + : RHSC->reverseBits())); + Function *F = Intrinsic::getDeclaration(I.getModule(), IID, I.getType()); + return CallInst::Create(F, {NewOp0}); + } + default: + return nullptr; + } +} + // FIXME: We use commutative matchers (m_c_*) for some, but not all, matches // here. We should standardize that construct where it is needed or choose some // other way to ensure that commutated variants of patterns are not missed. @@ -2194,9 +2214,6 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) { if (Value *V = foldUsingDistributiveLaws(I)) return replaceInstUsesWith(I, V); - if (Value *V = SimplifyBSwap(I, Builder)) - return replaceInstUsesWith(I, V); - if (Instruction *R = foldBinOpShiftWithShift(I)) return R; @@ -2688,6 +2705,9 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) { if (Instruction *Res = foldBinOpOfDisplacedShifts(I)) return Res; + if (Instruction *Res = foldBitwiseLogicWithIntrinsics(I, Builder)) + return Res; + return nullptr; } @@ -3347,9 +3367,6 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { if (Value *V = foldUsingDistributiveLaws(I)) return replaceInstUsesWith(I, V); - if (Value *V = SimplifyBSwap(I, Builder)) - return replaceInstUsesWith(I, V); - Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); Type *Ty = I.getType(); if (Ty->isIntOrIntVectorTy(1)) { @@ -3884,6 +3901,9 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { return BinaryOperator::CreateAnd(X, ConstantInt::get(Ty, *C1 | *C2)); } + if (Instruction *Res = foldBitwiseLogicWithIntrinsics(I, Builder)) + return Res; + return nullptr; } @@ -4507,9 +4527,6 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) { if (SimplifyDemandedInstructionBits(I)) return &I; - if (Value *V = SimplifyBSwap(I, Builder)) - return replaceInstUsesWith(I, V); - if (Instruction *R = foldNot(I)) return R; @@ -4799,5 +4816,8 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) { if (Instruction *Res = foldBinOpOfDisplacedShifts(I)) return Res; + if (Instruction *Res = foldBitwiseLogicWithIntrinsics(I, Builder)) + return Res; + return nullptr; } diff --git a/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll b/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll index ad2b56f492fb..a8683e563874 100644 --- a/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll +++ b/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll @@ -46,9 +46,8 @@ define i1 @test3(i32 %arg) { define i8 @add_bitreverse(i8 %a) { ; CHECK-LABEL: @add_bitreverse( -; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -4 -; CHECK-NEXT: [[REVERSE:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[B]]), !range [[RNG0:![0-9]+]] -; CHECK-NEXT: [[C:%.*]] = or disjoint i8 [[REVERSE]], -16 +; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[A:%.*]], 15 +; CHECK-NEXT: [[C:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[TMP1]]) ; CHECK-NEXT: ret i8 [[C]] ; %b = and i8 %a, 252 diff --git a/llvm/test/Transforms/InstCombine/bitwiselogic-bitmanip.ll b/llvm/test/Transforms/InstCombine/bitwiselogic-bitmanip.ll new file mode 100644 index 000000000000..d733bd41f0bc --- /dev/null +++ b/llvm/test/Transforms/InstCombine/bitwiselogic-bitmanip.ll @@ -0,0 +1,220 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=instcombine -S | FileCheck %s + +define i32 @test_or_fshl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) { +; CHECK-LABEL: define i32 @test_or_fshl( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[B]], [[D]] +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[SH]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh) + %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_and_fshl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) { +; CHECK-LABEL: define i32 @test_and_fshl( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[B]], [[D]] +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[SH]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh) + %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh) + %ret = and i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_xor_fshl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) { +; CHECK-LABEL: define i32 @test_xor_fshl( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[B]], [[D]] +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[SH]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh) + %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh) + %ret = xor i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_fshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) { +; CHECK-LABEL: define i32 @test_or_fshr( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[B]], [[D]] +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.fshr.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[SH]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %sh) + %val2 = call i32 @llvm.fshr.i32(i32 %c, i32 %d, i32 %sh) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_fshl_cascade(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: define i32 @test_or_fshl_cascade( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A]], [[B]] +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[A]], [[B]] +; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], [[C]] +; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[C]] +; CHECK-NEXT: [[OR2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP3]], i32 [[TMP4]], i32 24) +; CHECK-NEXT: ret i32 [[OR2]] +; + %fshl1 = call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 24) + %fshl2 = call i32 @llvm.fshl.i32(i32 %b, i32 %b, i32 24) + %fshl3 = call i32 @llvm.fshl.i32(i32 %c, i32 %c, i32 24) + %or1 = or i32 %fshl1, %fshl2 + %or2 = or i32 %or1, %fshl3 + ret i32 %or2 +} +define i32 @test_or_bitreverse(i32 %a, i32 %b) { +; CHECK-LABEL: define i32 @test_or_bitreverse( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A]], [[B]] +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[TMP1]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.bitreverse.i32(i32 %a) + %val2 = call i32 @llvm.bitreverse.i32(i32 %b) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_bitreverse_constant(i32 %a, i32 %b) { +; CHECK-LABEL: define i32 @test_or_bitreverse_constant( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A]], 255 +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[TMP1]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.bitreverse.i32(i32 %a) + %ret = or i32 %val1, 4278190080 + ret i32 %ret +} +define i32 @test_or_bswap(i32 %a, i32 %b) { +; CHECK-LABEL: define i32 @test_or_bswap( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A]], [[B]] +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.bswap.i32(i32 %a) + %val2 = call i32 @llvm.bswap.i32(i32 %b) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_bswap_constant(i32 %a, i32 %b) { +; CHECK-LABEL: define i32 @test_or_bswap_constant( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A]], 255 +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.bswap.i32(i32 %a) + %ret = or i32 %val1, 4278190080 + ret i32 %ret +} + +; Negative tests + +define i32 @test_or_fshl_fshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) { +; CHECK-LABEL: define i32 @test_or_fshl_fshr( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A]], i32 [[B]], i32 [[SH]]) +; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.fshr.i32(i32 [[C]], i32 [[D]], i32 [[SH]]) +; CHECK-NEXT: [[RET:%.*]] = or i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh) + %val2 = call i32 @llvm.fshr.i32(i32 %c, i32 %d, i32 %sh) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_bitreverse_bswap(i32 %a, i32 %b) { +; CHECK-LABEL: define i32 @test_or_bitreverse_bswap( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[A]]) +; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.bswap.i32(i32 [[B]]) +; CHECK-NEXT: [[RET:%.*]] = or i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.bitreverse.i32(i32 %a) + %val2 = call i32 @llvm.bswap.i32(i32 %b) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_fshl_mismatched_shamt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh1, i32 %sh2) { +; CHECK-LABEL: define i32 @test_or_fshl_mismatched_shamt( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH1:%.*]], i32 [[SH2:%.*]]) { +; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A]], i32 [[B]], i32 [[SH1]]) +; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.fshl.i32(i32 [[C]], i32 [[D]], i32 [[SH2]]) +; CHECK-NEXT: [[RET:%.*]] = or i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh1) + %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh2) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_add_fshl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) { +; CHECK-LABEL: define i32 @test_add_fshl( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A]], i32 [[B]], i32 [[SH]]) +; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.fshl.i32(i32 [[C]], i32 [[D]], i32 [[SH]]) +; CHECK-NEXT: [[RET:%.*]] = add i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh) + %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh) + %ret = add i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_fshl_multiuse(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) { +; CHECK-LABEL: define i32 @test_or_fshl_multiuse( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A]], i32 [[B]], i32 [[SH]]) +; CHECK-NEXT: call void @use(i32 [[VAL1]]) +; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.fshl.i32(i32 [[C]], i32 [[D]], i32 [[SH]]) +; CHECK-NEXT: [[RET:%.*]] = or i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh) + call void @use(i32 %val1) + %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_bitreverse_multiuse(i32 %a, i32 %b) { +; CHECK-LABEL: define i32 @test_or_bitreverse_multiuse( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[A]]) +; CHECK-NEXT: call void @use(i32 [[VAL1]]) +; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[B]]) +; CHECK-NEXT: [[RET:%.*]] = or i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.bitreverse.i32(i32 %a) + call void @use(i32 %val1) + %val2 = call i32 @llvm.bitreverse.i32(i32 %b) + %ret = or i32 %val1, %val2 + ret i32 %ret +} +define i32 @test_or_fshl_constant(i32 %a, i32 %b, i32 %sh) { +; CHECK-LABEL: define i32 @test_or_fshl_constant( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[SH:%.*]]) { +; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A]], i32 [[B]], i32 [[SH]]) +; CHECK-NEXT: [[RET:%.*]] = or i32 [[VAL1]], -16777216 +; CHECK-NEXT: ret i32 [[RET]] +; + %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh) + %ret = or i32 %val1, 4278190080 + ret i32 %ret +} + +declare void @use(i32) +declare i32 @llvm.fshl.i32(i32, i32, i32) +declare i32 @llvm.fshr.i32(i32, i32, i32) +declare i32 @llvm.bitreverse.i32(i32) +declare i32 @llvm.bswap.i32(i32) diff --git a/llvm/test/Transforms/InstCombine/bswap-fold.ll b/llvm/test/Transforms/InstCombine/bswap-fold.ll index a9061d3c95ce..05933d37057c 100644 --- a/llvm/test/Transforms/InstCombine/bswap-fold.ll +++ b/llvm/test/Transforms/InstCombine/bswap-fold.ll @@ -498,8 +498,8 @@ define i64 @bs_and64_multiuse1(i64 %a, i64 %b) #0 { define i64 @bs_and64_multiuse2(i64 %a, i64 %b) #0 { ; CHECK-LABEL: @bs_and64_multiuse2( ; CHECK-NEXT: [[T1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[A:%.*]]) -; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A]], [[B:%.*]] -; CHECK-NEXT: [[T3:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]]) +; CHECK-NEXT: [[T2:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]]) +; CHECK-NEXT: [[T3:%.*]] = and i64 [[T1]], [[T2]] ; CHECK-NEXT: [[T4:%.*]] = mul i64 [[T3]], [[T1]] ; CHECK-NEXT: ret i64 [[T4]] ; @@ -512,9 +512,9 @@ define i64 @bs_and64_multiuse2(i64 %a, i64 %b) #0 { define i64 @bs_and64_multiuse3(i64 %a, i64 %b) #0 { ; CHECK-LABEL: @bs_and64_multiuse3( +; CHECK-NEXT: [[T1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[A:%.*]]) ; CHECK-NEXT: [[T2:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]]) -; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A:%.*]], [[B]] -; CHECK-NEXT: [[T3:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]]) +; CHECK-NEXT: [[T3:%.*]] = and i64 [[T1]], [[T2]] ; CHECK-NEXT: [[T4:%.*]] = mul i64 [[T3]], [[T2]] ; CHECK-NEXT: ret i64 [[T4]] ; -- GitLab From adfd13157dac4f512f579c14de8da6c7c0c9b698 Mon Sep 17 00:00:00 2001 From: Mark Harley Date: Wed, 10 Jan 2024 11:56:52 +0000 Subject: [PATCH 318/652] [AArch64][SVE] Add optimisation for SVE intrinsics with no active lanes (#73964) This patch introduces optimisations for SVE intrinsic function calls which have all false predicates. --- .../AArch64/AArch64TargetTransformInfo.cpp | 98 +- ...-intrinsic-comb-m-forms-no-active-lanes.ll | 1324 +++++++++++++++++ 2 files changed, 1383 insertions(+), 39 deletions(-) create mode 100644 llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-m-forms-no-active-lanes.ll diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index b5b8b6829178..13b5e578391d 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -1406,9 +1406,23 @@ static std::optional instCombineSVEAllActive(IntrinsicInst &II, return &II; } +// Simplify operations where predicate has all inactive lanes or try to replace +// with _u form when all lanes are active +static std::optional +instCombineSVEAllOrNoActive(InstCombiner &IC, IntrinsicInst &II, + Intrinsic::ID IID) { + if (match(II.getOperand(0), m_ZeroInt())) { + // llvm_ir, pred(0), op1, op2 - Spec says to return op1 when all lanes are + // inactive for sv[func]_m + return IC.replaceInstUsesWith(II, II.getOperand(1)); + } + return instCombineSVEAllActive(II, IID); +} + static std::optional instCombineSVEVectorAdd(InstCombiner &IC, IntrinsicInst &II) { - if (auto II_U = instCombineSVEAllActive(II, Intrinsic::aarch64_sve_add_u)) + if (auto II_U = + instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_add_u)) return II_U; if (auto MLA = instCombineSVEVectorFuseMulAddSub( @@ -1423,7 +1437,8 @@ static std::optional instCombineSVEVectorAdd(InstCombiner &IC, static std::optional instCombineSVEVectorFAdd(InstCombiner &IC, IntrinsicInst &II) { - if (auto II_U = instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fadd_u)) + if (auto II_U = + instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fadd_u)) return II_U; if (auto FMLA = instCombineSVEVectorFuseMulAddSub instCombineSVEVectorFSub(InstCombiner &IC, IntrinsicInst &II) { - if (auto II_U = instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fsub_u)) + if (auto II_U = + instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fsub_u)) return II_U; if (auto FMLS = instCombineSVEVectorFuseMulAddSub instCombineSVEVectorSub(InstCombiner &IC, IntrinsicInst &II) { - if (auto II_U = instCombineSVEAllActive(II, Intrinsic::aarch64_sve_sub_u)) + if (auto II_U = + instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_sub_u)) return II_U; if (auto MLS = instCombineSVEVectorFuseMulAddSub( @@ -1523,11 +1540,6 @@ static std::optional instCombineSVEVectorMul(InstCombiner &IC, auto *OpMultiplicand = II.getOperand(1); auto *OpMultiplier = II.getOperand(2); - // Canonicalise a non _u intrinsic only. - if (II.getIntrinsicID() != IID) - if (auto II_U = instCombineSVEAllActive(II, IID)) - return II_U; - // Return true if a given instruction is a unit splat value, false otherwise. auto IsUnitSplat = [](auto *I) { auto *SplatValue = getSplatValue(I); @@ -1891,34 +1903,38 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC, case Intrinsic::aarch64_sve_ptest_last: return instCombineSVEPTest(IC, II); case Intrinsic::aarch64_sve_fabd: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fabd_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fabd_u); case Intrinsic::aarch64_sve_fadd: return instCombineSVEVectorFAdd(IC, II); case Intrinsic::aarch64_sve_fadd_u: return instCombineSVEVectorFAddU(IC, II); case Intrinsic::aarch64_sve_fdiv: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fdiv_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fdiv_u); case Intrinsic::aarch64_sve_fmax: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fmax_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fmax_u); case Intrinsic::aarch64_sve_fmaxnm: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fmaxnm_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fmaxnm_u); case Intrinsic::aarch64_sve_fmin: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fmin_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fmin_u); case Intrinsic::aarch64_sve_fminnm: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fminnm_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fminnm_u); case Intrinsic::aarch64_sve_fmla: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fmla_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fmla_u); case Intrinsic::aarch64_sve_fmls: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fmls_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fmls_u); case Intrinsic::aarch64_sve_fmul: + if (auto II_U = + instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fmul_u)) + return II_U; + return instCombineSVEVectorMul(IC, II, Intrinsic::aarch64_sve_fmul_u); case Intrinsic::aarch64_sve_fmul_u: return instCombineSVEVectorMul(IC, II, Intrinsic::aarch64_sve_fmul_u); case Intrinsic::aarch64_sve_fmulx: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fmulx_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fmulx_u); case Intrinsic::aarch64_sve_fnmla: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fnmla_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fnmla_u); case Intrinsic::aarch64_sve_fnmls: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_fnmls_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_fnmls_u); case Intrinsic::aarch64_sve_fsub: return instCombineSVEVectorFSub(IC, II); case Intrinsic::aarch64_sve_fsub_u: @@ -1930,20 +1946,24 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC, Intrinsic::aarch64_sve_mla_u>( IC, II, true); case Intrinsic::aarch64_sve_mla: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_mla_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_mla_u); case Intrinsic::aarch64_sve_mls: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_mls_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_mls_u); case Intrinsic::aarch64_sve_mul: + if (auto II_U = + instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_mul_u)) + return II_U; + return instCombineSVEVectorMul(IC, II, Intrinsic::aarch64_sve_mul_u); case Intrinsic::aarch64_sve_mul_u: return instCombineSVEVectorMul(IC, II, Intrinsic::aarch64_sve_mul_u); case Intrinsic::aarch64_sve_sabd: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_sabd_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_sabd_u); case Intrinsic::aarch64_sve_smax: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_smax_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_smax_u); case Intrinsic::aarch64_sve_smin: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_smin_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_smin_u); case Intrinsic::aarch64_sve_smulh: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_smulh_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_smulh_u); case Intrinsic::aarch64_sve_sub: return instCombineSVEVectorSub(IC, II); case Intrinsic::aarch64_sve_sub_u: @@ -1951,31 +1971,31 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC, Intrinsic::aarch64_sve_mls_u>( IC, II, true); case Intrinsic::aarch64_sve_uabd: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_uabd_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_uabd_u); case Intrinsic::aarch64_sve_umax: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_umax_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_umax_u); case Intrinsic::aarch64_sve_umin: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_umin_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_umin_u); case Intrinsic::aarch64_sve_umulh: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_umulh_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_umulh_u); case Intrinsic::aarch64_sve_asr: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_asr_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_asr_u); case Intrinsic::aarch64_sve_lsl: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_lsl_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_lsl_u); case Intrinsic::aarch64_sve_lsr: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_lsr_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_lsr_u); case Intrinsic::aarch64_sve_and: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_and_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_and_u); case Intrinsic::aarch64_sve_bic: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_bic_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_bic_u); case Intrinsic::aarch64_sve_eor: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_eor_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_eor_u); case Intrinsic::aarch64_sve_orr: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_orr_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_orr_u); case Intrinsic::aarch64_sve_sqsub: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_sqsub_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_sqsub_u); case Intrinsic::aarch64_sve_uqsub: - return instCombineSVEAllActive(II, Intrinsic::aarch64_sve_uqsub_u); + return instCombineSVEAllOrNoActive(IC, II, Intrinsic::aarch64_sve_uqsub_u); case Intrinsic::aarch64_sve_tbl: return instCombineSVETBL(IC, II); case Intrinsic::aarch64_sve_uunpkhi: diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-m-forms-no-active-lanes.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-m-forms-no-active-lanes.ll new file mode 100644 index 000000000000..463a5f5d2cfb --- /dev/null +++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-m-forms-no-active-lanes.ll @@ -0,0 +1,1324 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt -S -passes=instcombine < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; Replace SVE _m intrinsics with their first operand when the predicate is all false. + +; Float arithmetic + +declare @llvm.aarch64.sve.fabd.nxv8f16(, , ) +define @replace_fabd_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fabd_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fabd.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fabd.nxv4f32(, , ) +define @replace_fabd_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fabd_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fabd.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fabd.nxv2f64(, , ) +define @replace_fabd_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fabd_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fabd.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +; aarch64_sve_fadd intrinsic combines to a LLVM instruction fadd. + +declare @llvm.aarch64.sve.fadd.nxv8f16(, , ) +define @replace_fadd_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fadd_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fadd.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fadd.nxv4f32(, , ) +define @replace_fadd_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fadd_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fadd.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fadd.nxv2f64(, , ) +define @replace_fadd_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fadd_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fadd.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fdiv.nxv8f16(, , ) +define @replace_fdiv_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fdiv_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fdiv.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fdiv.nxv4f32(, , ) +define @replace_fdiv_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fdiv_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fdiv.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fdiv.nxv2f64(, , ) +define @replace_fdiv_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fdiv_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fdiv.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmax.nxv8f16(, , ) +define @replace_fmax_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmax_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmax.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmax.nxv4f32(, , ) +define @replace_fmax_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmax_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmax.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmax.nxv2f64(, , ) +define @replace_fmax_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmax_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmax.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmaxnm.nxv8f16(, , ) +define @replace_fmaxnm_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmaxnm_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmaxnm.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmaxnm.nxv4f32(, , ) +define @replace_fmaxnm_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmaxnm_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmaxnm.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmaxnm.nxv2f64(, , ) +define @replace_fmaxnm_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmaxnm_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmaxnm.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmin.nxv8f16(, , ) +define @replace_fmin_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmin_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmin.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmin.nxv4f32(, , ) +define @replace_fmin_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmin_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmin.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmin.nxv2f64(, , ) +define @replace_fmin_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmin_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmin.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fminnm.nxv8f16(, , ) +define @replace_fminnm_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fminnm_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fminnm.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fminnm.nxv4f32(, , ) +define @replace_fminnm_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fminnm_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fminnm.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fminnm.nxv2f64(, , ) +define @replace_fminnm_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fminnm_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fminnm.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmla.nxv8f16(, , , ) +define @replace_fmla_intrinsic_half( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fmla_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmla.nxv8f16( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fmla.nxv4f32(, , , ) +define @replace_fmla_intrinsic_float( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fmla_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmla.nxv4f32( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fmla.nxv2f64(, , , ) +define @replace_fmla_intrinsic_double( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fmla_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmla.nxv2f64( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fmls.nxv8f16(, , , ) +define @replace_fmls_intrinsic_half( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fmls_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmls.nxv8f16( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fmls.nxv4f32(, , , ) +define @replace_fmls_intrinsic_float( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fmls_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmls.nxv4f32( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fmls.nxv2f64(, , , ) +define @replace_fmls_intrinsic_double( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fmls_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmls.nxv2f64( zeroinitializer, %a, %b, %c) + ret %1 +} + +; aarch64_sve_fmul intrinsic combines to a LLVM instruction fmul. + +declare @llvm.aarch64.sve.fmul.nxv8f16(, , ) +define @replace_fmul_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmul_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmul.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmul.nxv4f32(, , ) +define @replace_fmul_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmul_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmul.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmul.nxv2f64(, , ) +define @replace_fmul_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmul_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmul.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmulx.nxv8f16(, , ) +define @replace_fmulx_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmulx_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmulx.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmulx.nxv4f32(, , ) +define @replace_fmulx_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmulx_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmulx.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fmulx.nxv2f64(, , ) +define @replace_fmulx_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fmulx_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fmulx.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fnmla.nxv8f16(, , , ) +define @replace_fnmla_intrinsic_half( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fnmla_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fnmla.nxv8f16( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fnmla.nxv4f32(, , , ) +define @replace_fnmla_intrinsic_float( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fnmla_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fnmla.nxv4f32( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fnmla.nxv2f64(, , , ) +define @replace_fnmla_intrinsic_double( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fnmla_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fnmla.nxv2f64( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fnmls.nxv8f16(, , , ) +define @replace_fnmls_intrinsic_half( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fnmls_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fnmls.nxv8f16( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fnmls.nxv4f32(, , , ) +define @replace_fnmls_intrinsic_float( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fnmls_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fnmls.nxv4f32( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.fnmls.nxv2f64(, , , ) +define @replace_fnmls_intrinsic_double( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_fnmls_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fnmls.nxv2f64( zeroinitializer, %a, %b, %c) + ret %1 +} + +; aarch64_sve_fsub intrinsic combines to a LLVM instruction fsub. + +declare @llvm.aarch64.sve.fsub.nxv8f16(, , ) +define @replace_fsub_intrinsic_half( %a, %b) #0 { +; CHECK-LABEL: define @replace_fsub_intrinsic_half +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fsub.nxv8f16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fsub.nxv4f32(, , ) +define @replace_fsub_intrinsic_float( %a, %b) #0 { +; CHECK-LABEL: define @replace_fsub_intrinsic_float +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fsub.nxv4f32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.fsub.nxv2f64(, , ) +define @replace_fsub_intrinsic_double( %a, %b) #0 { +; CHECK-LABEL: define @replace_fsub_intrinsic_double +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call fast @llvm.aarch64.sve.fsub.nxv2f64( zeroinitializer, %a, %b) + ret %1 +} + +; Integer arithmetic + +declare @llvm.aarch64.sve.add.nxv16i8(, , ) +define @replace_add_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_add_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.add.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.add.nxv8i16(, , ) +define @replace_add_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_add_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.add.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.add.nxv4i32(, , ) +define @replace_add_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_add_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.add.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.add.nxv2i64(, , ) +define @replace_add_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_add_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.add.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.mla.nxv16i8(, , , ) +define @replace_mla_intrinsic_i8( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mla_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mla.nxv16i8( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mla.nxv8i16(, , , ) +define @replace_mla_intrinsic_i16( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mla_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mla.nxv8i16( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mla.nxv4i32(, , , ) +define @replace_mla_intrinsic_i32( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mla_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mla.nxv4i32( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mla.nxv2i64(, , , ) +define @replace_mla_intrinsic_i64( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mla_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mla.nxv2i64( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mls.nxv16i8(, , , ) +define @replace_mls_intrinsic_i8( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mls_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mls.nxv16i8( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mls.nxv8i16(, , , ) +define @replace_mls_intrinsic_i16( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mls_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mls.nxv8i16( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mls.nxv4i32(, , , ) +define @replace_mls_intrinsic_i32( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mls_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mls.nxv4i32( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mls.nxv2i64(, , , ) +define @replace_mls_intrinsic_i64( %a, %b, %c) #0 { +; CHECK-LABEL: define @replace_mls_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]], [[C:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mls.nxv2i64( zeroinitializer, %a, %b, %c) + ret %1 +} + +declare @llvm.aarch64.sve.mul.nxv16i8(, , ) +define @replace_mul_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_mul_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mul.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.mul.nxv8i16(, , ) +define @replace_mul_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_mul_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mul.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.mul.nxv4i32(, , ) +define @replace_mul_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_mul_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mul.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.mul.nxv2i64(, , ) +define @replace_mul_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_mul_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.mul.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sabd.nxv16i8(, , ) +define @replace_sabd_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_sabd_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sabd.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sabd.nxv8i16(, , ) +define @replace_sabd_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_sabd_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sabd.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sabd.nxv4i32(, , ) +define @replace_sabd_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_sabd_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sabd.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sabd.nxv2i64(, , ) +define @replace_sabd_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_sabd_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sabd.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smax.nxv16i8(, , ) +define @replace_smax_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_smax_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smax.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smax.nxv8i16(, , ) +define @replace_smax_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_smax_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smax.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smax.nxv4i32(, , ) +define @replace_smax_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_smax_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smax.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smax.nxv2i64(, , ) +define @replace_smax_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_smax_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smax.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smin.nxv16i8(, , ) +define @replace_smin_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_smin_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smin.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smin.nxv8i16(, , ) +define @replace_smin_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_smin_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smin.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smin.nxv4i32(, , ) +define @replace_smin_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_smin_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smin.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smin.nxv2i64(, , ) +define @replace_smin_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_smin_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smin.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smulh.nxv16i8(, , ) +define @replace_smulh_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_smulh_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smulh.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smulh.nxv8i16(, , ) +define @replace_smulh_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_smulh_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smulh.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smulh.nxv4i32(, , ) +define @replace_smulh_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_smulh_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smulh.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.smulh.nxv2i64(, , ) +define @replace_smulh_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_smulh_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.smulh.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sub.nxv16i8(, , ) +define @replace_sub_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_sub_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sub.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sub.nxv8i16(, , ) +define @replace_sub_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_sub_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sub.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sub.nxv4i32(, , ) +define @replace_sub_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_sub_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sub.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sub.nxv2i64(, , ) +define @replace_sub_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_sub_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sub.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uabd.nxv16i8(, , ) +define @replace_uabd_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_uabd_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uabd.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uabd.nxv8i16(, , ) +define @replace_uabd_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_uabd_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uabd.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uabd.nxv4i32(, , ) +define @replace_uabd_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_uabd_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uabd.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uabd.nxv2i64(, , ) +define @replace_uabd_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_uabd_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uabd.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umax.nxv16i8(, , ) +define @replace_umax_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_umax_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umax.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umax.nxv8i16(, , ) +define @replace_umax_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_umax_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umax.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umax.nxv4i32(, , ) +define @replace_umax_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_umax_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umax.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umax.nxv2i64(, , ) +define @replace_umax_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_umax_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umax.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umin.nxv16i8(, , ) +define @replace_umin_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_umin_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umin.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umin.nxv8i16(, , ) +define @replace_umin_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_umin_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umin.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umin.nxv4i32(, , ) +define @replace_umin_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_umin_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umin.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umin.nxv2i64(, , ) +define @replace_umin_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_umin_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umin.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umulh.nxv16i8(, , ) +define @replace_umulh_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_umulh_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umulh.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umulh.nxv8i16(, , ) +define @replace_umulh_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_umulh_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umulh.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umulh.nxv4i32(, , ) +define @replace_umulh_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_umulh_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umulh.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.umulh.nxv2i64(, , ) +define @replace_umulh_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_umulh_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.umulh.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +; Shifts + +declare @llvm.aarch64.sve.asr.nxv16i8(, , ) +define @replace_asr_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_asr_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.asr.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.asr.nxv8i16(, , ) +define @replace_asr_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_asr_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.asr.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.asr.nxv4i32(, , ) +define @replace_asr_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_asr_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.asr.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.asr.nxv2i64(, , ) +define @replace_asr_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_asr_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.asr.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsl.nxv16i8(, , ) +define @replace_lsl_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsl_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsl.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsl.nxv8i16(, , ) +define @replace_lsl_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsl_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsl.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsl.nxv4i32(, , ) +define @replace_lsl_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsl_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsl.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsl.nxv2i64(, , ) +define @replace_lsl_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsl_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsl.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsr.nxv16i8(, , ) +define @replace_lsr_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsr_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsr.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsr.nxv8i16(, , ) +define @replace_lsr_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsr_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsr.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsr.nxv4i32(, , ) +define @replace_lsr_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsr_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsr.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.lsr.nxv2i64(, , ) +define @replace_lsr_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_lsr_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.lsr.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +; Logical operations + +declare @llvm.aarch64.sve.and.nxv16i8(, , ) +define @replace_and_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_and_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.and.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.and.nxv8i16(, , ) +define @replace_and_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_and_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.and.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.and.nxv4i32(, , ) +define @replace_and_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_and_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.and.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.and.nxv2i64(, , ) +define @replace_and_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_and_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.and.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.bic.nxv16i8(, , ) +define @replace_bic_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_bic_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.bic.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.bic.nxv8i16(, , ) +define @replace_bic_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_bic_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.bic.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.bic.nxv4i32(, , ) +define @replace_bic_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_bic_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.bic.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.bic.nxv2i64(, , ) +define @replace_bic_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_bic_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.bic.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.eor.nxv16i8(, , ) +define @replace_eor_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_eor_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.eor.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.eor.nxv8i16(, , ) +define @replace_eor_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_eor_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.eor.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.eor.nxv4i32(, , ) +define @replace_eor_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_eor_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.eor.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.eor.nxv2i64(, , ) +define @replace_eor_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_eor_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.eor.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.orr.nxv16i8(, , ) +define @replace_orr_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_orr_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.orr.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.orr.nxv8i16(, , ) +define @replace_orr_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_orr_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.orr.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.orr.nxv4i32(, , ) +define @replace_orr_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_orr_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.orr.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.orr.nxv2i64(, , ) +define @replace_orr_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_orr_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.orr.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +; SVE2 - Uniform DSP operations + +declare @llvm.aarch64.sve.sqsub.nxv16i8(, , ) +define @replace_sqsub_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_sqsub_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sqsub.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sqsub.nxv8i16(, , ) +define @replace_sqsub_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_sqsub_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sqsub.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sqsub.nxv4i32(, , ) +define @replace_sqsub_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_sqsub_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sqsub.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.sqsub.nxv2i64(, , ) +define @replace_sqsub_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_sqsub_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.sqsub.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uqsub.nxv16i8(, , ) +define @replace_uqsub_intrinsic_i8( %a, %b) #0 { +; CHECK-LABEL: define @replace_uqsub_intrinsic_i8 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uqsub.nxv16i8( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uqsub.nxv8i16(, , ) +define @replace_uqsub_intrinsic_i16( %a, %b) #0 { +; CHECK-LABEL: define @replace_uqsub_intrinsic_i16 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uqsub.nxv8i16( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uqsub.nxv4i32(, , ) +define @replace_uqsub_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_uqsub_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uqsub.nxv4i32( zeroinitializer, %a, %b) + ret %1 +} + +declare @llvm.aarch64.sve.uqsub.nxv2i64(, , ) +define @replace_uqsub_intrinsic_i64( %a, %b) #0 { +; CHECK-LABEL: define @replace_uqsub_intrinsic_i64 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: ret [[A]] +; + %1 = tail call @llvm.aarch64.sve.uqsub.nxv2i64( zeroinitializer, %a, %b) + ret %1 +} + +attributes #0 = { "target-features"="+sve,+sve2" } -- GitLab From 78cf2c041b778c82cc01b8606ec3e68840b769af Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 10 Jan 2024 12:09:38 +0000 Subject: [PATCH 319/652] [X86] pr77459.ll - add missing AVX512 check prefixes Missed these in 3210ce276350a247220b193db12a9b45d1034724 for the #77459 fix --- llvm/test/CodeGen/X86/pr77459.ll | 48 ++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/X86/pr77459.ll b/llvm/test/CodeGen/X86/pr77459.ll index c6736f4d3398..cf073e97137e 100644 --- a/llvm/test/CodeGen/X86/pr77459.ll +++ b/llvm/test/CodeGen/X86/pr77459.ll @@ -2,8 +2,8 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE,SSE2 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE,SSE42 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX2 -; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512 -; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 -mattr=+avx512vbmi | FileCheck %s --check-prefixes=AVX512 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512,AVX512-V4 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 -mattr=+avx512vbmi | FileCheck %s --check-prefixes=AVX512,AVX512-VBMI define i4 @reverse_cmp_v4i1(<4 x i32> %a0, <4 x i32> %a1) { ; SSE2-LABEL: reverse_cmp_v4i1: @@ -221,6 +221,28 @@ define i32 @reverse_cmp_v32i1(<32 x i8> %a0, <32 x i8> %a1) { ; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq +; +; AVX512-V4-LABEL: reverse_cmp_v32i1: +; AVX512-V4: # %bb.0: +; AVX512-V4-NEXT: vpcmpeqb %ymm1, %ymm0, %k0 +; AVX512-V4-NEXT: vpmovm2b %k0, %ymm0 +; AVX512-V4-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16] +; AVX512-V4-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,0,1] +; AVX512-V4-NEXT: vpmovb2m %ymm0, %k0 +; AVX512-V4-NEXT: kmovd %k0, %eax +; AVX512-V4-NEXT: vzeroupper +; AVX512-V4-NEXT: retq +; +; AVX512-VBMI-LABEL: reverse_cmp_v32i1: +; AVX512-VBMI: # %bb.0: +; AVX512-VBMI-NEXT: vpcmpeqb %ymm1, %ymm0, %k0 +; AVX512-VBMI-NEXT: vpmovm2b %k0, %ymm0 +; AVX512-VBMI-NEXT: vmovdqa {{.*#+}} ymm1 = [31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] +; AVX512-VBMI-NEXT: vpermb %ymm0, %ymm1, %ymm0 +; AVX512-VBMI-NEXT: vpmovb2m %ymm0, %k0 +; AVX512-VBMI-NEXT: kmovd %k0, %eax +; AVX512-VBMI-NEXT: vzeroupper +; AVX512-VBMI-NEXT: retq %cmp = icmp eq <32 x i8> %a0, %a1 %mask = bitcast <32 x i1> %cmp to i32 %rev = tail call i32 @llvm.bitreverse.i32(i32 %mask) @@ -306,6 +328,28 @@ define i64 @reverse_cmp_v64i1(<64 x i8> %a0, <64 x i8> %a1) { ; AVX2-NEXT: orq %rcx, %rax ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq +; +; AVX512-V4-LABEL: reverse_cmp_v64i1: +; AVX512-V4: # %bb.0: +; AVX512-V4-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 +; AVX512-V4-NEXT: vpmovm2b %k0, %zmm0 +; AVX512-V4-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48] +; AVX512-V4-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[6,7,4,5,2,3,0,1] +; AVX512-V4-NEXT: vpmovb2m %zmm0, %k0 +; AVX512-V4-NEXT: kmovq %k0, %rax +; AVX512-V4-NEXT: vzeroupper +; AVX512-V4-NEXT: retq +; +; AVX512-VBMI-LABEL: reverse_cmp_v64i1: +; AVX512-VBMI: # %bb.0: +; AVX512-VBMI-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 +; AVX512-VBMI-NEXT: vpmovm2b %k0, %zmm0 +; AVX512-VBMI-NEXT: vmovdqa64 {{.*#+}} zmm1 = [63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] +; AVX512-VBMI-NEXT: vpermb %zmm0, %zmm1, %zmm0 +; AVX512-VBMI-NEXT: vpmovb2m %zmm0, %k0 +; AVX512-VBMI-NEXT: kmovq %k0, %rax +; AVX512-VBMI-NEXT: vzeroupper +; AVX512-VBMI-NEXT: retq %cmp = icmp eq <64 x i8> %a0, %a1 %mask = bitcast <64 x i1> %cmp to i64 %rev = tail call i64 @llvm.bitreverse.i64(i64 %mask) -- GitLab From 5b4abae7630572c96a736faa1f09b1a3c37201a2 Mon Sep 17 00:00:00 2001 From: darkfeline Date: Wed, 10 Jan 2024 04:14:21 -0800 Subject: [PATCH 320/652] [emacs] Fix Emacs library formatting (#76110) This makes it easier to ship/install these using the builtin Emacs package format (in particular, a Version is required). --- .../clang-include-fixer/tool/clang-include-fixer.el | 1 + clang/tools/clang-format/clang-format.el | 1 + clang/tools/clang-rename/clang-rename.el | 1 + llvm/utils/emacs/tablegen-mode.el | 1 + mlir/utils/emacs/mlir-lsp-client.el | 2 ++ mlir/utils/emacs/mlir-mode.el | 3 ++- 6 files changed, 8 insertions(+), 1 deletion(-) diff --git a/clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.el b/clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.el index 272f282c47f5..f3a949f8c1b5 100644 --- a/clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.el +++ b/clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.el @@ -1,5 +1,6 @@ ;;; clang-include-fixer.el --- Emacs integration of the clang include fixer -*- lexical-binding: t; -*- +;; Version: 0.1.0 ;; Keywords: tools, c ;; Package-Requires: ((cl-lib "0.5") (json "1.2") (let-alist "1.0.4")) diff --git a/clang/tools/clang-format/clang-format.el b/clang/tools/clang-format/clang-format.el index 30ac7501afcb..f43bf063c629 100644 --- a/clang/tools/clang-format/clang-format.el +++ b/clang/tools/clang-format/clang-format.el @@ -1,5 +1,6 @@ ;;; clang-format.el --- Format code using clang-format -*- lexical-binding: t; -*- +;; Version: 0.1.0 ;; Keywords: tools, c ;; Package-Requires: ((cl-lib "0.3")) ;; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception diff --git a/clang/tools/clang-rename/clang-rename.el b/clang/tools/clang-rename/clang-rename.el index b6c3ed4c686b..3f47c11e2c75 100644 --- a/clang/tools/clang-rename/clang-rename.el +++ b/clang/tools/clang-rename/clang-rename.el @@ -1,5 +1,6 @@ ;;; clang-rename.el --- Renames every occurrence of a symbol found at . -*- lexical-binding: t; -*- +;; Version: 0.1.0 ;; Keywords: tools, c ;;; Commentary: diff --git a/llvm/utils/emacs/tablegen-mode.el b/llvm/utils/emacs/tablegen-mode.el index 330da4658870..b1cc1cb36c06 100644 --- a/llvm/utils/emacs/tablegen-mode.el +++ b/llvm/utils/emacs/tablegen-mode.el @@ -1,6 +1,7 @@ ;;; tablegen-mode.el --- Major mode for TableGen description files (part of LLVM project) ;; Maintainer: The LLVM team, http://llvm.org/ +;; Version: 1.0 ;;; Commentary: ;; A major mode for TableGen description files in LLVM. diff --git a/mlir/utils/emacs/mlir-lsp-client.el b/mlir/utils/emacs/mlir-lsp-client.el index 09dfa835decc..4397a55e7206 100644 --- a/mlir/utils/emacs/mlir-lsp-client.el +++ b/mlir/utils/emacs/mlir-lsp-client.el @@ -14,6 +14,8 @@ ;; See the License for the specific language governing permissions and ;; limitations under the License. +;; Version: 0.1.0 + ;;; Commentary: ;; LSP clinet to use with `mlir-mode' that uses `mlir-lsp-server' or any diff --git a/mlir/utils/emacs/mlir-mode.el b/mlir/utils/emacs/mlir-mode.el index 69056ba3620e..e5947df03f86 100644 --- a/mlir/utils/emacs/mlir-mode.el +++ b/mlir/utils/emacs/mlir-mode.el @@ -14,6 +14,8 @@ ;; See the License for the specific language governing permissions and ;; limitations under the License. +;; Version: 0.1.0 + ;;; Commentary: ;; Major mode for editing MLIR files. @@ -96,5 +98,4 @@ (add-to-list 'auto-mode-alist (cons "\\.mlirbc\\'" 'mlir-mode)) (provide 'mlir-mode) - ;;; mlir-mode.el ends here -- GitLab From 205aa3fb89769c703c14ff448cb7bff73438488f Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Wed, 10 Jan 2024 09:15:33 -0300 Subject: [PATCH 321/652] [flang] Document DEFAULT_SYSROOT usage on Darwin (#77353) --- flang/docs/GettingStarted.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/flang/docs/GettingStarted.md b/flang/docs/GettingStarted.md index 9656f5151acd..ada685426488 100644 --- a/flang/docs/GettingStarted.md +++ b/flang/docs/GettingStarted.md @@ -88,6 +88,10 @@ cmake \ ninja ``` +On Darwin, to make flang able to link binaries with the default sysroot without +having to specify additional flags, use the `DEFAULT_SYSROOT` cmake flag, e.g. +`-DDEFAULT_SYSROOT="$(xcrun --show-sdk-path)"`. + By default flang tests that do not specify an explicit `--target` flag use LLVM's default target triple. For these tests, if there is a need to test on a different triple by overriding the default, the following needs to be added to -- GitLab From 1220c9bafc11a3edf96921a8ab892d777b7ed06b Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 10 Jan 2024 20:24:20 +0800 Subject: [PATCH 322/652] [InstCombine] Fold the `log2_ceil` idiom (#76661) This patch folds the `log2_ceil` idiom: ``` (BW - ctlz(A)) + (is_power2(A) ? 0 : 1) -> zext(ctpop(A) >u/!= 1) + (ctlz(A, true) ^ (BW - 1)) (canonical form) -> BW - ctlz(A - 1, false) ``` Alive2: https://alive2.llvm.org/ce/z/6mSbdi --- .../InstCombine/InstCombineAddSub.cpp | 24 ++ .../InstCombine/fold-log2-ceil-idiom.ll | 337 ++++++++++++++++++ 2 files changed, 361 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 96b612254ca5..c7e6f32c5406 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1723,6 +1723,30 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) { I, Builder.CreateIntrinsic(Intrinsic::ctpop, {I.getType()}, {Builder.CreateOr(A, B)})); + // Fold the log2_ceil idiom: + // zext(ctpop(A) >u/!= 1) + (ctlz(A, true) ^ (BW - 1)) + // --> + // BW - ctlz(A - 1, false) + const APInt *XorC; + if (match(&I, + m_c_Add( + m_ZExt(m_ICmp(Pred, m_Intrinsic(m_Value(A)), + m_One())), + m_OneUse(m_ZExtOrSelf(m_OneUse(m_Xor( + m_OneUse(m_TruncOrSelf(m_OneUse( + m_Intrinsic(m_Deferred(A), m_One())))), + m_APInt(XorC))))))) && + (Pred == ICmpInst::ICMP_UGT || Pred == ICmpInst::ICMP_NE) && + *XorC == A->getType()->getScalarSizeInBits() - 1) { + Value *Sub = Builder.CreateAdd(A, Constant::getAllOnesValue(A->getType())); + Value *Ctlz = Builder.CreateIntrinsic(Intrinsic::ctlz, {A->getType()}, + {Sub, Builder.getFalse()}); + Value *Ret = Builder.CreateSub( + ConstantInt::get(A->getType(), A->getType()->getScalarSizeInBits()), + Ctlz, "", /*HasNUW*/ true, /*HasNSW*/ true); + return replaceInstUsesWith(I, Builder.CreateZExtOrTrunc(Ret, I.getType())); + } + if (Instruction *Res = foldSquareSumInt(I)) return Res; diff --git a/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll b/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll new file mode 100644 index 000000000000..2594c3fce814 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll @@ -0,0 +1,337 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=instcombine -S | FileCheck %s + +define i32 @log2_ceil_idiom(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i5 @log2_ceil_idiom_trunc(i32 %x) { +; CHECK-LABEL: define i5 @log2_ceil_idiom_trunc( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP3:%.*]] = sub nsw i32 0, [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = trunc i32 [[TMP3]] to i5 +; CHECK-NEXT: ret i5 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %trunc = trunc i32 %ctlz to i5 + %xor = xor i5 %trunc, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i5 + %ret = add i5 %xor, %zext + ret i5 %ret +} + +define i64 @log2_ceil_idiom_zext(i32 %x) { +; CHECK-LABEL: define i64 @log2_ceil_idiom_zext( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 32, [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = zext i32 [[TMP3]] to i64 +; CHECK-NEXT: ret i64 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ext = zext nneg i32 %xor to i64 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i64 + %ret = add i64 %ext, %zext + ret i64 %ret +} + +define i32 @log2_ceil_idiom_power2_test2(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_power2_test2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ne i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i32 @log2_ceil_idiom_commuted(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_commuted( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %zext, %xor + ret i32 %ret +} + +define i32 @log2_ceil_idiom_multiuse1(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_multiuse1( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: call void @use32(i32 [[CTPOP]]) +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + call void @use32(i32 %ctpop) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +; Negative tests + +define i32 @log2_ceil_idiom_x_may_be_zero(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_x_may_be_zero( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i4 @log2_ceil_idiom_trunc_too_short(i32 %x) { +; CHECK-LABEL: define i4 @log2_ceil_idiom_trunc_too_short( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[CTLZ]] to i4 +; CHECK-NEXT: [[XOR:%.*]] = xor i4 [[TRUNC]], -1 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i4 +; CHECK-NEXT: [[RET:%.*]] = add i4 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i4 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %trunc = trunc i32 %ctlz to i4 + %xor = xor i4 %trunc, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i4 + %ret = add i4 %xor, %zext + ret i4 %ret +} + +define i32 @log2_ceil_idiom_mismatched_operands(i32 %x, i32 %y) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_mismatched_operands( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[Y]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %y) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i32 @log2_ceil_idiom_wrong_constant(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_wrong_constant( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 30 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 30 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i32 @log2_ceil_idiom_not_a_power2_test1(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_not_a_power2_test1( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp eq i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i32 @log2_ceil_idiom_not_a_power2_test2(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_not_a_power2_test2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 2 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 2 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i32 @log2_ceil_idiom_multiuse2(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_multiuse2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: call void @use32(i32 [[CTLZ]]) +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + call void @use32(i32 %ctlz) + %xor = xor i32 %ctlz, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i32 @log2_ceil_idiom_multiuse3(i32 %x) { +; CHECK-LABEL: define i32 @log2_ceil_idiom_multiuse3( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 +; CHECK-NEXT: call void @use32(i32 [[XOR]]) +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i32 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + call void @use32(i32 %xor) + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i32 + %ret = add i32 %xor, %zext + ret i32 %ret +} + +define i5 @log2_ceil_idiom_trunc_multiuse4(i32 %x) { +; CHECK-LABEL: define i5 @log2_ceil_idiom_trunc_multiuse4( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[CTLZ]] to i5 +; CHECK-NEXT: call void @use5(i5 [[TRUNC]]) +; CHECK-NEXT: [[XOR:%.*]] = xor i5 [[TRUNC]], -1 +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i5 +; CHECK-NEXT: [[RET:%.*]] = add i5 [[XOR]], [[ZEXT]] +; CHECK-NEXT: ret i5 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %trunc = trunc i32 %ctlz to i5 + call void @use5(i5 %trunc) + %xor = xor i5 %trunc, 31 + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i5 + %ret = add i5 %xor, %zext + ret i5 %ret +} + +define i64 @log2_ceil_idiom_zext_multiuse5(i32 %x) { +; CHECK-LABEL: define i64 @log2_ceil_idiom_zext_multiuse5( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 +; CHECK-NEXT: [[EXT:%.*]] = zext nneg i32 [[XOR]] to i64 +; CHECK-NEXT: call void @use64(i64 [[EXT]]) +; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i64 +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i64 [[EXT]], [[ZEXT]] +; CHECK-NEXT: ret i64 [[RET]] +; + %ctlz = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %xor = xor i32 %ctlz, 31 + %ext = zext nneg i32 %xor to i64 + call void @use64(i64 %ext) + %ctpop = tail call i32 @llvm.ctpop.i32(i32 %x) + %cmp = icmp ugt i32 %ctpop, 1 + %zext = zext i1 %cmp to i64 + %ret = add i64 %ext, %zext + ret i64 %ret +} + +declare void @use5(i5) +declare void @use32(i32) +declare void @use64(i64) + +declare i32 @llvm.ctlz.i32(i32, i1) +declare i32 @llvm.ctpop.i32(i32) +;. +; CHECK: [[RNG0]] = !{i32 0, i32 33} +;. -- GitLab From c933bd818594c872435d6f1d2cc5ad18715a8986 Mon Sep 17 00:00:00 2001 From: Thomas Raoux Date: Wed, 10 Jan 2024 04:25:57 -0800 Subject: [PATCH 323/652] [MLIR][SCF] Add checks to verify that the pipeliner schedule is correct. (#77083) Add a check to validate that the schedule passed to the pipeliner transformation is valid and won't cause the pipeliner to break SSA. This checks that the for each operation in the loop operations are scheduled after their operands. --- .../Dialect/SCF/Transforms/LoopPipelining.cpp | 43 +++++++++++++++++++ mlir/test/Dialect/SCF/loop-pipelining.mlir | 34 ++++++++++++++- 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp b/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp index 7d45b484f765..9eda1a4597ba 100644 --- a/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp +++ b/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp @@ -67,6 +67,10 @@ protected: /// the Value. std::pair getDefiningOpAndDistance(Value value); + /// Return true if the schedule is possible and return false otherwise. A + /// schedule is correct if all definitions are scheduled before uses. + bool verifySchedule(); + public: /// Initalize the information for the given `op`, return true if it /// satisfies the pre-condition to apply pipelining. @@ -156,6 +160,11 @@ bool LoopPipelinerInternal::initializeLoopInfo( } } + if (!verifySchedule()) { + LDBG("--invalid schedule: " << op << " -> BAIL"); + return false; + } + // Currently, we do not support assigning stages to ops in nested regions. The // block of all operations assigned a stage should be the single `scf.for` // body block. @@ -194,6 +203,40 @@ bool LoopPipelinerInternal::initializeLoopInfo( return true; } +/// Compute unrolled cycles of each op (consumer) and verify that each op is +/// scheduled after its operands (producers) while adjusting for the distance +/// between producer and consumer. +bool LoopPipelinerInternal::verifySchedule() { + int64_t numCylesPerIter = opOrder.size(); + // Pre-compute the unrolled cycle of each op. + DenseMap unrolledCyles; + for (int64_t cycle = 0; cycle < numCylesPerIter; cycle++) { + Operation *def = opOrder[cycle]; + auto it = stages.find(def); + assert(it != stages.end()); + int64_t stage = it->second; + unrolledCyles[def] = cycle + stage * numCylesPerIter; + } + for (Operation *consumer : opOrder) { + int64_t consumerCycle = unrolledCyles[consumer]; + for (Value operand : consumer->getOperands()) { + auto [producer, distance] = getDefiningOpAndDistance(operand); + if (!producer) + continue; + auto it = unrolledCyles.find(producer); + // Skip producer coming from outside the loop. + if (it == unrolledCyles.end()) + continue; + int64_t producerCycle = it->second; + if (consumerCycle < producerCycle - numCylesPerIter * distance) { + consumer->emitError("operation scheduled before its operands"); + return false; + } + } + } + return true; +} + /// Clone `op` and call `callback` on the cloned op's oeprands as well as any /// operands of nested ops that: /// 1) aren't defined within the new op or diff --git a/mlir/test/Dialect/SCF/loop-pipelining.mlir b/mlir/test/Dialect/SCF/loop-pipelining.mlir index 33290d2db31d..8d6f454d1875 100644 --- a/mlir/test/Dialect/SCF/loop-pipelining.mlir +++ b/mlir/test/Dialect/SCF/loop-pipelining.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt %s -test-scf-pipelining -split-input-file | FileCheck %s +// RUN: mlir-opt %s -test-scf-pipelining -split-input-file -verify-diagnostics | FileCheck %s // RUN: mlir-opt %s -test-scf-pipelining=annotate -split-input-file | FileCheck %s --check-prefix ANNOTATE // RUN: mlir-opt %s -test-scf-pipelining=no-epilogue-peeling -split-input-file | FileCheck %s --check-prefix NOEPILOGUE @@ -814,3 +814,35 @@ func.func @yield_constant_loop(%A: memref) -> f32 { return %r : f32 } +// ----- + +func.func @invalid_schedule(%A: memref, %result: memref) { + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %cf = arith.constant 1.0 : f32 + scf.for %i0 = %c0 to %c4 step %c1 { + %A_elem = memref.load %A[%i0] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 2 } : memref + %A1_elem = arith.addf %A_elem, %cf { __test_pipelining_stage__ = 2, __test_pipelining_op_order__ = 0 } : f32 + // expected-error@+1 {{operation scheduled before its operands}} + memref.store %A1_elem, %result[%i0] { __test_pipelining_stage__ = 1, __test_pipelining_op_order__ = 1 } : memref + } { __test_pipelining_loop__ } + return +} + +// ----- + +func.func @invalid_schedule2(%A: memref, %result: memref) { + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %c4 = arith.constant 4 : index + %cf = arith.constant 1.0 : f32 + %r = scf.for %i0 = %c0 to %c4 step %c1 iter_args(%idx = %c0) -> (index) { + // expected-error@+1 {{operation scheduled before its operands}} + %A_elem = memref.load %A[%idx] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 0 } : memref + %idx1 = arith.addi %idx, %c1 { __test_pipelining_stage__ = 1, __test_pipelining_op_order__ = 1 } : index + memref.store %A_elem, %result[%idx] { __test_pipelining_stage__ = 2, __test_pipelining_op_order__ = 2 } : memref + scf.yield %idx1 : index + } { __test_pipelining_loop__ } + return +} -- GitLab From 19044b099db0882af788d44bf2369a5becf47b00 Mon Sep 17 00:00:00 2001 From: Maciej Gabka Date: Wed, 10 Jan 2024 12:28:00 +0000 Subject: [PATCH 324/652] [NFC][TLI] order SLEEF and ArmPL mappings by alphabetical order (#77500) To make checking test easier, it is better to keep an order of the TLI mappings. This patch sorts all variants of the SLEEF and ArmPL mappings in the order of their base names. This patch also removes some extra inconsistent whitespace added to some of the entries. --- llvm/include/llvm/Analysis/VecFuncs.def | 190 ++++++++++++------------ 1 file changed, 96 insertions(+), 94 deletions(-) diff --git a/llvm/include/llvm/Analysis/VecFuncs.def b/llvm/include/llvm/Analysis/VecFuncs.def index ee9207bb4f7d..b22bdd555cd4 100644 --- a/llvm/include/llvm/Analysis/VecFuncs.def +++ b/llvm/include/llvm/Analysis/VecFuncs.def @@ -470,123 +470,125 @@ TLI_DEFINE_VECFUNC("__exp2f_finite", "__svml_exp2f16", FIXED(16), "_ZGV_LLVM_N16 #elif defined(TLI_DEFINE_SLEEFGNUABI_VF2_VECFUNCS) -TLI_DEFINE_VECFUNC( "acos", "_ZGVnN2v_acos", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("acos", "_ZGVnN2v_acos", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "asin", "_ZGVnN2v_asin", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("asin", "_ZGVnN2v_asin", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "atan", "_ZGVnN2v_atan", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("atan", "_ZGVnN2v_atan", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "atan2", "_ZGVnN2vv_atan2", FIXED(2), "_ZGV_LLVM_N2vv") +TLI_DEFINE_VECFUNC("atan2", "_ZGVnN2vv_atan2", FIXED(2), "_ZGV_LLVM_N2vv") -TLI_DEFINE_VECFUNC( "atanh", "_ZGVnN2v_atanh", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("atanh", "_ZGVnN2v_atanh", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "cos", "_ZGVnN2v_cos", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.cos.f64", "_ZGVnN2v_cos", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("cos", "_ZGVnN2v_cos", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGVnN2v_cos", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "cosh", "_ZGVnN2v_cosh", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("cosh", "_ZGVnN2v_cosh", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "exp", "_ZGVnN2v_exp", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.exp.f64", "_ZGVnN2v_exp", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("exp", "_ZGVnN2v_exp", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGVnN2v_exp", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "exp2", "_ZGVnN2v_exp2", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.exp2.f64", "_ZGVnN2v_exp2", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("exp10", "_ZGVnN2v_exp10", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.exp10.f64", "_ZGVnN2v_exp10", FIXED(2), "_ZGV_LLVM_N2v") + +TLI_DEFINE_VECFUNC("exp2", "_ZGVnN2v_exp2", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.exp2.f64", "_ZGVnN2v_exp2", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "exp10", "_ZGVnN2v_exp10", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.exp10.f64", "_ZGVnN2v_exp10", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("fmod", "_ZGVnN2vv_fmod", FIXED(2), "_ZGV_LLVM_N2vv") -TLI_DEFINE_VECFUNC( "lgamma", "_ZGVnN2v_lgamma", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("lgamma", "_ZGVnN2v_lgamma", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "log", "_ZGVnN2v_log", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.log.f64", "_ZGVnN2v_log", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("log", "_ZGVnN2v_log", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVnN2v_log", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "log2", "_ZGVnN2v_log2", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.log2.f64", "_ZGVnN2v_log2", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("log10", "_ZGVnN2v_log10", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.log10.f64", "_ZGVnN2v_log10", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "log10", "_ZGVnN2v_log10", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.log10.f64", "_ZGVnN2v_log10", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("log2", "_ZGVnN2v_log2", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.log2.f64", "_ZGVnN2v_log2", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "modf", "_ZGVnN2vl8_modf", FIXED(2), "_ZGV_LLVM_N2vl8") +TLI_DEFINE_VECFUNC("modf", "_ZGVnN2vl8_modf", FIXED(2), "_ZGV_LLVM_N2vl8") -TLI_DEFINE_VECFUNC( "pow", "_ZGVnN2vv_pow", FIXED(2), "_ZGV_LLVM_N2vv") -TLI_DEFINE_VECFUNC( "llvm.pow.f64", "_ZGVnN2vv_pow", FIXED(2), "_ZGV_LLVM_N2vv") +TLI_DEFINE_VECFUNC("pow", "_ZGVnN2vv_pow", FIXED(2), "_ZGV_LLVM_N2vv") +TLI_DEFINE_VECFUNC("llvm.pow.f64", "_ZGVnN2vv_pow", FIXED(2), "_ZGV_LLVM_N2vv") -TLI_DEFINE_VECFUNC( "sin", "_ZGVnN2v_sin", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "llvm.sin.f64", "_ZGVnN2v_sin", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("sin", "_ZGVnN2v_sin", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.sin.f64", "_ZGVnN2v_sin", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "sincos", "_ZGVnN2vl8l8_sincos", FIXED(2), "_ZGV_LLVM_N2vl8l8") +TLI_DEFINE_VECFUNC("sincos", "_ZGVnN2vl8l8_sincos", FIXED(2), "_ZGV_LLVM_N2vl8l8") -TLI_DEFINE_VECFUNC( "sincospi", "_ZGVnN2vl8l8_sincospi", FIXED(2), "_ZGV_LLVM_N2vl8l8") +TLI_DEFINE_VECFUNC("sincospi", "_ZGVnN2vl8l8_sincospi", FIXED(2), "_ZGV_LLVM_N2vl8l8") -TLI_DEFINE_VECFUNC( "sinh", "_ZGVnN2v_sinh", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("sinh", "_ZGVnN2v_sinh", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "sqrt", "_ZGVnN2v_sqrt", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("sqrt", "_ZGVnN2v_sqrt", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "tan", "_ZGVnN2v_tan", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("tan", "_ZGVnN2v_tan", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "tanh", "_ZGVnN2v_tanh", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("tanh", "_ZGVnN2v_tanh", FIXED(2), "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC( "tgamma", "_ZGVnN2v_tgamma", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("tgamma", "_ZGVnN2v_tgamma", FIXED(2), "_ZGV_LLVM_N2v") #elif defined(TLI_DEFINE_SLEEFGNUABI_VF4_VECFUNCS) -TLI_DEFINE_VECFUNC( "acosf", "_ZGVnN4v_acosf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("acosf", "_ZGVnN4v_acosf", FIXED(4), "_ZGV_LLVM_N4v") + +TLI_DEFINE_VECFUNC("asinf", "_ZGVnN4v_asinf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "asinf", "_ZGVnN4v_asinf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("atanf", "_ZGVnN4v_atanf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "atanf", "_ZGVnN4v_atanf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("atan2f", "_ZGVnN4vv_atan2f", FIXED(4), "_ZGV_LLVM_N4vv") -TLI_DEFINE_VECFUNC( "atan2f", "_ZGVnN4vv_atan2f", FIXED(4), "_ZGV_LLVM_N4vv") +TLI_DEFINE_VECFUNC("atanhf", "_ZGVnN4v_atanhf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "atanhf", "_ZGVnN4v_atanhf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("cosf", "_ZGVnN4v_cosf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.cos.f32", "_ZGVnN4v_cosf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "cosf", "_ZGVnN4v_cosf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.cos.f32", "_ZGVnN4v_cosf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("coshf", "_ZGVnN4v_coshf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "coshf", "_ZGVnN4v_coshf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("expf", "_ZGVnN4v_expf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGVnN4v_expf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "expf", "_ZGVnN4v_expf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.exp.f32", "_ZGVnN4v_expf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("exp10f", "_ZGVnN4v_exp10f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.exp10.f32", "_ZGVnN4v_exp10f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "exp2f", "_ZGVnN4v_exp2f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.exp2.f32", "_ZGVnN4v_exp2f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("exp2f", "_ZGVnN4v_exp2f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.exp2.f32", "_ZGVnN4v_exp2f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "exp10f", "_ZGVnN4v_exp10f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.exp10.f32", "_ZGVnN4v_exp10f", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("fmodf", "_ZGVnN4vv_fmodf", FIXED(4), "_ZGV_LLVM_N4vv") -TLI_DEFINE_VECFUNC( "lgammaf", "_ZGVnN4v_lgammaf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("lgammaf", "_ZGVnN4v_lgammaf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "logf", "_ZGVnN4v_logf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.log.f32", "_ZGVnN4v_logf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("logf", "_ZGVnN4v_logf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVnN4v_logf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "log2f", "_ZGVnN4v_log2f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.log2.f32", "_ZGVnN4v_log2f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("log10f", "_ZGVnN4v_log10f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.log10.f32", "_ZGVnN4v_log10f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "log10f", "_ZGVnN4v_log10f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.log10.f32", "_ZGVnN4v_log10f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("log2f", "_ZGVnN4v_log2f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.log2.f32", "_ZGVnN4v_log2f", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "modff", "_ZGVnN4vl4_modff", FIXED(4), "_ZGV_LLVM_N4vl4") +TLI_DEFINE_VECFUNC("modff", "_ZGVnN4vl4_modff", FIXED(4), "_ZGV_LLVM_N4vl4") -TLI_DEFINE_VECFUNC( "powf", "_ZGVnN4vv_powf", FIXED(4), "_ZGV_LLVM_N4vv") -TLI_DEFINE_VECFUNC( "llvm.pow.f32", "_ZGVnN4vv_powf", FIXED(4), "_ZGV_LLVM_N4vv") +TLI_DEFINE_VECFUNC("powf", "_ZGVnN4vv_powf", FIXED(4), "_ZGV_LLVM_N4vv") +TLI_DEFINE_VECFUNC("llvm.pow.f32", "_ZGVnN4vv_powf", FIXED(4), "_ZGV_LLVM_N4vv") -TLI_DEFINE_VECFUNC( "sinf", "_ZGVnN4v_sinf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "llvm.sin.f32", "_ZGVnN4v_sinf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("sinf", "_ZGVnN4v_sinf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.sin.f32", "_ZGVnN4v_sinf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("sincosf", "_ZGVnN4vl4l4_sincosf", FIXED(4), "_ZGV_LLVM_N4vl4l4") TLI_DEFINE_VECFUNC("sincospif", "_ZGVnN4vl4l4_sincospif", FIXED(4), "_ZGV_LLVM_N4vl4l4") -TLI_DEFINE_VECFUNC( "sinhf", "_ZGVnN4v_sinhf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("sinhf", "_ZGVnN4v_sinhf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "sqrtf", "_ZGVnN4v_sqrtf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("sqrtf", "_ZGVnN4v_sqrtf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "tanf", "_ZGVnN4v_tanf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("tanf", "_ZGVnN4v_tanf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "tanhf", "_ZGVnN4v_tanhf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("tanhf", "_ZGVnN4v_tanhf", FIXED(4), "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC( "tgammaf", "_ZGVnN4v_tgammaf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("tgammaf", "_ZGVnN4v_tgammaf", FIXED(4), "_ZGV_LLVM_N4v") #elif defined(TLI_DEFINE_SLEEFGNUABI_SCALABLE_VECFUNCS) @@ -618,16 +620,16 @@ TLI_DEFINE_VECFUNC("expf", "_ZGVsMxv_expf", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGVsMxv_exp", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGVsMxv_expf", SCALABLE(4), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("exp2", "_ZGVsMxv_exp2", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("exp2f", "_ZGVsMxv_exp2f", SCALABLE(4), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("llvm.exp2.f64", "_ZGVsMxv_exp2", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("llvm.exp2.f32", "_ZGVsMxv_exp2f", SCALABLE(4), MASKED, "_ZGVsMxv") - TLI_DEFINE_VECFUNC("exp10", "_ZGVsMxv_exp10", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("exp10f", "_ZGVsMxv_exp10f", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp10.f64", "_ZGVsMxv_exp10", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp10.f32", "_ZGVsMxv_exp10f", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("exp2", "_ZGVsMxv_exp2", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("exp2f", "_ZGVsMxv_exp2f", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("llvm.exp2.f64", "_ZGVsMxv_exp2", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("llvm.exp2.f32", "_ZGVsMxv_exp2f", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("fmod", "_ZGVsMxvv_fmod", SCALABLE(2), MASKED, "_ZGVsMxvv") TLI_DEFINE_VECFUNC("fmodf", "_ZGVsMxvv_fmodf", SCALABLE(4), MASKED, "_ZGVsMxvv") @@ -639,16 +641,16 @@ TLI_DEFINE_VECFUNC("logf", "_ZGVsMxv_logf", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVsMxv_log", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVsMxv_logf", SCALABLE(4), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC( "log2", "_ZGVsMxv_log2", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC( "log2f", "_ZGVsMxv_log2f", SCALABLE(4), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC( "llvm.log2.f64", "_ZGVsMxv_log2", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC( "llvm.log2.f32", "_ZGVsMxv_log2f", SCALABLE(4), MASKED, "_ZGVsMxv") - TLI_DEFINE_VECFUNC("log10", "_ZGVsMxv_log10", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("log10f", "_ZGVsMxv_log10f", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log10.f64", "_ZGVsMxv_log10", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log10.f32", "_ZGVsMxv_log10f", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("log2", "_ZGVsMxv_log2", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("log2f", "_ZGVsMxv_log2f", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("llvm.log2.f64", "_ZGVsMxv_log2", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("llvm.log2.f32", "_ZGVsMxv_log2f", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("modf", "_ZGVsMxvl8_modf", SCALABLE(2), MASKED, "_ZGVsMxvl8") TLI_DEFINE_VECFUNC("modff", "_ZGVsMxvl4_modff", SCALABLE(4), MASKED, "_ZGVsMxvl4") @@ -765,16 +767,6 @@ TLI_DEFINE_VECFUNC("llvm.exp.f32", "armpl_vexpq_f32", FIXED(4), NOMASK, "_ZGV_LL TLI_DEFINE_VECFUNC("llvm.exp.f64", "armpl_svexp_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp.f32", "armpl_svexp_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("exp2", "armpl_vexp2q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC("exp2f", "armpl_vexp2q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC("exp2", "armpl_svexp2_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("exp2f", "armpl_svexp2_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") - -TLI_DEFINE_VECFUNC("llvm.exp2.f64", "armpl_vexp2q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC("llvm.exp2.f32", "armpl_vexp2q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC("llvm.exp2.f64", "armpl_svexp2_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("llvm.exp2.f32", "armpl_svexp2_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") - TLI_DEFINE_VECFUNC("exp10", "armpl_vexp10q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("exp10f", "armpl_vexp10q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("exp10", "armpl_svexp10_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") @@ -785,6 +777,16 @@ TLI_DEFINE_VECFUNC("llvm.exp10.f32", "armpl_vexp10q_f32", FIXED(4), NOMASK, "_ZG TLI_DEFINE_VECFUNC("llvm.exp10.f64", "armpl_svexp10_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp10.f32", "armpl_svexp10_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("exp2", "armpl_vexp2q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("exp2f", "armpl_vexp2q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("exp2", "armpl_svexp2_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("exp2f", "armpl_svexp2_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("llvm.exp2.f64", "armpl_vexp2q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.exp2.f32", "armpl_vexp2q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.exp2.f64", "armpl_svexp2_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("llvm.exp2.f32", "armpl_svexp2_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("expm1", "armpl_vexpm1q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("expm1f", "armpl_vexpm1q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("expm1", "armpl_svexpm1_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") @@ -830,6 +832,16 @@ TLI_DEFINE_VECFUNC("llvm.log.f32", "armpl_vlogq_f32", FIXED(4), NOMASK, "_ZGV_LL TLI_DEFINE_VECFUNC("llvm.log.f64", "armpl_svlog_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log.f32", "armpl_svlog_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("log10", "armpl_vlog10q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("log10f", "armpl_vlog10q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("log10", "armpl_svlog10_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("log10f", "armpl_svlog10_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("llvm.log10.f64", "armpl_vlog10q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("llvm.log10.f32", "armpl_vlog10q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("llvm.log10.f64", "armpl_svlog10_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("llvm.log10.f32", "armpl_svlog10_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("log1p", "armpl_vlog1pq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("log1pf", "armpl_vlog1pq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("log1p", "armpl_svlog1p_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") @@ -845,16 +857,6 @@ TLI_DEFINE_VECFUNC("llvm.log2.f32", "armpl_vlog2q_f32", FIXED(4), NOMASK, "_ZGV_ TLI_DEFINE_VECFUNC("llvm.log2.f64", "armpl_svlog2_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log2.f32", "armpl_svlog2_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("log10", "armpl_vlog10q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC("log10f", "armpl_vlog10q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC("log10", "armpl_svlog10_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("log10f", "armpl_svlog10_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") - -TLI_DEFINE_VECFUNC("llvm.log10.f64", "armpl_vlog10q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") -TLI_DEFINE_VECFUNC("llvm.log10.f32", "armpl_vlog10q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") -TLI_DEFINE_VECFUNC("llvm.log10.f64", "armpl_svlog10_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") -TLI_DEFINE_VECFUNC("llvm.log10.f32", "armpl_svlog10_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") - TLI_DEFINE_VECFUNC("modf", "armpl_vmodfq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vl8") TLI_DEFINE_VECFUNC("modff", "armpl_vmodfq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vl4") TLI_DEFINE_VECFUNC("modf", "armpl_svmodf_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvl8") -- GitLab From 77753750033632e353e17948457433efd67f92de Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Wed, 10 Jan 2024 09:23:14 -0300 Subject: [PATCH 325/652] [flang][doc] Correct spelling of CMake --- flang/docs/GettingStarted.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flang/docs/GettingStarted.md b/flang/docs/GettingStarted.md index ada685426488..043804e5a122 100644 --- a/flang/docs/GettingStarted.md +++ b/flang/docs/GettingStarted.md @@ -89,7 +89,7 @@ ninja ``` On Darwin, to make flang able to link binaries with the default sysroot without -having to specify additional flags, use the `DEFAULT_SYSROOT` cmake flag, e.g. +having to specify additional flags, use the `DEFAULT_SYSROOT` CMake flag, e.g. `-DDEFAULT_SYSROOT="$(xcrun --show-sdk-path)"`. By default flang tests that do not specify an explicit `--target` flag use -- GitLab From cc21aa1922b3d0c4fde52046d8d16d1048f8064e Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 10 Jan 2024 12:35:39 +0000 Subject: [PATCH 326/652] [X86] lower1BitShuffle - fold permute(setcc(x,y)) -> setcc(permute(x),permute(y)) for 32/64-bit element vectors Noticed in #77459 - for wider element types, its usually better to pre-shuffle the comparison arguments if we can, like we already for broadcasts --- llvm/lib/Target/X86/X86ISelLowering.cpp | 14 ++++---- llvm/test/CodeGen/X86/pr77459.ll | 5 ++- llvm/test/CodeGen/X86/vector-shuffle-v1.ll | 39 +++++++--------------- 3 files changed, 22 insertions(+), 36 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6da137426c56..5f6f500e49dd 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17224,6 +17224,7 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef Mask, "Cannot lower 512-bit vectors w/o basic ISA!"); int NumElts = Mask.size(); + int NumV2Elements = count_if(Mask, [NumElts](int M) { return M >= NumElts; }); // Try to recognize shuffles that are just padding a subvector with zeros. int SubvecElts = 0; @@ -17289,17 +17290,18 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef Mask, Offset += NumElts; // Increment for next iteration. } - // If we're broadcasting a SETCC result, try to broadcast the ops instead. + // If we're performing an unary shuffle on a SETCC result, try to shuffle the + // ops instead. // TODO: What other unary shuffles would benefit from this? - if (isBroadcastShuffleMask(Mask) && V1.getOpcode() == ISD::SETCC && - V1->hasOneUse()) { + if (NumV2Elements == 0 && V1.getOpcode() == ISD::SETCC && V1->hasOneUse()) { SDValue Op0 = V1.getOperand(0); SDValue Op1 = V1.getOperand(1); ISD::CondCode CC = cast(V1.getOperand(2))->get(); EVT OpVT = Op0.getValueType(); - return DAG.getSetCC( - DL, VT, DAG.getVectorShuffle(OpVT, DL, Op0, DAG.getUNDEF(OpVT), Mask), - DAG.getVectorShuffle(OpVT, DL, Op1, DAG.getUNDEF(OpVT), Mask), CC); + if (OpVT.getScalarSizeInBits() >= 32 || isBroadcastShuffleMask(Mask)) + return DAG.getSetCC( + DL, VT, DAG.getVectorShuffle(OpVT, DL, Op0, DAG.getUNDEF(OpVT), Mask), + DAG.getVectorShuffle(OpVT, DL, Op1, DAG.getUNDEF(OpVT), Mask), CC); } MVT ExtVT; diff --git a/llvm/test/CodeGen/X86/pr77459.ll b/llvm/test/CodeGen/X86/pr77459.ll index cf073e97137e..9c072e6f5e3f 100644 --- a/llvm/test/CodeGen/X86/pr77459.ll +++ b/llvm/test/CodeGen/X86/pr77459.ll @@ -42,10 +42,9 @@ define i4 @reverse_cmp_v4i1(<4 x i32> %a0, <4 x i32> %a1) { ; ; AVX512-LABEL: reverse_cmp_v4i1: ; AVX512: # %bb.0: -; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 -; AVX512-NEXT: vpmovm2d %k0, %xmm0 +; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0] ; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] -; AVX512-NEXT: vpmovd2m %xmm0, %k0 +; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: # kill: def $al killed $al killed $eax ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll index 809d94b649fb..6ef203999af6 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll @@ -9,8 +9,6 @@ define <2 x i1> @shuf2i1_1_0(<2 x i1> %a) { ; AVX512F-LABEL: shuf2i1_1_0: ; AVX512F: # %bb.0: ; AVX512F-NEXT: vpsllq $63, %xmm0, %xmm0 -; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 -; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} @@ -21,19 +19,15 @@ define <2 x i1> @shuf2i1_1_0(<2 x i1> %a) { ; AVX512VL-LABEL: shuf2i1_1_0: ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpsllq $63, %xmm0, %xmm0 +; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; AVX512VL-NEXT: vptestmq %xmm0, %xmm0, %k1 ; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} {z} -; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] -; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1 ; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z} ; AVX512VL-NEXT: retq ; ; VL_BW_DQ-LABEL: shuf2i1_1_0: ; VL_BW_DQ: # %bb.0: ; VL_BW_DQ-NEXT: vpsllq $63, %xmm0, %xmm0 -; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0 -; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0 ; VL_BW_DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0 ; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0 @@ -86,10 +80,8 @@ define <2 x i1> @shuf2i1_1_2(<2 x i1> %a) { define <4 x i1> @shuf4i1_3_2_10(<4 x i1> %a) { ; AVX512F-LABEL: shuf4i1_3_2_10: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 -; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] +; AVX512F-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 @@ -98,21 +90,17 @@ define <4 x i1> @shuf4i1_3_2_10(<4 x i1> %a) { ; ; AVX512VL-LABEL: shuf4i1_3_2_10: ; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] ; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1 ; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512VL-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1} {z} -; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0] -; AVX512VL-NEXT: vptestmd %xmm1, %xmm1, %k1 ; AVX512VL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} ; AVX512VL-NEXT: retq ; ; VL_BW_DQ-LABEL: shuf4i1_3_2_10: ; VL_BW_DQ: # %bb.0: -; VL_BW_DQ-NEXT: vpslld $31, %xmm0, %xmm0 -; VL_BW_DQ-NEXT: vpmovd2m %xmm0, %k0 -; VL_BW_DQ-NEXT: vpmovm2d %k0, %xmm0 ; VL_BW_DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] +; VL_BW_DQ-NEXT: vpslld $31, %xmm0, %xmm0 ; VL_BW_DQ-NEXT: vpmovd2m %xmm0, %k0 ; VL_BW_DQ-NEXT: vpmovm2d %k0, %xmm0 ; VL_BW_DQ-NEXT: retq @@ -123,11 +111,10 @@ define <4 x i1> @shuf4i1_3_2_10(<4 x i1> %a) { define <8 x i1> @shuf8i1_3_6_1_0_3_7_7_0(<8 x i64> %a, <8 x i64> %b, <8 x i64> %a1, <8 x i64> %b1) { ; AVX512F-LABEL: shuf8i1_3_6_1_0_3_7_7_0: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vpcmpeqq %zmm2, %zmm0, %k1 -; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [3,6,1,0,3,7,7,0] +; AVX512F-NEXT: vpermq %zmm2, %zmm1, %zmm2 ; AVX512F-NEXT: vpermq %zmm0, %zmm1, %zmm0 -; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 +; AVX512F-NEXT: vpcmpeqq %zmm2, %zmm0, %k1 ; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 @@ -136,12 +123,11 @@ define <8 x i1> @shuf8i1_3_6_1_0_3_7_7_0(<8 x i64> %a, <8 x i64> %b, <8 x i64> % ; ; AVX512VL-LABEL: shuf8i1_3_6_1_0_3_7_7_0: ; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqa64 {{.*#+}} zmm1 = [3,6,1,0,3,7,7,0] +; AVX512VL-NEXT: vpermq %zmm2, %zmm1, %zmm2 +; AVX512VL-NEXT: vpermq %zmm0, %zmm1, %zmm0 ; AVX512VL-NEXT: vpcmpeqq %zmm2, %zmm0, %k1 ; AVX512VL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 -; AVX512VL-NEXT: vmovdqa32 %ymm0, %ymm1 {%k1} {z} -; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [3,6,1,0,3,7,7,0] -; AVX512VL-NEXT: vpermd %ymm1, %ymm2, %ymm1 -; AVX512VL-NEXT: vptestmd %ymm1, %ymm1, %k1 ; AVX512VL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z} ; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0 ; AVX512VL-NEXT: vzeroupper @@ -149,11 +135,10 @@ define <8 x i1> @shuf8i1_3_6_1_0_3_7_7_0(<8 x i64> %a, <8 x i64> %b, <8 x i64> % ; ; VL_BW_DQ-LABEL: shuf8i1_3_6_1_0_3_7_7_0: ; VL_BW_DQ: # %bb.0: +; VL_BW_DQ-NEXT: vmovdqa64 {{.*#+}} zmm1 = [3,6,1,0,3,7,7,0] +; VL_BW_DQ-NEXT: vpermq %zmm2, %zmm1, %zmm2 +; VL_BW_DQ-NEXT: vpermq %zmm0, %zmm1, %zmm0 ; VL_BW_DQ-NEXT: vpcmpeqq %zmm2, %zmm0, %k0 -; VL_BW_DQ-NEXT: vpmovm2d %k0, %ymm0 -; VL_BW_DQ-NEXT: vmovdqa {{.*#+}} ymm1 = [3,6,1,0,3,7,7,0] -; VL_BW_DQ-NEXT: vpermd %ymm0, %ymm1, %ymm0 -; VL_BW_DQ-NEXT: vpmovd2m %ymm0, %k0 ; VL_BW_DQ-NEXT: vpmovm2w %k0, %xmm0 ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq -- GitLab From b8dca4fa729fcbd5d42ce3ca056dc4d278da2548 Mon Sep 17 00:00:00 2001 From: Vivek Khandelwal Date: Wed, 10 Jan 2024 18:09:32 +0530 Subject: [PATCH 327/652] [mlir][math] Add math.acosh|asin|asinh|atanh op (#77463) Signed-Off By: Vivek Khandelwal --- mlir/include/mlir/Dialect/Math/IR/MathOps.td | 108 ++++++++++++ mlir/lib/Conversion/MathToLibm/MathToLibm.cpp | 4 + mlir/lib/Dialect/Math/IR/MathOps.cpp | 72 ++++++++ .../MathToLibm/convert-to-libm.mlir | 166 ++++++++++++++++++ 4 files changed, 350 insertions(+) diff --git a/mlir/include/mlir/Dialect/Math/IR/MathOps.td b/mlir/include/mlir/Dialect/Math/IR/MathOps.td index fdb9ec09ae3e..3f6d2d2e4478 100644 --- a/mlir/include/mlir/Dialect/Math/IR/MathOps.td +++ b/mlir/include/mlir/Dialect/Math/IR/MathOps.td @@ -135,6 +135,87 @@ def Math_AbsIOp : Math_IntegerUnaryOp<"absi"> { let hasFolder = 1; } +//===----------------------------------------------------------------------===// +// AcoshOp +//===----------------------------------------------------------------------===// + +def Math_AcoshOp : Math_FloatUnaryOp<"acosh">{ + let summary = "Hyperbolic arcus cosine of the given value"; + let description = [{ + Syntax: + + ``` + operation ::= ssa-id `=` `math.acosh` ssa-use `:` type + ``` + + The `acosh` operation computes the arcus cosine of a given value. It takes + one operand of floating point type (i.e., scalar, tensor or vector) and returns + one result of the same type. It has no standard attributes. + + Example: + + ```mlir + // Hyperbolic arcus cosine of scalar value. + %a = math.acosh %b : f64 + ``` + }]; + let hasFolder = 1; +} + +//===----------------------------------------------------------------------===// +// AsinOp +//===----------------------------------------------------------------------===// + +def Math_AsinOp : Math_FloatUnaryOp<"asin">{ + let summary = "arcus sine of the given value"; + let description = [{ + Syntax: + + ``` + operation ::= ssa-id `=` `math.asin` ssa-use `:` type + ``` + + The `asin` operation computes the arcus sine of a given value. It takes + one operand of floating point type (i.e., scalar, tensor or vector) and returns + one result of the same type. It has no standard attributes. + + Example: + + ```mlir + // Arcus sine of scalar value. + %a = math.asin %b : f64 + ``` + }]; + let hasFolder = 1; +} + +//===----------------------------------------------------------------------===// +// AsinhOp +//===----------------------------------------------------------------------===// + +def Math_AsinhOp : Math_FloatUnaryOp<"asinh">{ + let summary = "hyperbolic arcus sine of the given value"; + let description = [{ + Syntax: + + ``` + operation ::= ssa-id `=` `math.asinh` ssa-use `:` type + ``` + + The `asinh` operation computes the hyperbolic arcus sine of a given value. It takes + one operand of floating point type (i.e., scalar, tensor or vector) and returns + one result of the same type. It has no standard attributes. + + Example: + + ```mlir + // Hyperbolic arcus sine of scalar value. + %a = math.asinh %b : f64 + ``` + }]; + let hasFolder = 1; +} + //===----------------------------------------------------------------------===// // AtanOp //===----------------------------------------------------------------------===// @@ -156,6 +237,33 @@ def Math_AtanOp : Math_FloatUnaryOp<"atan">{ let hasFolder = 1; } +//===----------------------------------------------------------------------===// +// AtanhOp +//===----------------------------------------------------------------------===// + +def Math_AtanhOp : Math_FloatUnaryOp<"atanh">{ + let summary = "hyperbolic arcus tangent of the given value"; + let description = [{ + Syntax: + + ``` + operation ::= ssa-id `=` `math.atanh` ssa-use `:` type + ``` + + The `atanh` operation computes the hyperbolic arcus tangent of a given value. It takes + one operand of floating point type (i.e., scalar, tensor or vector) and returns + one result of the same type. It has no standard attributes. + + Example: + + ```mlir + // Hyperbolic arcus tangent of scalar value. + %a = math.atanh %b : f64 + ``` + }]; + let hasFolder = 1; +} + //===----------------------------------------------------------------------===// // Atan2Op //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp b/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp index 80eec9b2df74..d1372576407f 100644 --- a/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp +++ b/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp @@ -163,8 +163,12 @@ void mlir::populateMathToLibmConversionPatterns(RewritePatternSet &patterns) { MLIRContext *ctx = patterns.getContext(); populatePatternsForOp(patterns, ctx, "acosf", "acos"); + populatePatternsForOp(patterns, ctx, "acoshf", "acosh"); + populatePatternsForOp(patterns, ctx, "asinf", "asin"); + populatePatternsForOp(patterns, ctx, "asinhf", "asinh"); populatePatternsForOp(patterns, ctx, "atan2f", "atan2"); populatePatternsForOp(patterns, ctx, "atanf", "atan"); + populatePatternsForOp(patterns, ctx, "atanhf", "atanh"); populatePatternsForOp(patterns, ctx, "cbrtf", "cbrt"); populatePatternsForOp(patterns, ctx, "ceilf", "ceil"); populatePatternsForOp(patterns, ctx, "cosf", "cos"); diff --git a/mlir/lib/Dialect/Math/IR/MathOps.cpp b/mlir/lib/Dialect/Math/IR/MathOps.cpp index bac46996fce7..1690585e78c5 100644 --- a/mlir/lib/Dialect/Math/IR/MathOps.cpp +++ b/mlir/lib/Dialect/Math/IR/MathOps.cpp @@ -59,6 +59,60 @@ OpFoldResult math::AcosOp::fold(FoldAdaptor adaptor) { }); } +//===----------------------------------------------------------------------===// +// AcoshOp folder +//===----------------------------------------------------------------------===// + +OpFoldResult math::AcoshOp::fold(FoldAdaptor adaptor) { + return constFoldUnaryOpConditional( + adaptor.getOperands(), [](const APFloat &a) -> std::optional { + switch (a.getSizeInBits(a.getSemantics())) { + case 64: + return APFloat(acosh(a.convertToDouble())); + case 32: + return APFloat(acoshf(a.convertToFloat())); + default: + return {}; + } + }); +} + +//===----------------------------------------------------------------------===// +// AsinOp folder +//===----------------------------------------------------------------------===// + +OpFoldResult math::AsinOp::fold(FoldAdaptor adaptor) { + return constFoldUnaryOpConditional( + adaptor.getOperands(), [](const APFloat &a) -> std::optional { + switch (a.getSizeInBits(a.getSemantics())) { + case 64: + return APFloat(asin(a.convertToDouble())); + case 32: + return APFloat(asinf(a.convertToFloat())); + default: + return {}; + } + }); +} + +//===----------------------------------------------------------------------===// +// AsinhOp folder +//===----------------------------------------------------------------------===// + +OpFoldResult math::AsinhOp::fold(FoldAdaptor adaptor) { + return constFoldUnaryOpConditional( + adaptor.getOperands(), [](const APFloat &a) -> std::optional { + switch (a.getSizeInBits(a.getSemantics())) { + case 64: + return APFloat(asinh(a.convertToDouble())); + case 32: + return APFloat(asinhf(a.convertToFloat())); + default: + return {}; + } + }); +} + //===----------------------------------------------------------------------===// // AtanOp folder //===----------------------------------------------------------------------===// @@ -77,6 +131,24 @@ OpFoldResult math::AtanOp::fold(FoldAdaptor adaptor) { }); } +//===----------------------------------------------------------------------===// +// AtanhOp folder +//===----------------------------------------------------------------------===// + +OpFoldResult math::AtanhOp::fold(FoldAdaptor adaptor) { + return constFoldUnaryOpConditional( + adaptor.getOperands(), [](const APFloat &a) -> std::optional { + switch (a.getSizeInBits(a.getSemantics())) { + case 64: + return APFloat(atanh(a.convertToDouble())); + case 32: + return APFloat(atanhf(a.convertToFloat())); + default: + return {}; + } + }); +} + //===----------------------------------------------------------------------===// // Atan2Op folder //===----------------------------------------------------------------------===// diff --git a/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir b/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir index bfe084b6ca0a..ffc2939afe7f 100644 --- a/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir +++ b/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir @@ -2,8 +2,16 @@ // CHECK-DAG: @acos(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @acosf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @acosh(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @acoshf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @asin(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @asinf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @asinh(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @asinhf(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @atan(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @atanf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @atanh(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @atanhf(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @erf(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @erff(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @expm1(f64) -> f64 attributes {llvm.readnone} @@ -70,6 +78,117 @@ func.func @acos_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (ve return %float_result, %double_result : vector<2xf32>, vector<2xf64> } +// CHECK-LABEL: func @acosh_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @acosh_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @acoshf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.acosh %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @acosh(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.acosh %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +// CHECK-LABEL: func @acosh_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @acoshf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @acoshf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @acosh(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @acosh(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } +func.func @acosh_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.acosh %float : vector<2xf32> + %double_result = math.acosh %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} + +// CHECK-LABEL: func @asin_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @asin_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @asinf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.asin %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @asin(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.asin %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +// CHECK-LABEL: func @asin_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @asinf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @asinf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @asin(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @asin(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } +func.func @asin_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.asin %float : vector<2xf32> + %double_result = math.asin %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} + +// CHECK-LABEL: func @asinh_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @asinh_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @asinhf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.asinh %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @asinh(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.asinh %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +// CHECK-LABEL: func @asinh_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @asinhf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @asinhf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @asinh(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @asinh(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } +func.func @asinh_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.asinh %float : vector<2xf32> + %double_result = math.asinh %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} + // CHECK-LABEL: func @atan_caller // CHECK-SAME: %[[FLOAT:.*]]: f32 // CHECK-SAME: %[[DOUBLE:.*]]: f64 @@ -117,6 +236,53 @@ func.func @atan_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (ve return %float_result, %double_result : vector<2xf32>, vector<2xf64> } +// CHECK-LABEL: func @atanh_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +// CHECK-SAME: %[[HALF:.*]]: f16 +// CHECK-SAME: %[[BFLOAT:.*]]: bf16 +func.func @atanh_caller(%float: f32, %double: f64, %half: f16, %bfloat: bf16) -> (f32, f64, f16, bf16) { + // CHECK: %[[FLOAT_RESULT:.*]] = call @atanhf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.atanh %float : f32 + // CHECK: %[[DOUBLE_RESULT:.*]] = call @atanh(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.atanh %double : f64 + // CHECK: %[[HALF_PROMOTED:.*]] = arith.extf %[[HALF]] : f16 to f32 + // CHECK: %[[HALF_CALL:.*]] = call @atanhf(%[[HALF_PROMOTED]]) : (f32) -> f32 + // CHECK: %[[HALF_RESULT:.*]] = arith.truncf %[[HALF_CALL]] : f32 to f16 + %half_result = math.atanh %half : f16 + // CHECK: %[[BFLOAT_PROMOTED:.*]] = arith.extf %[[BFLOAT]] : bf16 to f32 + // CHECK: %[[BFLOAT_CALL:.*]] = call @atanhf(%[[BFLOAT_PROMOTED]]) : (f32) -> f32 + // CHECK: %[[BFLOAT_RESULT:.*]] = arith.truncf %[[BFLOAT_CALL]] : f32 to bf16 + %bfloat_result = math.atanh %bfloat : bf16 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]], %[[HALF_RESULT]], %[[BFLOAT_RESULT]] + return %float_result, %double_result, %half_result, %bfloat_result : f32, f64, f16, bf16 +} + +// CHECK-LABEL: func @atanh_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @atanhf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @atanhf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @atanh(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @atanh(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } +func.func @atanh_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.atanh %float : vector<2xf32> + %double_result = math.atanh %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} + // CHECK-LABEL: func @tanh_caller // CHECK-SAME: %[[FLOAT:.*]]: f32 // CHECK-SAME: %[[DOUBLE:.*]]: f64 -- GitLab From 60bb5c54f6e1eeed0aae7917d10f746ee8135d9d Mon Sep 17 00:00:00 2001 From: Ivan Kosarev Date: Wed, 10 Jan 2024 12:58:18 +0000 Subject: [PATCH 328/652] [AMDGPU] Fix predicates for various True16 instructions. (#77581) Resolves AsmParser ambiguities, e.g., between V_SUBREV_F16_t16_dpp8_gfx11 and V_SUBREV_F16_t16_dpp8_gfx12. Part of . --- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 12 ++++++------ llvm/lib/Target/AMDGPU/VOPInstructions.td | 13 ++++++------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 3e66b5550cce..48d4e259bc1c 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -111,8 +111,8 @@ class VOP2_Real : VOP2_Real { - let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, - Gen.AssemblerPredicate); + let AssemblerPredicate = Gen.AssemblerPredicate; + let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); let DecoderNamespace = Gen.DecoderNamespace# !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); } @@ -1275,8 +1275,8 @@ class VOP2_DPP16 op, VOP2_DPP_Pseudo ps, int subtarget, class VOP2_DPP16_Gen op, VOP2_DPP_Pseudo ps, GFXGen Gen, string opName = ps.OpName, VOPProfile p = ps.Pfl> : VOP2_DPP16 { - let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, - Gen.AssemblerPredicate); + let AssemblerPredicate = Gen.AssemblerPredicate; + let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); let DecoderNamespace = "DPP"#Gen.DecoderNamespace# !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); } @@ -1304,8 +1304,8 @@ class VOP2_DPP8 op, VOP2_Pseudo ps, class VOP2_DPP8_Gen op, VOP2_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> : VOP2_DPP8 { - let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, - Gen.AssemblerPredicate); + let AssemblerPredicate = Gen.AssemblerPredicate; + let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); let DecoderNamespace = "DPP8"#Gen.DecoderNamespace# !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); } diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index fd4626d902ac..c4b9e7063093 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -208,8 +208,8 @@ class VOP3_Real : VOP3_Real { - let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, - Gen.AssemblerPredicate); + let AssemblerPredicate = Gen.AssemblerPredicate; + let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); let DecoderNamespace = Gen.DecoderNamespace# !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); } @@ -1340,8 +1340,8 @@ class VOP3_DPP16 op, VOP_DPP_Pseudo ps, int subtarget, class VOP3_DPP16_Gen op, VOP_DPP_Pseudo ps, GFXGen Gen, string opName = ps.OpName> : VOP3_DPP16 { - let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, - Gen.AssemblerPredicate); + let AssemblerPredicate = Gen.AssemblerPredicate; + let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); let DecoderNamespace = "DPP"#Gen.DecoderNamespace# !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); } @@ -1470,9 +1470,8 @@ multiclass VOP3_Real_dpp8_with_name op, string opName, let AsmString = asmName # ps.Pfl.AsmVOP3DPP8, DecoderNamespace = "DPP8"#Gen.DecoderNamespace# !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"), - AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, - Gen.AssemblerPredicate) in { - + OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], + [TruePredicate]) in { defm NAME : VOP3_Real_dpp8_Base; } } -- GitLab From 5c0b3a0cb7f70db3ebcd195596e5fadc12d0bc9c Mon Sep 17 00:00:00 2001 From: Michael Buch Date: Wed, 10 Jan 2024 13:08:11 +0000 Subject: [PATCH 329/652] [lldb][ClangASTImporter][NFC] Remove redundant do-while loop (#77596) This seems to have always been a redundant do-while since its introduction in `2e93a2ad2148d19337bf5f9885e46e3c00e8ab82`. --- .../Clang/ClangASTImporter.cpp | 51 +++++++++---------- 1 file changed, 24 insertions(+), 27 deletions(-) diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp index 5d109feb3d39..62a30c14912b 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp @@ -943,44 +943,41 @@ void ClangASTImporter::ASTImporterDelegate::ImportDefinitionTo( // the class was originally sourced from symbols. if (ObjCInterfaceDecl *to_objc_interface = dyn_cast(to)) { - do { - ObjCInterfaceDecl *to_superclass = to_objc_interface->getSuperClass(); + ObjCInterfaceDecl *to_superclass = to_objc_interface->getSuperClass(); - if (to_superclass) - break; // we're not going to override it if it's set + if (to_superclass) + return; // we're not going to override it if it's set - ObjCInterfaceDecl *from_objc_interface = - dyn_cast(from); + ObjCInterfaceDecl *from_objc_interface = dyn_cast(from); - if (!from_objc_interface) - break; + if (!from_objc_interface) + return; - ObjCInterfaceDecl *from_superclass = from_objc_interface->getSuperClass(); + ObjCInterfaceDecl *from_superclass = from_objc_interface->getSuperClass(); - if (!from_superclass) - break; + if (!from_superclass) + return; - llvm::Expected imported_from_superclass_decl = - Import(from_superclass); + llvm::Expected imported_from_superclass_decl = + Import(from_superclass); - if (!imported_from_superclass_decl) { - LLDB_LOG_ERROR(log, imported_from_superclass_decl.takeError(), - "Couldn't import decl: {0}"); - break; - } + if (!imported_from_superclass_decl) { + LLDB_LOG_ERROR(log, imported_from_superclass_decl.takeError(), + "Couldn't import decl: {0}"); + return; + } - ObjCInterfaceDecl *imported_from_superclass = - dyn_cast(*imported_from_superclass_decl); + ObjCInterfaceDecl *imported_from_superclass = + dyn_cast(*imported_from_superclass_decl); - if (!imported_from_superclass) - break; + if (!imported_from_superclass) + return; - if (!to_objc_interface->hasDefinition()) - to_objc_interface->startDefinition(); + if (!to_objc_interface->hasDefinition()) + to_objc_interface->startDefinition(); - to_objc_interface->setSuperClass(m_source_ctx->getTrivialTypeSourceInfo( - m_source_ctx->getObjCInterfaceType(imported_from_superclass))); - } while (false); + to_objc_interface->setSuperClass(m_source_ctx->getTrivialTypeSourceInfo( + m_source_ctx->getObjCInterfaceType(imported_from_superclass))); } } -- GitLab From d65a7d1f1a2139f927949ab6b1a9d90113de9a90 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Jan 2024 07:19:38 -0600 Subject: [PATCH 330/652] [Libomptarget] Do not run CPU tests if FFI was not found Summary: The previous behaviour before I made it dynamically open libFFI was that these tests would be ignored if FFI was not found. This now allows tests to be run without the dependency and thus the tests fails on some buildbots. This simply makesit not build the tests if it's not present. --- .../libomptarget/plugins-nextgen/CMakeLists.txt | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/openmp/libomptarget/plugins-nextgen/CMakeLists.txt b/openmp/libomptarget/plugins-nextgen/CMakeLists.txt index 882be3025003..9b4e94550239 100644 --- a/openmp/libomptarget/plugins-nextgen/CMakeLists.txt +++ b/openmp/libomptarget/plugins-nextgen/CMakeLists.txt @@ -82,11 +82,16 @@ if(CMAKE_SYSTEM_PROCESSOR MATCHES "${tmachine}$") target_include_directories("omptarget.rtl.${tmachine_libname}" PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) - list(APPEND LIBOMPTARGET_TESTED_PLUGINS "omptarget.rtl.${tmachine_libname}") - set(LIBOMPTARGET_TESTED_PLUGINS - "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE) - set(LIBOMPTARGET_SYSTEM_TARGETS - "${LIBOMPTARGET_SYSTEM_TARGETS} ${tmachine_triple} ${tmachine_triple}-LTO" PARENT_SCOPE) + if(LIBOMPTARGET_DEP_LIBFFI_FOUND) + list(APPEND LIBOMPTARGET_TESTED_PLUGINS "omptarget.rtl.${tmachine_libname}") + set(LIBOMPTARGET_TESTED_PLUGINS + "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE) + set(LIBOMPTARGET_SYSTEM_TARGETS + "${LIBOMPTARGET_SYSTEM_TARGETS} ${tmachine_triple} + ${tmachine_triple}-LTO" PARENT_SCOPE) + else() + libomptarget_say("Not generating ${tmachine_name} tests. LibFFI not found.") + endif() else() libomptarget_say("Not building ${tmachine_name} NextGen offloading plugin: machine not found in the system.") endif() -- GitLab From 9aa8c82748bfb313598e71476123b785f6da41b9 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Wed, 10 Jan 2024 15:12:19 +0100 Subject: [PATCH 331/652] [SystemZ] Fix 256-bit shifts when i128 is legal When i128 is a legal type, SelectionDAG now attempts to use SRL_PARTS etc. with type i128, which is not implemented. Fix by marking those as Expand, just like we do for i64. Fixes https://github.com/llvm/llvm-project/issues/77132 --- .../Target/SystemZ/SystemZISelLowering.cpp | 7 + llvm/test/CodeGen/SystemZ/shift-16.ll | 132 ++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 llvm/test/CodeGen/SystemZ/shift-16.ll diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 2450c6801a66..7d387c7b9f2f 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -340,6 +340,13 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, setLibcallName(RTLIB::SHL_I128, nullptr); setLibcallName(RTLIB::SRA_I128, nullptr); + // Also expand 256 bit shifts if i128 is a legal type. + if (isTypeLegal(MVT::i128)) { + setOperationAction(ISD::SRL_PARTS, MVT::i128, Expand); + setOperationAction(ISD::SHL_PARTS, MVT::i128, Expand); + setOperationAction(ISD::SRA_PARTS, MVT::i128, Expand); + } + // Handle bitcast from fp128 to i128. if (!isTypeLegal(MVT::i128)) setOperationAction(ISD::BITCAST, MVT::i128, Custom); diff --git a/llvm/test/CodeGen/SystemZ/shift-16.ll b/llvm/test/CodeGen/SystemZ/shift-16.ll new file mode 100644 index 000000000000..d9d0e06ba262 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/shift-16.ll @@ -0,0 +1,132 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; Test that 256-bit shifts still work when i128 is a legal type +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Shift left. +define i256 @f1(i256 %a, i256 %sh) { +; CHECK-LABEL: f1: +; CHECK: # %bb.0: +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 16(%r3), 3 +; CHECK-NEXT: l %r0, 28(%r4) +; CHECK-NEXT: clijhe %r0, 128, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: lhi %r1, 128 +; CHECK-NEXT: sr %r1, %r0 +; CHECK-NEXT: vlvgp %v2, %r1, %r1 +; CHECK-NEXT: vrepb %v2, %v2, 15 +; CHECK-NEXT: vsrlb %v3, %v1, %v2 +; CHECK-NEXT: vsrl %v2, %v3, %v2 +; CHECK-NEXT: vlvgp %v3, %r0, %r0 +; CHECK-NEXT: vrepb %v3, %v3, 15 +; CHECK-NEXT: vslb %v4, %v0, %v3 +; CHECK-NEXT: vslb %v1, %v1, %v3 +; CHECK-NEXT: vsl %v4, %v4, %v3 +; CHECK-NEXT: vo %v2, %v4, %v2 +; CHECK-NEXT: vsl %v1, %v1, %v3 +; CHECK-NEXT: cijlh %r0, 0, .LBB0_3 +; CHECK-NEXT: j .LBB0_4 +; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: ahik %r1, %r0, -128 +; CHECK-NEXT: vlvgp %v2, %r1, %r1 +; CHECK-NEXT: vrepb %v2, %v2, 15 +; CHECK-NEXT: vslb %v1, %v1, %v2 +; CHECK-NEXT: vsl %v2, %v1, %v2 +; CHECK-NEXT: vgbm %v1, 0 +; CHECK-NEXT: cije %r0, 0, .LBB0_4 +; CHECK-NEXT: .LBB0_3: +; CHECK-NEXT: vlr %v0, %v2 +; CHECK-NEXT: .LBB0_4: +; CHECK-NEXT: vst %v1, 16(%r2), 3 +; CHECK-NEXT: vst %v0, 0(%r2), 3 +; CHECK-NEXT: br %r14 + %res = shl i256 %a, %sh + ret i256 %res +} + +; Shift right logical. +define i256 @f2(i256 %a, i256 %sh) { +; CHECK-LABEL: f2: +; CHECK: # %bb.0: +; CHECK-NEXT: vl %v0, 16(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r3), 3 +; CHECK-NEXT: l %r0, 28(%r4) +; CHECK-NEXT: clijhe %r0, 128, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: lhi %r1, 128 +; CHECK-NEXT: sr %r1, %r0 +; CHECK-NEXT: vlvgp %v2, %r1, %r1 +; CHECK-NEXT: vrepb %v2, %v2, 15 +; CHECK-NEXT: vslb %v3, %v1, %v2 +; CHECK-NEXT: vsl %v2, %v3, %v2 +; CHECK-NEXT: vlvgp %v3, %r0, %r0 +; CHECK-NEXT: vrepb %v3, %v3, 15 +; CHECK-NEXT: vsrlb %v4, %v0, %v3 +; CHECK-NEXT: vsrlb %v1, %v1, %v3 +; CHECK-NEXT: vsrl %v4, %v4, %v3 +; CHECK-NEXT: vo %v2, %v4, %v2 +; CHECK-NEXT: vsrl %v1, %v1, %v3 +; CHECK-NEXT: cijlh %r0, 0, .LBB1_3 +; CHECK-NEXT: j .LBB1_4 +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: ahik %r1, %r0, -128 +; CHECK-NEXT: vlvgp %v2, %r1, %r1 +; CHECK-NEXT: vrepb %v2, %v2, 15 +; CHECK-NEXT: vsrlb %v1, %v1, %v2 +; CHECK-NEXT: vsrl %v2, %v1, %v2 +; CHECK-NEXT: vgbm %v1, 0 +; CHECK-NEXT: cije %r0, 0, .LBB1_4 +; CHECK-NEXT: .LBB1_3: +; CHECK-NEXT: vlr %v0, %v2 +; CHECK-NEXT: .LBB1_4: +; CHECK-NEXT: vst %v1, 0(%r2), 3 +; CHECK-NEXT: vst %v0, 16(%r2), 3 +; CHECK-NEXT: br %r14 + %res = lshr i256 %a, %sh + ret i256 %res +} + +; Shift right arithmetic. +define i256 @f3(i256 %a, i256 %sh) { +; CHECK-LABEL: f3: +; CHECK: # %bb.0: +; CHECK-NEXT: vl %v0, 16(%r3), 3 +; CHECK-NEXT: vl %v2, 0(%r3), 3 +; CHECK-NEXT: l %r0, 28(%r4) +; CHECK-NEXT: clijhe %r0, 128, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: lhi %r1, 128 +; CHECK-NEXT: sr %r1, %r0 +; CHECK-NEXT: vlvgp %v1, %r0, %r0 +; CHECK-NEXT: vlvgp %v4, %r1, %r1 +; CHECK-NEXT: vrepb %v3, %v1, 15 +; CHECK-NEXT: vrepb %v4, %v4, 15 +; CHECK-NEXT: vsrab %v1, %v2, %v3 +; CHECK-NEXT: vslb %v2, %v2, %v4 +; CHECK-NEXT: vsl %v2, %v2, %v4 +; CHECK-NEXT: vsrlb %v4, %v0, %v3 +; CHECK-NEXT: vsra %v1, %v1, %v3 +; CHECK-NEXT: vsrl %v3, %v4, %v3 +; CHECK-NEXT: vo %v2, %v3, %v2 +; CHECK-NEXT: cijlh %r0, 0, .LBB2_3 +; CHECK-NEXT: j .LBB2_4 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: vrepib %v1, 127 +; CHECK-NEXT: vsrab %v3, %v2, %v1 +; CHECK-NEXT: ahik %r1, %r0, -128 +; CHECK-NEXT: vsra %v1, %v3, %v1 +; CHECK-NEXT: vlvgp %v3, %r1, %r1 +; CHECK-NEXT: vrepb %v3, %v3, 15 +; CHECK-NEXT: vsrab %v2, %v2, %v3 +; CHECK-NEXT: vsra %v2, %v2, %v3 +; CHECK-NEXT: cije %r0, 0, .LBB2_4 +; CHECK-NEXT: .LBB2_3: +; CHECK-NEXT: vlr %v0, %v2 +; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: vst %v1, 0(%r2), 3 +; CHECK-NEXT: vst %v0, 16(%r2), 3 +; CHECK-NEXT: br %r14 + %res = ashr i256 %a, %sh + ret i256 %res +} -- GitLab From ae978baaf6cc5566036b89ceaadcabb47361ba2f Mon Sep 17 00:00:00 2001 From: John Brawn Date: Wed, 10 Jan 2024 14:32:59 +0000 Subject: [PATCH 332/652] [LoopFlatten] Recognise gep+gep (#72515) Now that InstCombine canonicalises add+gep to gep+gep, LoopFlatten needs to recognise (gep (gep ptr (i*M)), j) as being something it can optimise. --- llvm/include/llvm/IR/PatternMatch.h | 36 +++++ llvm/lib/Transforms/Scalar/LoopFlatten.cpp | 79 ++++++---- .../LoopFlatten/loop-flatten-gep.ll | 137 ++++++++++++++++++ 3 files changed, 225 insertions(+), 27 deletions(-) create mode 100644 llvm/test/Transforms/LoopFlatten/loop-flatten-gep.ll diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h index 447ac0f2aa61..90d99a6031c8 100644 --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -1495,6 +1495,36 @@ struct ThreeOps_match { } }; +/// Matches instructions with Opcode and any number of operands +template struct AnyOps_match { + std::tuple Operands; + + AnyOps_match(const OperandTypes &...Ops) : Operands(Ops...) {} + + // Operand matching works by recursively calling match_operands, matching the + // operands left to right. The first version is called for each operand but + // the last, for which the second version is called. The second version of + // match_operands is also used to match each individual operand. + template + std::enable_if_t match_operands(const Instruction *I) { + return match_operands(I) && match_operands(I); + } + + template + std::enable_if_t match_operands(const Instruction *I) { + return std::get(Operands).match(I->getOperand(Idx)); + } + + template bool match(OpTy *V) { + if (V->getValueID() == Value::InstructionVal + Opcode) { + auto *I = cast(V); + return I->getNumOperands() == sizeof...(OperandTypes) && + match_operands<0, sizeof...(OperandTypes) - 1>(I); + } + return false; + } +}; + /// Matches SelectInst. template inline ThreeOps_match @@ -1611,6 +1641,12 @@ m_Store(const ValueOpTy &ValueOp, const PointerOpTy &PointerOp) { PointerOp); } +/// Matches GetElementPtrInst. +template +inline auto m_GEP(const OperandTypes &...Ops) { + return AnyOps_match(Ops...); +} + //===----------------------------------------------------------------------===// // Matchers for CastInst classes // diff --git a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp index eef94636578d..533cefaf1061 100644 --- a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp +++ b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp @@ -207,6 +207,12 @@ struct FlattenInfo { match(MatchedMul, m_c_Mul(m_Trunc(m_Specific(OuterInductionPHI)), m_Value(MatchedItCount))); + // Matches the pattern ptr+i*M+j, with the two additions being done via GEP. + bool IsGEP = match(U, m_GEP(m_GEP(m_Value(), m_Value(MatchedMul)), + m_Specific(InnerInductionPHI))) && + match(MatchedMul, m_c_Mul(m_Specific(OuterInductionPHI), + m_Value(MatchedItCount))); + if (!MatchedItCount) return false; @@ -224,7 +230,7 @@ struct FlattenInfo { // Look through extends if the IV has been widened. Don't look through // extends if we already looked through a trunc. - if (Widened && IsAdd && + if (Widened && (IsAdd || IsGEP) && (isa(MatchedItCount) || isa(MatchedItCount))) { assert(MatchedItCount->getType() == InnerInductionPHI->getType() && "Unexpected type mismatch in types after widening"); @@ -236,7 +242,7 @@ struct FlattenInfo { LLVM_DEBUG(dbgs() << "Looking for inner trip count: "; InnerTripCount->dump()); - if ((IsAdd || IsAddTrunc) && MatchedItCount == InnerTripCount) { + if ((IsAdd || IsAddTrunc || IsGEP) && MatchedItCount == InnerTripCount) { LLVM_DEBUG(dbgs() << "Found. This sse is optimisable\n"); ValidOuterPHIUses.insert(MatchedMul); LinearIVUses.insert(U); @@ -646,33 +652,40 @@ static OverflowResult checkOverflow(FlattenInfo &FI, DominatorTree *DT, if (OR != OverflowResult::MayOverflow) return OR; - for (Value *V : FI.LinearIVUses) { - for (Value *U : V->users()) { - if (auto *GEP = dyn_cast(U)) { - for (Value *GEPUser : U->users()) { - auto *GEPUserInst = cast(GEPUser); - if (!isa(GEPUserInst) && - !(isa(GEPUserInst) && - GEP == GEPUserInst->getOperand(1))) - continue; - if (!isGuaranteedToExecuteForEveryIteration(GEPUserInst, - FI.InnerLoop)) - continue; - // The IV is used as the operand of a GEP which dominates the loop - // latch, and the IV is at least as wide as the address space of the - // GEP. In this case, the GEP would wrap around the address space - // before the IV increment wraps, which would be UB. - if (GEP->isInBounds() && - V->getType()->getIntegerBitWidth() >= - DL.getPointerTypeSizeInBits(GEP->getType())) { - LLVM_DEBUG( - dbgs() << "use of linear IV would be UB if overflow occurred: "; - GEP->dump()); - return OverflowResult::NeverOverflows; - } - } + auto CheckGEP = [&](GetElementPtrInst *GEP, Value *GEPOperand) { + for (Value *GEPUser : GEP->users()) { + auto *GEPUserInst = cast(GEPUser); + if (!isa(GEPUserInst) && + !(isa(GEPUserInst) && GEP == GEPUserInst->getOperand(1))) + continue; + if (!isGuaranteedToExecuteForEveryIteration(GEPUserInst, FI.InnerLoop)) + continue; + // The IV is used as the operand of a GEP which dominates the loop + // latch, and the IV is at least as wide as the address space of the + // GEP. In this case, the GEP would wrap around the address space + // before the IV increment wraps, which would be UB. + if (GEP->isInBounds() && + GEPOperand->getType()->getIntegerBitWidth() >= + DL.getPointerTypeSizeInBits(GEP->getType())) { + LLVM_DEBUG( + dbgs() << "use of linear IV would be UB if overflow occurred: "; + GEP->dump()); + return true; } } + return false; + }; + + // Check if any IV user is, or is used by, a GEP that would cause UB if the + // multiply overflows. + for (Value *V : FI.LinearIVUses) { + if (auto *GEP = dyn_cast(V)) + if (GEP->getNumIndices() == 1 && CheckGEP(GEP, GEP->getOperand(1))) + return OverflowResult::NeverOverflows; + for (Value *U : V->users()) + if (auto *GEP = dyn_cast(U)) + if (CheckGEP(GEP, V)) + return OverflowResult::NeverOverflows; } return OverflowResult::MayOverflow; @@ -778,6 +791,18 @@ static bool DoFlattenLoopPair(FlattenInfo &FI, DominatorTree *DT, LoopInfo *LI, OuterValue = Builder.CreateTrunc(FI.OuterInductionPHI, V->getType(), "flatten.trunciv"); + if (auto *GEP = dyn_cast(V)) { + // Replace the GEP with one that uses OuterValue as the offset. + auto *InnerGEP = cast(GEP->getOperand(0)); + Value *Base = InnerGEP->getOperand(0); + // When the base of the GEP doesn't dominate the outer induction phi then + // we need to insert the new GEP where the old GEP was. + if (!DT->dominates(Base, &*Builder.GetInsertPoint())) + Builder.SetInsertPoint(cast(V)); + OuterValue = Builder.CreateGEP(GEP->getSourceElementType(), Base, + OuterValue, "flatten." + V->getName()); + } + LLVM_DEBUG(dbgs() << "Replacing: "; V->dump(); dbgs() << "with: "; OuterValue->dump()); V->replaceAllUsesWith(OuterValue); diff --git a/llvm/test/Transforms/LoopFlatten/loop-flatten-gep.ll b/llvm/test/Transforms/LoopFlatten/loop-flatten-gep.ll new file mode 100644 index 000000000000..f4b8ea97237f --- /dev/null +++ b/llvm/test/Transforms/LoopFlatten/loop-flatten-gep.ll @@ -0,0 +1,137 @@ +; RUN: opt < %s -S -passes='loop(loop-flatten),verify' -verify-loop-info -verify-dom-info -verify-scev | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + +; We should be able to flatten the loops and turn the two geps into one. +; CHECK-LABEL: test1 +define void @test1(i32 %N, ptr %A) { +entry: + %cmp3 = icmp ult i32 0, %N + br i1 %cmp3, label %for.outer.preheader, label %for.end + +; CHECK-LABEL: for.outer.preheader: +; CHECK: %flatten.tripcount = mul i32 %N, %N +for.outer.preheader: + br label %for.inner.preheader + +; CHECK-LABEL: for.inner.preheader: +; CHECK: %flatten.arrayidx = getelementptr i32, ptr %A, i32 %i +for.inner.preheader: + %i = phi i32 [ 0, %for.outer.preheader ], [ %inc2, %for.outer ] + br label %for.inner + +; CHECK-LABEL: for.inner: +; CHECK: store i32 0, ptr %flatten.arrayidx, align 4 +; CHECK: br label %for.outer +for.inner: + %j = phi i32 [ 0, %for.inner.preheader ], [ %inc1, %for.inner ] + %mul = mul i32 %i, %N + %gep = getelementptr inbounds i32, ptr %A, i32 %mul + %arrayidx = getelementptr inbounds i32, ptr %gep, i32 %j + store i32 0, ptr %arrayidx, align 4 + %inc1 = add nuw i32 %j, 1 + %cmp2 = icmp ult i32 %inc1, %N + br i1 %cmp2, label %for.inner, label %for.outer + +; CHECK-LABEL: for.outer: +; CHECK: %cmp1 = icmp ult i32 %inc2, %flatten.tripcount +for.outer: + %inc2 = add i32 %i, 1 + %cmp1 = icmp ult i32 %inc2, %N + br i1 %cmp1, label %for.inner.preheader, label %for.end.loopexit + +for.end.loopexit: + br label %for.end + +for.end: + ret void +} + +; We can flatten, but the flattened gep has to be inserted after the load it +; depends on. +; CHECK-LABEL: test2 +define void @test2(i32 %N, ptr %A) { +entry: + %cmp3 = icmp ult i32 0, %N + br i1 %cmp3, label %for.outer.preheader, label %for.end + +; CHECK-LABEL: for.outer.preheader: +; CHECK: %flatten.tripcount = mul i32 %N, %N +for.outer.preheader: + br label %for.inner.preheader + +; CHECK-LABEL: for.inner.preheader: +; CHECK-NOT: getelementptr i32, ptr %ptr, i32 %i +for.inner.preheader: + %i = phi i32 [ 0, %for.outer.preheader ], [ %inc2, %for.outer ] + br label %for.inner + +; CHECK-LABEL: for.inner: +; CHECK: %flatten.arrayidx = getelementptr i32, ptr %ptr, i32 %i +; CHECK: store i32 0, ptr %flatten.arrayidx, align 4 +; CHECK: br label %for.outer +for.inner: + %j = phi i32 [ 0, %for.inner.preheader ], [ %inc1, %for.inner ] + %ptr = load volatile ptr, ptr %A, align 4 + %mul = mul i32 %i, %N + %gep = getelementptr inbounds i32, ptr %ptr, i32 %mul + %arrayidx = getelementptr inbounds i32, ptr %gep, i32 %j + store i32 0, ptr %arrayidx, align 4 + %inc1 = add nuw i32 %j, 1 + %cmp2 = icmp ult i32 %inc1, %N + br i1 %cmp2, label %for.inner, label %for.outer + +; CHECK-LABEL: for.outer: +; CHECK: %cmp1 = icmp ult i32 %inc2, %flatten.tripcount +for.outer: + %inc2 = add i32 %i, 1 + %cmp1 = icmp ult i32 %inc2, %N + br i1 %cmp1, label %for.inner.preheader, label %for.end.loopexit + +for.end.loopexit: + br label %for.end + +for.end: + ret void +} + +; We can't flatten if the gep offset is smaller than the pointer size. +; CHECK-LABEL: test3 +define void @test3(i16 %N, ptr %A) { +entry: + %cmp3 = icmp ult i16 0, %N + br i1 %cmp3, label %for.outer.preheader, label %for.end + +for.outer.preheader: + br label %for.inner.preheader + +; CHECK-LABEL: for.inner.preheader: +; CHECK-NOT: getelementptr i32, ptr %A, i16 %i +for.inner.preheader: + %i = phi i16 [ 0, %for.outer.preheader ], [ %inc2, %for.outer ] + br label %for.inner + +; CHECK-LABEL: for.inner: +; CHECK-NOT: getelementptr i32, ptr %A, i16 %i +; CHECK: br i1 %cmp2, label %for.inner, label %for.outer +for.inner: + %j = phi i16 [ 0, %for.inner.preheader ], [ %inc1, %for.inner ] + %mul = mul i16 %i, %N + %gep = getelementptr inbounds i32, ptr %A, i16 %mul + %arrayidx = getelementptr inbounds i32, ptr %gep, i16 %j + store i32 0, ptr %arrayidx, align 4 + %inc1 = add nuw i16 %j, 1 + %cmp2 = icmp ult i16 %inc1, %N + br i1 %cmp2, label %for.inner, label %for.outer + +for.outer: + %inc2 = add i16 %i, 1 + %cmp1 = icmp ult i16 %inc2, %N + br i1 %cmp1, label %for.inner.preheader, label %for.end.loopexit + +for.end.loopexit: + br label %for.end + +for.end: + ret void +} -- GitLab From 9bde5becb44ea071f5e1fa1f5d4071dc8788b18c Mon Sep 17 00:00:00 2001 From: HaohaiWen Date: Wed, 10 Jan 2024 22:34:18 +0800 Subject: [PATCH 333/652] [BranchFolding][SEH] Add test to track SEH CFG optimization (#77598) This test tracks BranchFolding pass which removes fall through jump and leaves landing-pad to be machine basic block of no predecessors. It would raise bug as introduced in #77441. --- .../X86/branchfolding-landingpad-cfg.mir | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 llvm/test/CodeGen/X86/branchfolding-landingpad-cfg.mir diff --git a/llvm/test/CodeGen/X86/branchfolding-landingpad-cfg.mir b/llvm/test/CodeGen/X86/branchfolding-landingpad-cfg.mir new file mode 100644 index 000000000000..a494701c2a39 --- /dev/null +++ b/llvm/test/CodeGen/X86/branchfolding-landingpad-cfg.mir @@ -0,0 +1,49 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=x86_64-pc-windows-msvc -run-pass=branch-folder -o - %s | FileCheck %s +--- +name: main +body: | + ; CHECK-LABEL: name: main + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x7ffff800), %bb.3(0x00000800) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: RET 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (machine-block-address-taken, landing-pad, ehfunclet-entry): + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: CLEANUPRET + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3 (landing-pad, ehfunclet-entry): + ; CHECK-NEXT: CLEANUPRET + bb.0: + successors: %bb.1(0x7ffff800), %bb.5(0x00000800) + JMP_1 %bb.1 + + bb.1: + successors: %bb.2(0x7ffff800), %bb.4(0x00000800) + + JMP_1 %bb.2 + + bb.2: + successors: %bb.3(0x7ffff800), %bb.4(0x00000800) + + JMP_1 %bb.3 + + bb.3: + successors: %bb.6(0x7ffff800) + + JMP_1 %bb.6 + + bb.4 (machine-block-address-taken, landing-pad, ehfunclet-entry): + successors: %bb.5(0x80000000) + CLEANUPRET + + bb.5 (landing-pad, ehfunclet-entry): + CLEANUPRET + + bb.6: + RET 0 +... -- GitLab From 113bce0c79fe5cc2b949949c5d96b7f679524b6e Mon Sep 17 00:00:00 2001 From: Prathamesh Tagore <63031630+meshtag@users.noreply.github.com> Date: Wed, 10 Jan 2024 20:25:27 +0530 Subject: [PATCH 334/652] [mlir][tensor] Fold producer linalg transpose with consumer tensor pack (#75658) Successor to https://github.com/llvm/llvm-project/pull/74206 Partial fix to https://github.com/openxla/iree/issues/15367 --- .../Transforms/PackAndUnpackPatterns.cpp | 44 ++++- .../Tensor/fold-into-pack-and-unpack.mlir | 177 ++++++++++++++++++ 2 files changed, 220 insertions(+), 1 deletion(-) diff --git a/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp b/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp index cfd838e85c1b..8ab69d8c59b4 100644 --- a/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp +++ b/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp @@ -9,6 +9,7 @@ #include "mlir/Dialect/Linalg/IR/Linalg.h" #include "mlir/Dialect/Tensor/IR/Tensor.h" #include "mlir/Dialect/Tensor/Transforms/Transforms.h" +#include "mlir/Dialect/Utils/IndexingUtils.h" #include "mlir/IR/PatternMatch.h" #include "llvm/Support/Debug.h" @@ -223,11 +224,52 @@ struct FoldProducerPackWithConsumerLinalgTransposeOp return success(); } }; + +/// Fold 'transpose' -> 'pack' into 'pack' since 'pack' already has transpose +/// semantics. +struct FoldConsumerPackWithProducerLinalgTransposeOp + : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(PackOp packOp, + PatternRewriter &rewriter) const override { + auto transposeOp = packOp.getSource().getDefiningOp(); + + if (!transposeOp) + return failure(); + + auto transposePermutation = transposeOp.getPermutation(); + auto outerDimsPerm = packOp.getOuterDimsPerm(); + auto innerDimsPos = packOp.getInnerDimsPos(); + SmallVector newInnerDimsPosVec; + SmallVector newOuterDimsPermVec = + llvm::to_vector(transposePermutation); + + if (!outerDimsPerm.empty()) + applyPermutationToVector(newOuterDimsPermVec, outerDimsPerm); + + // Can't use applyPermutationToVector for newInnerDimsPosVec since input and + // permutation rank won't necessarily be equal in all cases. + for (auto dim : innerDimsPos) + newInnerDimsPosVec.push_back(transposePermutation[dim]); + + Value output = packOp.createDestinationTensor( + rewriter, packOp.getLoc(), transposeOp.getOperand(0), + packOp.getMixedTiles(), newInnerDimsPosVec, newOuterDimsPermVec); + + rewriter.replaceOpWithNewOp( + packOp, transposeOp.getOperand(0), output, newInnerDimsPosVec, + packOp.getMixedTiles(), packOp.getPaddingValue(), newOuterDimsPermVec); + + return success(); + } +}; } // namespace void populateFoldIntoPackAndUnpackPatterns(RewritePatternSet &patterns) { patterns.insert( + FoldProducerPackWithConsumerLinalgTransposeOp, + FoldConsumerPackWithProducerLinalgTransposeOp>( patterns.getContext()); } diff --git a/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir b/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir index e9e3ca9c0087..6003135b66b1 100644 --- a/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir +++ b/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir @@ -345,3 +345,180 @@ func.func @tensor_pack_linalg_transpose_fold_dynamic_outer_dims_tile_dims_tile_s // CHECK: %[[PACK:.+]] = tensor.pack %[[ARG0]] outer_dims_perm = [2, 1, 3, 0] inner_dims_pos = [3, 1, 2] inner_tiles = [%[[ARG3]], %[[ARG1]], %[[ARG2]]] into %[[INIT]] : tensor -> tensor // CHECK: return %[[PACK]] : tensor // CHECK: } + +// ----- + +func.func @linalg_transpose_tensor_pack_fold(%arg0: tensor<56x57x1x64xf32>) -> tensor<1x57x56x2x32xf32> { + %0 = tensor.empty() : tensor<1x56x57x64xf32> + %transposed = linalg.transpose + ins(%arg0 : tensor<56x57x1x64xf32>) + outs(%0 : tensor<1x56x57x64xf32>) + permutation = [2, 0, 1, 3] + + %1 = tensor.empty() : tensor<1x57x56x2x32xf32> + %pack = tensor.pack %transposed + outer_dims_perm = [0, 2, 1, 3] + inner_dims_pos = [3] + inner_tiles = [32] + into %1 : tensor<1x56x57x64xf32> -> tensor<1x57x56x2x32xf32> + return %pack : tensor<1x57x56x2x32xf32> +} +//CHECK-LABEL: func @linalg_transpose_tensor_pack_fold( +// CHECK-SAME: %[[ARG0:.+]]: tensor<56x57x1x64xf32>) +// CHECK: %[[INIT:.+]] = tensor.empty() : tensor<1x57x56x2x32xf32> +// CHECK: %[[PACK:.+]] = tensor.pack %[[ARG0]] +// CHECK-SAME: outer_dims_perm = [2, 1, 0, 3] +// CHECK-SAME: inner_dims_pos = [3] inner_tiles = [32] +// CHECK-SAME: into %[[INIT]] +// CHECK: return %[[PACK]] + +// ----- + +func.func @linalg_transpose_tensor_pack_fold_with_padding(%arg0: tensor<56x57x1x55xf32>, %padding: f32) -> tensor<1x57x56x2x32xf32> { + %0 = tensor.empty() : tensor<1x56x57x55xf32> + %transpose = linalg.transpose + ins(%arg0 : tensor<56x57x1x55xf32>) + outs(%0 : tensor<1x56x57x55xf32>) + permutation = [2, 0, 1, 3] + + %1 = tensor.empty() : tensor<1x57x56x2x32xf32> + %pack = tensor.pack %transpose padding_value(%padding : f32) + outer_dims_perm = [0, 2, 1, 3] + inner_dims_pos = [3] + inner_tiles = [32] + into %1 : tensor<1x56x57x55xf32> -> tensor<1x57x56x2x32xf32> + return %pack : tensor<1x57x56x2x32xf32> +} +//CHECK-LABEL: func @linalg_transpose_tensor_pack_fold_with_padding( +// CHECK-SAME: %[[ARG0:.+]]: tensor<56x57x1x55xf32>, %[[PADDING:.+]]: f32) +// CHECK: %[[INIT:.+]] = tensor.empty() : tensor<1x57x56x2x32xf32> +// CHECK: %[[PACK:.+]] = tensor.pack %[[ARG0]] padding_value(%[[PADDING]] : f32) +// CHECK-SAME: outer_dims_perm = [2, 1, 0, 3] +// CHECK-SAME: inner_dims_pos = [3] inner_tiles = [32] +// CHECK-SAME: into %[[INIT]] +// CHECK: return %[[PACK]] + +// ----- + +func.func @linalg_transpose_tensor_pack_fold_no_outer_dims_perm(%arg0: tensor<56x57x1x64xf32>) -> tensor<1x56x57x2x32xf32> { + %0 = tensor.empty() : tensor<1x56x57x64xf32> + %transposed = linalg.transpose + ins(%arg0 : tensor<56x57x1x64xf32>) + outs(%0 : tensor<1x56x57x64xf32>) + permutation = [2, 0, 1, 3] + + %1 = tensor.empty() : tensor<1x56x57x2x32xf32> + %pack = tensor.pack %transposed + inner_dims_pos = [3] + inner_tiles = [32] + into %1 : tensor<1x56x57x64xf32> -> tensor<1x56x57x2x32xf32> + return %pack : tensor<1x56x57x2x32xf32> +} +//CHECK-LABEL: func @linalg_transpose_tensor_pack_fold_no_outer_dims_perm( +// CHECK-SAME: %[[ARG0:.+]]: tensor<56x57x1x64xf32>) +// CHECK: %[[INIT:.+]] = tensor.empty() : tensor<1x56x57x2x32xf32> +// CHECK: %[[PACK:.+]] = tensor.pack %[[ARG0]] +// CHECK-SAME: outer_dims_perm = [2, 0, 1, 3] +// CHECK-SAME: inner_dims_pos = [3] inner_tiles = [32] +// CHECK-SAME: into %[[INIT]] +// CHECK: return %[[PACK]] + +// ----- + +func.func @linalg_transpose_tensor_pack_fold_complex_inner_dims_change(%arg0: tensor<25x30x35x40xf32>, %transpose_dest: tensor<35x40x25x30xf32>, %pack_dest: tensor<3x35x5x8x5x10x5xf32>) -> tensor<3x35x5x8x5x10x5xf32> { + %transposed = linalg.transpose + ins(%arg0 : tensor<25x30x35x40xf32>) + outs(%transpose_dest : tensor<35x40x25x30xf32>) + permutation = [2, 3, 0, 1] + + %pack = tensor.pack %transposed + outer_dims_perm = [3, 0, 2, 1] + inner_dims_pos = [1, 3, 2] + inner_tiles = [5, 10, 5] + into %pack_dest : tensor<35x40x25x30xf32> -> tensor<3x35x5x8x5x10x5xf32> + return %pack : tensor<3x35x5x8x5x10x5xf32> +} +//CHECK-LABEL: func.func @linalg_transpose_tensor_pack_fold_complex_inner_dims_change( +// CHECK-SAME: %[[ARG0:.+]]: tensor<25x30x35x40xf32>, +// CHECK-SAME: %[[ARG1:.+]]: tensor<35x40x25x30xf32>, +// CHECK-SAME: %[[ARG2:.+]]: tensor<3x35x5x8x5x10x5xf32>) -> tensor<3x35x5x8x5x10x5xf32> { +// CHECK: %[[VAL0:.+]] = tensor.empty() : tensor<3x35x5x8x5x10x5xf32> +// CHECK: %[[PACK:.+]] = tensor.pack %[[ARG0]] +// CHECK-SAME: outer_dims_perm = [1, 2, 0, 3] +// CHECK-SAME: inner_dims_pos = [3, 1, 0] +// CHECK-SAME: inner_tiles = [5, 10, 5] +// CHECK-SAME: into %[[VAL0]] +// CHECK: return %[[PACK]] + +// ----- + +func.func @linalg_transpose_tensor_pack_fold_dynamic_outer_dims_tile_dims_tile_sizes(%arg0: tensor, %transpose_dest: tensor, %pack_dest: tensor, %tile_p : index, %tile_q : index, %tile_r : index) -> tensor { + %transposed = linalg.transpose + ins(%arg0 : tensor) + outs(%transpose_dest : tensor) + permutation = [2, 3, 0, 1] + + %pack = tensor.pack %transposed + outer_dims_perm = [3, 0, 2, 1] + inner_dims_pos = [1, 3, 2] + inner_tiles = [%tile_p, %tile_q, %tile_r] + into %pack_dest : tensor -> tensor + return %pack : tensor +} +// CHECK: #[[map:.+]] = affine_map<()[s0, s1] -> (s0 ceildiv s1)> +//CHECK-LABEL: func.func @linalg_transpose_tensor_pack_fold_dynamic_outer_dims_tile_dims_tile_sizes( +// CHECK-SAME: %[[ARG0:.+]]: tensor, %[[ARG1:.+]]: tensor, +// CHECK-SAME: %[[ARG2:.+]]: tensor, %[[ARG3:.+]]: index, %[[ARG4:.+]]: index, %[[ARG5:.+]]: index) -> tensor { +// CHECK: %[[C0:.+]] = arith.constant 0 : index +// CHECK: %[[C1:.+]] = arith.constant 1 : index +// CHECK: %[[C2:.+]] = arith.constant 2 : index +// CHECK: %[[C3:.+]] = arith.constant 3 : index +// CHECK: %[[DIM:.+]] = tensor.dim %[[ARG0]], %[[C0]] : tensor +// CHECK: %[[DIM0:.+]] = tensor.dim %[[ARG0]], %[[C1]] : tensor +// CHECK: %[[DIM1:.+]] = tensor.dim %[[ARG0]], %[[C2]] : tensor +// CHECK: %[[DIM2:.+]] = tensor.dim %[[ARG0]], %[[C3]] : tensor +// CHECK: %[[VAL0:.+]] = affine.apply #[[map:.+]]()[%[[DIM2]], %[[ARG3]]] +// CHECK: %[[VAL1:.+]] = affine.apply #[[map:.+]]()[%[[DIM0]], %[[ARG4]]] +// CHECK: %[[VAL2:.+]] = affine.apply #[[map:.+]]()[%[[DIM]], %[[ARG5]]] +// CHECK: %[[VAL3:.+]] = tensor.empty(%[[VAL1]], %[[DIM1]], %[[VAL2]], %[[VAL0]], %[[ARG3]], %[[ARG4]], %[[ARG5]]) : tensor +// CHECK: %[[PACK:.+]] = tensor.pack %[[ARG0]] outer_dims_perm = [1, 2, 0, 3] inner_dims_pos = [3, 1, 0] inner_tiles = [%[[ARG3]], %[[ARG4]], %[[ARG5]]] into %[[VAL3]] : tensor -> tensor +// CHECK: return %[[PACK]] : tensor + +// ----- + +func.func @linalg_transpose_tensor_pack_multiple_tiles(%arg0: tensor) -> tensor<32x?x64x16x2xbf16> { + %c0 = arith.constant 0 : index + %cst = arith.constant 0.000000e+00 : bf16 + %dim = tensor.dim %arg0, %c0 : tensor + + %0 = tensor.empty(%dim) : tensor<32x128x?xbf16> + %transposed = linalg.transpose + ins(%arg0 : tensor) + outs(%0 : tensor<32x128x?xbf16>) + permutation = [1, 2, 0] + + %2 = tensor.empty(%dim) : tensor<32x?x64x16x2xbf16> + %pack = tensor.pack %transposed + padding_value(%cst : bf16) + outer_dims_perm = [0, 2, 1] + inner_dims_pos = [2, 1] + inner_tiles = [16, 2] + into %2 : tensor<32x128x?xbf16> -> tensor<32x?x64x16x2xbf16> + return %pack : tensor<32x?x64x16x2xbf16> +} +// CHECK: #[[map:.+]] = affine_map<()[s0] -> (s0 ceildiv 16)> +//CHECK-LABEL: func.func @linalg_transpose_tensor_pack_multiple_tiles( +// CHECK-SAME: %[[ARG0:.+]]: tensor) -> tensor<32x?x64x16x2xbf16> { +// CHECK: %[[C0:.+]] = arith.constant 0 : index +// CHECK: %[[CST:.+]] = arith.constant 0.000000e+00 : bf16 +// CHECK: %[[DIM:.+]] = tensor.dim %[[ARG0]], %[[C0]] : tensor +// CHECK: %[[VAL0:.+]] = affine.apply #[[map:.+]]()[%[[DIM]]] +// CHECK: %[[VAL1:.+]] = tensor.empty(%[[VAL0]]) : tensor<32x?x64x16x2xbf16> +// CHECK: %[[PACK:.+]] = tensor.pack %[[ARG0]] +// CHECK-SAME: padding_value(%[[CST]] : bf16) +// CHECK-SAME: outer_dims_perm = [1, 0, 2] +// CHECK-SAME: inner_dims_pos = [0, 2] +// CHECK-SAME: inner_tiles = [16, 2] +// CHECK-SAME: into %[[VAL1]] : tensor -> tensor<32x?x64x16x2xbf16> +// CHECK: return %[[PACK]] : tensor<32x?x64x16x2xbf16> +// CHECK: } -- GitLab From 45be680b1ae51866568b1794fa6f59190042ee92 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 10 Jan 2024 22:57:17 +0800 Subject: [PATCH 335/652] [SimplifyCFG] Emit `rotl` directly in `ReduceSwitchRange` (#77603) This patch emits `ROTL(Cond, BitWidth - Shift)` directly in `ReduceSwitchRange`. This should give better codegen because `SimplifyDemandedBits` will break the rotation patterns in the original form. See also https://github.com/llvm/llvm-project/pull/73441 and the IR diff https://github.com/dtcxzyw/llvm-opt-benchmark/pull/115/files. This patch should cover most of cases handled by #73441. --- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 13 +++-- .../Transforms/SimplifyCFG/rangereduce.ll | 50 ++++++++----------- 2 files changed, 26 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 61d891d65346..7515e539e7fb 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -6919,18 +6919,17 @@ static bool ReduceSwitchRange(SwitchInst *SI, IRBuilder<> &Builder, auto *Ty = cast(SI->getCondition()->getType()); Builder.SetInsertPoint(SI); - auto *ShiftC = ConstantInt::get(Ty, Shift); - auto *Sub = Builder.CreateSub(SI->getCondition(), ConstantInt::get(Ty, Base)); - auto *LShr = Builder.CreateLShr(Sub, ShiftC); - auto *Shl = Builder.CreateShl(Sub, Ty->getBitWidth() - Shift); - auto *Rot = Builder.CreateOr(LShr, Shl); + Value *Sub = + Builder.CreateSub(SI->getCondition(), ConstantInt::get(Ty, Base)); + Value *Rot = Builder.CreateIntrinsic( + Ty, Intrinsic::fshl, + {Sub, Sub, ConstantInt::get(Ty, Ty->getBitWidth() - Shift)}); SI->replaceUsesOfWith(SI->getCondition(), Rot); for (auto Case : SI->cases()) { auto *Orig = Case.getCaseValue(); auto Sub = Orig->getValue() - APInt(Ty->getBitWidth(), Base); - Case.setValue( - cast(ConstantInt::get(Ty, Sub.lshr(ShiftC->getValue())))); + Case.setValue(cast(ConstantInt::get(Ty, Sub.lshr(Shift)))); } return true; } diff --git a/llvm/test/Transforms/SimplifyCFG/rangereduce.ll b/llvm/test/Transforms/SimplifyCFG/rangereduce.ll index b1a3802a2bb5..d47bf5f95418 100644 --- a/llvm/test/Transforms/SimplifyCFG/rangereduce.ll +++ b/llvm/test/Transforms/SimplifyCFG/rangereduce.ll @@ -7,13 +7,11 @@ target datalayout = "e-n32" define i32 @test1(i32 %a) { ; CHECK-LABEL: @test1( ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 97 -; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2 -; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30 -; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 4 -; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 30) +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 4 +; CHECK-NEXT: br i1 [[TMP3]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.test1, i32 0, i32 [[TMP4]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.test1, i32 0, i32 [[TMP2]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 ; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK: common.ret: @@ -183,13 +181,11 @@ three: define i32 @test6(i32 %a) optsize { ; CHECK-LABEL: @test6( ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], -109 -; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2 -; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30 -; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 4 -; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 30) +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 4 +; CHECK-NEXT: br i1 [[TMP3]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.test6, i32 0, i32 [[TMP4]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.test6, i32 0, i32 [[TMP2]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 ; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK: common.ret: @@ -218,15 +214,13 @@ define i8 @test7(i8 %a) optsize { ; CHECK-LABEL: @test7( ; CHECK-NEXT: common.ret: ; CHECK-NEXT: [[TMP0:%.*]] = sub i8 [[A:%.*]], -36 -; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[TMP0]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = shl i8 [[TMP0]], 6 -; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 4 -; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i8 [[TMP3]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.fshl.i8(i8 [[TMP0]], i8 [[TMP0]], i8 6) +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 4 +; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i8 [[TMP1]] to i32 ; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i32 [[SWITCH_CAST]], 8 ; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i32 -943228976, [[SWITCH_SHIFTAMT]] ; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i32 [[SWITCH_DOWNSHIFT]] to i8 -; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[TMP4]], i8 [[SWITCH_MASKED]], i8 -93 +; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[TMP2]], i8 [[SWITCH_MASKED]], i8 -93 ; CHECK-NEXT: ret i8 [[COMMON_RET_OP]] ; switch i8 %a, label %def [ @@ -250,13 +244,11 @@ three: define i32 @test8(i32 %a) optsize { ; CHECK-LABEL: @test8( ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 97 -; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2 -; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30 -; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 5 -; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 30) +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 5 +; CHECK-NEXT: br i1 [[TMP3]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr @switch.table.test8, i32 0, i32 [[TMP4]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr @switch.table.test8, i32 0, i32 [[TMP2]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 ; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK: common.ret: @@ -284,13 +276,11 @@ three: define i32 @test9(i32 %a) { ; CHECK-LABEL: @test9( ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 6 -; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 31 -; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 8 -; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 31) +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 8 +; CHECK-NEXT: br i1 [[TMP3]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.test9, i32 0, i32 [[TMP4]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.test9, i32 0, i32 [[TMP2]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 ; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK: common.ret: -- GitLab From fef2fc3400eb5a22a5ccc96bd3862bec0058d305 Mon Sep 17 00:00:00 2001 From: Visoiu Mistrih Francis <890283+francisvm@users.noreply.github.com> Date: Wed, 10 Jan 2024 06:59:38 -0800 Subject: [PATCH 336/652] [TableGen] Support non-def operators in !getdagop (#77531) `!getdagop` expects the dag operator to be a def, and errors out if it's not. While that's true in most cases, when multiclasses are involved, the late resolution of the dag operator can result in it not being a def yet, but still have a proper type, wich is required to check against the optional parameter Ty in `!getdagop`. e.g, in the following dag: ``` (!cast(TestInstructionAndPattern::NAME) foo) ``` the operator is a UnOpInit, but all we need here is to check its type. This fixes a bug where !getdagop is used to query the dag operator that is dependent on the multiclass, which is not yet resolved to a def. Once the folding is performed, the field becomes a record that can be queried. --- llvm/lib/TableGen/Record.cpp | 15 ++++++++------- llvm/test/TableGen/getsetop.td | 30 ++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 7 deletions(-) diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp index aa981fdab4b3..2b3e8a0c7f84 100644 --- a/llvm/lib/TableGen/Record.cpp +++ b/llvm/lib/TableGen/Record.cpp @@ -923,15 +923,16 @@ Init *UnOpInit::Fold(Record *CurRec, bool IsFinal) const { case GETDAGOP: if (DagInit *Dag = dyn_cast(LHS)) { - DefInit *DI = DefInit::get(Dag->getOperatorAsDef({})); - if (!DI->getType()->typeIsA(getType())) { + // TI is not necessarily a def due to the late resolution in multiclasses, + // but has to be a TypedInit. + auto *TI = cast(Dag->getOperator()); + if (!TI->getType()->typeIsA(getType())) { PrintFatalError(CurRec->getLoc(), - Twine("Expected type '") + - getType()->getAsString() + "', got '" + - DI->getType()->getAsString() + "' in: " + - getAsString() + "\n"); + Twine("Expected type '") + getType()->getAsString() + + "', got '" + TI->getType()->getAsString() + + "' in: " + getAsString() + "\n"); } else { - return DI; + return Dag->getOperator(); } } break; diff --git a/llvm/test/TableGen/getsetop.td b/llvm/test/TableGen/getsetop.td index 0a91e1b2a583..aac644fe34cb 100644 --- a/llvm/test/TableGen/getsetop.td +++ b/llvm/test/TableGen/getsetop.td @@ -8,6 +8,7 @@ // RUN: not llvm-tblgen -DERROR7 %s 2>&1 | FileCheck --check-prefix=ERROR7 %s // RUN: not llvm-tblgen -DERROR8 %s 2>&1 | FileCheck --check-prefix=ERROR8 %s // RUN: not llvm-tblgen -DERROR9 %s 2>&1 | FileCheck --check-prefix=ERROR9 %s +// RUN: not llvm-tblgen -DERROR10 %s 2>&1 | FileCheck --check-prefix=ERROR10 %s // !setop and !getop are deprecated in favor of !setdagop and !getdagop. // Two tests retain the old names just to be sure they are still supported. @@ -148,3 +149,32 @@ def test { dag orig_out_of_range = !setdagarg(orig, foo, (foo qux:$a)); #endif } + +// Copy a list (Predicates) that is a field in a dag operator +// (TestInstruction), which is defined in the same multiclass +// (TestInstructionAndPattern) as the destination of the copy +// (TestPattern::Predicates). +class TestInstruction _Predicates> { + list Predicates = _Predicates; +} +#ifdef ERROR10 +class OtherTestInstruction _Predicates> { + list Predicates = _Predicates; +} +// ERROR10: error: Expected type 'OtherTestInstruction', got 'TestInstruction' +class TestPattern { + list Predicates = !getdagop(D).Predicates; +} +#else +class TestPattern { + list Predicates = !getdagop(D).Predicates; +} +#endif + +multiclass TestInstructionAndPattern Predicates> { + def NAME : TestInstruction; + def : TestPattern<(!cast(NAME) foo)>; +} +// CHECK: def testInst0 { // TestInstruction +// CHECK-NEXT: list Predicates = [7]; +defm testInst0 : TestInstructionAndPattern<[7]>; -- GitLab From 79aa77626770c91badd7c9ba9d26e55a28d34416 Mon Sep 17 00:00:00 2001 From: Boian Petkantchin Date: Wed, 10 Jan 2024 07:01:16 -0800 Subject: [PATCH 337/652] [mlir][mesh] Add lowering of process multi-index op (#77490) * Rename mesh.process_index -> mesh.process_multi_index. * Add mesh.process_linear_index op. * Add lowering of mesh.process_multi_index into an expression using mesh.process_linear_index, mesh.cluster_shape and affine.delinearize_index. This is useful to lower mesh ops and prepare them for further lowering where the runtime may have only the linear index of a device/process. For example in MPI we have a rank (linear index) in a communicator. --- mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td | 32 ++++++- .../mlir/Dialect/Mesh/Transforms/Transforms.h | 26 ++++++ mlir/lib/Dialect/Mesh/IR/MeshOps.cpp | 33 ++++++-- .../Dialect/Mesh/Transforms/CMakeLists.txt | 2 + .../Mesh/Transforms/Simplifications.cpp | 2 +- .../Dialect/Mesh/Transforms/Spmdization.cpp | 4 +- .../Dialect/Mesh/Transforms/Transforms.cpp | 84 +++++++++++++++++++ mlir/test/Dialect/Mesh/invalid.mlir | 30 ++++--- mlir/test/Dialect/Mesh/ops.mlir | 31 ++++--- .../Mesh/process-multi-index-op-lowering.mlir | 23 +++++ .../Dialect/Mesh/resharding-spmdization.mlir | 4 +- mlir/test/lib/Dialect/Mesh/CMakeLists.txt | 1 + .../Mesh/TestProcessMultiIndexOpLowering.cpp | 55 ++++++++++++ mlir/tools/mlir-opt/mlir-opt.cpp | 2 + 14 files changed, 291 insertions(+), 38 deletions(-) create mode 100644 mlir/include/mlir/Dialect/Mesh/Transforms/Transforms.h create mode 100644 mlir/lib/Dialect/Mesh/Transforms/Transforms.cpp create mode 100644 mlir/test/Dialect/Mesh/process-multi-index-op-lowering.mlir create mode 100644 mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp diff --git a/mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td b/mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td index f459077ea120..a9068562f5c9 100644 --- a/mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td +++ b/mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td @@ -96,7 +96,8 @@ def Mesh_ClusterOp : Mesh_Op<"cluster", [Symbol]> { let hasVerifier = 1; } -def Mesh_ClusterShapeOp : Mesh_Op<"cluster_shape", [Pure, DeclareOpInterfaceMethods]> { +def Mesh_ClusterShapeOp : Mesh_Op<"cluster_shape", [ + Pure, DeclareOpInterfaceMethods]> { let summary = "Get the shape of the cluster."; let arguments = (ins FlatSymbolRefAttr:$mesh, @@ -209,11 +210,15 @@ def Mesh_ShardOp : Mesh_Op<"shard", [Pure, SameOperandsAndResultType]> { }]; } -def Mesh_ProcessIndexOp : Mesh_Op<"process_index", [Pure, DeclareOpInterfaceMethods]> { - let summary = "Get the index of current device along specified mesh axis."; +def Mesh_ProcessMultiIndexOp : Mesh_Op<"process_multi_index", [ + Pure, + DeclareOpInterfaceMethods +]> { + let summary = "Get the multi index of current device along specified mesh axes."; let description = [{ It is used in the SPMD format of IR. The `axes` mush be non-negative and less than the total number of mesh axes. + If the axes are empty then get the index along all axes. }]; let arguments = (ins FlatSymbolRefAttr:$mesh, @@ -232,6 +237,27 @@ def Mesh_ProcessIndexOp : Mesh_Op<"process_index", [Pure, DeclareOpInterfaceMeth ]; } +def Mesh_ProcessLinearIndexOp : Mesh_Op<"process_linear_index", [ + Pure, + DeclareOpInterfaceMethods +]> { + let summary = "Get the linear index of the current device."; + let description = [{ + Example: + ``` + %idx = mesh.process_linear_index on @mesh : index + ``` + if `@mesh` has shape `(10, 20, 30)`, a device with multi + index `(1, 2, 3)` will have linear index `3 + 30*2 + 20*30*1`. + }]; + let arguments = (ins FlatSymbolRefAttr:$mesh); + let results = (outs Index:$result); + let assemblyFormat = "`on` $mesh attr-dict `:` type($result)"; + let builders = [ + OpBuilder<(ins "::mlir::mesh::ClusterOp":$mesh)> + ]; +} + //===----------------------------------------------------------------------===// // collective communication ops //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/Mesh/Transforms/Transforms.h b/mlir/include/mlir/Dialect/Mesh/Transforms/Transforms.h new file mode 100644 index 000000000000..10a965daac71 --- /dev/null +++ b/mlir/include/mlir/Dialect/Mesh/Transforms/Transforms.h @@ -0,0 +1,26 @@ +//===- Transforms.h - Mesh Transforms ---------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_DIALECT_MESH_TRANSFORMS_TRANSFORMS_H +#define MLIR_DIALECT_MESH_TRANSFORMS_TRANSFORMS_H + +namespace mlir { +class RewritePatternSet; +class SymbolTableCollection; +class DialectRegistry; +namespace mesh { + +void processMultiIndexOpLoweringPopulatePatterns( + RewritePatternSet &patterns, SymbolTableCollection &symbolTableCollection); + +void processMultiIndexOpLoweringRegisterDialects(DialectRegistry ®istry); + +} // namespace mesh +} // namespace mlir + +#endif // MLIR_DIALECT_MESH_TRANSFORMS_TRANSFORMS_H diff --git a/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp b/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp index 6667d409df8b..9b110c462915 100644 --- a/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp +++ b/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp @@ -250,7 +250,8 @@ void ClusterShapeOp::build(OpBuilder &odsBuilder, OperationState &odsState, ClusterOp mesh) { build(odsBuilder, odsState, SmallVector(mesh.getRank(), odsBuilder.getIndexType()), - mesh.getSymName(), MeshAxesAttr()); + mesh.getSymName(), + MeshAxesAttr::get(odsBuilder.getContext(), SmallVector())); } void ClusterShapeOp::build(OpBuilder &odsBuilder, OperationState &odsState, @@ -325,11 +326,11 @@ bool MeshShardingAttr::operator==(MeshShardingAttr rhs) const { } //===----------------------------------------------------------------------===// -// mesh.process_index op +// mesh.process_multi_index op //===----------------------------------------------------------------------===// LogicalResult -ProcessIndexOp::verifySymbolUses(SymbolTableCollection &symbolTable) { +ProcessMultiIndexOp::verifySymbolUses(SymbolTableCollection &symbolTable) { auto mesh = ::getMesh(getOperation(), getMeshAttr(), symbolTable); if (failed(mesh)) { return failure(); @@ -348,20 +349,38 @@ ProcessIndexOp::verifySymbolUses(SymbolTableCollection &symbolTable) { return success(); } -void ProcessIndexOp::build(OpBuilder &odsBuilder, OperationState &odsState, - ClusterOp mesh) { +void ProcessMultiIndexOp::build(OpBuilder &odsBuilder, OperationState &odsState, + ClusterOp mesh) { build(odsBuilder, odsState, SmallVector(mesh.getRank(), odsBuilder.getIndexType()), mesh.getSymName(), MeshAxesAttr()); } -void ProcessIndexOp::build(OpBuilder &odsBuilder, OperationState &odsState, - StringRef mesh, ArrayRef axes) { +void ProcessMultiIndexOp::build(OpBuilder &odsBuilder, OperationState &odsState, + StringRef mesh, ArrayRef axes) { build(odsBuilder, odsState, SmallVector(axes.size(), odsBuilder.getIndexType()), mesh, MeshAxesAttr::get(odsBuilder.getContext(), axes)); } +//===----------------------------------------------------------------------===// +// mesh.process_linear_index op +//===----------------------------------------------------------------------===// + +LogicalResult +ProcessLinearIndexOp::verifySymbolUses(SymbolTableCollection &symbolTable) { + auto mesh = ::getMesh(getOperation(), getMeshAttr(), symbolTable); + if (failed(mesh)) { + return failure(); + } + return success(); +} + +void ProcessLinearIndexOp::build(OpBuilder &odsBuilder, + OperationState &odsState, ClusterOp mesh) { + build(odsBuilder, odsState, mesh.getSymName()); +} + //===----------------------------------------------------------------------===// // collective communication ops //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt b/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt index 7a70c047ec9d..dccb75848c94 100644 --- a/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt @@ -2,6 +2,7 @@ add_mlir_dialect_library(MLIRMeshTransforms Simplifications.cpp ShardingPropagation.cpp Spmdization.cpp + Transforms.cpp ADDITIONAL_HEADER_DIRS ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/Mesh @@ -11,6 +12,7 @@ add_mlir_dialect_library(MLIRMeshTransforms MLIRShardingInterface LINK_LIBS PUBLIC + MLIRAffineDialect MLIRArithDialect MLIRControlFlowDialect MLIRFuncDialect diff --git a/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp b/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp index 6262d3aa1626..c9275ad5ad45 100644 --- a/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp +++ b/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp @@ -1,4 +1,4 @@ -//===- Patterns.cpp - Mesh Patterns -----------------------------*- C++ -*-===// +//===- Simplifications.cpp - Mesh Simplifications ---------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp b/mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp index 37b865359596..0e83c024fc08 100644 --- a/mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp +++ b/mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp @@ -206,8 +206,8 @@ splitLastAxisInResharding(ImplicitLocOpBuilder &builder, Value processIndexAlongAxis = builder - .create(mesh.getSymName(), - SmallVector({splitMeshAxis})) + .create(mesh.getSymName(), + SmallVector({splitMeshAxis})) .getResult()[0]; MeshShardingAttr targetSharding = targetShardingInSplitLastAxis( diff --git a/mlir/lib/Dialect/Mesh/Transforms/Transforms.cpp b/mlir/lib/Dialect/Mesh/Transforms/Transforms.cpp new file mode 100644 index 000000000000..c27e173d877d --- /dev/null +++ b/mlir/lib/Dialect/Mesh/Transforms/Transforms.cpp @@ -0,0 +1,84 @@ +//===- Transforms.cpp ---------------------------------------------- C++ --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Mesh/Transforms/Transforms.h" +#include "mlir/Dialect/Affine/IR/AffineOps.h" +#include "mlir/Dialect/Mesh/IR/MeshOps.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/DialectRegistry.h" +#include "mlir/IR/ImplicitLocOpBuilder.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/IR/Value.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include +#include + +namespace mlir::mesh { + +namespace { + +/// Lower `mesh.process_multi_index` into expression using +/// `mesh.process_linear_index` and `mesh.cluster_shape`. +struct ProcessMultiIndexOpLowering : OpRewritePattern { + template + ProcessMultiIndexOpLowering(SymbolTableCollection &symbolTableCollection, + OpRewritePatternArgs &&...opRewritePatternArgs) + : OpRewritePattern( + std::forward(opRewritePatternArgs)...), + symbolTableCollection(symbolTableCollection) {} + + LogicalResult matchAndRewrite(ProcessMultiIndexOp op, + PatternRewriter &rewriter) const override { + ClusterOp mesh = + symbolTableCollection.lookupNearestSymbolFrom( + op.getOperation(), op.getMeshAttr()); + if (!mesh) { + return failure(); + } + + ImplicitLocOpBuilder builder(op->getLoc(), rewriter); + builder.setInsertionPointAfter(op.getOperation()); + Value linearIndex = builder.create(mesh); + ValueRange meshShape = builder.create(mesh).getResults(); + SmallVector completeMultiIndex = + builder.create(linearIndex, meshShape) + .getMultiIndex(); + SmallVector multiIndex; + ArrayRef opMeshAxes = op.getAxes(); + SmallVector opAxesIota; + if (opMeshAxes.empty()) { + opAxesIota.resize(mesh.getRank()); + std::iota(opAxesIota.begin(), opAxesIota.end(), 0); + opMeshAxes = opAxesIota; + } + llvm::transform(opMeshAxes, std::back_inserter(multiIndex), + [&completeMultiIndex](MeshAxis meshAxis) { + return completeMultiIndex[meshAxis]; + }); + rewriter.replaceAllUsesWith(op.getResults(), multiIndex); + return success(); + } + +private: + SymbolTableCollection &symbolTableCollection; +}; + +} // namespace + +void processMultiIndexOpLoweringPopulatePatterns( + RewritePatternSet &patterns, SymbolTableCollection &symbolTableCollection) { + patterns.add(symbolTableCollection, + patterns.getContext()); +} + +void processMultiIndexOpLoweringRegisterDialects(DialectRegistry ®istry) { + registry.insert(); +} + +} // namespace mlir::mesh diff --git a/mlir/test/Dialect/Mesh/invalid.mlir b/mlir/test/Dialect/Mesh/invalid.mlir index 3e1b04da0dfd..f3524a82a1b9 100644 --- a/mlir/test/Dialect/Mesh/invalid.mlir +++ b/mlir/test/Dialect/Mesh/invalid.mlir @@ -128,9 +128,9 @@ func.func @cluster_shape_invalid_mesh_name() -> (index) { mesh.cluster @mesh0(rank = 2, dim_sizes = 2x4) -func.func @process_index_mesh_axis_out_of_bounds() -> (index, index) { +func.func @process_multi_index_mesh_axis_out_of_bounds() -> (index, index) { // expected-error@+1 {{0-based mesh axis index 2 is out of bounds. The referenced mesh "mesh0" is of rank 2.}} - %0:2 = mesh.process_index on @mesh0 axes = [0, 2] : index, index + %0:2 = mesh.process_multi_index on @mesh0 axes = [0, 2] : index, index return %0#0, %0#1 : index, index } @@ -138,9 +138,9 @@ func.func @process_index_mesh_axis_out_of_bounds() -> (index, index) { mesh.cluster @mesh0(rank = 3, dim_sizes = 1x2x3) -func.func @process_index_duplicate_mesh_axis() -> (index, index, index) { +func.func @process_multi_index_duplicate_mesh_axis() -> (index, index, index) { // expected-error@+1 {{Mesh axes contains duplicate elements.}} - %0:3 = mesh.process_index on @mesh0 axes = [0, 2, 0] : index, index, index + %0:3 = mesh.process_multi_index on @mesh0 axes = [0, 2, 0] : index, index, index return %0#0, %0#1, %0#2 : index, index, index } @@ -148,9 +148,9 @@ func.func @process_index_duplicate_mesh_axis() -> (index, index, index) { mesh.cluster @mesh0(rank = 2, dim_sizes = 2x4) -func.func @process_index_wrong_number_of_results() -> (index, index) { +func.func @process_multi_index_wrong_number_of_results() -> (index, index) { // expected-error@+1 {{Unexpected number of results 2. Expected 1.}} - %0:2 = mesh.process_index on @mesh0 axes = [0] : index, index + %0:2 = mesh.process_multi_index on @mesh0 axes = [0] : index, index return %0#0, %0#1 : index, index } @@ -158,18 +158,26 @@ func.func @process_index_wrong_number_of_results() -> (index, index) { mesh.cluster @mesh0(rank = 3, dim_sizes = 1x2x3) -func.func @process_index_wrong_number_of_results_empty_mesh_axes() -> (index, index) { +func.func @process_multi_index_wrong_number_of_results_empty_mesh_axes() -> (index, index) { // expected-error@+1 {{Unexpected number of results 2. Expected 3.}} - %0:2 = mesh.process_index on @mesh0 : index, index + %0:2 = mesh.process_multi_index on @mesh0 : index, index return %0#0, %0#1 : index, index } // ----- -func.func @process_index_invalid_mesh_name() -> (index) { +func.func @process_multi_index_invalid_mesh_name() -> (index) { // expected-error@+1 {{Undefined required mesh symbol "this_mesh_symbol_does_not_exist".}} - %0 = mesh.process_index on @this_mesh_symbol_does_not_exist : index - return %0#0 : index + %0 = mesh.process_multi_index on @this_mesh_symbol_does_not_exist : index + return %0 : index +} + +// ----- + +func.func @process_linear_index_invalid_mesh_name() -> (index) { + // expected-error@+1 {{Undefined required mesh symbol "this_mesh_symbol_does_not_exist".}} + %0 = mesh.process_linear_index on @this_mesh_symbol_does_not_exist : index + return %0 : index } // ----- diff --git a/mlir/test/Dialect/Mesh/ops.mlir b/mlir/test/Dialect/Mesh/ops.mlir index a7c3b3dbab9c..0abe31c8b3f7 100644 --- a/mlir/test/Dialect/Mesh/ops.mlir +++ b/mlir/test/Dialect/Mesh/ops.mlir @@ -156,30 +156,37 @@ func.func @cluster_shape_empty_axes() -> (index, index, index) { return %0#0, %0#1, %0#2 : index, index, index } -// CHECK-LABEL: func @process_index -func.func @process_index() -> (index, index) { - // CHECK: %[[RES:.*]]:2 = mesh.process_index on @mesh0 axes = [0, 1] : index, index - %0:2 = mesh.process_index on @mesh0 axes = [0, 1] : index, index +// CHECK-LABEL: func @process_multi_index +func.func @process_multi_index() -> (index, index) { + // CHECK: %[[RES:.*]]:2 = mesh.process_multi_index on @mesh0 axes = [0, 1] : index, index + %0:2 = mesh.process_multi_index on @mesh0 axes = [0, 1] : index, index // CHECK: return %[[RES]]#0, %[[RES]]#1 : index, index return %0#0, %0#1 : index, index } -// CHECK-LABEL: func @process_index_default_axes -func.func @process_index_default_axes() -> (index, index, index) { - // CHECK: %[[RES:.*]]:3 = mesh.process_index on @mesh0 : index, index, index - %0:3 = mesh.process_index on @mesh0 : index, index, index +// CHECK-LABEL: func @process_multi_index_default_axes +func.func @process_multi_index_default_axes() -> (index, index, index) { + // CHECK: %[[RES:.*]]:3 = mesh.process_multi_index on @mesh0 : index, index, index + %0:3 = mesh.process_multi_index on @mesh0 : index, index, index // CHECK: return %[[RES]]#0, %[[RES]]#1, %[[RES]]#2 : index, index, index return %0#0, %0#1, %0#2 : index, index, index } -// CHECK-LABEL: func @process_index_empty_axes -func.func @process_index_empty_axes() -> (index, index, index) { - // CHECK: %[[RES:.*]]:3 = mesh.process_index on @mesh0 : index, index, index - %0:3 = mesh.process_index on @mesh0 axes = [] : index, index, index +// CHECK-LABEL: func @process_multi_index_empty_axes +func.func @process_multi_index_empty_axes() -> (index, index, index) { + // CHECK: %[[RES:.*]]:3 = mesh.process_multi_index on @mesh0 : index, index, index + %0:3 = mesh.process_multi_index on @mesh0 axes = [] : index, index, index // CHECK: return %[[RES]]#0, %[[RES]]#1, %[[RES]]#2 : index, index, index return %0#0, %0#1, %0#2 : index, index, index } +// CHECK-LABEL: func @process_linear_index +func.func @process_linear_index() -> index { + // CHECK: %[[RES:.*]] = mesh.process_linear_index on @mesh0 : index + %0 = mesh.process_linear_index on @mesh0 : index + // CHECK: return %[[RES]] : index + return %0 : index +} // CHECK-LABEL: func @all_reduce func.func @all_reduce( diff --git a/mlir/test/Dialect/Mesh/process-multi-index-op-lowering.mlir b/mlir/test/Dialect/Mesh/process-multi-index-op-lowering.mlir new file mode 100644 index 000000000000..9602fb729c26 --- /dev/null +++ b/mlir/test/Dialect/Mesh/process-multi-index-op-lowering.mlir @@ -0,0 +1,23 @@ +// RUN: mlir-opt -test-mesh-process-multi-index-op-lowering %s | FileCheck %s + +mesh.cluster @mesh2d(rank = 2) + +// CHECK-LABEL: func.func @multi_index_2d_mesh +func.func @multi_index_2d_mesh() -> (index, index) { + // CHECK: %[[LINEAR_IDX:.*]] = mesh.process_linear_index on @mesh2d : index + // CHECK: %[[MESH_SHAPE:.*]]:2 = mesh.cluster_shape @mesh2d : index, index + // CHECK: %[[MULTI_IDX:.*]]:2 = affine.delinearize_index %0 into (%[[MESH_SHAPE]]#0, %[[MESH_SHAPE]]#1) : index, index + %0:2 = mesh.process_multi_index on @mesh2d : index, index + // CHECK: return %[[MULTI_IDX]]#0, %[[MULTI_IDX]]#1 : index, index + return %0#0, %0#1 : index, index +} + +// CHECK-LABEL: func.func @multi_index_2d_mesh_single_inner_axis +func.func @multi_index_2d_mesh_single_inner_axis() -> index { + // CHECK: %[[LINEAR_IDX:.*]] = mesh.process_linear_index on @mesh2d : index + // CHECK: %[[MESH_SHAPE:.*]]:2 = mesh.cluster_shape @mesh2d : index, index + // CHECK: %[[MULTI_IDX:.*]]:2 = affine.delinearize_index %0 into (%[[MESH_SHAPE]]#0, %[[MESH_SHAPE]]#1) : index, index + %0 = mesh.process_multi_index on @mesh2d axes = [0] : index + // CHECK: return %[[MULTI_IDX]]#0 : index + return %0 : index +} diff --git a/mlir/test/Dialect/Mesh/resharding-spmdization.mlir b/mlir/test/Dialect/Mesh/resharding-spmdization.mlir index c7088fe646d8..786ea386df81 100644 --- a/mlir/test/Dialect/Mesh/resharding-spmdization.mlir +++ b/mlir/test/Dialect/Mesh/resharding-spmdization.mlir @@ -21,7 +21,7 @@ func.func @split_replicated_tensor_axis( ) -> tensor<3x14xf32> { // CHECK-DAG: %[[ZERO:.*]] = arith.constant 0 : index // CHECK-DAG: %[[TENSOR_SPLIT_AXIS_SIZE:.*]] = arith.constant 14 : index - // CHECK: %[[PROCESS_INDEX:.*]] = mesh.process_index on @mesh_1d axes = [0] : index + // CHECK: %[[PROCESS_INDEX:.*]] = mesh.process_multi_index on @mesh_1d axes = [0] : index // CHECK: %[[MESH_AXIS_SIZE:.*]] = mesh.cluster_shape @mesh_1d axes = [0] : index // CHECK: %[[TENSOR_SPLIT_AXIS_SIZE_MOD_MESH_AXIS_SIZE:.*]] = arith.remui %[[TENSOR_SPLIT_AXIS_SIZE]], %[[MESH_AXIS_SIZE]] : index // CHECK: %[[RESULT_TENSOR_AXIS_SIZE_CHECK:.*]] = arith.cmpi eq, %[[TENSOR_SPLIT_AXIS_SIZE_MOD_MESH_AXIS_SIZE]], %[[ZERO]] : index @@ -43,7 +43,7 @@ func.func @split_replicated_tensor_axis_dynamic( ) -> tensor { // CHECK-DAG: %[[ZERO:.*]] = arith.constant 0 : index // CHECK-DAG: %[[TWO:.*]] = arith.constant 2 : index - // CHECK: %[[PROCESS_INDEX:.*]] = mesh.process_index on @mesh_1d_dynamic axes = [0] : index + // CHECK: %[[PROCESS_INDEX:.*]] = mesh.process_multi_index on @mesh_1d_dynamic axes = [0] : index // CHECK: %[[MESH_AXIS_SIZE:.*]] = mesh.cluster_shape @mesh_1d_dynamic axes = [0] : index // CHECK: %[[TENSOR_SPLIT_AXIS_SIZE:.*]] = tensor.dim %[[ARG]], %[[ZERO]] : tensor // CHECK: %[[TENSOR_SPLIT_AXIS_SIZE_MOD_MESH_AXIS_SIZE:.*]] = arith.remui %[[TENSOR_SPLIT_AXIS_SIZE]], %[[MESH_AXIS_SIZE]] : index diff --git a/mlir/test/lib/Dialect/Mesh/CMakeLists.txt b/mlir/test/lib/Dialect/Mesh/CMakeLists.txt index daff88235b5b..00931e6c94fc 100644 --- a/mlir/test/lib/Dialect/Mesh/CMakeLists.txt +++ b/mlir/test/lib/Dialect/Mesh/CMakeLists.txt @@ -1,5 +1,6 @@ # Exclude tests from libMLIR.so add_mlir_library(MLIRMeshTest + TestProcessMultiIndexOpLowering.cpp TestReshardingSpmdization.cpp TestSimplifications.cpp diff --git a/mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp b/mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp new file mode 100644 index 000000000000..7acbf5189704 --- /dev/null +++ b/mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp @@ -0,0 +1,55 @@ +//===- TestProcessMultiIndexOpLowering.cpp --------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Mesh/IR/MeshOps.h" +#include "mlir/Dialect/Mesh/Transforms/Transforms.h" +#include "mlir/Dialect/Utils/IndexingUtils.h" +#include "mlir/IR/SymbolTable.h" +#include "mlir/Pass/Pass.h" +#include "mlir/Support/LogicalResult.h" +#include "mlir/Transforms/GreedyPatternRewriteDriver.h" + +using namespace mlir; + +namespace { +struct TestMultiIndexOpLoweringPass + : public PassWrapper> { + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(TestMultiIndexOpLoweringPass) + + void runOnOperation() override; + void getDependentDialects(DialectRegistry ®istry) const override { + registry.insert(); + mesh::processMultiIndexOpLoweringRegisterDialects(registry); + } + StringRef getArgument() const final { + return "test-mesh-process-multi-index-op-lowering"; + } + StringRef getDescription() const final { + return "Test lowering of mesh.process_multi_index op."; + } +}; +} // namespace + +void TestMultiIndexOpLoweringPass::runOnOperation() { + RewritePatternSet patterns(&getContext()); + SymbolTableCollection symbolTableCollection; + mesh::processMultiIndexOpLoweringPopulatePatterns(patterns, + symbolTableCollection); + LogicalResult status = + applyPatternsAndFoldGreedily(getOperation(), std::move(patterns)); + assert(succeeded(status) && "applyPatternsAndFoldGreedily failed."); +} + +namespace mlir { +namespace test { +void registerTestMultiIndexOpLoweringPass() { + PassRegistration(); +} +} // namespace test +} // namespace mlir diff --git a/mlir/tools/mlir-opt/mlir-opt.cpp b/mlir/tools/mlir-opt/mlir-opt.cpp index 09ff66e07957..5c6a72881ddf 100644 --- a/mlir/tools/mlir-opt/mlir-opt.cpp +++ b/mlir/tools/mlir-opt/mlir-opt.cpp @@ -120,6 +120,7 @@ void registerTestMemRefDependenceCheck(); void registerTestMemRefStrideCalculation(); void registerTestMeshSimplificationsPass(); void registerTestMeshReshardingSpmdizationPass(); +void registerTestMultiIndexOpLoweringPass(); void registerTestNextAccessPass(); void registerTestOneToNTypeConversionPass(); void registerTestOpaqueLoc(); @@ -240,6 +241,7 @@ void registerTestPasses() { mlir::test::registerTestMathPolynomialApproximationPass(); mlir::test::registerTestMemRefDependenceCheck(); mlir::test::registerTestMemRefStrideCalculation(); + mlir::test::registerTestMultiIndexOpLoweringPass(); mlir::test::registerTestMeshSimplificationsPass(); mlir::test::registerTestMeshReshardingSpmdizationPass(); mlir::test::registerTestNextAccessPass(); -- GitLab From 8b7bbedec7bcfbeaee4ab9b74471cbbbc8633e1a Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 10 Jan 2024 15:02:13 +0000 Subject: [PATCH 338/652] [LV] Re-add early exit in VPRecipeBuilder::createBlockInMask. Re-add early exit that was accidentally dropped in 51afb10. --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 51ce88480c08..1a5b9dbb82fa 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -8031,6 +8031,7 @@ void VPRecipeBuilder::createBlockInMask(BasicBlock *BB, VPlan &Plan) { VPValue *EdgeMask = createEdgeMask(Predecessor, BB, Plan); if (!EdgeMask) { // Mask of predecessor is all-one so mask of block is too. BlockMaskCache[BB] = EdgeMask; + return; } if (!BlockMask) { // BlockMask has its initialized nullptr value. -- GitLab From 14e291000f96c20e35ef494bd407f459b4617fca Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Wed, 10 Jan 2024 22:12:29 +0700 Subject: [PATCH 339/652] [RISCV] Remove extraneous semicolons. NFC --- llvm/include/llvm/Support/RISCVISAInfo.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h index c539448683d3..97f1051b0540 100644 --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/Support/RISCVISAInfo.h @@ -71,10 +71,10 @@ public: std::vector toFeatures(bool AddAllExtensions = false, bool IgnoreUnknown = true) const; - const OrderedExtensionMap &getExtensions() const { return Exts; }; + const OrderedExtensionMap &getExtensions() const { return Exts; } - unsigned getXLen() const { return XLen; }; - unsigned getFLen() const { return FLen; }; + unsigned getXLen() const { return XLen; } + unsigned getFLen() const { return FLen; } unsigned getMinVLen() const { return MinVLen; } unsigned getMaxVLen() const { return 65536; } unsigned getMaxELen() const { return MaxELen; } -- GitLab From 6876fe53afabfc6f0c3b5e7c838f32a282da6f77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Wed, 10 Jan 2024 15:19:16 +0000 Subject: [PATCH 340/652] [mlir][linalg] Add a test to demonstrate peeling + vectorisation (#77590) Following on from #75842, we can demonstrate that loop peeling combined with masked vectorisation and existing canonicalization for vector.mask operations leads to the following loop structure: ``` // M dimension scf.for 1:M // N dimension (contains vector ops _without_ masking) scf.for 1:UB // K dimension scf.for 1:K vector.add // N dimension (contains vector ops _with_ masking) scf.for UB:N // K dimension scf.for 1:K vector.mask { vector.add } ``` This is particularly beneficial for scalable vectors which normally require masking. This example demonstrates how to avoid them. --- .../transform-op-peel-and-vectorize.mlir | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir diff --git a/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir b/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir new file mode 100644 index 000000000000..762648050fdf --- /dev/null +++ b/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir @@ -0,0 +1,86 @@ +// RUN: mlir-opt %s --transform-interpreter --split-input-file -canonicalize | FileCheck %s + +// Demonstrates what happens when peeling the middle loop (2nd parallel +// dimension) followed by vectorization in the presence of _scalable_ vectors +// (these are introduced through scalable tiling). The main goal is to verify +// that canonicalizations fold away the masks in the main loop. + +func.func @matmul(%A: tensor<1024x512xf32>, + %B: tensor<512x2000xf32>, + %C: tensor<1024x2000xf32>) -> tensor<1024x2000xf32> { + +// CHECK: #[[MAP:.*]] = affine_map<()[s0] -> (-(2000 mod s0) + 2000)> +// CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index +// CHECK-DAG: %[[C2000:.*]] = arith.constant 2000 : index +// CHECK-DAG: %[[C8:.*]] = arith.constant 8 : index +// CHECK-DAG: %[[C1024:.*]] = arith.constant 1024 : index +// CHECK-DAG: %[[C512:.*]] = arith.constant 512 : index +// CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index +// CHECK-DAG: %[[C16:.*]] = arith.constant 16 : index +// CHECK: %[[VSCALE:.*]] = vector.vscale +// CHECK: %[[STEP:.*]] = arith.muli %[[VSCALE]], %[[C16]] : index +// CHECK: %2 = scf.for {{.*}} %[[C0]] to %[[C1024]] step %[[C8]] iter_args(%arg4 = %arg2) -> (tensor<1024x2000xf32>) { + +// Main loop after vectorisation (without masking) + +// CHECK: %[[UB_MAIN:.*]] = affine.apply #[[MAP]]()[%[[STEP]]] +// CHECK: scf.for {{.*}} %[[C0]] to %[[UB_MAIN]] step %[[STEP]] {{.*}} -> (tensor<1024x2000xf32>) { +// CHECK: scf.for %arg7 = %[[C0]] to %[[C512]] step %[[C1]] {{.*}} -> (tensor<1024x2000xf32>) { +// CHECK-NOT: vector.mask +// CHECK: arith.mulf {{.*}} : vector<8x[16]x1xf32> +// CHECK-NEXT: vector.shape_cast {{.*}} : vector<8x[16]x1xf32> to vector<8x[16]xf32> +// CHECK-NEXT: arith.addf {{.*}} : vector<8x[16]xf32> +// CHECK-NOT: vector.mask +// CHECK: scf.yield {{.*}} : tensor<1024x2000xf32> +// CHECK-NEXT: } +// CHECK-NEXT: scf.yield {{.*}} : tensor<1024x2000xf32> +// CHECK-NEXT: } + +// Remainder loop after vectorisation (with masking) + +// CHECK: scf.for {{.*}} %[[UB_MAIN]] to %[[C2000]] step %[[STEP]] {{.*}} -> (tensor<1024x2000xf32>) { +// CHECK: scf.for {{.*}} %[[C0]] to %[[C512]] step %[[C1]] {{.*}} -> (tensor<1024x2000xf32>) { +// CHECK: %[[MASK_1:.*]] = vector.create_mask {{.*}} : vector<1x[16]xi1> +// CHECK: %[[RHS:.*]] = vector.mask %[[MASK_1]] { vector.transfer_read {{.*}} } : vector<1x[16]xi1> -> vector<8x[16]x1xf32> +// CHECK: %[[MASK_2:.*]] = vector.create_mask {{.*}} : vector<8x[16]xi1> +// CHECK: %[[LHS:.*]] = vector.mask %[[MASK_2]] { vector.transfer_read {{.*}} } : vector<8x[16]xi1> -> vector<8x[16]xf32> +// CHECK: %[[MUL:.*]] = arith.mulf %{{.*}}, %[[RHS]] : vector<8x[16]x1xf32> +// CHECK: %[[MASK_3:.*]] = vector.create_mask {{.*}} : vector<8x[16]xi1> +// CHECK: vector.shape_cast %[[MUL]] : vector<8x[16]x1xf32> to vector<8x[16]xf32> +// CHECK: arith.addf %[[LHS]], %{{.*}} : vector<8x[16]xf32> +// CHECK: arith.select %[[MASK_3]], {{.*}} : vector<8x[16]xi1>, vector<8x[16]xf32> +// CHECK: vector.mask %[[MASK_2]] { vector.transfer_write {{.*}} } : vector<8x[16]xi1> -> tensor<8x?xf32> +// CHECK: scf.yield %inserted_slice : tensor<1024x2000xf32> +// CHECK: } +// CHECK: scf.yield %7 : tensor<1024x2000xf32> +// CHECK: } +// CHECK: scf.yield %5 : tensor<1024x2000xf32> +// CHECK-NEXT: } + + %res = linalg.matmul ins(%A, %B: tensor<1024x512xf32>, tensor<512x2000xf32>) + outs(%C: tensor<1024x2000xf32>) -> tensor<1024x2000xf32> + return %res : tensor<1024x2000xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%root: !transform.any_op {transform.readonly}) { + %matmul = transform.structured.match ops{["linalg.matmul"]} in %root : (!transform.any_op) -> !transform.any_op + // 1. Scalable tiling + %_, %loop_1, %loop_2, %loop_3 = + transform.structured.tile_using_for %matmul [8, [16], 1] : (!transform.any_op) + -> (!transform.any_op, !transform.op<"scf.for">, !transform.op<"scf.for">,!transform.op<"scf.for">) + + // 2. Loop peeling (only the middle dimension) + %main_loop, %remainder_loop = transform.loop.peel %loop_2 : (!transform.op<"scf.for">) -> (!transform.op<"scf.for">, !transform.op<"scf.for">) + + // 3. Vectorize the main loop + %matmul_main = transform.structured.match ops{["linalg.matmul"]} in %main_loop : (!transform.op<"scf.for">) -> !transform.any_op + transform.structured.vectorize %matmul_main vector_sizes [8, [16], 1] : !transform.any_op + + // 4. Vectorize the remainder loop + %matmul_remainder = transform.structured.match ops{["linalg.matmul"]} in %remainder_loop : (!transform.op<"scf.for">) -> !transform.any_op + transform.structured.vectorize %matmul_remainder vector_sizes [8, [16], 1] : !transform.any_op + + transform.yield + } +} -- GitLab From 73ce13d79bb6f200d6dde61a88369daf74c7a39e Mon Sep 17 00:00:00 2001 From: Alexey Bataev <5361294+alexey-bataev@users.noreply.github.com> Date: Wed, 10 Jan 2024 10:39:34 -0500 Subject: [PATCH 341/652] [SLP][TTI]Improve detection of the insert-subvector pattern for SLP. (#74749) SLP vectorizer passes the type of the subvector and the mask, which size determines the size of the resulting vector. TTI should support this pattern to improve cost estimation of the insert_subvector shuffle pattern. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 46 +++++++++++++++---- .../RISCV/remarks-insert-into-small-vector.ll | 17 +++---- 2 files changed, 42 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 8e22b54f002d..0ce5d619d9b1 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -6894,6 +6894,31 @@ protected: }; } // namespace +/// Returns the cost of the shuffle instructions with the given \p Kind, vector +/// type \p Tp and optional \p Mask. Adds SLP-specifc cost estimation for insert +/// subvector pattern. +static InstructionCost +getShuffleCost(const TargetTransformInfo &TTI, TTI::ShuffleKind Kind, + VectorType *Tp, ArrayRef Mask = std::nullopt, + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, + int Index = 0, VectorType *SubTp = nullptr, + ArrayRef Args = std::nullopt) { + if (Kind != TTI::SK_PermuteTwoSrc) + return TTI.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args); + int NumSrcElts = Tp->getElementCount().getKnownMinValue(); + int NumSubElts; + if (Mask.size() > 2 && ShuffleVectorInst::isInsertSubvectorMask( + Mask, NumSrcElts, NumSubElts, Index)) { + if (Index + NumSubElts > NumSrcElts && + Index + NumSrcElts <= static_cast(Mask.size())) + return TTI.getShuffleCost( + TTI::SK_InsertSubvector, + FixedVectorType::get(Tp->getElementType(), Mask.size()), std::nullopt, + TTI::TCK_RecipThroughput, Index, Tp); + } + return TTI.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args); +} + /// Merges shuffle masks and emits final shuffle instruction, if required. It /// supports shuffling of 2 input vectors. It implements lazy shuffles emission, /// when the actual shuffle instruction is generated only if this is actually @@ -7141,15 +7166,15 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { std::optional RegShuffleKind = CheckPerRegistersShuffle(SubMask); if (!RegShuffleKind) { - Cost += TTI.getShuffleCost( - *ShuffleKinds[Part], + Cost += ::getShuffleCost( + TTI, *ShuffleKinds[Part], FixedVectorType::get(VL.front()->getType(), NumElts), MaskSlice); continue; } if (*RegShuffleKind != TTI::SK_PermuteSingleSrc || !ShuffleVectorInst::isIdentityMask(SubMask, EltsPerVector)) { - Cost += TTI.getShuffleCost( - *RegShuffleKind, + Cost += ::getShuffleCost( + TTI, *RegShuffleKind, FixedVectorType::get(VL.front()->getType(), EltsPerVector), SubMask); } @@ -7222,8 +7247,8 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { cast(V1->getType())->getElementCount().getKnownMinValue(); if (isEmptyOrIdentity(Mask, VF)) return TTI::TCC_Free; - return TTI.getShuffleCost(TTI::SK_PermuteTwoSrc, - cast(V1->getType()), Mask); + return ::getShuffleCost(TTI, TTI::SK_PermuteTwoSrc, + cast(V1->getType()), Mask); } InstructionCost createShuffleVector(Value *V1, ArrayRef Mask) const { // Empty mask or identity mask are free. @@ -8101,7 +8126,8 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, for (unsigned I = OffsetEnd + 1 - Offset; I < VecSz; ++I) Mask[I] = ((I >= InMask.size()) || InMask.test(I)) ? PoisonMaskElem : I; - Cost += TTI->getShuffleCost(TTI::SK_PermuteTwoSrc, InsertVecTy, Mask); + Cost += + ::getShuffleCost(*TTI, TTI::SK_PermuteTwoSrc, InsertVecTy, Mask); } } return Cost; @@ -8428,8 +8454,8 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, return I->getOpcode() == E->getAltOpcode(); }, Mask); - VecCost += TTIRef.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, - FinalVecTy, Mask); + VecCost += ::getShuffleCost(TTIRef, TargetTransformInfo::SK_PermuteTwoSrc, + FinalVecTy, Mask); // Patterns like [fadd,fsub] can be combined into a single instruction // in x86. Reordering them into [fsub,fadd] blocks this pattern. So we // need to take into account their order when looking for the most used @@ -9133,7 +9159,7 @@ InstructionCost BoUpSLP::getTreeCost(ArrayRef VectorizedVals) { auto *FTy = FixedVectorType::get(TEs.back()->Scalars.front()->getType(), VF); InstructionCost C = - TTI->getShuffleCost(TTI::SK_PermuteTwoSrc, FTy, Mask); + ::getShuffleCost(*TTI, TTI::SK_PermuteTwoSrc, FTy, Mask); LLVM_DEBUG(dbgs() << "SLP: Adding cost " << C << " for final shuffle of vector node and external " "insertelement users.\n"; diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll index 8e0f38222224..de1eecd98eeb 100644 --- a/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll @@ -8,7 +8,7 @@ ; YAML-NEXT: Function: test ; YAML-NEXT: Args: ; YAML-NEXT: - String: 'Stores SLP vectorized with cost ' -; YAML-NEXT: - Cost: '9' +; YAML-NEXT: - Cost: '3' ; YAML-NEXT: - String: ' and with tree size ' ; YAML-NEXT: - TreeSize: '7' @@ -19,20 +19,15 @@ define void @test() { ; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr null, align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr null, align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr null, align 4 -; CHECK-NEXT: [[V9IDX:%.*]] = getelementptr i8, ptr null, i32 4 -; CHECK-NEXT: [[V14IDX:%.*]] = getelementptr i8, ptr null, i32 8 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> , float [[TMP1]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0 ; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x float> [[TMP4]], float [[TMP2]], i32 1 ; CHECK-NEXT: [[TMP6:%.*]] = fcmp ogt <2 x float> [[TMP3]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP6]], i32 0 -; CHECK-NEXT: [[V0_0:%.*]] = select i1 [[TMP7]], float [[TMP0]], float 0.000000e+00 -; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP6]], <2 x float> [[TMP3]], <2 x float> zeroinitializer -; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP6]], i32 1 -; CHECK-NEXT: [[V9_0:%.*]] = select i1 [[TMP9]], float [[TMP2]], float 0.000000e+00 -; CHECK-NEXT: store float [[V0_0]], ptr null, align 4 -; CHECK-NEXT: store float [[V9_0]], ptr [[V9IDX]], align 4 -; CHECK-NEXT: store <2 x float> [[TMP8]], ptr [[V14IDX]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i1> [[TMP6]], <2 x i1> poison, <4 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP5]], <2 x float> [[TMP3]], <4 x i32> +; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> , <4 x i32> +; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[TMP7]], <4 x float> [[TMP9]], <4 x float> zeroinitializer +; CHECK-NEXT: store <4 x float> [[TMP10]], ptr null, align 4 ; CHECK-NEXT: ret void ; entry: -- GitLab From 6c92770a80257018df69369fd617628c80b9fa18 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 10 Jan 2024 12:38:05 +0100 Subject: [PATCH 342/652] [RewriteStatepointsForGC] Remove unnecessary bitcasts (NFCI) --- .../Scalar/RewriteStatepointsForGC.cpp | 23 ++++--------------- 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp index 3f02441b74ba..b98f823ab00b 100644 --- a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp +++ b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp @@ -1975,19 +1975,10 @@ insertRelocationStores(iterator_range GCRelocs, assert(AllocaMap.count(OriginalValue)); Value *Alloca = AllocaMap[OriginalValue]; - // Emit store into the related alloca - // All gc_relocates are i8 addrspace(1)* typed, and it must be bitcasted to - // the correct type according to alloca. + // Emit store into the related alloca. assert(Relocate->getNextNode() && "Should always have one since it's not a terminator"); - IRBuilder<> Builder(Relocate->getNextNode()); - Value *CastedRelocatedValue = - Builder.CreateBitCast(Relocate, - cast(Alloca)->getAllocatedType(), - suffixed_name_or(Relocate, ".casted", "")); - - new StoreInst(CastedRelocatedValue, Alloca, - cast(CastedRelocatedValue)->getNextNode()); + new StoreInst(Relocate, Alloca, Relocate->getNextNode()); #ifndef NDEBUG VisitedLiveValues.insert(OriginalValue); @@ -2620,13 +2611,9 @@ static bool inlineGetBaseAndOffset(Function &F, Value *Base = findBasePointer(Callsite->getOperand(0), DVCache, KnownBases); assert(!DVCache.count(Callsite)); - auto *BaseBC = IRBuilder<>(Callsite).CreateBitCast( - Base, Callsite->getType(), suffixed_name_or(Base, ".cast", "")); - if (BaseBC != Base) - DVCache[BaseBC] = Base; - Callsite->replaceAllUsesWith(BaseBC); - if (!BaseBC->hasName()) - BaseBC->takeName(Callsite); + Callsite->replaceAllUsesWith(Base); + if (!Base->hasName()) + Base->takeName(Callsite); Callsite->eraseFromParent(); break; } -- GitLab From d301539b777c5047d1420003b4ab1e05a1f87166 Mon Sep 17 00:00:00 2001 From: Will Hawkins Date: Wed, 10 Jan 2024 10:51:06 -0500 Subject: [PATCH 343/652] [libc++][docs] Document the libc++ Lit testing format naming scheme (#73136) As a new contributor, I found it hard to find the documentation for the meaning of the names of different tests and how those names translate to Lit. This patch moves the documentation to the RST documentation we publish on the website instead of leaving it in the source code only. --- libcxx/docs/TestingLibcxx.rst | 96 +++++++++++++++++++++++++++--- libcxx/utils/libcxx/test/format.py | 61 ++----------------- 2 files changed, 93 insertions(+), 64 deletions(-) diff --git a/libcxx/docs/TestingLibcxx.rst b/libcxx/docs/TestingLibcxx.rst index 44f3904f4e42..e7645cb5885f 100644 --- a/libcxx/docs/TestingLibcxx.rst +++ b/libcxx/docs/TestingLibcxx.rst @@ -325,18 +325,98 @@ This macro is in a different header as ``assert_macros.h`` since it pulls in additional headers. .. note: This macro can only be used in test using C++20 or newer. The macro - was added at a time where most of lib++'s C++17 support was complete. + was added at a time where most of libc++'s C++17 support was complete. Since it is not expected to add this to existing tests no effort was taken to make it work in earlier language versions. -Additional reading ------------------- - -The function ``CxxStandardLibraryTest`` in the file -``libcxx/utils/libcxx/test/format.py`` has documentation about writing test. It -explains the difference between the test named ``foo.pass.cpp`` and named -``foo.verify.cpp`` are. +Test names +---------- + +The names of test files have meaning for the libc++-specific configuration of +Lit. Based on the pattern that matches the name of a test file, Lit will test +the code contained therein in different ways. Refer to the `Lit Meaning of libc++ +Test Filenames`_ when determining the names for new test files. + +.. _Lit Meaning of libc++ Test Filenames: +.. list-table:: Lit Meaning of libc++ Test Filenames + :widths: 25 75 + :header-rows: 1 + + * - Name Pattern + - Meaning + * - ``FOO.pass.cpp`` + - Checks whether the C++ code in the file compiles, links and runs successfully. + * - ``FOO.pass.mm`` + - Same as ``FOO.pass.cpp``, but for Objective-C++. + + * - ``FOO.compile.pass.cpp`` + - Checks whether the C++ code in the file compiles successfully. In general, prefer ``compile`` tests over ``verify`` tests, + subject to the specific recommendations, below, for when to write ``verify`` tests. + * - ``FOO.compile.pass.mm`` + - Same as ``FOO.compile.pass.cpp``, but for Objective-C++. + * - ``FOO.compile.fail.cpp`` + - Checks that the code in the file does *not* compile successfully. + + * - ``FOO.verify.cpp`` + - Compiles with clang-verify. This type of test is automatically marked as UNSUPPORTED if the compiler does not support clang-verify. + For additional information about how to write ``verify`` tests, see the `Internals Manual `_. + Prefer `verify` tests over ``compile`` tests to test that compilation fails for a particular reason. For example, use a ``verify`` test + to ensure that + + * an expected ``static_assert`` is triggered; + * the use of deprecated functions generates the proper warning; + * removed functions are no longer usable; or + * return values from functions marked ``[[nodiscard]]`` are stored. + + * - ``FOO.link.pass.cpp`` + - Checks that the C++ code in the file compiles and links successfully -- no run attempted. + * - ``FOO.link.pass.mm`` + - Same as ``FOO.link.pass.cpp``, but for Objective-C++. + * - ``FOO.link.fail.cpp`` + - Checks whether the C++ code in the file fails to link after successful compilation. + * - ``FOO.link.fail.mm`` + - Same as ``FOO.link.fail.cpp``, but for Objective-C++. + + * - ``FOO.sh.`` + - A *builtin Lit Shell* test. + * - ``FOO.gen.`` + - A variant of a *Lit Shell* test that generates one or more Lit tests on the fly. Executing this test must generate one or more files as expected + by LLVM split-file. Each generated file will drive an invocation of a separate Lit test. The format of the generated file will determine the type + of Lit test to be executed. This can be used to generate multiple Lit tests from a single source file, which is useful for testing repetitive properties + in the library. Be careful not to abuse this since this is not a replacement for usual code reuse techniques. + + +libc++-Specific Lit Features +---------------------------- + +Custom Directives +~~~~~~~~~~~~~~~~~ + +Lit has many directives built in (e.g., ``DEFINE``, ``UNSUPPORTED``). In addition to those directives, libc++ adds two additional libc++-specific directives that makes +writing tests easier. See `libc++-specific Lit Directives`_ for more information about the ``FILE_DEPENDENCIES`` and ``ADDITIONAL_COMPILE_FLAGS`` libc++-specific directives. + +.. _libc++-specific Lit Directives: +.. list-table:: libc++-specific Lit Directives + :widths: 20 35 45 + :header-rows: 1 + + * - Directive + - Parameters + - Usage + * - ``FILE_DEPENDENCIES`` + - ``// FILE_DEPENDENCIES: file, directory, /path/to/file, ...`` + - The paths given to the ``FILE_DEPENDENCIES`` directive can specify directories or specific files upon which a given test depend. For example, a test that requires some test + input stored in a data file would use this libc++-specific Lit directive. When a test file contains the ``FILE_DEPENDENCIES`` directive, Lit will collect the named files and copy + them to the directory represented by the ``%T`` substitution before the test executes. The copy is performed from the directory represented by the ``%S`` substitution + (i.e. the source directory of the test being executed) which makes it possible to use relative paths to specify the location of dependency files. After Lit copies + all the dependent files to the directory specified by the ``%T`` substitution, that directory should contain *all* the necessary inputs to run. In other words, + it should be possible to copy the contents of the directory specified by the ``%T`` substitution to a remote host where the execution of the test will actually occur. + * - ``ADDITIONAL_COMPILE_FLAGS`` + - ``// ADDITIONAL_COMPILE_FLAGS: flag1 flag2 ...`` + - The additional compiler flags specified by a space-separated list to the ``ADDITIONAL_COMPILE_FLAGS`` libc++-specific Lit directive will be added to the end of the ``%{compile_flags}`` + substitution for the test that contains it. This libc++-specific Lit directive makes it possible to add special compilation flags without having to resort to writing a ``.sh.cpp`` test (see + `Lit Meaning of libc++ Test Filenames`_), more powerful but perhaps overkill. Benchmarks ========== diff --git a/libcxx/utils/libcxx/test/format.py b/libcxx/utils/libcxx/test/format.py index e58e404bfcd2..5d84711bf5d2 100644 --- a/libcxx/utils/libcxx/test/format.py +++ b/libcxx/utils/libcxx/test/format.py @@ -151,38 +151,11 @@ class CxxStandardLibraryTest(lit.formats.FileBasedTest): """ Lit test format for the C++ Standard Library conformance test suite. - This test format is based on top of the ShTest format -- it basically - creates a shell script performing the right operations (compile/link/run) - based on the extension of the test file it encounters. It supports files - with the following extensions: - - FOO.pass.cpp - Compiles, links and runs successfully - FOO.pass.mm - Same as .pass.cpp, but for Objective-C++ - - FOO.compile.pass.cpp - Compiles successfully, link and run not attempted - FOO.compile.pass.mm - Same as .compile.pass.cpp, but for Objective-C++ - FOO.compile.fail.cpp - Does not compile successfully - - FOO.link.pass.cpp - Compiles and links successfully, run not attempted - FOO.link.pass.mm - Same as .link.pass.cpp, but for Objective-C++ - FOO.link.fail.cpp - Compiles successfully, but fails to link - - FOO.sh. - A builtin Lit Shell test - - FOO.gen. - A .sh test that generates one or more Lit tests on the - fly. Executing this test must generate one or more files - as expected by LLVM split-file, and each generated file - leads to a separate Lit test that runs that file as - defined by the test format. This can be used to generate - multiple Lit tests from a single source file, which is - useful for testing repetitive properties in the library. - Be careful not to abuse this since this is not a replacement - for usual code reuse techniques. - - FOO.verify.cpp - Compiles with clang-verify. This type of test is - automatically marked as UNSUPPORTED if the compiler - does not support Clang-verify. - + Lit tests are contained in files that follow a certain pattern, which determines the semantics of the test. + Under the hood, we basically generate a builtin Lit shell test that follows the ShTest format, and perform + the appropriate operations (compile/link/run). See + https://libcxx.llvm.org/TestingLibcxx.html#test-names + for a complete description of those semantics. Substitution requirements =============================== @@ -200,30 +173,6 @@ class CxxStandardLibraryTest(lit.formats.FileBasedTest): in the same command line. In other words, the test format doesn't perform separate compilation and linking steps in this case. - - Additional supported directives - =============================== - In addition to everything that's supported in Lit ShTests, this test format - also understands the following directives inside test files: - - // FILE_DEPENDENCIES: file, directory, /path/to/file - - This directive expresses that the test requires the provided files - or directories in order to run. An example is a test that requires - some test input stored in a data file. When a test file contains - such a directive, this test format will collect them and copy them - to the directory represented by %T. The intent is that %T contains - all the inputs necessary to run the test, such that e.g. execution - on a remote host can be done by simply copying %T to the host. - - // ADDITIONAL_COMPILE_FLAGS: flag1 flag2 flag3 - - This directive will cause the provided flags to be added to the - %{compile_flags} substitution for the test that contains it. This - allows adding special compilation flags without having to use a - .sh.cpp test, which would be more powerful but perhaps overkill. - - Additional provided substitutions and features ============================================== The test format will define the following substitutions for use inside tests: -- GitLab From 5934a6ee5967f795634d5161d46da8412be96404 Mon Sep 17 00:00:00 2001 From: Paul T Robinson Date: Wed, 10 Jan 2024 07:53:11 -0800 Subject: [PATCH 344/652] [Headers][X86] Reformat ia32intrin.h doc to match the other headers (#77525) Doxygen comment style for every other intrinsic-function header uses /// comments, so change ia32intrin.h from the /** style to /// style. While I was in there, change ` INSTR ` to `\c INSTR` and toss in a few missing full-stops. --- clang/lib/Headers/ia32intrin.h | 376 ++++++++++++++++----------------- 1 file changed, 182 insertions(+), 194 deletions(-) diff --git a/clang/lib/Headers/ia32intrin.h b/clang/lib/Headers/ia32intrin.h index f1904efd71c4..a8b59dfaad89 100644 --- a/clang/lib/Headers/ia32intrin.h +++ b/clang/lib/Headers/ia32intrin.h @@ -26,51 +26,48 @@ #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS #endif -/** Find the first set bit starting from the lsb. Result is undefined if - * input is 0. - * - * \headerfile - * - * This intrinsic corresponds to the BSF instruction or the - * TZCNT instruction. - * - * \param __A - * A 32-bit integer operand. - * \returns A 32-bit integer containing the bit number. - */ +/// Find the first set bit starting from the lsb. Result is undefined if +/// input is 0. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BSF instruction or the +/// \c TZCNT instruction. +/// +/// \param __A +/// A 32-bit integer operand. +/// \returns A 32-bit integer containing the bit number. static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __bsfd(int __A) { return __builtin_ctz((unsigned int)__A); } -/** Find the first set bit starting from the msb. Result is undefined if - * input is 0. - * - * \headerfile - * - * This intrinsic corresponds to the BSR instruction or the - * LZCNT instruction and an XOR . - * - * \param __A - * A 32-bit integer operand. - * \returns A 32-bit integer containing the bit number. - */ +/// Find the first set bit starting from the msb. Result is undefined if +/// input is 0. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BSR instruction or the +/// \c LZCNT instruction and an \c XOR. +/// +/// \param __A +/// A 32-bit integer operand. +/// \returns A 32-bit integer containing the bit number. static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __bsrd(int __A) { return 31 - __builtin_clz((unsigned int)__A); } -/** Swaps the bytes in the input. Converting little endian to big endian or - * vice versa. - * - * \headerfile - * - * This intrinsic corresponds to the BSWAP instruction. - * - * \param __A - * A 32-bit integer operand. - * \returns A 32-bit integer containing the swapped bytes. - */ +/// Swaps the bytes in the input. Converting little endian to big endian or +/// vice versa. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BSWAP instruction. +/// +/// \param __A +/// A 32-bit integer operand. +/// \returns A 32-bit integer containing the swapped bytes. static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __bswapd(int __A) { return (int)__builtin_bswap32((unsigned int)__A); @@ -85,51 +82,48 @@ _bswap(int __A) { #define _bit_scan_reverse(A) __bsrd((A)) #ifdef __x86_64__ -/** Find the first set bit starting from the lsb. Result is undefined if - * input is 0. - * - * \headerfile - * - * This intrinsic corresponds to the BSF instruction or the - * TZCNT instruction. - * - * \param __A - * A 64-bit integer operand. - * \returns A 32-bit integer containing the bit number. - */ +/// Find the first set bit starting from the lsb. Result is undefined if +/// input is 0. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BSF instruction or the +/// \c TZCNT instruction. +/// +/// \param __A +/// A 64-bit integer operand. +/// \returns A 32-bit integer containing the bit number. static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __bsfq(long long __A) { return (long long)__builtin_ctzll((unsigned long long)__A); } -/** Find the first set bit starting from the msb. Result is undefined if - * input is 0. - * - * \headerfile - * - * This intrinsic corresponds to the BSR instruction or the - * LZCNT instruction and an XOR . - * - * \param __A - * A 64-bit integer operand. - * \returns A 32-bit integer containing the bit number. - */ +/// Find the first set bit starting from the msb. Result is undefined if +/// input is 0. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BSR instruction or the +/// \c LZCNT instruction and an \c XOR. +/// +/// \param __A +/// A 64-bit integer operand. +/// \returns A 32-bit integer containing the bit number. static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __bsrq(long long __A) { return 63 - __builtin_clzll((unsigned long long)__A); } -/** Swaps the bytes in the input. Converting little endian to big endian or - * vice versa. - * - * \headerfile - * - * This intrinsic corresponds to the BSWAP instruction. - * - * \param __A - * A 64-bit integer operand. - * \returns A 64-bit integer containing the swapped bytes. - */ +/// Swaps the bytes in the input. Converting little endian to big endian or +/// vice versa. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BSWAP instruction. +/// +/// \param __A +/// A 64-bit integer operand. +/// \returns A 64-bit integer containing the swapped bytes. static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR __bswapq(long long __A) { return (long long)__builtin_bswap64((unsigned long long)__A); @@ -138,18 +132,17 @@ __bswapq(long long __A) { #define _bswap64(A) __bswapq((A)) #endif -/** Counts the number of bits in the source operand having a value of 1. - * - * \headerfile - * - * This intrinsic corresponds to the POPCNT instruction or a - * a sequence of arithmetic and logic ops to calculate it. - * - * \param __A - * An unsigned 32-bit integer operand. - * \returns A 32-bit integer containing the number of bits with value 1 in the - * source operand. - */ +/// Counts the number of bits in the source operand having a value of 1. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c POPCNT instruction or a +/// a sequence of arithmetic and logic ops to calculate it. +/// +/// \param __A +/// An unsigned 32-bit integer operand. +/// \returns A 32-bit integer containing the number of bits with value 1 in the +/// source operand. static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __popcntd(unsigned int __A) { @@ -159,18 +152,17 @@ __popcntd(unsigned int __A) #define _popcnt32(A) __popcntd((A)) #ifdef __x86_64__ -/** Counts the number of bits in the source operand having a value of 1. - * - * \headerfile - * - * This intrinsic corresponds to the POPCNT instruction or a - * a sequence of arithmetic and logic ops to calculate it. - * - * \param __A - * An unsigned 64-bit integer operand. - * \returns A 64-bit integer containing the number of bits with value 1 in the - * source operand. - */ +/// Counts the number of bits in the source operand having a value of 1. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c POPCNT instruction or a +/// a sequence of arithmetic and logic ops to calculate it. +/// +/// \param __A +/// An unsigned 64-bit integer operand. +/// \returns A 64-bit integer containing the number of bits with value 1 in the +/// source operand. static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR __popcntq(unsigned long long __A) { @@ -207,123 +199,120 @@ __writeeflags(unsigned int __f) } #endif /* !__x86_64__ */ -/** Cast a 32-bit float value to a 32-bit unsigned integer value - * - * \headerfile - * This intrinsic corresponds to the VMOVD / MOVD instruction in x86_64, - * and corresponds to the VMOVL / MOVL instruction in ia32. - * - * \param __A - * A 32-bit float value. - * \returns a 32-bit unsigned integer containing the converted value. - */ +/// Cast a 32-bit float value to a 32-bit unsigned integer value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VMOVD / \c MOVD instruction in x86_64, +/// and corresponds to the \c VMOVL / \c MOVL instruction in ia32. +/// +/// \param __A +/// A 32-bit float value. +/// \returns a 32-bit unsigned integer containing the converted value. static __inline__ unsigned int __DEFAULT_FN_ATTRS_CAST _castf32_u32(float __A) { return __builtin_bit_cast(unsigned int, __A); } -/** Cast a 64-bit float value to a 64-bit unsigned integer value - * - * \headerfile - * This intrinsic corresponds to the VMOVQ / MOVQ instruction in x86_64, - * and corresponds to the VMOVL / MOVL instruction in ia32. - * - * \param __A - * A 64-bit float value. - * \returns a 64-bit unsigned integer containing the converted value. - */ +/// Cast a 64-bit float value to a 64-bit unsigned integer value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VMOVQ / \c MOVQ instruction in x86_64, +/// and corresponds to the \c VMOVL / \c MOVL instruction in ia32. +/// +/// \param __A +/// A 64-bit float value. +/// \returns a 64-bit unsigned integer containing the converted value. static __inline__ unsigned long long __DEFAULT_FN_ATTRS_CAST _castf64_u64(double __A) { return __builtin_bit_cast(unsigned long long, __A); } -/** Cast a 32-bit unsigned integer value to a 32-bit float value - * - * \headerfile - * This intrinsic corresponds to the VMOVQ / MOVQ instruction in x86_64, - * and corresponds to the FLDS instruction in ia32. - * - * \param __A - * A 32-bit unsigned integer value. - * \returns a 32-bit float value containing the converted value. - */ +/// Cast a 32-bit unsigned integer value to a 32-bit float value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VMOVQ / \c MOVQ instruction in x86_64, +/// and corresponds to the \c FLDS instruction in ia32. +/// +/// \param __A +/// A 32-bit unsigned integer value. +/// \returns a 32-bit float value containing the converted value. static __inline__ float __DEFAULT_FN_ATTRS_CAST _castu32_f32(unsigned int __A) { return __builtin_bit_cast(float, __A); } -/** Cast a 64-bit unsigned integer value to a 64-bit float value - * - * \headerfile - * This intrinsic corresponds to the VMOVQ / MOVQ instruction in x86_64, - * and corresponds to the FLDL instruction in ia32. - * - * \param __A - * A 64-bit unsigned integer value. - * \returns a 64-bit float value containing the converted value. - */ +/// Cast a 64-bit unsigned integer value to a 64-bit float value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VMOVQ / \c MOVQ instruction in x86_64, +/// and corresponds to the \c FLDL instruction in ia32. +/// +/// \param __A +/// A 64-bit unsigned integer value. +/// \returns a 64-bit float value containing the converted value. static __inline__ double __DEFAULT_FN_ATTRS_CAST _castu64_f64(unsigned long long __A) { return __builtin_bit_cast(double, __A); } -/** Adds the unsigned integer operand to the CRC-32C checksum of the - * unsigned char operand. - * - * \headerfile - * - * This intrinsic corresponds to the CRC32B instruction. - * - * \param __C - * An unsigned integer operand to add to the CRC-32C checksum of operand - * \a __D. - * \param __D - * An unsigned 8-bit integer operand used to compute the CRC-32C checksum. - * \returns The result of adding operand \a __C to the CRC-32C checksum of - * operand \a __D. - */ +/// Adds the unsigned integer operand to the CRC-32C checksum of the +/// unsigned char operand. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c CRC32B instruction. +/// +/// \param __C +/// An unsigned integer operand to add to the CRC-32C checksum of operand +/// \a __D. +/// \param __D +/// An unsigned 8-bit integer operand used to compute the CRC-32C checksum. +/// \returns The result of adding operand \a __C to the CRC-32C checksum of +/// operand \a __D. static __inline__ unsigned int __DEFAULT_FN_ATTRS_CRC32 __crc32b(unsigned int __C, unsigned char __D) { return __builtin_ia32_crc32qi(__C, __D); } -/** Adds the unsigned integer operand to the CRC-32C checksum of the - * unsigned short operand. - * - * \headerfile - * - * This intrinsic corresponds to the CRC32W instruction. - * - * \param __C - * An unsigned integer operand to add to the CRC-32C checksum of operand - * \a __D. - * \param __D - * An unsigned 16-bit integer operand used to compute the CRC-32C checksum. - * \returns The result of adding operand \a __C to the CRC-32C checksum of - * operand \a __D. - */ +/// Adds the unsigned integer operand to the CRC-32C checksum of the +/// unsigned short operand. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c CRC32W instruction. +/// +/// \param __C +/// An unsigned integer operand to add to the CRC-32C checksum of operand +/// \a __D. +/// \param __D +/// An unsigned 16-bit integer operand used to compute the CRC-32C checksum. +/// \returns The result of adding operand \a __C to the CRC-32C checksum of +/// operand \a __D. static __inline__ unsigned int __DEFAULT_FN_ATTRS_CRC32 __crc32w(unsigned int __C, unsigned short __D) { return __builtin_ia32_crc32hi(__C, __D); } -/** Adds the unsigned integer operand to the CRC-32C checksum of the - * second unsigned integer operand. - * - * \headerfile - * - * This intrinsic corresponds to the CRC32D instruction. - * - * \param __C - * An unsigned integer operand to add to the CRC-32C checksum of operand - * \a __D. - * \param __D - * An unsigned 32-bit integer operand used to compute the CRC-32C checksum. - * \returns The result of adding operand \a __C to the CRC-32C checksum of - * operand \a __D. - */ +/// Adds the unsigned integer operand to the CRC-32C checksum of the +/// second unsigned integer operand. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c CRC32D instruction. +/// +/// \param __C +/// An unsigned integer operand to add to the CRC-32C checksum of operand +/// \a __D. +/// \param __D +/// An unsigned 32-bit integer operand used to compute the CRC-32C checksum. +/// \returns The result of adding operand \a __C to the CRC-32C checksum of +/// operand \a __D. static __inline__ unsigned int __DEFAULT_FN_ATTRS_CRC32 __crc32d(unsigned int __C, unsigned int __D) { @@ -331,21 +320,20 @@ __crc32d(unsigned int __C, unsigned int __D) } #ifdef __x86_64__ -/** Adds the unsigned integer operand to the CRC-32C checksum of the - * unsigned 64-bit integer operand. - * - * \headerfile - * - * This intrinsic corresponds to the CRC32Q instruction. - * - * \param __C - * An unsigned integer operand to add to the CRC-32C checksum of operand - * \a __D. - * \param __D - * An unsigned 64-bit integer operand used to compute the CRC-32C checksum. - * \returns The result of adding operand \a __C to the CRC-32C checksum of - * operand \a __D. - */ +/// Adds the unsigned integer operand to the CRC-32C checksum of the +/// unsigned 64-bit integer operand. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c CRC32Q instruction. +/// +/// \param __C +/// An unsigned integer operand to add to the CRC-32C checksum of operand +/// \a __D. +/// \param __D +/// An unsigned 64-bit integer operand used to compute the CRC-32C checksum. +/// \returns The result of adding operand \a __C to the CRC-32C checksum of +/// operand \a __D. static __inline__ unsigned long long __DEFAULT_FN_ATTRS_CRC32 __crc32q(unsigned long long __C, unsigned long long __D) { -- GitLab From 0d6412eae32777cd892a1a9ed016a07e68eaa191 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Jan 2024 10:07:53 -0600 Subject: [PATCH 345/652] [Libomptarget] Add error message back in after changes (#77528) Summary: My previous reworking of the image hangling removed the image info which was originally used for this extra error message requested by Ye Luo. I have since added in the necessary ELF facilities to extract it from the object file and can add it back in. It's a little verbose mostly from needing to shuffle around types and potential errors. --- openmp/libomptarget/src/omptarget.cpp | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/openmp/libomptarget/src/omptarget.cpp b/openmp/libomptarget/src/omptarget.cpp index a7d55d7ebd53..fe226345ed24 100644 --- a/openmp/libomptarget/src/omptarget.cpp +++ b/openmp/libomptarget/src/omptarget.cpp @@ -18,6 +18,7 @@ #include "PluginManager.h" #include "Shared/Debug.h" #include "Shared/EnvironmentVar.h" +#include "Shared/Utils.h" #include "device.h" #include "private.h" #include "rtl.h" @@ -29,6 +30,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/bit.h" +#include "llvm/Object/ObjectFile.h" #include #include @@ -308,10 +310,32 @@ void handleTargetOutcome(bool Success, ident_t *Loc) { FAILURE_MESSAGE("Consult https://openmp.llvm.org/design/Runtimes.html " "for debugging options.\n"); - if (!PM->getNumUsedPlugins()) + if (!PM->getNumUsedPlugins()) { FAILURE_MESSAGE( "No images found compatible with the installed hardware. "); + llvm::SmallVector Archs; + for (auto &Image : PM->deviceImages()) { + const char *Start = reinterpret_cast( + Image.getExecutableImage().ImageStart); + uint64_t Length = llvm::omp::target::getPtrDiff( + Start, Image.getExecutableImage().ImageEnd); + llvm::MemoryBufferRef Buffer(llvm::StringRef(Start, Length), + /*Identifier=*/""); + + auto ObjectOrErr = llvm::object::ObjectFile::createObjectFile(Buffer); + if (auto Err = ObjectOrErr.takeError()) { + llvm::consumeError(std::move(Err)); + continue; + } + + if (auto CPU = (*ObjectOrErr)->tryGetCPUName()) + Archs.push_back(*CPU); + } + fprintf(stderr, "Found %zu image(s): (%s)\n", Archs.size(), + llvm::join(Archs, ",").c_str()); + } + SourceInfo Info(Loc); if (Info.isAvailible()) fprintf(stderr, "%s:%d:%d: ", Info.getFilename(), Info.getLine(), -- GitLab From d03b8c3a048262eae1b13be829e20971e1714ade Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Jan 2024 10:10:08 -0600 Subject: [PATCH 346/652] [Libomptarget][NFC] Format in-line comments consistently (#77530) Summary: The LLVM style uses /*Foo=*/ when indicating the name of a constant. See https://llvm.org/docs/CodingStandards.html#comment-formatting. This is useful for consistency, as well as because `clang-format` understands this syntax and formats it more cleanly. Do a bulk update of this syntax. --- openmp/libomptarget/DeviceRTL/include/State.h | 26 +++++----- openmp/libomptarget/DeviceRTL/src/Kernel.cpp | 4 +- .../DeviceRTL/src/Parallelism.cpp | 26 +++++----- .../libomptarget/DeviceRTL/src/Reduction.cpp | 2 +- openmp/libomptarget/include/Shared/Profile.h | 2 +- .../plugins-nextgen/amdgpu/src/rtl.cpp | 14 +++--- .../common/include/GlobalHandler.h | 8 ++-- .../plugins-nextgen/common/src/JIT.cpp | 8 ++-- .../common/src/PluginInterface.cpp | 48 ++++++++----------- .../plugins-nextgen/cuda/src/rtl.cpp | 8 ++-- .../generic-elf-64bit/src/rtl.cpp | 4 +- openmp/libomptarget/src/OpenMP/Mapping.cpp | 18 +++---- .../libomptarget/src/OpenMP/OMPT/Callback.cpp | 36 +++++++------- openmp/libomptarget/src/device.cpp | 8 ++-- openmp/libomptarget/src/interface.cpp | 6 +-- openmp/libomptarget/src/omptarget.cpp | 6 +-- .../kernelreplay/llvm-omp-kernel-replay.cpp | 24 +++++----- 17 files changed, 120 insertions(+), 128 deletions(-) diff --git a/openmp/libomptarget/DeviceRTL/include/State.h b/openmp/libomptarget/DeviceRTL/include/State.h index c93de4191f83..1a3490394458 100644 --- a/openmp/libomptarget/DeviceRTL/include/State.h +++ b/openmp/libomptarget/DeviceRTL/include/State.h @@ -240,29 +240,29 @@ lookupPtr(ValueKind Kind, bool IsReadonly, bool ForceTeamState) { /// update ICV values we can declare in global scope. template struct Value { [[gnu::flatten, gnu::always_inline]] operator Ty() { - return lookup(/* IsReadonly */ true, /* IdentTy */ nullptr, - /* ForceTeamState */ false); + return lookup(/*IsReadonly=*/true, /*IdentTy=*/nullptr, + /*ForceTeamState=*/false); } [[gnu::flatten, gnu::always_inline]] Value &operator=(const Ty &Other) { - set(Other, /* IdentTy */ nullptr); + set(Other, /*IdentTy=*/nullptr); return *this; } [[gnu::flatten, gnu::always_inline]] Value &operator++() { - inc(1, /* IdentTy */ nullptr); + inc(1, /*IdentTy=*/nullptr); return *this; } [[gnu::flatten, gnu::always_inline]] Value &operator--() { - inc(-1, /* IdentTy */ nullptr); + inc(-1, /*IdentTy=*/nullptr); return *this; } [[gnu::flatten, gnu::always_inline]] void assert_eq(const Ty &V, IdentTy *Ident = nullptr, bool ForceTeamState = false) { - ASSERT(lookup(/* IsReadonly */ true, Ident, ForceTeamState) == V, nullptr); + ASSERT(lookup(/*IsReadonly=*/true, Ident, ForceTeamState) == V, nullptr); } private: @@ -273,12 +273,12 @@ private: } [[gnu::flatten, gnu::always_inline]] Ty &inc(int UpdateVal, IdentTy *Ident) { - return (lookup(/* IsReadonly */ false, Ident, /* ForceTeamState */ false) += + return (lookup(/*IsReadonly=*/false, Ident, /*ForceTeamState=*/false) += UpdateVal); } [[gnu::flatten, gnu::always_inline]] Ty &set(Ty UpdateVal, IdentTy *Ident) { - return (lookup(/* IsReadonly */ false, Ident, /* ForceTeamState */ false) = + return (lookup(/*IsReadonly=*/false, Ident, /*ForceTeamState=*/false) = UpdateVal); } @@ -290,8 +290,8 @@ private: /// we can declare in global scope. template struct PtrValue { [[gnu::flatten, gnu::always_inline]] operator Ty() { - return lookup(/* IsReadonly */ true, /* IdentTy */ nullptr, - /* ForceTeamState */ false); + return lookup(/*IsReadonly=*/true, /*IdentTy=*/nullptr, + /*ForceTeamState=*/false); } [[gnu::flatten, gnu::always_inline]] PtrValue &operator=(const Ty Other) { @@ -305,8 +305,8 @@ private: } Ty &set(Ty UpdateVal) { - return (lookup(/* IsReadonly */ false, /* IdentTy */ nullptr, - /* ForceTeamState */ false) = UpdateVal); + return (lookup(/*IsReadonly=*/false, /*IdentTy=*/nullptr, + /*ForceTeamState=*/false) = UpdateVal); } template friend struct ValueRAII; @@ -315,7 +315,7 @@ private: template struct ValueRAII { ValueRAII(VTy &V, Ty NewValue, Ty OldValue, bool Active, IdentTy *Ident, bool ForceTeamState = false) - : Ptr(Active ? &V.lookup(/* IsReadonly */ false, Ident, ForceTeamState) + : Ptr(Active ? &V.lookup(/*IsReadonly=*/false, Ident, ForceTeamState) : (Ty *)utils::UndefPtr), Val(OldValue), Active(Active) { if (!Active) diff --git a/openmp/libomptarget/DeviceRTL/src/Kernel.cpp b/openmp/libomptarget/DeviceRTL/src/Kernel.cpp index 06b12fec2167..95d4c728016d 100644 --- a/openmp/libomptarget/DeviceRTL/src/Kernel.cpp +++ b/openmp/libomptarget/DeviceRTL/src/Kernel.cpp @@ -78,11 +78,11 @@ int32_t __kmpc_target_init(KernelEnvironmentTy &KernelEnvironment, llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD; bool UseGenericStateMachine = Configuration.UseGenericStateMachine; if (IsSPMD) { - inititializeRuntime(/* IsSPMD */ true, KernelEnvironment, + inititializeRuntime(/*IsSPMD=*/true, KernelEnvironment, KernelLaunchEnvironment); synchronize::threadsAligned(atomic::relaxed); } else { - inititializeRuntime(/* IsSPMD */ false, KernelEnvironment, + inititializeRuntime(/*IsSPMD=*/false, KernelEnvironment, KernelLaunchEnvironment); // No need to wait since only the main threads will execute user // code and workers will run into a barrier right away. diff --git a/openmp/libomptarget/DeviceRTL/src/Parallelism.cpp b/openmp/libomptarget/DeviceRTL/src/Parallelism.cpp index 2c0701bd5358..7005477bf4c7 100644 --- a/openmp/libomptarget/DeviceRTL/src/Parallelism.cpp +++ b/openmp/libomptarget/DeviceRTL/src/Parallelism.cpp @@ -121,20 +121,20 @@ __kmpc_parallel_51(IdentTy *ident, int32_t, int32_t if_expr, // created. state::ValueRAII ParallelTeamSizeRAII(state::ParallelTeamSize, PTeamSize, 1u, TId == 0, ident, - /* ForceTeamState */ true); + /*ForceTeamState=*/true); state::ValueRAII ActiveLevelRAII(icv::ActiveLevel, 1u, 0u, TId == 0, - ident, /* ForceTeamState */ true); + ident, /*ForceTeamState=*/true); state::ValueRAII LevelRAII(icv::Level, 1u, 0u, TId == 0, ident, - /* ForceTeamState */ true); + /*ForceTeamState=*/true); // Synchronize all threads after the main thread (TId == 0) set up the // team state properly. synchronize::threadsAligned(atomic::acq_rel); state::ParallelTeamSize.assert_eq(PTeamSize, ident, - /* ForceTeamState */ true); - icv::ActiveLevel.assert_eq(1u, ident, /* ForceTeamState */ true); - icv::Level.assert_eq(1u, ident, /* ForceTeamState */ true); + /*ForceTeamState=*/true); + icv::ActiveLevel.assert_eq(1u, ident, /*ForceTeamState=*/true); + icv::Level.assert_eq(1u, ident, /*ForceTeamState=*/true); // Ensure we synchronize before we run user code to avoid invalidating the // assumptions above. @@ -152,9 +152,9 @@ __kmpc_parallel_51(IdentTy *ident, int32_t, int32_t if_expr, // __kmpc_target_deinit may not hold. synchronize::threadsAligned(atomic::acq_rel); - state::ParallelTeamSize.assert_eq(1u, ident, /* ForceTeamState */ true); - icv::ActiveLevel.assert_eq(0u, ident, /* ForceTeamState */ true); - icv::Level.assert_eq(0u, ident, /* ForceTeamState */ true); + state::ParallelTeamSize.assert_eq(1u, ident, /*ForceTeamState=*/true); + icv::ActiveLevel.assert_eq(0u, ident, /*ForceTeamState=*/true); + icv::Level.assert_eq(0u, ident, /*ForceTeamState=*/true); // Ensure we synchronize to create an aligned region around the assumptions. synchronize::threadsAligned(atomic::relaxed); @@ -242,14 +242,14 @@ __kmpc_parallel_51(IdentTy *ident, int32_t, int32_t if_expr, // created. state::ValueRAII ParallelTeamSizeRAII(state::ParallelTeamSize, PTeamSize, 1u, true, ident, - /* ForceTeamState */ true); + /*ForceTeamState=*/true); state::ValueRAII ParallelRegionFnRAII(state::ParallelRegionFn, wrapper_fn, (void *)nullptr, true, ident, - /* ForceTeamState */ true); + /*ForceTeamState=*/true); state::ValueRAII ActiveLevelRAII(icv::ActiveLevel, 1u, 0u, true, ident, - /* ForceTeamState */ true); + /*ForceTeamState=*/true); state::ValueRAII LevelRAII(icv::Level, 1u, 0u, true, ident, - /* ForceTeamState */ true); + /*ForceTeamState=*/true); // Master signals work to activate workers. synchronize::threads(atomic::seq_cst); diff --git a/openmp/libomptarget/DeviceRTL/src/Reduction.cpp b/openmp/libomptarget/DeviceRTL/src/Reduction.cpp index 0a9db3edabcc..744d1a3a231c 100644 --- a/openmp/libomptarget/DeviceRTL/src/Reduction.cpp +++ b/openmp/libomptarget/DeviceRTL/src/Reduction.cpp @@ -69,7 +69,7 @@ static int32_t nvptx_parallel_reduce_nowait(void *reduce_data, ShuffleReductFnTy shflFct, InterWarpCopyFnTy cpyFct) { uint32_t BlockThreadId = mapping::getThreadIdInBlock(); - if (mapping::isMainThreadInGenericMode(/* IsSPMD */ false)) + if (mapping::isMainThreadInGenericMode(/*IsSPMD=*/false)) BlockThreadId = 0; uint32_t NumThreads = omp_get_num_threads(); if (NumThreads == 1) diff --git a/openmp/libomptarget/include/Shared/Profile.h b/openmp/libomptarget/include/Shared/Profile.h index 7e580988a39b..39817bab36cb 100644 --- a/openmp/libomptarget/include/Shared/Profile.h +++ b/openmp/libomptarget/include/Shared/Profile.h @@ -32,7 +32,7 @@ class Profiler { Int32Envar ProfileGranularity = Int32Envar("LIBOMPTARGET_PROFILE_GRANULARITY", 500); - llvm::timeTraceProfilerInitialize(ProfileGranularity /* us */, + llvm::timeTraceProfilerInitialize(ProfileGranularity /*us=*/, "libomptarget"); } diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp index b67642e9e1bc..8424d0f5df08 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp @@ -2211,10 +2211,9 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { hsa_amd_pointer_info_t Info; Info.size = sizeof(hsa_amd_pointer_info_t); - hsa_status_t Status = - hsa_amd_pointer_info(HstPtr, &Info, /* Allocator */ nullptr, - /* Number of accessible agents (out) */ nullptr, - /* Accessible agents */ nullptr); + hsa_status_t Status = hsa_amd_pointer_info( + HstPtr, &Info, /*Allocator=*/nullptr, /*num_agents_accessible=*/nullptr, + /*accessible=*/nullptr); if (auto Err = Plugin::check(Status, "Error in hsa_amd_pointer_info: %s")) return std::move(Err); @@ -2789,7 +2788,7 @@ private: AMDHostDeviceTy &HostDevice; /// The current size of the global device memory pool (managed by us). - uint64_t DeviceMemoryPoolSize = 1L << 29L /* 512MB */; + uint64_t DeviceMemoryPoolSize = 1L << 29L /*512MB=*/; /// The current size of the stack that will be used in cases where it could /// not be statically determined. @@ -3031,9 +3030,8 @@ struct AMDGPUPluginTy final : public GenericPluginTy { /// Check whether the image is compatible with an AMDGPU device. Expected isELFCompatible(StringRef Image) const override { // Get the associated architecture and flags from the ELF. - auto ElfOrErr = - ELF64LEObjectFile::create(MemoryBufferRef(Image, /*Identifier=*/""), - /*InitContent=*/false); + auto ElfOrErr = ELF64LEObjectFile::create( + MemoryBufferRef(Image, /*Identifier=*/""), /*InitContent=*/false); if (!ElfOrErr) return ElfOrErr.takeError(); std::optional Processor = ElfOrErr->tryGetCPUName(); diff --git a/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h b/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h index d9fe938790ca..8707e7b4c504 100644 --- a/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h +++ b/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h @@ -138,7 +138,7 @@ public: const GlobalTy &HostGlobal, const GlobalTy &DeviceGlobal) { return moveGlobalBetweenDeviceAndHost(Device, HostGlobal, DeviceGlobal, - /* D2H */ true); + /*D2H=*/true); } /// Copy the memory associated with a global from the device to its @@ -147,7 +147,7 @@ public: Error readGlobalFromDevice(GenericDeviceTy &Device, DeviceImageTy &Image, const GlobalTy &HostGlobal) { return moveGlobalBetweenDeviceAndHost(Device, Image, HostGlobal, - /* D2H */ true); + /*D2H=*/true); } /// Copy the memory associated with a global from the host to its counterpart @@ -156,7 +156,7 @@ public: Error writeGlobalToDevice(GenericDeviceTy &Device, const GlobalTy &HostGlobal, const GlobalTy &DeviceGlobal) { return moveGlobalBetweenDeviceAndHost(Device, HostGlobal, DeviceGlobal, - /* D2H */ false); + /*D2H=*/false); } /// Copy the memory associated with a global from the host to its counterpart @@ -165,7 +165,7 @@ public: Error writeGlobalToDevice(GenericDeviceTy &Device, DeviceImageTy &Image, const GlobalTy &HostGlobal) { return moveGlobalBetweenDeviceAndHost(Device, Image, HostGlobal, - /* D2H */ false); + /*D2H=*/false); } }; diff --git a/openmp/libomptarget/plugins-nextgen/common/src/JIT.cpp b/openmp/libomptarget/plugins-nextgen/common/src/JIT.cpp index 7275be4edfca..9eb610cab4de 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/JIT.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/JIT.cpp @@ -93,7 +93,7 @@ createModuleFromImage(const __tgt_device_image &Image, LLVMContext &Context) { StringRef Data((const char *)Image.ImageStart, target::getPtrDiff(Image.ImageEnd, Image.ImageStart)); std::unique_ptr MB = MemoryBuffer::getMemBuffer( - Data, /* BufferName */ "", /* RequiresNullTerminator */ false); + Data, /*BufferName=*/"", /*RequiresNullTerminator=*/false); return createModuleFromMemoryBuffer(MB, Context); } @@ -186,7 +186,7 @@ void JITEngine::codegen(TargetMachine *TM, TargetLibraryInfoImpl *TLII, TM->addPassesToEmitFile(PM, OS, nullptr, TT.isNVPTX() ? CodeGenFileType::AssemblyFile : CodeGenFileType::ObjectFile, - /* DisableVerify */ false, MMIWP); + /*DisableVerify=*/false, MMIWP); PM.run(M); } @@ -196,8 +196,8 @@ JITEngine::backend(Module &M, const std::string &ComputeUnitKind, unsigned OptLevel) { auto RemarksFileOrErr = setupLLVMOptimizationRemarks( - M.getContext(), /* RemarksFilename */ "", /* RemarksPasses */ "", - /* RemarksFormat */ "", /* RemarksWithHotness */ false); + M.getContext(), /*RemarksFilename=*/"", /*RemarksPasses=*/"", + /*RemarksFormat=*/"", /*RemarksWithHotness=*/false); if (Error E = RemarksFileOrErr.takeError()) return std::move(E); if (*RemarksFileOrErr) diff --git a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp index 9490e58fc669..0db7910ec105 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp @@ -64,7 +64,7 @@ private: void *suggestAddress(uint64_t MaxMemoryAllocation) { // Get a valid pointer address for this system void *Addr = - Device->allocate(1024, /* HstPtr */ nullptr, TARGET_ALLOC_DEFAULT); + Device->allocate(1024, /*HstPtr=*/nullptr, TARGET_ALLOC_DEFAULT); Device->free(Addr); // Align Address to MaxMemoryAllocation Addr = (void *)alignPtr((Addr), MaxMemoryAllocation); @@ -104,8 +104,8 @@ private: constexpr size_t STEP = 1024 * 1024 * 1024ULL; MemoryStart = nullptr; for (TotalSize = MAX_MEMORY_ALLOCATION; TotalSize > 0; TotalSize -= STEP) { - MemoryStart = Device->allocate(TotalSize, /* HstPtr */ nullptr, - TARGET_ALLOC_DEFAULT); + MemoryStart = + Device->allocate(TotalSize, /*HstPtr=*/nullptr, TARGET_ALLOC_DEFAULT); if (MemoryStart) break; } @@ -214,8 +214,8 @@ public: for (auto &OffloadEntry : Image.getOffloadEntryTable()) { if (!OffloadEntry.size) continue; - Size += std::strlen(OffloadEntry.name) + /* '\0' */ 1 + - /* OffloadEntry.size value */ sizeof(uint32_t) + + // Get the total size of the string and entry including the null byte. + Size += std::strlen(OffloadEntry.name) + 1 + sizeof(uint32_t) + OffloadEntry.size; } @@ -735,13 +735,12 @@ Error GenericDeviceTy::init(GenericPluginTy &Plugin) { if (ompt::Initialized) { bool ExpectedStatus = false; if (OmptInitialized.compare_exchange_strong(ExpectedStatus, true)) - performOmptCallback(device_initialize, - /* device_num */ DeviceId + - Plugin.getDeviceIdStartIndex(), - /* type */ getComputeUnitKind().c_str(), - /* device */ reinterpret_cast(this), - /* lookup */ ompt::lookupCallbackByName, - /* documentation */ nullptr); + performOmptCallback(device_initialize, /*device_num=*/DeviceId + + Plugin.getDeviceIdStartIndex(), + /*type=*/getComputeUnitKind().c_str(), + /*device=*/reinterpret_cast(this), + /*lookup=*/ompt::lookupCallbackByName, + /*documentation=*/nullptr); } #endif @@ -835,7 +834,7 @@ Error GenericDeviceTy::deinit(GenericPluginTy &Plugin) { bool ExpectedStatus = true; if (OmptInitialized.compare_exchange_strong(ExpectedStatus, false)) performOmptCallback(device_finalize, - /* device_num */ DeviceId + + /*device_num=*/DeviceId + Plugin.getDeviceIdStartIndex()); } #endif @@ -897,16 +896,11 @@ GenericDeviceTy::loadBinary(GenericPluginTy &Plugin, if (ompt::Initialized) { size_t Bytes = getPtrDiff(InputTgtImage->ImageEnd, InputTgtImage->ImageStart); - performOmptCallback(device_load, - /* device_num */ DeviceId + - Plugin.getDeviceIdStartIndex(), - /* FileName */ nullptr, - /* File Offset */ 0, - /* VmaInFile */ nullptr, - /* ImgSize */ Bytes, - /* HostAddr */ InputTgtImage->ImageStart, - /* DeviceAddr */ nullptr, - /* FIXME: ModuleId */ 0); + performOmptCallback( + device_load, /*device_num=*/DeviceId + Plugin.getDeviceIdStartIndex(), + /*FileName=*/nullptr, /*FileOffset=*/0, /*VmaInFile=*/nullptr, + /*ImgSize=*/Bytes, /*HostAddr=*/InputTgtImage->ImageStart, + /*DeviceAddr=*/nullptr, /* FIXME: ModuleId */ 0); } #endif @@ -1293,7 +1287,7 @@ Error PinnedAllocationMapTy::lockMappedHostBuffer(void *HstPtr, size_t Size) { // If pinned, just insert the entry representing the whole pinned buffer. if (*IsPinnedOrErr) return insertEntry(BaseHstPtr, BaseDevAccessiblePtr, BaseSize, - /* Externally locked */ true); + /*Externallylocked=*/true); // Not externally pinned. Do nothing if locking of mapped buffers is disabled. if (!LockMappedBuffers) @@ -1863,7 +1857,7 @@ int32_t __tgt_rtl_data_notify_unmapped(int32_t DeviceId, void *HstPtr) { int32_t __tgt_rtl_data_submit(int32_t DeviceId, void *TgtPtr, void *HstPtr, int64_t Size) { return __tgt_rtl_data_submit_async(DeviceId, TgtPtr, HstPtr, Size, - /* AsyncInfoPtr */ nullptr); + /*AsyncInfoPtr=*/nullptr); } int32_t __tgt_rtl_data_submit_async(int32_t DeviceId, void *TgtPtr, @@ -1885,7 +1879,7 @@ int32_t __tgt_rtl_data_submit_async(int32_t DeviceId, void *TgtPtr, int32_t __tgt_rtl_data_retrieve(int32_t DeviceId, void *HstPtr, void *TgtPtr, int64_t Size) { return __tgt_rtl_data_retrieve_async(DeviceId, HstPtr, TgtPtr, Size, - /* AsyncInfoPtr */ nullptr); + /*AsyncInfoPtr=*/nullptr); } int32_t __tgt_rtl_data_retrieve_async(int32_t DeviceId, void *HstPtr, @@ -1909,7 +1903,7 @@ int32_t __tgt_rtl_data_exchange(int32_t SrcDeviceId, void *SrcPtr, int64_t Size) { return __tgt_rtl_data_exchange_async(SrcDeviceId, SrcPtr, DstDeviceId, DstPtr, Size, - /* AsyncInfoPtr */ nullptr); + /*AsyncInfoPtr=*/nullptr); } int32_t __tgt_rtl_data_exchange_async(int32_t SrcDeviceId, void *SrcPtr, diff --git a/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp index 0005bff7a803..fb51f96c07b7 100644 --- a/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp @@ -1216,10 +1216,10 @@ Error CUDAKernelTy::launchImpl(GenericDeviceTy &GenericDevice, std::max(KernelArgs.DynCGroupMem, GenericDevice.getDynamicMemorySize()); CUresult Res = - cuLaunchKernel(Func, NumBlocks, /* gridDimY */ 1, - /* gridDimZ */ 1, NumThreads, - /* blockDimY */ 1, /* blockDimZ */ 1, MaxDynCGroupMem, - Stream, (void **)Args, nullptr); + cuLaunchKernel(Func, NumBlocks, /*gridDimY=*/1, + /*gridDimZ=*/1, NumThreads, + /*blockDimY=*/1, /*blockDimZ=*/1, MaxDynCGroupMem, Stream, + (void **)Args, nullptr); return Plugin::check(Res, "Error in cuLaunchKernel for '%s': %s", getName()); } diff --git a/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp index 7f66b6827bce..6466afc543b5 100644 --- a/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/generic-elf-64bit/src/rtl.cpp @@ -73,8 +73,8 @@ struct GenELF64KernelTy : public GenericKernelTy { Func = (void (*)())Global.getPtr(); KernelEnvironment.Configuration.ExecMode = OMP_TGT_EXEC_MODE_GENERIC; - KernelEnvironment.Configuration.MayUseNestedParallelism = /* Unknown */ 2; - KernelEnvironment.Configuration.UseGenericStateMachine = /* Unknown */ 2; + KernelEnvironment.Configuration.MayUseNestedParallelism = /*Unknown=*/2; + KernelEnvironment.Configuration.UseGenericStateMachine = /*Unknown=*/2; // Set the maximum number of threads to a single. MaxNumThreads = 1; diff --git a/openmp/libomptarget/src/OpenMP/Mapping.cpp b/openmp/libomptarget/src/OpenMP/Mapping.cpp index a5c24810e0af..833856f2abf2 100644 --- a/openmp/libomptarget/src/OpenMP/Mapping.cpp +++ b/openmp/libomptarget/src/OpenMP/Mapping.cpp @@ -303,9 +303,9 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( // Notify the plugin about the new mapping. if (Device.notifyDataMapped(HstPtrBegin, Size)) - return {{false /* IsNewEntry */, false /* IsHostPointer */}, - nullptr /* Entry */, - nullptr /* TargetPointer */}; + return {{false /*IsNewEntry=*/, false /*IsHostPointer=*/}, + nullptr /*Entry=*/, + nullptr /*TargetPointer=*/}; } else { // This entry is not present and we did not create a new entry for it. LR.TPR.Flags.IsPresent = false; @@ -333,9 +333,9 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( LR.TPR.TargetPointer = nullptr; } else if (LR.TPR.getEntry()->addEventIfNecessary(Device, AsyncInfo) != OFFLOAD_SUCCESS) - return {{false /* IsNewEntry */, false /* IsHostPointer */}, - nullptr /* Entry */, - nullptr /* TargetPointer */}; + return {{false /*IsNewEntry=*/, false /*IsHostPointer=*/}, + nullptr /*Entry=*/, + nullptr /*TargetPointer=*/}; } else { // If not a host pointer and no present modifier, we need to wait for the // event if it exists. @@ -349,9 +349,9 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( // If it fails to wait for the event, we need to return nullptr in // case of any data race. REPORT("Failed to wait for event " DPxMOD ".\n", DPxPTR(Event)); - return {{false /* IsNewEntry */, false /* IsHostPointer */}, - nullptr /* Entry */, - nullptr /* TargetPointer */}; + return {{false /*IsNewEntry=*/, false /*IsHostPointer=*/}, + nullptr /*Entry=*/, + nullptr /*TargetPointer=*/}; } } } diff --git a/openmp/libomptarget/src/OpenMP/OMPT/Callback.cpp b/openmp/libomptarget/src/OpenMP/OMPT/Callback.cpp index da955e101956..82934f10486c 100644 --- a/openmp/libomptarget/src/OpenMP/OMPT/Callback.cpp +++ b/openmp/libomptarget/src/OpenMP/OMPT/Callback.cpp @@ -88,16 +88,16 @@ void Interface::beginTargetDataAlloc(int64_t DeviceId, void *HstPtrBegin, ompt_callback_target_data_op_emi_fn( ompt_scope_begin, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_alloc, HstPtrBegin, - /* SrcDeviceNum */ omp_get_initial_device(), *TgtPtrBegin, - /* TgtDeviceNum */ DeviceId, Size, Code); + /*SrcDeviceNum=*/omp_get_initial_device(), *TgtPtrBegin, + /*TgtDeviceNum=*/DeviceId, Size, Code); } else if (ompt_callback_target_data_op_fn) { // HostOpId is set by the runtime HostOpId = createOpId(); // Invoke the tool supplied data op callback ompt_callback_target_data_op_fn( TargetData.value, HostOpId, ompt_target_data_alloc, HstPtrBegin, - /* SrcDeviceNum */ omp_get_initial_device(), *TgtPtrBegin, - /* TgtDeviceNum */ DeviceId, Size, Code); + /*SrcDeviceNum=*/omp_get_initial_device(), *TgtPtrBegin, + /*TgtDeviceNum=*/DeviceId, Size, Code); } } @@ -111,8 +111,8 @@ void Interface::endTargetDataAlloc(int64_t DeviceId, void *HstPtrBegin, ompt_callback_target_data_op_emi_fn( ompt_scope_end, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_alloc, HstPtrBegin, - /* SrcDeviceNum */ omp_get_initial_device(), *TgtPtrBegin, - /* TgtDeviceNum */ DeviceId, Size, Code); + /*SrcDeviceNum=*/omp_get_initial_device(), *TgtPtrBegin, + /*TgtDeviceNum=*/DeviceId, Size, Code); } endTargetDataOperation(); } @@ -127,15 +127,15 @@ void Interface::beginTargetDataSubmit(int64_t DeviceId, void *TgtPtrBegin, ompt_callback_target_data_op_emi_fn( ompt_scope_begin, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_transfer_to_device, HstPtrBegin, - /* SrcDeviceNum */ omp_get_initial_device(), TgtPtrBegin, DeviceId, - Size, Code); + /*SrcDeviceNum=*/omp_get_initial_device(), TgtPtrBegin, DeviceId, Size, + Code); } else if (ompt_callback_target_data_op_fn) { // HostOpId is set by the runtime HostOpId = createOpId(); // Invoke the tool supplied data op callback ompt_callback_target_data_op_fn( TargetData.value, HostOpId, ompt_target_data_transfer_to_device, - HstPtrBegin, /* SrcDeviceNum */ omp_get_initial_device(), TgtPtrBegin, + HstPtrBegin, /*SrcDeviceNum=*/omp_get_initial_device(), TgtPtrBegin, DeviceId, Size, Code); } } @@ -150,8 +150,8 @@ void Interface::endTargetDataSubmit(int64_t DeviceId, void *TgtPtrBegin, ompt_callback_target_data_op_emi_fn( ompt_scope_end, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_transfer_to_device, HstPtrBegin, - /* SrcDeviceNum */ omp_get_initial_device(), TgtPtrBegin, DeviceId, - Size, Code); + /*SrcDeviceNum=*/omp_get_initial_device(), TgtPtrBegin, DeviceId, Size, + Code); } endTargetDataOperation(); } @@ -165,15 +165,15 @@ void Interface::beginTargetDataDelete(int64_t DeviceId, void *TgtPtrBegin, ompt_callback_target_data_op_emi_fn( ompt_scope_begin, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_delete, TgtPtrBegin, DeviceId, - /* TgtPtrBegin */ nullptr, /* TgtDeviceNum */ -1, /* Bytes */ 0, Code); + /*TgtPtrBegin=*/nullptr, /*TgtDeviceNum=*/-1, /*Bytes=*/0, Code); } else if (ompt_callback_target_data_op_fn) { // HostOpId is set by the runtime HostOpId = createOpId(); // Invoke the tool supplied data op callback ompt_callback_target_data_op_fn(TargetData.value, HostOpId, ompt_target_data_delete, TgtPtrBegin, - DeviceId, /* TgtPtrBegin */ nullptr, - /* TgtDeviceNum */ -1, /* Bytes */ 0, Code); + DeviceId, /*TgtPtrBegin=*/nullptr, + /*TgtDeviceNum=*/-1, /*Bytes=*/0, Code); } } @@ -186,7 +186,7 @@ void Interface::endTargetDataDelete(int64_t DeviceId, void *TgtPtrBegin, ompt_callback_target_data_op_emi_fn( ompt_scope_end, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_delete, TgtPtrBegin, DeviceId, - /* TgtPtrBegin */ nullptr, /* TgtDeviceNum */ -1, /* Bytes */ 0, Code); + /*TgtPtrBegin=*/nullptr, /*TgtDeviceNum=*/-1, /*Bytes=*/0, Code); } endTargetDataOperation(); } @@ -202,7 +202,7 @@ void Interface::beginTargetDataRetrieve(int64_t DeviceId, void *HstPtrBegin, ompt_scope_begin, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_transfer_from_device, TgtPtrBegin, DeviceId, HstPtrBegin, - /* TgtDeviceNum */ omp_get_initial_device(), Size, Code); + /*TgtDeviceNum=*/omp_get_initial_device(), Size, Code); } else if (ompt_callback_target_data_op_fn) { // HostOpId is set by the runtime HostOpId = createOpId(); @@ -210,7 +210,7 @@ void Interface::beginTargetDataRetrieve(int64_t DeviceId, void *HstPtrBegin, ompt_callback_target_data_op_fn( TargetData.value, HostOpId, ompt_target_data_transfer_from_device, TgtPtrBegin, DeviceId, HstPtrBegin, - /* TgtDeviceNum */ omp_get_initial_device(), Size, Code); + /*TgtDeviceNum=*/omp_get_initial_device(), Size, Code); } } @@ -225,7 +225,7 @@ void Interface::endTargetDataRetrieve(int64_t DeviceId, void *HstPtrBegin, ompt_scope_end, TargetTaskData, &TargetData, &HostOpId, ompt_target_data_transfer_from_device, TgtPtrBegin, DeviceId, HstPtrBegin, - /* TgtDeviceNum */ omp_get_initial_device(), Size, Code); + /*TgtDeviceNum=*/omp_get_initial_device(), Size, Code); } endTargetDataOperation(); } diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index fa8932361a51..654efd524024 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -117,7 +117,7 @@ void *DeviceTy::allocData(int64_t Size, void *HstPtr, int32_t Kind) { OMPT_IF_BUILT(InterfaceRAII TargetDataAllocRAII( RegionInterface.getCallbacks(), DeviceID, HstPtr, &TargetPtr, Size, - /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS(0));) TargetPtr = RTL->data_alloc(RTLDeviceID, Size, HstPtr, Kind); return TargetPtr; @@ -128,7 +128,7 @@ int32_t DeviceTy::deleteData(void *TgtAllocBegin, int32_t Kind) { OMPT_IF_BUILT(InterfaceRAII TargetDataDeleteRAII( RegionInterface.getCallbacks(), DeviceID, TgtAllocBegin, - /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS(0));) return RTL->data_delete(RTLDeviceID, TgtAllocBegin, Kind); } @@ -146,7 +146,7 @@ int32_t DeviceTy::submitData(void *TgtPtrBegin, void *HstPtrBegin, int64_t Size, InterfaceRAII TargetDataSubmitRAII( RegionInterface.getCallbacks(), DeviceID, TgtPtrBegin, HstPtrBegin, Size, - /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS(0));) if (!AsyncInfo || !RTL->data_submit_async || !RTL->synchronize) return RTL->data_submit(RTLDeviceID, TgtPtrBegin, HstPtrBegin, Size); @@ -168,7 +168,7 @@ int32_t DeviceTy::retrieveData(void *HstPtrBegin, void *TgtPtrBegin, InterfaceRAII TargetDataRetrieveRAII( RegionInterface.getCallbacks(), DeviceID, HstPtrBegin, TgtPtrBegin, Size, - /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS(0));) if (!RTL->data_retrieve_async || !RTL->synchronize) return RTL->data_retrieve(RTLDeviceID, HstPtrBegin, TgtPtrBegin, Size); diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp index 61d9db17f510..49495ac266f1 100644 --- a/openmp/libomptarget/src/interface.cpp +++ b/openmp/libomptarget/src/interface.cpp @@ -113,7 +113,7 @@ targetData(ident_t *Loc, int64_t DeviceId, int32_t ArgNum, void **ArgsBase, int Rc = OFFLOAD_SUCCESS; Rc = TargetDataFunction(Loc, *DeviceOrErr, ArgNum, ArgsBase, Args, ArgSizes, ArgTypes, ArgNames, ArgMappers, AsyncInfo, - false /* FromMapper */); + false /*FromMapper=*/); if (Rc == OFFLOAD_SUCCESS) Rc = AsyncInfo.synchronize(); @@ -293,7 +293,7 @@ static inline int targetKernel(ident_t *Loc, int64_t DeviceId, int32_t NumTeams, /// RAII to establish tool anchors before and after target region OMPT_IF_BUILT(InterfaceRAII TargetRAII( RegionInterface.getCallbacks(), DeviceId, - /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS(0));) int Rc = OFFLOAD_SUCCESS; Rc = target(Loc, *DeviceOrErr, HostPtr, *KernelArgs, AsyncInfo); @@ -387,7 +387,7 @@ EXTERN int __tgt_target_kernel_replay(ident_t *Loc, int64_t DeviceId, /// RAII to establish tool anchors before and after target region OMPT_IF_BUILT(InterfaceRAII TargetRAII( RegionInterface.getCallbacks(), DeviceId, - /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS(0));) AsyncInfoTy AsyncInfo(*DeviceOrErr); int Rc = target_replay(Loc, *DeviceOrErr, HostPtr, DeviceMemory, diff --git a/openmp/libomptarget/src/omptarget.cpp b/openmp/libomptarget/src/omptarget.cpp index fe226345ed24..eb2ecfc2bc56 100644 --- a/openmp/libomptarget/src/omptarget.cpp +++ b/openmp/libomptarget/src/omptarget.cpp @@ -227,7 +227,7 @@ static int initLibrary(DeviceTy &Device) { AsyncInfoTy AsyncInfo(Device); void *DevPtr; Device.retrieveData(&DevPtr, CurrDeviceEntryAddr, sizeof(void *), - AsyncInfo, /* Entry */ nullptr, &HDTTMap); + AsyncInfo, /*Entry=*/nullptr, &HDTTMap); if (AsyncInfo.synchronize() != OFFLOAD_SUCCESS) return OFFLOAD_FAIL; CurrDeviceEntryAddr = DevPtr; @@ -641,7 +641,7 @@ int targetDataBegin(ident_t *Loc, DeviceTy &Device, int32_t ArgNum, /*HstPtrName=*/nullptr, /*HasFlagTo=*/false, /*HasFlagAlways=*/false, IsImplicit, UpdateRef, HasCloseModifier, HasPresentModifier, HasHoldModifier, AsyncInfo, - /* OwnedTPR */ nullptr, /* ReleaseHDTTMap */ false); + /*OwnedTPR=*/nullptr, /*ReleaseHDTTMap=*/false); PointerTgtPtrBegin = PointerTpr.TargetPointer; IsHostPtr = PointerTpr.Flags.IsHostPointer; if (!PointerTgtPtrBegin) { @@ -1747,7 +1747,7 @@ int target_replay(ident_t *Loc, DeviceTy &Device, void *HostPtr, DP("Launching target execution %s with pointer " DPxMOD " (index=%d).\n", TargetTable->EntriesBegin[TM->Index].name, DPxPTR(TgtEntryPtr), TM->Index); - void *TgtPtr = Device.allocData(DeviceMemorySize, /* HstPtr */ nullptr, + void *TgtPtr = Device.allocData(DeviceMemorySize, /*HstPtr=*/nullptr, TARGET_ALLOC_DEFAULT); Device.submitData(TgtPtr, DeviceMemory, DeviceMemorySize, AsyncInfo); diff --git a/openmp/libomptarget/tools/kernelreplay/llvm-omp-kernel-replay.cpp b/openmp/libomptarget/tools/kernelreplay/llvm-omp-kernel-replay.cpp index fc3ff078a81f..761e04e4c7bb 100644 --- a/openmp/libomptarget/tools/kernelreplay/llvm-omp-kernel-replay.cpp +++ b/openmp/libomptarget/tools/kernelreplay/llvm-omp-kernel-replay.cpp @@ -57,8 +57,8 @@ int main(int argc, char **argv) { cl::ParseCommandLineOptions(argc, argv, "llvm-omp-kernel-replay\n"); ErrorOr> KernelInfoMB = - MemoryBuffer::getFile(InputFilename, /* isText */ true, - /* RequiresNullTerminator */ true); + MemoryBuffer::getFile(InputFilename, /*isText=*/true, + /*RequiresNullTerminator=*/true); if (!KernelInfoMB) report_fatal_error("Error reading the kernel info json file"); Expected JsonKernelInfo = @@ -100,8 +100,8 @@ int main(int argc, char **argv) { KernelEntry.addr = (void *)0x1; ErrorOr> ImageMB = - MemoryBuffer::getFile(KernelEntryName + ".image", /* isText */ false, - /* RequiresNullTerminator */ false); + MemoryBuffer::getFile(KernelEntryName + ".image", /*isText=*/false, + /*RequiresNullTerminator=*/false); if (!ImageMB) report_fatal_error("Error reading the kernel image."); @@ -127,7 +127,7 @@ int main(int argc, char **argv) { int32_t DeviceId = (DeviceIdOpt > -1 ? DeviceIdOpt : DeviceIdJson.value()); // TODO: do we need requires? - //__tgt_register_requires(/* Flags */1); + //__tgt_register_requires(/*Flags=*/1); __tgt_register_lib(&Desc); @@ -140,8 +140,8 @@ int main(int argc, char **argv) { } ErrorOr> DeviceMemoryMB = - MemoryBuffer::getFile(KernelEntryName + ".memory", /* isText */ false, - /* RequiresNullTerminator */ false); + MemoryBuffer::getFile(KernelEntryName + ".memory", /*isText=*/false, + /*RequiresNullTerminator=*/false); if (!DeviceMemoryMB) report_fatal_error("Error reading the kernel input device memory."); @@ -166,7 +166,7 @@ int main(int argc, char **argv) { } __tgt_target_kernel_replay( - /* Loc */ nullptr, DeviceId, KernelEntry.addr, (char *)recored_data, + /*Loc=*/nullptr, DeviceId, KernelEntry.addr, (char *)recored_data, DeviceMemoryMB.get()->getBufferSize(), TgtArgs.data(), TgtArgOffsets.data(), NumArgs.value(), NumTeams, NumThreads, LoopTripCount.value()); @@ -174,15 +174,15 @@ int main(int argc, char **argv) { if (VerifyOpt) { ErrorOr> OriginalOutputMB = MemoryBuffer::getFile(KernelEntryName + ".original.output", - /* isText */ false, - /* RequiresNullTerminator */ false); + /*isText=*/false, + /*RequiresNullTerminator=*/false); if (!OriginalOutputMB) report_fatal_error("Error reading the kernel original output file, make " "sure LIBOMPTARGET_SAVE_OUTPUT is set when recording"); ErrorOr> ReplayOutputMB = MemoryBuffer::getFile(KernelEntryName + ".replay.output", - /* isText */ false, - /* RequiresNullTerminator */ false); + /*isText=*/false, + /*RequiresNullTerminator=*/false); if (!ReplayOutputMB) report_fatal_error("Error reading the kernel replay output file"); -- GitLab From d4b4ded1867768ecb2c857ae9c2593764d7f3e41 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 10 Jan 2024 10:18:44 -0600 Subject: [PATCH 347/652] [Flang][Parser] Add missing #include "flang/Common/idioms.h" (#77484) The file format-specification.h uses definitions from Fortran::common, but doesn't include any headers that provide them. --- flang/include/flang/Parser/format-specification.h | 1 + 1 file changed, 1 insertion(+) diff --git a/flang/include/flang/Parser/format-specification.h b/flang/include/flang/Parser/format-specification.h index a34e68af2832..28c8affd7bde 100644 --- a/flang/include/flang/Parser/format-specification.h +++ b/flang/include/flang/Parser/format-specification.h @@ -18,6 +18,7 @@ // dependences on other parts of the compiler's source code. // TODO: support Q formatting extension? +#include "flang/Common/idioms.h" #include #include #include -- GitLab From 2472c45ba38828ee084360d52705955ff763e5b0 Mon Sep 17 00:00:00 2001 From: Han-Chung Wang Date: Wed, 10 Jan 2024 08:30:34 -0800 Subject: [PATCH 348/652] [mlir][tensor] Enhance pack/unpack simplification for identity outer_dims_perm cases. (#77409) They can be simplified to reshape ops if outer_dims_perm is an identity permutation. The revision adds a `isIdentityPermutation` method to IndexingUtils. --- .../mlir/Dialect/Utils/IndexingUtils.h | 3 ++ .../Dialect/Tensor/Transforms/CMakeLists.txt | 1 + .../Transforms/PackAndUnpackPatterns.cpp | 16 ++++++--- mlir/lib/Dialect/Utils/IndexingUtils.cpp | 7 ++++ .../Dialect/Tensor/simplify-pack-unpack.mlir | 36 +++++++++++++++++++ 5 files changed, 58 insertions(+), 5 deletions(-) diff --git a/mlir/include/mlir/Dialect/Utils/IndexingUtils.h b/mlir/include/mlir/Dialect/Utils/IndexingUtils.h index f51a8b28b754..2453d841f633 100644 --- a/mlir/include/mlir/Dialect/Utils/IndexingUtils.h +++ b/mlir/include/mlir/Dialect/Utils/IndexingUtils.h @@ -228,6 +228,9 @@ void applyPermutationToVector(SmallVector &inVec, /// Helper method to apply to inverse a permutation. SmallVector invertPermutationVector(ArrayRef permutation); +/// Returns true if `permutation` is an identity permutation. +bool isIdentityPermutation(ArrayRef permutation); + /// Method to check if an interchange vector is a permutation. bool isPermutationVector(ArrayRef interchange); diff --git a/mlir/lib/Dialect/Tensor/Transforms/CMakeLists.txt b/mlir/lib/Dialect/Tensor/Transforms/CMakeLists.txt index cbc0d499d9d5..c6ef6ed86e0d 100644 --- a/mlir/lib/Dialect/Tensor/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/Tensor/Transforms/CMakeLists.txt @@ -27,6 +27,7 @@ add_mlir_dialect_library(MLIRTensorTransforms MLIRArithUtils MLIRBufferizationDialect MLIRBufferizationTransforms + MLIRDialectUtils MLIRIR MLIRLinalgDialect MLIRMemRefDialect diff --git a/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp b/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp index 8ab69d8c59b4..06be017f24b8 100644 --- a/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp +++ b/mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp @@ -39,8 +39,12 @@ struct SimplifyPackToExpandShape : public OpRewritePattern { if (packOp.getPaddingValue()) return rewriter.notifyMatchFailure(packOp, "expects no padding value"); - if (!packOp.getOuterDimsPerm().empty()) - return rewriter.notifyMatchFailure(packOp, "expects no outer_dims_perm"); + auto outerDimsPerm = packOp.getOuterDimsPerm(); + if (!outerDimsPerm.empty() && !isIdentityPermutation(outerDimsPerm)) { + return rewriter.notifyMatchFailure( + packOp, + "expects outer_dims_perm is empty or an identity permutation"); + } RankedTensorType sourceType = packOp.getSourceType(); RankedTensorType destType = packOp.getDestType(); @@ -75,9 +79,11 @@ struct SimplifyUnPackToCollapseShape : public OpRewritePattern { LogicalResult matchAndRewrite(UnPackOp unpackOp, PatternRewriter &rewriter) const override { - if (!unpackOp.getOuterDimsPerm().empty()) { - return rewriter.notifyMatchFailure(unpackOp, - "expects no outer_dims_perm"); + auto outerDimsPerm = unpackOp.getOuterDimsPerm(); + if (!outerDimsPerm.empty() && !isIdentityPermutation(outerDimsPerm)) { + return rewriter.notifyMatchFailure( + unpackOp, + "expects outer_dims_perm is empty or an identity permutation"); } RankedTensorType sourceType = unpackOp.getSourceType(); diff --git a/mlir/lib/Dialect/Utils/IndexingUtils.cpp b/mlir/lib/Dialect/Utils/IndexingUtils.cpp index bb8a0d5912d7..2765d1eb1000 100644 --- a/mlir/lib/Dialect/Utils/IndexingUtils.cpp +++ b/mlir/lib/Dialect/Utils/IndexingUtils.cpp @@ -213,6 +213,13 @@ mlir::invertPermutationVector(ArrayRef permutation) { return inversion; } +bool mlir::isIdentityPermutation(ArrayRef permutation) { + for (auto i : llvm::seq(0, permutation.size())) + if (permutation[i] != i) + return false; + return true; +} + bool mlir::isPermutationVector(ArrayRef interchange) { assert(llvm::all_of(interchange, [](int64_t s) { return s >= 0; }) && "permutation must be non-negative"); diff --git a/mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir b/mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir index b78ab9bb3fd8..82bfe6fe8689 100644 --- a/mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir +++ b/mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir @@ -37,6 +37,30 @@ func.func @single_last_inner_dim_packing(%arg0: tensor<5x256xf32>) -> tensor<5x8 // ----- +// CHECK-LABEL: func.func @pack_1d_with_outer_dims_perm( +// CHECK-SAME: %[[ARG0:.+]]: tensor<64xf32>) +// CHECK: %[[EXPANDED:.+]] = tensor.expand_shape %[[ARG0]] {{\[}}[0, 1]] : tensor<64xf32> into tensor<2x32xf32> +// CHECK: return %[[EXPANDED]] : tensor<2x32xf32> +func.func @pack_1d_with_outer_dims_perm(%arg0: tensor<64xf32>) -> tensor<2x32xf32> { + %empty = tensor.empty() : tensor<2x32xf32> + %pack = tensor.pack %arg0 outer_dims_perm = [0] inner_dims_pos = [0] inner_tiles = [32] into %empty : tensor<64xf32> -> tensor<2x32xf32> + return %pack : tensor<2x32xf32> +} + +// ----- + +// CHECK-LABEL: func.func @single_last_inner_dim_packing_with_identity_outer_dims_perm( +// CHECK-SAME: %[[ARG0:.+]]: tensor<5x256xf32>) +// CHECK: %[[EXPANDED:.+]] = tensor.expand_shape %[[ARG0]] {{\[}}[0], [1, 2]] : tensor<5x256xf32> into tensor<5x8x32xf32> +// CHECK: return %[[EXPANDED]] : tensor<5x8x32xf32> +func.func @single_last_inner_dim_packing_with_identity_outer_dims_perm(%arg0: tensor<5x256xf32>) -> tensor<5x8x32xf32> { + %empty = tensor.empty() : tensor<5x8x32xf32> + %0 = tensor.pack %arg0 outer_dims_perm = [0, 1] inner_dims_pos = [1] inner_tiles = [32] into %empty : tensor<5x256xf32> -> tensor<5x8x32xf32> + return %0 : tensor<5x8x32xf32> +} + +// ----- + // CHECK-LABEL: func.func @packing_with_outer_dims_perm( // CHECK-NOT: tensor.expand_shape // CHECK: tensor.pack @@ -109,6 +133,18 @@ func.func @single_last_inner_dim_unpacking(%arg0: tensor<5x8x32xf32>) -> tensor< // ----- +// CHECK-LABEL: func.func @single_last_inner_dim_unpacking_with_identity_outer_dims_perm( +// CHECK-SAME: %[[ARG0:.+]]: tensor<5x8x32xf32>) +// CHECK: %[[COLLAPSED:.+]] = tensor.collapse_shape %[[ARG0]] {{\[}}[0], [1, 2]] : tensor<5x8x32xf32> into tensor<5x256xf32> +// CHECK: return %[[COLLAPSED]] : tensor<5x256xf32> +func.func @single_last_inner_dim_unpacking_with_identity_outer_dims_perm(%arg0: tensor<5x8x32xf32>) -> tensor<5x256xf32> { + %empty = tensor.empty() : tensor<5x256xf32> + %0 = tensor.unpack %arg0 outer_dims_perm = [0, 1] inner_dims_pos = [1] inner_tiles = [32] into %empty : tensor<5x8x32xf32> -> tensor<5x256xf32> + return %0 : tensor<5x256xf32> +} + +// ----- + // CHECK-LABEL: func.func @unpacking_with_outer_dims_perm( // CHECK-NOT: tensor.collpase_shape // CHECK: tensor.unpack -- GitLab From fb1523e7120aeb9584eef5b3241f03f1cadff62b Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 10 Jan 2024 17:41:22 +0100 Subject: [PATCH 349/652] [bazel] Port 79aa77626770c91badd7c9ba9d26e55a28d34416 --- utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 1 + utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel | 1 + 2 files changed, 2 insertions(+) diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 05cbf7816370..639b195de94e 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -3279,6 +3279,7 @@ cc_library( hdrs = glob(["include/mlir/Dialect/Mesh/Transforms/*.h"]), includes = ["include"], deps = [ + ":AffineDialect", ":ArithDialect", ":ControlFlowDialect", ":DialectUtils", diff --git a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel index 656a1d66208b..fe0f44f1f792 100644 --- a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel @@ -788,6 +788,7 @@ cc_library( deps = [ ":TestDialect", "//mlir:ArithDialect", + "//mlir:DialectUtils", "//mlir:FuncDialect", "//mlir:IR", "//mlir:MeshDialect", -- GitLab From 1d5106d69cf475215887c42834158d710e586f1b Mon Sep 17 00:00:00 2001 From: Frederik Carlier Date: Wed, 10 Jan 2024 08:52:13 -0800 Subject: [PATCH 350/652] Objective C: use C++ exceptions on MinGW+GNUstep (#77255) The GNUstep Objective C runtime (libobjc2) is adding support for the GNU ABI on Windows (more specifically, MinGW). The libobjc2 runtime uses C++ exceptions in that configuration; this PR updates clang to act accordingly. The corresponding change to libobjc2 is here: https://github.com/gnustep/libobjc2/pull/267 --- clang/lib/CodeGen/CGException.cpp | 7 ++- clang/lib/CodeGen/CGObjCGNU.cpp | 35 +++++++----- .../test/CodeGenObjC/exceptions-personality.m | 53 +++++++++++++++++++ clang/test/CodeGenObjC/personality.m | 5 +- clang/test/CodeGenObjCXX/personality.mm | 5 +- 5 files changed, 87 insertions(+), 18 deletions(-) create mode 100644 clang/test/CodeGenObjC/exceptions-personality.m diff --git a/clang/lib/CodeGen/CGException.cpp b/clang/lib/CodeGen/CGException.cpp index 0d507da5c1ba..56a246eb65e0 100644 --- a/clang/lib/CodeGen/CGException.cpp +++ b/clang/lib/CodeGen/CGException.cpp @@ -156,7 +156,9 @@ static const EHPersonality &getObjCPersonality(const TargetInfo &Target, case ObjCRuntime::WatchOS: return EHPersonality::NeXT_ObjC; case ObjCRuntime::GNUstep: - if (L.ObjCRuntime.getVersion() >= VersionTuple(1, 7)) + if (T.isOSCygMing()) + return EHPersonality::GNU_CPlusPlus_SEH; + else if (L.ObjCRuntime.getVersion() >= VersionTuple(1, 7)) return EHPersonality::GNUstep_ObjC; [[fallthrough]]; case ObjCRuntime::GCC: @@ -210,7 +212,8 @@ static const EHPersonality &getObjCXXPersonality(const TargetInfo &Target, return getObjCPersonality(Target, L); case ObjCRuntime::GNUstep: - return EHPersonality::GNU_ObjCXX; + return Target.getTriple().isOSCygMing() ? EHPersonality::GNU_CPlusPlus_SEH + : EHPersonality::GNU_ObjCXX; // The GCC runtime's personality function inherently doesn't support // mixed EH. Use the ObjC personality just to avoid returning null. diff --git a/clang/lib/CodeGen/CGObjCGNU.cpp b/clang/lib/CodeGen/CGObjCGNU.cpp index 9443fecf9b79..cd1a0b6a130f 100644 --- a/clang/lib/CodeGen/CGObjCGNU.cpp +++ b/clang/lib/CodeGen/CGObjCGNU.cpp @@ -168,6 +168,8 @@ protected: /// Does the current target use SEH-based exceptions? False implies /// Itanium-style DWARF unwinding. bool usesSEHExceptions; + /// Does the current target uses C++-based exceptions? + bool usesCxxExceptions; /// Helper to check if we are targeting a specific runtime version or later. bool isRuntime(ObjCRuntime::Kind kind, unsigned major, unsigned minor=0) { @@ -819,12 +821,18 @@ class CGObjCGNUstep : public CGObjCGNU { SlotLookupSuperFn.init(&CGM, "objc_slot_lookup_super", SlotTy, PtrToObjCSuperTy, SelectorTy); // If we're in ObjC++ mode, then we want to make - if (usesSEHExceptions) { - llvm::Type *VoidTy = llvm::Type::getVoidTy(VMContext); - // void objc_exception_rethrow(void) - ExceptionReThrowFn.init(&CGM, "objc_exception_rethrow", VoidTy); + llvm::Type *VoidTy = llvm::Type::getVoidTy(VMContext); + if (usesCxxExceptions) { + // void *__cxa_begin_catch(void *e) + EnterCatchFn.init(&CGM, "__cxa_begin_catch", PtrTy, PtrTy); + // void __cxa_end_catch(void) + ExitCatchFn.init(&CGM, "__cxa_end_catch", VoidTy); + // void objc_exception_rethrow(void*) + ExceptionReThrowFn.init(&CGM, "__cxa_rethrow", PtrTy); + } else if (usesSEHExceptions) { + // void objc_exception_rethrow(void) + ExceptionReThrowFn.init(&CGM, "objc_exception_rethrow", VoidTy); } else if (CGM.getLangOpts().CPlusPlus) { - llvm::Type *VoidTy = llvm::Type::getVoidTy(VMContext); // void *__cxa_begin_catch(void *e) EnterCatchFn.init(&CGM, "__cxa_begin_catch", PtrTy, PtrTy); // void __cxa_end_catch(void) @@ -833,7 +841,6 @@ class CGObjCGNUstep : public CGObjCGNU { ExceptionReThrowFn.init(&CGM, "_Unwind_Resume_or_Rethrow", VoidTy, PtrTy); } else if (R.getVersion() >= VersionTuple(1, 7)) { - llvm::Type *VoidTy = llvm::Type::getVoidTy(VMContext); // id objc_begin_catch(void *e) EnterCatchFn.init(&CGM, "objc_begin_catch", IdTy, PtrTy); // void objc_end_catch(void) @@ -841,7 +848,6 @@ class CGObjCGNUstep : public CGObjCGNU { // void _Unwind_Resume_or_Rethrow(void*) ExceptionReThrowFn.init(&CGM, "objc_exception_rethrow", VoidTy, PtrTy); } - llvm::Type *VoidTy = llvm::Type::getVoidTy(VMContext); SetPropertyAtomic.init(&CGM, "objc_setProperty_atomic", VoidTy, IdTy, SelectorTy, IdTy, PtrDiffTy); SetPropertyAtomicCopy.init(&CGM, "objc_setProperty_atomic_copy", VoidTy, @@ -2126,6 +2132,9 @@ CGObjCGNU::CGObjCGNU(CodeGenModule &cgm, unsigned runtimeABIVersion, msgSendMDKind = VMContext.getMDKindID("GNUObjCMessageSend"); usesSEHExceptions = cgm.getContext().getTargetInfo().getTriple().isWindowsMSVCEnvironment(); + usesCxxExceptions = + cgm.getContext().getTargetInfo().getTriple().isOSCygMing() && + isRuntime(ObjCRuntime::GNUstep, 2); CodeGenTypes &Types = CGM.getTypes(); IntTy = cast( @@ -2212,7 +2221,10 @@ CGObjCGNU::CGObjCGNU(CodeGenModule &cgm, unsigned runtimeABIVersion, // void objc_exception_throw(id); ExceptionThrowFn.init(&CGM, "objc_exception_throw", VoidTy, IdTy); - ExceptionReThrowFn.init(&CGM, "objc_exception_throw", VoidTy, IdTy); + ExceptionReThrowFn.init(&CGM, + usesCxxExceptions ? "objc_exception_rethrow" + : "objc_exception_throw", + VoidTy, IdTy); // int objc_sync_enter(id); SyncEnterFn.init(&CGM, "objc_sync_enter", IntTy, IdTy); // int objc_sync_exit(id); @@ -2389,7 +2401,7 @@ llvm::Constant *CGObjCGNUstep::GetEHType(QualType T) { if (usesSEHExceptions) return CGM.getCXXABI().getAddrOfRTTIDescriptor(T); - if (!CGM.getLangOpts().CPlusPlus) + if (!CGM.getLangOpts().CPlusPlus && !usesCxxExceptions) return CGObjCGNU::GetEHType(T); // For Objective-C++, we want to provide the ability to catch both C++ and @@ -3995,7 +4007,7 @@ void CGObjCGNU::EmitThrowStmt(CodeGenFunction &CGF, ExceptionAsObject = CGF.ObjCEHValueStack.back(); isRethrow = true; } - if (isRethrow && usesSEHExceptions) { + if (isRethrow && (usesSEHExceptions || usesCxxExceptions)) { // For SEH, ExceptionAsObject may be undef, because the catch handler is // not passed it for catchalls and so it is not visible to the catch // funclet. The real thrown object will still be live on the stack at this @@ -4005,8 +4017,7 @@ void CGObjCGNU::EmitThrowStmt(CodeGenFunction &CGF, // argument. llvm::CallBase *Throw = CGF.EmitRuntimeCallOrInvoke(ExceptionReThrowFn); Throw->setDoesNotReturn(); - } - else { + } else { ExceptionAsObject = CGF.Builder.CreateBitCast(ExceptionAsObject, IdTy); llvm::CallBase *Throw = CGF.EmitRuntimeCallOrInvoke(ExceptionThrowFn, ExceptionAsObject); diff --git a/clang/test/CodeGenObjC/exceptions-personality.m b/clang/test/CodeGenObjC/exceptions-personality.m new file mode 100644 index 000000000000..9c25ee38b6d7 --- /dev/null +++ b/clang/test/CodeGenObjC/exceptions-personality.m @@ -0,0 +1,53 @@ +// RUN: %clang_cc1 -triple x86_64-w64-windows-gnu -emit-llvm -fobjc-runtime=gnustep-2.0 -fexceptions -fobjc-exceptions -o %t %s +// RUN: FileCheck --check-prefixes=CHECK-MINGW-OBJC2 < %t %s + +// RUN: %clang_cc1 -triple x86_64-w64-windows-gnu -emit-llvm -fobjc-runtime=gcc -fexceptions -fobjc-exceptions -o %t %s +// RUN: FileCheck --check-prefixes=CHECK-MINGW-GCC < %t %s + +// RUN: %clang_cc1 -triple x86_64-w64-windows-msvc -emit-llvm -fobjc-runtime=gnustep-2.0 -fexceptions -fobjc-exceptions -o %t %s +// RUN: FileCheck --check-prefixes=CHECK-MSVC-OBJC2 < %t %s + +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -fobjc-runtime=gnustep-2.0 -fexceptions -fobjc-exceptions -o %t %s +// RUN: FileCheck --check-prefixes=CHECK-LINUX-OBJC2 < %t %s + +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -fobjc-runtime=gcc -fexceptions -fobjc-exceptions -o %t %s +// RUN: FileCheck --check-prefixes=CHECK-LINUX-GCC < %t %s +@interface Foo @end + +void throwing(void) { + @try + { + // CHECK-MINGW-OBJC2: personality ptr @__gxx_personality_seh0 + // CHECK-MINGW-OBJC2: invoke void @objc_exception_throw + + // CHECK-MINGW-GCC: personality ptr @__gnu_objc_personality_v0 + // CHECK-MINGW-GCC: invoke void @objc_exception_throw + + // CHECK-MSVC-OBJC2: personality ptr @__CxxFrameHandler3 + // CHECK-MSVC-OBJC2: invoke void @objc_exception_throw + + // CHECK-LINUX-OBJC2: personality ptr @__gnustep_objc_personality_v0 + // CHECK-LINUX-OBJC2: invoke void @objc_exception_throw + + // CHECK-LINUX-GCC: personality ptr @__gnu_objc_personality_v0 + @throw(@"error!"); + } + @catch(...) + { + // CHECK-MINGW-OBJC2: call ptr @__cxa_begin_catch + // CHECK-MINGW-OBJC2: invoke ptr @__cxa_rethrow + // CHECK-MINGW-OBJC2: invoke void @__cxa_end_catch + + // CHECK-MINGW-GCC: call void @objc_exception_throw + + // CHECK-MSVC-OBJC2: call void @objc_exception_rethrow + + // CHECK-LINUX-OBJC2: call ptr @objc_begin_catch + // CHECK-LINUX-OBJC2: invoke void @objc_exception_throw + // CHECK-LINUX-OBJC2: invoke void @objc_end_catch() + + // CHECK-LINUX-GCC: invoke void @objc_exception_throw + + @throw; + } +} diff --git a/clang/test/CodeGenObjC/personality.m b/clang/test/CodeGenObjC/personality.m index 6ec67ace3f1a..ede0aa34eaf6 100644 --- a/clang/test/CodeGenObjC/personality.m +++ b/clang/test/CodeGenObjC/personality.m @@ -27,8 +27,8 @@ // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=ios -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-NS // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=macosx -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-NS // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=watchos -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-NS -// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=gnustep-1.7 -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GNUSTEP-1_7 -// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=gnustep -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GNUSTEP +// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=gnustep-1.7 -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-WIN-GNU +// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=gnustep -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-WIN-GNU // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fobjc-runtime=gcc -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GCC // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -exception-model=seh -fobjc-exceptions -fobjc-runtime=gcc -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GCC-SEH // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -exception-model=sjlj -fobjc-exceptions -fobjc-runtime=gcc -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GCC-SJLJ @@ -50,6 +50,7 @@ void g(void); // CHECK-OBJFW-SJLJ: personality ptr @__gnu_objc_personality_sj0 // CHECK-WIN-MSVC: personality ptr @__CxxFrameHandler3 +// CHECK-WIN-GNU: personality ptr @__gxx_personality_seh0 // CHECK-MACOSX-FRAGILE-MINGW-DWARF: personality ptr @__gcc_personality_v0 // CHECK-MACOSX-FRAGILE-MINGW-SEH: personality ptr @__gcc_personality_seh0 diff --git a/clang/test/CodeGenObjCXX/personality.mm b/clang/test/CodeGenObjCXX/personality.mm index c6debe6f60c2..b8c7af962bd0 100644 --- a/clang/test/CodeGenObjCXX/personality.mm +++ b/clang/test/CodeGenObjCXX/personality.mm @@ -50,8 +50,8 @@ // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -exception-model=dwarf -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=watchos -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-NS // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -exception-model=seh -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=watchos -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-NS // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -exception-model=sjlj -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=watchos -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-NS -// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=gnustep-1.7 -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GNUSTEP-1_7 -// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=gnustep -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GNUSTEP +// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=gnustep-1.7 -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-WIN-GNU +// RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=gnustep -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-WIN-GNU // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=gcc -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GCC // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -exception-model=dwarf -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=gcc -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GCC // RUN: %clang_cc1 -triple i686-unknown-windows-gnu -fexceptions -exception-model=seh -fobjc-exceptions -fcxx-exceptions -fobjc-runtime=gcc -S -emit-llvm %s -o - | FileCheck %s -check-prefix CHECK-GCC-SEH @@ -81,6 +81,7 @@ void g(void); // CHECK-OBJFW-SJLJ: personality ptr @__gnu_objc_personality_sj0 // CHECK-WIN-MSVC: personality ptr @__CxxFrameHandler3 +// CHECK-WIN-GNU: personality ptr @__gxx_personality_seh0 void f(void) { @try { -- GitLab From af78e5daf0791135485dbd7972ffedb927727a6b Mon Sep 17 00:00:00 2001 From: Tai Ly Date: Wed, 10 Jan 2024 10:57:39 -0600 Subject: [PATCH 351/652] [mlir][tosa]Fix Rescale shift attr data type (#71084) Change Rescale shift attribute to be DenseI8ArrayAttr to match spec (instead of DenseI32ArrayAttr) This replaces https://reviews.llvm.org/D157439 Signed-off-by: Tai Ly --- mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td | 2 +- .../TosaToLinalg/tosa-to-linalg.mlir | 28 +++++++++---------- mlir/test/Dialect/Tosa/ops.mlir | 4 +-- mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir | 2 +- mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp | 5 ++-- 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td index 9dde59f634d7..3257ecd9d91f 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td @@ -1848,7 +1848,7 @@ def Tosa_RescaleOp: Tosa_Op<"rescale", [Pure, I32Attr:$input_zp, I32Attr:$output_zp, DenseI32ArrayAttr:$multiplier, - DenseI32ArrayAttr:$shift, + DenseI8ArrayAttr:$shift, BoolAttr:$scale32, BoolAttr:$double_round, BoolAttr:$per_channel diff --git a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir index 3931e454da2e..8a29752ff8d7 100644 --- a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir +++ b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir @@ -93,7 +93,7 @@ func.func @test_add_0d(%arg0: tensor, %arg1: tensor) -> tensor { // CHECK: linalg.yield [[ADDF]] : f32 // CHECK: } -> tensor %0 = tosa.add %arg0, %arg1 : (tensor, tensor) -> tensor - + // CHECK: return [[RESULT]] : tensor return %0 : tensor } @@ -223,7 +223,7 @@ func.func @test_add_1d_broadcast_static_to_static(%arg0: tensor<1xf32>, %arg1: t // CHECK: linalg.yield %[[VAL_4]] : f32 // CHECK: } -> tensor<3xf32> %0 = tosa.add %arg0, %arg1 : (tensor<1xf32>, tensor<3xf32>) -> tensor<3xf32> - + // CHECK: return %[[RESULT]] : tensor<3xf32> return %0 : tensor<3xf32> } @@ -352,7 +352,7 @@ func.func @test_add_2d_different_ranks(%arg0: tensor<3x4xf32>, %arg1: tensor<2x3 // CHECK: linalg.yield %[[VAL_4]] : f32 // CHECK: } -> tensor<2x3x4xf32> %0 = tosa.add %arg0, %arg1 : (tensor<3x4xf32>, tensor<2x3x4xf32>) -> tensor<2x3x4xf32> - + // CHECK: return %[[RESULT]] : tensor<2x3x4xf32> return %0 : tensor<2x3x4xf32> } @@ -1057,7 +1057,7 @@ func.func @rescale_i8(%arg0 : tensor<2xi8>) -> () { // CHECK-DAG: [[BOUNDED:%.+]] = arith.select [[MAXLT]], [[CMAX]], [[LOWER]] // CHECK-DAG: [[TRUNC:%.+]] = arith.trunci [[BOUNDED]] // CHECK-DAG: linalg.yield [[TRUNC]] - %0 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<2xi8>) -> tensor<2xi8> + %0 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<2xi8>) -> tensor<2xi8> // CHECK: [[C0:%.+]] = arith.constant 19689 // CHECK: [[C1:%.+]] = arith.constant 15 @@ -1079,7 +1079,7 @@ func.func @rescale_i8(%arg0 : tensor<2xi8>) -> () { // CHECK-DAG: [[TRUNC:%.+]] = arith.trunci [[BOUNDED]] // CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast [[TRUNC]] : i8 to ui8 // CHECK: linalg.yield [[CAST]] - %1 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<2xi8>) -> tensor<2xui8> + %1 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<2xi8>) -> tensor<2xui8> // CHECK: return return @@ -1096,13 +1096,13 @@ func.func @rescale_i8_dyn_batch(%arg0 : tensor) -> () { // CHECK: %[[BATCH:.+]] = tensor.dim %[[ARG0]], %[[C0]] // CHECK: %[[INIT:.+]] = tensor.empty(%[[BATCH]]) : tensor // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel", "parallel"]} ins(%[[ARG0]] : tensor) outs(%[[INIT]] : tensor) - %0 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor) -> tensor + %0 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor) -> tensor // CHECK: %[[C0:.+]] = arith.constant 0 // CHECK: %[[BATCH:.+]] = tensor.dim %[[ARG0]], %[[C0]] // CHECK: %[[INIT:.+]] = tensor.empty(%[[BATCH]]) : tensor // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel", "parallel"]} ins(%[[ARG0]] : tensor) outs(%[[INIT]] : tensor) - %1 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor) -> tensor + %1 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor) -> tensor return } @@ -1120,7 +1120,7 @@ func.func @rescale_dyn(%arg0 : tensor<1x?x?x32xi32>) -> () { // CHECK: %[[DIM2:.+]] = tensor.dim %[[ARG0]], %[[C2]] // CHECK: %[[INIT:.+]] = tensor.empty(%[[DIM1]], %[[DIM2]]) // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP1]], #[[$MAP1]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%[[ARG0]] : tensor<1x?x?x32xi32>) outs(%[[INIT]] : tensor<1x?x?x32xi8>) - %0 = tosa.rescale %arg0 {double_round = true, input_zp = 0 : i32, multiplier = array, output_zp = 0 : i32, per_channel = false, scale32 = true, shift = array} : (tensor<1x?x?x32xi32>) -> tensor<1x?x?x32xi8> + %0 = tosa.rescale %arg0 {double_round = true, input_zp = 0 : i32, multiplier = array, output_zp = 0 : i32, per_channel = false, scale32 = true, shift = array} : (tensor<1x?x?x32xi32>) -> tensor<1x?x?x32xi8> return } @@ -1151,7 +1151,7 @@ func.func @rescale_ui8(%arg0 : tensor<2xui8>) -> () { // CHECK-DAG: [[BOUNDED:%.+]] = arith.select [[MAXLT]], [[CMAX]], [[LOWER]] // CHECK-DAG: [[TRUNC:%.+]] = arith.trunci [[BOUNDED]] // CHECK: linalg.yield [[TRUNC]] - %0 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<2xui8>) -> tensor<2xi8> + %0 = tosa.rescale %arg0 {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<2xui8>) -> tensor<2xi8> return } @@ -1183,7 +1183,7 @@ func.func @rescale_per_channel(%arg0 : tensor<3xi8>) -> (tensor<3xi8>) { // CHECK-DAG: [[BOUNDED:%.+]] = arith.select [[MAXLT]], [[CMAX]], [[LOWER]] // CHECK-DAG: [[TRUNC:%.+]] = arith.trunci [[BOUNDED]] // CHECK-DAG: linalg.yield [[TRUNC]] - %0 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<3xi8>) -> tensor<3xi8> + %0 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<3xi8>) -> tensor<3xi8> // CHECK: return [[GENERIC]] return %0 : tensor<3xi8> @@ -1194,18 +1194,18 @@ func.func @rescale_per_channel(%arg0 : tensor<3xi8>) -> (tensor<3xi8>) { // CHECK-LABEL: @rescaleDoubleRound func.func @rescaleDoubleRound(%arg0 : tensor<2xi8>) -> (tensor<2xi8>) { // CHECK: linalg.generic - // CHECK: tosa.apply_scale + // CHECK: tosa.apply_scale // CHECK-SAME: {double_round = true} - %0 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = true, double_round = true, per_channel = false} : (tensor<2xi8>) -> tensor<2xi8> + %0 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = true, double_round = true, per_channel = false} : (tensor<2xi8>) -> tensor<2xi8> return %0 : tensor<2xi8> } // CHECK-LABEL: @rescaleUnnecessaryDoubleRound func.func @rescaleUnnecessaryDoubleRound(%arg0 : tensor<2xi8>) -> (tensor<2xi8>) { // CHECK: linalg.generic - // CHECK: tosa.apply_scale + // CHECK: tosa.apply_scale // CHECK-SAME: {double_round = false} - %0 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = true, double_round = true, per_channel = false} : (tensor<2xi8>) -> tensor<2xi8> + %0 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = true, double_round = true, per_channel = false} : (tensor<2xi8>) -> tensor<2xi8> return %0 : tensor<2xi8> } diff --git a/mlir/test/Dialect/Tosa/ops.mlir b/mlir/test/Dialect/Tosa/ops.mlir index a3d0b5e5447a..3d68464ebf0b 100644 --- a/mlir/test/Dialect/Tosa/ops.mlir +++ b/mlir/test/Dialect/Tosa/ops.mlir @@ -64,7 +64,7 @@ func.func @test_conv2d_q8xi4(%arg0: tensor<1x11x11x3xi8>) -> tensor<1x1x1x3xi8> %0 = "tosa.const"() {value = dense<0> : tensor<3x11x11x3xi4>} : () -> tensor<3x11x11x3xi4> %1 = "tosa.const"() {value = dense<[12, 23, 55]> : tensor<3xi32>} : () -> tensor<3xi32> %2 = "tosa.conv2d"(%arg0, %0, %1) {dilation = array, pad = array, quantization_info = #tosa.conv_quant, stride = array} : (tensor<1x11x11x3xi8>, tensor<3x11x11x3xi4>, tensor<3xi32>) -> tensor<1x1x1x3xi32> - %3 = "tosa.rescale"(%2) {double_round = true, input_zp = 0 : i32, multiplier = array, output_zp = 27 : i32, per_channel = true, scale32 = true, shift = array} : (tensor<1x1x1x3xi32>) -> tensor<1x1x1x3xi8> + %3 = "tosa.rescale"(%2) {double_round = true, input_zp = 0 : i32, multiplier = array, output_zp = 27 : i32, per_channel = true, scale32 = true, shift = array} : (tensor<1x1x1x3xi32>) -> tensor<1x1x1x3xi8> return %3 : tensor<1x1x1x3xi8> } @@ -604,7 +604,7 @@ func.func @test_cast3(%arg0: tensor<13x21x3xi32>) -> tensor<13x21x3x!quant.unifo // ----- // CHECK-LABEL: rescale func.func @test_rescale(%arg0: tensor<13x21x3x!quant.uniform>) -> tensor<13x21x3x!quant.uniform> { - %0 = tosa.rescale %arg0 {double_round = false, input_zp = 127 : i32, multiplier = array, output_zp = -1 : i32, per_channel = false, scale32 = true, shift = array} : (tensor<13x21x3x!quant.uniform>) -> tensor<13x21x3x!quant.uniform> + %0 = tosa.rescale %arg0 {double_round = false, input_zp = 127 : i32, multiplier = array, output_zp = -1 : i32, per_channel = false, scale32 = true, shift = array} : (tensor<13x21x3x!quant.uniform>) -> tensor<13x21x3x!quant.uniform> return %0 : tensor<13x21x3x!quant.uniform> } diff --git a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir index f5cd8bd48de1..1f0cfaf92c5c 100644 --- a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir +++ b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir @@ -94,7 +94,7 @@ func.func @test_unary_i32(%arg0 : tensor<4xi32>) -> () { %5 = tosa.reverse %arg0 { axis = 0 : i32 } : (tensor<4xi32>) -> tensor // CHECK: tosa.rescale %arg0 {{.+}} : (tensor<4xi32>) -> tensor<4xi16> - %6 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<4xi32>) -> tensor<*xi16> + %6 = tosa.rescale %arg0 {input_zp = 243 : i32, output_zp = 252 : i32, multiplier = array, shift = array, scale32 = false, double_round = false, per_channel = false} : (tensor<4xi32>) -> tensor<*xi16> // CHECK: tosa.identity %arg0 : (tensor<4xi32>) -> tensor<4xi32> %7 = tosa.identity %arg0 : (tensor<4xi32>) -> tensor diff --git a/mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp b/mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp index 9642301e8111..e5a3e2b6fcca 100644 --- a/mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp +++ b/mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp @@ -169,8 +169,9 @@ ConvertTosaConv2DOp::matchAndRewrite(Operation *op, op->getLoc(), outputType, newTosaConv2DOp.getResult(), rewriter.getI32IntegerAttr(0), rewriter.getI32IntegerAttr(outputZp), rewriter.getDenseI32ArrayAttr({multiplier}), - rewriter.getDenseI32ArrayAttr({shift}), rewriter.getBoolAttr(true), - rewriter.getBoolAttr(true), rewriter.getBoolAttr(false)); + rewriter.getDenseI8ArrayAttr({static_cast(shift)}), + rewriter.getBoolAttr(true), rewriter.getBoolAttr(true), + rewriter.getBoolAttr(false)); rewriter.replaceOp(op, {newTosaRescaleOp.getResult()}); return success(); -- GitLab From d7ac4123333a5bc042b2eb9e17df8f723f6b56d9 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Wed, 10 Jan 2024 17:07:03 +0000 Subject: [PATCH 352/652] [AArch64][SME] Fix definition of uclamp/sclamp instructions. (#77619) For some reason the arguments were in the wrong order. --- llvm/lib/Target/AArch64/SMEInstrFormats.td | 2 +- llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll | 16 ++++++++-------- .../CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll | 12 ++++-------- .../CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll | 12 ++++-------- 4 files changed, 17 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 70f3c2c99f0f..44d9a8ac7cb6 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -1268,7 +1268,7 @@ multiclass sve2_int_perm_revd { } class sve2_clamp sz, bit U, ZPRRegOp zpr_ty> - : I<(outs zpr_ty:$Zd), (ins zpr_ty:$Zn, zpr_ty:$Zm, zpr_ty:$_Zd), + : I<(outs zpr_ty:$Zd), (ins zpr_ty:$_Zd, zpr_ty:$Zn, zpr_ty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zm; diff --git a/llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll b/llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll index 28ec430aff3d..365fd5345484 100644 --- a/llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll +++ b/llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll @@ -3,7 +3,7 @@ ; Replace pattern min(max(v1,v2),v3) by clamp -define @uclampi8( %c, %a, %b) { +define @uclampi8( %a, %b, %c) { ; CHECK-LABEL: uclampi8: ; CHECK: // %bb.0: ; CHECK-NEXT: uclamp z0.b, z1.b, z2.b @@ -13,7 +13,7 @@ define @uclampi8( %c, %a ret %res } -define @uclampi16( %c, %a, %b) { +define @uclampi16( %a, %b, %c) { ; CHECK-LABEL: uclampi16: ; CHECK: // %bb.0: ; CHECK-NEXT: uclamp z0.h, z1.h, z2.h @@ -23,7 +23,7 @@ define @uclampi16( %c, % ret %res } -define @uclampi32( %c, %a, %b) { +define @uclampi32( %a, %b, %c) { ; CHECK-LABEL: uclampi32: ; CHECK: // %bb.0: ; CHECK-NEXT: uclamp z0.s, z1.s, z2.s @@ -33,7 +33,7 @@ define @uclampi32( %c, % ret %res } -define @uclampi64( %c, %a, %b) { +define @uclampi64( %a, %b, %c) { ; CHECK-LABEL: uclampi64: ; CHECK: // %bb.0: ; CHECK-NEXT: uclamp z0.d, z1.d, z2.d @@ -43,7 +43,7 @@ define @uclampi64( %c, % ret %res } -define @sclampi8( %c, %a, %b) { +define @sclampi8( %a, %b, %c) { ; CHECK-LABEL: sclampi8: ; CHECK: // %bb.0: ; CHECK-NEXT: sclamp z0.b, z1.b, z2.b @@ -53,7 +53,7 @@ define @sclampi8( %c, %a ret %res } -define @sclampi16( %c, %a, %b) { +define @sclampi16( %a, %b, %c) { ; CHECK-LABEL: sclampi16: ; CHECK: // %bb.0: ; CHECK-NEXT: sclamp z0.h, z1.h, z2.h @@ -63,7 +63,7 @@ define @sclampi16( %c, % ret %res } -define @sclampi32( %c, %a, %b) { +define @sclampi32( %a, %b, %c) { ; CHECK-LABEL: sclampi32: ; CHECK: // %bb.0: ; CHECK-NEXT: sclamp z0.s, z1.s, z2.s @@ -73,7 +73,7 @@ define @sclampi32( %c, % ret %res } -define @sclampi64( %c, %a, %b) { +define @sclampi64( %a, %b, %c) { ; CHECK-LABEL: sclampi64: ; CHECK: // %bb.0: ; CHECK-NEXT: sclamp z0.d, z1.d, z2.d diff --git a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll index cf59036d42db..912d5d853aa8 100644 --- a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll +++ b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll @@ -6,8 +6,7 @@ target triple = "aarch64-linux-gnu" define @test_sclamp_i8( %a, %b, %c) #0 { ; CHECK-LABEL: test_sclamp_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: sclamp z2.b, z0.b, z1.b -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: sclamp z0.b, z1.b, z2.b ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.sclamp.nxv16i8( %a, %b, %c) ret %res @@ -16,8 +15,7 @@ define @test_sclamp_i8( %a, @test_sclamp_i16( %a, %b, %c) #0 { ; CHECK-LABEL: test_sclamp_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: sclamp z2.h, z0.h, z1.h -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: sclamp z0.h, z1.h, z2.h ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.sclamp.nxv8i16( %a, %b, %c) ret %res @@ -26,8 +24,7 @@ define @test_sclamp_i16( %a, @test_sclamp_i32( %a, %b, %c) #0 { ; CHECK-LABEL: test_sclamp_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: sclamp z2.s, z0.s, z1.s -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: sclamp z0.s, z1.s, z2.s ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.sclamp.nxv4i32( %a, %b, %c) ret %res @@ -36,8 +33,7 @@ define @test_sclamp_i32( %a, @test_sclamp_i64( %a, %b, %c) #0 { ; CHECK-LABEL: test_sclamp_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: sclamp z2.d, z0.d, z1.d -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: sclamp z0.d, z1.d, z2.d ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.sclamp.nxv2i64( %a, %b, %c) ret %res diff --git a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll index 81a34e82d845..de1695162c98 100644 --- a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll +++ b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll @@ -6,8 +6,7 @@ target triple = "aarch64-linux-gnu" define @test_uclamp_i8( %a, %b, %c) #0 { ; CHECK-LABEL: test_uclamp_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: uclamp z2.b, z0.b, z1.b -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: uclamp z0.b, z1.b, z2.b ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.uclamp.nxv16i8( %a, %b, %c) ret %res @@ -16,8 +15,7 @@ define @test_uclamp_i8( %a, @test_uclamp_i16( %a, %b, %c) #0 { ; CHECK-LABEL: test_uclamp_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: uclamp z2.h, z0.h, z1.h -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: uclamp z0.h, z1.h, z2.h ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.uclamp.nxv8i16( %a, %b, %c) ret %res @@ -26,8 +24,7 @@ define @test_uclamp_i16( %a, @test_uclamp_i32( %a, %b, %c) #0 { ; CHECK-LABEL: test_uclamp_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: uclamp z2.s, z0.s, z1.s -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: uclamp z0.s, z1.s, z2.s ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.uclamp.nxv4i32( %a, %b, %c) ret %res @@ -36,8 +33,7 @@ define @test_uclamp_i32( %a, @test_uclamp_i64( %a, %b, %c) #0 { ; CHECK-LABEL: test_uclamp_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: uclamp z2.d, z0.d, z1.d -; CHECK-NEXT: mov z0.d, z2.d +; CHECK-NEXT: uclamp z0.d, z1.d, z2.d ; CHECK-NEXT: ret %res = call @llvm.aarch64.sve.uclamp.nxv2i64( %a, %b, %c) ret %res -- GitLab From 14e7dac92a32f900a66cb868be89c964b687a825 Mon Sep 17 00:00:00 2001 From: CarolineConcatto Date: Wed, 10 Jan 2024 17:12:14 +0000 Subject: [PATCH 353/652] [Clang][LLVM][AArch64]SVE2.1 update the intrinsics according to acle[1] (#76844) This patch changes the following intrinsic ```svst1uwq[_{d}] replaced by svst1wq[_{d}] svst1uwq_vnum[_{d}] replaced by svst1wq_vnum[_{d}] svst1udq[_{d}] replaced by svst1dq[_{d}] svst1udq_vnum[_{d}] replaced by svst1dq_vnum[_{d}] ``` Drops 'u' from the quadword stores because it is simply truncating the quadwords to 32 bits ``` svextq_lane[_{d}] replaced by svextq[_{d}] ``` EXTQ follows the previous defined EXT intrinsics ``` svdot[_{d}_{2}_{3}] replaced by svdot[_{d}_{2}] ``` Introduced with the latest SME2 ACLE change [1]https://github.com/ARM-software/acle/pull/257 --- clang/include/clang/Basic/arm_sve.td | 22 +-- clang/lib/CodeGen/CGBuiltin.cpp | 4 +- .../acle_sve2p1_dot.c | 12 +- .../acle_sve2p1_extq.c | 144 +++++++++--------- .../acle_sve2p1_st1_single.c | 144 +++++++++--------- .../acle_sve2p1_imm.cpp | 10 +- llvm/include/llvm/IR/IntrinsicsAArch64.td | 6 +- .../Target/AArch64/AArch64ISelDAGToDAG.cpp | 4 +- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 +- .../CodeGen/AArch64/sve2p1-intrinsics-extq.ll | 32 ++-- .../AArch64/sve2p1-intrinsics-st1-single.ll | 76 ++++----- 11 files changed, 234 insertions(+), 234 deletions(-) diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index 7f80fb0386cc..6f35e25617ad 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -454,11 +454,11 @@ let TargetGuard = "sve,bf16" in { let TargetGuard = "sve2p1" in { // Contiguous truncating store from quadword (single vector). - def SVST1UWQ : MInst<"svst1uwq[_{d}]", "vPcd", "iUif", [IsStore], MemEltTyInt32, "aarch64_sve_st1uwq">; - def SVST1UWQ_VNUM : MInst<"svst1uwq_vnum[_{d}]", "vPcld", "iUif", [IsStore], MemEltTyInt32, "aarch64_sve_st1uwq">; + def SVST1UWQ : MInst<"svst1wq[_{d}]", "vPcd", "iUif", [IsStore], MemEltTyInt32, "aarch64_sve_st1wq">; + def SVST1UWQ_VNUM : MInst<"svst1wq_vnum[_{d}]", "vPcld", "iUif", [IsStore], MemEltTyInt32, "aarch64_sve_st1wq">; - def SVST1UDQ : MInst<"svst1udq[_{d}]", "vPcd", "lUld", [IsStore], MemEltTyInt64, "aarch64_sve_st1udq">; - def SVST1UDQ_VNUM : MInst<"svst1udq_vnum[_{d}]", "vPcld", "lUld", [IsStore], MemEltTyInt64, "aarch64_sve_st1udq">; + def SVST1UDQ : MInst<"svst1dq[_{d}]", "vPcd", "lUld", [IsStore], MemEltTyInt64, "aarch64_sve_st1dq">; + def SVST1UDQ_VNUM : MInst<"svst1dq_vnum[_{d}]", "vPcld", "lUld", [IsStore], MemEltTyInt64, "aarch64_sve_st1dq">; // Store one vector (vector base + scalar offset) def SVST1Q_SCATTER_U64BASE_OFFSET : MInst<"svst1q_scatter[_{2}base]_offset[_{d}]", "vPgld", "cUcsUsiUilUlfhdb", [IsScatterStore, IsByteIndexed], MemEltTyDefault, "aarch64_sve_st1q_scatter_scalar_offset">; @@ -2040,12 +2040,12 @@ let TargetGuard = "sve2p1|sme2" in { } let TargetGuard = "sve2p1" in { -def SVDOT_X2_S : SInst<"svdot[_{d}_{2}_{3}]", "ddhh", "i", MergeNone, "aarch64_sve_sdot_x2", [], []>; -def SVDOT_X2_U : SInst<"svdot[_{d}_{2}_{3}]", "ddhh", "Ui", MergeNone, "aarch64_sve_udot_x2", [], []>; -def SVDOT_X2_F : SInst<"svdot[_{d}_{2}_{3}]", "ddhh", "f", MergeNone, "aarch64_sve_fdot_x2", [], []>; -def SVDOT_LANE_X2_S : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "i", MergeNone, "aarch64_sve_sdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; -def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "Ui", MergeNone, "aarch64_sve_udot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; -def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "f", MergeNone, "aarch64_sve_fdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; +def SVDOT_X2_S : SInst<"svdot[_{d}_{2}]", "ddhh", "i", MergeNone, "aarch64_sve_sdot_x2", [], []>; +def SVDOT_X2_U : SInst<"svdot[_{d}_{2}]", "ddhh", "Ui", MergeNone, "aarch64_sve_udot_x2", [], []>; +def SVDOT_X2_F : SInst<"svdot[_{d}_{2}]", "ddhh", "f", MergeNone, "aarch64_sve_fdot_x2", [], []>; +def SVDOT_LANE_X2_S : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "i", MergeNone, "aarch64_sve_sdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; +def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "Ui", MergeNone, "aarch64_sve_udot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; +def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "f", MergeNone, "aarch64_sve_fdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; } let TargetGuard = "sve2p1|sme2" in { @@ -2208,7 +2208,7 @@ let TargetGuard = "sve2p1" in { def SVTBLQ : SInst<"svtblq[_{d}]", "ddu", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_tblq">; def SVTBXQ : SInst<"svtbxq[_{d}]", "dddu", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_tbxq">; // EXTQ - def EXTQ : SInst<"svextq_lane[_{d}]", "dddk", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_extq_lane", [], [ImmCheck<2, ImmCheck0_15>]>; + def EXTQ : SInst<"svextq[_{d}]", "dddk", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_extq", [], [ImmCheck<2, ImmCheck0_15>]>; // PMOV // Move to Pred multiclass PMOV_TO_PRED flags=[], ImmCheckType immCh > { diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index f71dbf1729a1..1ed35befe136 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -9681,8 +9681,8 @@ Value *CodeGenFunction::EmitSVEMaskedStore(const CallExpr *E, bool IsQuadStore = false; switch (IntrinsicID) { - case Intrinsic::aarch64_sve_st1uwq: - case Intrinsic::aarch64_sve_st1udq: + case Intrinsic::aarch64_sve_st1wq: + case Intrinsic::aarch64_sve_st1dq: AddrMemoryTy = llvm::ScalableVectorType::get(MemEltTy, 1); PredTy = llvm::ScalableVectorType::get(IntegerType::get(getLLVMContext(), 1), 1); diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c index d01b59114d54..035ba244f944 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c @@ -26,7 +26,7 @@ // svint32_t test_svdot_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) { - return SVE_ACLE_FUNC(svdot,_s32_s16_s16,)(op1, op2, op3); + return SVE_ACLE_FUNC(svdot,_s32_s16,)(op1, op2, op3); } // CHECK-LABEL: @test_svdot_u32_x2( @@ -41,7 +41,7 @@ svint32_t test_svdot_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) // svuint32_t test_svdot_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) { - return SVE_ACLE_FUNC(svdot,_u32_u16_u16,)(op1, op2, op3); + return SVE_ACLE_FUNC(svdot,_u32_u16,)(op1, op2, op3); } // CHECK-LABEL: @test_svdot_f32_x2( @@ -56,7 +56,7 @@ svuint32_t test_svdot_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) // svfloat32_t test_svdot_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) { - return SVE_ACLE_FUNC(svdot,_f32_f16_f16,)(op1, op2, op3); + return SVE_ACLE_FUNC(svdot,_f32_f16,)(op1, op2, op3); } @@ -73,7 +73,7 @@ svfloat32_t test_svdot_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) // svint32_t test_svdot_lane_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) { - return SVE_ACLE_FUNC(svdot_lane,_s32_s16_s16,)(op1, op2, op3, 3); + return SVE_ACLE_FUNC(svdot_lane,_s32_s16,)(op1, op2, op3, 3); } // CHECK-LABEL: @test_svdot_lane_u32_x2( @@ -88,7 +88,7 @@ svint32_t test_svdot_lane_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) // svuint32_t test_svdot_lane_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) { - return SVE_ACLE_FUNC(svdot_lane,_u32_u16_u16,)(op1, op2, op3, 3); + return SVE_ACLE_FUNC(svdot_lane,_u32_u16,)(op1, op2, op3, 3); } // CHECK-LABEL: @test_svdot_lane_f32_x2( @@ -103,5 +103,5 @@ svuint32_t test_svdot_lane_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3 // svfloat32_t test_svdot_lane_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) { - return SVE_ACLE_FUNC(svdot_lane,_f32_f16_f16,)(op1, op2, op3, 3); + return SVE_ACLE_FUNC(svdot_lane,_f32_f16,)(op1, op2, op3, 3); } diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_extq.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_extq.c index 7704db5667a2..738b290b76cf 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_extq.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_extq.c @@ -20,194 +20,194 @@ #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 #endif -// CHECK-LABEL: define dso_local @test_svextq_lane_u8 +// CHECK-LABEL: define dso_local @test_svextq_u8 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv16i8( [[ZN]], [[ZM]], i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv16i8( [[ZN]], [[ZM]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z19test_svextq_lane_u8u11__SVUint8_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z14test_svextq_u8u11__SVUint8_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0:[0-9]+]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv16i8( [[ZN]], [[ZM]], i32 0) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv16i8( [[ZN]], [[ZM]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] // -svuint8_t test_svextq_lane_u8(svuint8_t zn, svuint8_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _u8,,)(zn, zm, 0); +svuint8_t test_svextq_u8(svuint8_t zn, svuint8_t zm) { + return SVE_ACLE_FUNC(svextq, _u8,,)(zn, zm, 0); } -// CHECK-LABEL: define dso_local @test_svextq_lane_s8 +// CHECK-LABEL: define dso_local @test_svextq_s8 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv16i8( [[ZN]], [[ZM]], i32 4) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv16i8( [[ZN]], [[ZM]], i32 4) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z19test_svextq_lane_s8u10__SVInt8_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z14test_svextq_s8u10__SVInt8_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv16i8( [[ZN]], [[ZM]], i32 4) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv16i8( [[ZN]], [[ZM]], i32 4) // CPP-CHECK-NEXT: ret [[TMP0]] // -svint8_t test_svextq_lane_s8(svint8_t zn, svint8_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _s8,,)(zn, zm, 4); +svint8_t test_svextq_s8(svint8_t zn, svint8_t zm) { + return SVE_ACLE_FUNC(svextq, _s8,,)(zn, zm, 4); } -// CHECK-LABEL: define dso_local @test_svextq_lane_u16 +// CHECK-LABEL: define dso_local @test_svextq_u16 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8i16( [[ZN]], [[ZM]], i32 1) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8i16( [[ZN]], [[ZM]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_u16u12__SVUint16_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_u16u12__SVUint16_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8i16( [[ZN]], [[ZM]], i32 1) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8i16( [[ZN]], [[ZM]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] // -svuint16_t test_svextq_lane_u16(svuint16_t zn, svuint16_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _u16,,)(zn, zm, 1); +svuint16_t test_svextq_u16(svuint16_t zn, svuint16_t zm) { + return SVE_ACLE_FUNC(svextq, _u16,,)(zn, zm, 1); } -// CHECK-LABEL: define dso_local @test_svextq_lane_s16 +// CHECK-LABEL: define dso_local @test_svextq_s16 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8i16( [[ZN]], [[ZM]], i32 5) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8i16( [[ZN]], [[ZM]], i32 5) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_s16u11__SVInt16_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_s16u11__SVInt16_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8i16( [[ZN]], [[ZM]], i32 5) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8i16( [[ZN]], [[ZM]], i32 5) // CPP-CHECK-NEXT: ret [[TMP0]] // -svint16_t test_svextq_lane_s16(svint16_t zn, svint16_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _s16,,)(zn, zm, 5); +svint16_t test_svextq_s16(svint16_t zn, svint16_t zm) { + return SVE_ACLE_FUNC(svextq, _s16,,)(zn, zm, 5); } -// CHECK-LABEL: define dso_local @test_svextq_lane_u32 +// CHECK-LABEL: define dso_local @test_svextq_u32 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv4i32( [[ZN]], [[ZM]], i32 2) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv4i32( [[ZN]], [[ZM]], i32 2) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_u32u12__SVUint32_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_u32u12__SVUint32_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv4i32( [[ZN]], [[ZM]], i32 2) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv4i32( [[ZN]], [[ZM]], i32 2) // CPP-CHECK-NEXT: ret [[TMP0]] // -svuint32_t test_svextq_lane_u32(svuint32_t zn, svuint32_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _u32,,)(zn, zm, 2); +svuint32_t test_svextq_u32(svuint32_t zn, svuint32_t zm) { + return SVE_ACLE_FUNC(svextq, _u32,,)(zn, zm, 2); } -// CHECK-LABEL: define dso_local @test_svextq_lane_s32 +// CHECK-LABEL: define dso_local @test_svextq_s32 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv4i32( [[ZN]], [[ZM]], i32 6) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv4i32( [[ZN]], [[ZM]], i32 6) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_s32u11__SVInt32_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_s32u11__SVInt32_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv4i32( [[ZN]], [[ZM]], i32 6) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv4i32( [[ZN]], [[ZM]], i32 6) // CPP-CHECK-NEXT: ret [[TMP0]] // -svint32_t test_svextq_lane_s32(svint32_t zn, svint32_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _s32,,)(zn, zm, 6); +svint32_t test_svextq_s32(svint32_t zn, svint32_t zm) { + return SVE_ACLE_FUNC(svextq, _s32,,)(zn, zm, 6); } -// CHECK-LABEL: define dso_local @test_svextq_lane_u64 +// CHECK-LABEL: define dso_local @test_svextq_u64 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv2i64( [[ZN]], [[ZM]], i32 3) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv2i64( [[ZN]], [[ZM]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_u64u12__SVUint64_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_u64u12__SVUint64_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv2i64( [[ZN]], [[ZM]], i32 3) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv2i64( [[ZN]], [[ZM]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] // -svuint64_t test_svextq_lane_u64(svuint64_t zn, svuint64_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _u64,,)(zn, zm, 3); +svuint64_t test_svextq_u64(svuint64_t zn, svuint64_t zm) { + return SVE_ACLE_FUNC(svextq, _u64,,)(zn, zm, 3); } -// CHECK-LABEL: define dso_local @test_svextq_lane_s64 +// CHECK-LABEL: define dso_local @test_svextq_s64 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv2i64( [[ZN]], [[ZM]], i32 7) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv2i64( [[ZN]], [[ZM]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_s64u11__SVInt64_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_s64u11__SVInt64_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv2i64( [[ZN]], [[ZM]], i32 7) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv2i64( [[ZN]], [[ZM]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] // -svint64_t test_svextq_lane_s64(svint64_t zn, svint64_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _s64,,)(zn, zm, 7); +svint64_t test_svextq_s64(svint64_t zn, svint64_t zm) { + return SVE_ACLE_FUNC(svextq, _s64,,)(zn, zm, 7); } -// CHECK-LABEL: define dso_local @test_svextq_lane_f16 +// CHECK-LABEL: define dso_local @test_svextq_f16 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8f16( [[ZN]], [[ZM]], i32 8) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8f16( [[ZN]], [[ZM]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_f16u13__SVFloat16_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_f16u13__SVFloat16_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8f16( [[ZN]], [[ZM]], i32 8) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8f16( [[ZN]], [[ZM]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] // -svfloat16_t test_svextq_lane_f16(svfloat16_t zn, svfloat16_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _f16,,)(zn, zm, 8); +svfloat16_t test_svextq_f16(svfloat16_t zn, svfloat16_t zm) { + return SVE_ACLE_FUNC(svextq, _f16,,)(zn, zm, 8); } -// CHECK-LABEL: define dso_local @test_svextq_lane_f32 +// CHECK-LABEL: define dso_local @test_svextq_f32 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv4f32( [[ZN]], [[ZM]], i32 9) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv4f32( [[ZN]], [[ZM]], i32 9) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_f32u13__SVFloat32_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_f32u13__SVFloat32_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv4f32( [[ZN]], [[ZM]], i32 9) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv4f32( [[ZN]], [[ZM]], i32 9) // CPP-CHECK-NEXT: ret [[TMP0]] // -svfloat32_t test_svextq_lane_f32(svfloat32_t zn, svfloat32_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _f32,,)(zn, zm, 9); +svfloat32_t test_svextq_f32(svfloat32_t zn, svfloat32_t zm) { + return SVE_ACLE_FUNC(svextq, _f32,,)(zn, zm, 9); } -// CHECK-LABEL: define dso_local @test_svextq_lane_f64 +// CHECK-LABEL: define dso_local @test_svextq_f64 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv2f64( [[ZN]], [[ZM]], i32 10) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv2f64( [[ZN]], [[ZM]], i32 10) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z20test_svextq_lane_f64u13__SVFloat64_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z15test_svextq_f64u13__SVFloat64_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv2f64( [[ZN]], [[ZM]], i32 10) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv2f64( [[ZN]], [[ZM]], i32 10) // CPP-CHECK-NEXT: ret [[TMP0]] // -svfloat64_t test_svextq_lane_f64(svfloat64_t zn, svfloat64_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _f64,,)(zn, zm, 10); +svfloat64_t test_svextq_f64(svfloat64_t zn, svfloat64_t zm) { + return SVE_ACLE_FUNC(svextq, _f64,,)(zn, zm, 10); } -// CHECK-LABEL: define dso_local @test_svextq_lane_bf16 +// CHECK-LABEL: define dso_local @test_svextq_bf16 // CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8bf16( [[ZN]], [[ZM]], i32 11) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8bf16( [[ZN]], [[ZM]], i32 11) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: define dso_local @_Z21test_svextq_lane_bf16u14__SVBfloat16_tS_ +// CPP-CHECK-LABEL: define dso_local @_Z16test_svextq_bf16u14__SVBfloat16_tS_ // CPP-CHECK-SAME: ( [[ZN:%.*]], [[ZM:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.lane.nxv8bf16( [[ZN]], [[ZM]], i32 11) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.extq.nxv8bf16( [[ZN]], [[ZM]], i32 11) // CPP-CHECK-NEXT: ret [[TMP0]] // -svbfloat16_t test_svextq_lane_bf16(svbfloat16_t zn, svbfloat16_t zm) { - return SVE_ACLE_FUNC(svextq_lane, _bf16,,)(zn, zm, 11); +svbfloat16_t test_svextq_bf16(svbfloat16_t zn, svbfloat16_t zm) { + return SVE_ACLE_FUNC(svextq, _bf16,,)(zn, zm, 11); } diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_st1_single.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_st1_single.c index 52c16faec7f3..27f7b8be7f18 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_st1_single.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_st1_single.c @@ -23,233 +23,233 @@ // ST1W -// CHECK-LABEL: define dso_local void @test_svst1uwq_u32 +// CHECK-LABEL: define dso_local void @test_svst1wq_u32 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z17test_svst1uwq_u32u10__SVBool_tPKju12__SVUint32_t +// CPP-CHECK-LABEL: define dso_local void @_Z16test_svst1wq_u32u10__SVBool_tPKju12__SVUint32_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0:[0-9]+]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) // CPP-CHECK-NEXT: ret void // -void test_svst1uwq_u32(svbool_t pred, uint32_t const * base, svuint32_t zt) { - SVE_ACLE_FUNC(svst1uwq, _u32, , )(pred, base, zt); +void test_svst1wq_u32(svbool_t pred, uint32_t const * base, svuint32_t zt) { + SVE_ACLE_FUNC(svst1wq, _u32, , )(pred, base, zt); } -// CHECK-LABEL: define dso_local void @test_svst1uwq_vnum_u32 +// CHECK-LABEL: define dso_local void @test_svst1wq_vnum_u32 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 1 -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z22test_svst1uwq_vnum_u32u10__SVBool_tPKju12__SVUint32_t +// CPP-CHECK-LABEL: define dso_local void @_Z21test_svst1wq_vnum_u32u10__SVBool_tPKju12__SVUint32_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 1 -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CPP-CHECK-NEXT: ret void // -void test_svst1uwq_vnum_u32(svbool_t pred, uint32_t const * base, svuint32_t zt) { - SVE_ACLE_FUNC(svst1uwq_vnum, _u32, , )(pred, base, 1, zt); +void test_svst1wq_vnum_u32(svbool_t pred, uint32_t const * base, svuint32_t zt) { + SVE_ACLE_FUNC(svst1wq_vnum, _u32, , )(pred, base, 1, zt); } -// CHECK-LABEL: define dso_local void @test_svst1uwq_s32 +// CHECK-LABEL: define dso_local void @test_svst1wq_s32 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z17test_svst1uwq_s32u10__SVBool_tPKiu11__SVInt32_t +// CPP-CHECK-LABEL: define dso_local void @_Z16test_svst1wq_s32u10__SVBool_tPKiu11__SVInt32_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[BASE]]) // CPP-CHECK-NEXT: ret void // -void test_svst1uwq_s32(svbool_t pred, int32_t const * base, svint32_t zt) { - SVE_ACLE_FUNC(svst1uwq, _s32, , )(pred, base, zt); +void test_svst1wq_s32(svbool_t pred, int32_t const * base, svint32_t zt) { + SVE_ACLE_FUNC(svst1wq, _s32, , )(pred, base, zt); } -// CHECK-LABEL: define dso_local void @test_svst1uwq_vnum_s32 +// CHECK-LABEL: define dso_local void @test_svst1wq_vnum_s32 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 1 -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z22test_svst1uwq_vnum_s32u10__SVBool_tPKiu11__SVInt32_t +// CPP-CHECK-LABEL: define dso_local void @_Z21test_svst1wq_vnum_s32u10__SVBool_tPKiu11__SVInt32_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 1 -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4i32( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CPP-CHECK-NEXT: ret void // -void test_svst1uwq_vnum_s32(svbool_t pred, int32_t const * base, svint32_t zt) { - SVE_ACLE_FUNC(svst1uwq_vnum, _s32, , )(pred, base, 1, zt); +void test_svst1wq_vnum_s32(svbool_t pred, int32_t const * base, svint32_t zt) { + SVE_ACLE_FUNC(svst1wq_vnum, _s32, , )(pred, base, 1, zt); } -// CHECK-LABEL: define dso_local void @test_svst1uwq_f32 +// CHECK-LABEL: define dso_local void @test_svst1wq_f32 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4f32( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4f32( [[ZT]], [[TMP0]], ptr [[BASE]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z17test_svst1uwq_f32u10__SVBool_tPKfu13__SVFloat32_t +// CPP-CHECK-LABEL: define dso_local void @_Z16test_svst1wq_f32u10__SVBool_tPKfu13__SVFloat32_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4f32( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4f32( [[ZT]], [[TMP0]], ptr [[BASE]]) // CPP-CHECK-NEXT: ret void // -void test_svst1uwq_f32(svbool_t pred, float32_t const * base, svfloat32_t zt) { - SVE_ACLE_FUNC(svst1uwq, _f32, , )(pred, base, zt); +void test_svst1wq_f32(svbool_t pred, float32_t const * base, svfloat32_t zt) { + SVE_ACLE_FUNC(svst1wq, _f32, , )(pred, base, zt); } -// CHECK-LABEL: define dso_local void @test_svst1uwq_vnum_f32 +// CHECK-LABEL: define dso_local void @test_svst1wq_vnum_f32 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 1 -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4f32( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4f32( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z22test_svst1uwq_vnum_f32u10__SVBool_tPKfu13__SVFloat32_t +// CPP-CHECK-LABEL: define dso_local void @_Z21test_svst1wq_vnum_f32u10__SVBool_tPKfu13__SVFloat32_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 1 -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1uwq.nxv4f32( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1wq.nxv4f32( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CPP-CHECK-NEXT: ret void // -void test_svst1uwq_vnum_f32(svbool_t pred, float32_t const * base, svfloat32_t zt) { - SVE_ACLE_FUNC(svst1uwq_vnum, _f32, , )(pred, base, 1, zt); +void test_svst1wq_vnum_f32(svbool_t pred, float32_t const * base, svfloat32_t zt) { + SVE_ACLE_FUNC(svst1wq_vnum, _f32, , )(pred, base, 1, zt); } // ST1D -// CHECK-LABEL: define dso_local void @test_svst1udq_u64 +// CHECK-LABEL: define dso_local void @test_svst1dq_u64 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z17test_svst1udq_u64u10__SVBool_tPKmu12__SVUint64_t +// CPP-CHECK-LABEL: define dso_local void @_Z16test_svst1dq_u64u10__SVBool_tPKmu12__SVUint64_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) // CPP-CHECK-NEXT: ret void // -void test_svst1udq_u64(svbool_t pred, uint64_t const * base, svuint64_t zt) { - SVE_ACLE_FUNC(svst1udq, _u64, , )(pred, base, zt); +void test_svst1dq_u64(svbool_t pred, uint64_t const * base, svuint64_t zt) { + SVE_ACLE_FUNC(svst1dq, _u64, , )(pred, base, zt); } -// CHECK-LABEL: define dso_local void @test_svst1udq_vnum_u64 +// CHECK-LABEL: define dso_local void @test_svst1dq_vnum_u64 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 -8 -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z22test_svst1udq_vnum_u64u10__SVBool_tPKmu12__SVUint64_t +// CPP-CHECK-LABEL: define dso_local void @_Z21test_svst1dq_vnum_u64u10__SVBool_tPKmu12__SVUint64_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 -8 -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CPP-CHECK-NEXT: ret void // -void test_svst1udq_vnum_u64(svbool_t pred, uint64_t const * base, svuint64_t zt) { - SVE_ACLE_FUNC(svst1udq_vnum, _u64, , )(pred, base, -8, zt); +void test_svst1dq_vnum_u64(svbool_t pred, uint64_t const * base, svuint64_t zt) { + SVE_ACLE_FUNC(svst1dq_vnum, _u64, , )(pred, base, -8, zt); } -// CHECK-LABEL: define dso_local void @test_svst1udq_s64 +// CHECK-LABEL: define dso_local void @test_svst1dq_s64 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z17test_svst1udq_s64u10__SVBool_tPKlu11__SVInt64_t +// CPP-CHECK-LABEL: define dso_local void @_Z16test_svst1dq_s64u10__SVBool_tPKlu11__SVInt64_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[BASE]]) // CPP-CHECK-NEXT: ret void // -void test_svst1udq_s64(svbool_t pred, int64_t const * base, svint64_t zt) { - SVE_ACLE_FUNC(svst1udq, _s64, , )(pred, base, zt); +void test_svst1dq_s64(svbool_t pred, int64_t const * base, svint64_t zt) { + SVE_ACLE_FUNC(svst1dq, _s64, , )(pred, base, zt); } -// CHECK-LABEL: define dso_local void @test_svst1udq_vnum_s64 +// CHECK-LABEL: define dso_local void @test_svst1dq_vnum_s64 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 -8 -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z22test_svst1udq_vnum_s64u10__SVBool_tPKlu11__SVInt64_t +// CPP-CHECK-LABEL: define dso_local void @_Z21test_svst1dq_vnum_s64u10__SVBool_tPKlu11__SVInt64_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 -8 -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2i64( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CPP-CHECK-NEXT: ret void // -void test_svst1udq_vnum_s64(svbool_t pred, int64_t const * base, svint64_t zt) { - SVE_ACLE_FUNC(svst1udq_vnum, _s64, , )(pred, base, -8, zt); +void test_svst1dq_vnum_s64(svbool_t pred, int64_t const * base, svint64_t zt) { + SVE_ACLE_FUNC(svst1dq_vnum, _s64, , )(pred, base, -8, zt); } -// CHECK-LABEL: define dso_local void @test_svst1udq_f64 +// CHECK-LABEL: define dso_local void @test_svst1dq_f64 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2f64( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2f64( [[ZT]], [[TMP0]], ptr [[BASE]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z17test_svst1udq_f64u10__SVBool_tPKdu13__SVFloat64_t +// CPP-CHECK-LABEL: define dso_local void @_Z16test_svst1dq_f64u10__SVBool_tPKdu13__SVFloat64_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2f64( [[ZT]], [[TMP0]], ptr [[BASE]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2f64( [[ZT]], [[TMP0]], ptr [[BASE]]) // CPP-CHECK-NEXT: ret void // -void test_svst1udq_f64(svbool_t pred, float64_t const * base, svfloat64_t zt) { - SVE_ACLE_FUNC(svst1udq, _f64, , )(pred, base, zt); +void test_svst1dq_f64(svbool_t pred, float64_t const * base, svfloat64_t zt) { + SVE_ACLE_FUNC(svst1dq, _f64, , )(pred, base, zt); } -// CHECK-LABEL: define dso_local void @test_svst1udq_vnum_f64 +// CHECK-LABEL: define dso_local void @test_svst1dq_vnum_f64 // CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 -8 -// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2f64( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2f64( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: define dso_local void @_Z22test_svst1udq_vnum_f64u10__SVBool_tPKdu13__SVFloat64_t +// CPP-CHECK-LABEL: define dso_local void @_Z21test_svst1dq_vnum_f64u10__SVBool_tPKdu13__SVFloat64_t // CPP-CHECK-SAME: ( [[PRED:%.*]], ptr noundef [[BASE:%.*]], [[ZT:%.*]]) #[[ATTR0]] { // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( [[PRED]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE]], i64 -8 -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1udq.nxv2f64( [[ZT]], [[TMP0]], ptr [[TMP1]]) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1dq.nxv2f64( [[ZT]], [[TMP0]], ptr [[TMP1]]) // CPP-CHECK-NEXT: ret void // -void test_svst1udq_vnum_f64(svbool_t pred, float64_t const * base, svfloat64_t zt) { - SVE_ACLE_FUNC(svst1udq_vnum, _f64, , )(pred, base, -8, zt); +void test_svst1dq_vnum_f64(svbool_t pred, float64_t const * base, svfloat64_t zt) { + SVE_ACLE_FUNC(svst1dq_vnum, _f64, , )(pred, base, -8, zt); } diff --git a/clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp b/clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp index a3ec4c5b8b1b..a6154daadeea 100644 --- a/clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp +++ b/clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp @@ -114,9 +114,9 @@ void test_cntp(svcount_t c) { void test_svdot_lane_2way(svint32_t s32, svuint32_t u32, svint16_t s16, svuint16_t u16, svfloat32_t f32, svfloat16_t f16) { - svdot_lane_s32_s16_s16(s32, s16, s16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} - svdot_lane_u32_u16_u16(u32, u16, u16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} - svdot_lane_f32_f16_f16(f32, f16, f16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + svdot_lane_s32_s16(s32, s16, s16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + svdot_lane_u32_u16(u32, u16, u16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + svdot_lane_f32_f16(f32, f16, f16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} } @@ -139,8 +139,8 @@ void test_svbfmul_lane(svbfloat16_t zn, svbfloat16_t zm, uint64_t idx){ __attribute__((target("+sve2p1"))) void test_svextq_lane(svint16_t zn_i16, svint16_t zm_i16, svfloat16_t zn_f16, svfloat16_t zm_f16){ - svextq_lane_s16(zn_i16, zm_i16, -1); // expected-error {{argument value -1 is outside the valid range [0, 15]}} - svextq_lane_f16(zn_f16, zm_f16, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} + svextq_s16(zn_i16, zm_i16, -1); // expected-error {{argument value -1 is outside the valid range [0, 15]}} + svextq_f16(zn_f16, zm_f16, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} } __attribute__((target("+sve2p1"))) diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index 9088168b4c67..acff5c20b1b9 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -2708,8 +2708,8 @@ class SVE2p1_Single_Store_Quadword : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, llvm_nxv1i1_ty, llvm_ptr_ty], [IntrWriteMem, IntrArgMemOnly]>; -def int_aarch64_sve_st1uwq : SVE2p1_Single_Store_Quadword; -def int_aarch64_sve_st1udq : SVE2p1_Single_Store_Quadword; +def int_aarch64_sve_st1wq : SVE2p1_Single_Store_Quadword; +def int_aarch64_sve_st1dq : SVE2p1_Single_Store_Quadword; def int_aarch64_sve_ld2q_sret : AdvSIMD_2Vec_PredLoad_Intrinsic; @@ -3617,7 +3617,7 @@ def int_aarch64_sve_tbxq : AdvSIMD_SVE2_TBX_Intrinsic; // SVE2.1 - Extract vector segment from each pair of quadword segments. // -def int_aarch64_sve_extq_lane : AdvSIMD_2VectorArgIndexed_Intrinsic; +def int_aarch64_sve_extq : AdvSIMD_2VectorArgIndexed_Intrinsic; // // SVE2.1 - Move predicate to/from vector diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index edc8cc7d4d1e..ea5679b4d5e3 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -6834,10 +6834,10 @@ static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) { return getPackedVectorTypeFromPredicateType( Ctx, Root->getOperand(6)->getValueType(0), /*NumVec=*/4); case Intrinsic::aarch64_sve_ld1udq: - case Intrinsic::aarch64_sve_st1udq: + case Intrinsic::aarch64_sve_st1dq: return EVT(MVT::nxv1i64); case Intrinsic::aarch64_sve_ld1uwq: - case Intrinsic::aarch64_sve_st1uwq: + case Intrinsic::aarch64_sve_st1wq: return EVT(MVT::nxv1i32); } } diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index ee10a7d1c706..26102f922d99 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1397,17 +1397,17 @@ let Predicates = [HasSVEorSME] in { (RegImmInst Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$base, (i64 0))>; } - // ld1quw/st1quw + // ld1quw/st1qw defm : sve_ld1q_pat; defm : sve_ld1q_pat; - defm : sve_st1q_pat; - defm : sve_st1q_pat; + defm : sve_st1q_pat; + defm : sve_st1q_pat; - // ld1qud/st1qud + // ld1qud/st1qd defm : sve_ld1q_pat; defm : sve_ld1q_pat; - defm : sve_st1q_pat; - defm : sve_st1q_pat; + defm : sve_st1q_pat; + defm : sve_st1q_pat; } // End HasSVEorSME @@ -4095,7 +4095,7 @@ defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv", int_aarch64_sve_fmaxqv>; defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv", int_aarch64_sve_fminqv>; defm DUPQ_ZZI : sve2p1_dupq<"dupq">; -defm EXTQ_ZZI : sve2p1_extq<"extq", int_aarch64_sve_extq_lane>; +defm EXTQ_ZZI : sve2p1_extq<"extq", int_aarch64_sve_extq>; defm PMOV_PZI : sve2p1_vector_to_pred<"pmov", int_aarch64_sve_pmov_to_pred_lane, int_aarch64_sve_pmov_to_pred_lane_zero>; defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov", int_aarch64_sve_pmov_to_vector_lane_merging, int_aarch64_sve_pmov_to_vector_lane_zeroing>; diff --git a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll index efe19432f9c3..a49aa7cfcf8a 100644 --- a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll +++ b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll @@ -6,7 +6,7 @@ define @test_extq_i8 ( %zn, @llvm.aarch64.sve.extq.lane.nxv16i8( %zn, %zm, i32 0) + %res = call @llvm.aarch64.sve.extq.nxv16i8( %zn, %zm, i32 0) ret %res } @@ -15,7 +15,7 @@ define @test_extq_i16 ( %zn, @llvm.aarch64.sve.extq.lane.nxv8i16( %zn, %zm, i32 1) + %res = call @llvm.aarch64.sve.extq.nxv8i16( %zn, %zm, i32 1) ret %res } @@ -24,7 +24,7 @@ define @test_extq_i32 ( %zn, @llvm.aarch64.sve.extq.lane.nxv4i32( %zn, %zm, i32 2) + %res = call @llvm.aarch64.sve.extq.nxv4i32( %zn, %zm, i32 2) ret %res } @@ -33,7 +33,7 @@ define @test_extq_i64 ( %zn, @llvm.aarch64.sve.extq.lane.nxv2i64( %zn, %zm, i32 3) + %res = call @llvm.aarch64.sve.extq.nxv2i64( %zn, %zm, i32 3) ret %res } @@ -42,7 +42,7 @@ define @test_extq_f16( %zn, @llvm.aarch64.sve.extq.lane.nxv8f16( %zn, %zm, i32 4) + %res = call @llvm.aarch64.sve.extq.nxv8f16( %zn, %zm, i32 4) ret %res } @@ -51,7 +51,7 @@ define @test_extq_f32( %zn, @llvm.aarch64.sve.extq.lane.nxv4f32( %zn, %zm, i32 5) + %res = call @llvm.aarch64.sve.extq.nxv4f32( %zn, %zm, i32 5) ret %res } @@ -60,7 +60,7 @@ define @test_extq_f64( %zn, @llvm.aarch64.sve.extq.lane.nxv2f64( %zn, %zm, i32 6) + %res = call @llvm.aarch64.sve.extq.nxv2f64( %zn, %zm, i32 6) ret %res } @@ -69,15 +69,15 @@ define @test_extq_bf16( %zn, @llvm.aarch64.sve.extq.lane.nxv8bf16( %zn, %zm, i32 15) + %res = call @llvm.aarch64.sve.extq.nxv8bf16( %zn, %zm, i32 15) ret %res } -declare @llvm.aarch64.sve.extq.lane.nxv16i8(, , i32) -declare @llvm.aarch64.sve.extq.lane.nxv8i16(, , i32) -declare @llvm.aarch64.sve.extq.lane.nxv4i32(, , i32) -declare @llvm.aarch64.sve.extq.lane.nxv2i64(, , i32) -declare @llvm.aarch64.sve.extq.lane.nxv8f16(, , i32) -declare @llvm.aarch64.sve.extq.lane.nxv4f32(, , i32) -declare @llvm.aarch64.sve.extq.lane.nxv2f64(, , i32) -declare @llvm.aarch64.sve.extq.lane.nxv8bf16(, , i32) +declare @llvm.aarch64.sve.extq.nxv16i8(, , i32) +declare @llvm.aarch64.sve.extq.nxv8i16(, , i32) +declare @llvm.aarch64.sve.extq.nxv4i32(, , i32) +declare @llvm.aarch64.sve.extq.nxv2i64(, , i32) +declare @llvm.aarch64.sve.extq.nxv8f16(, , i32) +declare @llvm.aarch64.sve.extq.nxv4f32(, , i32) +declare @llvm.aarch64.sve.extq.nxv2f64(, , i32) +declare @llvm.aarch64.sve.extq.nxv8bf16(, , i32) diff --git a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll index e93673c79c30..894c647453f5 100644 --- a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll +++ b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll @@ -3,128 +3,128 @@ ; ST1W -define void @test_svst1uwq_i32_ss( %zt, %pred, ptr %base, i64 %offset) { -; CHECK-LABEL: test_svst1uwq_i32_ss: +define void @test_svst1wq_i32_ss( %zt, %pred, ptr %base, i64 %offset) { +; CHECK-LABEL: test_svst1wq_i32_ss: ; CHECK: // %bb.0: ; CHECK-NEXT: st1w { z0.q }, p0, [x0, x1, lsl #2] ; CHECK-NEXT: ret %gep = getelementptr i32, ptr %base, i64 %offset - call void @llvm.aarch64.sve.st1uwq.nxv4i32( %zt, %pred, ptr %gep) + call void @llvm.aarch64.sve.st1wq.nxv4i32( %zt, %pred, ptr %gep) ret void } -define void @test_svst1uwq_i32_si( %zt, %pred, * %base) { -; CHECK-LABEL: test_svst1uwq_i32_si: +define void @test_svst1wq_i32_si( %zt, %pred, * %base) { +; CHECK-LABEL: test_svst1wq_i32_si: ; CHECK: // %bb.0: ; CHECK-NEXT: st1w { z0.q }, p0, [x0, #-8, mul vl] ; CHECK-NEXT: st1w { z0.q }, p0, [x0, #7, mul vl] ; CHECK-NEXT: ret %gep1 = getelementptr inbounds , * %base, i64 -8 - call void @llvm.aarch64.sve.st1uwq.nxv4i32( %zt, %pred, ptr %gep1) + call void @llvm.aarch64.sve.st1wq.nxv4i32( %zt, %pred, ptr %gep1) %gep2 = getelementptr inbounds , * %base, i64 7 - call void @llvm.aarch64.sve.st1uwq.nxv4i32( %zt, %pred, ptr %gep2) + call void @llvm.aarch64.sve.st1wq.nxv4i32( %zt, %pred, ptr %gep2) ret void } -define void @test_svst1uwq_i32_out_of_bound( %zt, %pred, * %base) { -; CHECK-LABEL: test_svst1uwq_i32_out_of_bound: +define void @test_svst1wq_i32_out_of_bound( %zt, %pred, * %base) { +; CHECK-LABEL: test_svst1wq_i32_out_of_bound: ; CHECK: // %bb.0: ; CHECK-NEXT: addvl x8, x0, #2 ; CHECK-NEXT: st1w { z0.q }, p0, [x8] ; CHECK-NEXT: ret %gep = getelementptr inbounds , * %base, i64 8 - call void @llvm.aarch64.sve.st1uwq.nxv4i32( %zt, %pred, ptr %gep) + call void @llvm.aarch64.sve.st1wq.nxv4i32( %zt, %pred, ptr %gep) ret void } -define void @test_svst1uwq_f32_ss( %zt, %pred, ptr %base, i64 %offset) { -; CHECK-LABEL: test_svst1uwq_f32_ss: +define void @test_svst1wq_f32_ss( %zt, %pred, ptr %base, i64 %offset) { +; CHECK-LABEL: test_svst1wq_f32_ss: ; CHECK: // %bb.0: ; CHECK-NEXT: st1w { z0.q }, p0, [x0, x1, lsl #2] ; CHECK-NEXT: ret %gep = getelementptr float, ptr %base, i64 %offset - call void @llvm.aarch64.sve.st1uwq.nxv4f32( %zt, %pred, ptr %gep) + call void @llvm.aarch64.sve.st1wq.nxv4f32( %zt, %pred, ptr %gep) ret void } -define void @test_svst1uwq_f32_si( %zt, %pred, * %base) { -; CHECK-LABEL: test_svst1uwq_f32_si: +define void @test_svst1wq_f32_si( %zt, %pred, * %base) { +; CHECK-LABEL: test_svst1wq_f32_si: ; CHECK: // %bb.0: ; CHECK-NEXT: st1w { z0.q }, p0, [x0, #-8, mul vl] ; CHECK-NEXT: st1w { z0.q }, p0, [x0, #7, mul vl] ; CHECK-NEXT: ret %gep1 = getelementptr inbounds , * %base, i64 -8 - call void @llvm.aarch64.sve.st1uwq.nxv4f32( %zt, %pred, ptr %gep1) + call void @llvm.aarch64.sve.st1wq.nxv4f32( %zt, %pred, ptr %gep1) %gep2 = getelementptr inbounds , * %base, i64 7 - call void @llvm.aarch64.sve.st1uwq.nxv4f32( %zt, %pred, ptr %gep2) + call void @llvm.aarch64.sve.st1wq.nxv4f32( %zt, %pred, ptr %gep2) ret void } ; ST1D -define void @test_svst1udq_i64_ss( %zt, %pred, ptr %base, i64 %offset) { -; CHECK-LABEL: test_svst1udq_i64_ss: +define void @test_svst1dq_i64_ss( %zt, %pred, ptr %base, i64 %offset) { +; CHECK-LABEL: test_svst1dq_i64_ss: ; CHECK: // %bb.0: ; CHECK-NEXT: st1d { z0.q }, p0, [x0, x1, lsl #3] ; CHECK-NEXT: ret %gep = getelementptr i64, ptr %base, i64 %offset - call void @llvm.aarch64.sve.st1udq.nxv2i64( %zt, %pred, ptr %gep) + call void @llvm.aarch64.sve.st1dq.nxv2i64( %zt, %pred, ptr %gep) ret void } -define void @test_svst1udq_i64_si( %zt, %pred, * %base) { -; CHECK-LABEL: test_svst1udq_i64_si: +define void @test_svst1dq_i64_si( %zt, %pred, * %base) { +; CHECK-LABEL: test_svst1dq_i64_si: ; CHECK: // %bb.0: ; CHECK-NEXT: st1d { z0.q }, p0, [x0, #-8, mul vl] ; CHECK-NEXT: st1d { z0.q }, p0, [x0, #7, mul vl] ; CHECK-NEXT: ret %gep1 = getelementptr inbounds , * %base, i64 -8 - call void @llvm.aarch64.sve.st1udq.nxv2i64( %zt, %pred, ptr %gep1) + call void @llvm.aarch64.sve.st1dq.nxv2i64( %zt, %pred, ptr %gep1) %gep2 = getelementptr inbounds , * %base, i64 7 - call void @llvm.aarch64.sve.st1udq.nxv2i64( %zt, %pred, ptr %gep2) + call void @llvm.aarch64.sve.st1dq.nxv2i64( %zt, %pred, ptr %gep2) ret void } -define void @test_svst1udq_i64_out_of_bound( %zt, %pred, * %base) { -; CHECK-LABEL: test_svst1udq_i64_out_of_bound: +define void @test_svst1dq_i64_out_of_bound( %zt, %pred, * %base) { +; CHECK-LABEL: test_svst1dq_i64_out_of_bound: ; CHECK: // %bb.0: ; CHECK-NEXT: addvl x8, x0, #-5 ; CHECK-NEXT: st1d { z0.q }, p0, [x8] ; CHECK-NEXT: ret %gep = getelementptr inbounds , * %base, i64 -10 - call void @llvm.aarch64.sve.st1udq.nxv2i64( %zt, %pred, ptr %gep) + call void @llvm.aarch64.sve.st1dq.nxv2i64( %zt, %pred, ptr %gep) ret void } -define void @test_svst1udq_f64_ss( %zt, %pred, ptr %base, i64 %offset) { -; CHECK-LABEL: test_svst1udq_f64_ss: +define void @test_svst1dq_f64_ss( %zt, %pred, ptr %base, i64 %offset) { +; CHECK-LABEL: test_svst1dq_f64_ss: ; CHECK: // %bb.0: ; CHECK-NEXT: st1d { z0.q }, p0, [x0, x1, lsl #3] ; CHECK-NEXT: ret %gep = getelementptr double, ptr %base, i64 %offset - call void @llvm.aarch64.sve.st1udq.nxv2f64( %zt, %pred, ptr %gep) + call void @llvm.aarch64.sve.st1dq.nxv2f64( %zt, %pred, ptr %gep) ret void } -define void @test_svst1udq_f64_si( %zt, %pred, * %base) { -; CHECK-LABEL: test_svst1udq_f64_si: +define void @test_svst1dq_f64_si( %zt, %pred, * %base) { +; CHECK-LABEL: test_svst1dq_f64_si: ; CHECK: // %bb.0: ; CHECK-NEXT: st1d { z0.q }, p0, [x0, #-8, mul vl] ; CHECK-NEXT: st1d { z0.q }, p0, [x0, #7, mul vl] ; CHECK-NEXT: ret %gep1 = getelementptr inbounds , * %base, i64 -8 - call void @llvm.aarch64.sve.st1udq.nxv2f64( %zt, %pred, ptr %gep1) + call void @llvm.aarch64.sve.st1dq.nxv2f64( %zt, %pred, ptr %gep1) %gep2 = getelementptr inbounds , * %base, i64 7 - call void @llvm.aarch64.sve.st1udq.nxv2f64( %zt, %pred, ptr %gep2) + call void @llvm.aarch64.sve.st1dq.nxv2f64( %zt, %pred, ptr %gep2) ret void } -declare void @llvm.aarch64.sve.st1uwq.nxv4i32(, , ptr) -declare void @llvm.aarch64.sve.st1uwq.nxv4f32(, , ptr) +declare void @llvm.aarch64.sve.st1wq.nxv4i32(, , ptr) +declare void @llvm.aarch64.sve.st1wq.nxv4f32(, , ptr) -declare void @llvm.aarch64.sve.st1udq.nxv2i64(, , ptr) -declare void @llvm.aarch64.sve.st1udq.nxv2f64(, , ptr) +declare void @llvm.aarch64.sve.st1dq.nxv2i64(, , ptr) +declare void @llvm.aarch64.sve.st1dq.nxv2f64(, , ptr) -- GitLab From c053e9f0f4b56a56582ad149a8c89434126eff7f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Jan 2024 09:18:40 -0800 Subject: [PATCH 354/652] [RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#77418) This changes the register class to GPRPair and adds the destination register as a source with a tied operand constraint. Parsing for the paired register is done with a custom parser that checks for even register and converts it to its pair version. A bit of care needs to be taken so that we only parse as a pair register based on which instruction we're parsing and the mode in the subtarget. This allows amocas.w to be parsed correcty in both modes. I've added a FIXME to note that we should be creating pair registers for Zdinx on RV32 to match the instructions CodeGen generates. --- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 75 +++++++++++++------ .../RISCV/Disassembler/RISCVDisassembler.cpp | 4 + llvm/lib/Target/RISCV/RISCVInstrInfoZa.td | 47 +++++++++++- llvm/test/MC/RISCV/rv32zacas-invalid.s | 20 ++--- llvm/test/MC/RISCV/rv64zacas-invalid.s | 18 ++--- 5 files changed, 121 insertions(+), 43 deletions(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 4250950a9172..7d42481db57f 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -199,6 +199,8 @@ class RISCVAsmParser : public MCTargetAsmParser { ParseStatus parseInsnDirectiveOpcode(OperandVector &Operands); ParseStatus parseInsnCDirectiveOpcode(OperandVector &Operands); ParseStatus parseGPRAsFPR(OperandVector &Operands); + template ParseStatus parseGPRPair(OperandVector &Operands); + ParseStatus parseGPRPair(OperandVector &Operands, bool IsRV64Inst); ParseStatus parseFRMArg(OperandVector &Operands); ParseStatus parseFenceArg(OperandVector &Operands); ParseStatus parseReglist(OperandVector &Operands); @@ -466,6 +468,12 @@ public: bool isGPRAsFPR() const { return isGPR() && Reg.IsGPRAsFPR; } + bool isGPRPair() const { + return Kind == KindTy::Register && + RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains( + Reg.RegNum); + } + static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, RISCVMCExpr::VariantKind &VK) { if (auto *RE = dyn_cast(Expr)) { @@ -1300,6 +1308,10 @@ unsigned RISCVAsmParser::checkTargetMatchPredicate(MCInst &Inst) { assert(Op.isReg()); MCRegister Reg = Op.getReg(); + if (RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg)) + continue; + + // FIXME: We should form a paired register during parsing/matching. if (((Reg.id() - RISCV::X0) & 1) != 0) return Match_RequiresEvenGPRs; } @@ -2222,6 +2234,48 @@ ParseStatus RISCVAsmParser::parseGPRAsFPR(OperandVector &Operands) { return ParseStatus::Success; } +template +ParseStatus RISCVAsmParser::parseGPRPair(OperandVector &Operands) { + return parseGPRPair(Operands, IsRV64); +} + +ParseStatus RISCVAsmParser::parseGPRPair(OperandVector &Operands, + bool IsRV64Inst) { + // If this is not an RV64 GPRPair instruction, don't parse as a GPRPair on + // RV64 as it will prevent matching the RV64 version of the same instruction + // that doesn't use a GPRPair. + // If this is an RV64 GPRPair instruction, there is no RV32 version so we can + // still parse as a pair. + if (!IsRV64Inst && isRV64()) + return ParseStatus::NoMatch; + + if (getLexer().isNot(AsmToken::Identifier)) + return ParseStatus::NoMatch; + + StringRef Name = getLexer().getTok().getIdentifier(); + MCRegister RegNo = matchRegisterNameHelper(isRVE(), Name); + + if (!RegNo) + return ParseStatus::NoMatch; + + if (!RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(RegNo)) + return ParseStatus::NoMatch; + + if ((RegNo - RISCV::X0) & 1) + return TokError("register must be even"); + + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size()); + getLexer().Lex(); + + const MCRegisterInfo *RI = getContext().getRegisterInfo(); + unsigned Pair = RI->getMatchingSuperReg( + RegNo, RISCV::sub_gpr_even, + &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]); + Operands.push_back(RISCVOperand::createReg(Pair, S, E)); + return ParseStatus::Success; +} + ParseStatus RISCVAsmParser::parseFRMArg(OperandVector &Operands) { if (getLexer().isNot(AsmToken::Identifier)) return TokError( @@ -3335,27 +3389,6 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst, return Error(Loc, "Operand must be constant 4."); } - bool IsAMOCAS_D = Opcode == RISCV::AMOCAS_D || Opcode == RISCV::AMOCAS_D_AQ || - Opcode == RISCV::AMOCAS_D_RL || - Opcode == RISCV::AMOCAS_D_AQ_RL; - bool IsAMOCAS_Q = Opcode == RISCV::AMOCAS_Q || Opcode == RISCV::AMOCAS_Q_AQ || - Opcode == RISCV::AMOCAS_Q_RL || - Opcode == RISCV::AMOCAS_Q_AQ_RL; - if ((!isRV64() && IsAMOCAS_D) || IsAMOCAS_Q) { - unsigned Rd = Inst.getOperand(0).getReg(); - unsigned Rs2 = Inst.getOperand(2).getReg(); - assert(Rd >= RISCV::X0 && Rd <= RISCV::X31); - if ((Rd - RISCV::X0) % 2 != 0) { - SMLoc Loc = Operands[1]->getStartLoc(); - return Error(Loc, "The destination register must be even."); - } - assert(Rs2 >= RISCV::X0 && Rs2 <= RISCV::X31); - if ((Rs2 - RISCV::X0) % 2 != 0) { - SMLoc Loc = Operands[2]->getStartLoc(); - return Error(Loc, "The source register must be even."); - } - } - const MCInstrDesc &MCID = MII.get(Opcode); if (!(MCID.TSFlags & RISCVII::ConstraintMask)) return false; diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index bc65cf2403b2..4dd039159e29 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -546,6 +546,10 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, !STI.hasFeature(RISCV::Feature64Bit), DecoderTableRV32Zdinx32, "RV32Zdinx table (Double in Integer and rv32)"); + TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) && + !STI.hasFeature(RISCV::Feature64Bit), + DecoderTableRV32Zacas32, + "RV32Zacas table (Compare-And-Swap and rv32)"); TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32, "RVZfinx table (Float in Integer)"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td index a09f5715b24f..ea8046d119d0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td @@ -17,13 +17,54 @@ // Zacas (Atomic Compare-and-Swap) //===----------------------------------------------------------------------===// +def GPRPairRV32Operand : AsmOperandClass { + let Name = "GPRPairRV32"; + let ParserMethod = "parseGPRPair"; + let PredicateMethod = "isGPRPair"; + let RenderMethod = "addRegOperands"; +} + +def GPRPairRV64Operand : AsmOperandClass { + let Name = "GPRPairRV64"; + let ParserMethod = "parseGPRPair"; + let PredicateMethod = "isGPRPair"; + let RenderMethod = "addRegOperands"; +} + +def GPRPairRV32 : RegisterOperand { + let ParserMatchClass = GPRPairRV32Operand; +} + +def GPRPairRV64 : RegisterOperand { + let ParserMatchClass = GPRPairRV64Operand; +} + +let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "$rd = $rd_wb" in +class AMO_cas funct5, bit aq, bit rl, bits<3> funct3, string opcodestr, + DAGOperand RC> + : RVInstRAtomic; + +multiclass AMO_cas_aq_rl funct5, bits<3> funct3, string opcodestr, + DAGOperand RC> { + def "" : AMO_cas; + def _AQ : AMO_cas; + def _RL : AMO_cas; + def _AQ_RL : AMO_cas; +} + let Predicates = [HasStdExtZacas] in { -defm AMOCAS_W : AMO_rr_aq_rl<0b00101, 0b010, "amocas.w">; -defm AMOCAS_D : AMO_rr_aq_rl<0b00101, 0b011, "amocas.d">; +defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>; } // Predicates = [HasStdExtZacas] +let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32Zacas" in { +defm AMOCAS_D_RV32 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPRPairRV32>; +} // Predicates = [HasStdExtZacas, IsRV32] + let Predicates = [HasStdExtZacas, IsRV64] in { -defm AMOCAS_Q : AMO_rr_aq_rl<0b00101, 0b100, "amocas.q">; +defm AMOCAS_D_RV64 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPR>; +defm AMOCAS_Q : AMO_cas_aq_rl<0b00101, 0b100, "amocas.q", GPRPairRV64>; } // Predicates = [HasStdExtZacas, IsRV64] //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/RISCV/rv32zacas-invalid.s b/llvm/test/MC/RISCV/rv32zacas-invalid.s index f6a5858d9b3e..b86246ca2ed1 100644 --- a/llvm/test/MC/RISCV/rv32zacas-invalid.s +++ b/llvm/test/MC/RISCV/rv32zacas-invalid.s @@ -2,17 +2,17 @@ # Non-zero offsets not supported for the third operand (rs1). amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 -amocas.d a1, a3, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 +amocas.d a0, a2, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 # First and second operands (rd and rs2) of amocas.d must be even for RV32. -amocas.d a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: The destination register must be even. -amocas.d a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: The source register must be even. -amocas.d.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even. -amocas.d.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even. -amocas.d.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even. -amocas.d.rl a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even. -amocas.d.aqrl a1, a2, (a1) # CHECK: :[[@LINE]]:15: error: The destination register must be even. -amocas.d.aqrl a0, a1, (a1) # CHECK: :[[@LINE]]:19: error: The source register must be even. +amocas.d a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: register must be even +amocas.d a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: register must be even +amocas.d.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: register must be even +amocas.d.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: register must be even +amocas.d.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: register must be even +amocas.d.rl a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: register must be even +amocas.d.aqrl a1, a2, (a1) # CHECK: :[[@LINE]]:15: error: register must be even +amocas.d.aqrl a0, a1, (a1) # CHECK: :[[@LINE]]:19: error: register must be even # amocas.q is not supported for RV32. -amocas.q a1, a1, (a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +amocas.q a0, a0, (a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv64zacas-invalid.s b/llvm/test/MC/RISCV/rv64zacas-invalid.s index feb570a29527..e6a4e4007e97 100644 --- a/llvm/test/MC/RISCV/rv64zacas-invalid.s +++ b/llvm/test/MC/RISCV/rv64zacas-invalid.s @@ -3,14 +3,14 @@ # Non-zero offsets not supported for the third operand (rs1). amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 amocas.d a1, a3, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 -amocas.q a1, a3, 3(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 +amocas.q a0, a2, 3(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 # First and second operands (rd and rs2) of amocas.q must be even. -amocas.q a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: The destination register must be even. -amocas.q a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: The source register must be even. -amocas.q.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even. -amocas.q.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even. -amocas.q.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even. -amocas.q.rl a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even. -amocas.q.aqrl a1, a2, (a1) # CHECK: :[[@LINE]]:15: error: The destination register must be even. -amocas.q.aqrl a0, a1, (a1) # CHECK: :[[@LINE]]:19: error: The source register must be even. +amocas.q a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: register must be even +amocas.q a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: register must be even +amocas.q.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: register must be even +amocas.q.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: register must be even +amocas.q.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: register must be even +amocas.q.rl a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: register must be even +amocas.q.aqrl a1, a2, (a1) # CHECK: :[[@LINE]]:15: error: register must be even +amocas.q.aqrl a0, a1, (a1) # CHECK: :[[@LINE]]:19: error: register must be even -- GitLab From 6bc7e3764c244b3d6ba2ab861889d80082766017 Mon Sep 17 00:00:00 2001 From: lorenzo chelini Date: Wed, 10 Jan 2024 11:23:02 -0600 Subject: [PATCH 355/652] [MLIR][Tensor] Fix checks for `fold-into-pack-and-unpack.mlir` (#77622) Fix after 113bce0 --- .../Dialect/Tensor/fold-into-pack-and-unpack.mlir | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir b/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir index 6003135b66b1..682107dbebbf 100644 --- a/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir +++ b/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir @@ -469,10 +469,10 @@ func.func @linalg_transpose_tensor_pack_fold_dynamic_outer_dims_tile_dims_tile_s //CHECK-LABEL: func.func @linalg_transpose_tensor_pack_fold_dynamic_outer_dims_tile_dims_tile_sizes( // CHECK-SAME: %[[ARG0:.+]]: tensor, %[[ARG1:.+]]: tensor, // CHECK-SAME: %[[ARG2:.+]]: tensor, %[[ARG3:.+]]: index, %[[ARG4:.+]]: index, %[[ARG5:.+]]: index) -> tensor { -// CHECK: %[[C0:.+]] = arith.constant 0 : index -// CHECK: %[[C1:.+]] = arith.constant 1 : index -// CHECK: %[[C2:.+]] = arith.constant 2 : index -// CHECK: %[[C3:.+]] = arith.constant 3 : index +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[C1:.+]] = arith.constant 1 : index +// CHECK-DAG: %[[C2:.+]] = arith.constant 2 : index +// CHECK-DAG: %[[C3:.+]] = arith.constant 3 : index // CHECK: %[[DIM:.+]] = tensor.dim %[[ARG0]], %[[C0]] : tensor // CHECK: %[[DIM0:.+]] = tensor.dim %[[ARG0]], %[[C1]] : tensor // CHECK: %[[DIM1:.+]] = tensor.dim %[[ARG0]], %[[C2]] : tensor @@ -509,8 +509,8 @@ func.func @linalg_transpose_tensor_pack_multiple_tiles(%arg0: tensor (s0 ceildiv 16)> //CHECK-LABEL: func.func @linalg_transpose_tensor_pack_multiple_tiles( // CHECK-SAME: %[[ARG0:.+]]: tensor) -> tensor<32x?x64x16x2xbf16> { -// CHECK: %[[C0:.+]] = arith.constant 0 : index -// CHECK: %[[CST:.+]] = arith.constant 0.000000e+00 : bf16 +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[CST:.+]] = arith.constant 0.000000e+00 : bf16 // CHECK: %[[DIM:.+]] = tensor.dim %[[ARG0]], %[[C0]] : tensor // CHECK: %[[VAL0:.+]] = affine.apply #[[map:.+]]()[%[[DIM]]] // CHECK: %[[VAL1:.+]] = tensor.empty(%[[VAL0]]) : tensor<32x?x64x16x2xbf16> -- GitLab From 7cc9ae95512edd0b969823fdfa062b92cb3c4d4e Mon Sep 17 00:00:00 2001 From: Okwan Kwon Date: Wed, 10 Jan 2024 09:23:36 -0800 Subject: [PATCH 356/652] [mlir] allow inlining complex ops (#77514) Complex ops are pure ops just like the arithmetic ops so they can be inlined. --- .../lib/Dialect/Complex/IR/ComplexDialect.cpp | 14 +++++++++++++ mlir/test/Transforms/inlining.mlir | 20 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp b/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp index e54b3a71bbc3..ca57171af156 100644 --- a/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp +++ b/mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp @@ -11,6 +11,7 @@ #include "mlir/Dialect/Complex/IR/Complex.h" #include "mlir/IR/Builders.h" #include "mlir/IR/DialectImplementation.h" +#include "mlir/Transforms/InliningUtils.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/TypeSwitch.h" @@ -18,6 +19,18 @@ using namespace mlir; #include "mlir/Dialect/Complex/IR/ComplexOpsDialect.cpp.inc" +namespace { +/// This class defines the interface for handling inlining for complex +/// dialect operations. +struct ComplexInlinerInterface : public DialectInlinerInterface { + using DialectInlinerInterface::DialectInlinerInterface; + /// All complex dialect ops can be inlined. + bool isLegalToInline(Operation *, Region *, bool, IRMapping &) const final { + return true; + } +}; +} // namespace + void complex::ComplexDialect::initialize() { addOperations< #define GET_OP_LIST @@ -28,6 +41,7 @@ void complex::ComplexDialect::initialize() { #include "mlir/Dialect/Complex/IR/ComplexAttributes.cpp.inc" >(); declarePromisedInterface(); + addInterfaces(); } Operation *complex::ComplexDialect::materializeConstant(OpBuilder &builder, diff --git a/mlir/test/Transforms/inlining.mlir b/mlir/test/Transforms/inlining.mlir index 9544f1eb0917..2a08e625ba79 100644 --- a/mlir/test/Transforms/inlining.mlir +++ b/mlir/test/Transforms/inlining.mlir @@ -297,3 +297,23 @@ func.func @inline_convert_and_handle_attr_call(%arg0 : i16) -> (i16) { %res = "test.conversion_call_op"(%arg0) { callee=@handle_attr_callee_fn } : (i16) -> (i16) return %res : i16 } + +// Check a function with complex ops is inlined. +func.func @double_square_complex(%cplx: complex) -> complex { + %double = complex.add %cplx, %cplx : complex + %square = complex.mul %double, %double : complex + return %square : complex +} + +// CHECK-LABEL: func @inline_with_complex_ops +func.func @inline_with_complex_ops() -> complex { + %c1 = arith.constant 1.0 : f32 + %c2 = arith.constant 2.0 : f32 + %c = complex.create %c1, %c2 : complex + + // CHECK: complex.add + // CHECK: complex.mul + // CHECK-NOT: call + %r = call @double_square_complex(%c) : (complex) -> (complex) + return %r : complex +} -- GitLab From 2c60d59864ed8b2b26c4f0683ee7a1816c6d951e Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Thu, 11 Jan 2024 00:37:01 +0700 Subject: [PATCH 357/652] [Flang] Support -mrvv-vector-bits flag (#77588) This patch adds support for the -mrvv-vector-bits flag in the Flang driver, and translates them to -mvscale-min/-mvscale-max. The code was copied from the Clang toolchain (similarly to what was done for AArch64's -msve-vector-bits flag) so it also supports the same -mrvv-vector-bits=zvl mode. Note that Flang doesn't yet define the __riscv_v_fixed_vlen macro, so the help text has been updated to highlight that it's only defined for Clang. --- clang/include/clang/Driver/Options.td | 12 +++-- clang/lib/Driver/ToolChains/Flang.cpp | 51 +++++++++++++++++++++ clang/lib/Driver/ToolChains/Flang.h | 7 +++ flang/test/Driver/driver-help-hidden.f90 | 2 + flang/test/Driver/driver-help.f90 | 2 + flang/test/Driver/riscv-rvv-vector-bits.f90 | 51 +++++++++++++++++++++ 6 files changed, 120 insertions(+), 5 deletions(-) create mode 100644 flang/test/Driver/riscv-rvv-vector-bits.f90 diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index a76e8dcff148..19becba4a5ad 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4585,11 +4585,13 @@ let Flags = [TargetSpecific] in { def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group, HelpText<"Enable use of experimental RISC-V extensions.">; def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group, - HelpText<"Specify the size in bits of an RVV vector register. Defaults to " - "the vector length agnostic value of \"scalable\". Accepts power of " - "2 values between 64 and 65536. Also accepts \"zvl\" " - "to use the value implied by -march/-mcpu. Value will be reflected " - "in __riscv_v_fixed_vlen preprocessor define (RISC-V only)">; + Visibility<[ClangOption, FlangOption]>, + HelpText<"Specify the size in bits of an RVV vector register">, + DocBrief<"Defaults to the vector length agnostic value of \"scalable\". " + "Accepts power of 2 values between 64 and 65536. Also accepts " + "\"zvl\" to use the value implied by -march/-mcpu. On Clang, value " + "will be reflected in __riscv_v_fixed_vlen preprocessor define " + "(RISC-V only)">; def munaligned_access : Flag<["-"], "munaligned-access">, Group, HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch/RISC-V only)">; diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 5d2fc6cb028e..422209e6c261 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "Flang.h" +#include "Arch/RISCV.h" #include "CommonArgs.h" #include "clang/Basic/CodeGenOptions.h" @@ -14,6 +15,8 @@ #include "llvm/Frontend/Debug/Options.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" +#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #include @@ -203,6 +206,51 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, } } +void Flang::AddRISCVTargetArgs(const ArgList &Args, + ArgStringList &CmdArgs) const { + const llvm::Triple &Triple = getToolChain().getTriple(); + // Handle -mrvv-vector-bits= + if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) { + StringRef Val = A->getValue(); + const Driver &D = getToolChain().getDriver(); + + // Get minimum VLen from march. + unsigned MinVLen = 0; + StringRef Arch = riscv::getRISCVArch(Args, Triple); + auto ISAInfo = llvm::RISCVISAInfo::parseArchString( + Arch, /*EnableExperimentalExtensions*/ true); + // Ignore parsing error. + if (!errorToBool(ISAInfo.takeError())) + MinVLen = (*ISAInfo)->getMinVLen(); + + // If the value is "zvl", use MinVLen from march. Otherwise, try to parse + // as integer as long as we have a MinVLen. + unsigned Bits = 0; + if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { + Bits = MinVLen; + } else if (!Val.getAsInteger(10, Bits)) { + // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that + // at least MinVLen. + if (Bits < MinVLen || Bits < llvm::RISCV::RVVBitsPerBlock || + Bits > 65536 || !llvm::isPowerOf2_32(Bits)) + Bits = 0; + } + + // If we got a valid value try to use it. + if (Bits != 0) { + unsigned VScaleMin = Bits / llvm::RISCV::RVVBitsPerBlock; + CmdArgs.push_back( + Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin))); + CmdArgs.push_back( + Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin))); + } else if (!Val.equals("scalable")) { + // Handle the unsupported values passed to mrvv-vector-bits. + D.Diag(diag::err_drv_unsupported_option_argument) + << A->getSpelling() << Val; + } + } +} + static void addVSDefines(const ToolChain &TC, const ArgList &Args, ArgStringList &CmdArgs) { @@ -321,6 +369,9 @@ void Flang::addTargetOptions(const ArgList &Args, AddAMDGPUTargetArgs(Args, CmdArgs); break; case llvm::Triple::riscv64: + getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); + AddRISCVTargetArgs(Args, CmdArgs); + break; case llvm::Triple::x86_64: getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); break; diff --git a/clang/lib/Driver/ToolChains/Flang.h b/clang/lib/Driver/ToolChains/Flang.h index 8d35080e1c0c..ec2e545a1d0b 100644 --- a/clang/lib/Driver/ToolChains/Flang.h +++ b/clang/lib/Driver/ToolChains/Flang.h @@ -70,6 +70,13 @@ private: void AddAMDGPUTargetArgs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const; + /// Add specific options for RISC-V target. + /// + /// \param [in] Args The list of input driver arguments + /// \param [out] CmdArgs The list of output command arguments + void AddRISCVTargetArgs(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const; + /// Extract offload options from the driver arguments and add them to /// the command arguments. /// \param [in] C The current compilation for the driver invocation diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90 index ab39dce962c6..68eafec16f98 100644 --- a/flang/test/Driver/driver-help-hidden.f90 +++ b/flang/test/Driver/driver-help-hidden.f90 @@ -122,6 +122,8 @@ ! CHECK-NEXT: -mllvm Additional arguments to forward to LLVM's option processing ! CHECK-NEXT: -mmlir Additional arguments to forward to MLIR's option processing ! CHECK-NEXT: -module-dir

Put MODULE files in +! CHECK-NEXT: -mrvv-vector-bits= +! CHECK-NEXT: Specify the size in bits of an RVV vector register ! CHECK-NEXT: -msve-vector-bits= ! CHECK-NEXT: Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only) ! CHECK-NEXT: --no-offload-arch= diff --git a/flang/test/Driver/driver-help.f90 b/flang/test/Driver/driver-help.f90 index c1ec2a028d4b..62e56a8c80f1 100644 --- a/flang/test/Driver/driver-help.f90 +++ b/flang/test/Driver/driver-help.f90 @@ -108,6 +108,8 @@ ! HELP-NEXT: -mllvm Additional arguments to forward to LLVM's option processing ! HELP-NEXT: -mmlir Additional arguments to forward to MLIR's option processing ! HELP-NEXT: -module-dir Put MODULE files in +! HELP-NEXT: -mrvv-vector-bits= +! HELP-NEXT: Specify the size in bits of an RVV vector register ! HELP-NEXT: -msve-vector-bits= ! HELP-NEXT: Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only) ! HELP-NEXT: --no-offload-arch= diff --git a/flang/test/Driver/riscv-rvv-vector-bits.f90 b/flang/test/Driver/riscv-rvv-vector-bits.f90 new file mode 100644 index 000000000000..f57b67258919 --- /dev/null +++ b/flang/test/Driver/riscv-rvv-vector-bits.f90 @@ -0,0 +1,51 @@ +! ----------------------------------------------------------------------------- +! Tests for the -mrvv-vector-bits flag (taken from the clang test) +! ----------------------------------------------------------------------------- + +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=128 2>&1 | FileCheck --check-prefix=CHECK-128 %s +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=256 2>&1 | FileCheck --check-prefix=CHECK-256 %s +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=512 2>&1 | FileCheck --check-prefix=CHECK-512 %s +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=1024 2>&1 | FileCheck --check-prefix=CHECK-1024 %s +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=2048 2>&1 | FileCheck --check-prefix=CHECK-2048 %s +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=scalable 2>&1 | FileCheck --check-prefix=CHECK-SCALABLE %s + +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gcv_zvl256b \ +! RUN: -mrvv-vector-bits=zvl 2>&1 | FileCheck --check-prefix=CHECK-256 %s +! RUN: %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gcv_zvl512b \ +! RUN: -mrvv-vector-bits=zvl 2>&1 | FileCheck --check-prefix=CHECK-512 %s + +! CHECK-128: "-fc1" +! CHECK-128-SAME: "-mvscale-max=2" "-mvscale-min=2" +! CHECK-256: "-fc1" +! CHECK-256-SAME: "-mvscale-max=4" "-mvscale-min=4" +! CHECK-512: "-fc1" +! CHECK-512-SAME: "-mvscale-max=8" "-mvscale-min=8" +! CHECK-1024: "-fc1" +! CHECK-1024-SAME: "-mvscale-max=16" "-mvscale-min=16" +! CHECK-2048: "-fc1" +! CHECK-2048-SAME: "-mvscale-max=32" "-mvscale-min=32" + +! CHECK-SCALABLE-NOT: "-mvscale-min= +! CHECK-SCALABLE-NOT: "-mvscale-max= + +! Error out if an unsupported value is passed to -mrvv-vector-bits. +! ----------------------------------------------------------------------------- +! RUN: not %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=16 2>&1 | FileCheck --check-prefix=CHECK-BAD-VALUE-ERROR %s +! RUN: not %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=A 2>&1 | FileCheck --check-prefix=CHECK-BAD-VALUE-ERROR %s +! RUN: not %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc_zve64x \ +! RUN: -mrvv-vector-bits=131072 2>&1 | FileCheck --check-prefix=CHECK-BAD-VALUE-ERROR %s +! RUN: not %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gc \ +! RUN: -mrvv-vector-bits=zvl 2>&1 | FileCheck --check-prefix=CHECK-BAD-VALUE-ERROR %s +! RUN: not %flang -c %s -### --target=riscv64-linux-gnu -march=rv64gcv \ +! RUN: -mrvv-vector-bits=64 2>&1 | FileCheck --check-prefix=CHECK-BAD-VALUE-ERROR %s +! +! CHECK-BAD-VALUE-ERROR: error: unsupported argument '{{.*}}' to option '-mrvv-vector-bits=' + -- GitLab From e203968e411bba6395133d93881eb32e7895e50b Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Jan 2024 11:42:04 -0600 Subject: [PATCH 358/652] [Libomptarget] Do not abort on failed plugin init (#77623) Summary: The current code logic is supposed to skip plugins that aren't found or could not be loaded. However, the plugic ontained a call to `abort` if it failed, which prevented us from continuing if initilalization the plugin failed (such as if `dlopen` failed for the dyanmic plugins). --- .../plugins-nextgen/common/src/PluginInterface.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp index 0db7910ec105..1bd70b85da34 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp @@ -1662,8 +1662,8 @@ extern "C" { int32_t __tgt_rtl_init_plugin() { auto Err = Plugin::initIfNeeded(); if (Err) { - REPORT("Failure to initialize plugin " GETNAME(TARGET_NAME) ": %s\n", - toString(std::move(Err)).data()); + [[maybe_unused]] std::string ErrStr = toString(std::move(Err)); + DP("Failed to init plugin: %s", ErrStr.c_str()); return OFFLOAD_FAIL; } -- GitLab From 6a075a9d5dda8f6ce37b176c6d4a7f87a770ec31 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 10 Jan 2024 23:19:09 +0530 Subject: [PATCH 359/652] [MLIR][NVVM]: Update setmaxregister NVVM Op (#77594) This patch updates the setmaxregister NVVM Op to use the intrinsics instead of inline-ptx. * The interface remains same (as expected). * Tests are added to verify the lowered intrinsics in Target/LLVMIR/nvvmir.mlir. Signed-off-by: Durgadoss R --- mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 16 ++++++++-------- .../test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir | 5 +++-- mlir/test/Target/LLVMIR/nvvmir.mlir | 9 +++++++++ 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td index 3a6c6e5438c6..1941c4dece1b 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td @@ -463,17 +463,17 @@ def SetMaxRegisterAction : I32EnumAttr<"SetMaxRegisterAction", "NVVM set max reg } def SetMaxRegisterActionAttr : EnumAttr; -def NVVM_SetMaxRegisterOp : NVVM_PTXBuilder_Op<"setmaxregister"> { +def NVVM_SetMaxRegisterOp : NVVM_Op<"setmaxregister"> { let arguments = (ins I32Attr:$regCount, SetMaxRegisterActionAttr:$action); let assemblyFormat = "$action $regCount attr-dict"; - let extraClassDefinition = [{ - std::string $cppClass::getPtx() { - if(getAction() == NVVM::SetMaxRegisterAction::increase) - return std::string("setmaxnreg.inc.sync.aligned.u32 %0;"); - return std::string("setmaxnreg.dec.sync.aligned.u32 %0;"); - } - }]; let hasVerifier = 1; + string llvmBuilder = [{ + auto intId = (op.getAction() == NVVM::SetMaxRegisterAction::increase) ? + llvm::Intrinsic::nvvm_setmaxnreg_inc_sync_aligned_u32 : + llvm::Intrinsic::nvvm_setmaxnreg_dec_sync_aligned_u32; + + createIntrinsicCall(builder, intId, builder.getInt32($regCount)); + }]; } def NVVM_FenceMbarrierInitOp : NVVM_PTXBuilder_Op<"fence.mbarrier.init"> { diff --git a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir index 7e08ec6ffcbd..2ee92e3d9527 100644 --- a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir +++ b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir @@ -628,9 +628,10 @@ llvm.func @init_mbarrier_arrive_expect_tx(%desc : !llvm.ptr, %pred : i1) { // ----- func.func @set_max_register() { - //CHECK: llvm.inline_asm has_side_effects asm_dialect = att "setmaxnreg.inc.sync.aligned.u32 $0;", "n" + // CHECK: nvvm.setmaxregister increase 232 nvvm.setmaxregister increase 232 - //CHECK: llvm.inline_asm has_side_effects asm_dialect = att "setmaxnreg.dec.sync.aligned.u32 $0;", "n" + + // CHECK: nvvm.setmaxregister decrease 40 nvvm.setmaxregister decrease 40 func.return } diff --git a/mlir/test/Target/LLVMIR/nvvmir.mlir b/mlir/test/Target/LLVMIR/nvvmir.mlir index f83be9dbb2ff..423b1a133a4a 100644 --- a/mlir/test/Target/LLVMIR/nvvmir.mlir +++ b/mlir/test/Target/LLVMIR/nvvmir.mlir @@ -369,6 +369,15 @@ llvm.func @cp_async_mbarrier_arrive(%bar_shared: !llvm.ptr<3>, %bar_gen: !llvm.p llvm.return } +// CHECK-LABEL: @llvm_nvvm_setmaxregister +llvm.func @llvm_nvvm_setmaxregister() { + // CHECK-LLVM: call void @llvm.nvvm.setmaxnreg.inc.sync.aligned.u32(i32 256) + nvvm.setmaxregister increase 256 + // CHECK-LLVM: call void @llvm.nvvm.setmaxnreg.dec.sync.aligned.u32(i32 24) + nvvm.setmaxregister decrease 24 + llvm.return +} + // CHECK-LABEL: @ld_matrix llvm.func @ld_matrix(%arg0: !llvm.ptr<3>) { // CHECK: call i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3(ptr addrspace(3) %{{.*}}) -- GitLab From f502b981b471c04bef1b2a6c581c02b59f931163 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 10 Jan 2024 13:02:50 -0500 Subject: [PATCH 360/652] [libc++][NFC] Add comment in test to explain the presence of some assertions --- .../ranges/range.utility.helpers/simple_view.compile.pass.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp b/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp index a58f74c3b591..440b12e2c71c 100644 --- a/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp +++ b/libcxx/test/libcxx/ranges/range.utility.helpers/simple_view.compile.pass.cpp @@ -50,6 +50,7 @@ static_assert(!std::ranges::__simple_view); static_assert( std::ranges::__simple_view); static_assert(!std::ranges::__simple_view); +// To make sure __simple_view and the test version of the concept stay in sync. static_assert(simple_view); static_assert(!simple_view); static_assert(!simple_view); -- GitLab From cd7eaaa6db0dc9a00a097ba8e6ebad6fb2dec56a Mon Sep 17 00:00:00 2001 From: Pete Lawrence Date: Wed, 10 Jan 2024 08:13:14 -1000 Subject: [PATCH 361/652] [lldb] Add color support to StreamString (#77380) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change just adds a `bool colors` parameter to the `StreamString` class's constructor, which it passes up to its superclass’s constructor. I'm working on another patch that prints out error messages using a `StreamString` but I wasn't getting colorized text because of this missing implementation detail. rdar://120671168 --- lldb/include/lldb/Utility/StreamString.h | 2 +- lldb/source/Utility/StreamString.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lldb/include/lldb/Utility/StreamString.h b/lldb/include/lldb/Utility/StreamString.h index 4c568acdcc6f..3d675caf8f3f 100644 --- a/lldb/include/lldb/Utility/StreamString.h +++ b/lldb/include/lldb/Utility/StreamString.h @@ -22,7 +22,7 @@ namespace lldb_private { class StreamString : public Stream { public: - StreamString(); + StreamString(bool colors = false); StreamString(uint32_t flags, uint32_t addr_size, lldb::ByteOrder byte_order); diff --git a/lldb/source/Utility/StreamString.cpp b/lldb/source/Utility/StreamString.cpp index 745a85b75765..0d35ccbdbbd0 100644 --- a/lldb/source/Utility/StreamString.cpp +++ b/lldb/source/Utility/StreamString.cpp @@ -11,7 +11,7 @@ using namespace lldb; using namespace lldb_private; -StreamString::StreamString() : Stream(0, 4, eByteOrderBig) {} +StreamString::StreamString(bool colors) : Stream(0, 4, eByteOrderBig, colors) {} StreamString::StreamString(uint32_t flags, uint32_t addr_size, ByteOrder byte_order) -- GitLab From 1c209322e462c1d1675cc4b9947712dcceac93b5 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Thu, 11 Jan 2024 01:22:41 +0700 Subject: [PATCH 362/652] [ADT] Make StringRef std::string_view conversion operator constexpr. NFC (#77506) This would allow us to compare StringRefs via std::string_view, avoiding having to make the existing StringRef compare machinery constexpr for now. --- llvm/include/llvm/ADT/StringRef.h | 4 ++-- llvm/unittests/ADT/StringRefTest.cpp | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/ADT/StringRef.h b/llvm/include/llvm/ADT/StringRef.h index d892333de391..1c6c96678b5d 100644 --- a/llvm/include/llvm/ADT/StringRef.h +++ b/llvm/include/llvm/ADT/StringRef.h @@ -128,7 +128,7 @@ namespace llvm { /// data - Get a pointer to the start of the string (which may not be null /// terminated). - [[nodiscard]] const char *data() const { return Data; } + [[nodiscard]] constexpr const char *data() const { return Data; } /// empty - Check if the string is empty. [[nodiscard]] constexpr bool empty() const { return Length == 0; } @@ -245,7 +245,7 @@ namespace llvm { /// @name Type Conversions /// @{ - operator std::string_view() const { + constexpr operator std::string_view() const { return std::string_view(data(), size()); } diff --git a/llvm/unittests/ADT/StringRefTest.cpp b/llvm/unittests/ADT/StringRefTest.cpp index a208527b6c80..8df71e8ad033 100644 --- a/llvm/unittests/ADT/StringRefTest.cpp +++ b/llvm/unittests/ADT/StringRefTest.cpp @@ -59,6 +59,7 @@ TEST(StringRefTest, Construction) { TEST(StringRefTest, Conversion) { EXPECT_EQ("hello", std::string(StringRef("hello"))); EXPECT_EQ("hello", std::string_view(StringRef("hello"))); + static_assert(std::string_view(StringRef("hello")) == "hello"); } TEST(StringRefTest, EmptyInitializerList) { @@ -78,9 +79,22 @@ TEST(StringRefTest, Iteration) { TEST(StringRefTest, StringOps) { const char *p = "hello"; + EXPECT_EQ(p, StringRef(p, 0).data()); + static_assert(StringRef("hello").data()[0] == 'h'); + static_assert(StringRef("hello").data()[1] == 'e'); + static_assert(StringRef("hello").data()[2] == 'l'); + static_assert(StringRef("hello").data()[3] == 'l'); + static_assert(StringRef("hello").data()[4] == 'o'); + static_assert(StringRef("hello").data()[5] == '\0'); + EXPECT_TRUE(StringRef().empty()); + static_assert(StringRef("").empty()); + static_assert(!StringRef("hello").empty()); + EXPECT_EQ((size_t) 5, StringRef("hello").size()); + static_assert(StringRef("hello").size() == 5); + EXPECT_GT( 0, StringRef("aab").compare("aad")); EXPECT_EQ( 0, StringRef("aab").compare("aab")); EXPECT_LT( 0, StringRef("aab").compare("aaa")); -- GitLab From cac6b1a5420d76f4635696372849dbbf07a77376 Mon Sep 17 00:00:00 2001 From: Erich Keane Date: Wed, 10 Jan 2024 10:26:49 -0800 Subject: [PATCH 363/652] [OpenACC] Implement 'var' parsing correctly, support array sections (#77617) While investigating implementing 'var-list' generically for the variety of clauses that support this syntax (an extensive list!) I discovered that it includes 'compound types' and members of compound types, as well as array sections. This patch genericizes that function, and implements it in terms of an assignment expression, and enables a simplified version of OMP Array Sections for it. OpenACC only supports a startidx + length, so this patch implements that parsing. However, it is currently still being represented as an OpenMP Array Section, which is semantically very similar. It is my intent to come back and genericize the OMP Array Sections types (or create a similar expression node) in the future when dealing with Sema. At the moment, the only obvious problem with it is that the diagnostic for using it in the 'wrong' place says OpenMP instead of OpenACC, which I intend to fix when I deal with the AST node changes. --- clang/include/clang/Parse/Parser.h | 24 ++++++- clang/lib/AST/ASTContext.cpp | 7 ++ clang/lib/Parse/ParseExpr.cpp | 26 ++++++-- clang/lib/Parse/ParseOpenACC.cpp | 65 ++++++------------- .../ParserOpenACC/parse-cache-construct.c | 40 ++++++++---- .../ParserOpenACC/parse-cache-construct.cpp | 65 +++++++++++++++++++ 6 files changed, 166 insertions(+), 61 deletions(-) diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index 2dbe090bd093..186dbb770858 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -234,6 +234,26 @@ class Parser : public CodeCompletionHandler { /// Parsing OpenACC directive mode. bool OpenACCDirectiveParsing = false; + /// Currently parsing a situation where an OpenACC array section could be + /// legal, such as a 'var-list'. + bool AllowOpenACCArraySections = false; + + /// RAII object to set reset OpenACC parsing a context where Array Sections + /// are allowed. + class OpenACCArraySectionRAII { + Parser &P; + + public: + OpenACCArraySectionRAII(Parser &P) : P(P) { + assert(!P.AllowOpenACCArraySections); + P.AllowOpenACCArraySections = true; + } + ~OpenACCArraySectionRAII() { + assert(P.AllowOpenACCArraySections); + P.AllowOpenACCArraySections = false; + } + }; + /// When true, we are directly inside an Objective-C message /// send expression. /// @@ -3546,8 +3566,8 @@ private: ExprResult ParseOpenACCIDExpression(); /// Parses the variable list for the `cache` construct. void ParseOpenACCCacheVarList(); - /// Parses a single variable in a variable list for the 'cache' construct. - bool ParseOpenACCCacheVar(); + /// Parses a single variable in a variable list for OpenACC. + bool ParseOpenACCVar(); bool ParseOpenACCWaitArgument(); private: diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index b60dcfaabfd1..d9cefcaa84d7 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -1318,6 +1318,13 @@ void ASTContext::InitBuiltinTypes(const TargetInfo &Target, InitBuiltinType(OMPArrayShapingTy, BuiltinType::OMPArrayShaping); InitBuiltinType(OMPIteratorTy, BuiltinType::OMPIterator); } + // Placeholder type for OpenACC array sections. + if (LangOpts.OpenACC) { + // FIXME: Once we implement OpenACC array sections in Sema, this will either + // be combined with the OpenMP type, or given its own type. In the meantime, + // just use the OpenMP type so that parsing can work. + InitBuiltinType(OMPArraySectionTy, BuiltinType::OMPArraySection); + } if (LangOpts.MatrixTypes) InitBuiltinType(IncompleteMatrixIdxTy, BuiltinType::IncompleteMatrixIdx); diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index 897810557976..dcfd290d39cc 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -1974,10 +1974,11 @@ Parser::ParsePostfixExpressionSuffix(ExprResult LHS) { PreferredType.enterSubscript(Actions, Tok.getLocation(), LHS.get()); // We try to parse a list of indexes in all language mode first - // and, in we find 0 or one index, we try to parse an OpenMP array + // and, in we find 0 or one index, we try to parse an OpenMP/OpenACC array // section. This allow us to support C++23 multi dimensional subscript and - // OpenMp sections in the same language mode. - if (!getLangOpts().OpenMP || Tok.isNot(tok::colon)) { + // OpenMP/OpenACC sections in the same language mode. + if ((!getLangOpts().OpenMP && !AllowOpenACCArraySections) || + Tok.isNot(tok::colon)) { if (!getLangOpts().CPlusPlus23) { ExprResult Idx; if (getLangOpts().CPlusPlus11 && Tok.is(tok::l_brace)) { @@ -2001,7 +2002,18 @@ Parser::ParsePostfixExpressionSuffix(ExprResult LHS) { } } - if (ArgExprs.size() <= 1 && getLangOpts().OpenMP) { + // Handle OpenACC first, since 'AllowOpenACCArraySections' is only enabled + // when actively parsing a 'var' in a 'var-list' during clause/'cache' + // parsing, so it is the most specific, and best allows us to handle + // OpenACC and OpenMP at the same time. + if (ArgExprs.size() <= 1 && AllowOpenACCArraySections) { + ColonProtectionRAIIObject RAII(*this); + if (Tok.is(tok::colon)) { + // Consume ':' + ColonLocFirst = ConsumeToken(); + Length = Actions.CorrectDelayedTyposInExpr(ParseExpression()); + } + } else if (ArgExprs.size() <= 1 && getLangOpts().OpenMP) { ColonProtectionRAIIObject RAII(*this); if (Tok.is(tok::colon)) { // Consume ':' @@ -2031,6 +2043,12 @@ Parser::ParsePostfixExpressionSuffix(ExprResult LHS) { if (!LHS.isInvalid() && !HasError && !Length.isInvalid() && !Stride.isInvalid() && Tok.is(tok::r_square)) { if (ColonLocFirst.isValid() || ColonLocSecond.isValid()) { + // FIXME: OpenACC hasn't implemented Sema/Array section handling at a + // semantic level yet. For now, just reuse the OpenMP implementation + // as it gets the parsing/type management mostly right, and we can + // replace this call to ActOnOpenACCArraySectionExpr in the future. + // Eventually we'll genericize the OPenMPArraySectionExpr type as + // well. LHS = Actions.ActOnOMPArraySectionExpr( LHS.get(), Loc, ArgExprs.empty() ? nullptr : ArgExprs[0], ColonLocFirst, ColonLocSecond, Length.get(), Stride.get(), RLoc); diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index c9224d3ae910..fc82324e235d 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -554,49 +554,17 @@ ExprResult Parser::ParseOpenACCIDExpression() { return getActions().CorrectDelayedTyposInExpr(Res); } -/// OpenACC 3.3, section 2.10: -/// A 'var' in a cache directive must be a single array element or a simple -/// subarray. In C and C++, a simple subarray is an array name followed by an -/// extended array range specification in brackets, with a start and length such -/// as: -/// -/// arr[lower:length] -/// -bool Parser::ParseOpenACCCacheVar() { - ExprResult ArrayName = ParseOpenACCIDExpression(); - if (ArrayName.isInvalid()) - return true; - - // If the expression is invalid, just continue parsing the brackets, there - // is likely other useful diagnostics we can emit inside of those. - - BalancedDelimiterTracker SquareBrackets(*this, tok::l_square, - tok::annot_pragma_openacc_end); - - // Square brackets are required, so error here, and try to recover by moving - // until the next comma, or the close paren/end of pragma. - if (SquareBrackets.expectAndConsume()) { - SkipUntil(tok::comma, tok::r_paren, tok::annot_pragma_openacc_end, - Parser::StopBeforeMatch); - return true; - } - - ExprResult Lower = getActions().CorrectDelayedTyposInExpr(ParseExpression()); - if (Lower.isInvalid()) - return true; - - // The 'length' expression is optional, as this could be a single array - // element. If there is no colon, we can treat it as that. - if (getCurToken().is(tok::colon)) { - ConsumeToken(); - ExprResult Length = - getActions().CorrectDelayedTyposInExpr(ParseExpression()); - if (Length.isInvalid()) - return true; - } - - // Diagnose the square bracket being in the wrong place and continue. - return SquareBrackets.consumeClose(); +/// OpenACC 3.3, section 1.6: +/// In this spec, a 'var' (in italics) is one of the following: +/// - a variable name (a scalar, array, or compisite variable name) +/// - a subarray specification with subscript ranges +/// - an array element +/// - a member of a composite variable +/// - a common block name between slashes (fortran only) +bool Parser::ParseOpenACCVar() { + OpenACCArraySectionRAII ArraySections(*this); + ExprResult Res = ParseAssignmentExpression(); + return Res.isInvalid(); } /// OpenACC 3.3, section 2.10: @@ -627,7 +595,16 @@ void Parser::ParseOpenACCCacheVarList() { if (!FirstArray) ExpectAndConsume(tok::comma); FirstArray = false; - if (ParseOpenACCCacheVar()) + + // OpenACC 3.3, section 2.10: + // A 'var' in a cache directive must be a single array element or a simple + // subarray. In C and C++, a simple subarray is an array name followed by + // an extended array range specification in brackets, with a start and + // length such as: + // + // arr[lower:length] + // + if (ParseOpenACCVar()) SkipUntil(tok::r_paren, tok::annot_pragma_openacc_end, tok::comma, StopBeforeMatch); } diff --git a/clang/test/ParserOpenACC/parse-cache-construct.c b/clang/test/ParserOpenACC/parse-cache-construct.c index 560f45423bc2..d54632fc8f46 100644 --- a/clang/test/ParserOpenACC/parse-cache-construct.c +++ b/clang/test/ParserOpenACC/parse-cache-construct.c @@ -1,10 +1,15 @@ // RUN: %clang_cc1 %s -verify -fopenacc +struct S { + int foo; + char Array[1]; +}; char *getArrayPtr(); void func() { char Array[10]; char *ArrayPtr = getArrayPtr(); int *readonly; + struct S s; for (int i = 0; i < 10; ++i) { // expected-error@+2{{expected '('}} @@ -46,7 +51,6 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+4{{expected '['}} // expected-error@+3{{expected ')'}} // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} @@ -60,13 +64,14 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+2{{expected '['}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc cache(ArrayPtr) } for (int i = 0; i < 10; ++i) { - // expected-error@+4{{expected expression}} + // expected-error@+6{{expected expression}} + // expected-error@+5{{expected ']'}} + // expected-note@+4{{to match this '['}} // expected-error@+3{{expected ')'}} // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} @@ -74,13 +79,17 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+2{{expected expression}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ']'}} + // expected-note@+2{{to match this '['}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc cache(ArrayPtr[, 5) } for (int i = 0; i < 10; ++i) { - // expected-error@+2{{expected expression}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ']'}} + // expected-note@+2{{to match this '['}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc cache(Array[) } @@ -91,7 +100,9 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+4{{expected expression}} + // expected-error@+6{{expected expression}} + // expected-error@+5{{expected ']'}} + // expected-note@+4{{to match this '['}} // expected-error@+3{{expected ')'}} // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} @@ -99,13 +110,11 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+2{{expected '['}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc cache(readonly) } for (int i = 0; i < 10; ++i) { - // expected-error@+2{{expected '['}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc cache(readonly:ArrayPtr) } @@ -122,7 +131,6 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+2{{expected '['}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc cache(readonly:ArrayPtr[5:*readonly], Array) } @@ -138,7 +146,7 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+4{{expected identifier}} + // expected-error@+4{{expected expression}} // expected-error@+3{{expected ')'}} // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} @@ -146,7 +154,7 @@ void func() { } for (int i = 0; i < 10; ++i) { - // expected-error@+2{{expected identifier}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc cache(readonly:ArrayPtr[5:*readonly],) } @@ -163,4 +171,14 @@ void func() { #pragma acc cache(readonly:ArrayPtr[5:3, *readonly], ArrayPtr[0]) } + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:s.foo) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+2{{left operand of comma operator has no effect}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:s.Array[1,2]) + } } diff --git a/clang/test/ParserOpenACC/parse-cache-construct.cpp b/clang/test/ParserOpenACC/parse-cache-construct.cpp index 3b2230cabae3..affe43d4b0f0 100644 --- a/clang/test/ParserOpenACC/parse-cache-construct.cpp +++ b/clang/test/ParserOpenACC/parse-cache-construct.cpp @@ -46,6 +46,71 @@ struct S { static constexpr char array[] ={1,2,3,4,5}; }; +struct Members { + int value = 5; + char array[5] ={1,2,3,4,5}; +}; +struct HasMembersArray { + Members MemArr[4]; +}; + + void use() { + + Members s; + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(s.array[s.value]) + } + HasMembersArray Arrs; + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[3].array[4]) + } + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[3].array[1:4]) + } + for (int i = 0; i < 10; ++i) { + // FIXME: Once we have a new array-section type to represent OpenACC as + // well, change this error message. + // expected-error@+2{{OpenMP array section is not allowed here}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[3:4].array[1:4]) + } + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{OpenMP array section is not allowed here}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[3:4].array[4]) + } + for (int i = 0; i < 10; ++i) { + // expected-error@+3{{expected ']'}} + // expected-note@+2{{to match this '['}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[3:4:].array[4]) + } + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[:].array[4]) + } + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected unqualified-id}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[::].array[4]) + } + for (int i = 0; i < 10; ++i) { + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ']'}} + // expected-note@+2{{to match this '['}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[: :].array[4]) + } + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Arrs.MemArr[3:].array[4]) + } func(); } + -- GitLab From 761b9d9e4631aa85f932e5ee33aae1f7b8a0538e Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 10 Jan 2024 13:34:03 -0500 Subject: [PATCH 364/652] [libc++] Remove _LIBCPP_C_HAS_NO_GETS (#77346) Since we use _LIBCPP_USING_IF_EXISTS to handle missing C library functions now, _LIBCPP_C_HAS_NO_GETS shouldn't be necessary anymore. See the discussion thread in #77242 for more details. --- libcxx/include/__config | 5 ----- libcxx/include/cstdio | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/libcxx/include/__config b/libcxx/include/__config index 082c73e672c7..1958d5c50ca9 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -1133,11 +1133,6 @@ __sanitizer_verify_double_ended_contiguous_container(const void*, const void*, c # define _LIBCPP_HAS_TRIVIAL_CONDVAR_DESTRUCTION # endif -// Some systems do not provide gets() in their C library, for security reasons. -# if defined(_LIBCPP_MSVCRT) || (defined(__FreeBSD_version) && __FreeBSD_version >= 1300043) || defined(__OpenBSD__) -# define _LIBCPP_C_HAS_NO_GETS -# endif - # if defined(__BIONIC__) || defined(__NuttX__) || defined(__Fuchsia__) || defined(__wasi__) || \ defined(_LIBCPP_HAS_MUSL_LIBC) || defined(__OpenBSD__) # define _LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE diff --git a/libcxx/include/cstdio b/libcxx/include/cstdio index b1b0ff8d3503..0a867cec1a38 100644 --- a/libcxx/include/cstdio +++ b/libcxx/include/cstdio @@ -159,7 +159,7 @@ using ::tmpfile _LIBCPP_USING_IF_EXISTS; using ::tmpnam _LIBCPP_USING_IF_EXISTS; using ::getchar _LIBCPP_USING_IF_EXISTS; -#if _LIBCPP_STD_VER <= 11 && !defined(_LIBCPP_C_HAS_NO_GETS) +#if _LIBCPP_STD_VER <= 11 using ::gets _LIBCPP_USING_IF_EXISTS; #endif using ::scanf _LIBCPP_USING_IF_EXISTS; -- GitLab From 04f77a1320e14560543e3b876f11804fa50a45ff Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 10 Jan 2024 09:57:19 -0800 Subject: [PATCH 365/652] [SLP][NFC]Replace constant by some meaningfull values to make test more relevant, NFC. --- .../X86/int-bitcast-minbitwidth.ll | 35 ++++++++++++------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll index a2bebef8af87..fa0a3610cc22 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll @@ -1,24 +1,35 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-3 < %s | FileCheck %s -define void @t() { -; CHECK-LABEL: define void @t() { +define void @t(i64 %v) { +; CHECK-LABEL: define void @t( +; CHECK-SAME: i64 [[V:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = or i32 0, 0 +; CHECK-NEXT: [[CONV12_1_I:%.*]] = trunc i64 [[V]] to i32 +; CHECK-NEXT: [[MUL_I_1_I:%.*]] = mul i32 [[CONV12_1_I]], 2 +; CHECK-NEXT: [[CONV12_I:%.*]] = trunc i64 [[V]] to i32 +; CHECK-NEXT: [[MUL_I_I:%.*]] = mul i32 [[CONV12_I]], 3 +; CHECK-NEXT: [[CONV14104_I:%.*]] = or i32 [[MUL_I_1_I]], [[MUL_I_I]] +; CHECK-NEXT: [[CONV12_1_I_1:%.*]] = trunc i64 [[V]] to i32 +; CHECK-NEXT: [[MUL_I_1_I_1:%.*]] = mul i32 [[CONV12_1_I_1]], 6 +; CHECK-NEXT: [[CONV12_I_1:%.*]] = trunc i64 [[V]] to i32 +; CHECK-NEXT: [[MUL_I_I_1:%.*]] = mul i32 [[CONV12_I_1]], 5 +; CHECK-NEXT: [[CONV14104_I_1:%.*]] = or i32 [[MUL_I_1_I_1]], [[MUL_I_I_1]] +; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[CONV14104_I]], [[CONV14104_I_1]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 65535 ; CHECK-NEXT: store i32 [[TMP1]], ptr null, align 4 ; CHECK-NEXT: ret void ; entry: - %conv12.1.i = trunc i64 0 to i32 - %mul.i.1.i = mul i32 %conv12.1.i, 0 - %conv12.i = trunc i64 0 to i32 - %mul.i.i = mul i32 %conv12.i, 0 + %conv12.1.i = trunc i64 %v to i32 + %mul.i.1.i = mul i32 %conv12.1.i, 2 + %conv12.i = trunc i64 %v to i32 + %mul.i.i = mul i32 %conv12.i, 3 %conv14104.i = or i32 %mul.i.1.i, %mul.i.i - %conv12.1.i.1 = trunc i64 0 to i32 - %mul.i.1.i.1 = mul i32 %conv12.1.i.1, 0 - %conv12.i.1 = trunc i64 0 to i32 - %mul.i.i.1 = mul i32 %conv12.i.1, 0 + %conv12.1.i.1 = trunc i64 %v to i32 + %mul.i.1.i.1 = mul i32 %conv12.1.i.1, 6 + %conv12.i.1 = trunc i64 %v to i32 + %mul.i.i.1 = mul i32 %conv12.i.1, 5 %conv14104.i.1 = or i32 %mul.i.1.i.1, %mul.i.i.1 %0 = or i32 %conv14104.i, %conv14104.i.1 %1 = and i32 %0, 65535 -- GitLab From 004ec8ea1e9bd775246dba4eb93c1025bedaa5bd Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Wed, 10 Jan 2024 10:39:33 -0800 Subject: [PATCH 366/652] [ci] Set timeout for individual tests and report slowest tests (#76300) There are builds like https://buildkite.com/llvm-project/github-pull-requests/builds/24894 It looks like a deadlock in a test, but we can't see which one. `--timeout=` will make lit kill and report such tests. `--time-tests` produces nice report about slowest test, so we can tune them over time. The same build as above with new flags https://buildkite.com/llvm-project/github-pull-requests/builds/24961 --- .ci/monolithic-linux.sh | 2 +- .ci/monolithic-windows.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.ci/monolithic-linux.sh b/.ci/monolithic-linux.sh index f0577d1069d5..1e7b2d2a36c2 100755 --- a/.ci/monolithic-linux.sh +++ b/.ci/monolithic-linux.sh @@ -45,7 +45,7 @@ cmake -S ${MONOREPO_ROOT}/llvm -B ${BUILD_DIR} \ -D LLVM_ENABLE_ASSERTIONS=ON \ -D LLVM_BUILD_EXAMPLES=ON \ -D COMPILER_RT_BUILD_LIBFUZZER=OFF \ - -D LLVM_LIT_ARGS="-v --xunit-xml-output ${BUILD_DIR}/test-results.xml" \ + -D LLVM_LIT_ARGS="-v --xunit-xml-output ${BUILD_DIR}/test-results.xml --timeout=1200 --time-tests" \ -D LLVM_ENABLE_LLD=ON \ -D CMAKE_CXX_FLAGS=-gmlt \ -D BOLT_CLANG_EXE=/usr/bin/clang \ diff --git a/.ci/monolithic-windows.sh b/.ci/monolithic-windows.sh index 7ac806a0b399..a704e855f011 100755 --- a/.ci/monolithic-windows.sh +++ b/.ci/monolithic-windows.sh @@ -45,7 +45,7 @@ cmake -S ${MONOREPO_ROOT}/llvm -B ${BUILD_DIR} \ -D LLVM_ENABLE_ASSERTIONS=ON \ -D LLVM_BUILD_EXAMPLES=ON \ -D COMPILER_RT_BUILD_LIBFUZZER=OFF \ - -D LLVM_LIT_ARGS="-v --xunit-xml-output ${BUILD_DIR}/test-results.xml" \ + -D LLVM_LIT_ARGS="-v --xunit-xml-output ${BUILD_DIR}/test-results.xml --timeout=1200 --time-tests" \ -D COMPILER_RT_BUILD_ORC=OFF \ -D CMAKE_C_COMPILER_LAUNCHER=sccache \ -D CMAKE_CXX_COMPILER_LAUNCHER=sccache \ -- GitLab From f1e4142f930a4c9d301061a1c31c9a8853f28d83 Mon Sep 17 00:00:00 2001 From: David CARLIER Date: Wed, 10 Jan 2024 18:40:03 +0000 Subject: [PATCH 367/652] [compiler-rt][profile] remove unneeded freebsd hack. (#77209) --- compiler-rt/lib/profile/InstrProfilingPlatformLinux.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/compiler-rt/lib/profile/InstrProfilingPlatformLinux.c b/compiler-rt/lib/profile/InstrProfilingPlatformLinux.c index d0c42462e5e3..19266ab6c6fb 100644 --- a/compiler-rt/lib/profile/InstrProfilingPlatformLinux.c +++ b/compiler-rt/lib/profile/InstrProfilingPlatformLinux.c @@ -20,15 +20,6 @@ #include "InstrProfiling.h" #include "InstrProfilingInternal.h" -#if defined(__FreeBSD__) && !defined(ElfW) -/* - * FreeBSD's elf.h and link.h headers do not define the ElfW(type) macro yet. - * If this is added to all supported FreeBSD versions in the future, this - * compatibility macro can be removed. - */ -#define ElfW(type) __ElfN(type) -#endif - #define PROF_DATA_START INSTR_PROF_SECT_START(INSTR_PROF_DATA_COMMON) #define PROF_DATA_STOP INSTR_PROF_SECT_STOP(INSTR_PROF_DATA_COMMON) #define PROF_NAME_START INSTR_PROF_SECT_START(INSTR_PROF_NAME_COMMON) -- GitLab From c1d02bd1479e669f6622f3f9b5b52423ae9631a1 Mon Sep 17 00:00:00 2001 From: Jacques Pienaar Date: Wed, 10 Jan 2024 10:41:02 -0800 Subject: [PATCH 368/652] [mlir] Change end of OperationDefinition. (#77273) Store the last token parsed in the parser state so that the range parsed can utilize its end rather than the start of the token after parsed. This results in a tighter range (especially true in the case of comments, see ```mlir |%c4 = arith.constant 4 : index // Foo | ``` vs ```mlir |%c4 = arith.constant 4 : index| ``` ). Discovered while working on a little textual post processing tool. --- mlir/lib/AsmParser/Parser.cpp | 12 +++++++----- mlir/lib/AsmParser/Parser.h | 5 +++++ mlir/lib/AsmParser/ParserState.h | 7 +++++-- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/mlir/lib/AsmParser/Parser.cpp b/mlir/lib/AsmParser/Parser.cpp index 3aa9adcbe1c5..00f2b0c0c2f1 100644 --- a/mlir/lib/AsmParser/Parser.cpp +++ b/mlir/lib/AsmParser/Parser.cpp @@ -1209,7 +1209,7 @@ ParseResult OperationParser::parseOperation() { resultIt += std::get<1>(record); } state.asmState->finalizeOperationDefinition( - op, nameTok.getLocRange(), /*endLoc=*/getToken().getLoc(), + op, nameTok.getLocRange(), /*endLoc=*/getLastToken().getEndLoc(), asmResultGroups); } @@ -1225,8 +1225,9 @@ ParseResult OperationParser::parseOperation() { // Add this operation to the assembly state if it was provided to populate. } else if (state.asmState) { - state.asmState->finalizeOperationDefinition(op, nameTok.getLocRange(), - /*endLoc=*/getToken().getLoc()); + state.asmState->finalizeOperationDefinition( + op, nameTok.getLocRange(), + /*endLoc=*/getLastToken().getEndLoc()); } return success(); @@ -1500,8 +1501,9 @@ Operation *OperationParser::parseGenericOperation(Block *insertBlock, // If we are populating the parser asm state, finalize this operation // definition. if (state.asmState) - state.asmState->finalizeOperationDefinition(op, nameToken.getLocRange(), - /*endLoc=*/getToken().getLoc()); + state.asmState->finalizeOperationDefinition( + op, nameToken.getLocRange(), + /*endLoc=*/getLastToken().getEndLoc()); return op; } diff --git a/mlir/lib/AsmParser/Parser.h b/mlir/lib/AsmParser/Parser.h index 01c55f97a08c..b959e67b8e25 100644 --- a/mlir/lib/AsmParser/Parser.h +++ b/mlir/lib/AsmParser/Parser.h @@ -102,6 +102,9 @@ public: const Token &getToken() const { return state.curToken; } StringRef getTokenSpelling() const { return state.curToken.getSpelling(); } + /// Return the last parsed token. + const Token &getLastToken() const { return state.lastToken; } + /// If the current token has the specified kind, consume it and return true. /// If not, return false. bool consumeIf(Token::Kind kind) { @@ -115,6 +118,7 @@ public: void consumeToken() { assert(state.curToken.isNot(Token::eof, Token::error) && "shouldn't advance past EOF or errors"); + state.lastToken = state.curToken; state.curToken = state.lex.lexToken(); } @@ -129,6 +133,7 @@ public: /// Reset the parser to the given lexer position. void resetToken(const char *tokPos) { state.lex.resetPointer(tokPos); + state.lastToken = state.curToken; state.curToken = state.lex.lexToken(); } diff --git a/mlir/lib/AsmParser/ParserState.h b/mlir/lib/AsmParser/ParserState.h index 1428ea3a82ce..159058a18fa4 100644 --- a/mlir/lib/AsmParser/ParserState.h +++ b/mlir/lib/AsmParser/ParserState.h @@ -54,8 +54,8 @@ struct ParserState { AsmParserCodeCompleteContext *codeCompleteContext) : config(config), lex(sourceMgr, config.getContext(), codeCompleteContext), - curToken(lex.lexToken()), symbols(symbols), asmState(asmState), - codeCompleteContext(codeCompleteContext) {} + curToken(lex.lexToken()), lastToken(Token::error, ""), symbols(symbols), + asmState(asmState), codeCompleteContext(codeCompleteContext) {} ParserState(const ParserState &) = delete; void operator=(const ParserState &) = delete; @@ -68,6 +68,9 @@ struct ParserState { /// This is the next token that hasn't been consumed yet. Token curToken; + /// This is the last token that has been consumed. + Token lastToken; + /// The current state for symbol parsing. SymbolState &symbols; -- GitLab From 5c9b713394486be91dc181062e5c01d696c30787 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 10 Jan 2024 13:41:48 -0500 Subject: [PATCH 369/652] [libc++][NFC] Fix typo in comments --- .../expected.expected/transform_error.mandates.verify.cpp | 4 ++-- .../expected.void/transform_error.mandates.verify.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp b/libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp index 46027fb46295..82024a068f00 100644 --- a/libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp +++ b/libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp @@ -6,9 +6,9 @@ // //===----------------------------------------------------------------------===// -// Clang-18 fixed some suspurious clang diagnostics. Once clang-18 is the +// Clang-18 fixed some spurious clang diagnostics. Once clang-18 is the // minumum required version these obsolete tests can be removed. -// TODO(LLVM-20) remove suspurious clang diagnostic tests. +// TODO(LLVM-20) remove spurious clang diagnostic tests. // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 diff --git a/libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp b/libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp index cce59b99c55a..0f2fb581ccd7 100644 --- a/libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp +++ b/libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp @@ -6,9 +6,9 @@ // //===----------------------------------------------------------------------===// -// Clang-18 fixed some suspurious clang diagnostics. Once clang-18 is the +// Clang-18 fixed some spurious clang diagnostics. Once clang-18 is the // minumum required version these obsolete tests can be removed. -// TODO(LLVM-20) remove suspurious clang diagnostic tests. +// TODO(LLVM-20) remove spurious clang diagnostic tests. // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 -- GitLab From 3358c77b01fff71c586cc998dd80e06662d9e854 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 10 Jan 2024 11:01:55 -0800 Subject: [PATCH 370/652] [CMake] Deprecate GCC_INSTALL_PREFIX (#77537) Part of https://reviews.llvm.org/D158218 GCC_INSTALL_PREFIX is a rarely-used legacy option inherited from pre-CMake build system and has configuration file replacement nowadays. Many `clang/test/Driver` tests specify `--gcc-toolchain=` to prevent failures when `GCC_INSTALL_PREFIX` is specified: some contributors add them to fix tests and some just do cargo culting. This is not healthy for contributors adding cross compilation support for this rarely used option. `DEFAULT_SYSROOT` should in spirit be deprecated as well, but a relative path doesn't have good replacement, so don't deprecate it for now. Link: https://discourse.llvm.org/t/add-gcc-install-dir-deprecate-gcc-toolchain-and-remove-gcc-install-prefix/65091 Link: https://discourse.llvm.org/t/correct-cmake-parameters-for-building-clang-and-lld-for-riscv/72833 --- With `GCC_INSTALL_PREFIX=/usr`, `clang a.c` behaves like `clang --gcc-toolchain=/usr a.c`. Here is a simplified version of GCC installation detection code. ``` if (OPT_gcc_install_dir_EQ) return OPT_gcc_install_dir_EQ; if (OPT_gcc_triple) candidate_gcc_triples = {OPT_gcc_triple}; else candidate_gcc_triples = collectCandidateTriples(); if (OPT_gcc_toolchain) prefixes = {OPT_gcc_toolchain}; else prefixes = {OPT_sysroot/usr, OPT_sysroot}; for (prefix : prefixes) if "$prefix/lib/gcc" exists // also tries $prefix/lib/gcc-cross for (triple : candidate_gcc_triples) if "$prefix/lib/gcc/$triple" exists return "$prefix/lib/gcc/$triple/$version"; // pick the largest version ``` `--gcc-toolchain=` specifies a directory where `lib/gcc{,-cross}/$triple/$version` can be found. If you actually want to use a specific version of GCC, specify something like `--gcc-install-dir=/usr/lib/gcc/x86_64-linux-gnu/11` in a configuration file. You can also specify `--gcc-triple=`. On Debian and its derivatives where the target triple omits the vendor part, the following ways are roughly equivalent, except that `--gcc-install-dir=` specifies a version as well: ``` clang --gcc-toolchain=/usr a.c clang --gcc-install-dir=/usr/lib/gcc/x86_64-linux-gnu/11 a.c clang --gcc-triple=x86_64-linux-gnu a.c ``` --- clang/CMakeLists.txt | 6 ++++++ clang/docs/ReleaseNotes.rst | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/clang/CMakeLists.txt b/clang/CMakeLists.txt index 9f814478c455..5f2b7f064da4 100644 --- a/clang/CMakeLists.txt +++ b/clang/CMakeLists.txt @@ -193,6 +193,12 @@ set(C_INCLUDE_DIRS "" CACHE STRING set(GCC_INSTALL_PREFIX "" CACHE PATH "Directory where gcc is installed." ) set(DEFAULT_SYSROOT "" CACHE STRING "Default to all compiler invocations for --sysroot=." ) +if(GCC_INSTALL_PREFIX) + message(WARNING "GCC_INSTALL_PREFIX is deprecated and will be removed. Use " + "configuration files (https://clang.llvm.org/docs/UsersManual.html#configuration-files)" + "to specify the default --gcc-install-dir= or --gcc-triple=. --gcc-toolchain= is discouraged. " + "See https://github.com/llvm/llvm-project/pull/77537 for detail.") +endif() set(ENABLE_LINKER_BUILD_ID OFF CACHE BOOL "pass --build-id to ld") diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 37f8bbc89d89..ade0036ba2fd 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -37,6 +37,12 @@ These changes are ones which we think may surprise users when upgrading to Clang |release| because of the opportunity they pose for disruption to existing code bases. +- The CMake variable ``GCC_INSTALL_PREFIX`` (which sets the default + ``--gcc-toolchain=``) is deprecated and will be removed. Specify + ``--gcc-install-dir=`` or ``--gcc-triple=`` in a `configuration file + ` as a + replacement. + (`#77537 `_) C/C++ Language Potentially Breaking Changes ------------------------------------------- -- GitLab From e6c2952eb51a422e17f002d97b0ea467be4d325b Mon Sep 17 00:00:00 2001 From: ChiaHungDuan Date: Wed, 10 Jan 2024 11:03:28 -0800 Subject: [PATCH 371/652] [scudo] Condition variable can be disabled by setting the flag to off (#77532) To enable the condition variable, you have to define both UseConditionVariable and the ConditionVariableT. Otherwise, it'll be disabled. However, you may want to disable the condition variable by setting UseConditionVariable=false, for example, while measuring the performance and you want to turn it off temporarily. Instead of requiring the removal of the variable, examining its value makes more sense. --- compiler-rt/lib/scudo/standalone/condition_variable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler-rt/lib/scudo/standalone/condition_variable.h b/compiler-rt/lib/scudo/standalone/condition_variable.h index 549f6e9f787b..4afebdc9d04c 100644 --- a/compiler-rt/lib/scudo/standalone/condition_variable.h +++ b/compiler-rt/lib/scudo/standalone/condition_variable.h @@ -51,7 +51,7 @@ struct ConditionVariableState { template struct ConditionVariableState { - static constexpr bool enabled() { return true; } + static constexpr bool enabled() { return Config::UseConditionVariable; } using ConditionVariableT = typename Config::ConditionVariableT; }; -- GitLab From 408dce82016463dcb5026b2ddfc62174970a88e9 Mon Sep 17 00:00:00 2001 From: Alexey Bataev <5361294+alexey-bataev@users.noreply.github.com> Date: Wed, 10 Jan 2024 14:06:29 -0500 Subject: [PATCH 372/652] [SLP]Do not require external uses for roots and single use for other instructions in computeMinimumValueSizes. (#72679) After changes, that does not require support from InstCombine, we can drop some extra requirements for values-to-be-demoted. No need to check for external uses for roots/other instructions, just check that the no non-vectorized insertelement instruction, which may require widening. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 15 +++++----- .../X86/int-bitcast-minbitwidth.ll | 21 ++++++-------- .../X86/minbitwidth-transformed-operand.ll | 28 +++++++------------ .../X86/root-trunc-extract-reuse.ll | 22 +++++++-------- 4 files changed, 35 insertions(+), 51 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 0ce5d619d9b1..6e3608ef3bef 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -13096,10 +13096,14 @@ bool BoUpSLP::collectValuesToDemote( if (isa(V)) return true; - // If the value is not a vectorized instruction in the expression with only - // one use, it cannot be demoted. + // If the value is not a vectorized instruction in the expression and not used + // by the insertelement instruction and not used in multiple vector nodes, it + // cannot be demoted. auto *I = dyn_cast(V); - if (!I || !I->hasOneUse() || !getTreeEntry(I) || !Visited.insert(I).second) + if (!I || !getTreeEntry(I) || MultiNodeScalars.contains(I) || + !Visited.insert(I).second || all_of(I->users(), [&](User *U) { + return isa(U) && !getTreeEntry(U); + })) return false; unsigned Start = 0; @@ -13170,11 +13174,6 @@ bool BoUpSLP::collectValuesToDemote( } void BoUpSLP::computeMinimumValueSizes() { - // If there are no external uses, the expression tree must be rooted by a - // store. We can't demote in-memory values, so there is nothing to do here. - if (ExternalUses.empty()) - return; - // We only attempt to truncate integer expressions. auto &TreeRoot = VectorizableTree[0]->Scalars; auto *TreeRootIT = dyn_cast(TreeRoot[0]->getType()); diff --git a/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll index fa0a3610cc22..a0af8e36b36c 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll @@ -5,19 +5,14 @@ define void @t(i64 %v) { ; CHECK-LABEL: define void @t( ; CHECK-SAME: i64 [[V:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CONV12_1_I:%.*]] = trunc i64 [[V]] to i32 -; CHECK-NEXT: [[MUL_I_1_I:%.*]] = mul i32 [[CONV12_1_I]], 2 -; CHECK-NEXT: [[CONV12_I:%.*]] = trunc i64 [[V]] to i32 -; CHECK-NEXT: [[MUL_I_I:%.*]] = mul i32 [[CONV12_I]], 3 -; CHECK-NEXT: [[CONV14104_I:%.*]] = or i32 [[MUL_I_1_I]], [[MUL_I_I]] -; CHECK-NEXT: [[CONV12_1_I_1:%.*]] = trunc i64 [[V]] to i32 -; CHECK-NEXT: [[MUL_I_1_I_1:%.*]] = mul i32 [[CONV12_1_I_1]], 6 -; CHECK-NEXT: [[CONV12_I_1:%.*]] = trunc i64 [[V]] to i32 -; CHECK-NEXT: [[MUL_I_I_1:%.*]] = mul i32 [[CONV12_I_1]], 5 -; CHECK-NEXT: [[CONV14104_I_1:%.*]] = or i32 [[MUL_I_1_I_1]], [[MUL_I_I_1]] -; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[CONV14104_I]], [[CONV14104_I_1]] -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 65535 -; CHECK-NEXT: store i32 [[TMP1]], ptr null, align 4 +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[V]], i32 0 +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[TMP1]] to <4 x i16> +; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i16> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = sext i16 [[TMP4]] to i32 +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 65535 +; CHECK-NEXT: store i32 [[TMP6]], ptr null, align 4 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll index 94446b99514b..2c834616becc 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll @@ -5,24 +5,16 @@ define void @test(i64 %d.promoted.i) { ; CHECK-LABEL: define void @test( ; CHECK-SAME: i64 [[D_PROMOTED_I:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> , i64 [[D_PROMOTED_I]], i32 0 -; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[TMP0]] to <2 x i1> -; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i1> zeroinitializer, [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = mul <2 x i1> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i1> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i1> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i1> [[TMP5]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <2 x i1> [[TMP6]], zeroinitializer -; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i1> [[TMP7]], zeroinitializer -; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i1> [[TMP8]], zeroinitializer -; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i1> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP10]], i32 0 -; CHECK-NEXT: [[TMP12:%.*]] = sext i1 [[TMP11]] to i32 -; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP10]], i32 1 -; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i32 -; CHECK-NEXT: [[TMP15:%.*]] = or i32 [[TMP12]], [[TMP14]] -; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 0 -; CHECK-NEXT: store i32 [[TMP16]], ptr null, align 4 +; CHECK-NEXT: [[AND_1_I:%.*]] = and i64 0, [[D_PROMOTED_I]] +; CHECK-NEXT: [[AND_1_I_1:%.*]] = and i64 0, 0 +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i64> , i64 [[AND_1_I_1]], i32 1 +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i64> [[TMP0]], i64 [[AND_1_I]], i32 9 +; CHECK-NEXT: [[TMP2:%.*]] = trunc <16 x i64> [[TMP1]] to <16 x i1> +; CHECK-NEXT: [[TMP3:%.*]] = mul <16 x i1> [[TMP2]], zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP4]] to i32 +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 0 +; CHECK-NEXT: store i32 [[TMP6]], ptr null, align 4 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/root-trunc-extract-reuse.ll b/llvm/test/Transforms/SLPVectorizer/X86/root-trunc-extract-reuse.ll index f48528e502b8..af46b4f57623 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/root-trunc-extract-reuse.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/root-trunc-extract-reuse.ll @@ -8,20 +8,18 @@ define i1 @test() { ; CHECK: then: ; CHECK-NEXT: br label [[ELSE]] ; CHECK: else: -; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i1> [ zeroinitializer, [[THEN]] ], [ zeroinitializer, [[ENTRY:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[TMP0]] to <2 x i32> -; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i1> [[TMP0]], i32 0 -; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 -; CHECK-NEXT: [[BF_CAST162:%.*]] = and i32 [[TMP3]], 0 -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> zeroinitializer, <2 x i32> [[TMP1]], <2 x i32> -; CHECK-NEXT: [[T13:%.*]] = and <2 x i32> [[TMP4]], zeroinitializer +; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ zeroinitializer, [[THEN]] ], [ zeroinitializer, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 0 +; CHECK-NEXT: [[BF_CAST162:%.*]] = and i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> zeroinitializer, <2 x i32> [[TMP0]], <2 x i32> +; CHECK-NEXT: [[T13:%.*]] = and <2 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: br label [[ELSE1:%.*]] ; CHECK: else1: -; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[T13]], <2 x i32> poison, <2 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP5]], i32 [[BF_CAST162]], i32 0 -; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt <2 x i32> [[TMP6]], zeroinitializer -; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP7]], i32 1 -; CHECK-NEXT: ret i1 [[TMP8]] +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[T13]], <2 x i32> poison, <2 x i32> +; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[BF_CAST162]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt <2 x i32> [[TMP4]], zeroinitializer +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP5]], i32 1 +; CHECK-NEXT: ret i1 [[TMP6]] ; entry: br i1 false, label %then, label %else -- GitLab From 51fbab134560ece663517bf1e8c2a30300d08f1a Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 10 Jan 2024 11:13:28 -0800 Subject: [PATCH 373/652] [asan] Enable StackSafetyAnalysis by default StackSafetyAnalysis determines whether stack-allocated variables are guaranteed to be safe from memory access bugs and enables the removal of certain unneeded instrumentations. (hwasan enables StackSafetyAnalysis in https://reviews.llvm.org/D108381) Test updates: * asan-stack-safety.ll: test the -asan-use-stack-safety=1 default * lifetime-uar-uas.ll: switch to an indexed store to prevent StackSafetyAnalysis from optimizing out instrumentation for %c * alloca_vla_interact.cpp: add a load to prevent StackSafetyAnalysis from optimizing out `__asan_alloca_poison` for the VLA `array` * scariness_score_test.cpp: add -asan-use-stack-safety=0 to make a load of a `__asan_poison_memory_region`-poisoned local variable fail as intended. * other .ll tests: add -asan-use-stack-safety=0 Reviewers: kstoimenov, eugenis, vitalybuka Reviewed By: kstoimenov Pull Request: https://github.com/llvm/llvm-project/pull/77210 --- .../test/asan/TestCases/alloca_vla_interact.cpp | 2 ++ .../test/asan/TestCases/scariness_score_test.cpp | 6 ++++-- .../Transforms/Instrumentation/AddressSanitizer.cpp | 2 +- .../AddressSanitizer/asan-stack-safety.ll | 2 +- .../Instrumentation/AddressSanitizer/debug_info.ll | 2 +- .../AddressSanitizer/lifetime-uar-uas.ll | 13 ++++++++----- .../Instrumentation/AddressSanitizer/lifetime.ll | 4 ++-- .../AddressSanitizer/local_stack_base.ll | 2 +- .../AddressSanitizer/stack_dynamic_alloca.ll | 8 ++++---- .../AddressSanitizer/stack_layout.ll | 4 ++-- 10 files changed, 26 insertions(+), 19 deletions(-) diff --git a/compiler-rt/test/asan/TestCases/alloca_vla_interact.cpp b/compiler-rt/test/asan/TestCases/alloca_vla_interact.cpp index 92b0afafc8db..96ac4c7db291 100644 --- a/compiler-rt/test/asan/TestCases/alloca_vla_interact.cpp +++ b/compiler-rt/test/asan/TestCases/alloca_vla_interact.cpp @@ -33,6 +33,8 @@ __attribute__((noinline)) void foo(int len) { if (i) assert(!__asan_region_is_poisoned(bot, 96)); // VLA is unpoisoned at the end of iteration. volatile char array[i]; + // Ensure that asan-use-stack-safety does not optimize out the poisoning. + if (i) array[0] = 0; assert(!(reinterpret_cast(array) & 31L)); // Alloca is unpoisoned at the end of iteration, // because dominated by VLA. diff --git a/compiler-rt/test/asan/TestCases/scariness_score_test.cpp b/compiler-rt/test/asan/TestCases/scariness_score_test.cpp index d73975feb687..9e55e33675fd 100644 --- a/compiler-rt/test/asan/TestCases/scariness_score_test.cpp +++ b/compiler-rt/test/asan/TestCases/scariness_score_test.cpp @@ -1,7 +1,9 @@ // Test how we produce the scariness score. // UAR Mode: runtime -// RUN: %clangxx_asan -O0 %s -o %t +// Case 26 loads a __asan_poison_memory_region-poisoned local variable, which is +// only instrumented when StackSafetyAnalysis is disabled. +// RUN: %clangxx_asan -O0 -mllvm -asan-use-stack-safety=0 %s -o %t // On OSX and Windows, alloc_dealloc_mismatch=1 isn't 100% reliable, so it's // off by default. It's safe for these tests, though, so we turn it on. // RUN: export %env_asan_opts=symbolize=0:detect_stack_use_after_return=1:handle_abort=1:print_scariness=1:alloc_dealloc_mismatch=1 @@ -36,7 +38,7 @@ // RUN: not %run %t 27 2>&1 | FileCheck %s --check-prefix=CHECK27 // // UAR Mode: always -// RUN: %clangxx_asan -O0 %s -o %t -fsanitize-address-use-after-return=always +// RUN: %clangxx_asan -O0 %s -o %t -fsanitize-address-use-after-return=always -mllvm -asan-use-stack-safety=0 // On OSX and Windows, alloc_dealloc_mismatch=1 isn't 100% reliable, so it's // off by default. It's safe for these tests, though, so we turn it on. // RUN: export %env_asan_opts=symbolize=0:handle_abort=1:print_scariness=1:alloc_dealloc_mismatch=1 diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp index e3deafa49bd9..5e7e08eaa997 100644 --- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp @@ -216,7 +216,7 @@ static cl::opt ClInstrumentWrites( cl::Hidden, cl::init(true)); static cl::opt - ClUseStackSafety("asan-use-stack-safety", cl::Hidden, cl::init(false), + ClUseStackSafety("asan-use-stack-safety", cl::Hidden, cl::init(true), cl::Hidden, cl::desc("Use Stack Safety analysis results"), cl::Optional); diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll index 02c58a1f4922..8210970aaaeb 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll @@ -1,7 +1,7 @@ ; REQUIRES: x86-registered-target ; RUN: opt < %s -S -asan-instrumentation-with-call-threshold=0 -passes=asan -asan-use-stack-safety=0 -o - | FileCheck %s --implicit-check-not="call {{.*}} @__asan_{{load|store|stack}}" --check-prefixes=CHECK,NOSAFETY -; RUN: opt < %s -S -asan-instrumentation-with-call-threshold=0 -passes=asan -asan-use-stack-safety=1 -o - | FileCheck %s --implicit-check-not="call {{.*}} @__asan_{{load|store|stack}}" +; RUN: opt < %s -S -asan-instrumentation-with-call-threshold=0 -passes=asan | FileCheck %s --implicit-check-not="call {{.*}} @__asan_{{load|store|stack}}" ; CHECK-LABEL: define i32 @load define i32 @load() sanitize_address { diff --git a/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll b/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll index 4c678f984864..edd63c614857 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -passes=asan -asan-use-after-return=never -S | FileCheck %s +; RUN: opt < %s -passes=asan -asan-use-after-return=never -asan-use-stack-safety=0 -S | FileCheck %s ; Checks that llvm.dbg.declare instructions are updated ; accordingly as we merge allocas. diff --git a/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll b/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll index 302205c4f6ca..a40dad526a14 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll @@ -11,26 +11,29 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind -define i32 @basic_test() sanitize_address { - ; CHECK-LABEL: define i32 @basic_test() +define i32 @basic_test(i64 %i) sanitize_address { + ; CHECK-LABEL: define i32 @basic_test( entry: %retval = alloca i32, align 4 - %c = alloca i8, align 1 + %c = alloca [2 x i8], align 1 ; Memory is poisoned in prologue: F1F1F1F104F3F8F2 ; CHECK-UAS: store i64 -866676825215864335, ptr %{{[0-9]+}} + ; CHECK-UAS-SS-NOT: store i64 call void @llvm.lifetime.start.p0(i64 1, ptr %c) ; Memory is unpoisoned at llvm.lifetime.start: 01 - ; CHECK-UAS: store i8 1, ptr %{{[0-9]+}} + ; CHECK-UAS: store i8 2, ptr %{{[0-9]+}} + %ci = getelementptr inbounds [2 x i8], ptr %c, i64 0, i64 %i store volatile i32 0, ptr %retval - store volatile i8 0, ptr %c, align 1 + store volatile i8 0, ptr %ci, align 1 call void @llvm.lifetime.end.p0(i64 1, ptr %c) ; Memory is poisoned at llvm.lifetime.end: F8 ; CHECK-UAS: store i8 -8, ptr %{{[0-9]+}} + ; CHECK-UAS-SS-NOT: store i8 -8, ; Unpoison memory at function exit in UAS mode. ; CHECK-UAS: store i64 0, ptr %{{[0-9]+}} diff --git a/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll b/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll index 7f158487a47a..1d073cdc3bdb 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll @@ -1,6 +1,6 @@ ; Test handling of llvm.lifetime intrinsics. -; RUN: opt < %s -passes=asan -asan-use-after-scope -asan-use-after-return=never -S | FileCheck %s --check-prefixes=CHECK,CHECK-DEFAULT -; RUN: opt < %s -passes=asan -asan-use-after-scope -asan-use-after-return=never -asan-instrument-dynamic-allocas=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DYNAMIC +; RUN: opt < %s -passes=asan -asan-use-after-scope -asan-use-after-return=never -asan-use-stack-safety=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-DEFAULT +; RUN: opt < %s -passes=asan -asan-use-after-scope -asan-use-after-return=never -asan-use-stack-safety=0 -asan-instrument-dynamic-allocas=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DYNAMIC target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll b/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll index 43b402e1b166..4e8466b68568 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -passes=asan -asan-skip-promotable-allocas=0 %s -o - | FileCheck %s +; RUN: opt -S -passes=asan -asan-use-stack-safety=0 -asan-skip-promotable-allocas=0 %s -o - | FileCheck %s ; Generated from: ; int bar(int y) { ; return y + 2; diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll b/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll index 98851b871393..cbb2001c45e6 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll @@ -1,14 +1,14 @@ -; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca \ +; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca -asan-use-stack-safety=0 \ ; RUN: -asan-use-after-return=runtime -S | FileCheck %s \ ; RUN: --check-prefixes=CHECK,CHECK-RUNTIME -; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca -asan-mapping-scale=5 \ +; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca -asan-mapping-scale=5 -asan-use-stack-safety=0 \ ; RUN: -asan-use-after-return=runtime -S | FileCheck %s \ ; RUN: --check-prefixes=CHECK,CHECK-RUNTIME -; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca \ +; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca -asan-use-stack-safety=0 \ ; RUN: -asan-use-after-return=always -S | FileCheck %s \ ; RUN: --check-prefixes=CHECK,CHECK-ALWAYS \ ; RUN: --implicit-check-not=__asan_option_detect_stack_use_after_return -; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca \ +; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca -asan-use-stack-safety=0 \ ; RUN: -asan-use-after-return=always -S | FileCheck %s \ ; RUN: --check-prefixes=CHECK,CHECK-ALWAYS \ ; RUN: --implicit-check-not=__asan_option_detect_stack_use_after_return diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll b/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll index 726f628607da..48465be36789 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll @@ -1,8 +1,8 @@ ; Test the ASan's stack layout. ; More tests in tests/Transforms/Utils/ASanStackFrameLayoutTest.cpp -; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca=0 -asan-use-after-scope -S \ +; RUN: opt < %s -passes=asan -asan-use-stack-safety=0 -asan-stack-dynamic-alloca=0 -asan-use-after-scope -S \ ; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-STATIC -; RUN: opt < %s -passes=asan -asan-stack-dynamic-alloca=1 -asan-use-after-scope -S \ +; RUN: opt < %s -passes=asan -asan-use-stack-safety=0 -asan-stack-dynamic-alloca=1 -asan-use-after-scope -S \ ; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-DYNAMIC target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -- GitLab From e80b9436476bba714e843461e03227b222185f7b Mon Sep 17 00:00:00 2001 From: Timm Baeder Date: Wed, 10 Jan 2024 20:19:04 +0100 Subject: [PATCH 374/652] [clang][Interp] Fix discarded integral and floating casts (#77295) We need to handle this at the CastExpr level. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 7 +++++++ clang/test/AST/Interp/literals.cpp | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index e6b3097a80d8..7f8bbe787324 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -114,6 +114,8 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { } case CK_FloatingCast: { + if (DiscardResult) + return this->discard(SubExpr); if (!this->visit(SubExpr)) return false; const auto *TargetSemantics = &Ctx.getFloatSemantics(CE->getType()); @@ -121,6 +123,8 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { } case CK_IntegralToFloating: { + if (DiscardResult) + return this->discard(SubExpr); std::optional FromT = classify(SubExpr->getType()); if (!FromT) return false; @@ -135,6 +139,9 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { case CK_FloatingToBoolean: case CK_FloatingToIntegral: { + if (DiscardResult) + return this->discard(SubExpr); + std::optional ToT = classify(CE->getType()); if (!ToT) diff --git a/clang/test/AST/Interp/literals.cpp b/clang/test/AST/Interp/literals.cpp index 85adfe551384..61825bc11438 100644 --- a/clang/test/AST/Interp/literals.cpp +++ b/clang/test/AST/Interp/literals.cpp @@ -1024,6 +1024,10 @@ namespace DiscardExprs { __null; __builtin_offsetof(A, a); 1,2; + (int)1.0; + (float)1; + (double)1.0f; + (signed)4u; return 0; } -- GitLab From a1dc813f759955ddbcf9b12ed052dfc8a07fdf4a Mon Sep 17 00:00:00 2001 From: Emilio Cota Date: Wed, 10 Jan 2024 14:32:57 -0500 Subject: [PATCH 375/652] [mlir][mesh] fix unused variable error --- mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp b/mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp index 7acbf5189704..5018a308a3bd 100644 --- a/mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp +++ b/mlir/test/lib/Dialect/Mesh/TestProcessMultiIndexOpLowering.cpp @@ -43,6 +43,7 @@ void TestMultiIndexOpLoweringPass::runOnOperation() { symbolTableCollection); LogicalResult status = applyPatternsAndFoldGreedily(getOperation(), std::move(patterns)); + (void)status; assert(succeeded(status) && "applyPatternsAndFoldGreedily failed."); } -- GitLab From 2dde029df8f9e3b2ece6899dc73bea226f227d11 Mon Sep 17 00:00:00 2001 From: Abhinav271828 <71174780+Abhinav271828@users.noreply.github.com> Date: Thu, 11 Jan 2024 01:28:36 +0530 Subject: [PATCH 376/652] [MLIR][Presburger] Implement computation of generating function for unimodular cones (#77235) We implement a function that computes the generating function corresponding to a unimodular cone. The generating function for a polytope is obtained by summing these generating functions over all tangent cones. --- .../mlir/Analysis/Presburger/Barvinok.h | 6 ++ .../Analysis/Presburger/IntegerRelation.h | 2 + .../include/mlir/Analysis/Presburger/Matrix.h | 3 + mlir/lib/Analysis/Presburger/Barvinok.cpp | 83 ++++++++++++++++++- mlir/lib/Analysis/Presburger/Matrix.cpp | 10 +++ .../Analysis/Presburger/BarvinokTest.cpp | 36 ++++++++ 6 files changed, 139 insertions(+), 1 deletion(-) diff --git a/mlir/include/mlir/Analysis/Presburger/Barvinok.h b/mlir/include/mlir/Analysis/Presburger/Barvinok.h index 15e805860db2..213af636e596 100644 --- a/mlir/include/mlir/Analysis/Presburger/Barvinok.h +++ b/mlir/include/mlir/Analysis/Presburger/Barvinok.h @@ -24,6 +24,7 @@ #ifndef MLIR_ANALYSIS_PRESBURGER_BARVINOK_H #define MLIR_ANALYSIS_PRESBURGER_BARVINOK_H +#include "mlir/Analysis/Presburger/GeneratingFunction.h" #include "mlir/Analysis/Presburger/IntegerRelation.h" #include "mlir/Analysis/Presburger/Matrix.h" #include @@ -77,6 +78,11 @@ ConeV getDual(ConeH cone); /// The returned cone is pointed at the origin. ConeH getDual(ConeV cone); +/// Compute the generating function for a unimodular cone. +/// The input cone must be unimodular; it assert-fails otherwise. +GeneratingFunction unimodularConeGeneratingFunction(ParamPoint vertex, int sign, + ConeH cone); + } // namespace detail } // namespace presburger } // namespace mlir diff --git a/mlir/include/mlir/Analysis/Presburger/IntegerRelation.h b/mlir/include/mlir/Analysis/Presburger/IntegerRelation.h index cd957280eb74..8e2c9fca0a17 100644 --- a/mlir/include/mlir/Analysis/Presburger/IntegerRelation.h +++ b/mlir/include/mlir/Analysis/Presburger/IntegerRelation.h @@ -221,6 +221,8 @@ public: return getInt64Vec(inequalities.getRow(idx)); } + inline IntMatrix getInequalities() const { return inequalities; } + /// Get the number of vars of the specified kind. unsigned getNumVarKind(VarKind kind) const { return space.getNumVarKind(kind); diff --git a/mlir/include/mlir/Analysis/Presburger/Matrix.h b/mlir/include/mlir/Analysis/Presburger/Matrix.h index 347e2e048978..38fac50c1353 100644 --- a/mlir/include/mlir/Analysis/Presburger/Matrix.h +++ b/mlir/include/mlir/Analysis/Presburger/Matrix.h @@ -181,6 +181,9 @@ public: /// `elems` must be equal to the number of columns. unsigned appendExtraRow(ArrayRef elems); + // Transpose the matrix without modifying it. + Matrix transpose() const; + /// Print the matrix. void print(raw_ostream &os) const; void dump() const; diff --git a/mlir/lib/Analysis/Presburger/Barvinok.cpp b/mlir/lib/Analysis/Presburger/Barvinok.cpp index 9152b66968a1..0bdc9015c3d6 100644 --- a/mlir/lib/Analysis/Presburger/Barvinok.cpp +++ b/mlir/lib/Analysis/Presburger/Barvinok.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "mlir/Analysis/Presburger/Barvinok.h" +#include "llvm/ADT/Sequence.h" using namespace mlir; using namespace presburger; @@ -24,7 +25,7 @@ ConeV mlir::presburger::detail::getDual(ConeH cone) { // is represented as a row [a1, ..., an, b] // and that b = 0. - for (unsigned i = 0; i < numIneq; ++i) { + for (auto i : llvm::seq(0, numIneq)) { assert(cone.atIneq(i, numVar) == 0 && "H-representation of cone is not centred at the origin!"); for (unsigned j = 0; j < numVar; ++j) { @@ -63,3 +64,83 @@ MPInt mlir::presburger::detail::getIndex(ConeV cone) { return cone.determinant(); } + +/// Compute the generating function for a unimodular cone. +/// This consists of a single term of the form +/// sign * x^num / prod_j (1 - x^den_j) +/// +/// sign is either +1 or -1. +/// den_j is defined as the set of generators of the cone. +/// num is computed by expressing the vertex as a weighted +/// sum of the generators, and then taking the floor of the +/// coefficients. +GeneratingFunction mlir::presburger::detail::unimodularConeGeneratingFunction( + ParamPoint vertex, int sign, ConeH cone) { + // Consider a cone with H-representation [0 -1]. + // [-1 -2] + // Let the vertex be given by the matrix [ 2 2 0], with 2 params. + // [-1 -1/2 1] + + // `cone` must be unimodular. + assert(getIndex(getDual(cone)) == 1 && "input cone is not unimodular!"); + + unsigned numVar = cone.getNumVars(); + unsigned numIneq = cone.getNumInequalities(); + + // Thus its ray matrix, U, is the inverse of the + // transpose of its inequality matrix, `cone`. + // The last column of the inequality matrix is null, + // so we remove it to obtain a square matrix. + FracMatrix transp = FracMatrix(cone.getInequalities()).transpose(); + transp.removeRow(numVar); + + FracMatrix generators(numVar, numIneq); + transp.determinant(/*inverse=*/&generators); // This is the U-matrix. + // Thus the generators are given by U = [2 -1]. + // [-1 0] + + // The powers in the denominator of the generating + // function are given by the generators of the cone, + // i.e., the rows of the matrix U. + std::vector denominator(numIneq); + ArrayRef row; + for (auto i : llvm::seq(0, numVar)) { + row = generators.getRow(i); + denominator[i] = Point(row); + } + + // The vertex is v \in Z^{d x (n+1)} + // We need to find affine functions of parameters λ_i(p) + // such that v = Σ λ_i(p)*u_i, + // where u_i are the rows of U (generators) + // The λ_i are given by the columns of Λ = v^T U^{-1}, and + // we have transp = U^{-1}. + // Then the exponent in the numerator will be + // Σ -floor(-λ_i(p))*u_i. + // Thus we store the (exponent of the) numerator as the affine function -Λ, + // since the generators u_i are already stored as the exponent of the + // denominator. Note that the outer -1 will have to be accounted for, as it is + // not stored. See end for an example. + + unsigned numColumns = vertex.getNumColumns(); + unsigned numRows = vertex.getNumRows(); + ParamPoint numerator(numColumns, numRows); + SmallVector ithCol(numRows); + for (auto i : llvm::seq(0, numColumns)) { + for (auto j : llvm::seq(0, numRows)) + ithCol[j] = vertex(j, i); + numerator.setRow(i, transp.preMultiplyWithRow(ithCol)); + numerator.negateRow(i); + } + // Therefore Λ will be given by [ 1 0 ] and the negation of this will be + // [ 1/2 -1 ] + // [ -1 -2 ] + // stored as the numerator. + // Algebraically, the numerator exponent is + // [ -2 ⌊ - N - M/2 + 1 ⌋ + 1 ⌊ 0 + M + 2 ⌋ ] -> first COLUMN of U is [2, -1] + // [ 1 ⌊ - N - M/2 + 1 ⌋ + 0 ⌊ 0 + M + 2 ⌋ ] -> second COLUMN of U is [-1, 0] + + return GeneratingFunction(numColumns - 1, SmallVector(1, sign), + std::vector({numerator}), + std::vector({denominator})); +} diff --git a/mlir/lib/Analysis/Presburger/Matrix.cpp b/mlir/lib/Analysis/Presburger/Matrix.cpp index b68a7b7004bb..349520747c5d 100644 --- a/mlir/lib/Analysis/Presburger/Matrix.cpp +++ b/mlir/lib/Analysis/Presburger/Matrix.cpp @@ -62,6 +62,16 @@ unsigned Matrix::appendExtraRow(ArrayRef elems) { return row; } +template +Matrix Matrix::transpose() const { + Matrix transp(nColumns, nRows); + for (unsigned row = 0; row < nRows; ++row) + for (unsigned col = 0; col < nColumns; ++col) + transp(col, row) = at(row, col); + + return transp; +} + template void Matrix::resizeHorizontally(unsigned newNColumns) { if (newNColumns < nColumns) diff --git a/mlir/unittests/Analysis/Presburger/BarvinokTest.cpp b/mlir/unittests/Analysis/Presburger/BarvinokTest.cpp index b88baa6c6b48..2936d95c802e 100644 --- a/mlir/unittests/Analysis/Presburger/BarvinokTest.cpp +++ b/mlir/unittests/Analysis/Presburger/BarvinokTest.cpp @@ -46,3 +46,39 @@ TEST(BarvinokTest, getIndex) { 4, 4, {{4, 2, 5, 1}, {4, 1, 3, 6}, {8, 2, 5, 6}, {5, 2, 5, 7}}); EXPECT_EQ(getIndex(cone), cone.determinant()); } + +// The following cones and vertices are randomly generated +// (s.t. the cones are unimodular) and the generating functions +// are computed. We check that the results contain the correct +// matrices. +TEST(BarvinokTest, unimodularConeGeneratingFunction) { + ConeH cone = defineHRep(2); + cone.addInequality({0, -1, 0}); + cone.addInequality({-1, -2, 0}); + + ParamPoint vertex = + makeFracMatrix(2, 3, {{2, 2, 0}, {-1, -Fraction(1, 2), 1}}); + + GeneratingFunction gf = unimodularConeGeneratingFunction(vertex, 1, cone); + + EXPECT_EQ_REPR_GENERATINGFUNCTION( + gf, GeneratingFunction( + 2, {1}, + {makeFracMatrix(3, 2, {{-1, 0}, {-Fraction(1, 2), 1}, {1, 2}})}, + {{{2, -1}, {-1, 0}}})); + + cone = defineHRep(3); + cone.addInequality({7, 1, 6, 0}); + cone.addInequality({9, 1, 7, 0}); + cone.addInequality({8, -1, 1, 0}); + + vertex = makeFracMatrix(3, 2, {{5, 2}, {6, 2}, {7, 1}}); + + gf = unimodularConeGeneratingFunction(vertex, 1, cone); + + EXPECT_EQ_REPR_GENERATINGFUNCTION( + gf, + GeneratingFunction( + 1, {1}, {makeFracMatrix(2, 3, {{-83, -100, -41}, {-22, -27, -15}})}, + {{{8, 47, -17}, {-7, -41, 15}, {1, 5, -2}}})); +} -- GitLab From 0a1b066bbaf7e3800f47697231d7e1e91744ecbf Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Jan 2024 12:00:40 -0800 Subject: [PATCH 377/652] [RISCV] Support isel for Zacas for XLen and i32. (#77666) This adds new isel patterns for Zacas that take priority over the pseudoinstructions we use for the A extension. Support for 2x XLen types will come in a separate patch since they need to be done differently. --- llvm/lib/Target/RISCV/RISCVFeatures.td | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 14 +- llvm/lib/Target/RISCV/RISCVInstrInfoZa.td | 51 + .../RISCV/atomic-cmpxchg-branch-on-result.ll | 274 ++- llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 1824 +++++++++++++++-- 5 files changed, 1977 insertions(+), 187 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index bb7a3291085d..279509575bb5 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -736,6 +736,7 @@ def FeatureStdExtZacas def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, AssemblerPredicate<(all_of FeatureStdExtZacas), "'Zacas' (Atomic Compare-And-Swap Instructions)">; +def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; //===----------------------------------------------------------------------===// // Vendor extensions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index 1ff5189260a9..44552c00c62e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -333,11 +333,17 @@ multiclass PseudoCmpXchgPat; } -let Predicates = [HasStdExtA] in { - +let Predicates = [HasStdExtA, NoStdExtZacas] in { def PseudoCmpXchg32 : PseudoCmpXchg; defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32>; +} + +let Predicates = [HasStdExtA, NoStdExtZacas, IsRV64] in { +def PseudoCmpXchg64 : PseudoCmpXchg; +defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64, i64>; +} +let Predicates = [HasStdExtA] in { def PseudoMaskedCmpXchg32 : Pseudo<(outs GPR:$res, GPR:$scratch), (ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, @@ -356,10 +362,6 @@ def : Pat<(int_riscv_masked_cmpxchg_i32 } // Predicates = [HasStdExtA] let Predicates = [HasStdExtA, IsRV64] in { - -def PseudoCmpXchg64 : PseudoCmpXchg; -defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64, i64>; - def : Pat<(int_riscv_masked_cmpxchg_i64 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering), (PseudoMaskedCmpXchg32 diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td index ea8046d119d0..ffcdd0010749 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td @@ -67,6 +67,57 @@ defm AMOCAS_D_RV64 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPR>; defm AMOCAS_Q : AMO_cas_aq_rl<0b00101, 0b100, "amocas.q", GPRPairRV64>; } // Predicates = [HasStdExtZacas, IsRV64] +multiclass AMOCASPat ExtraPreds = []> { + let Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds) in { + def : Pat<(!cast(AtomicOp#"_monotonic") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_acquire") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst#"_AQ") GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_release") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst#"_RL") GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_acq_rel") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_seq_cst") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>; + } // Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds) + let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in { + def : Pat<(!cast(AtomicOp#"_monotonic") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_acquire") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_release") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_acq_rel") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>; + def : Pat<(!cast(AtomicOp#"_seq_cst") (vt GPR:$addr), + (vt GPR:$cmp), + (vt GPR:$new)), + (!cast(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>; + } // Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) +} + +defm : AMOCASPat<"atomic_cmp_swap_32", "AMOCAS_W">; +defm : AMOCASPat<"atomic_cmp_swap_64", "AMOCAS_D_RV64", i64, [IsRV64]>; + //===----------------------------------------------------------------------===// // Zawrs (Wait-on-Reservation-Set) //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll index 651f58d32442..a8477cc550fe 100644 --- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll +++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll @@ -1,30 +1,44 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ -; RUN: | FileCheck -check-prefixes=CHECK,RV32IA %s +; RUN: | FileCheck -check-prefixes=NOZACAS,RV32IA %s +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=ZACAS,RV32IA-ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ -; RUN: | FileCheck -check-prefixes=CHECK,RV64IA %s +; RUN: | FileCheck -check-prefixes=NOZACAS,RV64IA %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZACAS %s ; Test cmpxchg followed by a branch on the cmpxchg success value to see if the ; branch is folded into the cmpxchg expansion. define void @cmpxchg_and_branch1(ptr %ptr, i32 signext %cmp, i32 signext %val) nounwind { -; CHECK-LABEL: cmpxchg_and_branch1: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: .LBB0_1: # %do_cmpxchg -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB0_3 Depth 2 -; CHECK-NEXT: .LBB0_3: # %do_cmpxchg -; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-NEXT: lr.w.aqrl a3, (a0) -; CHECK-NEXT: bne a3, a1, .LBB0_1 -; CHECK-NEXT: # %bb.4: # %do_cmpxchg -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=2 -; CHECK-NEXT: sc.w.rl a4, a2, (a0) -; CHECK-NEXT: bnez a4, .LBB0_3 -; CHECK-NEXT: # %bb.5: # %do_cmpxchg -; CHECK-NEXT: # %bb.2: # %exit -; CHECK-NEXT: ret +; NOZACAS-LABEL: cmpxchg_and_branch1: +; NOZACAS: # %bb.0: # %entry +; NOZACAS-NEXT: .LBB0_1: # %do_cmpxchg +; NOZACAS-NEXT: # =>This Loop Header: Depth=1 +; NOZACAS-NEXT: # Child Loop BB0_3 Depth 2 +; NOZACAS-NEXT: .LBB0_3: # %do_cmpxchg +; NOZACAS-NEXT: # Parent Loop BB0_1 Depth=1 +; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2 +; NOZACAS-NEXT: lr.w.aqrl a3, (a0) +; NOZACAS-NEXT: bne a3, a1, .LBB0_1 +; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB0_3 Depth=2 +; NOZACAS-NEXT: sc.w.rl a4, a2, (a0) +; NOZACAS-NEXT: bnez a4, .LBB0_3 +; NOZACAS-NEXT: # %bb.5: # %do_cmpxchg +; NOZACAS-NEXT: # %bb.2: # %exit +; NOZACAS-NEXT: ret +; +; ZACAS-LABEL: cmpxchg_and_branch1: +; ZACAS: # %bb.0: # %entry +; ZACAS-NEXT: .LBB0_1: # %do_cmpxchg +; ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; ZACAS-NEXT: mv a3, a1 +; ZACAS-NEXT: amocas.w.aqrl a3, a2, (a0) +; ZACAS-NEXT: bne a3, a1, .LBB0_1 +; ZACAS-NEXT: # %bb.2: # %exit +; ZACAS-NEXT: ret entry: br label %do_cmpxchg do_cmpxchg: @@ -36,25 +50,35 @@ exit: } define void @cmpxchg_and_branch2(ptr %ptr, i32 signext %cmp, i32 signext %val) nounwind { -; CHECK-LABEL: cmpxchg_and_branch2: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: .LBB1_1: # %do_cmpxchg -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB1_3 Depth 2 -; CHECK-NEXT: .LBB1_3: # %do_cmpxchg -; CHECK-NEXT: # Parent Loop BB1_1 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-NEXT: lr.w.aqrl a3, (a0) -; CHECK-NEXT: bne a3, a1, .LBB1_5 -; CHECK-NEXT: # %bb.4: # %do_cmpxchg -; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=2 -; CHECK-NEXT: sc.w.rl a4, a2, (a0) -; CHECK-NEXT: bnez a4, .LBB1_3 -; CHECK-NEXT: .LBB1_5: # %do_cmpxchg -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 -; CHECK-NEXT: beq a3, a1, .LBB1_1 -; CHECK-NEXT: # %bb.2: # %exit -; CHECK-NEXT: ret +; NOZACAS-LABEL: cmpxchg_and_branch2: +; NOZACAS: # %bb.0: # %entry +; NOZACAS-NEXT: .LBB1_1: # %do_cmpxchg +; NOZACAS-NEXT: # =>This Loop Header: Depth=1 +; NOZACAS-NEXT: # Child Loop BB1_3 Depth 2 +; NOZACAS-NEXT: .LBB1_3: # %do_cmpxchg +; NOZACAS-NEXT: # Parent Loop BB1_1 Depth=1 +; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2 +; NOZACAS-NEXT: lr.w.aqrl a3, (a0) +; NOZACAS-NEXT: bne a3, a1, .LBB1_5 +; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB1_3 Depth=2 +; NOZACAS-NEXT: sc.w.rl a4, a2, (a0) +; NOZACAS-NEXT: bnez a4, .LBB1_3 +; NOZACAS-NEXT: .LBB1_5: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB1_1 Depth=1 +; NOZACAS-NEXT: beq a3, a1, .LBB1_1 +; NOZACAS-NEXT: # %bb.2: # %exit +; NOZACAS-NEXT: ret +; +; ZACAS-LABEL: cmpxchg_and_branch2: +; ZACAS: # %bb.0: # %entry +; ZACAS-NEXT: .LBB1_1: # %do_cmpxchg +; ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; ZACAS-NEXT: mv a3, a1 +; ZACAS-NEXT: amocas.w.aqrl a3, a2, (a0) +; ZACAS-NEXT: beq a3, a1, .LBB1_1 +; ZACAS-NEXT: # %bb.2: # %exit +; ZACAS-NEXT: ret entry: br label %do_cmpxchg do_cmpxchg: @@ -96,6 +120,36 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV32IA-NEXT: # %bb.2: # %exit ; RV32IA-NEXT: ret ; +; RV32IA-ZACAS-LABEL: cmpxchg_masked_and_branch1: +; RV32IA-ZACAS: # %bb.0: # %entry +; RV32IA-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-ZACAS-NEXT: slli a4, a0, 3 +; RV32IA-ZACAS-NEXT: li a0, 255 +; RV32IA-ZACAS-NEXT: sll a0, a0, a4 +; RV32IA-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-ZACAS-NEXT: sll a1, a1, a4 +; RV32IA-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-ZACAS-NEXT: sll a2, a2, a4 +; RV32IA-ZACAS-NEXT: .LBB2_1: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: # Child Loop BB2_3 Depth 2 +; RV32IA-ZACAS-NEXT: .LBB2_3: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # Parent Loop BB2_1 Depth=1 +; RV32IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) +; RV32IA-ZACAS-NEXT: and a5, a4, a0 +; RV32IA-ZACAS-NEXT: bne a5, a1, .LBB2_1 +; RV32IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV32IA-ZACAS-NEXT: xor a5, a4, a2 +; RV32IA-ZACAS-NEXT: and a5, a5, a0 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB2_3 +; RV32IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # %bb.2: # %exit +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-LABEL: cmpxchg_masked_and_branch1: ; RV64IA: # %bb.0: # %entry ; RV64IA-NEXT: andi a3, a0, -4 @@ -125,6 +179,36 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV64IA-NEXT: # %bb.5: # %do_cmpxchg ; RV64IA-NEXT: # %bb.2: # %exit ; RV64IA-NEXT: ret +; +; RV64IA-ZACAS-LABEL: cmpxchg_masked_and_branch1: +; RV64IA-ZACAS: # %bb.0: # %entry +; RV64IA-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-ZACAS-NEXT: slli a4, a0, 3 +; RV64IA-ZACAS-NEXT: li a0, 255 +; RV64IA-ZACAS-NEXT: sllw a0, a0, a4 +; RV64IA-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-ZACAS-NEXT: sllw a1, a1, a4 +; RV64IA-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-ZACAS-NEXT: sllw a2, a2, a4 +; RV64IA-ZACAS-NEXT: .LBB2_1: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 +; RV64IA-ZACAS-NEXT: # Child Loop BB2_3 Depth 2 +; RV64IA-ZACAS-NEXT: .LBB2_3: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # Parent Loop BB2_1 Depth=1 +; RV64IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 +; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) +; RV64IA-ZACAS-NEXT: and a5, a4, a0 +; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB2_1 +; RV64IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV64IA-ZACAS-NEXT: xor a5, a4, a2 +; RV64IA-ZACAS-NEXT: and a5, a5, a0 +; RV64IA-ZACAS-NEXT: xor a5, a4, a5 +; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV64IA-ZACAS-NEXT: bnez a5, .LBB2_3 +; RV64IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # %bb.2: # %exit +; RV64IA-ZACAS-NEXT: ret entry: br label %do_cmpxchg do_cmpxchg: @@ -169,6 +253,39 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV32IA-NEXT: # %bb.2: # %exit ; RV32IA-NEXT: ret ; +; RV32IA-ZACAS-LABEL: cmpxchg_masked_and_branch2: +; RV32IA-ZACAS: # %bb.0: # %entry +; RV32IA-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-ZACAS-NEXT: slli a4, a0, 3 +; RV32IA-ZACAS-NEXT: li a0, 255 +; RV32IA-ZACAS-NEXT: sll a0, a0, a4 +; RV32IA-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-ZACAS-NEXT: sll a1, a1, a4 +; RV32IA-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-ZACAS-NEXT: sll a2, a2, a4 +; RV32IA-ZACAS-NEXT: .LBB3_1: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: # Child Loop BB3_3 Depth 2 +; RV32IA-ZACAS-NEXT: .LBB3_3: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # Parent Loop BB3_1 Depth=1 +; RV32IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) +; RV32IA-ZACAS-NEXT: and a5, a4, a0 +; RV32IA-ZACAS-NEXT: bne a5, a1, .LBB3_5 +; RV32IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV32IA-ZACAS-NEXT: xor a5, a4, a2 +; RV32IA-ZACAS-NEXT: and a5, a5, a0 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB3_3 +; RV32IA-ZACAS-NEXT: .LBB3_5: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # in Loop: Header=BB3_1 Depth=1 +; RV32IA-ZACAS-NEXT: and a4, a4, a0 +; RV32IA-ZACAS-NEXT: beq a1, a4, .LBB3_1 +; RV32IA-ZACAS-NEXT: # %bb.2: # %exit +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-LABEL: cmpxchg_masked_and_branch2: ; RV64IA: # %bb.0: # %entry ; RV64IA-NEXT: andi a3, a0, -4 @@ -201,6 +318,39 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV64IA-NEXT: beq a1, a4, .LBB3_1 ; RV64IA-NEXT: # %bb.2: # %exit ; RV64IA-NEXT: ret +; +; RV64IA-ZACAS-LABEL: cmpxchg_masked_and_branch2: +; RV64IA-ZACAS: # %bb.0: # %entry +; RV64IA-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-ZACAS-NEXT: slli a4, a0, 3 +; RV64IA-ZACAS-NEXT: li a0, 255 +; RV64IA-ZACAS-NEXT: sllw a0, a0, a4 +; RV64IA-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-ZACAS-NEXT: sllw a1, a1, a4 +; RV64IA-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-ZACAS-NEXT: sllw a2, a2, a4 +; RV64IA-ZACAS-NEXT: .LBB3_1: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 +; RV64IA-ZACAS-NEXT: # Child Loop BB3_3 Depth 2 +; RV64IA-ZACAS-NEXT: .LBB3_3: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # Parent Loop BB3_1 Depth=1 +; RV64IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 +; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) +; RV64IA-ZACAS-NEXT: and a5, a4, a0 +; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB3_5 +; RV64IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV64IA-ZACAS-NEXT: xor a5, a4, a2 +; RV64IA-ZACAS-NEXT: and a5, a5, a0 +; RV64IA-ZACAS-NEXT: xor a5, a4, a5 +; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV64IA-ZACAS-NEXT: bnez a5, .LBB3_3 +; RV64IA-ZACAS-NEXT: .LBB3_5: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # in Loop: Header=BB3_1 Depth=1 +; RV64IA-ZACAS-NEXT: and a4, a4, a0 +; RV64IA-ZACAS-NEXT: beq a1, a4, .LBB3_1 +; RV64IA-ZACAS-NEXT: # %bb.2: # %exit +; RV64IA-ZACAS-NEXT: ret entry: br label %do_cmpxchg do_cmpxchg: @@ -212,25 +362,35 @@ exit: } define void @cmpxchg_and_irrelevant_branch(ptr %ptr, i32 signext %cmp, i32 signext %val, i1 zeroext %bool) nounwind { -; CHECK-LABEL: cmpxchg_and_irrelevant_branch: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: .LBB4_1: # %do_cmpxchg -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB4_3 Depth 2 -; CHECK-NEXT: .LBB4_3: # %do_cmpxchg -; CHECK-NEXT: # Parent Loop BB4_1 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-NEXT: lr.w.aqrl a4, (a0) -; CHECK-NEXT: bne a4, a1, .LBB4_5 -; CHECK-NEXT: # %bb.4: # %do_cmpxchg -; CHECK-NEXT: # in Loop: Header=BB4_3 Depth=2 -; CHECK-NEXT: sc.w.rl a5, a2, (a0) -; CHECK-NEXT: bnez a5, .LBB4_3 -; CHECK-NEXT: .LBB4_5: # %do_cmpxchg -; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 -; CHECK-NEXT: beqz a3, .LBB4_1 -; CHECK-NEXT: # %bb.2: # %exit -; CHECK-NEXT: ret +; NOZACAS-LABEL: cmpxchg_and_irrelevant_branch: +; NOZACAS: # %bb.0: # %entry +; NOZACAS-NEXT: .LBB4_1: # %do_cmpxchg +; NOZACAS-NEXT: # =>This Loop Header: Depth=1 +; NOZACAS-NEXT: # Child Loop BB4_3 Depth 2 +; NOZACAS-NEXT: .LBB4_3: # %do_cmpxchg +; NOZACAS-NEXT: # Parent Loop BB4_1 Depth=1 +; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2 +; NOZACAS-NEXT: lr.w.aqrl a4, (a0) +; NOZACAS-NEXT: bne a4, a1, .LBB4_5 +; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB4_3 Depth=2 +; NOZACAS-NEXT: sc.w.rl a5, a2, (a0) +; NOZACAS-NEXT: bnez a5, .LBB4_3 +; NOZACAS-NEXT: .LBB4_5: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB4_1 Depth=1 +; NOZACAS-NEXT: beqz a3, .LBB4_1 +; NOZACAS-NEXT: # %bb.2: # %exit +; NOZACAS-NEXT: ret +; +; ZACAS-LABEL: cmpxchg_and_irrelevant_branch: +; ZACAS: # %bb.0: # %entry +; ZACAS-NEXT: .LBB4_1: # %do_cmpxchg +; ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; ZACAS-NEXT: mv a4, a1 +; ZACAS-NEXT: amocas.w.aqrl a4, a2, (a0) +; ZACAS-NEXT: beqz a3, .LBB4_1 +; ZACAS-NEXT: # %bb.2: # %exit +; ZACAS-NEXT: ret entry: br label %do_cmpxchg do_cmpxchg: diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll index 46ed01b11584..b3c9224646ed 100644 --- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll @@ -3,14 +3,22 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-WMO-ZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-TSO-ZACAS %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-WMO-ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO-ZACAS %s define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic: @@ -125,6 +133,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-WMO-NEXT: .LBB1_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a4, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB1_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB1_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB1_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -148,6 +179,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-TSO-NEXT: .LBB1_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a4, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB1_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB1_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -184,6 +238,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-WMO-NEXT: .LBB1_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: li a4, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB1_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB1_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB1_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -206,6 +283,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-TSO-NEXT: bnez a5, .LBB1_1 ; RV64IA-TSO-NEXT: .LBB1_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: li a4, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB1_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB1_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire monotonic ret void } @@ -247,6 +347,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-WMO-NEXT: .LBB2_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a4, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB2_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB2_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB2_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i8_acquire_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -270,6 +393,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-TSO-NEXT: .LBB2_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a4, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB2_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB2_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_acquire_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -306,6 +452,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-WMO-NEXT: .LBB2_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: li a4, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB2_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB2_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB2_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -328,6 +497,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-TSO-NEXT: bnez a5, .LBB2_1 ; RV64IA-TSO-NEXT: .LBB2_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: li a4, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB2_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB2_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire ret void } @@ -369,6 +561,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-WMO-NEXT: .LBB3_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a4, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB3_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB3_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB3_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i8_release_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -392,6 +607,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-TSO-NEXT: .LBB3_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a4, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB3_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB3_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_release_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -428,6 +666,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-WMO-NEXT: .LBB3_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: li a4, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB3_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB3_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB3_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i8_release_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -450,6 +711,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-TSO-NEXT: bnez a5, .LBB3_1 ; RV64IA-TSO-NEXT: .LBB3_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: li a4, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB3_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB3_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic ret void } @@ -491,6 +775,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-WMO-NEXT: .LBB4_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a4, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB4_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB4_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB4_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i8_release_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -514,6 +821,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-TSO-NEXT: .LBB4_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a4, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB4_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB4_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB4_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_release_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -550,6 +880,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-WMO-NEXT: .LBB4_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: li a4, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB4_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB4_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB4_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i8_release_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -572,6 +925,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-TSO-NEXT: bnez a5, .LBB4_1 ; RV64IA-TSO-NEXT: .LBB4_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: li a4, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB4_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB4_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB4_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire ret void } @@ -613,6 +989,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-WMO-NEXT: .LBB5_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a4, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB5_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB5_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB5_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -636,6 +1035,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-TSO-NEXT: .LBB5_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a4, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB5_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB5_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB5_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -672,6 +1094,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-WMO-NEXT: .LBB5_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: li a4, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB5_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB5_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB5_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -694,6 +1139,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-TSO-NEXT: bnez a5, .LBB5_1 ; RV64IA-TSO-NEXT: .LBB5_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: li a4, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB5_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB5_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB5_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic ret void } @@ -735,6 +1203,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-WMO-NEXT: .LBB6_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a4, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB6_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB6_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB6_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -758,6 +1249,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV32IA-TSO-NEXT: .LBB6_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a4, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB6_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB6_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB6_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -794,6 +1308,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-WMO-NEXT: .LBB6_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: li a4, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB6_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB6_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB6_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -816,6 +1353,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; RV64IA-TSO-NEXT: bnez a5, .LBB6_1 ; RV64IA-TSO-NEXT: .LBB6_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: li a4, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB6_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB6_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB6_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire ret void } @@ -1164,6 +1724,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32IA-WMO-NEXT: .LBB11_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB11_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB11_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB11_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -1188,6 +1772,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32IA-TSO-NEXT: .LBB11_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB11_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB11_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB11_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1225,6 +1833,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64IA-WMO-NEXT: .LBB11_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB11_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB11_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB11_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -1248,6 +1880,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB11_1 ; RV64IA-TSO-NEXT: .LBB11_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB11_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB11_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB11_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire monotonic ret void } @@ -1290,6 +1946,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32IA-WMO-NEXT: .LBB12_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB12_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB12_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB12_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i16_acquire_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -1314,6 +1994,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32IA-TSO-NEXT: .LBB12_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB12_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB12_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB12_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_acquire_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1351,6 +2055,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64IA-WMO-NEXT: .LBB12_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB12_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB12_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB12_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -1374,6 +2102,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB12_1 ; RV64IA-TSO-NEXT: .LBB12_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB12_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB12_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB12_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire ret void } @@ -1416,6 +2168,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32IA-WMO-NEXT: .LBB13_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB13_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB13_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB13_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i16_release_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -1440,6 +2216,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32IA-TSO-NEXT: .LBB13_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB13_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB13_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB13_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_release_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1477,6 +2277,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64IA-WMO-NEXT: .LBB13_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB13_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB13_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB13_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i16_release_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -1500,6 +2324,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB13_1 ; RV64IA-TSO-NEXT: .LBB13_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB13_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB13_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB13_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic ret void } @@ -1542,6 +2390,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32IA-WMO-NEXT: .LBB14_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB14_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB14_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB14_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i16_release_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -1566,6 +2438,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32IA-TSO-NEXT: .LBB14_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB14_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB14_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB14_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_release_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1603,6 +2499,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64IA-WMO-NEXT: .LBB14_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB14_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB14_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB14_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i16_release_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -1626,6 +2546,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB14_1 ; RV64IA-TSO-NEXT: .LBB14_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB14_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB14_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB14_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire ret void } @@ -1668,6 +2612,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32IA-WMO-NEXT: .LBB15_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB15_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB15_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB15_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -1692,6 +2660,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV32IA-TSO-NEXT: .LBB15_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB15_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB15_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB15_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1729,6 +2721,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64IA-WMO-NEXT: .LBB15_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB15_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB15_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB15_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -1752,6 +2768,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB15_1 ; RV64IA-TSO-NEXT: .LBB15_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB15_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB15_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB15_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic ret void } @@ -1794,6 +2834,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32IA-WMO-NEXT: .LBB16_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB16_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB16_1 +; RV32IA-WMO-ZACAS-NEXT: .LBB16_3: +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: andi a3, a0, -4 @@ -1818,6 +2882,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV32IA-TSO-NEXT: .LBB16_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB16_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB16_1 +; RV32IA-TSO-ZACAS-NEXT: .LBB16_3: +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1855,6 +2943,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64IA-WMO-NEXT: .LBB16_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-WMO-ZACAS-NEXT: lui a4, 16 +; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3) +; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB16_3 +; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3) +; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB16_1 +; RV64IA-WMO-ZACAS-NEXT: .LBB16_3: +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: andi a3, a0, -4 @@ -1878,6 +2990,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB16_1 ; RV64IA-TSO-NEXT: .LBB16_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4 +; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV64IA-TSO-ZACAS-NEXT: lui a4, 16 +; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1 +; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0 +; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0 +; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3) +; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5 +; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB16_3 +; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0 +; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5 +; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4 +; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3) +; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB16_1 +; RV64IA-TSO-ZACAS-NEXT: .LBB16_3: +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire ret void } @@ -2130,16 +3266,32 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: cmpxchg_i32_monotonic_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a0) -; RV32IA-NEXT: bne a3, a1, .LBB20_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 -; RV32IA-NEXT: sc.w a4, a2, (a0) -; RV32IA-NEXT: bnez a4, .LBB20_1 -; RV32IA-NEXT: .LBB20_3: -; RV32IA-NEXT: ret +; RV32IA-WMO-LABEL: cmpxchg_i32_monotonic_monotonic: +; RV32IA-WMO: # %bb.0: +; RV32IA-WMO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NEXT: lr.w a3, (a0) +; RV32IA-WMO-NEXT: bne a3, a1, .LBB20_3 +; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 +; RV32IA-WMO-NEXT: sc.w a4, a2, (a0) +; RV32IA-WMO-NEXT: bnez a4, .LBB20_1 +; RV32IA-WMO-NEXT: .LBB20_3: +; RV32IA-WMO-NEXT: ret +; +; RV32IA-ZACAS-LABEL: cmpxchg_i32_monotonic_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-ZACAS-NEXT: ret +; +; RV32IA-TSO-LABEL: cmpxchg_i32_monotonic_monotonic: +; RV32IA-TSO: # %bb.0: +; RV32IA-TSO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NEXT: lr.w a3, (a0) +; RV32IA-TSO-NEXT: bne a3, a1, .LBB20_3 +; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 +; RV32IA-TSO-NEXT: sc.w a4, a2, (a0) +; RV32IA-TSO-NEXT: bnez a4, .LBB20_1 +; RV32IA-TSO-NEXT: .LBB20_3: +; RV32IA-TSO-NEXT: ret ; ; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV64I: # %bb.0: @@ -2154,17 +3306,35 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic: -; RV64IA: # %bb.0: -; RV64IA-NEXT: sext.w a1, a1 -; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB20_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 -; RV64IA-NEXT: sc.w a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB20_1 -; RV64IA-NEXT: .LBB20_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i32_monotonic_monotonic: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: sext.w a1, a1 +; RV64IA-WMO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.w a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB20_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 +; RV64IA-WMO-NEXT: sc.w a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB20_1 +; RV64IA-WMO-NEXT: .LBB20_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-ZACAS-LABEL: cmpxchg_i32_monotonic_monotonic: +; RV64IA-ZACAS: # %bb.0: +; RV64IA-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i32_monotonic_monotonic: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: sext.w a1, a1 +; RV64IA-TSO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.w a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB20_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 +; RV64IA-TSO-NEXT: sc.w a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB20_1 +; RV64IA-TSO-NEXT: .LBB20_3: +; RV64IA-TSO-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic ret void } @@ -2194,6 +3364,11 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32IA-WMO-NEXT: .LBB21_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i32_acquire_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 @@ -2205,6 +3380,11 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32IA-TSO-NEXT: .LBB21_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2230,6 +3410,12 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64IA-WMO-NEXT: .LBB21_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: sext.w a1, a1 @@ -2241,6 +3427,12 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB21_1 ; RV64IA-TSO-NEXT: .LBB21_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire monotonic ret void } @@ -2270,6 +3462,11 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32IA-WMO-NEXT: .LBB22_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i32_acquire_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 @@ -2281,6 +3478,11 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32IA-TSO-NEXT: .LBB22_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_acquire_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2306,6 +3508,12 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64IA-WMO-NEXT: .LBB22_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: sext.w a1, a1 @@ -2317,6 +3525,12 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB22_1 ; RV64IA-TSO-NEXT: .LBB22_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire acquire ret void } @@ -2346,6 +3560,11 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32IA-WMO-NEXT: .LBB23_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.rl a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i32_release_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 @@ -2357,6 +3576,11 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32IA-TSO-NEXT: .LBB23_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_release_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2382,6 +3606,12 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64IA-WMO-NEXT: .LBB23_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.rl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i32_release_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: sext.w a1, a1 @@ -2393,6 +3623,12 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB23_1 ; RV64IA-TSO-NEXT: .LBB23_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic ret void } @@ -2422,6 +3658,11 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32IA-WMO-NEXT: .LBB24_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i32_release_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 @@ -2433,6 +3674,11 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32IA-TSO-NEXT: .LBB24_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_release_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2458,6 +3704,12 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64IA-WMO-NEXT: .LBB24_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i32_release_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: sext.w a1, a1 @@ -2469,6 +3721,12 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB24_1 ; RV64IA-TSO-NEXT: .LBB24_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release acquire ret void } @@ -2498,6 +3756,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32IA-WMO-NEXT: .LBB25_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 @@ -2509,6 +3772,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32IA-TSO-NEXT: .LBB25_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2534,6 +3802,12 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64IA-WMO-NEXT: .LBB25_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: sext.w a1, a1 @@ -2545,6 +3819,12 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB25_1 ; RV64IA-TSO-NEXT: .LBB25_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic ret void } @@ -2574,6 +3854,11 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32IA-WMO-NEXT: .LBB26_3: ; RV32IA-WMO-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; ; RV32IA-TSO-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV32IA-TSO: # %bb.0: ; RV32IA-TSO-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 @@ -2585,6 +3870,11 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32IA-TSO-NEXT: .LBB26_3: ; RV32IA-TSO-NEXT: ret ; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2610,6 +3900,12 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64IA-WMO-NEXT: .LBB26_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: sext.w a1, a1 @@ -2621,6 +3917,12 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB26_1 ; RV64IA-TSO-NEXT: .LBB26_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel acquire ret void } @@ -2639,16 +3941,37 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a0) -; RV32IA-NEXT: bne a3, a1, .LBB27_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a4, a2, (a0) -; RV32IA-NEXT: bnez a4, .LBB27_1 -; RV32IA-NEXT: .LBB27_3: -; RV32IA-NEXT: ret +; RV32IA-WMO-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV32IA-WMO: # %bb.0: +; RV32IA-WMO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NEXT: lr.w.aqrl a3, (a0) +; RV32IA-WMO-NEXT: bne a3, a1, .LBB27_3 +; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 +; RV32IA-WMO-NEXT: sc.w.rl a4, a2, (a0) +; RV32IA-WMO-NEXT: bnez a4, .LBB27_1 +; RV32IA-WMO-NEXT: .LBB27_3: +; RV32IA-WMO-NEXT: ret +; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV32IA-TSO: # %bb.0: +; RV32IA-TSO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NEXT: lr.w.aqrl a3, (a0) +; RV32IA-TSO-NEXT: bne a3, a1, .LBB27_3 +; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 +; RV32IA-TSO-NEXT: sc.w.rl a4, a2, (a0) +; RV32IA-TSO-NEXT: bnez a4, .LBB27_1 +; RV32IA-TSO-NEXT: .LBB27_3: +; RV32IA-TSO-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret ; ; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64I: # %bb.0: @@ -2663,17 +3986,41 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic: -; RV64IA: # %bb.0: -; RV64IA-NEXT: sext.w a1, a1 -; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB27_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB27_1 -; RV64IA-NEXT: .LBB27_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: sext.w a1, a1 +; RV64IA-WMO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.w.aqrl a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB27_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 +; RV64IA-WMO-NEXT: sc.w.rl a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB27_1 +; RV64IA-WMO-NEXT: .LBB27_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: sext.w a1, a1 +; RV64IA-TSO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.w.aqrl a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB27_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 +; RV64IA-TSO-NEXT: sc.w.rl a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB27_1 +; RV64IA-TSO-NEXT: .LBB27_3: +; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic ret void } @@ -2692,16 +4039,37 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire: -; RV32IA: # %bb.0: -; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a0) -; RV32IA-NEXT: bne a3, a1, .LBB28_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a4, a2, (a0) -; RV32IA-NEXT: bnez a4, .LBB28_1 -; RV32IA-NEXT: .LBB28_3: -; RV32IA-NEXT: ret +; RV32IA-WMO-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV32IA-WMO: # %bb.0: +; RV32IA-WMO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NEXT: lr.w.aqrl a3, (a0) +; RV32IA-WMO-NEXT: bne a3, a1, .LBB28_3 +; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 +; RV32IA-WMO-NEXT: sc.w.rl a4, a2, (a0) +; RV32IA-WMO-NEXT: bnez a4, .LBB28_1 +; RV32IA-WMO-NEXT: .LBB28_3: +; RV32IA-WMO-NEXT: ret +; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV32IA-TSO: # %bb.0: +; RV32IA-TSO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NEXT: lr.w.aqrl a3, (a0) +; RV32IA-TSO-NEXT: bne a3, a1, .LBB28_3 +; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 +; RV32IA-TSO-NEXT: sc.w.rl a4, a2, (a0) +; RV32IA-TSO-NEXT: bnez a4, .LBB28_1 +; RV32IA-TSO-NEXT: .LBB28_3: +; RV32IA-TSO-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret ; ; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64I: # %bb.0: @@ -2716,17 +4084,41 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire: -; RV64IA: # %bb.0: -; RV64IA-NEXT: sext.w a1, a1 -; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB28_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB28_1 -; RV64IA-NEXT: .LBB28_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: sext.w a1, a1 +; RV64IA-WMO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.w.aqrl a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB28_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 +; RV64IA-WMO-NEXT: sc.w.rl a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB28_1 +; RV64IA-WMO-NEXT: .LBB28_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: sext.w a1, a1 +; RV64IA-TSO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.w.aqrl a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB28_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 +; RV64IA-TSO-NEXT: sc.w.rl a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB28_1 +; RV64IA-TSO-NEXT: .LBB28_3: +; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire ret void } @@ -2745,16 +4137,37 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a0) -; RV32IA-NEXT: bne a3, a1, .LBB29_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a4, a2, (a0) -; RV32IA-NEXT: bnez a4, .LBB29_1 -; RV32IA-NEXT: .LBB29_3: -; RV32IA-NEXT: ret +; RV32IA-WMO-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV32IA-WMO: # %bb.0: +; RV32IA-WMO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NEXT: lr.w.aqrl a3, (a0) +; RV32IA-WMO-NEXT: bne a3, a1, .LBB29_3 +; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 +; RV32IA-WMO-NEXT: sc.w.rl a4, a2, (a0) +; RV32IA-WMO-NEXT: bnez a4, .LBB29_1 +; RV32IA-WMO-NEXT: .LBB29_3: +; RV32IA-WMO-NEXT: ret +; +; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV32IA-TSO: # %bb.0: +; RV32IA-TSO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NEXT: lr.w.aqrl a3, (a0) +; RV32IA-TSO-NEXT: bne a3, a1, .LBB29_3 +; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 +; RV32IA-TSO-NEXT: sc.w.rl a4, a2, (a0) +; RV32IA-TSO-NEXT: bnez a4, .LBB29_1 +; RV32IA-TSO-NEXT: .LBB29_3: +; RV32IA-TSO-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV32IA-TSO-ZACAS-NEXT: ret ; ; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64I: # %bb.0: @@ -2769,17 +4182,41 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: -; RV64IA: # %bb.0: -; RV64IA-NEXT: sext.w a1, a1 -; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB29_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB29_1 -; RV64IA-NEXT: .LBB29_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: sext.w a1, a1 +; RV64IA-WMO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.w.aqrl a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB29_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 +; RV64IA-WMO-NEXT: sc.w.rl a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB29_1 +; RV64IA-WMO-NEXT: .LBB29_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: sext.w a1, a1 +; RV64IA-TSO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.w.aqrl a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB29_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 +; RV64IA-TSO-NEXT: sc.w.rl a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB29_1 +; RV64IA-TSO-NEXT: .LBB29_3: +; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 +; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst ret void } @@ -2830,16 +4267,32 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounw ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic: -; RV64IA: # %bb.0: -; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.d a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB30_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1 -; RV64IA-NEXT: sc.d a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB30_1 -; RV64IA-NEXT: .LBB30_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i64_monotonic_monotonic: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.d a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB30_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1 +; RV64IA-WMO-NEXT: sc.d a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB30_1 +; RV64IA-WMO-NEXT: .LBB30_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-ZACAS-LABEL: cmpxchg_i64_monotonic_monotonic: +; RV64IA-ZACAS: # %bb.0: +; RV64IA-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i64_monotonic_monotonic: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.d a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB30_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1 +; RV64IA-TSO-NEXT: sc.d a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB30_1 +; RV64IA-TSO-NEXT: .LBB30_3: +; RV64IA-TSO-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val monotonic monotonic ret void } @@ -2903,6 +4356,11 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64IA-WMO-NEXT: .LBB31_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acquire_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 @@ -2913,6 +4371,11 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB31_1 ; RV64IA-TSO-NEXT: .LBB31_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acquire_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire monotonic ret void } @@ -2976,6 +4439,11 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64IA-WMO-NEXT: .LBB32_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acquire_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 @@ -2986,6 +4454,11 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB32_1 ; RV64IA-TSO-NEXT: .LBB32_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acquire_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire acquire ret void } @@ -3049,6 +4522,11 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64IA-WMO-NEXT: .LBB33_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_release_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.rl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i64_release_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 @@ -3059,6 +4537,11 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB33_1 ; RV64IA-TSO-NEXT: .LBB33_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_release_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release monotonic ret void } @@ -3122,6 +4605,11 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64IA-WMO-NEXT: .LBB34_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_release_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i64_release_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 @@ -3132,6 +4620,11 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB34_1 ; RV64IA-TSO-NEXT: .LBB34_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_release_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release acquire ret void } @@ -3195,6 +4688,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64IA-WMO-NEXT: .LBB35_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acq_rel_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 @@ -3205,6 +4703,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64IA-TSO-NEXT: bnez a4, .LBB35_1 ; RV64IA-TSO-NEXT: .LBB35_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acq_rel_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel monotonic ret void } @@ -3268,6 +4771,11 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64IA-WMO-NEXT: .LBB36_3: ; RV64IA-WMO-NEXT: ret ; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acq_rel_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; ; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV64IA-TSO: # %bb.0: ; RV64IA-TSO-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 @@ -3278,6 +4786,11 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64IA-TSO-NEXT: bnez a4, .LBB36_1 ; RV64IA-TSO-NEXT: .LBB36_3: ; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acq_rel_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel acquire ret void } @@ -3330,16 +4843,37 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic: -; RV64IA: # %bb.0: -; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.d.aqrl a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB37_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 -; RV64IA-NEXT: sc.d.rl a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB37_1 -; RV64IA-NEXT: .LBB37_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i64_seq_cst_monotonic: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.d.aqrl a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB37_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 +; RV64IA-WMO-NEXT: sc.d.rl a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB37_1 +; RV64IA-WMO-NEXT: .LBB37_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_seq_cst_monotonic: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_monotonic: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.d.aqrl a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB37_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 +; RV64IA-TSO-NEXT: sc.d.rl a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB37_1 +; RV64IA-TSO-NEXT: .LBB37_3: +; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_seq_cst_monotonic: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic ret void } @@ -3392,16 +4926,37 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire: -; RV64IA: # %bb.0: -; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.d.aqrl a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB38_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 -; RV64IA-NEXT: sc.d.rl a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB38_1 -; RV64IA-NEXT: .LBB38_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i64_seq_cst_acquire: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.d.aqrl a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB38_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 +; RV64IA-WMO-NEXT: sc.d.rl a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB38_1 +; RV64IA-WMO-NEXT: .LBB38_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_seq_cst_acquire: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_acquire: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.d.aqrl a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB38_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 +; RV64IA-TSO-NEXT: sc.d.rl a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB38_1 +; RV64IA-TSO-NEXT: .LBB38_3: +; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_seq_cst_acquire: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire ret void } @@ -3454,16 +5009,37 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst: -; RV64IA: # %bb.0: -; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.d.aqrl a3, (a0) -; RV64IA-NEXT: bne a3, a1, .LBB39_3 -; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 -; RV64IA-NEXT: sc.d.rl a4, a2, (a0) -; RV64IA-NEXT: bnez a4, .LBB39_1 -; RV64IA-NEXT: .LBB39_3: -; RV64IA-NEXT: ret +; RV64IA-WMO-LABEL: cmpxchg_i64_seq_cst_seq_cst: +; RV64IA-WMO: # %bb.0: +; RV64IA-WMO-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-WMO-NEXT: lr.d.aqrl a3, (a0) +; RV64IA-WMO-NEXT: bne a3, a1, .LBB39_3 +; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 +; RV64IA-WMO-NEXT: sc.d.rl a4, a2, (a0) +; RV64IA-WMO-NEXT: bnez a4, .LBB39_1 +; RV64IA-WMO-NEXT: .LBB39_3: +; RV64IA-WMO-NEXT: ret +; +; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_seq_cst_seq_cst: +; RV64IA-WMO-ZACAS: # %bb.0: +; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0) +; RV64IA-WMO-ZACAS-NEXT: ret +; +; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_seq_cst: +; RV64IA-TSO: # %bb.0: +; RV64IA-TSO-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 +; RV64IA-TSO-NEXT: lr.d.aqrl a3, (a0) +; RV64IA-TSO-NEXT: bne a3, a1, .LBB39_3 +; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 +; RV64IA-TSO-NEXT: sc.d.rl a4, a2, (a0) +; RV64IA-TSO-NEXT: bnez a4, .LBB39_1 +; RV64IA-TSO-NEXT: .LBB39_3: +; RV64IA-TSO-NEXT: ret +; +; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_seq_cst_seq_cst: +; RV64IA-TSO-ZACAS: # %bb.0: +; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0) +; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst ret void } -- GitLab From 183eae0643719aac75ef689ee295b697d5367245 Mon Sep 17 00:00:00 2001 From: Chris B Date: Wed, 10 Jan 2024 14:12:30 -0600 Subject: [PATCH 378/652] [HLSL][Docs] Add documentation for HLSL functions (#75397) This adds a new document that covers the HLSL approach to function calls and parameter semantics. At time of writing this document is a proposal for the implementation. --- clang/docs/HLSL/FunctionCalls.rst | 321 ++++++++++++++++++++++++++++++ clang/docs/HLSL/HLSLDocs.rst | 1 + 2 files changed, 322 insertions(+) create mode 100644 clang/docs/HLSL/FunctionCalls.rst diff --git a/clang/docs/HLSL/FunctionCalls.rst b/clang/docs/HLSL/FunctionCalls.rst new file mode 100644 index 000000000000..996ddd6944b1 --- /dev/null +++ b/clang/docs/HLSL/FunctionCalls.rst @@ -0,0 +1,321 @@ +=================== +HLSL Function Calls +=================== + +.. contents:: + :local: + +Introduction +============ + +This document describes the design and implementation of HLSL's function call +semantics in Clang. This includes details related to argument conversion and +parameter lifetimes. + +This document does not seek to serve as official documentation for HLSL's +call semantics, but does provide an overview to assist a reader. The +authoritative documentation for HLSL's language semantics is the `draft language +specification `_. + +Argument Semantics +================== + +In HLSL, all function arguments are passed by value in and out of functions. +HLSL has 3 keywords which denote the parameter semantics (``in``, ``out`` and +``inout``). In a function declaration a parameter may be annotated any of the +following ways: + +#. - denotes input +#. ``in`` - denotes input +#. ``out`` - denotes output +#. ``in out`` - denotes input and output +#. ``out in`` - denotes input and output +#. ``inout`` - denotes input and output + +Parameters that are exclusively input behave like C/C++ parameters that are +passed by value. + +For parameters that are output (or input and output), a temporary value is +created in the caller. The temporary value is then passed by-address. For +output-only parameters, the temporary is uninitialized when passed (if the +parameter is not explicitly initialized inside the function an undefined value +is stored back to the argument expression). For parameters that are both input +and output, the temporary is initialized from the lvalue argument expression +through implicit or explicit casting from the lvalue argument type to the +parameter type. + +On return of the function, the values of any parameter temporaries are written +back to the argument expression through an inverted conversion sequence (if an +``out`` parameter was not initialized in the function, the uninitialized value +may be written back). + +Parameters of constant-sized array type are also passed with value semantics. +This requires input parameters of arrays to construct temporaries and the +temporaries go through array-to-pointer decay when initializing parameters. + +Implementations are allowed to avoid unnecessary temporaries, and HLSL's strict +no-alias rules can enable some trivial optimizations. + +Array Temporaries +----------------- + +Given the following example: + +.. code-block:: c++ + + void fn(float a[4]) { + a[0] = a[1] + a[2] + a[3]; + } + + float4 main() : SV_Target { + float arr[4] = {1, 1, 1, 1}; + fn(arr); + return float4(arr[0], arr[1], arr[2], arr[3]); + } + +In C or C++, the array parameter decays to a pointer, so after the call to +``fn``, the value of ``arr[0]`` is ``3``. In HLSL, the array is passed by value, +so modifications inside ``fn`` do not propagate out. + +.. note:: + + DXC may pass unsized arrays directly as decayed pointers, which is an + unfortunate behavior divergence. + +Out Parameter Temporaries +------------------------- + +.. code-block:: c++ + + void Init(inout int X, inout int Y) { + Y = 2; + X = 1; + } + + void main() { + int V; + Init(V, V); // MSVC (or clang-cl) V == 2, Clang V == 1 + } + +In the above example the ``Init`` function's behavior depends on the C++ +implementation. C++ does not define the order in which parameters are +initialized or destroyed. In MSVC and Clang's MSVC compatibility mode, arguments +are emitted right-to-left and destroyed left-to-right. This means that the +parameter initialization and destruction occurs in the order: {``Y``, ``X``, +``~X``, ``~Y``}. This causes the write-back of the value of ``Y`` to occur last, +so the resulting value of ``V`` is ``2``. In the Itanium C++ ABI, the parameter +ordering is reversed, so the initialization and destruction occurs in the order: +{``X``, ``Y``, ``~Y``, ``X``}. This causes the write-back of the value ``X`` to +occur last, resulting in the value of ``V`` being set to ``1``. + +.. code-block:: c++ + + void Trunc(inout int3 V) { } + + + void main() { + float3 F = {1.5, 2.6, 3.3}; + Trunc(F); // F == {1.0, 2.0, 3.0} + } + +In the above example, the argument expression ``F`` undergoes element-wise +conversion from a float vector to an integer vector to create a temporary +``int3``. On expiration the temporary undergoes elementwise conversion back to +the floating point vector type ``float3``. This results in an implicit +element-wise conversion of the vector even if the value is unused in the +function (effectively truncating the floating point values). + + +.. code-block:: c++ + + void UB(out int X) {} + + void main() { + int X = 7; + UB(X); // X is undefined! + } + +In this example an initialized value is passed to an ``out`` parameter. +Parameters marked ``out`` are not initialized by the argument expression or +implicitly by the function. They must be explicitly initialized. In this case +the argument is not initialized in the function so the temporary is still +uninitialized when it is copied back to the argument expression. This is +undefined behavior in HLSL, and any use of the argument after the call is a use +of an undefined value which may be illegal in the target (DXIL programs with +used or potentially used ``undef`` or ``poison`` values fail validation). + +Clang Implementation +==================== + +.. note:: + + The implementation described here is a proposal. It has not yet been fully + implemented, so the current state of Clang's sources may not reflect this + design. A prototype implementation was built on DXC which is Clang-3.7 based. + The prototype can be found + `here `_. A lot + of the changes in the prototype implementation are restoring Clang-3.7 code + that was previously modified to its original state. + +The implementation in clang depends on two new AST nodes and minor extensions to +Clang's existing support for Objective-C write-back arguments. The goal of this +design is to capture the semantic details of HLSL function calls in the AST, and +minimize the amount of magic that needs to occur during IR generation. + +The two new AST nodes are ``HLSLArrayTemporaryExpr`` and ``HLSLOutParamExpr``, +which respectively represent the temporaries used for passing arrays by value +and the temporaries created for function outputs. + +Array Temporaries +----------------- + +The ``HLSLArrayTemporaryExpr`` represents temporary values for input +constant-sized array arguments. This applies for all constant-sized array +arguments regardless of whether or not the parameter is constant-sized or +unsized. + +.. code-block:: c++ + + void SizedArray(float a[4]); + void UnsizedArray(float a[]); + + void main() { + float arr[4] = {1, 1, 1, 1}; + SizedArray(arr); + UnsizedArray(arr); + } + +In the example above, the following AST is generated for the call to +``SizedArray``: + +.. code-block:: text + + CallExpr 'void' + |-ImplicitCastExpr 'void (*)(float [4])' + | `-DeclRefExpr 'void (float [4])' lvalue Function 'SizedArray' 'void (float [4])' + `-HLSLArrayTemporaryExpr 'float [4]' + `-DeclRefExpr 'float [4]' lvalue Var 'arr' 'float [4]' + +In the example above, the following AST is generated for the call to +``UnsizedArray``: + +.. code-block:: text + + CallExpr 'void' + |-ImplicitCastExpr 'void (*)(float [])' + | `-DeclRefExpr 'void (float [])' lvalue Function 'UnsizedArray' 'void (float [])' + `-HLSLArrayTemporaryExpr 'float [4]' + `-DeclRefExpr 'float [4]' lvalue Var 'arr' 'float [4]' + +In both of these cases the argument expression is of known array size so we can +initialize an appropriately sized temporary. + +It is illegal in HLSL to convert an unsized array to a sized array: + +.. code-block:: c++ + + void SizedArray(float a[4]); + void UnsizedArray(float a[]) { + SizedArray(a); // Cannot convert float[] to float[4] + } + +When converting a sized array to an unsized array, an array temporary can also +be inserted. Given the following code: + +.. code-block:: c++ + + void UnsizedArray(float a[]); + void SizedArray(float a[4]) { + UnsizedArray(a); + } + +An expected AST should be something like: + +.. code-block:: text + + CallExpr 'void' + |-ImplicitCastExpr 'void (*)(float [])' + | `-DeclRefExpr 'void (float [])' lvalue Function 'UnsizedArray' 'void (float [])' + `-HLSLArrayTemporaryExpr 'float [4]' + `-DeclRefExpr 'float [4]' lvalue Var 'arr' 'float [4]' + +Out Parameter Temporaries +------------------------- + +Output parameters are defined in HLSL as *casting expiring values* (cx-values), +which is a term made up for HLSL. A cx-value is a temporary value which may be +the result of a cast, and stores its value back to an lvalue when the value +expires. + +To represent this concept in Clang we introduce a new ``HLSLOutParamExpr``. An +``HLSLOutParamExpr`` has two forms, one with a single sub-expression and one +with two sub-expressions. + +The single sub-expression form is used when the argument expression and the +function parameter are the same type, so no cast is required. As in this +example: + +.. code-block:: c++ + + void Init(inout int X) { + X = 1; + } + + void main() { + int V; + Init(V); + } + +The expected AST formulation for this code would be something like: + +.. code-block:: text + + CallExpr 'void' + |-ImplicitCastExpr 'void (*)(int &)' + | `-DeclRefExpr 'void (int &)' lvalue Function 'Init' 'void (int &)' + |-HLSLOutParamExpr 'int' lvalue inout + `-DeclRefExpr 'int' lvalue Var 'V' 'int' + +The ``HLSLOutParamExpr`` captures that the value is ``inout`` vs ``out`` to +denote whether or not the temporary is initialized from the sub-expression. If +no casting is required the sub-expression denotes the lvalue expression that the +cx-value will be copied to when the value expires. + +The two sub-expression form of the AST node is required when the argument type +is not the same as the parameter type. Given this example: + +.. code-block:: c++ + + void Trunc(inout int3 V) { } + + + void main() { + float3 F = {1.5, 2.6, 3.3}; + Trunc(F); + } + +For this case the ``HLSLOutParamExpr`` will have sub-expressions to record both +casting expression sequences for the initialization and write back: + +.. code-block:: text + + -CallExpr 'void' + |-ImplicitCastExpr 'void (*)(int3 &)' + | `-DeclRefExpr 'void (int3 &)' lvalue Function 'inc_i32' 'void (int3 &)' + `-HLSLOutParamExpr 'int3' lvalue inout + |-ImplicitCastExpr 'float3' + | `-ImplicitCastExpr 'int3' + | `-OpaqueValueExpr 'int3' lvalue + `-ImplicitCastExpr 'int3' + `-ImplicitCastExpr 'float3' + `-DeclRefExpr 'float3' lvalue 'F' 'float3' + +In this formation the write-back casts are captured as the first sub-expression +and they cast from an ``OpaqueValueExpr``. In IR generation we can use the +``OpaqueValueExpr`` as a placeholder for the ``HLSLOutParamExpr``'s temporary +value on function return. + +In code generation this can be implemented with some targeted extensions to the +Objective-C write-back support. Specifically extending CGCall.cpp's +``EmitWriteback`` function to support casting expressions and emission of +aggregate lvalues. diff --git a/clang/docs/HLSL/HLSLDocs.rst b/clang/docs/HLSL/HLSLDocs.rst index a02dd2e8a962..1f232129548d 100644 --- a/clang/docs/HLSL/HLSLDocs.rst +++ b/clang/docs/HLSL/HLSLDocs.rst @@ -14,3 +14,4 @@ HLSL Design and Implementation HLSLIRReference ResourceTypes EntryFunctions + FunctionCalls -- GitLab From 1c342571b80d0f76202ec590a19706fe9e05c86d Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Jan 2024 12:40:26 -0800 Subject: [PATCH 379/652] [LV] Use value_or to simplify code. NFC (#77030) --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 1a5b9dbb82fa..9743fa0e7402 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -5004,9 +5004,8 @@ VectorizationFactor LoopVectorizationPlanner::selectVectorizationFactor( VectorizationFactor Candidate(i, C.first, ScalarCost.ScalarCost); #ifndef NDEBUG - unsigned AssumedMinimumVscale = 1; - if (std::optional VScale = getVScaleForTuning(OrigLoop, TTI)) - AssumedMinimumVscale = *VScale; + unsigned AssumedMinimumVscale = + getVScaleForTuning(OrigLoop, TTI).value_or(1); unsigned Width = Candidate.Width.isScalable() ? Candidate.Width.getKnownMinValue() * AssumedMinimumVscale -- GitLab From 3378514a4da2a09abf644273c7170ffebbd25b43 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Jan 2024 12:41:11 -0800 Subject: [PATCH 380/652] [RISCV] Use any_extend for type legalizing atomic_compare_swap with Zacas. (#77669) With Zacas we will use amocas.w which doesn't require the input to be sign extended. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 +++++ llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 +--- llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 19 ------------------- 3 files changed, 6 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 90d648dab2ae..cb9ffabc4123 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -19364,6 +19364,11 @@ bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, return false; } +ISD::NodeType RISCVTargetLowering::getExtendForAtomicCmpSwapArg() const { + // Zacas will use amocas.w which does not require extension. + return Subtarget.hasStdExtZacas() ? ISD::ANY_EXTEND : ISD::SIGN_EXTEND; +} + Register RISCVTargetLowering::getExceptionPointerRegister( const Constant *PersonalityFn) const { return RISCV::X10; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 0d14e5b757bd..c65953e37b17 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -633,9 +633,7 @@ public: return ISD::SIGN_EXTEND; } - ISD::NodeType getExtendForAtomicCmpSwapArg() const override { - return ISD::SIGN_EXTEND; - } + ISD::NodeType getExtendForAtomicCmpSwapArg() const override; bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override; diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll index b3c9224646ed..5b3e5789e8d9 100644 --- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll @@ -3320,7 +3320,6 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw ; ; RV64IA-ZACAS-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV64IA-ZACAS: # %bb.0: -; RV64IA-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-ZACAS-NEXT: ret ; @@ -3412,7 +3411,6 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -3430,7 +3428,6 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire monotonic @@ -3510,7 +3507,6 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -3528,7 +3524,6 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire acquire @@ -3608,7 +3603,6 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_monotonic: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.rl a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -3626,7 +3620,6 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_monotonic: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic @@ -3706,7 +3699,6 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -3724,7 +3716,6 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_acquire: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release acquire @@ -3804,7 +3795,6 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -3822,7 +3812,6 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic @@ -3902,7 +3891,6 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -3920,7 +3908,6 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel acquire @@ -4000,7 +3987,6 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -4018,7 +4004,6 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic @@ -4098,7 +4083,6 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -4116,7 +4100,6 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire @@ -4196,7 +4179,6 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: -; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0) ; RV64IA-WMO-ZACAS-NEXT: ret ; @@ -4214,7 +4196,6 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind ; ; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64IA-TSO-ZACAS: # %bb.0: -; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1 ; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-TSO-ZACAS-NEXT: ret %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst -- GitLab From fb7fe49960ae053c92985f3376d85a15bbd10d1a Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Thu, 11 Jan 2024 03:45:13 +0700 Subject: [PATCH 381/652] [CommandLine][NFCI] Do not add 'All' to 'RegisteredSubCommands' (#77041) After #75679, it is no longer necessary to add the `All` pseudo subcommand to the list of registered subcommands. The change causes the list to contain only real subcommands, i.e. an unnamed top-level subcommand and named ones. This simplifies the code a bit by removing some checks for this special case. --- llvm/lib/Support/CommandLine.cpp | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Support/CommandLine.cpp b/llvm/lib/Support/CommandLine.cpp index 7360d733d96e..9a57936be2db 100644 --- a/llvm/lib/Support/CommandLine.cpp +++ b/llvm/lib/Support/CommandLine.cpp @@ -164,10 +164,7 @@ public: // This collects the different subcommands that have been registered. SmallPtrSet RegisteredSubCommands; - CommandLineParser() { - registerSubCommand(&SubCommand::getTopLevel()); - registerSubCommand(&SubCommand::getAll()); - } + CommandLineParser() { registerSubCommand(&SubCommand::getTopLevel()); } void ResetAllOptionOccurrences(); @@ -348,15 +345,15 @@ public: // For all options that have been registered for all subcommands, add the // option to this subcommand now. - if (sub != &SubCommand::getAll()) { - for (auto &E : SubCommand::getAll().OptionsMap) { - Option *O = E.second; - if ((O->isPositional() || O->isSink() || O->isConsumeAfter()) || - O->hasArgStr()) - addOption(O, sub); - else - addLiteralOption(*O, sub, E.first()); - } + assert(sub != &SubCommand::getAll() && + "SubCommand::getAll() should not be registered"); + for (auto &E : SubCommand::getAll().OptionsMap) { + Option *O = E.second; + if ((O->isPositional() || O->isSink() || O->isConsumeAfter()) || + O->hasArgStr()) + addOption(O, sub); + else + addLiteralOption(*O, sub, E.first()); } } @@ -384,7 +381,6 @@ public: SubCommand::getTopLevel().reset(); SubCommand::getAll().reset(); registerSubCommand(&SubCommand::getTopLevel()); - registerSubCommand(&SubCommand::getAll()); DefaultOptions.clear(); } @@ -532,8 +528,8 @@ SubCommand *CommandLineParser::LookupSubCommand(StringRef Name, // Find a subcommand with the edit distance == 1. SubCommand *NearestMatch = nullptr; for (auto *S : RegisteredSubCommands) { - if (S == &SubCommand::getAll()) - continue; + assert(S != &SubCommand::getAll() && + "SubCommand::getAll() is not expected in RegisteredSubCommands"); if (S->getName().empty()) continue; -- GitLab From a08506e374f5938e30a9c13b61a697e8c0e12aa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 10 Jan 2024 22:57:59 +0200 Subject: [PATCH 382/652] [LLD] [MinGW] Add support for more ThinLTO specific options (#77387) This was missed when mass-adding support for other LTO options in 0b51e648307cf6c21c463d3e73e51c03aaa8c9e2. Group the existing thinlto_cache_dir with these other options in a new group, next to the other LTO options. This skips adding the options --thinlto-emit-index-files and --thinlto-single-module=, which don't seem to have corresponding options on the lld-link level currently. This should fix https://github.com/mstorsjo/llvm-mingw/issues/386. --- lld/MinGW/Driver.cpp | 21 +++++++++++++++++---- lld/MinGW/Options.td | 11 +++++++++-- lld/test/MinGW/driver.test | 23 ++++++++++++++++++++--- 3 files changed, 46 insertions(+), 9 deletions(-) diff --git a/lld/MinGW/Driver.cpp b/lld/MinGW/Driver.cpp index 5ba1bf0e4b4e..4752d92e3b1d 100644 --- a/lld/MinGW/Driver.cpp +++ b/lld/MinGW/Driver.cpp @@ -270,8 +270,6 @@ bool link(ArrayRef argsArr, llvm::raw_ostream &stdoutOS, add("-lldmap:" + StringRef(a->getValue())); if (auto *a = args.getLastArg(OPT_reproduce)) add("-reproduce:" + StringRef(a->getValue())); - if (auto *a = args.getLastArg(OPT_thinlto_cache_dir)) - add("-lldltocache:" + StringRef(a->getValue())); if (auto *a = args.getLastArg(OPT_file_alignment)) add("-filealign:" + StringRef(a->getValue())); if (auto *a = args.getLastArg(OPT_section_alignment)) @@ -440,8 +438,6 @@ bool link(ArrayRef argsArr, llvm::raw_ostream &stdoutOS, if (auto *arg = args.getLastArg(OPT_plugin_opt_mcpu_eq)) add("-mllvm:-mcpu=" + StringRef(arg->getValue())); - if (auto *arg = args.getLastArg(OPT_thinlto_jobs_eq)) - add("-opt:lldltojobs=" + StringRef(arg->getValue())); if (auto *arg = args.getLastArg(OPT_lto_O)) add("-opt:lldlto=" + StringRef(arg->getValue())); if (auto *arg = args.getLastArg(OPT_lto_CGO)) @@ -453,6 +449,23 @@ bool link(ArrayRef argsArr, llvm::raw_ostream &stdoutOS, if (auto *arg = args.getLastArg(OPT_lto_cs_profile_file)) add("-lto-cs-profile-file:" + StringRef(arg->getValue())); + if (auto *a = args.getLastArg(OPT_thinlto_cache_dir)) + add("-lldltocache:" + StringRef(a->getValue())); + if (auto *a = args.getLastArg(OPT_thinlto_cache_policy)) + add("-lldltocachepolicy:" + StringRef(a->getValue())); + if (args.hasArg(OPT_thinlto_emit_imports_files)) + add("-thinlto-emit-imports-files"); + if (args.hasArg(OPT_thinlto_index_only)) + add("-thinlto-index-only"); + if (auto *arg = args.getLastArg(OPT_thinlto_index_only_eq)) + add("-thinlto-index-only:" + StringRef(arg->getValue())); + if (auto *arg = args.getLastArg(OPT_thinlto_jobs_eq)) + add("-opt:lldltojobs=" + StringRef(arg->getValue())); + if (auto *arg = args.getLastArg(OPT_thinlto_object_suffix_replace_eq)) + add("-thinlto-object-suffix-replace:" + StringRef(arg->getValue())); + if (auto *arg = args.getLastArg(OPT_thinlto_prefix_replace_eq)) + add("-thinlto-prefix-replace:" + StringRef(arg->getValue())); + for (auto *a : args.filtered(OPT_plugin_opt_eq_minus)) add("-mllvm:-" + StringRef(a->getValue())); diff --git a/lld/MinGW/Options.td b/lld/MinGW/Options.td index d8471d5a7bc9..02f00f27406c 100644 --- a/lld/MinGW/Options.td +++ b/lld/MinGW/Options.td @@ -149,6 +149,7 @@ defm wrap: Eq<"wrap", "Use wrapper functions for symbol">, MetaVarName<"">; +// LLD specific options, for LTO, shared with the ELF backend def lto_O: JJ<"lto-O">, MetaVarName<"">, HelpText<"Optimization level for LTO">; def lto_CGO: JJ<"lto-CGO">, MetaVarName<"">, @@ -158,8 +159,16 @@ def lto_cs_profile_generate: FF<"lto-cs-profile-generate">, def lto_cs_profile_file: JJ<"lto-cs-profile-file=">, HelpText<"Context sensitive profile file path">; +def thinlto_cache_dir: JJ<"thinlto-cache-dir=">, + HelpText<"Path to ThinLTO cached object file directory">; +defm thinlto_cache_policy: EEq<"thinlto-cache-policy", "Pruning policy for the ThinLTO cache">; +def thinlto_emit_imports_files: FF<"thinlto-emit-imports-files">; +def thinlto_index_only: FF<"thinlto-index-only">; +def thinlto_index_only_eq: JJ<"thinlto-index-only=">; def thinlto_jobs_eq: JJ<"thinlto-jobs=">, HelpText<"Number of ThinLTO jobs. Default to --threads=">; +def thinlto_object_suffix_replace_eq: JJ<"thinlto-object-suffix-replace=">; +def thinlto_prefix_replace_eq: JJ<"thinlto-prefix-replace=">; def plugin_opt_eq_minus: J<"plugin-opt=-">, HelpText<"Specify an LLVM option for compatibility with LLVMgold.so">; @@ -186,8 +195,6 @@ def appcontainer: F<"appcontainer">, HelpText<"Set the appcontainer flag in the defm delayload: Eq<"delayload", "DLL to load only on demand">; defm mllvm: EqNoHelp<"mllvm">; defm pdb: Eq<"pdb", "Output PDB debug info file, chosen implicitly if the argument is empty">; -def thinlto_cache_dir: JJ<"thinlto-cache-dir=">, - HelpText<"Path to ThinLTO cached object file directory">; defm Xlink : Eq<"Xlink", "Pass to the COFF linker">, MetaVarName<"">; defm guard_cf : B<"guard-cf", "Enable Control Flow Guard" , "Do not enable Control Flow Guard (default)">; diff --git a/lld/test/MinGW/driver.test b/lld/test/MinGW/driver.test index 5a9a6e227184..559a32bfa242 100644 --- a/lld/test/MinGW/driver.test +++ b/lld/test/MinGW/driver.test @@ -297,9 +297,6 @@ RUN: ld.lld -### -m i386pep foo.o --disable-runtime-pseudo-reloc 2>&1 | FileChec RUN: ld.lld -### -m i386pep foo.o -disable-runtime-pseudo-reloc 2>&1 | FileCheck -check-prefix DISABLE_RUNTIME_PSEUDO_RELOC %s DISABLE_RUNTIME_PSEUDO_RELOC: -runtime-pseudo-reloc:no -RUN: ld.lld -### foo.o -m i386pe --thinlto-cache-dir=_foo 2>&1 | FileCheck -check-prefix=THINLTO_CACHEDIR %s -THINLTO_CACHEDIR: -lldltocache:_foo - RUN: ld.lld -### -m i386pep foo.o --file-alignment 0x1000 2>&1 | FileCheck -check-prefix FILEALIGN %s RUN: ld.lld -### -m i386pep foo.o -file-alignment 0x1000 2>&1 | FileCheck -check-prefix FILEALIGN %s RUN: ld.lld -### -m i386pep foo.o --file-alignment=0x1000 2>&1 | FileCheck -check-prefix FILEALIGN %s @@ -382,10 +379,30 @@ RUN: ld.lld -### foo.o -m i386pep --guard-longjmp 2>&1 | FileCheck -check-prefix RUN: ld.lld -### foo.o -m i386pep --no-guard-cf --guard-longjmp 2>&1 | FileCheck -check-prefix=GUARD_LONGJMP_NO_CF %s GUARD_LONGJMP_NO_CF: warning: parameter --guard-longjmp only takes effect when used with --guard-cf +RUN: ld.lld -### foo.o -m i386pe --thinlto-cache-dir=_foo 2>&1 | FileCheck -check-prefix=THINLTO_CACHEDIR %s +THINLTO_CACHEDIR: -lldltocache:_foo + +RUN: ld.lld -### foo.o -m i386pe --thinlto-cache-policy=_foo 2>&1 | FileCheck -check-prefix=THINLTO_CACHE_POLICY %s +THINLTO_CACHE_POLICY: -lldltocachepolicy:_foo + +RUN: ld.lld -### foo.o -m i386pe --thinlto-emit-imports-files 2>&1 | FileCheck -check-prefix=THINLTO_EMIT_IMPORTS_FILES %s +THINLTO_EMIT_IMPORTS_FILES: -thinlto-emit-imports-files + +RUN: ld.lld -### foo.o -m i386pe --thinlto-index-only 2>&1 | FileCheck -check-prefix=THINLTO_INDEX_ONLY %s +THINLTO_INDEX_ONLY: -thinlto-index-only{{ }} +RUN: ld.lld -### foo.o -m i386pe --thinlto-index-only=_foo 2>&1 | FileCheck -check-prefix=THINLTO_INDEX_ONLY_EQ %s +THINLTO_INDEX_ONLY_EQ: -thinlto-index-only:_foo + RUN: ld.lld -### foo.o -m i386pep --threads 3 --thinlto-jobs=4 2>&1 | FileCheck -check-prefix=THREADS %s RUN: ld.lld -### foo.o -m i386pep --threads 3 -plugin-opt=jobs=4 2>&1 | FileCheck -check-prefix=THREADS %s THREADS: -threads:3 {{.*}} -opt:lldltojobs=4 +RUN: ld.lld -### foo.o -m i386pe --thinlto-object-suffix-replace=_foo 2>&1 | FileCheck -check-prefix=THINLTO_OBJECT_SUFFIX_REPLACE %s +THINLTO_OBJECT_SUFFIX_REPLACE: -thinlto-object-suffix-replace:_foo + +RUN: ld.lld -### foo.o -m i386pe --thinlto-prefix-replace=_foo 2>&1 | FileCheck -check-prefix=THINLTO_PREFIX_REPLACE %s +THINLTO_PREFIX_REPLACE: -thinlto-prefix-replace:_foo + RUN: ld.lld -### foo.o -m i386pep -plugin-opt=mcpu=x86-64 -plugin-opt=-emulated-tls -plugin-opt=thinlto -plugin-opt=O2 -plugin-opt=dwo_dir=foo -plugin-opt=cs-profile-generate -plugin-opt=cs-profile-path=bar 2>&1 | FileCheck -check-prefix=LTO_OPTS %s LTO_OPTS: -mllvm:-mcpu=x86-64 -opt:lldlto=2 -dwodir:foo -lto-cs-profile-generate -lto-cs-profile-file:bar -mllvm:-emulated-tls -- GitLab From aec73eade7af0e22c944714bec31570181bc1ad4 Mon Sep 17 00:00:00 2001 From: Aart Bik <39774503+aartbik@users.noreply.github.com> Date: Wed, 10 Jan 2024 13:36:20 -0800 Subject: [PATCH 383/652] [mlir][sparse] allow unknown ops in one-shot bufferization in mini-pipeline (#77688) Rationale: Since this mini-pipeline may be used in alternative pipelines (viz. different from the default "sparsifier" pipeline) where unknown ops are handled by alternative bufferization methods that are downstream of this mini-pipeline, we allow unknown ops by default (failure to bufferize is eventually apparent by failing to convert to LLVM IR). This is part of enabling e2e testing for TORCH-MLIR tests using a sparsifier backend --- .../Transforms/SparsificationAndBufferizationPass.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp index 6266c63064ff..f497be6e48eb 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp @@ -201,6 +201,12 @@ mlir::getBufferizationOptionsForSparsification(bool analysisOnly) { options.testAnalysisOnly = true; options.printConflicts = true; } + // Since this mini-pipeline may be used in alternative pipelines (viz. + // different from the default "sparsifier" pipeline) where unknown ops + // are handled by alternative bufferization methods that are downstream + // of this mini-pipeline, we allow unknown ops by default (failure to + // bufferize is eventually apparent by failing to convert to LLVM IR). + options.allowUnknownOps = true; return options; } -- GitLab From e51fe958a226888f57ad3646034e6060b830f01a Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Thu, 11 Jan 2024 02:12:23 +0400 Subject: [PATCH 384/652] [clang][NFC] Improve comments in C++ DR test suite (#77670) Previously, we've been mentioning tests that were placed in their own files in corresponding `drNNxx.cpp` file. This patch makes sure we do this consistently, and improves upon existing practice by specifying the name of the file test is placed in. --- clang/test/CXX/drs/dr17xx.cpp | 6 ++++++ clang/test/CXX/drs/dr1xx.cpp | 4 ++-- clang/test/CXX/drs/dr23xx.cpp | 2 ++ clang/test/CXX/drs/dr4xx.cpp | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/clang/test/CXX/drs/dr17xx.cpp b/clang/test/CXX/drs/dr17xx.cpp index 0c44fb231ce5..885ed00ace0f 100644 --- a/clang/test/CXX/drs/dr17xx.cpp +++ b/clang/test/CXX/drs/dr17xx.cpp @@ -89,6 +89,8 @@ S s(q); // #dr1736-s #endif } +// dr1748 is in dr1748.cpp + namespace dr1753 { // dr1753: 11 typedef int T; struct A { typedef int T; }; @@ -159,6 +161,8 @@ namespace dr1762 { // dr1762: 14 #endif } +// dr1772 is in dr177x.cpp + namespace dr1778 { // dr1778: 9 // Superseded by P1286R2. #if __cplusplus >= 201103L @@ -174,6 +178,8 @@ namespace dr1778 { // dr1778: 9 #endif } +// dr1779 is in dr177x.cpp + namespace dr1794 { // dr1794: yes // NB: dup 1710 #if __cplusplus >= 201103L diff --git a/clang/test/CXX/drs/dr1xx.cpp b/clang/test/CXX/drs/dr1xx.cpp index 064ecace5906..064b69411f0b 100644 --- a/clang/test/CXX/drs/dr1xx.cpp +++ b/clang/test/CXX/drs/dr1xx.cpp @@ -283,7 +283,7 @@ namespace dr116 { // dr116: yes } // dr117: na -// dr118 is in its own file. +// dr118 is in dr118.cpp // dr119: na // dr120: na @@ -789,7 +789,7 @@ namespace dr155 { // dr155: dup 632 // expected-warning@-1 {{braces around scalar initializer}} } -// dr158 is in its own file. +// dr158 is in dr158.cpp namespace dr159 { // dr159: 3.5 namespace X { void f(); } diff --git a/clang/test/CXX/drs/dr23xx.cpp b/clang/test/CXX/drs/dr23xx.cpp index 9ced61d2aae3..d2f4e7652ab5 100644 --- a/clang/test/CXX/drs/dr23xx.cpp +++ b/clang/test/CXX/drs/dr23xx.cpp @@ -213,6 +213,8 @@ namespace dr2387 { // dr2387: 9 #endif } +// dr2390 is in dr2390.cpp + namespace dr2394 { // dr2394: 15 struct A {}; diff --git a/clang/test/CXX/drs/dr4xx.cpp b/clang/test/CXX/drs/dr4xx.cpp index fd5c842c1085..fa90764df9b0 100644 --- a/clang/test/CXX/drs/dr4xx.cpp +++ b/clang/test/CXX/drs/dr4xx.cpp @@ -282,7 +282,7 @@ namespace dr410 { // dr410: no // expected-note@#dr410-z {{declared private here}} } -// dr412 is in its own file. +// dr412 is in dr412.cpp namespace dr413 { // dr413: yes struct S { -- GitLab From 8ca07e57c3be0dc41dbb95f6b21e541fecd74e8a Mon Sep 17 00:00:00 2001 From: Andrew Gozillon Date: Wed, 10 Jan 2024 16:20:16 -0600 Subject: [PATCH 385/652] [Flang][OpenMP][Offloading][Test] Adjust slightly incorrect tests now cmake configuration works These tests were slightly broken, in one case a failing test that now works. In the other case some accidentally left over code during a name change that broke compilation due to missing symbols. --- .../test/offloading/fortran/target_map_common_block.f90 | 3 +-- .../fortran/{failing => }/target_map_common_block1.f90 | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) rename openmp/libomptarget/test/offloading/fortran/{failing => }/target_map_common_block1.f90 (98%) diff --git a/openmp/libomptarget/test/offloading/fortran/target_map_common_block.f90 b/openmp/libomptarget/test/offloading/fortran/target_map_common_block.f90 index f20423edb957..402de2782b25 100644 --- a/openmp/libomptarget/test/offloading/fortran/target_map_common_block.f90 +++ b/openmp/libomptarget/test/offloading/fortran/target_map_common_block.f90 @@ -15,8 +15,7 @@ program main call commonblock_simple_with_implicit_type_var call commonblock_simple_with_integer call commonblock_simple_with_real - call commonblock_simple_to - call commonblock_simple_from + call commonblock_simple_to_from call set_commonblock_named call use_commonblock_named end program main diff --git a/openmp/libomptarget/test/offloading/fortran/failing/target_map_common_block1.f90 b/openmp/libomptarget/test/offloading/fortran/target_map_common_block1.f90 similarity index 98% rename from openmp/libomptarget/test/offloading/fortran/failing/target_map_common_block1.f90 rename to openmp/libomptarget/test/offloading/fortran/target_map_common_block1.f90 index 235da47a9103..35bbe511d931 100644 --- a/openmp/libomptarget/test/offloading/fortran/failing/target_map_common_block1.f90 +++ b/openmp/libomptarget/test/offloading/fortran/target_map_common_block1.f90 @@ -7,7 +7,6 @@ ! UNSUPPORTED: x86_64-pc-linux-gnu-LTO ! RUN: %libomptarget-compile-fortran-run-and-check-generic -! XFAIL: * program main use omp_lib -- GitLab From 98e3d98bf34ff9202e8b82d4967c02e4fd7d6532 Mon Sep 17 00:00:00 2001 From: Christopher Di Bella Date: Wed, 10 Jan 2024 14:28:22 -0800 Subject: [PATCH 386/652] [libc++] Rename local variable to avoid shadowing error (#77672) Due to the inclusion of a header, a global type is was being shadowed, which upset GCC. --- .../range.join/range.join.sentinel/ctor.other.pass.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp index fb1e8eb1ebef..8e78c3732e20 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp @@ -71,10 +71,10 @@ constexpr bool test() { BufferView, sentinel_wrapper>, bidirectional_iterator, sentinel_wrapper>>; using JoinView = std::ranges::join_view; - using sentinel = std::ranges::sentinel_t; - using const_sentinel = std::ranges::sentinel_t; - static_assert(!std::constructible_from); - static_assert(!std::constructible_from); + using sentinel_t = std::ranges::sentinel_t; + using const_sentinel_t = std::ranges::sentinel_t; + static_assert(!std::constructible_from); + static_assert(!std::constructible_from); } return true; } -- GitLab From 21a784f24e3f6c09558de6a3dfb32e2069955405 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Wed, 10 Jan 2024 15:05:58 -0800 Subject: [PATCH 387/652] [llvm-exegesis] Add tablegen support for validation counters (#76652) This patch adds support in the llvm-exegesis tablegen emitter for validation counters. Full support for validation counters in llvm-exegesis will be added in a future patch. --- llvm/include/llvm/Target/TargetPfmCounters.td | 24 +++++++++ llvm/lib/Target/X86/X86PfmCounters.td | 6 +++ llvm/tools/llvm-exegesis/lib/Target.cpp | 9 +++- llvm/tools/llvm-exegesis/lib/Target.h | 10 ++++ llvm/utils/TableGen/ExegesisEmitter.cpp | 52 ++++++++++++++++++- 5 files changed, 97 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/Target/TargetPfmCounters.td b/llvm/include/llvm/Target/TargetPfmCounters.td index b00f3e19c35f..49b2d1fc2565 100644 --- a/llvm/include/llvm/Target/TargetPfmCounters.td +++ b/llvm/include/llvm/Target/TargetPfmCounters.td @@ -28,6 +28,27 @@ class PfmIssueCounter string ResourceName = resource_name; } +// Definition of a validation event. A validation event represents a specific +// event that can be measured using performance counters that is interesting +// in regard to the snippet state. +class ValidationEvent { + int EventNumber = event_number; +} + +def L1DCacheLoadMiss : ValidationEvent<0>; +def InstructionRetired : ValidationEvent<1>; +def DataTLBLoadMiss : ValidationEvent<2>; +def DataTLBStoreMiss : ValidationEvent<3>; + +// PfmValidationCounter provides a mapping between the events that are +// are interesting in regards to the snippet execution environment and +// a concrete performance counter name that can be looked up in libpfm. +class PfmValidationCounter + : PfmCounter { + // The name of the event that the validation counter detects. + ValidationEvent EventType = event_type; +} + def NoPfmCounter : PfmCounter <""> {} // Set of PfmCounters for measuring sched model characteristics. @@ -38,6 +59,9 @@ class ProcPfmCounters { PfmCounter UopsCounter = NoPfmCounter; // Processors can define how to measure issued uops by defining IssueCounters. list IssueCounters = []; + // Processor can list mappings between validation events and real counters + // to measure the specified events. + list ValidationCounters = []; } // A binding of a set of counters to a CPU. diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index 49ef6efc6aec..99cac504f157 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -275,6 +275,9 @@ def ZnVer2PfmCounters : ProcPfmCounters { PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">, PfmIssueCounter<"Zn2Divider", "div_op_count"> ]; + let ValidationCounters = [ + PfmValidationCounter + ]; } def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>; @@ -288,6 +291,9 @@ def ZnVer3PfmCounters : ProcPfmCounters { PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">, PfmIssueCounter<"Zn3Divider", "div_op_count"> ]; + let ValidationCounters = [ + PfmValidationCounter + ]; } def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>; diff --git a/llvm/tools/llvm-exegesis/lib/Target.cpp b/llvm/tools/llvm-exegesis/lib/Target.cpp index 23c80e5b9895..fe1eded63dc5 100644 --- a/llvm/tools/llvm-exegesis/lib/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/Target.cpp @@ -149,10 +149,15 @@ std::unique_ptr ExegesisTarget::createUopsBenchmarkRunner( static_assert(std::is_trivial_v, "We shouldn't have dynamic initialization here"); + const PfmCountersInfo PfmCountersInfo::Default = {nullptr, nullptr, nullptr, - 0u}; + 0u, nullptr, 0u}; const PfmCountersInfo PfmCountersInfo::Dummy = { - pfm::PerfEvent::DummyEventString, pfm::PerfEvent::DummyEventString, nullptr, + pfm::PerfEvent::DummyEventString, + pfm::PerfEvent::DummyEventString, + nullptr, + 0u, + nullptr, 0u}; const PfmCountersInfo &ExegesisTarget::getPfmCounters(StringRef CpuName) const { diff --git a/llvm/tools/llvm-exegesis/lib/Target.h b/llvm/tools/llvm-exegesis/lib/Target.h index c37dd8b70821..9d3bb2b44af1 100644 --- a/llvm/tools/llvm-exegesis/lib/Target.h +++ b/llvm/tools/llvm-exegesis/lib/Target.h @@ -39,6 +39,13 @@ extern cl::OptionCategory Options; extern cl::OptionCategory BenchmarkOptions; extern cl::OptionCategory AnalysisOptions; +enum ValidationEvent { + L1DCacheLoadMiss, + InstructionRetired, + DataTLBLoadMiss, + DataTLBStoreMiss +}; + struct PfmCountersInfo { // An optional name of a performance counter that can be used to measure // cycles. @@ -59,6 +66,9 @@ struct PfmCountersInfo { const IssueCounter *IssueCounters; unsigned NumIssueCounters; + const std::pair *ValidationEvents; + unsigned NumValidationEvents; + static const PfmCountersInfo Default; static const PfmCountersInfo Dummy; }; diff --git a/llvm/utils/TableGen/ExegesisEmitter.cpp b/llvm/utils/TableGen/ExegesisEmitter.cpp index 736f1220be14..d48c7f3a480f 100644 --- a/llvm/utils/TableGen/ExegesisEmitter.cpp +++ b/llvm/utils/TableGen/ExegesisEmitter.cpp @@ -81,6 +81,11 @@ collectPfmCounters(const RecordKeeper &Records) { "duplicate ResourceName " + ResourceName); AddPfmCounterName(IssueCounter); } + + for (const Record *ValidationCounter : + Def->getValueAsListOfDefs("ValidationCounters")) + AddPfmCounterName(ValidationCounter); + AddPfmCounterName(Def->getValueAsDef("CycleCounter")); AddPfmCounterName(Def->getValueAsDef("UopsCounter")); } @@ -100,6 +105,17 @@ ExegesisEmitter::ExegesisEmitter(RecordKeeper &RK) Target = std::string(Targets[0]->getName()); } +struct ValidationCounterInfo { + int64_t EventNumber; + StringRef EventName; + unsigned PfmCounterID; +}; + +bool EventNumberLess(const ValidationCounterInfo &LHS, + const ValidationCounterInfo &RHS) { + return LHS.EventNumber < RHS.EventNumber; +} + void ExegesisEmitter::emitPfmCountersInfo(const Record &Def, unsigned &IssueCountersTableOffset, raw_ostream &OS) const { @@ -109,6 +125,31 @@ void ExegesisEmitter::emitPfmCountersInfo(const Record &Def, Def.getValueAsDef("UopsCounter")->getValueAsString("Counter"); const size_t NumIssueCounters = Def.getValueAsListOfDefs("IssueCounters").size(); + const size_t NumValidationCounters = + Def.getValueAsListOfDefs("ValidationCounters").size(); + + // Emit Validation Counters Array + if (NumValidationCounters != 0) { + std::vector ValidationCounters; + ValidationCounters.reserve(NumValidationCounters); + for (const Record *ValidationCounter : + Def.getValueAsListOfDefs("ValidationCounters")) { + ValidationCounters.push_back( + {ValidationCounter->getValueAsDef("EventType") + ->getValueAsInt("EventNumber"), + ValidationCounter->getValueAsDef("EventType")->getName(), + getPfmCounterId(ValidationCounter->getValueAsString("Counter"))}); + } + std::sort(ValidationCounters.begin(), ValidationCounters.end(), + EventNumberLess); + OS << "\nstatic const std::pair " << Target + << Def.getName() << "ValidationCounters[] = {\n"; + for (const ValidationCounterInfo &VCI : ValidationCounters) { + OS << " { " << VCI.EventName << ", " << Target << "PfmCounterNames[" + << VCI.PfmCounterID << "]},\n"; + } + OS << "};\n"; + } OS << "\nstatic const PfmCountersInfo " << Target << Def.getName() << " = {\n"; @@ -129,10 +170,17 @@ void ExegesisEmitter::emitPfmCountersInfo(const Record &Def, // Issue Counters if (NumIssueCounters == 0) - OS << " nullptr, // No issue counters.\n 0\n"; + OS << " nullptr, 0, // No issue counters\n"; else OS << " " << Target << "PfmIssueCounters + " << IssueCountersTableOffset - << ", " << NumIssueCounters << " // Issue counters.\n"; + << ", " << NumIssueCounters << ", // Issue counters.\n"; + + // Validation Counters + if (NumValidationCounters == 0) + OS << " nullptr, 0 // No validation counters.\n"; + else + OS << " " << Target << Def.getName() << "ValidationCounters, " + << NumValidationCounters << " // Validation counters.\n"; OS << "};\n"; IssueCountersTableOffset += NumIssueCounters; -- GitLab From 04a906ec980e7bf49ffda0808766f51d08e8ae76 Mon Sep 17 00:00:00 2001 From: PiJoules <6019989+PiJoules@users.noreply.github.com> Date: Wed, 10 Jan 2024 15:12:42 -0800 Subject: [PATCH 388/652] [llvm][lld] Support R_AARCH64_GOTPCREL32 (#72584) This is the follopw implementation to https://github.com/ARM-software/abi-aa/pull/223 that supports this relocation in llvm and lld. --- lld/ELF/Arch/AArch64.cpp | 3 +++ lld/test/ELF/aarch64-reloc-gotpcrel32.s | 27 +++++++++++++++++++ .../llvm/BinaryFormat/ELFRelocs/AArch64.def | 1 + .../MCTargetDesc/AArch64ELFObjectWriter.cpp | 8 ++++-- llvm/test/MC/AArch64/elf-reloc-gotpcrel32.s | 14 ++++++++++ 5 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 lld/test/ELF/aarch64-reloc-gotpcrel32.s create mode 100644 llvm/test/MC/AArch64/elf-reloc-gotpcrel32.s diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp index 54b0a84e5213..71a1b1111e42 100644 --- a/lld/ELF/Arch/AArch64.cpp +++ b/lld/ELF/Arch/AArch64.cpp @@ -165,6 +165,8 @@ RelExpr AArch64::getRelExpr(RelType type, const Symbol &s, case R_AARCH64_ADR_GOT_PAGE: case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: return R_AARCH64_GOT_PAGE_PC; + case R_AARCH64_GOTPCREL32: + return R_GOT_PC; case R_AARCH64_NONE: return R_NONE; default: @@ -374,6 +376,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel, write32(loc, val); break; case R_AARCH64_PLT32: + case R_AARCH64_GOTPCREL32: checkInt(loc, val, 32, rel); write32(loc, val); break; diff --git a/lld/test/ELF/aarch64-reloc-gotpcrel32.s b/lld/test/ELF/aarch64-reloc-gotpcrel32.s new file mode 100644 index 000000000000..4d007776a86a --- /dev/null +++ b/lld/test/ELF/aarch64-reloc-gotpcrel32.s @@ -0,0 +1,27 @@ +// REQUIRES: aarch64 +// RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o +// RUN: ld.lld %t.o -o %t.so -shared --noinhibit-exec 2>&1 | FileCheck %s --check-prefix=WARN +// RUN: llvm-readelf -S %t.so | FileCheck --check-prefix=SEC %s +// RUN: llvm-objdump --no-print-imm-hex -s -d %t.so | FileCheck %s + +// SEC: .got PROGBITS 0000000000020390 + + .section .data + .globl bar +bar: + + .globl _start +_start: // PC = 0x303a0 +// bar@GOTPCREL = 0x20390 (got entry for `bar`) - 0x303a0 (.) = 0xf0fffeff +// bar@GOTPCREL+4 = 0x20390 (got entry for `bar`) - 0x303a4 (.) + 4 = 0xf0fffeff +// bar@GOTPCREL-4 = 0x20390 (got entry for `bar`) - 0x303a8 (.) - 4 = 0xe4fffeff +// CHECK: Contents of section .data: +// CHECK-NEXT: {{.*}} f0fffeff f0fffeff e4fffeff + .word bar@GOTPCREL + .word bar@GOTPCREL+4 + .word bar@GOTPCREL-4 + +// WARN: relocation R_AARCH64_GOTPCREL32 out of range: {{.*}} is not in [-2147483648, 2147483647]; references 'baz' +// WARN: relocation R_AARCH64_GOTPCREL32 out of range: {{.*}} is not in [-2147483648, 2147483647]; references 'baz' + .word baz@GOTPCREL+0xffffffff + .word baz@GOTPCREL-0xffffffff diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def index 30375de420e3..5fb3fa4aeb7b 100644 --- a/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def +++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def @@ -59,6 +59,7 @@ ELF_RELOC(R_AARCH64_ADR_GOT_PAGE, 0x137) ELF_RELOC(R_AARCH64_LD64_GOT_LO12_NC, 0x138) ELF_RELOC(R_AARCH64_LD64_GOTPAGE_LO15, 0x139) ELF_RELOC(R_AARCH64_PLT32, 0x13a) +ELF_RELOC(R_AARCH64_GOTPCREL32, 0x13b) ELF_RELOC(R_AARCH64_TLSGD_ADR_PREL21, 0x200) ELF_RELOC(R_AARCH64_TLSGD_ADR_PAGE21, 0x201) ELF_RELOC(R_AARCH64_TLSGD_ADD_LO12_NC, 0x202) diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp index 496ab18e9b19..6e074b6a63c4 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp @@ -120,7 +120,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, assert((!Target.getSymA() || Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None || - Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT) && + Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT || + Target.getSymA()->getKind() == MCSymbolRefExpr::VK_GOTPCREL) && "Should only be expression-level modifiers here"); assert((!Target.getSymB() || @@ -206,7 +207,10 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, case FK_Data_2: return R_CLS(ABS16); case FK_Data_4: - return R_CLS(ABS32); + return (!IsILP32 && + Target.getAccessVariant() == MCSymbolRefExpr::VK_GOTPCREL) + ? ELF::R_AARCH64_GOTPCREL32 + : R_CLS(ABS32); case FK_Data_8: if (IsILP32) { Ctx.reportError(Fixup.getLoc(), diff --git a/llvm/test/MC/AArch64/elf-reloc-gotpcrel32.s b/llvm/test/MC/AArch64/elf-reloc-gotpcrel32.s new file mode 100644 index 000000000000..afbcaad9e1df --- /dev/null +++ b/llvm/test/MC/AArch64/elf-reloc-gotpcrel32.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r - | FileCheck %s + + .section .data +this: + .word this@GOTPCREL + .word extern_sym@GOTPCREL+4 + .word negative_offset@GOTPCREL-4 + +// CHECK: Section ({{.*}}) .rela.data +// CHECK-NEXT: 0x0 R_AARCH64_GOTPCREL32 this 0x0 +// CHECK-NEXT: 0x4 R_AARCH64_GOTPCREL32 extern_sym 0x4 +// CHECK-NEXT: 0x8 R_AARCH64_GOTPCREL32 negative_offset 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: } -- GitLab From f7678c81fe96dc8a350d947b77ce5311a9f99612 Mon Sep 17 00:00:00 2001 From: PiJoules <6019989+PiJoules@users.noreply.github.com> Date: Wed, 10 Jan 2024 15:16:55 -0800 Subject: [PATCH 389/652] [llvm][lld] Support R_RISCV_GOT32_PCREL (#72587) This is the followup implementation to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/402 that supports this relocation in llvm and lld. --- lld/ELF/Arch/RISCV.cpp | 3 +++ lld/test/ELF/riscv64-reloc-got32-pcrel.s | 27 +++++++++++++++++++ .../llvm/BinaryFormat/ELFRelocs/RISCV.def | 3 +-- .../MCTargetDesc/RISCVELFObjectWriter.cpp | 2 ++ llvm/test/MC/RISCV/elf-reloc-got32-pcrel.s | 14 ++++++++++ 5 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 lld/test/ELF/riscv64-reloc-got32-pcrel.s create mode 100644 llvm/test/MC/RISCV/elf-reloc-got32-pcrel.s diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 1d3d179e5d6f..62498ded1a2b 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -290,6 +290,7 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s, case R_RISCV_PLT32: return R_PLT_PC; case R_RISCV_GOT_HI20: + case R_RISCV_GOT32_PCREL: return R_GOT_PC; case R_RISCV_PCREL_LO12_I: case R_RISCV_PCREL_LO12_S: @@ -499,6 +500,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { case R_RISCV_SET32: case R_RISCV_32_PCREL: case R_RISCV_PLT32: + case R_RISCV_GOT32_PCREL: + checkInt(loc, val, 32, rel); write32le(loc, val); return; diff --git a/lld/test/ELF/riscv64-reloc-got32-pcrel.s b/lld/test/ELF/riscv64-reloc-got32-pcrel.s new file mode 100644 index 000000000000..24bd828235b2 --- /dev/null +++ b/lld/test/ELF/riscv64-reloc-got32-pcrel.s @@ -0,0 +1,27 @@ +// REQUIRES: riscv +// RUN: llvm-mc -filetype=obj -triple=riscv64 %s -o %t.o +// RUN: ld.lld %t.o -o %t.so -shared --noinhibit-exec 2>&1 | FileCheck %s --check-prefix=WARN +// RUN: llvm-readelf -S %t.so | FileCheck --check-prefix=SEC %s +// RUN: llvm-objdump --no-print-imm-hex -s -d %t.so | FileCheck %s + +// SEC: .got PROGBITS 0000000000002390 + + .section .data + .globl bar +bar: + + .globl _start +_start: // PC = 0x33a8 +// bar@GOTPCREL = 0x2398 (got entry for `bar`) - 0x33a8 (.) = 0xf0efffff +// bar@GOTPCREL+4 = 0x2398 (got entry for `bar`) - 0x33ac (.) + 4 = 0xf0efffff +// bar@GOTPCREL-4 = 0x2398 (got entry for `bar`) - 0x33b0 (.) - 4 = 0xe4efffff +// CHECK: Contents of section .data: +// CHECK-NEXT: {{.*}} f0efffff f0efffff e4efffff + .word bar@GOTPCREL + .word bar@GOTPCREL+4 + .word bar@GOTPCREL-4 + +// WARN: relocation R_RISCV_GOT32_PCREL out of range: {{.*}} is not in [-2147483648, 2147483647]; references 'baz' +// WARN: relocation R_RISCV_GOT32_PCREL out of range: {{.*}} is not in [-2147483648, 2147483647]; references 'baz' + .word baz@GOTPCREL+0xffffffff + .word baz@GOTPCREL-0xffffffff diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def index c7fd6490041c..b478799c91fb 100644 --- a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def +++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def @@ -40,8 +40,7 @@ ELF_RELOC(R_RISCV_SUB8, 37) ELF_RELOC(R_RISCV_SUB16, 38) ELF_RELOC(R_RISCV_SUB32, 39) ELF_RELOC(R_RISCV_SUB64, 40) -ELF_RELOC(R_RISCV_GNU_VTINHERIT, 41) -ELF_RELOC(R_RISCV_GNU_VTENTRY, 42) +ELF_RELOC(R_RISCV_GOT32_PCREL, 41) ELF_RELOC(R_RISCV_ALIGN, 43) ELF_RELOC(R_RISCV_RVC_BRANCH, 44) ELF_RELOC(R_RISCV_RVC_JUMP, 45) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp index 0799267eaf7c..76e5b3ed4025 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp @@ -106,6 +106,8 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx, if (Expr->getKind() == MCExpr::Target && cast(Expr)->getKind() == RISCVMCExpr::VK_RISCV_32_PCREL) return ELF::R_RISCV_32_PCREL; + if (Target.getSymA()->getKind() == MCSymbolRefExpr::VK_GOTPCREL) + return ELF::R_RISCV_GOT32_PCREL; return ELF::R_RISCV_32; case FK_Data_8: return ELF::R_RISCV_64; diff --git a/llvm/test/MC/RISCV/elf-reloc-got32-pcrel.s b/llvm/test/MC/RISCV/elf-reloc-got32-pcrel.s new file mode 100644 index 000000000000..32a1d57fb536 --- /dev/null +++ b/llvm/test/MC/RISCV/elf-reloc-got32-pcrel.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=riscv64 -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r - | FileCheck %s + + .section .data +this: + .word this@GOTPCREL + .word extern_sym@GOTPCREL+4 + .word negative_offset@GOTPCREL-4 + +// CHECK: Section ({{.*}}) .rela.data +// CHECK-NEXT: 0x0 R_RISCV_GOT32_PCREL this 0x0 +// CHECK-NEXT: 0x4 R_RISCV_GOT32_PCREL extern_sym 0x4 +// CHECK-NEXT: 0x8 R_RISCV_GOT32_PCREL negative_offset 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: } -- GitLab From f65265ab779f5c6c571ff702aae5670722765ae0 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Wed, 10 Jan 2024 15:15:45 -0800 Subject: [PATCH 390/652] [llvm-exegesis] Fix validation counters While landing #76652, I realized I messed up a rebase/merge at some point and some of the changes I intended to land with #76652 ended up in a different PR (#76653) instead. This patch fixes the validation counters to how they were intended to land in #76652. --- llvm/include/llvm/Target/TargetPfmCounters.td | 5 +--- llvm/lib/Target/X86/X86PfmCounters.td | 24 ++++++++++++++----- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/llvm/include/llvm/Target/TargetPfmCounters.td b/llvm/include/llvm/Target/TargetPfmCounters.td index 49b2d1fc2565..33dff741fa2a 100644 --- a/llvm/include/llvm/Target/TargetPfmCounters.td +++ b/llvm/include/llvm/Target/TargetPfmCounters.td @@ -35,10 +35,7 @@ class ValidationEvent { int EventNumber = event_number; } -def L1DCacheLoadMiss : ValidationEvent<0>; -def InstructionRetired : ValidationEvent<1>; -def DataTLBLoadMiss : ValidationEvent<2>; -def DataTLBStoreMiss : ValidationEvent<3>; +def InstructionRetired : ValidationEvent<0>; // PfmValidationCounter provides a mapping between the events that are // are interesting in regards to the snippet execution environment and diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index 99cac504f157..48d689549709 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -18,6 +18,10 @@ def DefaultPfmCounters : ProcPfmCounters {} def : PfmCountersDefaultBinding; // Intel X86 Counters. +defvar DefaultIntelPfmValidationCounters = [ + PfmValidationCounter +]; + def PentiumPfmCounters : ProcPfmCounters { let CycleCounter = PfmCounter<"cpu_clk_unhalted">; let UopsCounter = PfmCounter<"uops_retired">; @@ -100,6 +104,7 @@ def SandyBridgePfmCounters : ProcPfmCounters { PfmIssueCounter<"SBPort4", "uops_dispatched_port:port_4">, PfmIssueCounter<"SBPort5", "uops_dispatched_port:port_5"> ]; + let ValidationCounters = DefaultIntelPfmValidationCounters; } def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>; def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>; @@ -117,6 +122,7 @@ def HaswellPfmCounters : ProcPfmCounters { PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">, PfmIssueCounter<"HWPort7", "uops_executed_port:port_7"> ]; + let ValidationCounters = DefaultIntelPfmValidationCounters; } def : PfmCountersBinding<"haswell", HaswellPfmCounters>; @@ -133,6 +139,7 @@ def BroadwellPfmCounters : ProcPfmCounters { PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">, PfmIssueCounter<"BWPort7", "uops_executed_port:port_7"> ]; + let ValidationCounters = DefaultIntelPfmValidationCounters; } def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>; @@ -149,6 +156,7 @@ def SkylakeClientPfmCounters : ProcPfmCounters { PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">, PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7"> ]; + let ValidationCounters = DefaultIntelPfmValidationCounters; } def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>; @@ -165,6 +173,7 @@ def SkylakeServerPfmCounters : ProcPfmCounters { PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">, PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7"> ]; + let ValidationCounters = DefaultIntelPfmValidationCounters; } def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>; def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>; @@ -182,6 +191,7 @@ def IceLakePfmCounters : ProcPfmCounters { PfmIssueCounter<"ICXPort6", "uops_dispatched_port:port_6">, PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8"> ]; + let ValidationCounters = DefaultIntelPfmValidationCounters; } def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>; def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>; @@ -189,6 +199,10 @@ def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>; def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>; // AMD X86 Counters. +defvar DefaultAMDPfmValidationCounters = [ + PfmValidationCounter +]; + // Set basic counters for AMD cpus that we know libpfm4 supports. def DefaultAMDPfmCounters : ProcPfmCounters { let CycleCounter = PfmCounter<"cpu_clk_unhalted">; @@ -265,6 +279,7 @@ def ZnVer1PfmCounters : ProcPfmCounters { PfmIssueCounter<"ZnAGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">, PfmIssueCounter<"ZnDivider", "div_op_count"> ]; + let ValidationCounters = DefaultAMDPfmValidationCounters; } def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>; @@ -275,9 +290,7 @@ def ZnVer2PfmCounters : ProcPfmCounters { PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">, PfmIssueCounter<"Zn2Divider", "div_op_count"> ]; - let ValidationCounters = [ - PfmValidationCounter - ]; + let ValidationCounters = DefaultAMDPfmValidationCounters; } def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>; @@ -291,9 +304,7 @@ def ZnVer3PfmCounters : ProcPfmCounters { PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">, PfmIssueCounter<"Zn3Divider", "div_op_count"> ]; - let ValidationCounters = [ - PfmValidationCounter - ]; + let ValidationCounters = DefaultAMDPfmValidationCounters; } def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>; @@ -308,5 +319,6 @@ def ZnVer4PfmCounters : ProcPfmCounters { PfmIssueCounter<"Zn4Divider", "div_op_count">, PfmIssueCounter<"Zn4AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch"> ]; + let ValidationCounters = DefaultAMDPfmValidationCounters; } def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>; -- GitLab From fefdef808c230c79dca2eb504490ad0f17a765a5 Mon Sep 17 00:00:00 2001 From: Bill Wendling <5993918+bwendling@users.noreply.github.com> Date: Wed, 10 Jan 2024 15:21:10 -0800 Subject: [PATCH 391/652] [Clang] Implement the 'counted_by' attribute (#76348) The 'counted_by' attribute is used on flexible array members. The argument for the attribute is the name of the field member holding the count of elements in the flexible array. This information is used to improve the results of the array bound sanitizer and the '__builtin_dynamic_object_size' builtin. The 'count' field member must be within the same non-anonymous, enclosing struct as the flexible array member. For example: ``` struct bar; struct foo { int count; struct inner { struct { int count; /* The 'count' referenced by 'counted_by' */ }; struct { /* ... */ struct bar *array[] __attribute__((counted_by(count))); }; } baz; }; ``` This example specifies that the flexible array member 'array' has the number of elements allocated for it in 'count': ``` struct bar; struct foo { size_t count; /* ... */ struct bar *array[] __attribute__((counted_by(count))); }; ``` This establishes a relationship between 'array' and 'count'; specifically that 'p->array' must have *at least* 'p->count' number of elements available. It's the user's responsibility to ensure that this relationship is maintained throughout changes to the structure. In the following, the allocated array erroneously has fewer elements than what's specified by 'p->count'. This would result in an out-of-bounds access not not being detected: ``` struct foo *p; void foo_alloc(size_t count) { p = malloc(MAX(sizeof(struct foo), offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); p->count = count + 42; } ``` The next example updates 'p->count', breaking the relationship requirement that 'p->array' must have at least 'p->count' number of elements available: ``` void use_foo(int index, int val) { p->count += 42; p->array[index] = val; /* The sanitizer can't properly check this access */ } ``` In this example, an update to 'p->count' maintains the relationship requirement: ``` void use_foo(int index, int val) { if (p->count == 0) return; --p->count; p->array[index] = val; } ``` --- clang/docs/ReleaseNotes.rst | 5 + clang/include/clang/AST/DeclBase.h | 10 + clang/include/clang/Basic/Attr.td | 18 + clang/include/clang/Basic/AttrDocs.td | 78 + .../clang/Basic/DiagnosticSemaKinds.td | 13 + clang/include/clang/Sema/Sema.h | 3 + clang/include/clang/Sema/TypoCorrection.h | 12 +- clang/lib/AST/ASTImporter.cpp | 13 + clang/lib/AST/DeclBase.cpp | 74 +- clang/lib/AST/Expr.cpp | 83 +- clang/lib/CodeGen/CGBuiltin.cpp | 240 +++ clang/lib/CodeGen/CGExpr.cpp | 340 ++- clang/lib/CodeGen/CodeGenFunction.h | 22 + clang/lib/Sema/SemaDecl.cpp | 6 + clang/lib/Sema/SemaDeclAttr.cpp | 133 ++ clang/lib/Sema/SemaExpr.cpp | 16 +- clang/test/CodeGen/attr-counted-by.c | 1828 +++++++++++++++++ clang/test/CodeGen/bounds-checking.c | 10 +- ...a-attribute-supported-attributes-list.test | 1 + clang/test/Sema/attr-counted-by.c | 64 + 20 files changed, 2877 insertions(+), 92 deletions(-) create mode 100644 clang/test/CodeGen/attr-counted-by.c create mode 100644 clang/test/Sema/attr-counted-by.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index ade0036ba2fd..a60c5a7cd058 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -208,6 +208,11 @@ C Language Changes - Enums will now be represented in TBAA metadata using their actual underlying integer type. Previously they were treated as chars, which meant they could alias with all other types. +- Clang now supports the C-only attribute ``counted_by``. When applied to a + struct's flexible array member, it points to the struct field that holds the + number of elements in the flexible array member. This information can improve + the results of the array bound sanitizer and the + ``__builtin_dynamic_object_size`` builtin. C23 Feature Support ^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h index 10dcbdb262d8..5b1038582bc6 100644 --- a/clang/include/clang/AST/DeclBase.h +++ b/clang/include/clang/AST/DeclBase.h @@ -19,6 +19,7 @@ #include "clang/AST/SelectorLocationsKind.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LLVM.h" +#include "clang/Basic/LangOptions.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/Specifiers.h" #include "llvm/ADT/ArrayRef.h" @@ -488,6 +489,15 @@ public: // Return true if this is a FileContext Decl. bool isFileContextDecl() const; + /// Whether it resembles a flexible array member. This is a static member + /// because we want to be able to call it with a nullptr. That allows us to + /// perform non-Decl specific checks based on the object's type and strict + /// flex array level. + static bool isFlexibleArrayMemberLike( + ASTContext &Context, const Decl *D, QualType Ty, + LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, + bool IgnoreTemplateOrMacroSubstitution); + ASTContext &getASTContext() const LLVM_READONLY; /// Helper to get the language options from the ASTContext. diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index d5eabaad4889..a03b0e44e15f 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -4372,3 +4372,21 @@ def CodeAlign: StmtAttr { static constexpr int MaximumAlignment = 4096; }]; } + +def CountedBy : InheritableAttr { + let Spellings = [Clang<"counted_by">]; + let Subjects = SubjectList<[Field]>; + let Args = [IdentifierArgument<"CountedByField">]; + let Documentation = [CountedByDocs]; + let LangOpts = [COnly]; + // FIXME: This is ugly. Let using a DeclArgument would be nice, but a Decl + // isn't yet available due to the fact that we're still parsing the + // structure. Maybe that code could be changed sometime in the future. + code AdditionalMembers = [{ + private: + SourceRange CountedByFieldLoc; + public: + SourceRange getCountedByFieldLoc() const { return CountedByFieldLoc; } + void setCountedByFieldLoc(SourceRange Loc) { CountedByFieldLoc = Loc; } + }]; +} diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 5416a0cbdd07..2e8d7752c975 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7749,3 +7749,81 @@ but do not pass them to the underlying coroutine or pass them by value. .. _`CRT`: https://clang.llvm.org/docs/AttributeReference.html#coro-return-type }]; } + +def CountedByDocs : Documentation { + let Category = DocCatField; + let Content = [{ +Clang supports the ``counted_by`` attribute on the flexible array member of a +structure in C. The argument for the attribute is the name of a field member +holding the count of elements in the flexible array. This information can be +used to improve the results of the array bound sanitizer and the +``__builtin_dynamic_object_size`` builtin. The ``count`` field member must be +within the same non-anonymous, enclosing struct as the flexible array member. + +This example specifies that the flexible array member ``array`` has the number +of elements allocated for it in ``count``: + +.. code-block:: c + + struct bar; + + struct foo { + size_t count; + char other; + struct bar *array[] __attribute__((counted_by(count))); + }; + +This establishes a relationship between ``array`` and ``count``. Specifically, +``array`` must have at least ``count`` number of elements available. It's the +user's responsibility to ensure that this relationship is maintained through +changes to the structure. + +In the following example, the allocated array erroneously has fewer elements +than what's specified by ``p->count``. This would result in an out-of-bounds +access not being detected. + +.. code-block:: c + + #define SIZE_INCR 42 + + struct foo *p; + + void foo_alloc(size_t count) { + p = malloc(MAX(sizeof(struct foo), + offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); + p->count = count + SIZE_INCR; + } + +The next example updates ``p->count``, but breaks the relationship requirement +that ``p->array`` must have at least ``p->count`` number of elements available: + +.. code-block:: c + + #define SIZE_INCR 42 + + struct foo *p; + + void foo_alloc(size_t count) { + p = malloc(MAX(sizeof(struct foo), + offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); + p->count = count; + } + + void use_foo(int index, int val) { + p->count += SIZE_INCR + 1; /* 'count' is now larger than the number of elements of 'array'. */ + p->array[index] = val; /* The sanitizer can't properly check this access. */ + } + +In this example, an update to ``p->count`` maintains the relationship +requirement: + +.. code-block:: c + + void use_foo(int index, int val) { + if (p->count == 0) + return; + --p->count; + p->array[index] = val; + } + }]; +} diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 3884dca59e2f..1a79892e4003 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -6441,6 +6441,19 @@ def warn_superclass_variable_sized_type_not_at_end : Warning< "field %0 can overwrite instance variable %1 with variable sized type %2" " in superclass %3">, InGroup; +def err_flexible_array_count_not_in_same_struct : Error< + "'counted_by' field %0 isn't within the same struct as the flexible array">; +def err_counted_by_attr_not_on_flexible_array_member : Error< + "'counted_by' only applies to C99 flexible array members">; +def err_counted_by_attr_refers_to_flexible_array : Error< + "'counted_by' cannot refer to the flexible array %0">; +def err_counted_by_must_be_in_structure : Error< + "field %0 in 'counted_by' not inside structure">; +def err_flexible_array_counted_by_attr_field_not_integer : Error< + "field %0 in 'counted_by' must be a non-boolean integer type">; +def note_flexible_array_counted_by_attr_field : Note< + "field %0 declared here">; + let CategoryName = "ARC Semantic Issue" in { // ARC-mode diagnostics. diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index edaee4c4b66d..cf2d4fbe6d3b 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -4799,6 +4799,8 @@ public: bool CheckAlwaysInlineAttr(const Stmt *OrigSt, const Stmt *CurSt, const AttributeCommonInfo &A); + bool CheckCountedByAttr(Scope *Scope, const FieldDecl *FD); + /// Adjust the calling convention of a method to be the ABI default if it /// wasn't specified explicitly. This handles method types formed from /// function type typedefs and typename template arguments. @@ -5642,6 +5644,7 @@ public: CorrectionCandidateCallback &CCC, TemplateArgumentListInfo *ExplicitTemplateArgs = nullptr, ArrayRef Args = std::nullopt, + DeclContext *LookupCtx = nullptr, TypoExpr **Out = nullptr); DeclResult LookupIvarInObjCMethod(LookupResult &Lookup, Scope *S, diff --git a/clang/include/clang/Sema/TypoCorrection.h b/clang/include/clang/Sema/TypoCorrection.h index e0f8d152dbe5..09de164297e7 100644 --- a/clang/include/clang/Sema/TypoCorrection.h +++ b/clang/include/clang/Sema/TypoCorrection.h @@ -282,7 +282,7 @@ class CorrectionCandidateCallback { public: static const unsigned InvalidDistance = TypoCorrection::InvalidDistance; - explicit CorrectionCandidateCallback(IdentifierInfo *Typo = nullptr, + explicit CorrectionCandidateCallback(const IdentifierInfo *Typo = nullptr, NestedNameSpecifier *TypoNNS = nullptr) : Typo(Typo), TypoNNS(TypoNNS) {} @@ -319,7 +319,7 @@ public: /// this method. virtual std::unique_ptr clone() = 0; - void setTypoName(IdentifierInfo *II) { Typo = II; } + void setTypoName(const IdentifierInfo *II) { Typo = II; } void setTypoNNS(NestedNameSpecifier *NNS) { TypoNNS = NNS; } // Flags for context-dependent keywords. WantFunctionLikeCasts is only @@ -345,13 +345,13 @@ protected: candidate.getCorrectionSpecifier() == TypoNNS; } - IdentifierInfo *Typo; + const IdentifierInfo *Typo; NestedNameSpecifier *TypoNNS; }; class DefaultFilterCCC final : public CorrectionCandidateCallback { public: - explicit DefaultFilterCCC(IdentifierInfo *Typo = nullptr, + explicit DefaultFilterCCC(const IdentifierInfo *Typo = nullptr, NestedNameSpecifier *TypoNNS = nullptr) : CorrectionCandidateCallback(Typo, TypoNNS) {} @@ -365,6 +365,10 @@ public: template class DeclFilterCCC final : public CorrectionCandidateCallback { public: + explicit DeclFilterCCC(const IdentifierInfo *Typo = nullptr, + NestedNameSpecifier *TypoNNS = nullptr) + : CorrectionCandidateCallback(Typo, TypoNNS) {} + bool ValidateCandidate(const TypoCorrection &candidate) override { return candidate.getCorrectionDeclAs(); } diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 5e5570bb42a1..0540159f07e8 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -9030,6 +9030,10 @@ class AttrImporter { public: AttrImporter(ASTImporter &I) : Importer(I), NImporter(I) {} + // Useful for accessing the imported attribute. + template T *castAttrAs() { return cast(ToAttr); } + template const T *castAttrAs() const { return cast(ToAttr); } + // Create an "importer" for an attribute parameter. // Result of the 'value()' of that object is to be passed to the function // 'importAttr', in the order that is expected by the attribute class. @@ -9243,6 +9247,15 @@ Expected ASTImporter::Import(const Attr *FromAttr) { From->args_size()); break; } + case attr::CountedBy: { + AI.cloneAttr(FromAttr); + const auto *CBA = cast(FromAttr); + Expected SR = Import(CBA->getCountedByFieldLoc()).get(); + if (!SR) + return SR.takeError(); + AI.castAttrAs()->setCountedByFieldLoc(SR.get()); + break; + } default: { // The default branch works for attributes that have no arguments to import. diff --git a/clang/lib/AST/DeclBase.cpp b/clang/lib/AST/DeclBase.cpp index b1733c2d052a..8163f9bdaf8d 100644 --- a/clang/lib/AST/DeclBase.cpp +++ b/clang/lib/AST/DeclBase.cpp @@ -29,7 +29,6 @@ #include "clang/AST/Type.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LLVM.h" -#include "clang/Basic/LangOptions.h" #include "clang/Basic/Module.h" #include "clang/Basic/ObjCRuntime.h" #include "clang/Basic/PartialDiagnostic.h" @@ -411,6 +410,79 @@ bool Decl::isFileContextDecl() const { return DC && DC->isFileContext(); } +bool Decl::isFlexibleArrayMemberLike( + ASTContext &Ctx, const Decl *D, QualType Ty, + LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, + bool IgnoreTemplateOrMacroSubstitution) { + // For compatibility with existing code, we treat arrays of length 0 or + // 1 as flexible array members. + const auto *CAT = Ctx.getAsConstantArrayType(Ty); + if (CAT) { + using FAMKind = LangOptions::StrictFlexArraysLevelKind; + + llvm::APInt Size = CAT->getSize(); + if (StrictFlexArraysLevel == FAMKind::IncompleteOnly) + return false; + + // GCC extension, only allowed to represent a FAM. + if (Size.isZero()) + return true; + + if (StrictFlexArraysLevel == FAMKind::ZeroOrIncomplete && Size.uge(1)) + return false; + + if (StrictFlexArraysLevel == FAMKind::OneZeroOrIncomplete && Size.uge(2)) + return false; + } else if (!Ctx.getAsIncompleteArrayType(Ty)) { + return false; + } + + if (const auto *OID = dyn_cast_if_present(D)) + return OID->getNextIvar() == nullptr; + + const auto *FD = dyn_cast_if_present(D); + if (!FD) + return false; + + if (CAT) { + // GCC treats an array memeber of a union as an FAM if the size is one or + // zero. + llvm::APInt Size = CAT->getSize(); + if (FD->getParent()->isUnion() && (Size.isZero() || Size.isOne())) + return true; + } + + // Don't consider sizes resulting from macro expansions or template argument + // substitution to form C89 tail-padded arrays. + if (IgnoreTemplateOrMacroSubstitution) { + TypeSourceInfo *TInfo = FD->getTypeSourceInfo(); + while (TInfo) { + TypeLoc TL = TInfo->getTypeLoc(); + + // Look through typedefs. + if (TypedefTypeLoc TTL = TL.getAsAdjusted()) { + const TypedefNameDecl *TDL = TTL.getTypedefNameDecl(); + TInfo = TDL->getTypeSourceInfo(); + continue; + } + + if (auto CTL = TL.getAs()) { + if (const Expr *SizeExpr = + dyn_cast_if_present(CTL.getSizeExpr()); + !SizeExpr || SizeExpr->getExprLoc().isMacroID()) + return false; + } + + break; + } + } + + // Test that the field is the last in the structure. + RecordDecl::field_iterator FI( + DeclContext::decl_iterator(const_cast(FD))); + return ++FI == FD->getParent()->field_end(); +} + TranslationUnitDecl *Decl::getTranslationUnitDecl() { if (auto *TUD = dyn_cast(this)) return TUD; diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp index a90f92d07f86..b125fc676da8 100644 --- a/clang/lib/AST/Expr.cpp +++ b/clang/lib/AST/Expr.cpp @@ -205,85 +205,22 @@ bool Expr::isKnownToHaveBooleanValue(bool Semantic) const { } bool Expr::isFlexibleArrayMemberLike( - ASTContext &Context, + ASTContext &Ctx, LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, bool IgnoreTemplateOrMacroSubstitution) const { - - // For compatibility with existing code, we treat arrays of length 0 or - // 1 as flexible array members. - const auto *CAT = Context.getAsConstantArrayType(getType()); - if (CAT) { - llvm::APInt Size = CAT->getSize(); - - using FAMKind = LangOptions::StrictFlexArraysLevelKind; - - if (StrictFlexArraysLevel == FAMKind::IncompleteOnly) - return false; - - // GCC extension, only allowed to represent a FAM. - if (Size == 0) - return true; - - if (StrictFlexArraysLevel == FAMKind::ZeroOrIncomplete && Size.uge(1)) - return false; - - if (StrictFlexArraysLevel == FAMKind::OneZeroOrIncomplete && Size.uge(2)) - return false; - } else if (!Context.getAsIncompleteArrayType(getType())) - return false; - const Expr *E = IgnoreParens(); + const Decl *D = nullptr; - const NamedDecl *ND = nullptr; - if (const auto *DRE = dyn_cast(E)) - ND = DRE->getDecl(); - else if (const auto *ME = dyn_cast(E)) - ND = ME->getMemberDecl(); + if (const auto *ME = dyn_cast(E)) + D = ME->getMemberDecl(); + else if (const auto *DRE = dyn_cast(E)) + D = DRE->getDecl(); else if (const auto *IRE = dyn_cast(E)) - return IRE->getDecl()->getNextIvar() == nullptr; - - if (!ND) - return false; + D = IRE->getDecl(); - // A flexible array member must be the last member in the class. - // FIXME: If the base type of the member expr is not FD->getParent(), - // this should not be treated as a flexible array member access. - if (const auto *FD = dyn_cast(ND)) { - // GCC treats an array memeber of a union as an FAM if the size is one or - // zero. - if (CAT) { - llvm::APInt Size = CAT->getSize(); - if (FD->getParent()->isUnion() && (Size.isZero() || Size.isOne())) - return true; - } - - // Don't consider sizes resulting from macro expansions or template argument - // substitution to form C89 tail-padded arrays. - if (IgnoreTemplateOrMacroSubstitution) { - TypeSourceInfo *TInfo = FD->getTypeSourceInfo(); - while (TInfo) { - TypeLoc TL = TInfo->getTypeLoc(); - // Look through typedefs. - if (TypedefTypeLoc TTL = TL.getAsAdjusted()) { - const TypedefNameDecl *TDL = TTL.getTypedefNameDecl(); - TInfo = TDL->getTypeSourceInfo(); - continue; - } - if (ConstantArrayTypeLoc CTL = TL.getAs()) { - const Expr *SizeExpr = dyn_cast(CTL.getSizeExpr()); - if (!SizeExpr || SizeExpr->getExprLoc().isMacroID()) - return false; - } - break; - } - } - - RecordDecl::field_iterator FI( - DeclContext::decl_iterator(const_cast(FD))); - return ++FI == FD->getParent()->field_end(); - } - - return false; + return Decl::isFlexibleArrayMemberLike(Ctx, D, E->getType(), + StrictFlexArraysLevel, + IgnoreTemplateOrMacroSubstitution); } const ValueDecl * diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 1ed35befe136..998fcc3af581 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -25,6 +25,7 @@ #include "clang/AST/Attr.h" #include "clang/AST/Decl.h" #include "clang/AST/OSLog.h" +#include "clang/AST/OperationKinds.h" #include "clang/Basic/TargetBuiltins.h" #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" @@ -818,6 +819,238 @@ CodeGenFunction::evaluateOrEmitBuiltinObjectSize(const Expr *E, unsigned Type, return ConstantInt::get(ResType, ObjectSize, /*isSigned=*/true); } +const FieldDecl *CodeGenFunction::FindFlexibleArrayMemberField( + ASTContext &Ctx, const RecordDecl *RD, StringRef Name, uint64_t &Offset) { + const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = + getLangOpts().getStrictFlexArraysLevel(); + unsigned FieldNo = 0; + bool IsUnion = RD->isUnion(); + + for (const Decl *D : RD->decls()) { + if (const auto *Field = dyn_cast(D); + Field && (Name.empty() || Field->getNameAsString() == Name) && + Decl::isFlexibleArrayMemberLike( + Ctx, Field, Field->getType(), StrictFlexArraysLevel, + /*IgnoreTemplateOrMacroSubstitution=*/true)) { + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); + Offset += Layout.getFieldOffset(FieldNo); + return Field; + } + + if (const auto *Record = dyn_cast(D)) + if (const FieldDecl *Field = + FindFlexibleArrayMemberField(Ctx, Record, Name, Offset)) { + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); + Offset += Layout.getFieldOffset(FieldNo); + return Field; + } + + if (!IsUnion && isa(D)) + ++FieldNo; + } + + return nullptr; +} + +static unsigned CountCountedByAttrs(const RecordDecl *RD) { + unsigned Num = 0; + + for (const Decl *D : RD->decls()) { + if (const auto *FD = dyn_cast(D); + FD && FD->hasAttr()) { + return ++Num; + } + + if (const auto *Rec = dyn_cast(D)) + Num += CountCountedByAttrs(Rec); + } + + return Num; +} + +llvm::Value * +CodeGenFunction::emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, + llvm::IntegerType *ResType) { + // The code generated here calculates the size of a struct with a flexible + // array member that uses the counted_by attribute. There are two instances + // we handle: + // + // struct s { + // unsigned long flags; + // int count; + // int array[] __attribute__((counted_by(count))); + // } + // + // 1) bdos of the flexible array itself: + // + // __builtin_dynamic_object_size(p->array, 1) == + // p->count * sizeof(*p->array) + // + // 2) bdos of a pointer into the flexible array: + // + // __builtin_dynamic_object_size(&p->array[42], 1) == + // (p->count - 42) * sizeof(*p->array) + // + // 2) bdos of the whole struct, including the flexible array: + // + // __builtin_dynamic_object_size(p, 1) == + // max(sizeof(struct s), + // offsetof(struct s, array) + p->count * sizeof(*p->array)) + // + ASTContext &Ctx = getContext(); + const Expr *Base = E->IgnoreParenImpCasts(); + const Expr *Idx = nullptr; + + if (const auto *UO = dyn_cast(Base); + UO && UO->getOpcode() == UO_AddrOf) { + Expr *SubExpr = UO->getSubExpr()->IgnoreParenImpCasts(); + if (const auto *ASE = dyn_cast(SubExpr)) { + Base = ASE->getBase()->IgnoreParenImpCasts(); + Idx = ASE->getIdx()->IgnoreParenImpCasts(); + + if (const auto *IL = dyn_cast(Idx)) { + int64_t Val = IL->getValue().getSExtValue(); + if (Val < 0) + return getDefaultBuiltinObjectSizeResult(Type, ResType); + + if (Val == 0) + // The index is 0, so we don't need to take it into account. + Idx = nullptr; + } + } else { + // Potential pointer to another element in the struct. + Base = SubExpr; + } + } + + // Get the flexible array member Decl. + const RecordDecl *OuterRD = nullptr; + std::string FAMName; + if (const auto *ME = dyn_cast(Base)) { + // Check if \p Base is referencing the FAM itself. + const ValueDecl *VD = ME->getMemberDecl(); + OuterRD = VD->getDeclContext()->getOuterLexicalRecordContext(); + FAMName = VD->getNameAsString(); + } else if (const auto *DRE = dyn_cast(Base)) { + // Check if we're pointing to the whole struct. + QualType Ty = DRE->getDecl()->getType(); + if (Ty->isPointerType()) + Ty = Ty->getPointeeType(); + OuterRD = Ty->getAsRecordDecl(); + + // If we have a situation like this: + // + // struct union_of_fams { + // int flags; + // union { + // signed char normal_field; + // struct { + // int count1; + // int arr1[] __counted_by(count1); + // }; + // struct { + // signed char count2; + // int arr2[] __counted_by(count2); + // }; + // }; + // }; + // + // We don't konw which 'count' to use in this scenario: + // + // size_t get_size(struct union_of_fams *p) { + // return __builtin_dynamic_object_size(p, 1); + // } + // + // Instead of calculating a wrong number, we give up. + if (OuterRD && CountCountedByAttrs(OuterRD) > 1) + return nullptr; + } + + if (!OuterRD) + return nullptr; + + uint64_t Offset = 0; + const FieldDecl *FAMDecl = + FindFlexibleArrayMemberField(Ctx, OuterRD, FAMName, Offset); + Offset = Ctx.toCharUnitsFromBits(Offset).getQuantity(); + + if (!FAMDecl || !FAMDecl->hasAttr()) + // No flexible array member found or it doesn't have the "counted_by" + // attribute. + return nullptr; + + const FieldDecl *CountedByFD = FindCountedByField(FAMDecl); + if (!CountedByFD) + // Can't find the field referenced by the "counted_by" attribute. + return nullptr; + + // Build a load of the counted_by field. + bool IsSigned = CountedByFD->getType()->isSignedIntegerType(); + Value *CountedByInst = EmitCountedByFieldExpr(Base, FAMDecl, CountedByFD); + if (!CountedByInst) + return getDefaultBuiltinObjectSizeResult(Type, ResType); + + CountedByInst = Builder.CreateIntCast(CountedByInst, ResType, IsSigned); + + // Build a load of the index and subtract it from the count. + Value *IdxInst = nullptr; + if (Idx) { + if (Idx->HasSideEffects(getContext())) + // We can't have side-effects. + return getDefaultBuiltinObjectSizeResult(Type, ResType); + + bool IdxSigned = Idx->getType()->isSignedIntegerType(); + IdxInst = EmitAnyExprToTemp(Idx).getScalarVal(); + IdxInst = Builder.CreateIntCast(IdxInst, ResType, IdxSigned); + + // We go ahead with the calculation here. If the index turns out to be + // negative, we'll catch it at the end. + CountedByInst = + Builder.CreateSub(CountedByInst, IdxInst, "", !IsSigned, IsSigned); + } + + // Calculate how large the flexible array member is in bytes. + const ArrayType *ArrayTy = Ctx.getAsArrayType(FAMDecl->getType()); + CharUnits Size = Ctx.getTypeSizeInChars(ArrayTy->getElementType()); + llvm::Constant *ElemSize = + llvm::ConstantInt::get(ResType, Size.getQuantity(), IsSigned); + Value *FAMSize = + Builder.CreateMul(CountedByInst, ElemSize, "", !IsSigned, IsSigned); + FAMSize = Builder.CreateIntCast(FAMSize, ResType, IsSigned); + Value *Res = FAMSize; + + if (const auto *DRE = dyn_cast(Base)) { + // The whole struct is specificed in the __bdos. + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(OuterRD); + + // Get the offset of the FAM. + llvm::Constant *FAMOffset = ConstantInt::get(ResType, Offset, IsSigned); + Value *OffsetAndFAMSize = + Builder.CreateAdd(FAMOffset, Res, "", !IsSigned, IsSigned); + + // Get the full size of the struct. + llvm::Constant *SizeofStruct = + ConstantInt::get(ResType, Layout.getSize().getQuantity(), IsSigned); + + // max(sizeof(struct s), + // offsetof(struct s, array) + p->count * sizeof(*p->array)) + Res = IsSigned + ? Builder.CreateBinaryIntrinsic(llvm::Intrinsic::smax, + OffsetAndFAMSize, SizeofStruct) + : Builder.CreateBinaryIntrinsic(llvm::Intrinsic::umax, + OffsetAndFAMSize, SizeofStruct); + } + + // A negative \p IdxInst or \p CountedByInst means that the index lands + // outside of the flexible array member. If that's the case, we want to + // return 0. + Value *Cmp = Builder.CreateIsNotNeg(CountedByInst); + if (IdxInst) + Cmp = Builder.CreateAnd(Builder.CreateIsNotNeg(IdxInst), Cmp); + + return Builder.CreateSelect(Cmp, Res, ConstantInt::get(ResType, 0, IsSigned)); +} + /// Returns a Value corresponding to the size of the given expression. /// This Value may be either of the following: /// - A llvm::Argument (if E is a param with the pass_object_size attribute on @@ -850,6 +1083,13 @@ CodeGenFunction::emitBuiltinObjectSize(const Expr *E, unsigned Type, } } + if (IsDynamic) { + // Emit special code for a flexible array member with the "counted_by" + // attribute. + if (Value *V = emitFlexibleArrayMemberSize(E, Type, ResType)) + return V; + } + // LLVM can't handle Type=3 appropriately, and __builtin_object_size shouldn't // evaluate E for side-effects. In either case, we shouldn't lower to // @llvm.objectsize. diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 3f277725d9e7..d12e85b48d0b 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -26,10 +26,12 @@ #include "clang/AST/Attr.h" #include "clang/AST/DeclObjC.h" #include "clang/AST/NSAPI.h" +#include "clang/AST/StmtVisitor.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/CodeGenOptions.h" #include "clang/Basic/SourceManager.h" #include "llvm/ADT/Hashing.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Intrinsics.h" @@ -925,16 +927,21 @@ static llvm::Value *getArrayIndexingBound(CodeGenFunction &CGF, if (CE->getCastKind() == CK_ArrayToPointerDecay && !CE->getSubExpr()->isFlexibleArrayMemberLike(CGF.getContext(), StrictFlexArraysLevel)) { + CodeGenFunction::SanitizerScope SanScope(&CGF); + IndexedType = CE->getSubExpr()->getType(); const ArrayType *AT = IndexedType->castAsArrayTypeUnsafe(); if (const auto *CAT = dyn_cast(AT)) return CGF.Builder.getInt(CAT->getSize()); - else if (const auto *VAT = dyn_cast(AT)) + + if (const auto *VAT = dyn_cast(AT)) return CGF.getVLASize(VAT).NumElts; // Ignore pass_object_size here. It's not applicable on decayed pointers. } } + CodeGenFunction::SanitizerScope SanScope(&CGF); + QualType EltTy{Base->getType()->getPointeeOrArrayElementType(), 0}; if (llvm::Value *POS = CGF.LoadPassedObjectSize(Base, EltTy)) { IndexedType = Base->getType(); @@ -944,22 +951,248 @@ static llvm::Value *getArrayIndexingBound(CodeGenFunction &CGF, return nullptr; } +namespace { + +/// \p StructAccessBase returns the base \p Expr of a field access. It returns +/// either a \p DeclRefExpr, representing the base pointer to the struct, i.e.: +/// +/// p in p-> a.b.c +/// +/// or a \p MemberExpr, if the \p MemberExpr has the \p RecordDecl we're +/// looking for: +/// +/// struct s { +/// struct s *ptr; +/// int count; +/// char array[] __attribute__((counted_by(count))); +/// }; +/// +/// If we have an expression like \p p->ptr->array[index], we want the +/// \p MemberExpr for \p p->ptr instead of \p p. +class StructAccessBase + : public ConstStmtVisitor { + const RecordDecl *ExpectedRD; + + bool IsExpectedRecordDecl(const Expr *E) const { + QualType Ty = E->getType(); + if (Ty->isPointerType()) + Ty = Ty->getPointeeType(); + return ExpectedRD == Ty->getAsRecordDecl(); + } + +public: + StructAccessBase(const RecordDecl *ExpectedRD) : ExpectedRD(ExpectedRD) {} + + //===--------------------------------------------------------------------===// + // Visitor Methods + //===--------------------------------------------------------------------===// + + // NOTE: If we build C++ support for counted_by, then we'll have to handle + // horrors like this: + // + // struct S { + // int x, y; + // int blah[] __attribute__((counted_by(x))); + // } s; + // + // int foo(int index, int val) { + // int (S::*IHatePMDs)[] = &S::blah; + // (s.*IHatePMDs)[index] = val; + // } + + const Expr *Visit(const Expr *E) { + return ConstStmtVisitor::Visit(E); + } + + const Expr *VisitStmt(const Stmt *S) { return nullptr; } + + // These are the types we expect to return (in order of most to least + // likely): + // + // 1. DeclRefExpr - This is the expression for the base of the structure. + // It's exactly what we want to build an access to the \p counted_by + // field. + // 2. MemberExpr - This is the expression that has the same \p RecordDecl + // as the flexble array member's lexical enclosing \p RecordDecl. This + // allows us to catch things like: "p->p->array" + // 3. CompoundLiteralExpr - This is for people who create something + // heretical like (struct foo has a flexible array member): + // + // (struct foo){ 1, 2 }.blah[idx]; + const Expr *VisitDeclRefExpr(const DeclRefExpr *E) { + return IsExpectedRecordDecl(E) ? E : nullptr; + } + const Expr *VisitMemberExpr(const MemberExpr *E) { + if (IsExpectedRecordDecl(E) && E->isArrow()) + return E; + const Expr *Res = Visit(E->getBase()); + return !Res && IsExpectedRecordDecl(E) ? E : Res; + } + const Expr *VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) { + return IsExpectedRecordDecl(E) ? E : nullptr; + } + const Expr *VisitCallExpr(const CallExpr *E) { + return IsExpectedRecordDecl(E) ? E : nullptr; + } + + const Expr *VisitArraySubscriptExpr(const ArraySubscriptExpr *E) { + if (IsExpectedRecordDecl(E)) + return E; + return Visit(E->getBase()); + } + const Expr *VisitCastExpr(const CastExpr *E) { + return Visit(E->getSubExpr()); + } + const Expr *VisitParenExpr(const ParenExpr *E) { + return Visit(E->getSubExpr()); + } + const Expr *VisitUnaryAddrOf(const UnaryOperator *E) { + return Visit(E->getSubExpr()); + } + const Expr *VisitUnaryDeref(const UnaryOperator *E) { + return Visit(E->getSubExpr()); + } +}; + +} // end anonymous namespace + +using RecIndicesTy = + SmallVector, 8>; + +static bool getGEPIndicesToField(CodeGenFunction &CGF, const RecordDecl *RD, + const FieldDecl *FD, RecIndicesTy &Indices) { + const CGRecordLayout &Layout = CGF.CGM.getTypes().getCGRecordLayout(RD); + int64_t FieldNo = -1; + for (const Decl *D : RD->decls()) { + if (const auto *Field = dyn_cast(D)) { + FieldNo = Layout.getLLVMFieldNo(Field); + if (FD == Field) { + Indices.emplace_back(std::make_pair(RD, CGF.Builder.getInt32(FieldNo))); + return true; + } + } + + if (const auto *Record = dyn_cast(D)) { + ++FieldNo; + if (getGEPIndicesToField(CGF, Record, FD, Indices)) { + if (RD->isUnion()) + FieldNo = 0; + Indices.emplace_back(std::make_pair(RD, CGF.Builder.getInt32(FieldNo))); + return true; + } + } + } + + return false; +} + +/// This method is typically called in contexts where we can't generate +/// side-effects, like in __builtin_dynamic_object_size. When finding +/// expressions, only choose those that have either already been emitted or can +/// be loaded without side-effects. +/// +/// - \p FAMDecl: the \p Decl for the flexible array member. It may not be +/// within the top-level struct. +/// - \p CountDecl: must be within the same non-anonymous struct as \p FAMDecl. +llvm::Value *CodeGenFunction::EmitCountedByFieldExpr( + const Expr *Base, const FieldDecl *FAMDecl, const FieldDecl *CountDecl) { + const RecordDecl *RD = CountDecl->getParent()->getOuterLexicalRecordContext(); + + // Find the base struct expr (i.e. p in p->a.b.c.d). + const Expr *StructBase = StructAccessBase(RD).Visit(Base); + if (!StructBase || StructBase->HasSideEffects(getContext())) + return nullptr; + + llvm::Value *Res = nullptr; + if (const auto *DRE = dyn_cast(StructBase)) { + Res = EmitDeclRefLValue(DRE).getPointer(*this); + Res = Builder.CreateAlignedLoad(ConvertType(DRE->getType()), Res, + getPointerAlign(), "dre.load"); + } else if (const MemberExpr *ME = dyn_cast(StructBase)) { + LValue LV = EmitMemberExpr(ME); + Address Addr = LV.getAddress(*this); + Res = Addr.getPointer(); + } else if (StructBase->getType()->isPointerType()) { + LValueBaseInfo BaseInfo; + TBAAAccessInfo TBAAInfo; + Address Addr = EmitPointerWithAlignment(StructBase, &BaseInfo, &TBAAInfo); + Res = Addr.getPointer(); + } else { + return nullptr; + } + + llvm::Value *Zero = Builder.getInt32(0); + RecIndicesTy Indices; + + getGEPIndicesToField(*this, RD, CountDecl, Indices); + + for (auto I = Indices.rbegin(), E = Indices.rend(); I != E; ++I) + Res = Builder.CreateInBoundsGEP( + ConvertType(QualType(I->first->getTypeForDecl(), 0)), Res, + {Zero, I->second}, "..counted_by.gep"); + + return Builder.CreateAlignedLoad(ConvertType(CountDecl->getType()), Res, + getIntAlign(), "..counted_by.load"); +} + +const FieldDecl *CodeGenFunction::FindCountedByField(const FieldDecl *FD) { + if (!FD || !FD->hasAttr()) + return nullptr; + + const auto *CBA = FD->getAttr(); + if (!CBA) + return nullptr; + + auto GetNonAnonStructOrUnion = + [](const RecordDecl *RD) -> const RecordDecl * { + while (RD && RD->isAnonymousStructOrUnion()) { + const auto *R = dyn_cast(RD->getDeclContext()); + if (!R) + return nullptr; + RD = R; + } + return RD; + }; + const RecordDecl *EnclosingRD = GetNonAnonStructOrUnion(FD->getParent()); + if (!EnclosingRD) + return nullptr; + + DeclarationName DName(CBA->getCountedByField()); + DeclContext::lookup_result Lookup = EnclosingRD->lookup(DName); + + if (Lookup.empty()) + return nullptr; + + const NamedDecl *ND = Lookup.front(); + if (const auto *IFD = dyn_cast(ND)) + ND = IFD->getAnonField(); + + return dyn_cast(ND); +} + void CodeGenFunction::EmitBoundsCheck(const Expr *E, const Expr *Base, llvm::Value *Index, QualType IndexType, bool Accessed) { assert(SanOpts.has(SanitizerKind::ArrayBounds) && "should not be called unless adding bounds checks"); - SanitizerScope SanScope(this); - const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = - getLangOpts().getStrictFlexArraysLevel(); - + getLangOpts().getStrictFlexArraysLevel(); QualType IndexedType; llvm::Value *Bound = getArrayIndexingBound(*this, Base, IndexedType, StrictFlexArraysLevel); + + EmitBoundsCheckImpl(E, Bound, Index, IndexType, IndexedType, Accessed); +} + +void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, + llvm::Value *Index, + QualType IndexType, + QualType IndexedType, bool Accessed) { if (!Bound) return; + SanitizerScope SanScope(this); + bool IndexSigned = IndexType->isSignedIntegerOrEnumerationType(); llvm::Value *IndexVal = Builder.CreateIntCast(Index, SizeTy, IndexSigned); llvm::Value *BoundVal = Builder.CreateIntCast(Bound, SizeTy, false); @@ -975,7 +1208,6 @@ void CodeGenFunction::EmitBoundsCheck(const Expr *E, const Expr *Base, SanitizerHandler::OutOfBounds, StaticData, Index); } - CodeGenFunction::ComplexPairTy CodeGenFunction:: EmitComplexPrePostIncDec(const UnaryOperator *E, LValue LV, bool isInc, bool isPre) { @@ -3823,6 +4055,61 @@ static Address emitArraySubscriptGEP(CodeGenFunction &CGF, Address addr, return Address(eltPtr, CGF.ConvertTypeForMem(eltType), eltAlign); } +/// The offset of a field from the beginning of the record. +static bool getFieldOffsetInBits(CodeGenFunction &CGF, const RecordDecl *RD, + const FieldDecl *FD, int64_t &Offset) { + ASTContext &Ctx = CGF.getContext(); + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); + unsigned FieldNo = 0; + + for (const Decl *D : RD->decls()) { + if (const auto *Record = dyn_cast(D)) + if (getFieldOffsetInBits(CGF, Record, FD, Offset)) { + Offset += Layout.getFieldOffset(FieldNo); + return true; + } + + if (const auto *Field = dyn_cast(D)) + if (FD == Field) { + Offset += Layout.getFieldOffset(FieldNo); + return true; + } + + if (isa(D)) + ++FieldNo; + } + + return false; +} + +/// Returns the relative offset difference between \p FD1 and \p FD2. +/// \code +/// offsetof(struct foo, FD1) - offsetof(struct foo, FD2) +/// \endcode +/// Both fields must be within the same struct. +static std::optional getOffsetDifferenceInBits(CodeGenFunction &CGF, + const FieldDecl *FD1, + const FieldDecl *FD2) { + const RecordDecl *FD1OuterRec = + FD1->getParent()->getOuterLexicalRecordContext(); + const RecordDecl *FD2OuterRec = + FD2->getParent()->getOuterLexicalRecordContext(); + + if (FD1OuterRec != FD2OuterRec) + // Fields must be within the same RecordDecl. + return std::optional(); + + int64_t FD1Offset = 0; + if (!getFieldOffsetInBits(CGF, FD1OuterRec, FD1, FD1Offset)) + return std::optional(); + + int64_t FD2Offset = 0; + if (!getFieldOffsetInBits(CGF, FD2OuterRec, FD2, FD2Offset)) + return std::optional(); + + return std::make_optional(FD1Offset - FD2Offset); +} + LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E, bool Accessed) { // The index must always be an integer, which is not an aggregate. Emit it @@ -3950,6 +4237,47 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E, ArrayLV = EmitLValue(Array); auto *Idx = EmitIdxAfterBase(/*Promote*/true); + if (SanOpts.has(SanitizerKind::ArrayBounds)) { + // If the array being accessed has a "counted_by" attribute, generate + // bounds checking code. The "count" field is at the top level of the + // struct or in an anonymous struct, that's also at the top level. Future + // expansions may allow the "count" to reside at any place in the struct, + // but the value of "counted_by" will be a "simple" path to the count, + // i.e. "a.b.count", so we shouldn't need the full force of EmitLValue or + // similar to emit the correct GEP. + const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = + getLangOpts().getStrictFlexArraysLevel(); + + if (const auto *ME = dyn_cast(Array); + ME && + ME->isFlexibleArrayMemberLike(getContext(), StrictFlexArraysLevel) && + ME->getMemberDecl()->hasAttr()) { + const FieldDecl *FAMDecl = dyn_cast(ME->getMemberDecl()); + if (const FieldDecl *CountFD = FindCountedByField(FAMDecl)) { + if (std::optional Diff = + getOffsetDifferenceInBits(*this, CountFD, FAMDecl)) { + CharUnits OffsetDiff = CGM.getContext().toCharUnitsFromBits(*Diff); + + // Create a GEP with a byte offset between the FAM and count and + // use that to load the count value. + Addr = Builder.CreatePointerBitCastOrAddrSpaceCast( + ArrayLV.getAddress(*this), Int8PtrTy, Int8Ty); + + llvm::Type *CountTy = ConvertType(CountFD->getType()); + llvm::Value *Res = Builder.CreateInBoundsGEP( + Int8Ty, Addr.getPointer(), + Builder.getInt32(OffsetDiff.getQuantity()), ".counted_by.gep"); + Res = Builder.CreateAlignedLoad(CountTy, Res, getIntAlign(), + ".counted_by.load"); + + // Now emit the bounds checking. + EmitBoundsCheckImpl(E, Res, Idx, E->getIdx()->getType(), + Array->getType(), Accessed); + } + } + } + } + // Propagate the alignment from the array itself to the result. QualType arrayType = Array->getType(); Addr = emitArraySubscriptGEP( diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 07c7678df87e..143ad64e8816 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3073,6 +3073,25 @@ public: /// this expression is used as an lvalue, for instance in "&Arr[Idx]". void EmitBoundsCheck(const Expr *E, const Expr *Base, llvm::Value *Index, QualType IndexType, bool Accessed); + void EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, + llvm::Value *Index, QualType IndexType, + QualType IndexedType, bool Accessed); + + // Find a struct's flexible array member. It may be embedded inside multiple + // sub-structs, but must still be the last field. + const FieldDecl *FindFlexibleArrayMemberField(ASTContext &Ctx, + const RecordDecl *RD, + StringRef Name, + uint64_t &Offset); + + /// Find the FieldDecl specified in a FAM's "counted_by" attribute. Returns + /// \p nullptr if either the attribute or the field doesn't exist. + const FieldDecl *FindCountedByField(const FieldDecl *FD); + + /// Build an expression accessing the "counted_by" field. + llvm::Value *EmitCountedByFieldExpr(const Expr *Base, + const FieldDecl *FAMDecl, + const FieldDecl *CountDecl); llvm::Value *EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, bool isInc, bool isPre); @@ -4873,6 +4892,9 @@ private: llvm::Value *EmittedE, bool IsDynamic); + llvm::Value *emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, + llvm::IntegerType *ResType); + void emitZeroOrPatternForAutoVarInit(QualType type, const VarDecl &D, Address Loc); diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 8e46c4984d93..e92fd104d78e 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -2315,6 +2315,12 @@ void Sema::ActOnPopScope(SourceLocation Loc, Scope *S) { } ShadowingDecls.erase(ShadowI); } + + if (!getLangOpts().CPlusPlus && S->isClassScope()) { + if (auto *FD = dyn_cast(TmpD); + FD && FD->hasAttr()) + CheckCountedByAttr(S, FD); + } } llvm::sort(DeclDiags, diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index d059b406ef86..1a58cfd8e417 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -8460,6 +8460,135 @@ static void handleZeroCallUsedRegsAttr(Sema &S, Decl *D, const ParsedAttr &AL) { D->addAttr(ZeroCallUsedRegsAttr::Create(S.Context, Kind, AL)); } +static void handleCountedByAttr(Sema &S, Decl *D, const ParsedAttr &AL) { + if (!AL.isArgIdent(0)) { + S.Diag(AL.getLoc(), diag::err_attribute_argument_type) + << AL << AANT_ArgumentIdentifier; + return; + } + + IdentifierLoc *IL = AL.getArgAsIdent(0); + CountedByAttr *CBA = + ::new (S.Context) CountedByAttr(S.Context, AL, IL->Ident); + CBA->setCountedByFieldLoc(IL->Loc); + D->addAttr(CBA); +} + +static const FieldDecl * +FindFieldInTopLevelOrAnonymousStruct(const RecordDecl *RD, + const IdentifierInfo *FieldName) { + for (const Decl *D : RD->decls()) { + if (const auto *FD = dyn_cast(D)) + if (FD->getName() == FieldName->getName()) + return FD; + + if (const auto *R = dyn_cast(D)) + if (const FieldDecl *FD = + FindFieldInTopLevelOrAnonymousStruct(R, FieldName)) + return FD; + } + + return nullptr; +} + +bool Sema::CheckCountedByAttr(Scope *S, const FieldDecl *FD) { + LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = + LangOptions::StrictFlexArraysLevelKind::IncompleteOnly; + if (!Decl::isFlexibleArrayMemberLike(Context, FD, FD->getType(), + StrictFlexArraysLevel, true)) { + // The "counted_by" attribute must be on a flexible array member. + SourceRange SR = FD->getLocation(); + Diag(SR.getBegin(), diag::err_counted_by_attr_not_on_flexible_array_member) + << SR; + return true; + } + + const auto *CBA = FD->getAttr(); + const IdentifierInfo *FieldName = CBA->getCountedByField(); + + auto GetNonAnonStructOrUnion = [](const RecordDecl *RD) { + while (RD && !RD->getDeclName()) + if (const auto *R = dyn_cast(RD->getDeclContext())) + RD = R; + else + break; + + return RD; + }; + + const RecordDecl *EnclosingRD = GetNonAnonStructOrUnion(FD->getParent()); + const FieldDecl *CountFD = + FindFieldInTopLevelOrAnonymousStruct(EnclosingRD, FieldName); + + if (!CountFD) { + DeclarationNameInfo NameInfo(FieldName, + CBA->getCountedByFieldLoc().getBegin()); + LookupResult MemResult(*this, NameInfo, Sema::LookupMemberName); + LookupName(MemResult, S); + + if (!MemResult.empty()) { + SourceRange SR = CBA->getCountedByFieldLoc(); + Diag(SR.getBegin(), diag::err_flexible_array_count_not_in_same_struct) + << CBA->getCountedByField() << SR; + + if (auto *ND = MemResult.getAsSingle()) { + SR = ND->getLocation(); + Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) + << ND << SR; + } + + return true; + } else { + // The "counted_by" field needs to exist in the struct. + LookupResult OrdResult(*this, NameInfo, Sema::LookupOrdinaryName); + LookupName(OrdResult, S); + + if (!OrdResult.empty()) { + SourceRange SR = FD->getLocation(); + Diag(SR.getBegin(), diag::err_counted_by_must_be_in_structure) + << FieldName << SR; + + if (auto *ND = OrdResult.getAsSingle()) { + SR = ND->getLocation(); + Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) + << ND << SR; + } + + return true; + } + } + + CXXScopeSpec SS; + DeclFilterCCC Filter(FieldName); + return DiagnoseEmptyLookup(S, SS, MemResult, Filter, nullptr, std::nullopt, + const_cast(FD->getDeclContext())); + } + + if (CountFD->hasAttr()) { + // The "counted_by" field can't point to the flexible array member. + SourceRange SR = CBA->getCountedByFieldLoc(); + Diag(SR.getBegin(), diag::err_counted_by_attr_refers_to_flexible_array) + << CBA->getCountedByField() << SR; + return true; + } + + if (!CountFD->getType()->isIntegerType() || + CountFD->getType()->isBooleanType()) { + // The "counted_by" field must have an integer type. + SourceRange SR = CBA->getCountedByFieldLoc(); + Diag(SR.getBegin(), + diag::err_flexible_array_counted_by_attr_field_not_integer) + << CBA->getCountedByField() << SR; + + SR = CountFD->getLocation(); + Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) + << CountFD << SR; + return true; + } + + return false; +} + static void handleFunctionReturnThunksAttr(Sema &S, Decl *D, const ParsedAttr &AL) { StringRef KindStr; @@ -9420,6 +9549,10 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, handleAvailableOnlyInDefaultEvalMethod(S, D, AL); break; + case ParsedAttr::AT_CountedBy: + handleCountedByAttr(S, D, AL); + break; + // Microsoft attributes: case ParsedAttr::AT_LayoutVersion: handleLayoutVersion(S, D, AL); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 60ad035570c8..2f48ea237cdf 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -2469,7 +2469,8 @@ bool Sema::DiagnoseDependentMemberLookup(const LookupResult &R) { bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, CorrectionCandidateCallback &CCC, TemplateArgumentListInfo *ExplicitTemplateArgs, - ArrayRef Args, TypoExpr **Out) { + ArrayRef Args, DeclContext *LookupCtx, + TypoExpr **Out) { DeclarationName Name = R.getLookupName(); unsigned diagnostic = diag::err_undeclared_var_use; @@ -2485,7 +2486,8 @@ bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, // unqualified lookup. This is useful when (for example) the // original lookup would not have found something because it was a // dependent name. - DeclContext *DC = SS.isEmpty() ? CurContext : nullptr; + DeclContext *DC = + LookupCtx ? LookupCtx : (SS.isEmpty() ? CurContext : nullptr); while (DC) { if (isa(DC)) { LookupQualifiedName(R, DC); @@ -2528,12 +2530,12 @@ bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, emitEmptyLookupTypoDiagnostic(TC, *this, SS, Name, TypoLoc, Args, diagnostic, diagnostic_suggest); }, - nullptr, CTK_ErrorRecovery); + nullptr, CTK_ErrorRecovery, LookupCtx); if (*Out) return true; - } else if (S && - (Corrected = CorrectTypo(R.getLookupNameInfo(), R.getLookupKind(), - S, &SS, CCC, CTK_ErrorRecovery))) { + } else if (S && (Corrected = + CorrectTypo(R.getLookupNameInfo(), R.getLookupKind(), S, + &SS, CCC, CTK_ErrorRecovery, LookupCtx))) { std::string CorrectedStr(Corrected.getAsString(getLangOpts())); bool DroppedSpecifier = Corrected.WillReplaceSpecifier() && Name.getAsString() == CorrectedStr; @@ -2823,7 +2825,7 @@ Sema::ActOnIdExpression(Scope *S, CXXScopeSpec &SS, // a template name, but we happen to have always already looked up the name // before we get here if it must be a template name. if (DiagnoseEmptyLookup(S, SS, R, CCC ? *CCC : DefaultValidator, nullptr, - std::nullopt, &TE)) { + std::nullopt, nullptr, &TE)) { if (TE && KeywordReplacement) { auto &State = getTypoExprState(TE); auto BestTC = State.Consumer->getNextCorrection(); diff --git a/clang/test/CodeGen/attr-counted-by.c b/clang/test/CodeGen/attr-counted-by.c new file mode 100644 index 000000000000..c59749acc536 --- /dev/null +++ b/clang/test/CodeGen/attr-counted-by.c @@ -0,0 +1,1828 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -DCOUNTED_BY -O2 -Wall -fsanitize=array-bounds,object-size,local-bounds -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=SANITIZE-WITH-ATTR %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -DCOUNTED_BY -O2 -Wall -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=NO-SANITIZE-WITH-ATTR %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O2 -Wall -fsanitize=array-bounds,object-size,local-bounds -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=SANITIZE-WITHOUT-ATTR %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O2 -Wall -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=NO-SANITIZE-WITHOUT-ATTR %s + +#if !__has_attribute(counted_by) +#error "has attribute broken" +#endif + +#ifdef COUNTED_BY +#define __counted_by(member) __attribute__((__counted_by__(member))) +#else +#define __counted_by(member) +#endif + +#define DECLARE_FLEX_ARRAY(TYPE, NAME) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[]; \ + } + +#define DECLARE_BOUNDED_FLEX_ARRAY(COUNT_TYPE, COUNT, TYPE, NAME) \ + struct { \ + COUNT_TYPE COUNT; \ + TYPE NAME[] __counted_by(COUNT); \ + } + +#define DECLARE_FLEX_ARRAY_COUNTED_BY(TYPE, NAME, COUNTED_BY) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[] __counted_by(COUNTED_BY); \ + } + +typedef long unsigned int size_t; + +struct annotated { + unsigned long flags; + int count; + int array[] __counted_by(count); +}; + +struct union_of_fams { + unsigned long flags; + union { + /* count member type intentionally mismatched to induce padding */ + DECLARE_BOUNDED_FLEX_ARRAY(int, count_bytes, unsigned char, bytes); + DECLARE_BOUNDED_FLEX_ARRAY(unsigned char, count_ints, unsigned char, ints); + DECLARE_FLEX_ARRAY(unsigned char, unsafe); + }; +}; + +struct anon_struct { + unsigned long flags; + size_t count; + DECLARE_FLEX_ARRAY_COUNTED_BY(int, array, count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test1( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3:![0-9]+]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB2:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12:[0-9]+]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test1( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test1( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test1( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test1(struct annotated *p, int index, int val) { + p->array[index] = val; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test2( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], [[INDEX]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB4:[0-9]+]], i64 [[INDEX]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP2]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test2( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP0]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test2( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test2( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test2(struct annotated *p, size_t index) { + p->array[index] = __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test2_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 [[TMP1]], i64 0 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP3]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test2_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 [[TMP1]], i64 0 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP3]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test2_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test2_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test2_bdos(struct annotated *p) { + return __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test3( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], [[INDEX]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB5:[0-9]+]], i64 [[INDEX]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP3]], i64 4) +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 12 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP6]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test3( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP4]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test3( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test3( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test3(struct annotated *p, size_t index) { + // This test differs from 'test2' by checking bdos on the whole array and not + // just the FAM. + p->array[index] = __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test3_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 12 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP3]], i64 0 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP5]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test3_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR5:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP3]], i64 0 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP5]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test3_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test3_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test3_bdos(struct annotated *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test4( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT4:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB6:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont4: +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 244 +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 252 +// SANITIZE-WITH-ATTR-NEXT: [[CONV1:%.*]] = select i1 [[TMP2]], i32 [[TMP5]], i32 0 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV1]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD7:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM13:%.*]] = sext i32 [[ADD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD7]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = icmp ult i64 [[IDXPROM13]], [[TMP6]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP7]], label [[CONT20:%.*]], label [[HANDLER_OUT_OF_BOUNDS16:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds16: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB7:[0-9]+]], i64 [[IDXPROM13]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont20: +// SANITIZE-WITH-ATTR-NEXT: [[TMP8:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD7]], 3 +// SANITIZE-WITH-ATTR-NEXT: [[TMP9:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD7]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 240 +// SANITIZE-WITH-ATTR-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 252 +// SANITIZE-WITH-ATTR-NEXT: [[CONV9:%.*]] = select i1 [[TMP8]], i32 [[TMP11]], i32 0 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM13]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV9]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD23:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[ADD29:%.*]] = add nsw i32 [[INDEX]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM30:%.*]] = sext i32 [[ADD29]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP12:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD23]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP13:%.*]] = icmp ult i64 [[IDXPROM30]], [[TMP12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP13]], label [[CONT37:%.*]], label [[HANDLER_OUT_OF_BOUNDS33:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds33: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB8:[0-9]+]], i64 [[IDXPROM30]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont37: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM30]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP14:%.*]] = icmp sgt i32 [[FAM_IDX]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP15:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD23]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP16:%.*]] = sext i32 [[FAM_IDX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP17:%.*]] = sub nsw i64 [[TMP15]], [[TMP16]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[TMP17]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP19:%.*]] = and i1 [[TMP14]], [[TMP18]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTTR:%.*]] = trunc i64 [[TMP17]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP20:%.*]] = shl i32 [[DOTTR]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP21:%.*]] = and i32 [[TMP20]], 252 +// SANITIZE-WITH-ATTR-NEXT: [[CONV25:%.*]] = select i1 [[TMP19]], i32 [[TMP21]], i32 0 +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV25]], ptr [[ARRAYIDX35]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test4( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 244 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 252 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV1:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV1]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD4:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD4]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 240 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD4]], 3 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = and i32 [[TMP5]], 252 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV6:%.*]] = select i1 [[TMP6]], i32 [[TMP7]], i32 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM8:%.*]] = sext i32 [[ADD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM8]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV6]], ptr [[ARRAYIDX9]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD12:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP8:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD12]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP9:%.*]] = sext i32 [[FAM_IDX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP10:%.*]] = sub nsw i64 [[TMP8]], [[TMP9]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP11:%.*]] = icmp sgt i64 [[TMP10]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP12:%.*]] = icmp sgt i32 [[FAM_IDX]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP13:%.*]] = and i1 [[TMP12]], [[TMP11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTTR:%.*]] = trunc i64 [[TMP10]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP14:%.*]] = shl i32 [[DOTTR]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP15:%.*]] = and i32 [[TMP14]], 252 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV14:%.*]] = select i1 [[TMP13]], i32 [[TMP15]], i32 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ADD16:%.*]] = add nsw i32 [[INDEX]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM17:%.*]] = sext i32 [[ADD16]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM17]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV14]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test4( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM17:%.*]] = sext i32 [[ADD]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM17]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[ADD31:%.*]] = add nsw i32 [[INDEX]], 2 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM32:%.*]] = sext i32 [[ADD31]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM32]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX33]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test4( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX3]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM9:%.*]] = sext i32 [[ADD]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM9]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX10]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ADD17:%.*]] = add nsw i32 [[INDEX]], 2 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM18:%.*]] = sext i32 [[ADD17]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM18]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX19]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test4(struct annotated *p, int index, int fam_idx) { + // This tests calculating the size from a pointer inside the FAM. + p->array[index] = (unsigned char)__builtin_dynamic_object_size(&p->array[3], 1); + p->array[index + 1] = (unsigned char)__builtin_dynamic_object_size(&(p->array[4]), 1); + p->array[index + 2] = (unsigned char)__builtin_dynamic_object_size(&(p->array[fam_idx]), 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test4_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sub nsw i64 [[TMP0]], [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i64 [[TMP2]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[INDEX]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = and i1 [[TMP5]], [[TMP4]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 [[TMP3]], i64 0 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP7]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test4_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sub nsw i64 [[TMP0]], [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i64 [[TMP2]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[INDEX]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = and i1 [[TMP5]], [[TMP4]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 [[TMP3]], i64 0 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP7]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test4_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test4_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test4_bdos(struct annotated *p, int index) { + return __builtin_dynamic_object_size(&p->array[index], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test5( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[DOT_COUNTED_BY_LOAD]], [[IDXPROM]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB9:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 16 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP2]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test5( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 16 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test5( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test5( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test5(struct anon_struct *p, int index) { + p->array[index] = __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test5_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add nuw i64 [[TMP0]], 16 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test5_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add nuw i64 [[TMP0]], 16 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP2]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test5_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test5_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test5_bdos(struct anon_struct *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test6( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[DOT_COUNTED_BY_LOAD]], [[IDXPROM]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB10:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test6( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP0]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test6( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test6( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test6(struct anon_struct *p, int index) { + p->array[index] = __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test6_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP0]] +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP1]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test6_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP0]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP1]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test6_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test6_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test6_bdos(struct anon_struct *p) { + return __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test7( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i8, ptr [[TMP0]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i8 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP1]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT7:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB12:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont7: +// SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test7( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test7( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test7( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test7(struct union_of_fams *p, int index) { + p->ints[index] = __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test7_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR5:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test7_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test7_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test7_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test7_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test8( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT9:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB13:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont9: +// SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i8 [[DOT_COUNTED_BY_LOAD]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test8( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 [[DOT_COUNTED_BY_LOAD]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test8( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test8( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test8(struct union_of_fams *p, int index) { + p->ints[index] = __builtin_dynamic_object_size(p->ints, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test8_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test8_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test8_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test8_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test8_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p->ints, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test9( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[TMP0]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP1]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT7:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB14:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont7: +// SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test9( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR6]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test9( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test9( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test9(struct union_of_fams *p, int index) { + p->bytes[index] = (unsigned char)__builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test9_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR5]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test9_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR7]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test9_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test9_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test9_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test10( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT9:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB15:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont9: +// SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = trunc i32 [[NARROW]] to i8 +// SANITIZE-WITH-ATTR-NEXT: store i8 [[CONV]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test10( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR3]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = trunc i32 [[NARROW]] to i8 +// NO-SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 [[CONV]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test10( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test10( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test10(struct union_of_fams *p, int index) { + p->bytes[index] = (unsigned char)__builtin_dynamic_object_size(p->bytes, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test10_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext nneg i32 [[NARROW]] to i64 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test10_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR5]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext nneg i32 [[NARROW]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test10_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test10_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test10_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p->bytes, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test11( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB16:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test11( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test11( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test11( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test11(struct annotated *p, int index) { + p->array[index] = __builtin_dynamic_object_size(&p->count, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test11_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 4 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test11_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 4 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test11_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 4 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test11_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 4 +// +size_t test11_bdos(struct annotated *p) { + return __builtin_dynamic_object_size(&p->count, 1); +} + +struct { + struct { + struct { + int num_entries; + }; + }; + int entries[] __attribute__((__counted_by__(num_entries))); +} test12_foo; + +struct hang { + int entries[6]; +} test12_bar; + +int test12_a, test12_b; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test12( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR13:[0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT9:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[INDEX]], 6 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB18:[0-9]+]], i64 [[TMP1]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP2]], ptr @test12_b, align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr @test12_foo, align 4 +// SANITIZE-WITH-ATTR-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[DOTCOUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[DOTNOT]], label [[HANDLER_OUT_OF_BOUNDS4:%.*]], label [[HANDLER_TYPE_MISMATCH6:%.*]], !prof [[PROF10:![0-9]+]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds4: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB19:[0-9]+]], i64 0) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.type_mismatch6: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_type_mismatch_v1_abort(ptr nonnull @[[GLOB20:[0-9]+]], i64 ptrtoint (ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0) to i64)) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test12( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR9:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR16:[0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0), align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP1]], ptr @test12_a, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: br label [[FOR_COND:%.*]] +// NO-SANITIZE-WITH-ATTR: for.cond: +// NO-SANITIZE-WITH-ATTR-NEXT: br label [[FOR_COND]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test12( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR8:[0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[INDEX]], 6 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[CONT:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8:![0-9]+]], !nosanitize [[META9:![0-9]+]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB2:[0-9]+]], i64 [[TMP1]]) #[[ATTR9:[0-9]+]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: cont: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[TMP1]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP2]], ptr @test12_b, align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr @test12_foo, align 4 +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[DOTCOUNTED_BY_LOAD]], 0 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[DOTNOT]], label [[HANDLER_OUT_OF_BOUNDS4:%.*]], label [[HANDLER_TYPE_MISMATCH6:%.*]], !prof [[PROF10:![0-9]+]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds4: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB4:[0-9]+]], i64 0) #[[ATTR9]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.type_mismatch6: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_type_mismatch_v1_abort(ptr nonnull @[[GLOB5:[0-9]+]], i64 ptrtoint (ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0) to i64)) #[[ATTR9]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test12( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR11:[0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0), align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP1]], ptr @test12_a, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: br label [[FOR_COND:%.*]] +// NO-SANITIZE-WITHOUT-ATTR: for.cond: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: br label [[FOR_COND]] +// +int test12(int index) { + struct hang baz = test12_bar; + + for (;; test12_a = (&test12_foo)->entries[0]) + test12_b = baz.entries[index]; + + return test12_b; +} + +struct test13_foo { + struct test13_bar *domain; +} test13_f; + +struct test13_bar { + struct test13_bar *parent; + int revmap_size; + struct test13_foo *revmap[] __attribute__((__counted_by__(revmap_size))); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test13( +// SANITIZE-WITH-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA11:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], [[INDEX]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB23:[0-9]+]], i64 [[INDEX]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont5: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITH-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 0 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test13( +// NO-SANITIZE-WITH-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR12:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA8:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITH-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 0 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test13( +// SANITIZE-WITHOUT-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA11:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], [[INDEX]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP2]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB8:[0-9]+]], i64 [[INDEX]]) #[[ATTR9]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: cont5: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITHOUT-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 0 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test13( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA8:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 0 +// +int test13(long index) { + test13_f.domain->revmap[index] = 0; + return 0; +} + +struct test14_foo { + int x, y; + int blah[] __attribute__((counted_by(x))); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test14( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB24:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: trap: +// SANITIZE-WITH-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR12]] +// SANITIZE-WITH-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test14( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTCOMPOUNDLITERAL:%.*]] = alloca [[STRUCT_TEST14_FOO:%.*]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 1, ptr [[DOTCOMPOUNDLITERAL]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 2, ptr [[Y]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test14( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB9:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR9]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: trap: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test14( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR3]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOMPOUNDLITERAL:%.*]] = alloca [[STRUCT_TEST14_FOO:%.*]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 1, ptr [[DOTCOMPOUNDLITERAL]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 2, ptr [[Y]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +int test14(int idx) { + return (struct test14_foo){ 1, 2 }.blah[idx]; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test15( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB25:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: trap: +// SANITIZE-WITH-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR12]] +// SANITIZE-WITH-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test15( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR7]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[FOO:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR16]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 1, ptr [[FOO]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[FOO]], i64 4 +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 2, ptr [[TMP0]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[FOO]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR16]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test15( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB10:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR9]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: trap: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test15( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[FOO:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 1, ptr [[FOO]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[FOO]], i64 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 2, ptr [[TMP0]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[FOO]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] +// +int test15(int idx) { + struct { + int x, y; + int blah[] __attribute__((counted_by(x))); + } foo = { 1, 2 }; + + return foo.blah[idx]; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test19( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test19( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test19( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test19( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test19(struct annotated *p) { + // Avoid pointer arithmetic. It could lead to security issues. + return __builtin_dynamic_object_size(&(p + 42)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test20( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test20( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test20( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test20( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test20(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(++p)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test21( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test21( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test21( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test21( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test21(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(p++)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test22( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test22( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test22( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test22( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test22(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(--p)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test23( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test23( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test23( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test23( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test23(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(p--)->array[2], 1); +} + +struct tests_foo { + int count; + int arr[] __counted_by(count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test24( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 10 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[DOTCOUNTED_BY_LOAD]], 10 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT4:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB26:[0-9]+]], i64 10) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont4: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO]], ptr [[VAR]], i64 21 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test24( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test24( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test24( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR8:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +int test24(int c, struct tests_foo *var) { + // Invalid: there can't be an array of flexible arrays. + return var[10].arr[10]; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test25( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[TMP0]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[DOTCOUNTED_BY_LOAD]], 10 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB27:[0-9]+]], i64 10) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont5: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test25( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR13:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test25( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test25( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR9:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] +// +int test25(int c, struct tests_foo **var) { + // Double dereferenced variable. + return (**var).arr[10]; +} + +// Outer struct +struct test26_foo { + int a; + struct tests_foo s; +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test26( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[FOO:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[S:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[S]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB28:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont5: +// SANITIZE-WITH-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO]], ptr [[FOO]], i64 1 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test26( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[FOO:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test26( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[FOO:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test26( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[FOO:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +int test26(int c, struct test26_foo *foo) { + // Invalid: A structure with a flexible array must be a pointer. + return foo->s.arr[c]; +} + +struct test27_baz; + +struct test27_bar { + unsigned char type; + unsigned char flags; + unsigned short use_cnt; + unsigned char hw_priv; +}; + +struct test27_foo { + struct test27_baz *a; + + unsigned char bit1 : 1; + unsigned char bit2 : 1; + unsigned char bit3 : 1; + + unsigned int n_tables; + unsigned long missed; + struct test27_bar *entries[] __counted_by(n_tables); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local ptr @test27( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB30:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM4:%.*]] = sext i32 [[J]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP2]], i64 [[IDXPROM4]] +// SANITIZE-WITH-ATTR-NEXT: ret ptr [[ARRAYIDX5]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local ptr @test27( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[J]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM1]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret ptr [[ARRAYIDX2]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local ptr @test27( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM3:%.*]] = sext i32 [[J]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM3]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret ptr [[ARRAYIDX4]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local ptr @test27( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR8]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[J]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM1]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret ptr [[ARRAYIDX2]] +// +struct test27_bar *test27(struct test27_foo *p, int i, int j) { + return &p->entries[i][j]; +} + +struct test28_foo { + struct test28_foo *s; + int count; + int arr[] __counted_by(count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test28( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP4]], label [[CONT17:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB31:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont17: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP5]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test28( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR13]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP3]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test28( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP3]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test28( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR9]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP3]] +// +int test28(struct test28_foo *p, int i) { + return p->s->s->s->arr[i]; +} + +struct annotated_struct_array { + struct annotated *ann_array[10]; + unsigned long flags; + int count; + int array[] __counted_by(count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test29( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[IDX1]], 10 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[IDX1]] to i64 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB33:[0-9]+]], i64 [[TMP1]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP2]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM15:%.*]] = sext i32 [[IDX2]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[IDXPROM15]], [[TMP3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP4]], label [[CONT20:%.*]], label [[HANDLER_OUT_OF_BOUNDS16:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds16: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB34:[0-9]+]], i64 [[IDXPROM15]]) #[[ATTR12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont20: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM15]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP5]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test29( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR14:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX1]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP0]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM4:%.*]] = sext i32 [[IDX2]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[TMP0]], i64 0, i32 2, i64 [[IDXPROM4]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test29( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[IDX1]], 10 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[IDX1]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[CONT21:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB12:[0-9]+]], i64 [[TMP1]]) #[[ATTR9]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: cont21: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[TMP1]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM18:%.*]] = sext i32 [[IDX2]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM18]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX19]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test29( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR10:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX1]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM5:%.*]] = sext i32 [[IDX2]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[IDXPROM5]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX6]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test29(struct annotated_struct_array *ann, int idx1, int idx2) { + ann->ann_array[idx1]->array[idx2] = __builtin_dynamic_object_size(ann->ann_array[idx1]->array, 1); +} diff --git a/clang/test/CodeGen/bounds-checking.c b/clang/test/CodeGen/bounds-checking.c index 636d4f289e24..8100e30d0650 100644 --- a/clang/test/CodeGen/bounds-checking.c +++ b/clang/test/CodeGen/bounds-checking.c @@ -69,7 +69,6 @@ int f7(union U *u, int i) { return u->c[i]; } - char B[10]; char B2[10]; // CHECK-LABEL: @f8 @@ -82,3 +81,12 @@ void f8(int i, int k) { // NOOPTARRAY: call void @llvm.ubsantrap(i8 4) B2[k] = '\0'; } + +// See commit 9a954c6 that caused a SEGFAULT in this code. +struct S { + __builtin_va_list ap; +} *s; +// CHECK-LABEL: @f9 +struct S *f9(int i) { + return &s[i]; +} diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test index 2f80c96e1d52..e476c15b35de 100644 --- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test +++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test @@ -62,6 +62,7 @@ // CHECK-NEXT: CoroOnlyDestroyWhenComplete (SubjectMatchRule_record) // CHECK-NEXT: CoroReturnType (SubjectMatchRule_record) // CHECK-NEXT: CoroWrapper (SubjectMatchRule_function) +// CHECK-NEXT: CountedBy (SubjectMatchRule_field) // CHECK-NEXT: DLLExport (SubjectMatchRule_function, SubjectMatchRule_variable, SubjectMatchRule_record, SubjectMatchRule_objc_interface) // CHECK-NEXT: DLLImport (SubjectMatchRule_function, SubjectMatchRule_variable, SubjectMatchRule_record, SubjectMatchRule_objc_interface) // CHECK-NEXT: Destructor (SubjectMatchRule_function) diff --git a/clang/test/Sema/attr-counted-by.c b/clang/test/Sema/attr-counted-by.c new file mode 100644 index 000000000000..f14da9c77fa8 --- /dev/null +++ b/clang/test/Sema/attr-counted-by.c @@ -0,0 +1,64 @@ +// RUN: %clang_cc1 -fsyntax-only -verify %s + +#define __counted_by(f) __attribute__((counted_by(f))) + +struct bar; + +struct not_found { + int count; + struct bar *fam[] __counted_by(bork); // expected-error {{use of undeclared identifier 'bork'}} +}; + +struct no_found_count_not_in_substruct { + unsigned long flags; + unsigned char count; // expected-note {{field 'count' declared here}} + struct A { + int dummy; + int array[] __counted_by(count); // expected-error {{'counted_by' field 'count' isn't within the same struct as the flexible array}} + } a; +}; + +struct not_found_suggest { + int bork; // expected-note {{'bork' declared here}} + struct bar *fam[] __counted_by(blork); // expected-error {{use of undeclared identifier 'blork'; did you mean 'bork'?}} +}; + +int global; // expected-note {{'global' declared here}} + +struct found_outside_of_struct { + int bork; + struct bar *fam[] __counted_by(global); // expected-error {{field 'global' in 'counted_by' not inside structure}} +}; + +struct self_referrential { + int bork; + struct bar *self[] __counted_by(self); // expected-error {{'counted_by' cannot refer to the flexible array 'self'}} +}; + +struct non_int_count { + double dbl_count; // expected-note {{field 'dbl_count' declared here}} + struct bar *fam[] __counted_by(dbl_count); // expected-error {{field 'dbl_count' in 'counted_by' must be a non-boolean integer type}} +}; + +struct array_of_ints_count { + int integers[2]; // expected-note {{field 'integers' declared here}} + struct bar *fam[] __counted_by(integers); // expected-error {{field 'integers' in 'counted_by' must be a non-boolean integer type}} +}; + +struct not_a_fam { + int count; + struct bar *non_fam __counted_by(count); // expected-error {{'counted_by' only applies to C99 flexible array members}} +}; + +struct not_a_c99_fam { + int count; + struct bar *non_c99_fam[0] __counted_by(count); // expected-error {{'counted_by' only applies to C99 flexible array members}} +}; + +struct annotated_with_anon_struct { + unsigned long flags; + struct { + unsigned char count; // expected-note {{'count' declared here}} + int array[] __counted_by(crount); // expected-error {{use of undeclared identifier 'crount'; did you mean 'count'?}} + }; +}; -- GitLab From 8ae8ae967406bc8cb1c21396b879681b06bdbfe6 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Wed, 10 Jan 2024 15:32:08 -0800 Subject: [PATCH 392/652] [llvm-exegesis] Update validation counters enum To be consistent with f65265ab779f5c6c571ff702aae5670722765ae0. --- llvm/tools/llvm-exegesis/lib/Target.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/Target.h b/llvm/tools/llvm-exegesis/lib/Target.h index 9d3bb2b44af1..a9e21c782b4d 100644 --- a/llvm/tools/llvm-exegesis/lib/Target.h +++ b/llvm/tools/llvm-exegesis/lib/Target.h @@ -40,10 +40,7 @@ extern cl::OptionCategory BenchmarkOptions; extern cl::OptionCategory AnalysisOptions; enum ValidationEvent { - L1DCacheLoadMiss, - InstructionRetired, - DataTLBLoadMiss, - DataTLBStoreMiss + InstructionRetired }; struct PfmCountersInfo { -- GitLab From 4a3fb9ce27dda17e97341f28005a28836c909cfc Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 10 Jan 2024 14:57:13 -0800 Subject: [PATCH 393/652] [Clang] Update 'counted_by' documentation Describe a limitation of the 'counted_by' attribute when used in unions. Also fix a errant typo. --- clang/include/clang/Basic/AttrDocs.td | 28 +++++++++++++++++++++++++++ clang/lib/CodeGen/CGBuiltin.cpp | 2 +- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 2e8d7752c975..c025acd3b106 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7825,5 +7825,33 @@ requirement: --p->count; p->array[index] = val; } + +Flexible array members, with the ``counted_by`` attribute, in unions are +supported with one limitation. If multiple flexible array members have the +``counted_by`` attribute, ``__builtin_dynamic_object_size`` won't be able to +calculate the object's size. For instance, in this example: + +.. code-block:: c + + struct union_of_fams { + int flags; + union { + unsigned long normal_field; + struct { + int count1; + int arr1[] __counted_by(count1); + }; + struct { + signed char count2; + int arr2[] __counted_by(count2); + }; + }; + }; + + size_t get_size(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p, 1); + } + +a call to ``get_size`` will return ``-1``. }]; } diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 998fcc3af581..b5aee3eaa53c 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -955,7 +955,7 @@ CodeGenFunction::emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, // }; // }; // - // We don't konw which 'count' to use in this scenario: + // We don't know which 'count' to use in this scenario: // // size_t get_size(struct union_of_fams *p) { // return __builtin_dynamic_object_size(p, 1); -- GitLab From 422b84a77167c43259e18cc3eff88b4b2530defc Mon Sep 17 00:00:00 2001 From: Billy Zhu Date: Wed, 10 Jan 2024 16:10:06 -0800 Subject: [PATCH 394/652] [MLIR][LLVM] DI Expression Rewrite & Legalization (#77541) Add a rewriter for DIExpressions & use it to run legalization patterns before exporting to llvm (because LLVM dialect allows DI Expressions that may not be valid in LLVM IR). The rewriter driver works similarly to the existing mlir rewriter drivers, except it operates on lists of DIExpressionElemAttr (i.e. DIExpressionAttr). Each rewrite pattern transforms a range of DIExpressionElemAttr into a new list of DIExpressionElemAttr. In addition, this PR sets up a place to add legalization patterns that are broadly applicable internally to the LLVM dialect, and they will always be applied prior to export. This PR adds one pattern for merging fragment operators. --------- Co-authored-by: Tobias Gysi --- .../Transforms/DIExpressionLegalization.h | 51 +++++++++++++ .../LLVMIR/Transforms/DIExpressionRewriter.h | 67 +++++++++++++++++ .../Dialect/LLVMIR/Transforms/CMakeLists.txt | 2 + .../Transforms/DIExpressionLegalization.cpp | 61 +++++++++++++++ .../Transforms/DIExpressionRewriter.cpp | 75 +++++++++++++++++++ .../LLVMIR/Transforms/LegalizeForExport.cpp | 2 + mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 2 + .../LLVMIR/di-expression-legalization.mlir | 42 +++++++++++ 8 files changed, 302 insertions(+) create mode 100644 mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionLegalization.h create mode 100644 mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionRewriter.h create mode 100644 mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionLegalization.cpp create mode 100644 mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionRewriter.cpp create mode 100644 mlir/test/Dialect/LLVMIR/di-expression-legalization.mlir diff --git a/mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionLegalization.h b/mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionLegalization.h new file mode 100644 index 000000000000..2faf19b788b3 --- /dev/null +++ b/mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionLegalization.h @@ -0,0 +1,51 @@ +//===- DIExpressionLegalization.h - DIExpression Legalization Patterns ----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Declarations for known legalization patterns for DIExpressions that should +// be performed before translation into llvm. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_DIALECT_LLVMIR_TRANSFORMS_DIEXPRESSIONLEGALIZATION_H +#define MLIR_DIALECT_LLVMIR_TRANSFORMS_DIEXPRESSIONLEGALIZATION_H + +#include "mlir/Dialect/LLVMIR/Transforms/DIExpressionRewriter.h" + +namespace mlir { +namespace LLVM { + +//===----------------------------------------------------------------------===// +// Rewrite Patterns +//===----------------------------------------------------------------------===// + +/// Adjacent DW_OP_LLVM_fragment should be merged into one. +/// +/// E.g. +/// #llvm.di_expression<[ +/// DW_OP_LLVM_fragment(32, 32), DW_OP_LLVM_fragment(32, 64) +/// ]> +/// => +/// #llvm.di_expression<[DW_OP_LLVM_fragment(64, 32)]> +class MergeFragments : public DIExpressionRewriter::ExprRewritePattern { +public: + OpIterT match(OpIterRange operators) const override; + SmallVector replace(OpIterRange operators) const override; +}; + +//===----------------------------------------------------------------------===// +// Runner +//===----------------------------------------------------------------------===// + +/// Register all known legalization patterns declared here and apply them to +/// all ops in `op`. +void legalizeDIExpressionsRecursively(Operation *op); + +} // namespace LLVM +} // namespace mlir + +#endif // MLIR_DIALECT_LLVMIR_TRANSFORMS_DIEXPRESSIONLEGALIZATION_H diff --git a/mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionRewriter.h b/mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionRewriter.h new file mode 100644 index 000000000000..2d9841518a63 --- /dev/null +++ b/mlir/include/mlir/Dialect/LLVMIR/Transforms/DIExpressionRewriter.h @@ -0,0 +1,67 @@ +//===- DIExpressionRewriter.h - Rewriter for DIExpression operators -------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// A driver for running rewrite patterns on DIExpression operators. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_DIALECT_LLVMIR_TRANSFORMS_DIEXPRESSIONREWRITER_H +#define MLIR_DIALECT_LLVMIR_TRANSFORMS_DIEXPRESSIONREWRITER_H + +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include + +namespace mlir { +namespace LLVM { + +/// Rewriter for DIExpressionAttr. +/// +/// Users of this rewriter register their own rewrite patterns. Each pattern +/// matches on a contiguous range of LLVM DIExpressionElemAttrs, and can be +/// used to rewrite it into a new range of DIExpressionElemAttrs of any length. +class DIExpressionRewriter { +public: + using OperatorT = LLVM::DIExpressionElemAttr; + + class ExprRewritePattern { + public: + using OperatorT = DIExpressionRewriter::OperatorT; + using OpIterT = std::deque::const_iterator; + using OpIterRange = llvm::iterator_range; + + virtual ~ExprRewritePattern() = default; + /// Checks whether a particular prefix of operators matches this pattern. + /// The provided argument is guaranteed non-empty. + /// Return the iterator after the last matched element. + virtual OpIterT match(OpIterRange) const = 0; + /// Replace the operators with a new list of operators. + /// The provided argument is guaranteed to be the same length as returned + /// by the `match` function. + virtual SmallVector replace(OpIterRange) const = 0; + }; + + /// Register a rewrite pattern with the rewriter. + /// Rewrite patterns are attempted in the order of registration. + void addPattern(std::unique_ptr pattern); + + /// Simplify a DIExpression according to all the patterns registered. + /// An optional `maxNumRewrites` can be passed to limit the number of rewrites + /// that gets applied. + LLVM::DIExpressionAttr + simplify(LLVM::DIExpressionAttr expr, + std::optional maxNumRewrites = {}) const; + +private: + /// The registered patterns. + SmallVector> patterns; +}; + +} // namespace LLVM +} // namespace mlir + +#endif // MLIR_DIALECT_LLVMIR_TRANSFORMS_DIEXPRESSIONREWRITER_H diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt b/mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt index 47a2a251bf3e..c80494a44011 100644 --- a/mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt @@ -1,5 +1,7 @@ add_mlir_dialect_library(MLIRLLVMIRTransforms AddComdats.cpp + DIExpressionLegalization.cpp + DIExpressionRewriter.cpp DIScopeForLLVMFuncOp.cpp LegalizeForExport.cpp OptimizeForNVVM.cpp diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionLegalization.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionLegalization.cpp new file mode 100644 index 000000000000..7d3170bb9682 --- /dev/null +++ b/mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionLegalization.cpp @@ -0,0 +1,61 @@ +//===- DIExpressionLegalization.cpp - DIExpression Legalization Patterns --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/LLVMIR/Transforms/DIExpressionLegalization.h" + +#include "llvm/BinaryFormat/Dwarf.h" + +using namespace mlir; +using namespace LLVM; + +//===----------------------------------------------------------------------===// +// MergeFragments +//===----------------------------------------------------------------------===// + +MergeFragments::OpIterT MergeFragments::match(OpIterRange operators) const { + OpIterT it = operators.begin(); + if (it == operators.end() || + it->getOpcode() != llvm::dwarf::DW_OP_LLVM_fragment) + return operators.begin(); + + ++it; + if (it == operators.end() || + it->getOpcode() != llvm::dwarf::DW_OP_LLVM_fragment) + return operators.begin(); + + return ++it; +} + +SmallVector +MergeFragments::replace(OpIterRange operators) const { + OpIterT it = operators.begin(); + OperatorT first = *(it++); + OperatorT second = *it; + // Add offsets & select the size of the earlier operator (the one closer to + // the IR value). + uint64_t offset = first.getArguments()[0] + second.getArguments()[0]; + uint64_t size = first.getArguments()[1]; + OperatorT newOp = OperatorT::get( + first.getContext(), llvm::dwarf::DW_OP_LLVM_fragment, {offset, size}); + return SmallVector{newOp}; +} + +//===----------------------------------------------------------------------===// +// Runner +//===----------------------------------------------------------------------===// + +void mlir::LLVM::legalizeDIExpressionsRecursively(Operation *op) { + LLVM::DIExpressionRewriter rewriter; + rewriter.addPattern(std::make_unique()); + + AttrTypeReplacer replacer; + replacer.addReplacement([&rewriter](LLVM::DIExpressionAttr expr) { + return rewriter.simplify(expr); + }); + replacer.recursivelyReplaceElementsIn(op); +} diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionRewriter.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionRewriter.cpp new file mode 100644 index 000000000000..6fdb2f8c1964 --- /dev/null +++ b/mlir/lib/Dialect/LLVMIR/Transforms/DIExpressionRewriter.cpp @@ -0,0 +1,75 @@ +//===- DIExpressionRewriter.cpp - Rewriter for DIExpression operators -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/LLVMIR/Transforms/DIExpressionRewriter.h" +#include "mlir/Transforms/GreedyPatternRewriteDriver.h" +#include "llvm/Support/Debug.h" + +using namespace mlir; +using namespace LLVM; + +#define DEBUG_TYPE "llvm-di-expression-simplifier" + +//===----------------------------------------------------------------------===// +// DIExpressionRewriter +//===----------------------------------------------------------------------===// + +void DIExpressionRewriter::addPattern( + std::unique_ptr pattern) { + patterns.emplace_back(std::move(pattern)); +} + +DIExpressionAttr +DIExpressionRewriter::simplify(DIExpressionAttr expr, + std::optional maxNumRewrites) const { + ArrayRef operators = expr.getOperations(); + + // `inputs` contains the unprocessed postfix of operators. + // `result` contains the already finalized prefix of operators. + // Invariant: concat(result, inputs) is equivalent to `operators` after some + // application of the rewrite patterns. + // Using a deque for inputs so that we have efficient front insertion and + // removal. Random access is not necessary for patterns. + std::deque inputs(operators.begin(), operators.end()); + SmallVector result; + + uint64_t numRewrites = 0; + while (!inputs.empty() && + (!maxNumRewrites || numRewrites < *maxNumRewrites)) { + bool foundMatch = false; + for (const std::unique_ptr &pattern : patterns) { + ExprRewritePattern::OpIterT matchEnd = pattern->match(inputs); + if (matchEnd == inputs.begin()) + continue; + + foundMatch = true; + SmallVector replacement = + pattern->replace(llvm::make_range(inputs.cbegin(), matchEnd)); + inputs.erase(inputs.begin(), matchEnd); + inputs.insert(inputs.begin(), replacement.begin(), replacement.end()); + ++numRewrites; + break; + } + + if (!foundMatch) { + // If no match, pass along the current operator. + result.push_back(inputs.front()); + inputs.pop_front(); + } + } + + if (maxNumRewrites && numRewrites >= *maxNumRewrites) { + LLVM_DEBUG(llvm::dbgs() + << "LLVMDIExpressionSimplifier exceeded max num rewrites (" + << maxNumRewrites << ")\n"); + // Skip rewriting the rest. + result.append(inputs.begin(), inputs.end()); + } + + return LLVM::DIExpressionAttr::get(expr.getContext(), result); +} diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp index 61c1378d9612..1ac994fa5fb7 100644 --- a/mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp +++ b/mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp @@ -9,6 +9,7 @@ #include "mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/Dialect/LLVMIR/Transforms/DIExpressionLegalization.h" #include "mlir/IR/Block.h" #include "mlir/IR/Builders.h" #include "mlir/IR/BuiltinOps.h" @@ -79,6 +80,7 @@ struct LegalizeForExportPass : public LLVM::impl::LLVMLegalizeForExportBase { void runOnOperation() override { LLVM::ensureDistinctSuccessors(getOperation()); + LLVM::legalizeDIExpressionsRecursively(getOperation()); } }; } // namespace diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp index ce46a194ea7d..fbbfb5b83eb6 100644 --- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp @@ -19,6 +19,7 @@ #include "mlir/Dialect/DLTI/DLTI.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" #include "mlir/Dialect/LLVMIR/LLVMInterfaces.h" +#include "mlir/Dialect/LLVMIR/Transforms/DIExpressionLegalization.h" #include "mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h" #include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "mlir/Dialect/OpenMP/OpenMPInterfaces.h" @@ -1568,6 +1569,7 @@ mlir::translateModuleToLLVMIR(Operation *module, llvm::LLVMContext &llvmContext, return nullptr; LLVM::ensureDistinctSuccessors(module); + LLVM::legalizeDIExpressionsRecursively(module); ModuleTranslation translator(module, std::move(llvmModule)); llvm::IRBuilder<> llvmBuilder(llvmContext); diff --git a/mlir/test/Dialect/LLVMIR/di-expression-legalization.mlir b/mlir/test/Dialect/LLVMIR/di-expression-legalization.mlir new file mode 100644 index 000000000000..60fbc8135be6 --- /dev/null +++ b/mlir/test/Dialect/LLVMIR/di-expression-legalization.mlir @@ -0,0 +1,42 @@ +// RUN: mlir-opt -llvm-legalize-for-export --split-input-file %s | FileCheck %s -check-prefix=CHECK-OPT +// RUN: mlir-translate -mlir-to-llvmir --split-input-file %s | FileCheck %s -check-prefix=CHECK-TRANSLATE + +#di_file = #llvm.di_file<"foo.c" in "/mlir/"> +#di_compile_unit = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #di_file, producer = "MLIR", isOptimized = true, emissionKind = Full> +#di_subprogram = #llvm.di_subprogram +#i32_type = #llvm.di_basic_type +#i8_type = #llvm.di_basic_type + +// struct0: {i8, i32} +#struct0_first = #llvm.di_derived_type +#struct0_second = #llvm.di_derived_type +#struct0 = #llvm.di_composite_type + +// struct1: {i8, struct0} +#struct1_first = #llvm.di_derived_type +#struct1_second = #llvm.di_derived_type +#struct1 = #llvm.di_composite_type + +// struct2: {i32, struct1} +#struct2_first = #llvm.di_derived_type +#struct2_second = #llvm.di_derived_type +#struct2 = #llvm.di_composite_type + +#var0 = #llvm.di_local_variable +#var1 = #llvm.di_local_variable +#var2 = #llvm.di_local_variable + +#loc = loc("test.mlir":0:0) + +llvm.func @merge_fragments(%arg0: !llvm.ptr, %arg1: !llvm.ptr, %arg2: !llvm.ptr) { + // CHECK-OPT: #llvm.di_expression<[DW_OP_deref, DW_OP_LLVM_fragment(32, 32)]> + // CHECK-TRANSLATE: !DIExpression(DW_OP_deref, DW_OP_LLVM_fragment, 32, 32)) + llvm.intr.dbg.value #var0 #llvm.di_expression<[DW_OP_deref, DW_OP_LLVM_fragment(32, 32)]> = %arg0 : !llvm.ptr loc(fused<#di_subprogram>[#loc]) + // CHECK-OPT: #llvm.di_expression<[DW_OP_deref, DW_OP_LLVM_fragment(64, 32)]> + // CHECK-TRANSLATE: !DIExpression(DW_OP_deref, DW_OP_LLVM_fragment, 64, 32)) + llvm.intr.dbg.value #var1 #llvm.di_expression<[DW_OP_deref, DW_OP_LLVM_fragment(32, 32), DW_OP_LLVM_fragment(32, 64)]> = %arg1 : !llvm.ptr loc(fused<#di_subprogram>[#loc]) + // CHECK-OPT: #llvm.di_expression<[DW_OP_deref, DW_OP_LLVM_fragment(96, 32)]> + // CHECK-TRANSLATE: !DIExpression(DW_OP_deref, DW_OP_LLVM_fragment, 96, 32)) + llvm.intr.dbg.value #var2 #llvm.di_expression<[DW_OP_deref, DW_OP_LLVM_fragment(32, 32), DW_OP_LLVM_fragment(32, 64), DW_OP_LLVM_fragment(32, 96)]> = %arg2 : !llvm.ptr loc(fused<#di_subprogram>[#loc]) + llvm.return +} -- GitLab From 66981f9c616812fdc452c3c03a901b85e2e2fd90 Mon Sep 17 00:00:00 2001 From: Mingming Liu Date: Wed, 10 Jan 2024 16:17:15 -0800 Subject: [PATCH 395/652] [docs][IRPGO]Document two binary formats for instrumentation-based profiles, with a focus on IRPGO. (#76105) --- compiler-rt/include/profile/InstrProfData.inc | 2 + llvm/docs/InstrProfileFormat.rst | 480 ++++++++++++++++++ llvm/docs/UserGuides.rst | 4 + llvm/include/llvm/ProfileData/InstrProf.h | 3 +- .../llvm/ProfileData/InstrProfData.inc | 2 + 5 files changed, 490 insertions(+), 1 deletion(-) create mode 100644 llvm/docs/InstrProfileFormat.rst diff --git a/compiler-rt/include/profile/InstrProfData.inc b/compiler-rt/include/profile/InstrProfData.inc index f5de23ff4b94..25df899b3f36 100644 --- a/compiler-rt/include/profile/InstrProfData.inc +++ b/compiler-rt/include/profile/InstrProfData.inc @@ -123,6 +123,8 @@ INSTR_PROF_VALUE_NODE(PtrToNodeT, llvm::PointerType::getUnqual(Ctx), Next, \ /* INSTR_PROF_RAW_HEADER start */ /* Definition of member fields of the raw profile header data structure. */ +/* Please update llvm/docs/InstrProfileFormat.rst as appropriate when updating + raw profile format. */ #ifndef INSTR_PROF_RAW_HEADER #define INSTR_PROF_RAW_HEADER(Type, Name, Initializer) #else diff --git a/llvm/docs/InstrProfileFormat.rst b/llvm/docs/InstrProfileFormat.rst new file mode 100644 index 000000000000..2069b87a245a --- /dev/null +++ b/llvm/docs/InstrProfileFormat.rst @@ -0,0 +1,480 @@ +=================================== +Instrumentation Profile Format +=================================== + +.. contents:: + :local: + + +Overview +========= + +Clang supports two types of profiling via instrumentation [1]_: frontend-based +and IR-based, and both could support a variety of use cases [2]_ . +This document describes two binary serialization formats (raw and indexed) to +store instrumented profiles with a specific emphasis on IRPGO use case, in the +sense that when specific header fields and payload sections have different ways +of interpretation across use cases, the documentation is based on IRPGO. + +.. note:: + Frontend-generated profiles are used together with coverage mapping for + `source-based code coverage`_. The `coverage mapping format`_ is different from + profile format. + +.. _`source-based code coverage`: https://clang.llvm.org/docs/SourceBasedCodeCoverage.html +.. _`coverage mapping format`: https://llvm.org/docs/CoverageMappingFormat.html + +Raw Profile Format +=================== + +The raw profile is generated by running the instrumented binary. The raw profile +data from an executable or a shared library [3]_ consists of a header and +multiple sections, with each section as a memory dump. The raw profile data needs +to be reasonably compact and fast to generate. + +There are no backward or forward version compatiblity guarantees for the raw profile +format. That is, compilers and tools `require`_ a specific raw profile version +to parse the profiles. + +.. _`require`: https://github.com/llvm/llvm-project/blob/bffdde8b8e5d9a76a47949cd0f574f3ce656e181/llvm/lib/ProfileData/InstrProfReader.cpp#L551-L558 + +To feed profiles back into compilers for an optimized build (e.g., via +``-fprofile-use`` for IR instrumentation), a raw profile must to be converted into +indexed format. + +General Storage Layout +----------------------- + +The storage layout of raw profile data format is illustrated below. Basically, +when the raw profile is read into an memory buffer, the actual byte offset of a +section is inferred from the section's order in the layout and size information +of all the sections ahead of it. + +:: + + +----+-----------------------+ + | | Magic | + | +-----------------------+ + | | Version | + | +-----------------------+ + H | Size Info for | + E | Section 1 | + A +-----------------------+ + D | Size Info for | + E | Section 2 | + R +-----------------------+ + | | ... | + | +-----------------------+ + | | Size Info for | + | | Section N | + +----+-----------------------+ + P | Section 1 | + A +-----------------------+ + Y | Section 2 | + L +-----------------------+ + O | ... | + A +-----------------------+ + D | Section N | + +----+-----------------------+ + + +.. note:: + Sections might be padded to meet specific alignment requirements. For + simplicity, header fields and data sections solely for padding purpose are + omitted in the data layout graph above and the rest of this document. + +Header +------- + +``Magic`` + Magic number encodes profile format (raw, indexed or text). For the raw format, + the magic number also encodes the endianness (big or little) and C pointer + size (4 or 8 bytes) of the platform on which the profile is generated. + + A factory method reads the magic number to construct reader properly and returns + error upon unrecognized format. Specifically, the factory method and raw profile + reader implementation make sure that a raw profile file could be read back on + a platform with the opposite endianness and/or the other C pointer size. + +``Version`` + The lower 32 bits specify the actual version and the most significant 32 bits + specify the variant types of the profile. IR-based instrumentation PGO and + context-sensitive IR-based instrumentation PGO are two variant types. + +``BinaryIdsSize`` + The byte size of `binary id`_ section. + +``NumData`` + The number of profile metadata. The byte size of `profile metadata`_ section + could be computed with this field. + +``NumCounter`` + The number of entries in the profile counter section. The byte size of `counter`_ + section could be computed with this field. + +``NumBitmapBytes`` + The number of bytes in the profile `bitmap`_ section. + +``NamesSize`` + The number of bytes in the name section. + +.. _`CountersDelta`: + +``CountersDelta`` + This field records the in-memory address difference between the `profile metadata`_ + and counter section in the instrumented binary, i.e., ``start(__llvm_prf_cnts) - start(__llvm_prf_data)``. + + It's used jointly with the `CounterPtr`_ field to compute the counter offset + relative to ``start(__llvm_prf_cnts)``. Check out calculation-of-counter-offset_ + for a visualized explanation. + + .. note:: + The ``__llvm_prf_data`` object file section might not be loaded into memory + when instrumented binary runs or might not get generated in the instrumented + binary in the first place. In those cases, ``CountersDelta`` is not used and + other mechanisms are used to match counters with instrumented code. See + `lightweight instrumentation`_ and `binary profile correlation`_ for examples. + +``BitmapDelta`` + This field records the in-memory address difference between the `profile metadata`_ + and bitmap section in the instrumented binary, i.e., ``start(__llvm_prf_bits) - start(__llvm_prf_data)``. + + It's used jointly with the `BitmapPtr`_ to find the bitmap of a profile data + record, in a similar way to how counters are referenced as explained by + calculation-of-counter-offset_ . + + Similar to `CountersDelta`_ field, this field may not be used in non-PGO variants + of profiles. + +``NamesDelta`` + Records the in-memory address of name section. Not used except for raw profile + reader error checking. + +``ValueKindLast`` + Records the number of value kinds. Macro `VALUE_PROF_KIND`_ defines the value + kinds with a description of the kind. + +.. _`VALUE_PROF_KIND`: https://github.com/llvm/llvm-project/blob/7e405eb722e40c79b7726201d0f76b5dab34ba0f/compiler-rt/include/profile/InstrProfData.inc#L184-L186 + +Payload Sections +------------------ + +Binary Ids +^^^^^^^^^^^ +Stores the binary ids of the instrumented binaries to associate binaries with +profiles for source code coverage. See `binary id`_ RFC for the design. + +.. _`profile metadata`: + +Profile Metadata +^^^^^^^^^^^^^^^^^^ + +This section stores the metadata to map counters and value profiles back to +instrumented code regions (e.g., LLVM IR for IRPGO). + +The in-memory representation of the metadata is `__llvm_profile_data`_. +Some fields are used to reference data from other sections in the profile. +The fields are documented as follows: + +.. _`__llvm_profile_data`: https://github.com/llvm/llvm-project/blob/7c3b67d2038cfb48a80299089f6a1308eee1df7f/compiler-rt/include/profile/InstrProfData.inc#L65-L95 + +``NameRef`` + The MD5 of the function's PGO name. PGO name has the format + ``[]`` where ```` and + ```` are provided for local-linkage functions to tell possibly + identical functions. + +.. _FuncHash: + +``FuncHash`` + A checksum of the function's IR, taking control flow graph and instrumented + value sites into accounts. See `computeCFGHash`_ for details. + +.. _`computeCFGHash`: https://github.com/llvm/llvm-project/blob/7c3b67d2038cfb48a80299089f6a1308eee1df7f/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp#L616-L685 + +.. _`CounterPtr`: + +``CounterPtr`` + The in-memory address difference between profile data and the start of corresponding + counters. Counter position is stored this way (as a link-time constant) to reduce + instrumented binary size compared with snapshotting the address of symbols directly. + See `commit a1532ed`_ for further information. + +.. _`commit a1532ed`: https://github.com/llvm/llvm-project/commit/a1532ed27582038e2d9588108ba0fe8237f01844 + + .. note:: + ``CounterPtr`` might represent a different value for non-IRPGO use case. For + example, for `binary profile correlation`_, it represents the absolute address of counter. + When in doubt, check source code. + +.. _`BitmapPtr`: + +``BitmapPtr`` + The in-memory address difference between profile data and the start address of + corresponding bitmap. + + .. note:: + Similar to `CounterPtr`_, this field may represent a different value for non-IRPGO use case. + +``FunctionPointer`` + Records the function address when instrumented binary runs. This is used to + map the profiled callee address of indirect calls to the ``NameRef`` during + conversion from raw to indexed profiles. + +``Values`` + Represents value profiles in a two dimensional array. The number of elements + in the first dimension is the number of instrumented value sites across all + kinds. Each element in the first dimension is the head of a linked list, and + the each element in the second dimension is linked list element, carrying + ```` as payload. This is used by compiler runtime when + writing out value profiles. + + .. note:: + Value profiling is supported by frontend and IR PGO instrumentation, + but it's not supported in all cases (e.g., `lightweight instrumentation`_). + +``NumCounters`` + The number of counters for the instrumented function. + +``NumValueSites`` + This is an array of counters, and each counter represents the number of + instrumented sites for a kind of value in the function. + +``NumBitmapBytes`` + The number of bitmap bytes for the function. + +.. _`counter`: + +Profile Counters +^^^^^^^^^^^^^^^^^ + +For PGO [4]_, the counters within an instrumented function of a specific `FuncHash`_ +are stored contiguously and in an order that is consistent with instrumentation points selection. + +.. _calculation-of-counter-offset: + +As mentioned above, the recorded counter offset is relative to the profile metadata. +So how are function counters located in the raw profile data? + +Basically, the profile reader iterates profile metadata (from the `profile metadata`_ +section) and makes use of the recorded relative distances, as illustrated below. + +:: + + + --> start(__llvm_prf_data) --> +---------------------+ ------------+ + | | Data 1 | | + | +---------------------+ =====|| | + | | Data 2 | || | + | +---------------------+ || | + | | ... | || | + Counter| +---------------------+ || | + Delta | | Data N | || | + | +---------------------+ || | CounterPtr1 + | || | + | CounterPtr2 || | + | || | + | || | + + --> start(__llvm_prf_cnts) --> +---------------------+ || | + | ... | || | + +---------------------+ -----||----+ + | Counter for | || + | Data 1 | || + +---------------------+ || + | ... | || + +---------------------+ =====|| + | Counter for | + | Data 2 | + +---------------------+ + | ... | + +---------------------+ + | Counter for | + | Data N | + +---------------------+ + + +In the graph, + +* The profile header records ``CounterDelta`` with the value as ``start(__llvm_prf_cnts) - start(__llvm_prf_data)``. + We will call it ``CounterDeltaInitVal`` below for convenience. +* For each profile data record ``ProfileDataN``, ``CounterPtr`` is recorded as + ``start(CounterN) - start(ProfileDataN)``, where ``ProfileDataN`` is the N-th + entry in ``__llvm_prf_data``, and ``CounterN`` represents the corresponding + profile counters. + +Each time the reader advances to the next data record, it `updates`_ ``CounterDelta`` +to minus the size of one ``ProfileData``. + +.. _`updates`: https://github.com/llvm/llvm-project/blob/17ff25a58ee4f29816d932fdb75f0d305718069f/llvm/include/llvm/ProfileData/InstrProfReader.h#L439-L444 + +For the counter corresponding to the first data record, the byte offset +relative to the start of the counter section is calculated as ``CounterPtr1 - CounterDeltaInitVal``. +When profile reader advances to the second data record, note ``CounterDelta`` +is updated to ``CounterDeltaInitVal - sizeof(ProfileData)``. +Thus the byte offset relative to the start of the counter section is calculated +as ``CounterPtr2 - (CounterDeltaInitVal - sizeof(ProfileData))``. + +.. _`bitmap`: + +Bitmap +^^^^^^^ +This section is used for source-based `Modified Condition/Decision Coverage`_ code coverage. Check out `Bitmap RFC`_ +for the design. + +.. _`Modified Condition/Decision Coverage`: https://en.wikipedia.org/wiki/Modified_condition/decision_coverage +.. _`Bitmap RFC`: https://discourse.llvm.org/t/rfc-source-based-mc-dc-code-coverage/59244 + +Names +^^^^^^ + +This section contains possibly compressed concatenated string of functions' PGO +names. If compressed, zlib library is used. + +Function names serve as keys in the PGO data hash table when raw profiles are +converted into indexed profiles. They are also crucial for ``llvm-profdata`` to +show the profiles in a human-readable way. + +Value Profile Data +^^^^^^^^^^^^^^^^^^^^ + +This section contains the profile data for value profiling. + +The value profiles corresponding to a profile metadata are serialized contiguously +as one record, and value profile records are stored in the same order as the +respective profile data, such that a raw profile reader `advances`_ the pointer to +profile data and the pointer to value profile records simutaneously [5]_ to find +value profiles for a per function, per `FuncHash`_ profile data. + +.. _`advances`: https://github.com/llvm/llvm-project/blob/7e15fa9161eda7497a5d6abf0d951a1d12d86550/llvm/include/llvm/ProfileData/InstrProfReader.h#L456-L457 + +Indexed Profile Format +=========================== + +Indexed profiles are generated from ``llvm-profdata``. In the indexed profiles, +function data are organized as on-disk hash table such that compilers can +look up profile data for functions in an IR module. + +Compilers and tools must retain backward compatibility with indexed profiles. +That is, a tool or a compiler built at newer versions of code must understand +profiles generated by older tools or compilers. + +General Storage Layout +----------------------- + +:: + + +-----------------------+---+ + | Magic | | + +-----------------------+ | + | Version | | + +-----------------------+ | + | HashType | H + +-----------------------+ E + +-------| HashOffset | A + | +-----------------------+ D + +-----------| MemProfOffset | E + | | +-----------------------+ R + | | +--| BinaryIdOffset | | + | | | +-----------------------+ | + +---------------| TemporalProf- | | + | | | | | TracesOffset | | + | | | | +-----------------------+---+ + | | | | | Profile Summary | | + | | | | +-----------------------+ P + | | +------>| Function data | A + | | | +-----------------------+ Y + | +---------->| MemProf profile data | L + | | +-----------------------+ O + | +->| Binary Ids | A + | +-----------------------+ D + +-------------->| Temporal profiles | | + +-----------------------+---+ + +Header +-------- + +``Magic`` + The purpose of the magic number is to be able to tell if the profile is an + indexed profile. + +``Version`` + Similar to raw profile version, the lower 32 bits specify the version of the + indexed profile and the most significant 32 bits are reserved to specify the + variant types of the profile. + +``HashType`` + The hashing scheme for on-disk hash table keys. Only MD5 hashing is used as of + writing. + +``HashOffset`` + An on-disk hash table stores the per-function profile records. This field records + the offset of this hash table's metadata (i.e., the number of buckets and + entries), which follows right after the payload of the entire hash table. + +``MemProfOffset`` + Records the byte offset of MemProf profiling data. + +``BinaryIdOffset`` + Records the byte offset of binary id sections. + +``TemporalProfTracesOffset`` + Records the byte offset of temporal profiles. + +Payload Sections +------------------ + +(CS) Profile Summary +^^^^^^^^^^^^^^^^^^^^^ +This section is right after profile header. It stores the serialized profile +summary. For context-sensitive IR-based instrumentation PGO, this section stores +an additional profile summary corresponding to the context-sensitive profiles. + +Function data +^^^^^^^^^^^^^^^^^^ +This section stores functions and their profiling data as an on-disk hash table. +Profile data for functions with the same name are grouped together and share one +hash table entry (the functions may come from different shared libraries for +instance). The profile data for them are organized as a sequence of key-value +pair where the key is `FuncHash`_, and the value is profiled information (represented +by `InstrProfRecord`_) for the function. + +.. _`InstrProfRecord`: https://github.com/llvm/llvm-project/blob/7e405eb722e40c79b7726201d0f76b5dab34ba0f/llvm/include/llvm/ProfileData/InstrProf.h#L693 + +MemProf Profile data +^^^^^^^^^^^^^^^^^^^^^^ +This section stores function's memory profiling data. See +`MemProf binary serialization format RFC`_ for the design. + +.. _`MemProf binary serialization format RFC`: https://lists.llvm.org/pipermail/llvm-dev/2021-September/153007.html + +Binary Ids +^^^^^^^^^^^^^^^^^^^^^^ +The section is used to carry on `binary id`_ information from raw profiles. + +Temporal Profile Traces +^^^^^^^^^^^^^^^^^^^^^^^^ +The section is used to carry on temporal profile information from raw profiles. +See `temporal profiling`_ for the design. + +Profile Data Usage +======================================= + +``llvm-profdata`` is the command line tool to display and process instrumentation- +based profile data. For supported usages, check out `llvm-profdata documentation `_. + +.. [1] For usage, see https://clang.llvm.org/docs/UsersManual.html#profiling-with-instrumentation +.. [2] For example, IR-based instrumentation supports `lightweight instrumentation`_ + and `temporal profiling`_. Frontend instrumentation could support `single-byte counters`_. +.. [3] A raw profile file could contain the concatenation of multiple raw + profiles, for example, from an executable and its shared libraries. Raw + profile reader could parse all raw profiles from the file correctly. +.. [4] The counter section is used by a few variant types (like temporal + profiling) and might have different semantics there. +.. [5] The step size of data pointer is the ``sizeof(ProfileData)``, and the step + size of value profile pointer is calcuated based on the number of collected + values. + +.. _`lightweight instrumentation`: https://groups.google.com/g/llvm-dev/c/r03Z6JoN7d4 +.. _`temporal profiling`: https://discourse.llvm.org/t/rfc-temporal-profiling-extension-for-irpgo/68068 +.. _`single-byte counters`: https://discourse.llvm.org/t/rfc-single-byte-counters-for-source-based-code-coverage/75685 +.. _`binary profile correlation`: https://discourse.llvm.org/t/rfc-add-binary-profile-correlation-to-not-load-profile-metadata-sections-into-memory-at-runtime/74565 +.. _`binary id`: https://lists.llvm.org/pipermail/llvm-dev/2021-June/151154.html diff --git a/llvm/docs/UserGuides.rst b/llvm/docs/UserGuides.rst index 006df613bc5e..2f450ef46025 100644 --- a/llvm/docs/UserGuides.rst +++ b/llvm/docs/UserGuides.rst @@ -43,6 +43,7 @@ intermediate LLVM representation. HowToCrossCompileBuiltinsOnArm HowToCrossCompileLLVM HowToUpdateDebugInfo + InstrProfileFormat InstrRefDebugInfo LinkTimeOptimization LoopTerminology @@ -177,6 +178,9 @@ Optimizations referencing, to determine variable locations for debug info in the final stages of compilation. +:doc:`InstrProfileFormat` + This document explains two binary formats of instrumentation-based profiles. + Code Generation --------------- diff --git a/llvm/include/llvm/ProfileData/InstrProf.h b/llvm/include/llvm/ProfileData/InstrProf.h index 36be2e7d869e..87e7bbbd727e 100644 --- a/llvm/include/llvm/ProfileData/InstrProf.h +++ b/llvm/include/llvm/ProfileData/InstrProf.h @@ -1035,7 +1035,8 @@ const HashT HashType = HashT::MD5; inline uint64_t ComputeHash(StringRef K) { return ComputeHash(HashType, K); } // This structure defines the file header of the LLVM profile -// data file in indexed-format. +// data file in indexed-format. Please update llvm/docs/InstrProfileFormat.rst +// as appropriate when updating the indexed profile format. struct Header { uint64_t Magic; uint64_t Version; diff --git a/llvm/include/llvm/ProfileData/InstrProfData.inc b/llvm/include/llvm/ProfileData/InstrProfData.inc index f5de23ff4b94..25df899b3f36 100644 --- a/llvm/include/llvm/ProfileData/InstrProfData.inc +++ b/llvm/include/llvm/ProfileData/InstrProfData.inc @@ -123,6 +123,8 @@ INSTR_PROF_VALUE_NODE(PtrToNodeT, llvm::PointerType::getUnqual(Ctx), Next, \ /* INSTR_PROF_RAW_HEADER start */ /* Definition of member fields of the raw profile header data structure. */ +/* Please update llvm/docs/InstrProfileFormat.rst as appropriate when updating + raw profile format. */ #ifndef INSTR_PROF_RAW_HEADER #define INSTR_PROF_RAW_HEADER(Type, Name, Initializer) #else -- GitLab From 03be448cce8b6a5f1aa36fc1b316508b08b3aa9f Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 10 Jan 2024 16:47:34 -0800 Subject: [PATCH 396/652] [RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU (#77631) Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen pipeline. This test prematurely stops at the first one, which doesn't cleanup the virtual register map and cause an assertion failure. Ideally we can solve this by teaching `-stop-after` how to stop at the last instance of a Pass, but we're just marking XFAIL for these two targets for now. --- llvm/test/CodeGen/Generic/live-debug-label.ll | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/llvm/test/CodeGen/Generic/live-debug-label.ll b/llvm/test/CodeGen/Generic/live-debug-label.ll index 5022e1f187d1..3121b8700ed1 100644 --- a/llvm/test/CodeGen/Generic/live-debug-label.ll +++ b/llvm/test/CodeGen/Generic/live-debug-label.ll @@ -2,6 +2,13 @@ ; ; NVPTX produces a different order of the BBs ; XFAIL: target=nvptx{{.*}} +; Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen +; pipeline. This test prematurely stops at the first one, which doesn't cleanup +; the virtual register map and cause an assertion failure. Ideally we can solve +; this by teaching `-stop-after` how to stop at the last instance of a Pass, +; but we're just marking XFAIL for these two targets for now. +; XFAIL: target=riscv{{.*}} +; XFAIL: target=amdgcn-{{.*}} ; Generated with "clang++ -g -O1 -S -emit-llvm" ; -- GitLab From 753dc0a01ccc3cbe87d5ee0fe0ec7f8db340966f Mon Sep 17 00:00:00 2001 From: Yinying Li <107574043+yinying-lisa-li@users.noreply.github.com> Date: Wed, 10 Jan 2024 20:04:43 -0500 Subject: [PATCH 397/652] [mlir][verifyMemref] Fix bug and support more types for verifyMemref (#77682) 1. Fix a bug in verifyMemref to pass in `data` instead of `baseptr`, which didn't verify data correctly. 2. Add `==` for f16 and bf16. 3. Add a comprehensive test of verifyMemref for all supported types. --- .../mlir/ExecutionEngine/Float16bits.h | 3 + .../mlir/ExecutionEngine/RunnerUtils.h | 16 +- mlir/lib/ExecutionEngine/Float16bits.cpp | 4 + mlir/lib/ExecutionEngine/RunnerUtils.cpp | 30 ++++ .../Dialect/Memref/verify-memref.mlir | 167 ++++++++++++++++++ 5 files changed, 217 insertions(+), 3 deletions(-) create mode 100644 mlir/test/Integration/Dialect/Memref/verify-memref.mlir diff --git a/mlir/include/mlir/ExecutionEngine/Float16bits.h b/mlir/include/mlir/ExecutionEngine/Float16bits.h index 5eb1f2ce0763..ad409841b2a9 100644 --- a/mlir/include/mlir/ExecutionEngine/Float16bits.h +++ b/mlir/include/mlir/ExecutionEngine/Float16bits.h @@ -48,6 +48,9 @@ MLIR_FLOAT16_EXPORT std::ostream &operator<<(std::ostream &os, const f16 &f); // Outputs a bfloat value. MLIR_FLOAT16_EXPORT std::ostream &operator<<(std::ostream &os, const bf16 &d); +MLIR_FLOAT16_EXPORT bool operator==(const f16 &f1, const f16 &f2); +MLIR_FLOAT16_EXPORT bool operator==(const bf16 &bf1, const bf16 &bf2); + extern "C" MLIR_FLOAT16_EXPORT void printF16(uint16_t bits); extern "C" MLIR_FLOAT16_EXPORT void printBF16(uint16_t bits); diff --git a/mlir/include/mlir/ExecutionEngine/RunnerUtils.h b/mlir/include/mlir/ExecutionEngine/RunnerUtils.h index ebf95f90f374..9a748370c36e 100644 --- a/mlir/include/mlir/ExecutionEngine/RunnerUtils.h +++ b/mlir/include/mlir/ExecutionEngine/RunnerUtils.h @@ -331,9 +331,9 @@ int64_t verifyMemRef(const DynamicMemRefType &actual, } // Return the number of errors. int64_t printCounter = 0; - return MemRefDataVerifier::verify( - std::cerr, actual.basePtr, expected.basePtr, actual.rank, actual.offset, - actual.sizes, actual.strides, printCounter); + return MemRefDataVerifier::verify(std::cerr, actual.data, expected.data, + actual.rank, actual.offset, actual.sizes, + actual.strides, printCounter); } /// Verify the equivalence of two unranked memrefs and return the number of @@ -429,8 +429,18 @@ _mlir_ciface_printMemref1dC64(StridedMemRefType *m); extern "C" MLIR_RUNNERUTILS_EXPORT void _mlir_ciface_printMemrefVector4x4xf32( StridedMemRefType, 2> *m); +extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefI8( + UnrankedMemRefType *actual, UnrankedMemRefType *expected); +extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefI16( + UnrankedMemRefType *actual, UnrankedMemRefType *expected); extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefI32( UnrankedMemRefType *actual, UnrankedMemRefType *expected); +extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefI64( + UnrankedMemRefType *actual, UnrankedMemRefType *expected); +extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefBF16( + UnrankedMemRefType *actual, UnrankedMemRefType *expected); +extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefF16( + UnrankedMemRefType *actual, UnrankedMemRefType *expected); extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefF32( UnrankedMemRefType *actual, UnrankedMemRefType *expected); extern "C" MLIR_RUNNERUTILS_EXPORT int64_t _mlir_ciface_verifyMemRefF64( diff --git a/mlir/lib/ExecutionEngine/Float16bits.cpp b/mlir/lib/ExecutionEngine/Float16bits.cpp index 38a05fe86bbd..841610e3c161 100644 --- a/mlir/lib/ExecutionEngine/Float16bits.cpp +++ b/mlir/lib/ExecutionEngine/Float16bits.cpp @@ -150,6 +150,10 @@ std::ostream &operator<<(std::ostream &os, const bf16 &d) { return os; } +bool operator==(const f16 &f1, const f16 &f2) { return f1.bits == f2.bits; } + +bool operator==(const bf16 &f1, const bf16 &f2) { return f1.bits == f2.bits; } + // Mark these symbols as weak so they don't conflict when compiler-rt also // defines them. #define ATTR_WEAK diff --git a/mlir/lib/ExecutionEngine/RunnerUtils.cpp b/mlir/lib/ExecutionEngine/RunnerUtils.cpp index 378aa7ce35ef..eaa83bfc693f 100644 --- a/mlir/lib/ExecutionEngine/RunnerUtils.cpp +++ b/mlir/lib/ExecutionEngine/RunnerUtils.cpp @@ -219,12 +219,42 @@ _mlir_ciface_printMemref1dC64(StridedMemRefType *M) { impl::printMemRef(*M); } +extern "C" int64_t +_mlir_ciface_verifyMemRefI8(UnrankedMemRefType *actual, + UnrankedMemRefType *expected) { + return impl::verifyMemRef(*actual, *expected); +} + +extern "C" int64_t +_mlir_ciface_verifyMemRefI16(UnrankedMemRefType *actual, + UnrankedMemRefType *expected) { + return impl::verifyMemRef(*actual, *expected); +} + extern "C" int64_t _mlir_ciface_verifyMemRefI32(UnrankedMemRefType *actual, UnrankedMemRefType *expected) { return impl::verifyMemRef(*actual, *expected); } +extern "C" int64_t +_mlir_ciface_verifyMemRefI64(UnrankedMemRefType *actual, + UnrankedMemRefType *expected) { + return impl::verifyMemRef(*actual, *expected); +} + +extern "C" int64_t +_mlir_ciface_verifyMemRefF16(UnrankedMemRefType *actual, + UnrankedMemRefType *expected) { + return impl::verifyMemRef(*actual, *expected); +} + +extern "C" int64_t +_mlir_ciface_verifyMemRefBF16(UnrankedMemRefType *actual, + UnrankedMemRefType *expected) { + return impl::verifyMemRef(*actual, *expected); +} + extern "C" int64_t _mlir_ciface_verifyMemRefF32(UnrankedMemRefType *actual, UnrankedMemRefType *expected) { diff --git a/mlir/test/Integration/Dialect/Memref/verify-memref.mlir b/mlir/test/Integration/Dialect/Memref/verify-memref.mlir new file mode 100644 index 000000000000..b7e2a46688f4 --- /dev/null +++ b/mlir/test/Integration/Dialect/Memref/verify-memref.mlir @@ -0,0 +1,167 @@ +// RUN: mlir-opt %s \ +// RUN: -func-bufferize -arith-bufferize --canonicalize \ +// RUN: -convert-vector-to-scf -convert-scf-to-cf -convert-vector-to-llvm -finalize-memref-to-llvm\ +// RUN: -convert-func-to-llvm -reconcile-unrealized-casts |\ +// RUN: mlir-cpu-runner \ +// RUN: -e entry -entry-point-result=void \ +// RUN: -shared-libs=%mlir_c_runner_utils,%mlir_runner_utils |\ +// RUN: FileCheck %s + +module { + func.func private @verifyMemRefI8(%a : tensor<*xi8>, %b : tensor<*xi8>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefI16(%a : tensor<*xi16>, %b : tensor<*xi16>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefI32(%a : tensor<*xi32>, %b : tensor<*xi32>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefI64(%a : tensor<*xi64>, %b : tensor<*xi64>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefBF16(%a : tensor<*xbf16>, %b : tensor<*xbf16>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefF16(%a : tensor<*xf16>, %b : tensor<*xf16>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefF32(%a : tensor<*xf32>, %b : tensor<*xf32>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefF64(%a : tensor<*xf64>, %b : tensor<*xf64>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefC32(%a : tensor<*xcomplex>, %b : tensor<*xcomplex>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefC64(%a : tensor<*xcomplex>, %b : tensor<*xcomplex>) -> i64 attributes { llvm.emit_c_interface } + func.func private @verifyMemRefInd(%a : tensor<*xindex>, %b : tensor<*xindex>) -> i64 attributes { llvm.emit_c_interface } + + func.func @entry() { + %i8 = arith.constant dense<90> : tensor<3x3xi8> + %i16 = arith.constant dense<1> : tensor<3x3xi16> + %i32 = arith.constant dense<2> : tensor<3x3xi32> + %i64 = arith.constant dense<3> : tensor<3x3xi64> + %f16 = arith.constant dense<1.5> : tensor<3x3xf16> + %bf16 = arith.constant dense<2.5> : tensor<3x3xbf16> + %f32 = arith.constant dense<3.5> : tensor<3x3xf32> + %f64 = arith.constant dense<4.5> : tensor<3x3xf64> + %c32 = arith.constant dense<(1.000000e+01,5.000000e+00)> : tensor<3x3xcomplex> + %c64 = arith.constant dense<(2.000000e+01,5.000000e+00)> : tensor<3x3xcomplex> + %ind = arith.constant dense<4> : tensor<3x3xindex> + + %1 = tensor.cast %i8 : tensor<3x3xi8> to tensor<*xi8> + %2 = tensor.cast %i16 : tensor<3x3xi16> to tensor<*xi16> + %3 = tensor.cast %i32 : tensor<3x3xi32> to tensor<*xi32> + %4 = tensor.cast %i64 : tensor<3x3xi64> to tensor<*xi64> + %5 = tensor.cast %f16 : tensor<3x3xf16> to tensor<*xf16> + %6 = tensor.cast %bf16 : tensor<3x3xbf16> to tensor<*xbf16> + %7 = tensor.cast %f32 : tensor<3x3xf32> to tensor<*xf32> + %8 = tensor.cast %f64 : tensor<3x3xf64> to tensor<*xf64> + %9 = tensor.cast %c32 : tensor<3x3xcomplex> to tensor<*xcomplex> + %10 = tensor.cast %c64 : tensor<3x3xcomplex> to tensor<*xcomplex> + %11 = tensor.cast %ind : tensor<3x3xindex> to tensor<*xindex> + + // + // Ensure that verifyMemRef could detect equal memrefs. + // + // CHECK: 0 + %res0 = call @verifyMemRefI8(%1, %1) : (tensor<*xi8>, tensor<*xi8>) -> (i64) + vector.print %res0 : i64 + + // CHECK-NEXT: 0 + %res1 = call @verifyMemRefI16(%2, %2) : (tensor<*xi16>, tensor<*xi16>) -> (i64) + vector.print %res1 : i64 + + // CHECK-NEXT: 0 + %res2 = call @verifyMemRefI32(%3, %3) : (tensor<*xi32>, tensor<*xi32>) -> (i64) + vector.print %res2 : i64 + + // CHECK-NEXT: 0 + %res3 = call @verifyMemRefI64(%4, %4) : (tensor<*xi64>, tensor<*xi64>) -> (i64) + vector.print %res3 : i64 + + // CHECK-NEXT: 0 + %res4 = call @verifyMemRefF16(%5, %5) : (tensor<*xf16>, tensor<*xf16>) -> (i64) + vector.print %res4 : i64 + + // CHECK-NEXT: 0 + %res5 = call @verifyMemRefBF16(%6, %6) : (tensor<*xbf16>, tensor<*xbf16>) -> (i64) + vector.print %res5 : i64 + + // CHECK-NEXT: 0 + %res6 = call @verifyMemRefF32(%7, %7) : (tensor<*xf32>, tensor<*xf32>) -> (i64) + vector.print %res6 : i64 + + // CHECK-NEXT: 0 + %res7 = call @verifyMemRefF64(%8, %8) : (tensor<*xf64>, tensor<*xf64>) -> (i64) + vector.print %res7 : i64 + + // CHECK-NEXT: 0 + %res8 = call @verifyMemRefC32(%9, %9) : (tensor<*xcomplex>, tensor<*xcomplex>) -> (i64) + vector.print %res8 : i64 + + // CHECK-NEXT: 0 + %res9 = call @verifyMemRefC64(%10, %10) : (tensor<*xcomplex>, tensor<*xcomplex>) -> (i64) + vector.print %res9 : i64 + + // CHECK-NEXT: 0 + %res10 = call @verifyMemRefInd(%11, %11) : (tensor<*xindex>, tensor<*xindex>) -> (i64) + vector.print %res10 : i64 + + // + // Ensure that verifyMemRef could detect the correct number of errors + // for unequal memrefs. + // + %m1 = arith.constant dense<100> : tensor<3x3xi8> + %f1 = tensor.cast %m1 : tensor<3x3xi8> to tensor<*xi8> + %fail_res1 = call @verifyMemRefI8(%1, %f1) : (tensor<*xi8>, tensor<*xi8>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res1 : i64 + + %m2 = arith.constant dense<100> : tensor<3x3xi16> + %f2 = tensor.cast %m2 : tensor<3x3xi16> to tensor<*xi16> + %fail_res2 = call @verifyMemRefI16(%2, %f2) : (tensor<*xi16>, tensor<*xi16>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res2 : i64 + + %m3 = arith.constant dense<100> : tensor<3x3xi32> + %f3 = tensor.cast %m3 : tensor<3x3xi32> to tensor<*xi32> + %fail_res3 = call @verifyMemRefI32(%3, %f3) : (tensor<*xi32>, tensor<*xi32>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res3 : i64 + + %m4 = arith.constant dense<100> : tensor<3x3xi64> + %f4 = tensor.cast %m4 : tensor<3x3xi64> to tensor<*xi64> + %fail_res4 = call @verifyMemRefI64(%4, %f4) : (tensor<*xi64>, tensor<*xi64>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res4 : i64 + + %m5 = arith.constant dense<100.0> : tensor<3x3xf16> + %f5 = tensor.cast %m5 : tensor<3x3xf16> to tensor<*xf16> + %fail_res5 = call @verifyMemRefF16(%5, %f5) : (tensor<*xf16>, tensor<*xf16>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res5 : i64 + + %m6 = arith.constant dense<100.0> : tensor<3x3xbf16> + %f6 = tensor.cast %m6 : tensor<3x3xbf16> to tensor<*xbf16> + %fail_res6 = call @verifyMemRefBF16(%6, %f6) : (tensor<*xbf16>, tensor<*xbf16>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res6 : i64 + + %m7 = arith.constant dense<100.0> : tensor<3x3xf32> + %f7 = tensor.cast %m7 : tensor<3x3xf32> to tensor<*xf32> + %fail_res7 = call @verifyMemRefF32(%7, %f7) : (tensor<*xf32>, tensor<*xf32>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res7 : i64 + + %m8 = arith.constant dense<100.0> : tensor<3x3xf64> + %f8 = tensor.cast %m8 : tensor<3x3xf64> to tensor<*xf64> + %fail_res8 = call @verifyMemRefF64(%8, %f8) : (tensor<*xf64>, tensor<*xf64>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res8 : i64 + + %m9 = arith.constant dense<(5.000000e+01,1.000000e+00)> : tensor<3x3xcomplex> + %f9 = tensor.cast %m9 : tensor<3x3xcomplex> to tensor<*xcomplex> + %fail_res9 = call @verifyMemRefC32(%9, %f9) : (tensor<*xcomplex>, tensor<*xcomplex>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res9 : i64 + + %m10 = arith.constant dense<(5.000000e+01,1.000000e+00)> : tensor<3x3xcomplex> + %f10 = tensor.cast %m10 : tensor<3x3xcomplex> to tensor<*xcomplex> + %fail_res10 = call @verifyMemRefC64(%10, %f10) : (tensor<*xcomplex>, tensor<*xcomplex>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res10 : i64 + + %m11 = arith.constant dense<100> : tensor<3x3xindex> + %f11 = tensor.cast %m11 : tensor<3x3xindex> to tensor<*xindex> + %fail_res11 = call @verifyMemRefInd(%11, %f11) : (tensor<*xindex>, tensor<*xindex>) -> (i64) + // CHECK-NEXT: 9 + vector.print %fail_res11 : i64 + + return + } +} -- GitLab From 66d022f326779c8abe80b272751fab1a10992222 Mon Sep 17 00:00:00 2001 From: Ben Shi <2283975856@qq.com> Date: Thu, 11 Jan 2024 09:10:34 +0800 Subject: [PATCH 398/652] [clang][analyzer] Fix incorrect range of 'ftell' in the StdLibraryFunctionsChecker (#77576) According to https://pubs.opengroup.org/onlinepubs/9699919799/, the return value of `ftell` is not restricted to `> 0`, and may return `0` in real world. --- .../lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp index 32a2deab871c..3b36565681a7 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp @@ -2274,7 +2274,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( addToFunctionSummaryMap( "ftell", Signature(ArgTypes{FilePtrTy}, RetType{LongTy}), Summary(NoEvalCall) - .Case({ReturnValueCondition(WithinRange, Range(1, LongMax))}, + .Case({ReturnValueCondition(WithinRange, Range(0, LongMax))}, ErrnoUnchanged, GenericSuccessMsg) .Case(ReturnsMinusOne, ErrnoNEZeroIrrelevant, GenericFailureMsg) .ArgConstraint(NotNull(ArgNo(0)))); -- GitLab From 31fd6d116daba3b7f8e17a2c9d671e265f49be3c Mon Sep 17 00:00:00 2001 From: Boian Petkantchin Date: Wed, 10 Jan 2024 17:28:17 -0800 Subject: [PATCH 399/652] [mlir][mesh] fix ProcessMultiIndexOp building (#77676) Insert default empty mesh axes array instead of null attribute without MLIR context, since the attribute is default-valued not just optional. --- mlir/lib/Dialect/Mesh/IR/MeshOps.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp b/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp index 9b110c462915..957b380efd51 100644 --- a/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp +++ b/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp @@ -353,7 +353,7 @@ void ProcessMultiIndexOp::build(OpBuilder &odsBuilder, OperationState &odsState, ClusterOp mesh) { build(odsBuilder, odsState, SmallVector(mesh.getRank(), odsBuilder.getIndexType()), - mesh.getSymName(), MeshAxesAttr()); + mesh.getSymName(), ArrayRef()); } void ProcessMultiIndexOp::build(OpBuilder &odsBuilder, OperationState &odsState, -- GitLab From d85a13b867b17fa93965bc7e439a58c954045217 Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Wed, 10 Jan 2024 17:58:59 -0800 Subject: [PATCH 400/652] Revert "[CommandLine][NFCI] Do not add 'All' to 'RegisteredSubCommands' (#77041)" This reverts commit fb7fe49960ae053c92985f3376d85a15bbd10d1a. The commit introduced a bug where an option with the `All' subcommand would not be added to a category initialized after that option. --- llvm/lib/Support/CommandLine.cpp | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Support/CommandLine.cpp b/llvm/lib/Support/CommandLine.cpp index 9a57936be2db..7360d733d96e 100644 --- a/llvm/lib/Support/CommandLine.cpp +++ b/llvm/lib/Support/CommandLine.cpp @@ -164,7 +164,10 @@ public: // This collects the different subcommands that have been registered. SmallPtrSet RegisteredSubCommands; - CommandLineParser() { registerSubCommand(&SubCommand::getTopLevel()); } + CommandLineParser() { + registerSubCommand(&SubCommand::getTopLevel()); + registerSubCommand(&SubCommand::getAll()); + } void ResetAllOptionOccurrences(); @@ -345,15 +348,15 @@ public: // For all options that have been registered for all subcommands, add the // option to this subcommand now. - assert(sub != &SubCommand::getAll() && - "SubCommand::getAll() should not be registered"); - for (auto &E : SubCommand::getAll().OptionsMap) { - Option *O = E.second; - if ((O->isPositional() || O->isSink() || O->isConsumeAfter()) || - O->hasArgStr()) - addOption(O, sub); - else - addLiteralOption(*O, sub, E.first()); + if (sub != &SubCommand::getAll()) { + for (auto &E : SubCommand::getAll().OptionsMap) { + Option *O = E.second; + if ((O->isPositional() || O->isSink() || O->isConsumeAfter()) || + O->hasArgStr()) + addOption(O, sub); + else + addLiteralOption(*O, sub, E.first()); + } } } @@ -381,6 +384,7 @@ public: SubCommand::getTopLevel().reset(); SubCommand::getAll().reset(); registerSubCommand(&SubCommand::getTopLevel()); + registerSubCommand(&SubCommand::getAll()); DefaultOptions.clear(); } @@ -528,8 +532,8 @@ SubCommand *CommandLineParser::LookupSubCommand(StringRef Name, // Find a subcommand with the edit distance == 1. SubCommand *NearestMatch = nullptr; for (auto *S : RegisteredSubCommands) { - assert(S != &SubCommand::getAll() && - "SubCommand::getAll() is not expected in RegisteredSubCommands"); + if (S == &SubCommand::getAll()) + continue; if (S->getName().empty()) continue; -- GitLab From 2dce77201c0c6b541a53aa7a09ec06e7561e8f74 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Wed, 10 Jan 2024 21:05:09 -0500 Subject: [PATCH 401/652] Revert "[Clang] Implement the 'counted_by' attribute (#76348)" This reverts commit fefdef808c230c79dca2eb504490ad0f17a765a5. Breaks check-clang, see https://github.com/llvm/llvm-project/pull/76348#issuecomment-1886029515 Also revert follow-on "[Clang] Update 'counted_by' documentation" This reverts commit 4a3fb9ce27dda17e97341f28005a28836c909cfc. --- clang/docs/ReleaseNotes.rst | 5 - clang/include/clang/AST/DeclBase.h | 10 - clang/include/clang/Basic/Attr.td | 18 - clang/include/clang/Basic/AttrDocs.td | 106 - .../clang/Basic/DiagnosticSemaKinds.td | 13 - clang/include/clang/Sema/Sema.h | 3 - clang/include/clang/Sema/TypoCorrection.h | 12 +- clang/lib/AST/ASTImporter.cpp | 13 - clang/lib/AST/DeclBase.cpp | 74 +- clang/lib/AST/Expr.cpp | 83 +- clang/lib/CodeGen/CGBuiltin.cpp | 240 --- clang/lib/CodeGen/CGExpr.cpp | 340 +-- clang/lib/CodeGen/CodeGenFunction.h | 22 - clang/lib/Sema/SemaDecl.cpp | 6 - clang/lib/Sema/SemaDeclAttr.cpp | 133 -- clang/lib/Sema/SemaExpr.cpp | 16 +- clang/test/CodeGen/attr-counted-by.c | 1828 ----------------- clang/test/CodeGen/bounds-checking.c | 10 +- ...a-attribute-supported-attributes-list.test | 1 - clang/test/Sema/attr-counted-by.c | 64 - 20 files changed, 92 insertions(+), 2905 deletions(-) delete mode 100644 clang/test/CodeGen/attr-counted-by.c delete mode 100644 clang/test/Sema/attr-counted-by.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index a60c5a7cd058..ade0036ba2fd 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -208,11 +208,6 @@ C Language Changes - Enums will now be represented in TBAA metadata using their actual underlying integer type. Previously they were treated as chars, which meant they could alias with all other types. -- Clang now supports the C-only attribute ``counted_by``. When applied to a - struct's flexible array member, it points to the struct field that holds the - number of elements in the flexible array member. This information can improve - the results of the array bound sanitizer and the - ``__builtin_dynamic_object_size`` builtin. C23 Feature Support ^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h index 5b1038582bc6..10dcbdb262d8 100644 --- a/clang/include/clang/AST/DeclBase.h +++ b/clang/include/clang/AST/DeclBase.h @@ -19,7 +19,6 @@ #include "clang/AST/SelectorLocationsKind.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LLVM.h" -#include "clang/Basic/LangOptions.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/Specifiers.h" #include "llvm/ADT/ArrayRef.h" @@ -489,15 +488,6 @@ public: // Return true if this is a FileContext Decl. bool isFileContextDecl() const; - /// Whether it resembles a flexible array member. This is a static member - /// because we want to be able to call it with a nullptr. That allows us to - /// perform non-Decl specific checks based on the object's type and strict - /// flex array level. - static bool isFlexibleArrayMemberLike( - ASTContext &Context, const Decl *D, QualType Ty, - LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, - bool IgnoreTemplateOrMacroSubstitution); - ASTContext &getASTContext() const LLVM_READONLY; /// Helper to get the language options from the ASTContext. diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index a03b0e44e15f..d5eabaad4889 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -4372,21 +4372,3 @@ def CodeAlign: StmtAttr { static constexpr int MaximumAlignment = 4096; }]; } - -def CountedBy : InheritableAttr { - let Spellings = [Clang<"counted_by">]; - let Subjects = SubjectList<[Field]>; - let Args = [IdentifierArgument<"CountedByField">]; - let Documentation = [CountedByDocs]; - let LangOpts = [COnly]; - // FIXME: This is ugly. Let using a DeclArgument would be nice, but a Decl - // isn't yet available due to the fact that we're still parsing the - // structure. Maybe that code could be changed sometime in the future. - code AdditionalMembers = [{ - private: - SourceRange CountedByFieldLoc; - public: - SourceRange getCountedByFieldLoc() const { return CountedByFieldLoc; } - void setCountedByFieldLoc(SourceRange Loc) { CountedByFieldLoc = Loc; } - }]; -} diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index c025acd3b106..5416a0cbdd07 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7749,109 +7749,3 @@ but do not pass them to the underlying coroutine or pass them by value. .. _`CRT`: https://clang.llvm.org/docs/AttributeReference.html#coro-return-type }]; } - -def CountedByDocs : Documentation { - let Category = DocCatField; - let Content = [{ -Clang supports the ``counted_by`` attribute on the flexible array member of a -structure in C. The argument for the attribute is the name of a field member -holding the count of elements in the flexible array. This information can be -used to improve the results of the array bound sanitizer and the -``__builtin_dynamic_object_size`` builtin. The ``count`` field member must be -within the same non-anonymous, enclosing struct as the flexible array member. - -This example specifies that the flexible array member ``array`` has the number -of elements allocated for it in ``count``: - -.. code-block:: c - - struct bar; - - struct foo { - size_t count; - char other; - struct bar *array[] __attribute__((counted_by(count))); - }; - -This establishes a relationship between ``array`` and ``count``. Specifically, -``array`` must have at least ``count`` number of elements available. It's the -user's responsibility to ensure that this relationship is maintained through -changes to the structure. - -In the following example, the allocated array erroneously has fewer elements -than what's specified by ``p->count``. This would result in an out-of-bounds -access not being detected. - -.. code-block:: c - - #define SIZE_INCR 42 - - struct foo *p; - - void foo_alloc(size_t count) { - p = malloc(MAX(sizeof(struct foo), - offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); - p->count = count + SIZE_INCR; - } - -The next example updates ``p->count``, but breaks the relationship requirement -that ``p->array`` must have at least ``p->count`` number of elements available: - -.. code-block:: c - - #define SIZE_INCR 42 - - struct foo *p; - - void foo_alloc(size_t count) { - p = malloc(MAX(sizeof(struct foo), - offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); - p->count = count; - } - - void use_foo(int index, int val) { - p->count += SIZE_INCR + 1; /* 'count' is now larger than the number of elements of 'array'. */ - p->array[index] = val; /* The sanitizer can't properly check this access. */ - } - -In this example, an update to ``p->count`` maintains the relationship -requirement: - -.. code-block:: c - - void use_foo(int index, int val) { - if (p->count == 0) - return; - --p->count; - p->array[index] = val; - } - -Flexible array members, with the ``counted_by`` attribute, in unions are -supported with one limitation. If multiple flexible array members have the -``counted_by`` attribute, ``__builtin_dynamic_object_size`` won't be able to -calculate the object's size. For instance, in this example: - -.. code-block:: c - - struct union_of_fams { - int flags; - union { - unsigned long normal_field; - struct { - int count1; - int arr1[] __counted_by(count1); - }; - struct { - signed char count2; - int arr2[] __counted_by(count2); - }; - }; - }; - - size_t get_size(struct union_of_fams *p) { - return __builtin_dynamic_object_size(p, 1); - } - -a call to ``get_size`` will return ``-1``. - }]; -} diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 1a79892e4003..3884dca59e2f 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -6441,19 +6441,6 @@ def warn_superclass_variable_sized_type_not_at_end : Warning< "field %0 can overwrite instance variable %1 with variable sized type %2" " in superclass %3">, InGroup; -def err_flexible_array_count_not_in_same_struct : Error< - "'counted_by' field %0 isn't within the same struct as the flexible array">; -def err_counted_by_attr_not_on_flexible_array_member : Error< - "'counted_by' only applies to C99 flexible array members">; -def err_counted_by_attr_refers_to_flexible_array : Error< - "'counted_by' cannot refer to the flexible array %0">; -def err_counted_by_must_be_in_structure : Error< - "field %0 in 'counted_by' not inside structure">; -def err_flexible_array_counted_by_attr_field_not_integer : Error< - "field %0 in 'counted_by' must be a non-boolean integer type">; -def note_flexible_array_counted_by_attr_field : Note< - "field %0 declared here">; - let CategoryName = "ARC Semantic Issue" in { // ARC-mode diagnostics. diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index cf2d4fbe6d3b..edaee4c4b66d 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -4799,8 +4799,6 @@ public: bool CheckAlwaysInlineAttr(const Stmt *OrigSt, const Stmt *CurSt, const AttributeCommonInfo &A); - bool CheckCountedByAttr(Scope *Scope, const FieldDecl *FD); - /// Adjust the calling convention of a method to be the ABI default if it /// wasn't specified explicitly. This handles method types formed from /// function type typedefs and typename template arguments. @@ -5644,7 +5642,6 @@ public: CorrectionCandidateCallback &CCC, TemplateArgumentListInfo *ExplicitTemplateArgs = nullptr, ArrayRef Args = std::nullopt, - DeclContext *LookupCtx = nullptr, TypoExpr **Out = nullptr); DeclResult LookupIvarInObjCMethod(LookupResult &Lookup, Scope *S, diff --git a/clang/include/clang/Sema/TypoCorrection.h b/clang/include/clang/Sema/TypoCorrection.h index 09de164297e7..e0f8d152dbe5 100644 --- a/clang/include/clang/Sema/TypoCorrection.h +++ b/clang/include/clang/Sema/TypoCorrection.h @@ -282,7 +282,7 @@ class CorrectionCandidateCallback { public: static const unsigned InvalidDistance = TypoCorrection::InvalidDistance; - explicit CorrectionCandidateCallback(const IdentifierInfo *Typo = nullptr, + explicit CorrectionCandidateCallback(IdentifierInfo *Typo = nullptr, NestedNameSpecifier *TypoNNS = nullptr) : Typo(Typo), TypoNNS(TypoNNS) {} @@ -319,7 +319,7 @@ public: /// this method. virtual std::unique_ptr clone() = 0; - void setTypoName(const IdentifierInfo *II) { Typo = II; } + void setTypoName(IdentifierInfo *II) { Typo = II; } void setTypoNNS(NestedNameSpecifier *NNS) { TypoNNS = NNS; } // Flags for context-dependent keywords. WantFunctionLikeCasts is only @@ -345,13 +345,13 @@ protected: candidate.getCorrectionSpecifier() == TypoNNS; } - const IdentifierInfo *Typo; + IdentifierInfo *Typo; NestedNameSpecifier *TypoNNS; }; class DefaultFilterCCC final : public CorrectionCandidateCallback { public: - explicit DefaultFilterCCC(const IdentifierInfo *Typo = nullptr, + explicit DefaultFilterCCC(IdentifierInfo *Typo = nullptr, NestedNameSpecifier *TypoNNS = nullptr) : CorrectionCandidateCallback(Typo, TypoNNS) {} @@ -365,10 +365,6 @@ public: template class DeclFilterCCC final : public CorrectionCandidateCallback { public: - explicit DeclFilterCCC(const IdentifierInfo *Typo = nullptr, - NestedNameSpecifier *TypoNNS = nullptr) - : CorrectionCandidateCallback(Typo, TypoNNS) {} - bool ValidateCandidate(const TypoCorrection &candidate) override { return candidate.getCorrectionDeclAs(); } diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 0540159f07e8..5e5570bb42a1 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -9030,10 +9030,6 @@ class AttrImporter { public: AttrImporter(ASTImporter &I) : Importer(I), NImporter(I) {} - // Useful for accessing the imported attribute. - template T *castAttrAs() { return cast(ToAttr); } - template const T *castAttrAs() const { return cast(ToAttr); } - // Create an "importer" for an attribute parameter. // Result of the 'value()' of that object is to be passed to the function // 'importAttr', in the order that is expected by the attribute class. @@ -9247,15 +9243,6 @@ Expected ASTImporter::Import(const Attr *FromAttr) { From->args_size()); break; } - case attr::CountedBy: { - AI.cloneAttr(FromAttr); - const auto *CBA = cast(FromAttr); - Expected SR = Import(CBA->getCountedByFieldLoc()).get(); - if (!SR) - return SR.takeError(); - AI.castAttrAs()->setCountedByFieldLoc(SR.get()); - break; - } default: { // The default branch works for attributes that have no arguments to import. diff --git a/clang/lib/AST/DeclBase.cpp b/clang/lib/AST/DeclBase.cpp index 8163f9bdaf8d..b1733c2d052a 100644 --- a/clang/lib/AST/DeclBase.cpp +++ b/clang/lib/AST/DeclBase.cpp @@ -29,6 +29,7 @@ #include "clang/AST/Type.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LLVM.h" +#include "clang/Basic/LangOptions.h" #include "clang/Basic/Module.h" #include "clang/Basic/ObjCRuntime.h" #include "clang/Basic/PartialDiagnostic.h" @@ -410,79 +411,6 @@ bool Decl::isFileContextDecl() const { return DC && DC->isFileContext(); } -bool Decl::isFlexibleArrayMemberLike( - ASTContext &Ctx, const Decl *D, QualType Ty, - LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, - bool IgnoreTemplateOrMacroSubstitution) { - // For compatibility with existing code, we treat arrays of length 0 or - // 1 as flexible array members. - const auto *CAT = Ctx.getAsConstantArrayType(Ty); - if (CAT) { - using FAMKind = LangOptions::StrictFlexArraysLevelKind; - - llvm::APInt Size = CAT->getSize(); - if (StrictFlexArraysLevel == FAMKind::IncompleteOnly) - return false; - - // GCC extension, only allowed to represent a FAM. - if (Size.isZero()) - return true; - - if (StrictFlexArraysLevel == FAMKind::ZeroOrIncomplete && Size.uge(1)) - return false; - - if (StrictFlexArraysLevel == FAMKind::OneZeroOrIncomplete && Size.uge(2)) - return false; - } else if (!Ctx.getAsIncompleteArrayType(Ty)) { - return false; - } - - if (const auto *OID = dyn_cast_if_present(D)) - return OID->getNextIvar() == nullptr; - - const auto *FD = dyn_cast_if_present(D); - if (!FD) - return false; - - if (CAT) { - // GCC treats an array memeber of a union as an FAM if the size is one or - // zero. - llvm::APInt Size = CAT->getSize(); - if (FD->getParent()->isUnion() && (Size.isZero() || Size.isOne())) - return true; - } - - // Don't consider sizes resulting from macro expansions or template argument - // substitution to form C89 tail-padded arrays. - if (IgnoreTemplateOrMacroSubstitution) { - TypeSourceInfo *TInfo = FD->getTypeSourceInfo(); - while (TInfo) { - TypeLoc TL = TInfo->getTypeLoc(); - - // Look through typedefs. - if (TypedefTypeLoc TTL = TL.getAsAdjusted()) { - const TypedefNameDecl *TDL = TTL.getTypedefNameDecl(); - TInfo = TDL->getTypeSourceInfo(); - continue; - } - - if (auto CTL = TL.getAs()) { - if (const Expr *SizeExpr = - dyn_cast_if_present(CTL.getSizeExpr()); - !SizeExpr || SizeExpr->getExprLoc().isMacroID()) - return false; - } - - break; - } - } - - // Test that the field is the last in the structure. - RecordDecl::field_iterator FI( - DeclContext::decl_iterator(const_cast(FD))); - return ++FI == FD->getParent()->field_end(); -} - TranslationUnitDecl *Decl::getTranslationUnitDecl() { if (auto *TUD = dyn_cast(this)) return TUD; diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp index b125fc676da8..a90f92d07f86 100644 --- a/clang/lib/AST/Expr.cpp +++ b/clang/lib/AST/Expr.cpp @@ -205,22 +205,85 @@ bool Expr::isKnownToHaveBooleanValue(bool Semantic) const { } bool Expr::isFlexibleArrayMemberLike( - ASTContext &Ctx, + ASTContext &Context, LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, bool IgnoreTemplateOrMacroSubstitution) const { + + // For compatibility with existing code, we treat arrays of length 0 or + // 1 as flexible array members. + const auto *CAT = Context.getAsConstantArrayType(getType()); + if (CAT) { + llvm::APInt Size = CAT->getSize(); + + using FAMKind = LangOptions::StrictFlexArraysLevelKind; + + if (StrictFlexArraysLevel == FAMKind::IncompleteOnly) + return false; + + // GCC extension, only allowed to represent a FAM. + if (Size == 0) + return true; + + if (StrictFlexArraysLevel == FAMKind::ZeroOrIncomplete && Size.uge(1)) + return false; + + if (StrictFlexArraysLevel == FAMKind::OneZeroOrIncomplete && Size.uge(2)) + return false; + } else if (!Context.getAsIncompleteArrayType(getType())) + return false; + const Expr *E = IgnoreParens(); - const Decl *D = nullptr; - if (const auto *ME = dyn_cast(E)) - D = ME->getMemberDecl(); - else if (const auto *DRE = dyn_cast(E)) - D = DRE->getDecl(); + const NamedDecl *ND = nullptr; + if (const auto *DRE = dyn_cast(E)) + ND = DRE->getDecl(); + else if (const auto *ME = dyn_cast(E)) + ND = ME->getMemberDecl(); else if (const auto *IRE = dyn_cast(E)) - D = IRE->getDecl(); + return IRE->getDecl()->getNextIvar() == nullptr; + + if (!ND) + return false; - return Decl::isFlexibleArrayMemberLike(Ctx, D, E->getType(), - StrictFlexArraysLevel, - IgnoreTemplateOrMacroSubstitution); + // A flexible array member must be the last member in the class. + // FIXME: If the base type of the member expr is not FD->getParent(), + // this should not be treated as a flexible array member access. + if (const auto *FD = dyn_cast(ND)) { + // GCC treats an array memeber of a union as an FAM if the size is one or + // zero. + if (CAT) { + llvm::APInt Size = CAT->getSize(); + if (FD->getParent()->isUnion() && (Size.isZero() || Size.isOne())) + return true; + } + + // Don't consider sizes resulting from macro expansions or template argument + // substitution to form C89 tail-padded arrays. + if (IgnoreTemplateOrMacroSubstitution) { + TypeSourceInfo *TInfo = FD->getTypeSourceInfo(); + while (TInfo) { + TypeLoc TL = TInfo->getTypeLoc(); + // Look through typedefs. + if (TypedefTypeLoc TTL = TL.getAsAdjusted()) { + const TypedefNameDecl *TDL = TTL.getTypedefNameDecl(); + TInfo = TDL->getTypeSourceInfo(); + continue; + } + if (ConstantArrayTypeLoc CTL = TL.getAs()) { + const Expr *SizeExpr = dyn_cast(CTL.getSizeExpr()); + if (!SizeExpr || SizeExpr->getExprLoc().isMacroID()) + return false; + } + break; + } + } + + RecordDecl::field_iterator FI( + DeclContext::decl_iterator(const_cast(FD))); + return ++FI == FD->getParent()->field_end(); + } + + return false; } const ValueDecl * diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index b5aee3eaa53c..1ed35befe136 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -25,7 +25,6 @@ #include "clang/AST/Attr.h" #include "clang/AST/Decl.h" #include "clang/AST/OSLog.h" -#include "clang/AST/OperationKinds.h" #include "clang/Basic/TargetBuiltins.h" #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" @@ -819,238 +818,6 @@ CodeGenFunction::evaluateOrEmitBuiltinObjectSize(const Expr *E, unsigned Type, return ConstantInt::get(ResType, ObjectSize, /*isSigned=*/true); } -const FieldDecl *CodeGenFunction::FindFlexibleArrayMemberField( - ASTContext &Ctx, const RecordDecl *RD, StringRef Name, uint64_t &Offset) { - const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = - getLangOpts().getStrictFlexArraysLevel(); - unsigned FieldNo = 0; - bool IsUnion = RD->isUnion(); - - for (const Decl *D : RD->decls()) { - if (const auto *Field = dyn_cast(D); - Field && (Name.empty() || Field->getNameAsString() == Name) && - Decl::isFlexibleArrayMemberLike( - Ctx, Field, Field->getType(), StrictFlexArraysLevel, - /*IgnoreTemplateOrMacroSubstitution=*/true)) { - const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); - Offset += Layout.getFieldOffset(FieldNo); - return Field; - } - - if (const auto *Record = dyn_cast(D)) - if (const FieldDecl *Field = - FindFlexibleArrayMemberField(Ctx, Record, Name, Offset)) { - const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); - Offset += Layout.getFieldOffset(FieldNo); - return Field; - } - - if (!IsUnion && isa(D)) - ++FieldNo; - } - - return nullptr; -} - -static unsigned CountCountedByAttrs(const RecordDecl *RD) { - unsigned Num = 0; - - for (const Decl *D : RD->decls()) { - if (const auto *FD = dyn_cast(D); - FD && FD->hasAttr()) { - return ++Num; - } - - if (const auto *Rec = dyn_cast(D)) - Num += CountCountedByAttrs(Rec); - } - - return Num; -} - -llvm::Value * -CodeGenFunction::emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, - llvm::IntegerType *ResType) { - // The code generated here calculates the size of a struct with a flexible - // array member that uses the counted_by attribute. There are two instances - // we handle: - // - // struct s { - // unsigned long flags; - // int count; - // int array[] __attribute__((counted_by(count))); - // } - // - // 1) bdos of the flexible array itself: - // - // __builtin_dynamic_object_size(p->array, 1) == - // p->count * sizeof(*p->array) - // - // 2) bdos of a pointer into the flexible array: - // - // __builtin_dynamic_object_size(&p->array[42], 1) == - // (p->count - 42) * sizeof(*p->array) - // - // 2) bdos of the whole struct, including the flexible array: - // - // __builtin_dynamic_object_size(p, 1) == - // max(sizeof(struct s), - // offsetof(struct s, array) + p->count * sizeof(*p->array)) - // - ASTContext &Ctx = getContext(); - const Expr *Base = E->IgnoreParenImpCasts(); - const Expr *Idx = nullptr; - - if (const auto *UO = dyn_cast(Base); - UO && UO->getOpcode() == UO_AddrOf) { - Expr *SubExpr = UO->getSubExpr()->IgnoreParenImpCasts(); - if (const auto *ASE = dyn_cast(SubExpr)) { - Base = ASE->getBase()->IgnoreParenImpCasts(); - Idx = ASE->getIdx()->IgnoreParenImpCasts(); - - if (const auto *IL = dyn_cast(Idx)) { - int64_t Val = IL->getValue().getSExtValue(); - if (Val < 0) - return getDefaultBuiltinObjectSizeResult(Type, ResType); - - if (Val == 0) - // The index is 0, so we don't need to take it into account. - Idx = nullptr; - } - } else { - // Potential pointer to another element in the struct. - Base = SubExpr; - } - } - - // Get the flexible array member Decl. - const RecordDecl *OuterRD = nullptr; - std::string FAMName; - if (const auto *ME = dyn_cast(Base)) { - // Check if \p Base is referencing the FAM itself. - const ValueDecl *VD = ME->getMemberDecl(); - OuterRD = VD->getDeclContext()->getOuterLexicalRecordContext(); - FAMName = VD->getNameAsString(); - } else if (const auto *DRE = dyn_cast(Base)) { - // Check if we're pointing to the whole struct. - QualType Ty = DRE->getDecl()->getType(); - if (Ty->isPointerType()) - Ty = Ty->getPointeeType(); - OuterRD = Ty->getAsRecordDecl(); - - // If we have a situation like this: - // - // struct union_of_fams { - // int flags; - // union { - // signed char normal_field; - // struct { - // int count1; - // int arr1[] __counted_by(count1); - // }; - // struct { - // signed char count2; - // int arr2[] __counted_by(count2); - // }; - // }; - // }; - // - // We don't know which 'count' to use in this scenario: - // - // size_t get_size(struct union_of_fams *p) { - // return __builtin_dynamic_object_size(p, 1); - // } - // - // Instead of calculating a wrong number, we give up. - if (OuterRD && CountCountedByAttrs(OuterRD) > 1) - return nullptr; - } - - if (!OuterRD) - return nullptr; - - uint64_t Offset = 0; - const FieldDecl *FAMDecl = - FindFlexibleArrayMemberField(Ctx, OuterRD, FAMName, Offset); - Offset = Ctx.toCharUnitsFromBits(Offset).getQuantity(); - - if (!FAMDecl || !FAMDecl->hasAttr()) - // No flexible array member found or it doesn't have the "counted_by" - // attribute. - return nullptr; - - const FieldDecl *CountedByFD = FindCountedByField(FAMDecl); - if (!CountedByFD) - // Can't find the field referenced by the "counted_by" attribute. - return nullptr; - - // Build a load of the counted_by field. - bool IsSigned = CountedByFD->getType()->isSignedIntegerType(); - Value *CountedByInst = EmitCountedByFieldExpr(Base, FAMDecl, CountedByFD); - if (!CountedByInst) - return getDefaultBuiltinObjectSizeResult(Type, ResType); - - CountedByInst = Builder.CreateIntCast(CountedByInst, ResType, IsSigned); - - // Build a load of the index and subtract it from the count. - Value *IdxInst = nullptr; - if (Idx) { - if (Idx->HasSideEffects(getContext())) - // We can't have side-effects. - return getDefaultBuiltinObjectSizeResult(Type, ResType); - - bool IdxSigned = Idx->getType()->isSignedIntegerType(); - IdxInst = EmitAnyExprToTemp(Idx).getScalarVal(); - IdxInst = Builder.CreateIntCast(IdxInst, ResType, IdxSigned); - - // We go ahead with the calculation here. If the index turns out to be - // negative, we'll catch it at the end. - CountedByInst = - Builder.CreateSub(CountedByInst, IdxInst, "", !IsSigned, IsSigned); - } - - // Calculate how large the flexible array member is in bytes. - const ArrayType *ArrayTy = Ctx.getAsArrayType(FAMDecl->getType()); - CharUnits Size = Ctx.getTypeSizeInChars(ArrayTy->getElementType()); - llvm::Constant *ElemSize = - llvm::ConstantInt::get(ResType, Size.getQuantity(), IsSigned); - Value *FAMSize = - Builder.CreateMul(CountedByInst, ElemSize, "", !IsSigned, IsSigned); - FAMSize = Builder.CreateIntCast(FAMSize, ResType, IsSigned); - Value *Res = FAMSize; - - if (const auto *DRE = dyn_cast(Base)) { - // The whole struct is specificed in the __bdos. - const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(OuterRD); - - // Get the offset of the FAM. - llvm::Constant *FAMOffset = ConstantInt::get(ResType, Offset, IsSigned); - Value *OffsetAndFAMSize = - Builder.CreateAdd(FAMOffset, Res, "", !IsSigned, IsSigned); - - // Get the full size of the struct. - llvm::Constant *SizeofStruct = - ConstantInt::get(ResType, Layout.getSize().getQuantity(), IsSigned); - - // max(sizeof(struct s), - // offsetof(struct s, array) + p->count * sizeof(*p->array)) - Res = IsSigned - ? Builder.CreateBinaryIntrinsic(llvm::Intrinsic::smax, - OffsetAndFAMSize, SizeofStruct) - : Builder.CreateBinaryIntrinsic(llvm::Intrinsic::umax, - OffsetAndFAMSize, SizeofStruct); - } - - // A negative \p IdxInst or \p CountedByInst means that the index lands - // outside of the flexible array member. If that's the case, we want to - // return 0. - Value *Cmp = Builder.CreateIsNotNeg(CountedByInst); - if (IdxInst) - Cmp = Builder.CreateAnd(Builder.CreateIsNotNeg(IdxInst), Cmp); - - return Builder.CreateSelect(Cmp, Res, ConstantInt::get(ResType, 0, IsSigned)); -} - /// Returns a Value corresponding to the size of the given expression. /// This Value may be either of the following: /// - A llvm::Argument (if E is a param with the pass_object_size attribute on @@ -1083,13 +850,6 @@ CodeGenFunction::emitBuiltinObjectSize(const Expr *E, unsigned Type, } } - if (IsDynamic) { - // Emit special code for a flexible array member with the "counted_by" - // attribute. - if (Value *V = emitFlexibleArrayMemberSize(E, Type, ResType)) - return V; - } - // LLVM can't handle Type=3 appropriately, and __builtin_object_size shouldn't // evaluate E for side-effects. In either case, we shouldn't lower to // @llvm.objectsize. diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index d12e85b48d0b..3f277725d9e7 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -26,12 +26,10 @@ #include "clang/AST/Attr.h" #include "clang/AST/DeclObjC.h" #include "clang/AST/NSAPI.h" -#include "clang/AST/StmtVisitor.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/CodeGenOptions.h" #include "clang/Basic/SourceManager.h" #include "llvm/ADT/Hashing.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Intrinsics.h" @@ -927,21 +925,16 @@ static llvm::Value *getArrayIndexingBound(CodeGenFunction &CGF, if (CE->getCastKind() == CK_ArrayToPointerDecay && !CE->getSubExpr()->isFlexibleArrayMemberLike(CGF.getContext(), StrictFlexArraysLevel)) { - CodeGenFunction::SanitizerScope SanScope(&CGF); - IndexedType = CE->getSubExpr()->getType(); const ArrayType *AT = IndexedType->castAsArrayTypeUnsafe(); if (const auto *CAT = dyn_cast(AT)) return CGF.Builder.getInt(CAT->getSize()); - - if (const auto *VAT = dyn_cast(AT)) + else if (const auto *VAT = dyn_cast(AT)) return CGF.getVLASize(VAT).NumElts; // Ignore pass_object_size here. It's not applicable on decayed pointers. } } - CodeGenFunction::SanitizerScope SanScope(&CGF); - QualType EltTy{Base->getType()->getPointeeOrArrayElementType(), 0}; if (llvm::Value *POS = CGF.LoadPassedObjectSize(Base, EltTy)) { IndexedType = Base->getType(); @@ -951,248 +944,22 @@ static llvm::Value *getArrayIndexingBound(CodeGenFunction &CGF, return nullptr; } -namespace { - -/// \p StructAccessBase returns the base \p Expr of a field access. It returns -/// either a \p DeclRefExpr, representing the base pointer to the struct, i.e.: -/// -/// p in p-> a.b.c -/// -/// or a \p MemberExpr, if the \p MemberExpr has the \p RecordDecl we're -/// looking for: -/// -/// struct s { -/// struct s *ptr; -/// int count; -/// char array[] __attribute__((counted_by(count))); -/// }; -/// -/// If we have an expression like \p p->ptr->array[index], we want the -/// \p MemberExpr for \p p->ptr instead of \p p. -class StructAccessBase - : public ConstStmtVisitor { - const RecordDecl *ExpectedRD; - - bool IsExpectedRecordDecl(const Expr *E) const { - QualType Ty = E->getType(); - if (Ty->isPointerType()) - Ty = Ty->getPointeeType(); - return ExpectedRD == Ty->getAsRecordDecl(); - } - -public: - StructAccessBase(const RecordDecl *ExpectedRD) : ExpectedRD(ExpectedRD) {} - - //===--------------------------------------------------------------------===// - // Visitor Methods - //===--------------------------------------------------------------------===// - - // NOTE: If we build C++ support for counted_by, then we'll have to handle - // horrors like this: - // - // struct S { - // int x, y; - // int blah[] __attribute__((counted_by(x))); - // } s; - // - // int foo(int index, int val) { - // int (S::*IHatePMDs)[] = &S::blah; - // (s.*IHatePMDs)[index] = val; - // } - - const Expr *Visit(const Expr *E) { - return ConstStmtVisitor::Visit(E); - } - - const Expr *VisitStmt(const Stmt *S) { return nullptr; } - - // These are the types we expect to return (in order of most to least - // likely): - // - // 1. DeclRefExpr - This is the expression for the base of the structure. - // It's exactly what we want to build an access to the \p counted_by - // field. - // 2. MemberExpr - This is the expression that has the same \p RecordDecl - // as the flexble array member's lexical enclosing \p RecordDecl. This - // allows us to catch things like: "p->p->array" - // 3. CompoundLiteralExpr - This is for people who create something - // heretical like (struct foo has a flexible array member): - // - // (struct foo){ 1, 2 }.blah[idx]; - const Expr *VisitDeclRefExpr(const DeclRefExpr *E) { - return IsExpectedRecordDecl(E) ? E : nullptr; - } - const Expr *VisitMemberExpr(const MemberExpr *E) { - if (IsExpectedRecordDecl(E) && E->isArrow()) - return E; - const Expr *Res = Visit(E->getBase()); - return !Res && IsExpectedRecordDecl(E) ? E : Res; - } - const Expr *VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) { - return IsExpectedRecordDecl(E) ? E : nullptr; - } - const Expr *VisitCallExpr(const CallExpr *E) { - return IsExpectedRecordDecl(E) ? E : nullptr; - } - - const Expr *VisitArraySubscriptExpr(const ArraySubscriptExpr *E) { - if (IsExpectedRecordDecl(E)) - return E; - return Visit(E->getBase()); - } - const Expr *VisitCastExpr(const CastExpr *E) { - return Visit(E->getSubExpr()); - } - const Expr *VisitParenExpr(const ParenExpr *E) { - return Visit(E->getSubExpr()); - } - const Expr *VisitUnaryAddrOf(const UnaryOperator *E) { - return Visit(E->getSubExpr()); - } - const Expr *VisitUnaryDeref(const UnaryOperator *E) { - return Visit(E->getSubExpr()); - } -}; - -} // end anonymous namespace - -using RecIndicesTy = - SmallVector, 8>; - -static bool getGEPIndicesToField(CodeGenFunction &CGF, const RecordDecl *RD, - const FieldDecl *FD, RecIndicesTy &Indices) { - const CGRecordLayout &Layout = CGF.CGM.getTypes().getCGRecordLayout(RD); - int64_t FieldNo = -1; - for (const Decl *D : RD->decls()) { - if (const auto *Field = dyn_cast(D)) { - FieldNo = Layout.getLLVMFieldNo(Field); - if (FD == Field) { - Indices.emplace_back(std::make_pair(RD, CGF.Builder.getInt32(FieldNo))); - return true; - } - } - - if (const auto *Record = dyn_cast(D)) { - ++FieldNo; - if (getGEPIndicesToField(CGF, Record, FD, Indices)) { - if (RD->isUnion()) - FieldNo = 0; - Indices.emplace_back(std::make_pair(RD, CGF.Builder.getInt32(FieldNo))); - return true; - } - } - } - - return false; -} - -/// This method is typically called in contexts where we can't generate -/// side-effects, like in __builtin_dynamic_object_size. When finding -/// expressions, only choose those that have either already been emitted or can -/// be loaded without side-effects. -/// -/// - \p FAMDecl: the \p Decl for the flexible array member. It may not be -/// within the top-level struct. -/// - \p CountDecl: must be within the same non-anonymous struct as \p FAMDecl. -llvm::Value *CodeGenFunction::EmitCountedByFieldExpr( - const Expr *Base, const FieldDecl *FAMDecl, const FieldDecl *CountDecl) { - const RecordDecl *RD = CountDecl->getParent()->getOuterLexicalRecordContext(); - - // Find the base struct expr (i.e. p in p->a.b.c.d). - const Expr *StructBase = StructAccessBase(RD).Visit(Base); - if (!StructBase || StructBase->HasSideEffects(getContext())) - return nullptr; - - llvm::Value *Res = nullptr; - if (const auto *DRE = dyn_cast(StructBase)) { - Res = EmitDeclRefLValue(DRE).getPointer(*this); - Res = Builder.CreateAlignedLoad(ConvertType(DRE->getType()), Res, - getPointerAlign(), "dre.load"); - } else if (const MemberExpr *ME = dyn_cast(StructBase)) { - LValue LV = EmitMemberExpr(ME); - Address Addr = LV.getAddress(*this); - Res = Addr.getPointer(); - } else if (StructBase->getType()->isPointerType()) { - LValueBaseInfo BaseInfo; - TBAAAccessInfo TBAAInfo; - Address Addr = EmitPointerWithAlignment(StructBase, &BaseInfo, &TBAAInfo); - Res = Addr.getPointer(); - } else { - return nullptr; - } - - llvm::Value *Zero = Builder.getInt32(0); - RecIndicesTy Indices; - - getGEPIndicesToField(*this, RD, CountDecl, Indices); - - for (auto I = Indices.rbegin(), E = Indices.rend(); I != E; ++I) - Res = Builder.CreateInBoundsGEP( - ConvertType(QualType(I->first->getTypeForDecl(), 0)), Res, - {Zero, I->second}, "..counted_by.gep"); - - return Builder.CreateAlignedLoad(ConvertType(CountDecl->getType()), Res, - getIntAlign(), "..counted_by.load"); -} - -const FieldDecl *CodeGenFunction::FindCountedByField(const FieldDecl *FD) { - if (!FD || !FD->hasAttr()) - return nullptr; - - const auto *CBA = FD->getAttr(); - if (!CBA) - return nullptr; - - auto GetNonAnonStructOrUnion = - [](const RecordDecl *RD) -> const RecordDecl * { - while (RD && RD->isAnonymousStructOrUnion()) { - const auto *R = dyn_cast(RD->getDeclContext()); - if (!R) - return nullptr; - RD = R; - } - return RD; - }; - const RecordDecl *EnclosingRD = GetNonAnonStructOrUnion(FD->getParent()); - if (!EnclosingRD) - return nullptr; - - DeclarationName DName(CBA->getCountedByField()); - DeclContext::lookup_result Lookup = EnclosingRD->lookup(DName); - - if (Lookup.empty()) - return nullptr; - - const NamedDecl *ND = Lookup.front(); - if (const auto *IFD = dyn_cast(ND)) - ND = IFD->getAnonField(); - - return dyn_cast(ND); -} - void CodeGenFunction::EmitBoundsCheck(const Expr *E, const Expr *Base, llvm::Value *Index, QualType IndexType, bool Accessed) { assert(SanOpts.has(SanitizerKind::ArrayBounds) && "should not be called unless adding bounds checks"); + SanitizerScope SanScope(this); + const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = - getLangOpts().getStrictFlexArraysLevel(); + getLangOpts().getStrictFlexArraysLevel(); + QualType IndexedType; llvm::Value *Bound = getArrayIndexingBound(*this, Base, IndexedType, StrictFlexArraysLevel); - - EmitBoundsCheckImpl(E, Bound, Index, IndexType, IndexedType, Accessed); -} - -void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, - llvm::Value *Index, - QualType IndexType, - QualType IndexedType, bool Accessed) { if (!Bound) return; - SanitizerScope SanScope(this); - bool IndexSigned = IndexType->isSignedIntegerOrEnumerationType(); llvm::Value *IndexVal = Builder.CreateIntCast(Index, SizeTy, IndexSigned); llvm::Value *BoundVal = Builder.CreateIntCast(Bound, SizeTy, false); @@ -1208,6 +975,7 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, SanitizerHandler::OutOfBounds, StaticData, Index); } + CodeGenFunction::ComplexPairTy CodeGenFunction:: EmitComplexPrePostIncDec(const UnaryOperator *E, LValue LV, bool isInc, bool isPre) { @@ -4055,61 +3823,6 @@ static Address emitArraySubscriptGEP(CodeGenFunction &CGF, Address addr, return Address(eltPtr, CGF.ConvertTypeForMem(eltType), eltAlign); } -/// The offset of a field from the beginning of the record. -static bool getFieldOffsetInBits(CodeGenFunction &CGF, const RecordDecl *RD, - const FieldDecl *FD, int64_t &Offset) { - ASTContext &Ctx = CGF.getContext(); - const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); - unsigned FieldNo = 0; - - for (const Decl *D : RD->decls()) { - if (const auto *Record = dyn_cast(D)) - if (getFieldOffsetInBits(CGF, Record, FD, Offset)) { - Offset += Layout.getFieldOffset(FieldNo); - return true; - } - - if (const auto *Field = dyn_cast(D)) - if (FD == Field) { - Offset += Layout.getFieldOffset(FieldNo); - return true; - } - - if (isa(D)) - ++FieldNo; - } - - return false; -} - -/// Returns the relative offset difference between \p FD1 and \p FD2. -/// \code -/// offsetof(struct foo, FD1) - offsetof(struct foo, FD2) -/// \endcode -/// Both fields must be within the same struct. -static std::optional getOffsetDifferenceInBits(CodeGenFunction &CGF, - const FieldDecl *FD1, - const FieldDecl *FD2) { - const RecordDecl *FD1OuterRec = - FD1->getParent()->getOuterLexicalRecordContext(); - const RecordDecl *FD2OuterRec = - FD2->getParent()->getOuterLexicalRecordContext(); - - if (FD1OuterRec != FD2OuterRec) - // Fields must be within the same RecordDecl. - return std::optional(); - - int64_t FD1Offset = 0; - if (!getFieldOffsetInBits(CGF, FD1OuterRec, FD1, FD1Offset)) - return std::optional(); - - int64_t FD2Offset = 0; - if (!getFieldOffsetInBits(CGF, FD2OuterRec, FD2, FD2Offset)) - return std::optional(); - - return std::make_optional(FD1Offset - FD2Offset); -} - LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E, bool Accessed) { // The index must always be an integer, which is not an aggregate. Emit it @@ -4237,47 +3950,6 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E, ArrayLV = EmitLValue(Array); auto *Idx = EmitIdxAfterBase(/*Promote*/true); - if (SanOpts.has(SanitizerKind::ArrayBounds)) { - // If the array being accessed has a "counted_by" attribute, generate - // bounds checking code. The "count" field is at the top level of the - // struct or in an anonymous struct, that's also at the top level. Future - // expansions may allow the "count" to reside at any place in the struct, - // but the value of "counted_by" will be a "simple" path to the count, - // i.e. "a.b.count", so we shouldn't need the full force of EmitLValue or - // similar to emit the correct GEP. - const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = - getLangOpts().getStrictFlexArraysLevel(); - - if (const auto *ME = dyn_cast(Array); - ME && - ME->isFlexibleArrayMemberLike(getContext(), StrictFlexArraysLevel) && - ME->getMemberDecl()->hasAttr()) { - const FieldDecl *FAMDecl = dyn_cast(ME->getMemberDecl()); - if (const FieldDecl *CountFD = FindCountedByField(FAMDecl)) { - if (std::optional Diff = - getOffsetDifferenceInBits(*this, CountFD, FAMDecl)) { - CharUnits OffsetDiff = CGM.getContext().toCharUnitsFromBits(*Diff); - - // Create a GEP with a byte offset between the FAM and count and - // use that to load the count value. - Addr = Builder.CreatePointerBitCastOrAddrSpaceCast( - ArrayLV.getAddress(*this), Int8PtrTy, Int8Ty); - - llvm::Type *CountTy = ConvertType(CountFD->getType()); - llvm::Value *Res = Builder.CreateInBoundsGEP( - Int8Ty, Addr.getPointer(), - Builder.getInt32(OffsetDiff.getQuantity()), ".counted_by.gep"); - Res = Builder.CreateAlignedLoad(CountTy, Res, getIntAlign(), - ".counted_by.load"); - - // Now emit the bounds checking. - EmitBoundsCheckImpl(E, Res, Idx, E->getIdx()->getType(), - Array->getType(), Accessed); - } - } - } - } - // Propagate the alignment from the array itself to the result. QualType arrayType = Array->getType(); Addr = emitArraySubscriptGEP( diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 143ad64e8816..07c7678df87e 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3073,25 +3073,6 @@ public: /// this expression is used as an lvalue, for instance in "&Arr[Idx]". void EmitBoundsCheck(const Expr *E, const Expr *Base, llvm::Value *Index, QualType IndexType, bool Accessed); - void EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, - llvm::Value *Index, QualType IndexType, - QualType IndexedType, bool Accessed); - - // Find a struct's flexible array member. It may be embedded inside multiple - // sub-structs, but must still be the last field. - const FieldDecl *FindFlexibleArrayMemberField(ASTContext &Ctx, - const RecordDecl *RD, - StringRef Name, - uint64_t &Offset); - - /// Find the FieldDecl specified in a FAM's "counted_by" attribute. Returns - /// \p nullptr if either the attribute or the field doesn't exist. - const FieldDecl *FindCountedByField(const FieldDecl *FD); - - /// Build an expression accessing the "counted_by" field. - llvm::Value *EmitCountedByFieldExpr(const Expr *Base, - const FieldDecl *FAMDecl, - const FieldDecl *CountDecl); llvm::Value *EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, bool isInc, bool isPre); @@ -4892,9 +4873,6 @@ private: llvm::Value *EmittedE, bool IsDynamic); - llvm::Value *emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, - llvm::IntegerType *ResType); - void emitZeroOrPatternForAutoVarInit(QualType type, const VarDecl &D, Address Loc); diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index e92fd104d78e..8e46c4984d93 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -2315,12 +2315,6 @@ void Sema::ActOnPopScope(SourceLocation Loc, Scope *S) { } ShadowingDecls.erase(ShadowI); } - - if (!getLangOpts().CPlusPlus && S->isClassScope()) { - if (auto *FD = dyn_cast(TmpD); - FD && FD->hasAttr()) - CheckCountedByAttr(S, FD); - } } llvm::sort(DeclDiags, diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 1a58cfd8e417..d059b406ef86 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -8460,135 +8460,6 @@ static void handleZeroCallUsedRegsAttr(Sema &S, Decl *D, const ParsedAttr &AL) { D->addAttr(ZeroCallUsedRegsAttr::Create(S.Context, Kind, AL)); } -static void handleCountedByAttr(Sema &S, Decl *D, const ParsedAttr &AL) { - if (!AL.isArgIdent(0)) { - S.Diag(AL.getLoc(), diag::err_attribute_argument_type) - << AL << AANT_ArgumentIdentifier; - return; - } - - IdentifierLoc *IL = AL.getArgAsIdent(0); - CountedByAttr *CBA = - ::new (S.Context) CountedByAttr(S.Context, AL, IL->Ident); - CBA->setCountedByFieldLoc(IL->Loc); - D->addAttr(CBA); -} - -static const FieldDecl * -FindFieldInTopLevelOrAnonymousStruct(const RecordDecl *RD, - const IdentifierInfo *FieldName) { - for (const Decl *D : RD->decls()) { - if (const auto *FD = dyn_cast(D)) - if (FD->getName() == FieldName->getName()) - return FD; - - if (const auto *R = dyn_cast(D)) - if (const FieldDecl *FD = - FindFieldInTopLevelOrAnonymousStruct(R, FieldName)) - return FD; - } - - return nullptr; -} - -bool Sema::CheckCountedByAttr(Scope *S, const FieldDecl *FD) { - LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = - LangOptions::StrictFlexArraysLevelKind::IncompleteOnly; - if (!Decl::isFlexibleArrayMemberLike(Context, FD, FD->getType(), - StrictFlexArraysLevel, true)) { - // The "counted_by" attribute must be on a flexible array member. - SourceRange SR = FD->getLocation(); - Diag(SR.getBegin(), diag::err_counted_by_attr_not_on_flexible_array_member) - << SR; - return true; - } - - const auto *CBA = FD->getAttr(); - const IdentifierInfo *FieldName = CBA->getCountedByField(); - - auto GetNonAnonStructOrUnion = [](const RecordDecl *RD) { - while (RD && !RD->getDeclName()) - if (const auto *R = dyn_cast(RD->getDeclContext())) - RD = R; - else - break; - - return RD; - }; - - const RecordDecl *EnclosingRD = GetNonAnonStructOrUnion(FD->getParent()); - const FieldDecl *CountFD = - FindFieldInTopLevelOrAnonymousStruct(EnclosingRD, FieldName); - - if (!CountFD) { - DeclarationNameInfo NameInfo(FieldName, - CBA->getCountedByFieldLoc().getBegin()); - LookupResult MemResult(*this, NameInfo, Sema::LookupMemberName); - LookupName(MemResult, S); - - if (!MemResult.empty()) { - SourceRange SR = CBA->getCountedByFieldLoc(); - Diag(SR.getBegin(), diag::err_flexible_array_count_not_in_same_struct) - << CBA->getCountedByField() << SR; - - if (auto *ND = MemResult.getAsSingle()) { - SR = ND->getLocation(); - Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) - << ND << SR; - } - - return true; - } else { - // The "counted_by" field needs to exist in the struct. - LookupResult OrdResult(*this, NameInfo, Sema::LookupOrdinaryName); - LookupName(OrdResult, S); - - if (!OrdResult.empty()) { - SourceRange SR = FD->getLocation(); - Diag(SR.getBegin(), diag::err_counted_by_must_be_in_structure) - << FieldName << SR; - - if (auto *ND = OrdResult.getAsSingle()) { - SR = ND->getLocation(); - Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) - << ND << SR; - } - - return true; - } - } - - CXXScopeSpec SS; - DeclFilterCCC Filter(FieldName); - return DiagnoseEmptyLookup(S, SS, MemResult, Filter, nullptr, std::nullopt, - const_cast(FD->getDeclContext())); - } - - if (CountFD->hasAttr()) { - // The "counted_by" field can't point to the flexible array member. - SourceRange SR = CBA->getCountedByFieldLoc(); - Diag(SR.getBegin(), diag::err_counted_by_attr_refers_to_flexible_array) - << CBA->getCountedByField() << SR; - return true; - } - - if (!CountFD->getType()->isIntegerType() || - CountFD->getType()->isBooleanType()) { - // The "counted_by" field must have an integer type. - SourceRange SR = CBA->getCountedByFieldLoc(); - Diag(SR.getBegin(), - diag::err_flexible_array_counted_by_attr_field_not_integer) - << CBA->getCountedByField() << SR; - - SR = CountFD->getLocation(); - Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) - << CountFD << SR; - return true; - } - - return false; -} - static void handleFunctionReturnThunksAttr(Sema &S, Decl *D, const ParsedAttr &AL) { StringRef KindStr; @@ -9549,10 +9420,6 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, handleAvailableOnlyInDefaultEvalMethod(S, D, AL); break; - case ParsedAttr::AT_CountedBy: - handleCountedByAttr(S, D, AL); - break; - // Microsoft attributes: case ParsedAttr::AT_LayoutVersion: handleLayoutVersion(S, D, AL); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 2f48ea237cdf..60ad035570c8 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -2469,8 +2469,7 @@ bool Sema::DiagnoseDependentMemberLookup(const LookupResult &R) { bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, CorrectionCandidateCallback &CCC, TemplateArgumentListInfo *ExplicitTemplateArgs, - ArrayRef Args, DeclContext *LookupCtx, - TypoExpr **Out) { + ArrayRef Args, TypoExpr **Out) { DeclarationName Name = R.getLookupName(); unsigned diagnostic = diag::err_undeclared_var_use; @@ -2486,8 +2485,7 @@ bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, // unqualified lookup. This is useful when (for example) the // original lookup would not have found something because it was a // dependent name. - DeclContext *DC = - LookupCtx ? LookupCtx : (SS.isEmpty() ? CurContext : nullptr); + DeclContext *DC = SS.isEmpty() ? CurContext : nullptr; while (DC) { if (isa(DC)) { LookupQualifiedName(R, DC); @@ -2530,12 +2528,12 @@ bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, emitEmptyLookupTypoDiagnostic(TC, *this, SS, Name, TypoLoc, Args, diagnostic, diagnostic_suggest); }, - nullptr, CTK_ErrorRecovery, LookupCtx); + nullptr, CTK_ErrorRecovery); if (*Out) return true; - } else if (S && (Corrected = - CorrectTypo(R.getLookupNameInfo(), R.getLookupKind(), S, - &SS, CCC, CTK_ErrorRecovery, LookupCtx))) { + } else if (S && + (Corrected = CorrectTypo(R.getLookupNameInfo(), R.getLookupKind(), + S, &SS, CCC, CTK_ErrorRecovery))) { std::string CorrectedStr(Corrected.getAsString(getLangOpts())); bool DroppedSpecifier = Corrected.WillReplaceSpecifier() && Name.getAsString() == CorrectedStr; @@ -2825,7 +2823,7 @@ Sema::ActOnIdExpression(Scope *S, CXXScopeSpec &SS, // a template name, but we happen to have always already looked up the name // before we get here if it must be a template name. if (DiagnoseEmptyLookup(S, SS, R, CCC ? *CCC : DefaultValidator, nullptr, - std::nullopt, nullptr, &TE)) { + std::nullopt, &TE)) { if (TE && KeywordReplacement) { auto &State = getTypoExprState(TE); auto BestTC = State.Consumer->getNextCorrection(); diff --git a/clang/test/CodeGen/attr-counted-by.c b/clang/test/CodeGen/attr-counted-by.c deleted file mode 100644 index c59749acc536..000000000000 --- a/clang/test/CodeGen/attr-counted-by.c +++ /dev/null @@ -1,1828 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -DCOUNTED_BY -O2 -Wall -fsanitize=array-bounds,object-size,local-bounds -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=SANITIZE-WITH-ATTR %s -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -DCOUNTED_BY -O2 -Wall -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=NO-SANITIZE-WITH-ATTR %s -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O2 -Wall -fsanitize=array-bounds,object-size,local-bounds -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=SANITIZE-WITHOUT-ATTR %s -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O2 -Wall -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=NO-SANITIZE-WITHOUT-ATTR %s - -#if !__has_attribute(counted_by) -#error "has attribute broken" -#endif - -#ifdef COUNTED_BY -#define __counted_by(member) __attribute__((__counted_by__(member))) -#else -#define __counted_by(member) -#endif - -#define DECLARE_FLEX_ARRAY(TYPE, NAME) \ - struct { \ - struct { } __empty_ ## NAME; \ - TYPE NAME[]; \ - } - -#define DECLARE_BOUNDED_FLEX_ARRAY(COUNT_TYPE, COUNT, TYPE, NAME) \ - struct { \ - COUNT_TYPE COUNT; \ - TYPE NAME[] __counted_by(COUNT); \ - } - -#define DECLARE_FLEX_ARRAY_COUNTED_BY(TYPE, NAME, COUNTED_BY) \ - struct { \ - struct { } __empty_ ## NAME; \ - TYPE NAME[] __counted_by(COUNTED_BY); \ - } - -typedef long unsigned int size_t; - -struct annotated { - unsigned long flags; - int count; - int array[] __counted_by(count); -}; - -struct union_of_fams { - unsigned long flags; - union { - /* count member type intentionally mismatched to induce padding */ - DECLARE_BOUNDED_FLEX_ARRAY(int, count_bytes, unsigned char, bytes); - DECLARE_BOUNDED_FLEX_ARRAY(unsigned char, count_ints, unsigned char, ints); - DECLARE_FLEX_ARRAY(unsigned char, unsafe); - }; -}; - -struct anon_struct { - unsigned long flags; - size_t count; - DECLARE_FLEX_ARRAY_COUNTED_BY(int, array, count); -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test1( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2:![0-9]+]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3:![0-9]+]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB2:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12:[0-9]+]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4:![0-9]+]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test1( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test1( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test1( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test1(struct annotated *p, int index, int val) { - p->array[index] = val; -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test2( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], [[INDEX]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB4:[0-9]+]], i64 [[INDEX]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP2]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test2( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP0]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test2( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test2( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test2(struct annotated *p, size_t index) { - p->array[index] = __builtin_dynamic_object_size(p->array, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test2_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 -// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 [[TMP1]], i64 0 -// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP3]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test2_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 [[TMP1]], i64 0 -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP3]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test2_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test2_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test2_bdos(struct annotated *p) { - return __builtin_dynamic_object_size(p->array, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test3( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], [[INDEX]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB5:[0-9]+]], i64 [[INDEX]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP3]], i64 4) -// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32 -// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 12 -// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP6]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test3( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 12 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP4]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test3( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test3( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test3(struct annotated *p, size_t index) { - // This test differs from 'test2' by checking bdos on the whole array and not - // just the FAM. - p->array[index] = __builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test3_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) -// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 12 -// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 -// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP3]], i64 0 -// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP5]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test3_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR5:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 12 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP3]], i64 0 -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP5]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test3_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test3_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test3_bdos(struct annotated *p) { - return __builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test4( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT4:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB6:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont4: -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 244 -// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 252 -// SANITIZE-WITH-ATTR-NEXT: [[CONV1:%.*]] = select i1 [[TMP2]], i32 [[TMP5]], i32 0 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV1]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD7:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM13:%.*]] = sext i32 [[ADD]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD7]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = icmp ult i64 [[IDXPROM13]], [[TMP6]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP7]], label [[CONT20:%.*]], label [[HANDLER_OUT_OF_BOUNDS16:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds16: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB7:[0-9]+]], i64 [[IDXPROM13]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont20: -// SANITIZE-WITH-ATTR-NEXT: [[TMP8:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD7]], 3 -// SANITIZE-WITH-ATTR-NEXT: [[TMP9:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD7]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 240 -// SANITIZE-WITH-ATTR-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 252 -// SANITIZE-WITH-ATTR-NEXT: [[CONV9:%.*]] = select i1 [[TMP8]], i32 [[TMP11]], i32 0 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM13]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV9]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD23:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[ADD29:%.*]] = add nsw i32 [[INDEX]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM30:%.*]] = sext i32 [[ADD29]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP12:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD23]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP13:%.*]] = icmp ult i64 [[IDXPROM30]], [[TMP12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP13]], label [[CONT37:%.*]], label [[HANDLER_OUT_OF_BOUNDS33:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds33: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB8:[0-9]+]], i64 [[IDXPROM30]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont37: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM30]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP14:%.*]] = icmp sgt i32 [[FAM_IDX]], -1 -// SANITIZE-WITH-ATTR-NEXT: [[TMP15:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD23]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP16:%.*]] = sext i32 [[FAM_IDX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP17:%.*]] = sub nsw i64 [[TMP15]], [[TMP16]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[TMP17]], -1 -// SANITIZE-WITH-ATTR-NEXT: [[TMP19:%.*]] = and i1 [[TMP14]], [[TMP18]] -// SANITIZE-WITH-ATTR-NEXT: [[DOTTR:%.*]] = trunc i64 [[TMP17]] to i32 -// SANITIZE-WITH-ATTR-NEXT: [[TMP20:%.*]] = shl i32 [[DOTTR]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP21:%.*]] = and i32 [[TMP20]], 252 -// SANITIZE-WITH-ATTR-NEXT: [[CONV25:%.*]] = select i1 [[TMP19]], i32 [[TMP21]], i32 0 -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV25]], ptr [[ARRAYIDX35]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test4( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 244 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 252 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV1:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV1]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD4:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD4]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 240 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD4]], 3 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = and i32 [[TMP5]], 252 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV6:%.*]] = select i1 [[TMP6]], i32 [[TMP7]], i32 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM8:%.*]] = sext i32 [[ADD]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM8]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV6]], ptr [[ARRAYIDX9]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD12:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP8:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD12]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP9:%.*]] = sext i32 [[FAM_IDX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP10:%.*]] = sub nsw i64 [[TMP8]], [[TMP9]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP11:%.*]] = icmp sgt i64 [[TMP10]], -1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP12:%.*]] = icmp sgt i32 [[FAM_IDX]], -1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP13:%.*]] = and i1 [[TMP12]], [[TMP11]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTTR:%.*]] = trunc i64 [[TMP10]] to i32 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP14:%.*]] = shl i32 [[DOTTR]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP15:%.*]] = and i32 [[TMP14]], 252 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV14:%.*]] = select i1 [[TMP13]], i32 [[TMP15]], i32 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ADD16:%.*]] = add nsw i32 [[INDEX]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM17:%.*]] = sext i32 [[ADD16]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM17]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV14]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test4( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM17:%.*]] = sext i32 [[ADD]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM17]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[ADD31:%.*]] = add nsw i32 [[INDEX]], 2 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM32:%.*]] = sext i32 [[ADD31]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM32]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX33]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test4( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX3]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM9:%.*]] = sext i32 [[ADD]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM9]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX10]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ADD17:%.*]] = add nsw i32 [[INDEX]], 2 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM18:%.*]] = sext i32 [[ADD17]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM18]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX19]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test4(struct annotated *p, int index, int fam_idx) { - // This tests calculating the size from a pointer inside the FAM. - p->array[index] = (unsigned char)__builtin_dynamic_object_size(&p->array[3], 1); - p->array[index + 1] = (unsigned char)__builtin_dynamic_object_size(&(p->array[4]), 1); - p->array[index + 2] = (unsigned char)__builtin_dynamic_object_size(&(p->array[fam_idx]), 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test4_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sub nsw i64 [[TMP0]], [[TMP1]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i64 [[TMP2]], -1 -// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[INDEX]], -1 -// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = and i1 [[TMP5]], [[TMP4]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 [[TMP3]], i64 0 -// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP7]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test4_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sub nsw i64 [[TMP0]], [[TMP1]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i64 [[TMP2]], -1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[INDEX]], -1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = and i1 [[TMP5]], [[TMP4]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 [[TMP3]], i64 0 -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP7]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test4_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test4_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test4_bdos(struct annotated *p, int index) { - return __builtin_dynamic_object_size(&p->array[index], 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test5( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[DOT_COUNTED_BY_LOAD]], [[IDXPROM]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB9:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 16 -// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP2]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test5( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 16 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test5( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test5( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test5(struct anon_struct *p, int index) { - p->array[index] = __builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test5_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add nuw i64 [[TMP0]], 16 -// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP1]] -// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP2]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test5_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add nuw i64 [[TMP0]], 16 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP1]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP2]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test5_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test5_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test5_bdos(struct anon_struct *p) { - return __builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test6( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[DOT_COUNTED_BY_LOAD]], [[IDXPROM]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB10:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test6( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP0]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test6( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test6( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test6(struct anon_struct *p, int index) { - p->array[index] = __builtin_dynamic_object_size(p->array, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test6_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP0]] -// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP1]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test6_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP0]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP1]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test6_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test6_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test6_bdos(struct anon_struct *p) { - return __builtin_dynamic_object_size(p->array, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test7( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i8, ptr [[TMP0]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i8 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP1]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT7:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB12:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont7: -// SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8:![0-9]+]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test7( -// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test7( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test7( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test7(struct union_of_fams *p, int index) { - p->ints[index] = __builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test7_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR5:[0-9]+]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test7_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test7_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test7_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test7_bdos(struct union_of_fams *p) { - return __builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test8( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT9:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB13:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont9: -// SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: store i8 [[DOT_COUNTED_BY_LOAD]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test8( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i8 [[DOT_COUNTED_BY_LOAD]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test8( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test8( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test8(struct union_of_fams *p, int index) { - p->ints[index] = __builtin_dynamic_object_size(p->ints, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test8_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64 -// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test8_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test8_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test8_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test8_bdos(struct union_of_fams *p) { - return __builtin_dynamic_object_size(p->ints, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test9( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[TMP0]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP1]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT7:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB14:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont7: -// SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test9( -// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR6]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test9( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test9( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test9(struct union_of_fams *p, int index) { - p->bytes[index] = (unsigned char)__builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test9_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR5]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test9_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR7]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test9_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test9_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test9_bdos(struct union_of_fams *p) { - return __builtin_dynamic_object_size(p, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test10( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT9:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB15:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont9: -// SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) -// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = trunc i32 [[NARROW]] to i8 -// SANITIZE-WITH-ATTR-NEXT: store i8 [[CONV]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test10( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR3]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = trunc i32 [[NARROW]] to i8 -// NO-SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i8 [[CONV]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test10( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test10( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test10(struct union_of_fams *p, int index) { - p->bytes[index] = (unsigned char)__builtin_dynamic_object_size(p->bytes, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test10_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext nneg i32 [[NARROW]] to i64 -// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test10_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR5]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext nneg i32 [[NARROW]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test10_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test10_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test10_bdos(struct union_of_fams *p) { - return __builtin_dynamic_object_size(p->bytes, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test11( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB16:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test11( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test11( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test11( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test11(struct annotated *p, int index) { - p->array[index] = __builtin_dynamic_object_size(&p->count, 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test11_bdos( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 4 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test11_bdos( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 4 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test11_bdos( -// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 4 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test11_bdos( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 4 -// -size_t test11_bdos(struct annotated *p) { - return __builtin_dynamic_object_size(&p->count, 1); -} - -struct { - struct { - struct { - int num_entries; - }; - }; - int entries[] __attribute__((__counted_by__(num_entries))); -} test12_foo; - -struct hang { - int entries[6]; -} test12_bar; - -int test12_a, test12_b; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test12( -// SANITIZE-WITH-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 -// SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR13:[0-9]+]] -// SANITIZE-WITH-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT9:![0-9]+]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[INDEX]], 6 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB18:[0-9]+]], i64 [[TMP1]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[TMP1]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP2]], ptr @test12_b, align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr @test12_foo, align 4 -// SANITIZE-WITH-ATTR-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[DOTCOUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: br i1 [[DOTNOT]], label [[HANDLER_OUT_OF_BOUNDS4:%.*]], label [[HANDLER_TYPE_MISMATCH6:%.*]], !prof [[PROF10:![0-9]+]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds4: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB19:[0-9]+]], i64 0) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.type_mismatch6: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_type_mismatch_v1_abort(ptr nonnull @[[GLOB20:[0-9]+]], i64 ptrtoint (ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0) to i64)) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test12( -// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR9:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR16:[0-9]+]] -// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0), align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP1]], ptr @test12_a, align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: br label [[FOR_COND:%.*]] -// NO-SANITIZE-WITH-ATTR: for.cond: -// NO-SANITIZE-WITH-ATTR-NEXT: br label [[FOR_COND]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test12( -// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 -// SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR8:[0-9]+]] -// SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[INDEX]], 6 -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[CONT:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8:![0-9]+]], !nosanitize [[META9:![0-9]+]] -// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB2:[0-9]+]], i64 [[TMP1]]) #[[ATTR9:[0-9]+]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: cont: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[TMP1]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP2]], ptr @test12_b, align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr @test12_foo, align 4 -// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[DOTCOUNTED_BY_LOAD]], 0 -// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[DOTNOT]], label [[HANDLER_OUT_OF_BOUNDS4:%.*]], label [[HANDLER_TYPE_MISMATCH6:%.*]], !prof [[PROF10:![0-9]+]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds4: -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB4:[0-9]+]], i64 0) #[[ATTR9]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: handler.type_mismatch6: -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_type_mismatch_v1_abort(ptr nonnull @[[GLOB5:[0-9]+]], i64 ptrtoint (ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0) to i64)) #[[ATTR9]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test12( -// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR11:[0-9]+]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0), align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP1]], ptr @test12_a, align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: br label [[FOR_COND:%.*]] -// NO-SANITIZE-WITHOUT-ATTR: for.cond: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: br label [[FOR_COND]] -// -int test12(int index) { - struct hang baz = test12_bar; - - for (;; test12_a = (&test12_foo)->entries[0]) - test12_b = baz.entries[index]; - - return test12_b; -} - -struct test13_foo { - struct test13_bar *domain; -} test13_f; - -struct test13_bar { - struct test13_bar *parent; - int revmap_size; - struct test13_foo *revmap[] __attribute__((__counted_by__(revmap_size))); -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test13( -// SANITIZE-WITH-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA11:![0-9]+]] -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], [[INDEX]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB23:[0-9]+]], i64 [[INDEX]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont5: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] -// SANITIZE-WITH-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14:![0-9]+]] -// SANITIZE-WITH-ATTR-NEXT: ret i32 0 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test13( -// NO-SANITIZE-WITH-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR12:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA8:![0-9]+]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] -// NO-SANITIZE-WITH-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11:![0-9]+]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 0 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test13( -// SANITIZE-WITHOUT-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA11:![0-9]+]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 1 -// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], [[INDEX]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP2]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB8:[0-9]+]], i64 [[INDEX]]) #[[ATTR9]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: cont5: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] -// SANITIZE-WITHOUT-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14:![0-9]+]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 0 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test13( -// NO-SANITIZE-WITHOUT-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA8:![0-9]+]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11:![0-9]+]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 0 -// -int test13(long index) { - test13_f.domain->revmap[index] = 0; - return 0; -} - -struct test14_foo { - int x, y; - int blah[] __attribute__((counted_by(x))); -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test14( -// SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB24:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: trap: -// SANITIZE-WITH-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR12]] -// SANITIZE-WITH-ATTR-NEXT: unreachable -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test14( -// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTCOMPOUNDLITERAL:%.*]] = alloca [[STRUCT_TEST14_FOO:%.*]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 1, ptr [[DOTCOMPOUNDLITERAL]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 2, ptr [[Y]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test14( -// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 -// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB9:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR9]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: trap: -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test14( -// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR3]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOMPOUNDLITERAL:%.*]] = alloca [[STRUCT_TEST14_FOO:%.*]], align 4 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 1, ptr [[DOTCOMPOUNDLITERAL]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 1 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 2, ptr [[Y]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] -// -int test14(int idx) { - return (struct test14_foo){ 1, 2 }.blah[idx]; -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test15( -// SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB25:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: trap: -// SANITIZE-WITH-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR12]] -// SANITIZE-WITH-ATTR-NEXT: unreachable -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test15( -// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR7]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[FOO:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR16]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 1, ptr [[FOO]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[FOO]], i64 4 -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 2, ptr [[TMP0]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[FOO]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR16]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test15( -// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 -// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB10:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR9]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: trap: -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test15( -// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[FOO:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 4 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 1, ptr [[FOO]], align 4 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[FOO]], i64 4 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 2, ptr [[TMP0]], align 4 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[FOO]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] -// -int test15(int idx) { - struct { - int x, y; - int blah[] __attribute__((counted_by(x))); - } foo = { 1, 2 }; - - return foo.blah[idx]; -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test19( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test19( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test19( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test19( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test19(struct annotated *p) { - // Avoid pointer arithmetic. It could lead to security issues. - return __builtin_dynamic_object_size(&(p + 42)->array[2], 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test20( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test20( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test20( -// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test20( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test20(struct annotated *p) { - // Avoid side-effects. - return __builtin_dynamic_object_size(&(++p)->array[2], 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test21( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test21( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test21( -// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test21( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test21(struct annotated *p) { - // Avoid side-effects. - return __builtin_dynamic_object_size(&(p++)->array[2], 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test22( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test22( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test22( -// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test22( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test22(struct annotated *p) { - // Avoid side-effects. - return __builtin_dynamic_object_size(&(--p)->array[2], 1); -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test23( -// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR6]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test23( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test23( -// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test23( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR3]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 -// -size_t test23(struct annotated *p) { - // Avoid side-effects. - return __builtin_dynamic_object_size(&(p--)->array[2], 1); -} - -struct tests_foo { - int count; - int arr[] __counted_by(count); -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test24( -// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 10 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[DOTCOUNTED_BY_LOAD]], 10 -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT4:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB26:[0-9]+]], i64 10) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont4: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO]], ptr [[VAR]], i64 21 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test24( -// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test24( -// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test24( -// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR8:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] -// -int test24(int c, struct tests_foo *var) { - // Invalid: there can't be an array of flexible arrays. - return var[10].arr[10]; -} - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test25( -// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[TMP0]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[DOTCOUNTED_BY_LOAD]], 10 -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB27:[0-9]+]], i64 10) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont5: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP2]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test25( -// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR13:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test25( -// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test25( -// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR9:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] -// -int test25(int c, struct tests_foo **var) { - // Double dereferenced variable. - return (**var).arr[10]; -} - -// Outer struct -struct test26_foo { - int a; - struct tests_foo s; -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test26( -// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[FOO:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[S:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[S]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB28:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont5: -// SANITIZE-WITH-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO]], ptr [[FOO]], i64 1 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP2]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test26( -// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[FOO:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test26( -// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[FOO:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test26( -// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[FOO:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] -// -int test26(int c, struct test26_foo *foo) { - // Invalid: A structure with a flexible array must be a pointer. - return foo->s.arr[c]; -} - -struct test27_baz; - -struct test27_bar { - unsigned char type; - unsigned char flags; - unsigned short use_cnt; - unsigned char hw_priv; -}; - -struct test27_foo { - struct test27_baz *a; - - unsigned char bit1 : 1; - unsigned char bit2 : 1; - unsigned char bit3 : 1; - - unsigned int n_tables; - unsigned long missed; - struct test27_bar *entries[] __counted_by(n_tables); -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local ptr @test27( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 2 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB30:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM4:%.*]] = sext i32 [[J]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP2]], i64 [[IDXPROM4]] -// SANITIZE-WITH-ATTR-NEXT: ret ptr [[ARRAYIDX5]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local ptr @test27( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[J]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM1]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret ptr [[ARRAYIDX2]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local ptr @test27( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM3:%.*]] = sext i32 [[J]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM3]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret ptr [[ARRAYIDX4]] -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local ptr @test27( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR8]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[J]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM1]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret ptr [[ARRAYIDX2]] -// -struct test27_bar *test27(struct test27_foo *p, int i, int j) { - return &p->entries[i][j]; -} - -struct test28_foo { - struct test28_foo *s; - int count; - int arr[] __counted_by(count); -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test28( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP4]], label [[CONT17:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB31:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont17: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP5]] -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test28( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR13]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP3]] -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test28( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP3]] -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test28( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR9]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP3]] -// -int test28(struct test28_foo *p, int i) { - return p->s->s->s->arr[i]; -} - -struct annotated_struct_array { - struct annotated *ann_array[10]; - unsigned long flags; - int count; - int array[] __counted_by(count); -}; - -// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test29( -// SANITIZE-WITH-ATTR-SAME: ptr noundef [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITH-ATTR-NEXT: entry: -// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[IDX1]], 10 -// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[IDX1]] to i64 -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB33:[0-9]+]], i64 [[TMP1]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont3: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[TMP1]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP2]], i64 0, i32 1 -// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM15:%.*]] = sext i32 [[IDX2]] to i64 -// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[IDXPROM15]], [[TMP3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP4]], label [[CONT20:%.*]], label [[HANDLER_OUT_OF_BOUNDS16:%.*]], !prof [[PROF3]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: handler.out_of_bounds16: -// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB34:[0-9]+]], i64 [[IDXPROM15]]) #[[ATTR12]], !nosanitize [[META2]] -// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] -// SANITIZE-WITH-ATTR: cont20: -// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM15]] -// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 -// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 -// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP5]] -// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA4]] -// SANITIZE-WITH-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test29( -// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR14:[0-9]+]] { -// NO-SANITIZE-WITH-ATTR-NEXT: entry: -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX1]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP0]], i64 0, i32 1 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 -// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 -// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 -// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] -// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM4:%.*]] = sext i32 [[IDX2]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[TMP0]], i64 0, i32 2, i64 [[IDXPROM4]] -// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITH-ATTR-NEXT: ret void -// -// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test29( -// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR0]] { -// SANITIZE-WITHOUT-ATTR-NEXT: entry: -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[IDX1]], 10 -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[IDX1]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[CONT21:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: -// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB12:[0-9]+]], i64 [[TMP1]]) #[[ATTR9]], !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] -// SANITIZE-WITHOUT-ATTR: cont21: -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[TMP1]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] -// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM18:%.*]] = sext i32 [[IDX2]] to i64 -// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM18]] -// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX19]], align 4, !tbaa [[TBAA2]] -// SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test29( -// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR10:[0-9]+]] { -// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX1]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[IDXPROM]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM5:%.*]] = sext i32 [[IDX2]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[IDXPROM5]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX6]], align 4, !tbaa [[TBAA2]] -// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void -// -void test29(struct annotated_struct_array *ann, int idx1, int idx2) { - ann->ann_array[idx1]->array[idx2] = __builtin_dynamic_object_size(ann->ann_array[idx1]->array, 1); -} diff --git a/clang/test/CodeGen/bounds-checking.c b/clang/test/CodeGen/bounds-checking.c index 8100e30d0650..636d4f289e24 100644 --- a/clang/test/CodeGen/bounds-checking.c +++ b/clang/test/CodeGen/bounds-checking.c @@ -69,6 +69,7 @@ int f7(union U *u, int i) { return u->c[i]; } + char B[10]; char B2[10]; // CHECK-LABEL: @f8 @@ -81,12 +82,3 @@ void f8(int i, int k) { // NOOPTARRAY: call void @llvm.ubsantrap(i8 4) B2[k] = '\0'; } - -// See commit 9a954c6 that caused a SEGFAULT in this code. -struct S { - __builtin_va_list ap; -} *s; -// CHECK-LABEL: @f9 -struct S *f9(int i) { - return &s[i]; -} diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test index e476c15b35de..2f80c96e1d52 100644 --- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test +++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test @@ -62,7 +62,6 @@ // CHECK-NEXT: CoroOnlyDestroyWhenComplete (SubjectMatchRule_record) // CHECK-NEXT: CoroReturnType (SubjectMatchRule_record) // CHECK-NEXT: CoroWrapper (SubjectMatchRule_function) -// CHECK-NEXT: CountedBy (SubjectMatchRule_field) // CHECK-NEXT: DLLExport (SubjectMatchRule_function, SubjectMatchRule_variable, SubjectMatchRule_record, SubjectMatchRule_objc_interface) // CHECK-NEXT: DLLImport (SubjectMatchRule_function, SubjectMatchRule_variable, SubjectMatchRule_record, SubjectMatchRule_objc_interface) // CHECK-NEXT: Destructor (SubjectMatchRule_function) diff --git a/clang/test/Sema/attr-counted-by.c b/clang/test/Sema/attr-counted-by.c deleted file mode 100644 index f14da9c77fa8..000000000000 --- a/clang/test/Sema/attr-counted-by.c +++ /dev/null @@ -1,64 +0,0 @@ -// RUN: %clang_cc1 -fsyntax-only -verify %s - -#define __counted_by(f) __attribute__((counted_by(f))) - -struct bar; - -struct not_found { - int count; - struct bar *fam[] __counted_by(bork); // expected-error {{use of undeclared identifier 'bork'}} -}; - -struct no_found_count_not_in_substruct { - unsigned long flags; - unsigned char count; // expected-note {{field 'count' declared here}} - struct A { - int dummy; - int array[] __counted_by(count); // expected-error {{'counted_by' field 'count' isn't within the same struct as the flexible array}} - } a; -}; - -struct not_found_suggest { - int bork; // expected-note {{'bork' declared here}} - struct bar *fam[] __counted_by(blork); // expected-error {{use of undeclared identifier 'blork'; did you mean 'bork'?}} -}; - -int global; // expected-note {{'global' declared here}} - -struct found_outside_of_struct { - int bork; - struct bar *fam[] __counted_by(global); // expected-error {{field 'global' in 'counted_by' not inside structure}} -}; - -struct self_referrential { - int bork; - struct bar *self[] __counted_by(self); // expected-error {{'counted_by' cannot refer to the flexible array 'self'}} -}; - -struct non_int_count { - double dbl_count; // expected-note {{field 'dbl_count' declared here}} - struct bar *fam[] __counted_by(dbl_count); // expected-error {{field 'dbl_count' in 'counted_by' must be a non-boolean integer type}} -}; - -struct array_of_ints_count { - int integers[2]; // expected-note {{field 'integers' declared here}} - struct bar *fam[] __counted_by(integers); // expected-error {{field 'integers' in 'counted_by' must be a non-boolean integer type}} -}; - -struct not_a_fam { - int count; - struct bar *non_fam __counted_by(count); // expected-error {{'counted_by' only applies to C99 flexible array members}} -}; - -struct not_a_c99_fam { - int count; - struct bar *non_c99_fam[0] __counted_by(count); // expected-error {{'counted_by' only applies to C99 flexible array members}} -}; - -struct annotated_with_anon_struct { - unsigned long flags; - struct { - unsigned char count; // expected-note {{'count' declared here}} - int array[] __counted_by(crount); // expected-error {{use of undeclared identifier 'crount'; did you mean 'count'?}} - }; -}; -- GitLab From 6d19e89d240dfd91af748ef5126d33077f3411c1 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Thu, 11 Jan 2024 10:35:07 +0800 Subject: [PATCH 402/652] [Pass] Remove trailing whitespace in `PassRegistry.def` NFC (#77710) --- llvm/lib/Passes/PassRegistry.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index fbaca001d1fe..0b53b59787dd 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -423,7 +423,7 @@ FUNCTION_PASS("structurizecfg", StructurizeCFGPass()) FUNCTION_PASS("tailcallelim", TailCallElimPass()) FUNCTION_PASS("tlshoist", TLSVariableHoistPass()) FUNCTION_PASS("transform-warning", WarnMissedTransformationsPass()) -FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass()) +FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass()) FUNCTION_PASS("tsan", ThreadSanitizerPass()) FUNCTION_PASS("typepromotion", TypePromotionPass(TM)) FUNCTION_PASS("unify-loop-exits", UnifyLoopExitsPass()) -- GitLab From e0c734561d5b268f8d24e68c535df8aa41369690 Mon Sep 17 00:00:00 2001 From: "S. B. Tam" Date: Thu, 11 Jan 2024 10:55:52 +0800 Subject: [PATCH 403/652] [libc++][test] Replace uses of `_LIBCPP_ABI_MICROSOFT` in tests (#77233) --- .../memory/trivial_abi/unique_ptr_destruction_order.pass.cpp | 4 +++- .../support.exception/propagation/make_exception_ptr.pass.cpp | 2 +- .../support.exception/propagation/rethrow_exception.pass.cpp | 2 +- libcxx/test/support/msvc_stdlib_force_include.h | 1 + libcxx/test/support/test_macros.h | 4 ++++ 5 files changed, 10 insertions(+), 3 deletions(-) diff --git a/libcxx/test/libcxx/memory/trivial_abi/unique_ptr_destruction_order.pass.cpp b/libcxx/test/libcxx/memory/trivial_abi/unique_ptr_destruction_order.pass.cpp index f8025f8ef57c..8752ba5a01d6 100644 --- a/libcxx/test/libcxx/memory/trivial_abi/unique_ptr_destruction_order.pass.cpp +++ b/libcxx/test/libcxx/memory/trivial_abi/unique_ptr_destruction_order.pass.cpp @@ -17,6 +17,8 @@ #include #include +#include "test_macros.h" + __attribute__((noinline)) void call_something() { asm volatile(""); } struct Base { @@ -55,7 +57,7 @@ int main(int, char**) { func(A(shared_buf, &cur_idx), std::unique_ptr(new B(shared_buf, &cur_idx)), C(shared_buf, &cur_idx)); -#if defined(_LIBCPP_ABI_MICROSOFT) +#if defined(TEST_ABI_MICROSOFT) // On Microsoft ABI, the dtor order is always A,B,C (because callee-destroyed) assert(shared_buf[0] == 'A' && shared_buf[1] == 'B' && shared_buf[2] == 'C'); #else diff --git a/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp b/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp index e97b15adc50a..8290b874db64 100644 --- a/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp @@ -39,7 +39,7 @@ int main(int, char**) } catch (const A& a) { -#ifndef _LIBCPP_ABI_MICROSOFT +#ifndef TEST_ABI_MICROSOFT assert(A::constructed == 1); #else // On Windows exception_ptr copies the exception diff --git a/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp b/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp index d109f98fbc21..57e1e8e90caa 100644 --- a/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp @@ -47,7 +47,7 @@ int main(int, char**) } catch (const A& a) { -#ifndef _LIBCPP_ABI_MICROSOFT +#ifndef TEST_ABI_MICROSOFT assert(A::constructed == 1); #else // On Windows the exception_ptr copies the exception diff --git a/libcxx/test/support/msvc_stdlib_force_include.h b/libcxx/test/support/msvc_stdlib_force_include.h index c027dc5c851e..6c26085e72c4 100644 --- a/libcxx/test/support/msvc_stdlib_force_include.h +++ b/libcxx/test/support/msvc_stdlib_force_include.h @@ -101,6 +101,7 @@ const AssertionDialogAvoider assertion_dialog_avoider{}; #endif #define TEST_SHORT_WCHAR +#define TEST_ABI_MICROSOFT #define _LIBCPP_AVAILABILITY_THROW_BAD_ANY_CAST diff --git a/libcxx/test/support/test_macros.h b/libcxx/test/support/test_macros.h index 5ca4d611e1e4..fe68e13de6bc 100644 --- a/libcxx/test/support/test_macros.h +++ b/libcxx/test/support/test_macros.h @@ -451,6 +451,10 @@ inline Tp const& DoNotOptimize(Tp const& value) { # define TEST_SHORT_WCHAR #endif +#ifdef _LIBCPP_ABI_MICROSOFT +# define TEST_ABI_MICROSOFT +#endif + // This is a temporary workaround for user-defined `operator new` definitions // not being picked up on Apple platforms in some circumstances. This is under // investigation and should be short-lived. -- GitLab From 5a66c8ddc393dabbeba6c488bb802ebd9d43dd7f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 11 Jan 2024 11:03:58 +0800 Subject: [PATCH 404/652] [Clang][doc] Add blank line before lists (#77573) The doc is not correctly rendered with missing blank lines. --- clang/docs/LanguageExtensions.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 23a7f4f5d5b9..c1420079f751 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -829,6 +829,7 @@ to ``float``; see below for more information on this emulation. see below. * ``_Float16`` is supported on the following targets: + * 32-bit ARM (natively on some architecture versions) * 64-bit ARM (AArch64) (natively on ARMv8.2a and above) * AMDGPU (natively) @@ -837,6 +838,7 @@ to ``float``; see below for more information on this emulation. * RISC-V (natively if Zfh or Zhinx is available) * ``__bf16`` is supported on the following targets (currently never natively): + * 32-bit ARM * 64-bit ARM (AArch64) * RISC-V -- GitLab From 4eb68f53db608465cf557dbdfe85d9b4eb608fff Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 10 Jan 2024 19:05:25 -0800 Subject: [PATCH 405/652] [Instrumentation] Use a range-based for loop (NFC) --- llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp index 44167f4b471c..c20fc942eaf0 100644 --- a/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp +++ b/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp @@ -617,9 +617,7 @@ void FuncPGOInstrumentation::computeCFGHash() { std::vector Indexes; JamCRC JC; for (auto &BB : F) { - const Instruction *TI = BB.getTerminator(); - for (unsigned I = 0, E = TI->getNumSuccessors(); I != E; ++I) { - BasicBlock *Succ = TI->getSuccessor(I); + for (BasicBlock *Succ : successors(&BB)) { auto BI = findBBInfo(Succ); if (BI == nullptr) continue; -- GitLab From 1bc4cb51afb9abf6049ccfa44069cb1f0612e678 Mon Sep 17 00:00:00 2001 From: XinWang10 <108658776+XinWang10@users.noreply.github.com> Date: Thu, 11 Jan 2024 11:09:55 +0800 Subject: [PATCH 406/652] [X86][MC] Fix wrong action when encoding enqcmd/enqcmds (#77571) Mentioned in https://github.com/llvm/llvm-project/pull/77293, enqcmd/enqcmds are special for its mem operand, like movdir64b(see https://github.com/llvm/llvm-project/commit/4dd5e9c60efa9), 0x67 prefix can not only modify its address size, so it's mem base and index reg should be the same type as source reg. --- llvm/lib/Target/X86/X86InstrMisc.td | 12 +++--- llvm/test/MC/X86/index-operations.s | 58 +++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 97c625a64cfc..753cf62392a1 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1523,28 +1523,28 @@ def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$ // ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity // let SchedRW = [WriteStore], Defs = [EFLAGS] in { - def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), + def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src), "enqcmd\t{$src, $dst|$dst, $src}", [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>, T8, XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; - def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), + def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src), "enqcmd\t{$src, $dst|$dst, $src}", [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>, T8, XD, AdSize32, Requires<[HasENQCMD]>; - def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), + def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src), "enqcmd\t{$src, $dst|$dst, $src}", [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>, T8, XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>; - def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), + def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src), "enqcmds\t{$src, $dst|$dst, $src}", [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>, T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; - def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), + def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src), "enqcmds\t{$src, $dst|$dst, $src}", [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>, T8, XS, AdSize32, Requires<[HasENQCMD]>; - def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), + def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src), "enqcmds\t{$src, $dst|$dst, $src}", [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>, T8, XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>; diff --git a/llvm/test/MC/X86/index-operations.s b/llvm/test/MC/X86/index-operations.s index 899cf4656549..59498b0ced12 100644 --- a/llvm/test/MC/X86/index-operations.s +++ b/llvm/test/MC/X86/index-operations.s @@ -188,3 +188,61 @@ movdir64b 291(%esi, %eiz, 4), %ebx movdir64b 291(%rsi, %riz, 4), %rbx // 64: movdir64b 291(%rsi,%riz,4), %rbx # encoding: [0x66,0x0f,0x38,0xf8,0x9c,0xa6,0x23,0x01,0x00,0x00] + +enqcmd 291(%si), %ecx +// ERR64: error: invalid 16-bit base register +// ERR32: invalid operand +// ERR16: invalid operand + +enqcmd 291(%esi), %cx +// ERR64: error: invalid operand for instruction +// ERR32: invalid operand +// ERR16: invalid operand + +enqcmd (%rdx), %r15d +// ERR64: [[#@LINE-1]]:[[#]]: error: invalid operand + +enqcmd (%edx), %r15 +// ERR64: [[#@LINE-1]]:[[#]]: error: invalid operand + +enqcmd (%eip), %ebx +// 64: enqcmd (%eip), %ebx # encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x1d,0x00,0x00,0x00,0x00] + +enqcmd (%rip), %rbx +// 64: enqcmd (%rip), %rbx # encoding: [0xf2,0x0f,0x38,0xf8,0x1d,0x00,0x00,0x00,0x00] + +enqcmd 291(%esi, %eiz, 4), %ebx +// 64: enqcmd 291(%esi,%eiz,4), %ebx # encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x9c,0xa6,0x23,0x01,0x00,0x00] +// 32: enqcmd 291(%esi,%eiz,4), %ebx # encoding: [0xf2,0x0f,0x38,0xf8,0x9c,0xa6,0x23,0x01,0x00,0x00] + +enqcmd 291(%rsi, %riz, 4), %rbx +// 64: enqcmd 291(%rsi,%riz,4), %rbx # encoding: [0xf2,0x0f,0x38,0xf8,0x9c,0xa6,0x23,0x01,0x00,0x00] + +enqcmds 291(%si), %ecx +// ERR64: error: invalid 16-bit base register +// ERR32: invalid operand +// ERR16: invalid operand + +enqcmds 291(%esi), %cx +// ERR64: error: invalid operand for instruction +// ERR32: invalid operand +// ERR16: invalid operand + +enqcmds (%rdx), %r15d +// ERR64: [[#@LINE-1]]:[[#]]: error: invalid operand + +enqcmds (%edx), %r15 +// ERR64: [[#@LINE-1]]:[[#]]: error: invalid operand + +enqcmds (%eip), %ebx +// 64: enqcmds (%eip), %ebx # encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x1d,0x00,0x00,0x00,0x00] + +enqcmds (%rip), %rbx +// 64: enqcmds (%rip), %rbx # encoding: [0xf3,0x0f,0x38,0xf8,0x1d,0x00,0x00,0x00,0x00] + +enqcmds 291(%esi, %eiz, 4), %ebx +// 64: enqcmds 291(%esi,%eiz,4), %ebx # encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x9c,0xa6,0x23,0x01,0x00,0x00] +// 32: enqcmds 291(%esi,%eiz,4), %ebx # encoding: [0xf3,0x0f,0x38,0xf8,0x9c,0xa6,0x23,0x01,0x00,0x00] + +enqcmds 291(%rsi, %riz, 4), %rbx +// 64: enqcmds 291(%rsi,%riz,4), %rbx # encoding: [0xf3,0x0f,0x38,0xf8,0x9c,0xa6,0x23,0x01,0x00,0x00] -- GitLab From cc77e33271371e6ea29569ba06db9cfd1aac022a Mon Sep 17 00:00:00 2001 From: James Grant <42079499+jamesg-nz@users.noreply.github.com> Date: Thu, 11 Jan 2024 16:32:14 +1300 Subject: [PATCH 407/652] [clang-format] Don't apply severe penalty if no possible column formats (#76675) If there are possible column formats, but they weren't selected because they don't fit within remaining characters for the current path then applying severe penalty to induce column layout by selection of a different path seems fair. But if due to style configuration or what the input code is, there are no possible column formats, different paths aren't going to have column layouts. Seems wrong to apply the severe penalty to induce column layouts if there are none available. It just causes selection of sub-optimal paths, e.g. get bad formatting when brace initializers are used inside lambda bodies. Fixes #56350 --- clang/lib/Format/FormatToken.cpp | 4 ++-- clang/unittests/Format/FormatTest.cpp | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/clang/lib/Format/FormatToken.cpp b/clang/lib/Format/FormatToken.cpp index 7a2df8c53952..b791c5a26bbe 100644 --- a/clang/lib/Format/FormatToken.cpp +++ b/clang/lib/Format/FormatToken.cpp @@ -113,8 +113,8 @@ unsigned CommaSeparatedList::formatAfterToken(LineState &State, if (!State.NextToken || !State.NextToken->Previous) return 0; - if (Formats.size() == 1) - return 0; // Handled by formatFromToken + if (Formats.size() <= 1) + return 0; // Handled by formatFromToken (1) or avoid severe penalty (0). // Ensure that we start on the opening brace. const FormatToken *LBrace = diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 25ef5c680af8..c346f382b343 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -13875,6 +13875,21 @@ TEST_F(FormatTest, FormatsBracedListsInColumnLayout) { getLLVMStyleWithColumns(35)); verifyFormat("aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa(aaaaaaaaaaaaaaaaaaa, {},\n" " aaaaaaaaaaaaaaaaaaaaaaa);"); + + // No possible column formats, don't want the optimal paths penalized. + verifyFormat( + "waarudo::unit desk = {\n" + " .s = \"desk\", .p = p, .b = [] { return w::r{3, 10} * w::m; }};"); + verifyFormat("SomeType something1([](const Input &i) -> Output { return " + "Output{1, 2}; },\n" + " [](const Input &i) -> Output { return " + "Output{1, 2}; });"); + FormatStyle NoBinPacking = getLLVMStyle(); + NoBinPacking.BinPackParameters = false; + verifyFormat("waarudo::unit desk = {\n" + " .s = \"desk\", .p = p, .b = [] { return w::r{3, 10, 1, 1, " + "1, 1} * w::m; }};", + NoBinPacking); } TEST_F(FormatTest, PullTrivialFunctionDefinitionsIntoSingleLine) { -- GitLab From b2c0c6f3f2741415d5257e16ca8d4083abe1b487 Mon Sep 17 00:00:00 2001 From: Gedare Bloom Date: Wed, 10 Jan 2024 20:35:03 -0700 Subject: [PATCH 408/652] [clang-format]: Split alignment of declarations around assignment (#69340) Function pointers are detected as a type of declaration using FunctionTypeLParen. They are aligned based on rules for AlignConsecutiveDeclarations. When a function pointer is on the right-hand side of an assignment, the alignment of the function pointer can result in excessive whitespace padding due to the ordering of alignment, as the alignment processes a line from left-to-right and first aligns the declarations before and after the assignment operator, and then aligns the assignment operator. Injection of whitespace by alignment of declarations after the equal sign followed by alignment of the equal sign results in the excessive whitespace. Fixes #68079. --- clang/docs/ClangFormatStyleOptions.rst | 68 +++++++++++++++++++ clang/docs/ReleaseNotes.rst | 1 + clang/include/clang/Format/Format.h | 20 +++++- clang/lib/Format/Format.cpp | 30 ++++----- clang/lib/Format/WhitespaceManager.cpp | 9 ++- clang/unittests/Format/ConfigParseTest.cpp | 66 +++++++++--------- clang/unittests/Format/FormatTest.cpp | 78 +++++++++++++++++++++- 7 files changed, 223 insertions(+), 49 deletions(-) diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index 3d42571e82d8..ac9a0b70ed5d 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -392,6 +392,23 @@ the configuration (without a prefix: ``Auto``). a &= 2; bbb = 2; + * ``bool AlignFunctionPointers`` Only for ``AlignConsecutiveDeclarations``. Whether function pointers are + aligned. + + .. code-block:: c++ + + true: + unsigned i; + int &r; + int *p; + int (*f)(); + + false: + unsigned i; + int &r; + int *p; + int (*f)(); + * ``bool PadOperators`` Only for ``AlignConsecutiveAssignments``. Whether short assignment operators are left-padded to the same length as long ones in order to put all assignment operators to the right of the left hand side. @@ -517,6 +534,23 @@ the configuration (without a prefix: ``Auto``). a &= 2; bbb = 2; + * ``bool AlignFunctionPointers`` Only for ``AlignConsecutiveDeclarations``. Whether function pointers are + aligned. + + .. code-block:: c++ + + true: + unsigned i; + int &r; + int *p; + int (*f)(); + + false: + unsigned i; + int &r; + int *p; + int (*f)(); + * ``bool PadOperators`` Only for ``AlignConsecutiveAssignments``. Whether short assignment operators are left-padded to the same length as long ones in order to put all assignment operators to the right of the left hand side. @@ -642,6 +676,23 @@ the configuration (without a prefix: ``Auto``). a &= 2; bbb = 2; + * ``bool AlignFunctionPointers`` Only for ``AlignConsecutiveDeclarations``. Whether function pointers are + aligned. + + .. code-block:: c++ + + true: + unsigned i; + int &r; + int *p; + int (*f)(); + + false: + unsigned i; + int &r; + int *p; + int (*f)(); + * ``bool PadOperators`` Only for ``AlignConsecutiveAssignments``. Whether short assignment operators are left-padded to the same length as long ones in order to put all assignment operators to the right of the left hand side. @@ -768,6 +819,23 @@ the configuration (without a prefix: ``Auto``). a &= 2; bbb = 2; + * ``bool AlignFunctionPointers`` Only for ``AlignConsecutiveDeclarations``. Whether function pointers are + aligned. + + .. code-block:: c++ + + true: + unsigned i; + int &r; + int *p; + int (*f)(); + + false: + unsigned i; + int &r; + int *p; + int (*f)(); + * ``bool PadOperators`` Only for ``AlignConsecutiveAssignments``. Whether short assignment operators are left-padded to the same length as long ones in order to put all assignment operators to the right of the left hand side. diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index ade0036ba2fd..7abc65b8734a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1094,6 +1094,7 @@ clang-format - Add ``ObjCPropertyAttributeOrder`` which can be used to sort ObjC property attributes (like ``nonatomic, strong, nullable``). - Add ``.clang-format-ignore`` files. +- Add ``AlignFunctionPointers`` sub-option for ``AlignConsecutiveDeclarations``. libclang -------- diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 8604dea689f9..59b645ecab71 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -225,6 +225,22 @@ struct FormatStyle { /// bbb = 2; /// \endcode bool AlignCompound; + /// Only for ``AlignConsecutiveDeclarations``. Whether function pointers are + /// aligned. + /// \code + /// true: + /// unsigned i; + /// int &r; + /// int *p; + /// int (*f)(); + /// + /// false: + /// unsigned i; + /// int &r; + /// int *p; + /// int (*f)(); + /// \endcode + bool AlignFunctionPointers; /// Only for ``AlignConsecutiveAssignments``. Whether short assignment /// operators are left-padded to the same length as long ones in order to /// put all assignment operators to the right of the left hand side. @@ -247,7 +263,9 @@ struct FormatStyle { bool operator==(const AlignConsecutiveStyle &R) const { return Enabled == R.Enabled && AcrossEmptyLines == R.AcrossEmptyLines && AcrossComments == R.AcrossComments && - AlignCompound == R.AlignCompound && PadOperators == R.PadOperators; + AlignCompound == R.AlignCompound && + AlignFunctionPointers == R.AlignFunctionPointers && + PadOperators == R.PadOperators; } bool operator!=(const AlignConsecutiveStyle &R) const { return !(*this == R); diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index f798d555bf99..ff5ed6c306f3 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -76,41 +76,39 @@ template <> struct MappingTraits { FormatStyle::AlignConsecutiveStyle( {/*Enabled=*/false, /*AcrossEmptyLines=*/false, /*AcrossComments=*/false, /*AlignCompound=*/false, - /*PadOperators=*/true})); + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); IO.enumCase(Value, "Consecutive", FormatStyle::AlignConsecutiveStyle( {/*Enabled=*/true, /*AcrossEmptyLines=*/false, /*AcrossComments=*/false, /*AlignCompound=*/false, - /*PadOperators=*/true})); + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); IO.enumCase(Value, "AcrossEmptyLines", FormatStyle::AlignConsecutiveStyle( {/*Enabled=*/true, /*AcrossEmptyLines=*/true, /*AcrossComments=*/false, /*AlignCompound=*/false, - /*PadOperators=*/true})); + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); IO.enumCase(Value, "AcrossComments", - FormatStyle::AlignConsecutiveStyle({/*Enabled=*/true, - /*AcrossEmptyLines=*/false, - /*AcrossComments=*/true, - /*AlignCompound=*/false, - /*PadOperators=*/true})); + FormatStyle::AlignConsecutiveStyle( + {/*Enabled=*/true, /*AcrossEmptyLines=*/false, + /*AcrossComments=*/true, /*AlignCompound=*/false, + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); IO.enumCase(Value, "AcrossEmptyLinesAndComments", - FormatStyle::AlignConsecutiveStyle({/*Enabled=*/true, - /*AcrossEmptyLines=*/true, - /*AcrossComments=*/true, - /*AlignCompound=*/false, - /*PadOperators=*/true})); + FormatStyle::AlignConsecutiveStyle( + {/*Enabled=*/true, /*AcrossEmptyLines=*/true, + /*AcrossComments=*/true, /*AlignCompound=*/false, + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); // For backward compatibility. IO.enumCase(Value, "true", FormatStyle::AlignConsecutiveStyle( {/*Enabled=*/true, /*AcrossEmptyLines=*/false, /*AcrossComments=*/false, /*AlignCompound=*/false, - /*PadOperators=*/true})); + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); IO.enumCase(Value, "false", FormatStyle::AlignConsecutiveStyle( {/*Enabled=*/false, /*AcrossEmptyLines=*/false, /*AcrossComments=*/false, /*AlignCompound=*/false, - /*PadOperators=*/true})); + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); } static void mapping(IO &IO, FormatStyle::AlignConsecutiveStyle &Value) { @@ -118,6 +116,7 @@ template <> struct MappingTraits { IO.mapOptional("AcrossEmptyLines", Value.AcrossEmptyLines); IO.mapOptional("AcrossComments", Value.AcrossComments); IO.mapOptional("AlignCompound", Value.AlignCompound); + IO.mapOptional("AlignFunctionPointers", Value.AlignFunctionPointers); IO.mapOptional("PadOperators", Value.PadOperators); } }; @@ -1432,6 +1431,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { LLVMStyle.AlignConsecutiveAssignments.AcrossEmptyLines = false; LLVMStyle.AlignConsecutiveAssignments.AcrossComments = false; LLVMStyle.AlignConsecutiveAssignments.AlignCompound = false; + LLVMStyle.AlignConsecutiveAssignments.AlignFunctionPointers = false; LLVMStyle.AlignConsecutiveAssignments.PadOperators = true; LLVMStyle.AlignConsecutiveBitFields = {}; LLVMStyle.AlignConsecutiveDeclarations = {}; diff --git a/clang/lib/Format/WhitespaceManager.cpp b/clang/lib/Format/WhitespaceManager.cpp index 3bc6915b8df0..f1d176f182ff 100644 --- a/clang/lib/Format/WhitespaceManager.cpp +++ b/clang/lib/Format/WhitespaceManager.cpp @@ -978,7 +978,14 @@ void WhitespaceManager::alignConsecutiveDeclarations() { AlignTokens( Style, - [](Change const &C) { + [&](Change const &C) { + if (Style.AlignConsecutiveDeclarations.AlignFunctionPointers) { + for (const auto *Prev = C.Tok->Previous; Prev; Prev = Prev->Previous) + if (Prev->is(tok::equal)) + return false; + if (C.Tok->is(TT_FunctionTypeLParen)) + return true; + } if (C.Tok->is(TT_FunctionDeclarationName)) return true; if (C.Tok->isNot(TT_StartOfName)) diff --git a/clang/unittests/Format/ConfigParseTest.cpp b/clang/unittests/Format/ConfigParseTest.cpp index 0c9f68f303d8..18ecba270e34 100644 --- a/clang/unittests/Format/ConfigParseTest.cpp +++ b/clang/unittests/Format/ConfigParseTest.cpp @@ -289,37 +289,43 @@ TEST(ConfigParseTest, ParsesConfiguration) { #define CHECK_ALIGN_CONSECUTIVE(FIELD) \ do { \ Style.FIELD.Enabled = true; \ - CHECK_PARSE(#FIELD ": None", FIELD, \ - FormatStyle::AlignConsecutiveStyle( \ - {/*Enabled=*/false, /*AcrossEmptyLines=*/false, \ - /*AcrossComments=*/false, /*AlignCompound=*/false, \ - /*PadOperators=*/true})); \ - CHECK_PARSE(#FIELD ": Consecutive", FIELD, \ - FormatStyle::AlignConsecutiveStyle( \ - {/*Enabled=*/true, /*AcrossEmptyLines=*/false, \ - /*AcrossComments=*/false, /*AlignCompound=*/false, \ - /*PadOperators=*/true})); \ - CHECK_PARSE(#FIELD ": AcrossEmptyLines", FIELD, \ - FormatStyle::AlignConsecutiveStyle( \ - {/*Enabled=*/true, /*AcrossEmptyLines=*/true, \ - /*AcrossComments=*/false, /*AlignCompound=*/false, \ - /*PadOperators=*/true})); \ - CHECK_PARSE(#FIELD ": AcrossEmptyLinesAndComments", FIELD, \ - FormatStyle::AlignConsecutiveStyle( \ - {/*Enabled=*/true, /*AcrossEmptyLines=*/true, \ - /*AcrossComments=*/true, /*AlignCompound=*/false, \ - /*PadOperators=*/true})); \ + CHECK_PARSE( \ + #FIELD ": None", FIELD, \ + FormatStyle::AlignConsecutiveStyle( \ + {/*Enabled=*/false, /*AcrossEmptyLines=*/false, \ + /*AcrossComments=*/false, /*AlignCompound=*/false, \ + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); \ + CHECK_PARSE( \ + #FIELD ": Consecutive", FIELD, \ + FormatStyle::AlignConsecutiveStyle( \ + {/*Enabled=*/true, /*AcrossEmptyLines=*/false, \ + /*AcrossComments=*/false, /*AlignCompound=*/false, \ + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); \ + CHECK_PARSE( \ + #FIELD ": AcrossEmptyLines", FIELD, \ + FormatStyle::AlignConsecutiveStyle( \ + {/*Enabled=*/true, /*AcrossEmptyLines=*/true, \ + /*AcrossComments=*/false, /*AlignCompound=*/false, \ + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); \ + CHECK_PARSE( \ + #FIELD ": AcrossEmptyLinesAndComments", FIELD, \ + FormatStyle::AlignConsecutiveStyle( \ + {/*Enabled=*/true, /*AcrossEmptyLines=*/true, \ + /*AcrossComments=*/true, /*AlignCompound=*/false, \ + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); \ /* For backwards compability, false / true should still parse */ \ - CHECK_PARSE(#FIELD ": false", FIELD, \ - FormatStyle::AlignConsecutiveStyle( \ - {/*Enabled=*/false, /*AcrossEmptyLines=*/false, \ - /*AcrossComments=*/false, /*AlignCompound=*/false, \ - /*PadOperators=*/true})); \ - CHECK_PARSE(#FIELD ": true", FIELD, \ - FormatStyle::AlignConsecutiveStyle( \ - {/*Enabled=*/true, /*AcrossEmptyLines=*/false, \ - /*AcrossComments=*/false, /*AlignCompound=*/false, \ - /*PadOperators=*/true})); \ + CHECK_PARSE( \ + #FIELD ": false", FIELD, \ + FormatStyle::AlignConsecutiveStyle( \ + {/*Enabled=*/false, /*AcrossEmptyLines=*/false, \ + /*AcrossComments=*/false, /*AlignCompound=*/false, \ + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); \ + CHECK_PARSE( \ + #FIELD ": true", FIELD, \ + FormatStyle::AlignConsecutiveStyle( \ + {/*Enabled=*/true, /*AcrossEmptyLines=*/false, \ + /*AcrossComments=*/false, /*AlignCompound=*/false, \ + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); \ \ CHECK_PARSE_NESTED_BOOL(FIELD, Enabled); \ CHECK_PARSE_NESTED_BOOL(FIELD, AcrossEmptyLines); \ diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index c346f382b343..9fd55db44df6 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -2046,13 +2046,26 @@ TEST_F(FormatTest, SeparatePointerReferenceAlignment) { Style); Style.AlignConsecutiveDeclarations.Enabled = true; + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = true; verifyFormat("Const unsigned int *c;\n" "const unsigned int *d;\n" "Const unsigned int &e;\n" "const unsigned int &f;\n" + "int *f1(int *a, int &b, int &&c);\n" + "double *(*f2)(int *a, double &&b);\n" "const unsigned &&g;\n" "Const unsigned h;", Style); + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = false; + verifyFormat("Const unsigned int *c;\n" + "const unsigned int *d;\n" + "Const unsigned int &e;\n" + "const unsigned int &f;\n" + "int *f1(int *a, int &b, int &&c);\n" + "double *(*f2)(int *a, double &&b);\n" + "const unsigned &&g;\n" + "Const unsigned h;", + Style); Style.PointerAlignment = FormatStyle::PAS_Left; Style.ReferenceAlignment = FormatStyle::RAS_Pointer; @@ -2091,13 +2104,26 @@ TEST_F(FormatTest, SeparatePointerReferenceAlignment) { Style); Style.AlignConsecutiveDeclarations.Enabled = true; + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = true; verifyFormat("Const unsigned int* c;\n" "const unsigned int* d;\n" "Const unsigned int& e;\n" "const unsigned int& f;\n" + "int* f1(int* a, int& b, int&& c);\n" + "double* (*f2)(int* a, double&& b);\n" "const unsigned&& g;\n" "Const unsigned h;", Style); + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = false; + verifyFormat("Const unsigned int* c;\n" + "const unsigned int* d;\n" + "Const unsigned int& e;\n" + "const unsigned int& f;\n" + "int* f1(int* a, int& b, int&& c);\n" + "double* (*f2)(int* a, double&& b);\n" + "const unsigned&& g;\n" + "Const unsigned h;", + Style); Style.PointerAlignment = FormatStyle::PAS_Right; Style.ReferenceAlignment = FormatStyle::RAS_Left; @@ -2116,13 +2142,26 @@ TEST_F(FormatTest, SeparatePointerReferenceAlignment) { verifyFormat("for (int a = 0, b++; const Foo *c : {1, 2, 3})", Style); Style.AlignConsecutiveDeclarations.Enabled = true; + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = true; verifyFormat("Const unsigned int *c;\n" "const unsigned int *d;\n" "Const unsigned int& e;\n" "const unsigned int& f;\n" - "const unsigned g;\n" + "int *f1(int *a, int& b, int&& c);\n" + "double *(*f2)(int *a, double&& b);\n" + "const unsigned&& g;\n" "Const unsigned h;", Style); + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = false; + verifyFormat("Const unsigned int *c;\n" + "const unsigned int *d;\n" + "Const unsigned int& e;\n" + "const unsigned int& f;\n" + "int *f1(int *a, int& b, int&& c);\n" + "double *(*f2)(int *a, double&& b);\n" + "const unsigned&& g;\n" + "Const unsigned h;", + Style); Style.PointerAlignment = FormatStyle::PAS_Left; Style.ReferenceAlignment = FormatStyle::RAS_Middle; @@ -2156,13 +2195,26 @@ TEST_F(FormatTest, SeparatePointerReferenceAlignment) { Style); Style.AlignConsecutiveDeclarations.Enabled = true; + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = true; verifyFormat("Const unsigned int* c;\n" "const unsigned int* d;\n" "Const unsigned int & e;\n" "const unsigned int & f;\n" + "int* f1(int* a, int & b, int && c);\n" + "double* (*f2)(int* a, double && b);\n" "const unsigned && g;\n" "Const unsigned h;", Style); + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = false; + verifyFormat("Const unsigned int* c;\n" + "const unsigned int* d;\n" + "Const unsigned int & e;\n" + "const unsigned int & f;\n" + "int* f1(int* a, int & b, int && c);\n" + "double* (*f2)(int* a, double && b);\n" + "const unsigned && g;\n" + "Const unsigned h;", + Style); Style.PointerAlignment = FormatStyle::PAS_Middle; Style.ReferenceAlignment = FormatStyle::RAS_Right; @@ -2181,13 +2233,26 @@ TEST_F(FormatTest, SeparatePointerReferenceAlignment) { verifyFormat("for (int a = 0, b++; const Foo * c : {1, 2, 3})", Style); Style.AlignConsecutiveDeclarations.Enabled = true; + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = true; verifyFormat("Const unsigned int * c;\n" "const unsigned int * d;\n" "Const unsigned int &e;\n" "const unsigned int &f;\n" + "int * f1(int * a, int &b, int &&c);\n" + "double * (*f2)(int * a, double &&b);\n" "const unsigned &&g;\n" "Const unsigned h;", Style); + Style.AlignConsecutiveDeclarations.AlignFunctionPointers = false; + verifyFormat("Const unsigned int * c;\n" + "const unsigned int * d;\n" + "Const unsigned int &e;\n" + "const unsigned int &f;\n" + "int * f1(int * a, int &b, int &&c);\n" + "double * (*f2)(int * a, double &&b);\n" + "const unsigned &&g;\n" + "Const unsigned h;", + Style); // FIXME: we don't handle this yet, so output may be arbitrary until it's // specifically handled @@ -18933,6 +18998,15 @@ TEST_F(FormatTest, AlignConsecutiveDeclarations) { " \"bb\"};\n" "int bbbbbbb = 0;", Alignment); + // http://llvm.org/PR68079 + verifyFormat("using Fn = int (A::*)();\n" + "using RFn = int (A::*)() &;\n" + "using RRFn = int (A::*)() &&;", + Alignment); + verifyFormat("using Fn = int (A::*)();\n" + "using RFn = int *(A::*)() &;\n" + "using RRFn = double (A::*)() &&;", + Alignment); // PAS_Right verifyFormat("void SomeFunction(int parameter = 0) {\n" @@ -19585,7 +19659,7 @@ TEST_F(FormatTest, AlignWithLineBreaks) { FormatStyle::AlignConsecutiveStyle( {/*Enabled=*/false, /*AcrossEmptyLines=*/false, /*AcrossComments=*/false, /*AlignCompound=*/false, - /*PadOperators=*/true})); + /*AlignFunctionPointers=*/false, /*PadOperators=*/true})); EXPECT_EQ(Style.AlignConsecutiveDeclarations, FormatStyle::AlignConsecutiveStyle({})); verifyFormat("void foo() {\n" -- GitLab From 093e6bdd4bec8ce9b3baf1e8e0a07aa6549dd5d4 Mon Sep 17 00:00:00 2001 From: XDeme <66138117+XDeme@users.noreply.github.com> Date: Thu, 11 Jan 2024 00:46:11 -0300 Subject: [PATCH 409/652] [clang-format] Fix crash involving array designators (#77045) Fixes llvm/llvm-project#76716 Fixes parsing of `[0]{}`. Before this patch it was begin parsed as a lambda, now it is correctly parsed as a designator initializer. --- clang/lib/Format/UnwrappedLineParser.cpp | 2 +- clang/lib/Format/WhitespaceManager.h | 1 + clang/unittests/Format/FormatTest.cpp | 12 ++++++++++++ clang/unittests/Format/TokenAnnotatorTest.cpp | 5 +++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 684609747a55..d4aa3735c2a5 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -2308,7 +2308,7 @@ bool UnwrappedLineParser::tryToParseLambdaIntroducer() { LeftSquare->isCppStructuredBinding(Style)) { return false; } - if (FormatTok->is(tok::l_square)) + if (FormatTok->is(tok::l_square) || tok::isLiteral(FormatTok->Tok.getKind())) return false; if (FormatTok->is(tok::r_square)) { const FormatToken *Next = Tokens->peekNextToken(/*SkipComment=*/true); diff --git a/clang/lib/Format/WhitespaceManager.h b/clang/lib/Format/WhitespaceManager.h index 24fe492dcb02..dc6f60e5deee 100644 --- a/clang/lib/Format/WhitespaceManager.h +++ b/clang/lib/Format/WhitespaceManager.h @@ -282,6 +282,7 @@ private: for (auto PrevIter = Start; PrevIter != End; ++PrevIter) { // If we broke the line the initial spaces are already // accounted for. + assert(PrevIter->Index < Changes.size()); if (Changes[PrevIter->Index].NewlinesBefore > 0) NetWidth = 0; NetWidth += diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 9fd55db44df6..8f115fb8cbf0 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -20931,6 +20931,12 @@ TEST_F(FormatTest, CatchAlignArrayOfStructuresRightAlignment) { "};", Style); + verifyNoCrash("Foo foo[] = {\n" + " [0] = {1, 1},\n" + " [1] { 1, 1, },\n" + " [2] { 1, 1, },\n" + "};"); + verifyFormat("return GradForUnaryCwise(g, {\n" " {{\"sign\"}, \"Sign\", " " {\"x\", \"dy\"}},\n" @@ -21173,6 +21179,12 @@ TEST_F(FormatTest, CatchAlignArrayOfStructuresLeftAlignment) { "};", Style); + verifyNoCrash("Foo foo[] = {\n" + " [0] = {1, 1},\n" + " [1] { 1, 1, },\n" + " [2] { 1, 1, },\n" + "};"); + verifyFormat("return GradForUnaryCwise(g, {\n" " {{\"sign\"}, \"Sign\", {\"x\", " "\"dy\"} },\n" diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index decc0785c5cd..494205a1f2d8 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -2324,6 +2324,11 @@ TEST_F(TokenAnnotatorTest, UnderstandDesignatedInitializers) { EXPECT_BRACE_KIND(Tokens[1], BK_BracedInit); EXPECT_TOKEN(Tokens[6], tok::period, TT_DesignatedInitializerPeriod); EXPECT_TOKEN(Tokens[13], tok::period, TT_DesignatedInitializerPeriod); + + Tokens = annotate("Foo foo[] = {[0]{}};"); + ASSERT_EQ(Tokens.size(), 14u) << Tokens; + EXPECT_TOKEN(Tokens[6], tok::l_square, TT_DesignatedInitializerLSquare); + EXPECT_BRACE_KIND(Tokens[9], BK_BracedInit); } TEST_F(TokenAnnotatorTest, UnderstandsJavaScript) { -- GitLab From 9ed30012fb4f43de42ef2f265fe384d9d0b0edf2 Mon Sep 17 00:00:00 2001 From: Ivan Butygin Date: Thu, 11 Jan 2024 04:51:57 +0100 Subject: [PATCH 410/652] [mlir][arith][nfc] Fix typos (#77700) Cleanup after https://github.com/llvm/llvm-project/pull/77211 --- .../mlir/Conversion/ArithCommon/AttrToLLVMConverter.h | 6 +++--- mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td | 2 +- mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td | 2 +- mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h b/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h index 0296ec969d0b..32d7979c32df 100644 --- a/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h +++ b/mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h @@ -29,12 +29,12 @@ convertArithFastMathAttrToLLVM(arith::FastMathFlagsAttr fmfAttr); /// Maps arithmetic overflow enum values to LLVM enum values. LLVM::IntegerOverflowFlags -convertArithOveflowFlagsToLLVM(arith::IntegerOverflowFlags arithFlags); +convertArithOverflowFlagsToLLVM(arith::IntegerOverflowFlags arithFlags); /// Creates an LLVM overflow attribute from a given arithmetic overflow /// attribute. LLVM::IntegerOverflowFlagsAttr -convertArithOveflowAttrToLLVM(arith::IntegerOverflowFlagsAttr flagsAttr); +convertArithOverflowAttrToLLVM(arith::IntegerOverflowFlagsAttr flagsAttr); // Attribute converter that populates a NamedAttrList by removing the fastmath // attribute from the source operation attributes, and replacing it with an @@ -80,7 +80,7 @@ public: if (arithAttr) { StringRef targetAttrName = TargetOp::getIntegerOverflowAttrName(); convertedAttr.set(targetAttrName, - convertArithOveflowAttrToLLVM(arithAttr)); + convertArithOverflowAttrToLLVM(arithAttr)); } } diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td b/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td index e248422f84db..73a5d9c32ef2 100644 --- a/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td +++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td @@ -93,7 +93,7 @@ def ArithIntegerOverflowFlagsInterface : OpInterface<"ArithIntegerOverflowFlagsI }] >, StaticInterfaceMethod< - /*desc=*/ [{Returns the name of the IntegerOveflowFlagsAttr attribute + /*desc=*/ [{Returns the name of the IntegerOverflowFlagsAttr attribute for the operation}], /*returnType=*/ "StringRef", /*methodName=*/ "getIntegerOverflowAttrName", diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td index 81589eaf5fd0..3b2a132a881e 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td @@ -92,7 +92,7 @@ def IntegerOverflowFlagsInterface : OpInterface<"IntegerOverflowFlagsInterface"> }] >, StaticInterfaceMethod< - /*desc=*/ [{Returns the name of the IntegerOveflowFlagsAttr attribute + /*desc=*/ [{Returns the name of the IntegerOverflowFlagsAttr attribute for the operation}], /*returnType=*/ "StringRef", /*methodName=*/ "getIntegerOverflowAttrName", diff --git a/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp b/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp index 3e9aef87b9ef..dab064a3a954 100644 --- a/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp +++ b/mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp @@ -35,7 +35,7 @@ mlir::arith::convertArithFastMathAttrToLLVM(arith::FastMathFlagsAttr fmfAttr) { fmfAttr.getContext(), convertArithFastMathFlagsToLLVM(arithFMF)); } -LLVM::IntegerOverflowFlags mlir::arith::convertArithOveflowFlagsToLLVM( +LLVM::IntegerOverflowFlags mlir::arith::convertArithOverflowFlagsToLLVM( arith::IntegerOverflowFlags arithFlags) { LLVM::IntegerOverflowFlags llvmFlags{}; const std::pair @@ -49,9 +49,9 @@ LLVM::IntegerOverflowFlags mlir::arith::convertArithOveflowFlagsToLLVM( return llvmFlags; } -LLVM::IntegerOverflowFlagsAttr mlir::arith::convertArithOveflowAttrToLLVM( +LLVM::IntegerOverflowFlagsAttr mlir::arith::convertArithOverflowAttrToLLVM( arith::IntegerOverflowFlagsAttr flagsAttr) { arith::IntegerOverflowFlags arithFlags = flagsAttr.getValue(); return LLVM::IntegerOverflowFlagsAttr::get( - flagsAttr.getContext(), convertArithOveflowFlagsToLLVM(arithFlags)); + flagsAttr.getContext(), convertArithOverflowFlagsToLLVM(arithFlags)); } -- GitLab From 1fe7bdb87b0d6331b243b3834565ad9423d8f4b0 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Thu, 11 Jan 2024 12:15:17 +0800 Subject: [PATCH 411/652] [X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564) We supported encoding/decoding for these instructions in https://github.com/llvm/llvm-project/pull/76319 https://github.com/llvm/llvm-project/pull/76721 https://github.com/llvm/llvm-project/pull/76919 --- llvm/lib/Target/X86/X86InstrArithmetic.td | 110 ++-- llvm/lib/Target/X86/X86InstrCompiler.td | 380 +++++++------- llvm/test/CodeGen/X86/apx/adc.ll | 485 +++++++++++++++++ llvm/test/CodeGen/X86/apx/add.ll | 595 +++++++++++++++++++++ llvm/test/CodeGen/X86/apx/dec.ll | 137 +++++ llvm/test/CodeGen/X86/apx/imul.ll | 139 +++++ llvm/test/CodeGen/X86/apx/inc.ll | 193 +++++++ llvm/test/CodeGen/X86/apx/neg.ll | 233 +++++++++ llvm/test/CodeGen/X86/apx/not.ll | 137 +++++ llvm/test/CodeGen/X86/apx/or.ll | 593 +++++++++++++++++++++ llvm/test/CodeGen/X86/apx/sbb.ll | 433 +++++++++++++++ llvm/test/CodeGen/X86/apx/sub.ll | 609 ++++++++++++++++++++++ llvm/test/CodeGen/X86/apx/xor.ll | 545 +++++++++++++++++++ 13 files changed, 4378 insertions(+), 211 deletions(-) create mode 100644 llvm/test/CodeGen/X86/apx/adc.ll create mode 100644 llvm/test/CodeGen/X86/apx/add.ll create mode 100644 llvm/test/CodeGen/X86/apx/dec.ll create mode 100644 llvm/test/CodeGen/X86/apx/imul.ll create mode 100644 llvm/test/CodeGen/X86/apx/inc.ll create mode 100644 llvm/test/CodeGen/X86/apx/neg.ll create mode 100644 llvm/test/CodeGen/X86/apx/not.ll create mode 100644 llvm/test/CodeGen/X86/apx/or.ll create mode 100644 llvm/test/CodeGen/X86/apx/sbb.ll create mode 100644 llvm/test/CodeGen/X86/apx/sub.ll create mode 100644 llvm/test/CodeGen/X86/apx/xor.ll diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 5cfa95e085e3..76b0fe5f5cad 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1107,43 +1107,85 @@ def : Pat<(store (X86adc_flag GR64:$src, (loadi64 addr:$dst), EFLAGS), // Patterns for basic arithmetic ops with relocImm for the immediate field. multiclass ArithBinOp_RF_relocImm_Pats { - def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2), - (!cast(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>; - def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2), - (!cast(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>; - def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2), - (!cast(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>; - def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2), - (!cast(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>; - - def : Pat<(store (OpNode (load addr:$dst), relocImm8_su:$src), addr:$dst), - (!cast(NAME#"8mi") addr:$dst, relocImm8_su:$src)>; - def : Pat<(store (OpNode (load addr:$dst), relocImm16_su:$src), addr:$dst), - (!cast(NAME#"16mi") addr:$dst, relocImm16_su:$src)>; - def : Pat<(store (OpNode (load addr:$dst), relocImm32_su:$src), addr:$dst), - (!cast(NAME#"32mi") addr:$dst, relocImm32_su:$src)>; - def : Pat<(store (OpNode (load addr:$dst), i64relocImmSExt32_su:$src), addr:$dst), - (!cast(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>; + let Predicates = [NoNDD] in { + def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2), + (!cast(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>; + def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2), + (!cast(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>; + def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2), + (!cast(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>; + def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2), + (!cast(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>; + + def : Pat<(store (OpNode (load addr:$dst), relocImm8_su:$src), addr:$dst), + (!cast(NAME#"8mi") addr:$dst, relocImm8_su:$src)>; + def : Pat<(store (OpNode (load addr:$dst), relocImm16_su:$src), addr:$dst), + (!cast(NAME#"16mi") addr:$dst, relocImm16_su:$src)>; + def : Pat<(store (OpNode (load addr:$dst), relocImm32_su:$src), addr:$dst), + (!cast(NAME#"32mi") addr:$dst, relocImm32_su:$src)>; + def : Pat<(store (OpNode (load addr:$dst), i64relocImmSExt32_su:$src), addr:$dst), + (!cast(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>; + } + let Predicates = [HasNDD] in { + def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2), + (!cast(NAME#"8ri_ND") GR8:$src1, relocImm8_su:$src2)>; + def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2), + (!cast(NAME#"16ri_ND") GR16:$src1, relocImm16_su:$src2)>; + def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2), + (!cast(NAME#"32ri_ND") GR32:$src1, relocImm32_su:$src2)>; + def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2), + (!cast(NAME#"64ri32_ND") GR64:$src1, i64relocImmSExt32_su:$src2)>; + + def : Pat<(OpNode (load addr:$dst), relocImm8_su:$src), + (!cast(NAME#"8mi_ND") addr:$dst, relocImm8_su:$src)>; + def : Pat<(OpNode (load addr:$dst), relocImm16_su:$src), + (!cast(NAME#"16mi_ND") addr:$dst, relocImm16_su:$src)>; + def : Pat<(OpNode (load addr:$dst), relocImm32_su:$src), + (!cast(NAME#"32mi_ND") addr:$dst, relocImm32_su:$src)>; + def : Pat<(OpNode (load addr:$dst), i64relocImmSExt32_su:$src), + (!cast(NAME#"64mi32_ND") addr:$dst, i64relocImmSExt32_su:$src)>; + } } multiclass ArithBinOp_RFF_relocImm_Pats { - def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2, EFLAGS), - (!cast(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>; - def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2, EFLAGS), - (!cast(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>; - def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2, EFLAGS), - (!cast(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>; - def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2, EFLAGS), - (!cast(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>; - - def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm8_su:$src, EFLAGS), addr:$dst), - (!cast(NAME#"8mi") addr:$dst, relocImm8_su:$src)>; - def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm16_su:$src, EFLAGS), addr:$dst), - (!cast(NAME#"16mi") addr:$dst, relocImm16_su:$src)>; - def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm32_su:$src, EFLAGS), addr:$dst), - (!cast(NAME#"32mi") addr:$dst, relocImm32_su:$src)>; - def : Pat<(store (OpNodeFlag (load addr:$dst), i64relocImmSExt32_su:$src, EFLAGS), addr:$dst), - (!cast(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>; + let Predicates = [NoNDD] in { + def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2, EFLAGS), + (!cast(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>; + def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2, EFLAGS), + (!cast(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>; + def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2, EFLAGS), + (!cast(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>; + def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2, EFLAGS), + (!cast(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>; + + def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm8_su:$src, EFLAGS), addr:$dst), + (!cast(NAME#"8mi") addr:$dst, relocImm8_su:$src)>; + def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm16_su:$src, EFLAGS), addr:$dst), + (!cast(NAME#"16mi") addr:$dst, relocImm16_su:$src)>; + def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm32_su:$src, EFLAGS), addr:$dst), + (!cast(NAME#"32mi") addr:$dst, relocImm32_su:$src)>; + def : Pat<(store (OpNodeFlag (load addr:$dst), i64relocImmSExt32_su:$src, EFLAGS), addr:$dst), + (!cast(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>; + } + let Predicates = [HasNDD] in { + def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2, EFLAGS), + (!cast(NAME#"8ri_ND") GR8:$src1, relocImm8_su:$src2)>; + def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2, EFLAGS), + (!cast(NAME#"16ri_ND") GR16:$src1, relocImm16_su:$src2)>; + def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2, EFLAGS), + (!cast(NAME#"32ri_ND") GR32:$src1, relocImm32_su:$src2)>; + def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2, EFLAGS), + (!cast(NAME#"64ri32_ND") GR64:$src1, i64relocImmSExt32_su:$src2)>; + + def : Pat<(OpNodeFlag (load addr:$dst), relocImm8_su:$src, EFLAGS), + (!cast(NAME#"8mi_ND") addr:$dst, relocImm8_su:$src)>; + def : Pat<(OpNodeFlag (load addr:$dst), relocImm16_su:$src, EFLAGS), + (!cast(NAME#"16mi_ND") addr:$dst, relocImm16_su:$src)>; + def : Pat<(OpNodeFlag (load addr:$dst), relocImm32_su:$src, EFLAGS), + (!cast(NAME#"32mi_ND") addr:$dst, relocImm32_su:$src)>; + def : Pat<(OpNodeFlag (load addr:$dst), i64relocImmSExt32_su:$src, EFLAGS), + (!cast(NAME#"64mi32_ND") addr:$dst, i64relocImmSExt32_su:$src)>; + } } multiclass ArithBinOp_F_relocImm_Pats { diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index c77c77ee4a3e..422391a6e02a 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -1550,13 +1550,24 @@ def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. let AddedComplexity = 1 in { -def : Pat<(and GR64:$src, i64immZExt32:$imm), - (SUBREG_TO_REG - (i64 0), - (AND32ri - (EXTRACT_SUBREG GR64:$src, sub_32bit), - (i32 (GetLo32XForm imm:$imm))), - sub_32bit)>; + let Predicates = [NoNDD] in { + def : Pat<(and GR64:$src, i64immZExt32:$imm), + (SUBREG_TO_REG + (i64 0), + (AND32ri + (EXTRACT_SUBREG GR64:$src, sub_32bit), + (i32 (GetLo32XForm imm:$imm))), + sub_32bit)>; + } + let Predicates = [HasNDD] in { + def : Pat<(and GR64:$src, i64immZExt32:$imm), + (SUBREG_TO_REG + (i64 0), + (AND32ri_ND + (EXTRACT_SUBREG GR64:$src, sub_32bit), + (i32 (GetLo32XForm imm:$imm))), + sub_32bit)>; + } } // AddedComplexity = 1 @@ -1762,10 +1773,18 @@ def : Pat<(X86xor_flag (i8 (trunc GR32:$src)), // where the least significant bit is not 0. However, the probability of this // happening is considered low enough that this is officially not a // "real problem". -def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; -def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; -def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; -def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; +let Predicates = [NoNDD] in { + def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; + def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; + def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; + def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; +} +let Predicates = [HasNDD] in { + def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr_ND GR8 :$src1, GR8 :$src1)>; + def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr_ND GR16:$src1, GR16:$src1)>; + def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr_ND GR32:$src1, GR32:$src1)>; + def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr_ND GR64:$src1, GR64:$src1)>; +} // Shift amount is implicitly masked. multiclass MaskedShiftAmountPats { @@ -1937,75 +1956,179 @@ defm : one_bit_patterns; // EFLAGS-defining Patterns //===----------------------------------------------------------------------===// -// add reg, reg -def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; -def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; -def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; -def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>; - -// add reg, mem -def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), - (ADD8rm GR8:$src1, addr:$src2)>; -def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), - (ADD16rm GR16:$src1, addr:$src2)>; -def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), - (ADD32rm GR32:$src1, addr:$src2)>; -def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), - (ADD64rm GR64:$src1, addr:$src2)>; - -// add reg, imm -def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; -def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; -def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; -def : Pat<(add GR64:$src1, i64immSExt32:$src2), (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; - -// sub reg, reg -def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; -def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; -def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; -def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>; - -// sub reg, mem -def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), - (SUB8rm GR8:$src1, addr:$src2)>; -def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), - (SUB16rm GR16:$src1, addr:$src2)>; -def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), - (SUB32rm GR32:$src1, addr:$src2)>; -def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), - (SUB64rm GR64:$src1, addr:$src2)>; - -// sub reg, imm -def : Pat<(sub GR8:$src1, imm:$src2), - (SUB8ri GR8:$src1, imm:$src2)>; -def : Pat<(sub GR16:$src1, imm:$src2), - (SUB16ri GR16:$src1, imm:$src2)>; -def : Pat<(sub GR32:$src1, imm:$src2), - (SUB32ri GR32:$src1, imm:$src2)>; -def : Pat<(sub GR64:$src1, i64immSExt32:$src2), - (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; - -// sub 0, reg -def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; -def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; -def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; -def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; - -// mul reg, reg -def : Pat<(mul GR16:$src1, GR16:$src2), - (IMUL16rr GR16:$src1, GR16:$src2)>; -def : Pat<(mul GR32:$src1, GR32:$src2), - (IMUL32rr GR32:$src1, GR32:$src2)>; -def : Pat<(mul GR64:$src1, GR64:$src2), - (IMUL64rr GR64:$src1, GR64:$src2)>; - -// mul reg, mem -def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), - (IMUL16rm GR16:$src1, addr:$src2)>; -def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), - (IMUL32rm GR32:$src1, addr:$src2)>; -def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), - (IMUL64rm GR64:$src1, addr:$src2)>; +multiclass EFLAGSDefiningPats { + let Predicates = [p] in { + // add reg, reg + def : Pat<(add GR8 :$src1, GR8 :$src2), (!cast(ADD8rr#suffix) GR8 :$src1, GR8 :$src2)>; + def : Pat<(add GR16:$src1, GR16:$src2), (!cast(ADD16rr#suffix) GR16:$src1, GR16:$src2)>; + def : Pat<(add GR32:$src1, GR32:$src2), (!cast(ADD32rr#suffix) GR32:$src1, GR32:$src2)>; + def : Pat<(add GR64:$src1, GR64:$src2), (!cast(ADD64rr#suffix) GR64:$src1, GR64:$src2)>; + + // add reg, mem + def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), + (!cast(ADD8rm#suffix) GR8:$src1, addr:$src2)>; + def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), + (!cast(ADD16rm#suffix) GR16:$src1, addr:$src2)>; + def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), + (!cast(ADD32rm#suffix) GR32:$src1, addr:$src2)>; + def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), + (!cast(ADD64rm#suffix) GR64:$src1, addr:$src2)>; + + // add reg, imm + def : Pat<(add GR8 :$src1, imm:$src2), (!cast(ADD8ri#suffix) GR8:$src1 , imm:$src2)>; + def : Pat<(add GR16:$src1, imm:$src2), (!cast(ADD16ri#suffix) GR16:$src1, imm:$src2)>; + def : Pat<(add GR32:$src1, imm:$src2), (!cast(ADD32ri#suffix) GR32:$src1, imm:$src2)>; + def : Pat<(add GR64:$src1, i64immSExt32:$src2), (!cast(ADD64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; + + // sub reg, reg + def : Pat<(sub GR8 :$src1, GR8 :$src2), (!cast(SUB8rr#suffix) GR8 :$src1, GR8 :$src2)>; + def : Pat<(sub GR16:$src1, GR16:$src2), (!cast(SUB16rr#suffix) GR16:$src1, GR16:$src2)>; + def : Pat<(sub GR32:$src1, GR32:$src2), (!cast(SUB32rr#suffix) GR32:$src1, GR32:$src2)>; + def : Pat<(sub GR64:$src1, GR64:$src2), (!cast(SUB64rr#suffix) GR64:$src1, GR64:$src2)>; + + // sub reg, mem + def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), + (!cast(SUB8rm#suffix) GR8:$src1, addr:$src2)>; + def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), + (!cast(SUB16rm#suffix) GR16:$src1, addr:$src2)>; + def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), + (!cast(SUB32rm#suffix) GR32:$src1, addr:$src2)>; + def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), + (!cast(SUB64rm#suffix) GR64:$src1, addr:$src2)>; + + // sub reg, imm + def : Pat<(sub GR8:$src1, imm:$src2), + (!cast(SUB8ri#suffix) GR8:$src1, imm:$src2)>; + def : Pat<(sub GR16:$src1, imm:$src2), + (!cast(SUB16ri#suffix) GR16:$src1, imm:$src2)>; + def : Pat<(sub GR32:$src1, imm:$src2), + (!cast(SUB32ri#suffix) GR32:$src1, imm:$src2)>; + def : Pat<(sub GR64:$src1, i64immSExt32:$src2), + (!cast(SUB64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; + + // sub 0, reg + def : Pat<(X86sub_flag 0, GR8 :$src), (!cast(NEG8r#suffix) GR8 :$src)>; + def : Pat<(X86sub_flag 0, GR16:$src), (!cast(NEG16r#suffix) GR16:$src)>; + def : Pat<(X86sub_flag 0, GR32:$src), (!cast(NEG32r#suffix) GR32:$src)>; + def : Pat<(X86sub_flag 0, GR64:$src), (!cast(NEG64r#suffix) GR64:$src)>; + + // mul reg, reg + def : Pat<(mul GR16:$src1, GR16:$src2), + (!cast(IMUL16rr#suffix) GR16:$src1, GR16:$src2)>; + def : Pat<(mul GR32:$src1, GR32:$src2), + (!cast(IMUL32rr#suffix) GR32:$src1, GR32:$src2)>; + def : Pat<(mul GR64:$src1, GR64:$src2), + (!cast(IMUL64rr#suffix) GR64:$src1, GR64:$src2)>; + + // mul reg, mem + def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), + (!cast(IMUL16rm#suffix) GR16:$src1, addr:$src2)>; + def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), + (!cast(IMUL32rm#suffix) GR32:$src1, addr:$src2)>; + def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), + (!cast(IMUL64rm#suffix) GR64:$src1, addr:$src2)>; + + // or reg/reg. + def : Pat<(or GR8 :$src1, GR8 :$src2), (!cast(OR8rr#suffix) GR8 :$src1, GR8 :$src2)>; + def : Pat<(or GR16:$src1, GR16:$src2), (!cast(OR16rr#suffix) GR16:$src1, GR16:$src2)>; + def : Pat<(or GR32:$src1, GR32:$src2), (!cast(OR32rr#suffix) GR32:$src1, GR32:$src2)>; + def : Pat<(or GR64:$src1, GR64:$src2), (!cast(OR64rr#suffix) GR64:$src1, GR64:$src2)>; + + // or reg/mem + def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), + (!cast(OR8rm#suffix) GR8:$src1, addr:$src2)>; + def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), + (!cast(OR16rm#suffix) GR16:$src1, addr:$src2)>; + def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), + (!cast(OR32rm#suffix) GR32:$src1, addr:$src2)>; + def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), + (!cast(OR64rm#suffix) GR64:$src1, addr:$src2)>; + + // or reg/imm + def : Pat<(or GR8:$src1 , imm:$src2), (!cast(OR8ri#suffix) GR8 :$src1, imm:$src2)>; + def : Pat<(or GR16:$src1, imm:$src2), (!cast(OR16ri#suffix) GR16:$src1, imm:$src2)>; + def : Pat<(or GR32:$src1, imm:$src2), (!cast(OR32ri#suffix) GR32:$src1, imm:$src2)>; + def : Pat<(or GR64:$src1, i64immSExt32:$src2), + (!cast(OR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; + + // xor reg/reg + def : Pat<(xor GR8 :$src1, GR8 :$src2), (!cast(XOR8rr#suffix) GR8 :$src1, GR8 :$src2)>; + def : Pat<(xor GR16:$src1, GR16:$src2), (!cast(XOR16rr#suffix) GR16:$src1, GR16:$src2)>; + def : Pat<(xor GR32:$src1, GR32:$src2), (!cast(XOR32rr#suffix) GR32:$src1, GR32:$src2)>; + def : Pat<(xor GR64:$src1, GR64:$src2), (!cast(XOR64rr#suffix) GR64:$src1, GR64:$src2)>; + + // xor reg/mem + def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), + (!cast(XOR8rm#suffix) GR8:$src1, addr:$src2)>; + def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), + (!cast(XOR16rm#suffix) GR16:$src1, addr:$src2)>; + def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), + (!cast(XOR32rm#suffix) GR32:$src1, addr:$src2)>; + def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), + (!cast(XOR64rm#suffix) GR64:$src1, addr:$src2)>; + + // xor reg/imm + def : Pat<(xor GR8:$src1, imm:$src2), + (!cast(XOR8ri#suffix) GR8:$src1, imm:$src2)>; + def : Pat<(xor GR16:$src1, imm:$src2), + (!cast(XOR16ri#suffix) GR16:$src1, imm:$src2)>; + def : Pat<(xor GR32:$src1, imm:$src2), + (!cast(XOR32ri#suffix) GR32:$src1, imm:$src2)>; + def : Pat<(xor GR64:$src1, i64immSExt32:$src2), + (!cast(XOR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; + + // and reg/reg + def : Pat<(and GR8 :$src1, GR8 :$src2), (!cast(AND8rr#suffix) GR8 :$src1, GR8 :$src2)>; + def : Pat<(and GR16:$src1, GR16:$src2), (!cast(AND16rr#suffix) GR16:$src1, GR16:$src2)>; + def : Pat<(and GR32:$src1, GR32:$src2), (!cast(AND32rr#suffix) GR32:$src1, GR32:$src2)>; + def : Pat<(and GR64:$src1, GR64:$src2), (!cast(AND64rr#suffix) GR64:$src1, GR64:$src2)>; + + // and reg/mem + def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), + (!cast(AND8rm#suffix) GR8:$src1, addr:$src2)>; + def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), + (!cast(AND16rm#suffix) GR16:$src1, addr:$src2)>; + def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), + (!cast(AND32rm#suffix) GR32:$src1, addr:$src2)>; + def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), + (!cast(AND64rm#suffix) GR64:$src1, addr:$src2)>; + + // and reg/imm + def : Pat<(and GR8:$src1, imm:$src2), + (!cast(AND8ri#suffix) GR8:$src1, imm:$src2)>; + def : Pat<(and GR16:$src1, imm:$src2), + (!cast(AND16ri#suffix) GR16:$src1, imm:$src2)>; + def : Pat<(and GR32:$src1, imm:$src2), + (!cast(AND32ri#suffix) GR32:$src1, imm:$src2)>; + def : Pat<(and GR64:$src1, i64immSExt32:$src2), + (!cast(AND64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; + } + + // Increment/Decrement reg. + // Do not make INC/DEC if it is slow + let Predicates = [UseIncDec, p] in { + def : Pat<(add GR8:$src, 1), (!cast(INC8r#suffix) GR8:$src)>; + def : Pat<(add GR16:$src, 1), (!cast(INC16r#suffix) GR16:$src)>; + def : Pat<(add GR32:$src, 1), (!cast(INC32r#suffix) GR32:$src)>; + def : Pat<(add GR64:$src, 1), (!cast(INC64r#suffix) GR64:$src)>; + def : Pat<(add GR8:$src, -1), (!cast(DEC8r#suffix) GR8:$src)>; + def : Pat<(add GR16:$src, -1), (!cast(DEC16r#suffix) GR16:$src)>; + def : Pat<(add GR32:$src, -1), (!cast(DEC32r#suffix) GR32:$src)>; + def : Pat<(add GR64:$src, -1), (!cast(DEC64r#suffix) GR64:$src)>; + + def : Pat<(X86add_flag_nocf GR8:$src, -1), (!cast(DEC8r#suffix) GR8:$src)>; + def : Pat<(X86add_flag_nocf GR16:$src, -1), (!cast(DEC16r#suffix) GR16:$src)>; + def : Pat<(X86add_flag_nocf GR32:$src, -1), (!cast(DEC32r#suffix) GR32:$src)>; + def : Pat<(X86add_flag_nocf GR64:$src, -1), (!cast(DEC64r#suffix) GR64:$src)>; + def : Pat<(X86sub_flag_nocf GR8:$src, -1), (!cast(INC8r#suffix) GR8:$src)>; + def : Pat<(X86sub_flag_nocf GR16:$src, -1), (!cast(INC16r#suffix) GR16:$src)>; + def : Pat<(X86sub_flag_nocf GR32:$src, -1), (!cast(INC32r#suffix) GR32:$src)>; + def : Pat<(X86sub_flag_nocf GR64:$src, -1), (!cast(INC64r#suffix) GR64:$src)>; + } +} + +defm : EFLAGSDefiningPats<"", NoNDD>; +defm : EFLAGSDefiningPats<"_ND", HasNDD>; // mul reg, imm def : Pat<(mul GR16:$src1, imm:$src2), @@ -2023,103 +2146,6 @@ def : Pat<(mul (loadi32 addr:$src1), imm:$src2), def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; -// Increment/Decrement reg. -// Do not make INC/DEC if it is slow -let Predicates = [UseIncDec] in { - def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; - def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; - def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; - def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; - def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; - def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; - def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; - def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; - - def : Pat<(X86add_flag_nocf GR8:$src, -1), (DEC8r GR8:$src)>; - def : Pat<(X86add_flag_nocf GR16:$src, -1), (DEC16r GR16:$src)>; - def : Pat<(X86add_flag_nocf GR32:$src, -1), (DEC32r GR32:$src)>; - def : Pat<(X86add_flag_nocf GR64:$src, -1), (DEC64r GR64:$src)>; - def : Pat<(X86sub_flag_nocf GR8:$src, -1), (INC8r GR8:$src)>; - def : Pat<(X86sub_flag_nocf GR16:$src, -1), (INC16r GR16:$src)>; - def : Pat<(X86sub_flag_nocf GR32:$src, -1), (INC32r GR32:$src)>; - def : Pat<(X86sub_flag_nocf GR64:$src, -1), (INC64r GR64:$src)>; -} - -// or reg/reg. -def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; -def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; -def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; -def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; - -// or reg/mem -def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), - (OR8rm GR8:$src1, addr:$src2)>; -def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), - (OR16rm GR16:$src1, addr:$src2)>; -def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), - (OR32rm GR32:$src1, addr:$src2)>; -def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), - (OR64rm GR64:$src1, addr:$src2)>; - -// or reg/imm -def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; -def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; -def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; -def : Pat<(or GR64:$src1, i64immSExt32:$src2), - (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; - -// xor reg/reg -def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; -def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; -def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; -def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; - -// xor reg/mem -def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), - (XOR8rm GR8:$src1, addr:$src2)>; -def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), - (XOR16rm GR16:$src1, addr:$src2)>; -def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), - (XOR32rm GR32:$src1, addr:$src2)>; -def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), - (XOR64rm GR64:$src1, addr:$src2)>; - -// xor reg/imm -def : Pat<(xor GR8:$src1, imm:$src2), - (XOR8ri GR8:$src1, imm:$src2)>; -def : Pat<(xor GR16:$src1, imm:$src2), - (XOR16ri GR16:$src1, imm:$src2)>; -def : Pat<(xor GR32:$src1, imm:$src2), - (XOR32ri GR32:$src1, imm:$src2)>; -def : Pat<(xor GR64:$src1, i64immSExt32:$src2), - (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; - -// and reg/reg -def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; -def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; -def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; -def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; - -// and reg/mem -def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), - (AND8rm GR8:$src1, addr:$src2)>; -def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), - (AND16rm GR16:$src1, addr:$src2)>; -def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), - (AND32rm GR32:$src1, addr:$src2)>; -def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), - (AND64rm GR64:$src1, addr:$src2)>; - -// and reg/imm -def : Pat<(and GR8:$src1, imm:$src2), - (AND8ri GR8:$src1, imm:$src2)>; -def : Pat<(and GR16:$src1, imm:$src2), - (AND16ri GR16:$src1, imm:$src2)>; -def : Pat<(and GR32:$src1, imm:$src2), - (AND32ri GR32:$src1, imm:$src2)>; -def : Pat<(and GR64:$src1, i64immSExt32:$src2), - (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; - // Bit scan instruction patterns to match explicit zero-undef behavior. def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; diff --git a/llvm/test/CodeGen/X86/apx/adc.ll b/llvm/test/CodeGen/X86/apx/adc.ll new file mode 100644 index 000000000000..8e2df5c27720 --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/adc.ll @@ -0,0 +1,485 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @adc8rr(i8 %a, i8 %b, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: adc8rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: adcb %sil, %dil, %al +; CHECK-NEXT: retq + %s = add i8 %a, %b + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = add i8 %s, %z + ret i8 %r +} + +define i16 @adc16rr(i16 %a, i16 %b, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: adcw %si, %di, %ax +; CHECK-NEXT: retq + %s = add i16 %a, %b + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + ret i16 %r +} + +define i32 @adc32rr(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: adcl %esi, %edi, %eax +; CHECK-NEXT: retq + %s = add i32 %a, %b + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + ret i32 %r +} + +define i64 @adc64rr(i64 %a, i64 %b, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: adcq %rsi, %rdi, %rax +; CHECK-NEXT: retq + %s = add i64 %a, %b + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + ret i64 %r +} + +define i8 @adc8rm(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: adc8rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: adcb (%rsi), %dil, %al +; CHECK-NEXT: retq + %b = load i8, ptr %ptr + %s = add i8 %a, %b + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = add i8 %s, %z + ret i8 %r +} + +define i16 @adc16rm(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: adcw (%rsi), %di, %ax +; CHECK-NEXT: retq + %b = load i16, ptr %ptr + %s = add i16 %a, %b + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + ret i16 %r +} + +define i32 @adc32rm(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: adcl (%rsi), %edi, %eax +; CHECK-NEXT: retq + %b = load i32, ptr %ptr + %s = add i32 %a, %b + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + ret i32 %r +} + +define i64 @adc64rm(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: adcq (%rsi), %rdi, %rax +; CHECK-NEXT: retq + %b = load i64, ptr %ptr + %s = add i64 %a, %b + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + ret i64 %r +} + +define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: adcw $0, %di, %ax +; CHECK-NEXT: addl $123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %s = add i16 %a, 123 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + ret i16 %r +} + +define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: adcl $123, %edi, %eax +; CHECK-NEXT: retq + %s = add i32 %a, 123 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + ret i32 %r +} + +define i64 @adc64ri8(i64 %a, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: adcq $123, %rdi, %rax +; CHECK-NEXT: retq + %s = add i64 %a, 123 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + ret i64 %r +} + +define i8 @adc8ri(i8 %a, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: adc8ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %sil, %dl, %al +; CHECK-NEXT: adcb $123, %dil, %al +; CHECK-NEXT: retq + %s = add i8 %a, 123 + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = add i8 %s, %z + ret i8 %r +} + +define i16 @adc16ri(i16 %a, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: adcw $0, %di, %ax +; CHECK-NEXT: addl $1234, %eax, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %s = add i16 %a, 1234 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + ret i16 %r +} + +define i32 @adc32ri(i32 %a, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: adcl $123456, %edi, %eax # imm = 0x1E240 +; CHECK-NEXT: retq + %s = add i32 %a, 123456 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + ret i32 %r +} + +define i64 @adc64ri(i64 %a, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: adcq $123456, %rdi, %rax # imm = 0x1E240 +; CHECK-NEXT: retq + %s = add i64 %a, 123456 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + ret i64 %r +} + +define i8 @adc8mr(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: adc8mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: adcb %dil, (%rsi), %al +; CHECK-NEXT: retq + %b = load i8, ptr %ptr + %s = add i8 %b, %a + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = add i8 %s, %z + ret i8 %r +} + +define i16 @adc16mr(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: adcw %di, (%rsi), %ax +; CHECK-NEXT: retq + %b = load i16, ptr %ptr + %s = add i16 %b, %a + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + ret i16 %r +} + +define i32 @adc32mr(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: adcl %edi, (%rsi), %eax +; CHECK-NEXT: retq + %b = load i32, ptr %ptr + %s = add i32 %b, %a + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + ret i32 %r +} + +define i64 @adc64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: adcq %rdi, (%rsi), %rax +; CHECK-NEXT: retq + %b = load i64, ptr %ptr + %s = add i64 %b, %a + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + ret i64 %r +} + +define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16mi8: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: adcw $0, (%rdi), %ax +; CHECK-NEXT: addl $123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %a = load i16, ptr %ptr + %s = add i16 %a, 123 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + ret i16 %r +} + +define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32mi8: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: adcl $123, (%rdi), %eax +; CHECK-NEXT: retq + %a = load i32, ptr %ptr + %s = add i32 %a, 123 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + ret i32 %r +} + +define i64 @adc64mi8(ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64mi8: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: adcq $123, (%rdi), %rax +; CHECK-NEXT: retq + %a = load i64, ptr %ptr + %s = add i64 %a, 123 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + ret i64 %r +} + +define i8 @adc8mi(ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: adc8mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %sil, %dl, %al +; CHECK-NEXT: adcb $123, (%rdi), %al +; CHECK-NEXT: retq + %a = load i8, ptr %ptr + %s = add i8 %a, 123 + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = add i8 %s, %z + ret i8 %r +} + +define i16 @adc16mi(ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: adcw $0, (%rdi), %ax +; CHECK-NEXT: addl $1234, %eax, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %a = load i16, ptr %ptr + %s = add i16 %a, 1234 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + ret i16 %r +} + +define i32 @adc32mi(ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: adcl $123456, (%rdi), %eax # imm = 0x1E240 +; CHECK-NEXT: retq + %a = load i32, ptr %ptr + %s = add i32 %a, 123456 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + ret i32 %r +} + +define i64 @adc64mi(ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: adcq $123456, (%rdi), %rax # imm = 0x1E240 +; CHECK-NEXT: retq + %a = load i64, ptr %ptr + %s = add i64 %a, 123456 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + ret i64 %r +} + +define void @adc8mr_legacy(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: adc8mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: adcb %dil, (%rsi) +; CHECK-NEXT: retq + %b = load i8, ptr %ptr + %s = add i8 %b, %a + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = add i8 %s, %z + store i8 %r, ptr %ptr + ret void +} + +define void @adc16mr_legacy(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: adcw %di, (%rsi) +; CHECK-NEXT: retq + %b = load i16, ptr %ptr + %s = add i16 %b, %a + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + store i16 %r, ptr %ptr + ret void +} + +define void @adc32mr_legacy(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: adcl %edi, (%rsi) +; CHECK-NEXT: retq + %b = load i32, ptr %ptr + %s = add i32 %b, %a + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + store i32 %r, ptr %ptr + ret void +} + +define void @adc64mr_legacy(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: adcq %rdi, (%rsi) +; CHECK-NEXT: retq + %b = load i64, ptr %ptr + %s = add i64 %b, %a + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + store i64 %r, ptr %ptr + ret void +} + +define void @adc8mi_legacy(ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: adc8mi_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %sil, %dl, %al +; CHECK-NEXT: adcb $123, (%rdi) +; CHECK-NEXT: retq + %a = load i8, ptr %ptr + %s = add i8 %a, 123 + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = add i8 %s, %z + store i8 %r, ptr %ptr + ret void +} + +define void @adc16mi_legacy(ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: adc16mi_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: adcw $0, (%rdi), %ax +; CHECK-NEXT: addl $1234, %eax, %eax # imm = 0x4D2 +; CHECK-NEXT: movw %ax, (%rdi) +; CHECK-NEXT: retq + %a = load i16, ptr %ptr + %s = add i16 %a, 1234 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = add i16 %s, %z + store i16 %r, ptr %ptr + ret void +} + +define void @adc32mi_legacy(ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: adc32mi_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: adcl $123456, (%rdi) # imm = 0x1E240 +; CHECK-NEXT: retq + %a = load i32, ptr %ptr + %s = add i32 %a, 123456 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = add i32 %s, %z + store i32 %r, ptr %ptr + ret void +} + +define void @adc64mi_legacy(ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: adc64mi_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: adcq $123456, (%rdi) # imm = 0x1E240 +; CHECK-NEXT: retq + %a = load i64, ptr %ptr + %s = add i64 %a, 123456 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = add i64 %s, %z + store i64 %r, ptr %ptr + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/add.ll b/llvm/test/CodeGen/X86/apx/add.ll new file mode 100644 index 000000000000..7502cde2df3c --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/add.ll @@ -0,0 +1,595 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @add8rr(i8 noundef %a, i8 noundef %b) { +; CHECK-LABEL: add8rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb %sil, %dil, %al +; CHECK-NEXT: retq +entry: + %add = add i8 %a, %b + ret i8 %add +} + +define i16 @add16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: add16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl %esi, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %add = add i16 %a, %b + ret i16 %add +} + +define i32 @add32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: add32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl %esi, %edi, %eax +; CHECK-NEXT: retq +entry: + %add = add i32 %a, %b + ret i32 %add +} + +define i64 @add64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: add64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq %rsi, %rdi, %rax +; CHECK-NEXT: retq +entry: + %add = add i64 %a, %b + ret i64 %add +} + +define i8 @add8rm(i8 noundef %a, ptr %ptr) { +; CHECK-LABEL: add8rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb (%rsi), %dil, %al +; CHECK-NEXT: retq +entry: + %b = load i8, ptr %ptr + %add = add i8 %a, %b + ret i8 %add +} + +define i16 @add16rm(i16 noundef %a, ptr %ptr) { +; CHECK-LABEL: add16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw (%rsi), %di, %ax +; CHECK-NEXT: retq +entry: + %b = load i16, ptr %ptr + %add = add i16 %a, %b + ret i16 %add +} + +define i32 @add32rm(i32 noundef %a, ptr %ptr) { +; CHECK-LABEL: add32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl (%rsi), %edi, %eax +; CHECK-NEXT: retq +entry: + %b = load i32, ptr %ptr + %add = add i32 %a, %b + ret i32 %add +} + +define i64 @add64rm(i64 noundef %a, ptr %ptr) { +; CHECK-LABEL: add64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq (%rsi), %rdi, %rax +; CHECK-NEXT: retq +entry: + %b = load i64, ptr %ptr + %add = add i64 %a, %b + ret i64 %add +} + +define i16 @add16ri8(i16 noundef %a) { +; CHECK-LABEL: add16ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %add = add i16 %a, 123 + ret i16 %add +} + +define i32 @add32ri8(i32 noundef %a) { +; CHECK-LABEL: add32ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123, %edi, %eax +; CHECK-NEXT: retq +entry: + %add = add i32 %a, 123 + ret i32 %add +} + +define i64 @add64ri8(i64 noundef %a) { +; CHECK-LABEL: add64ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $123, %rdi, %rax +; CHECK-NEXT: retq +entry: + %add = add i64 %a, 123 + ret i64 %add +} + +define i8 @add8ri(i8 noundef %a) { +; CHECK-LABEL: add8ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb $123, %dil, %al +; CHECK-NEXT: retq +entry: + %add = add i8 %a, 123 + ret i8 %add +} + +define i16 @add16ri(i16 noundef %a) { +; CHECK-LABEL: add16ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $1234, %edi, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %add = add i16 %a, 1234 + ret i16 %add +} + +define i32 @add32ri(i32 noundef %a) { +; CHECK-LABEL: add32ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123456, %edi, %eax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %add = add i32 %a, 123456 + ret i32 %add +} + +define i64 @add64ri(i64 noundef %a) { +; CHECK-LABEL: add64ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $123456, %rdi, %rax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %add = add i64 %a, 123456 + ret i64 %add +} + +define i8 @add8mr(ptr %a, i8 noundef %b) { +; CHECK-LABEL: add8mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb %sil, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %add = add nsw i8 %t, %b + ret i8 %add +} + +define i16 @add16mr(ptr %a, i16 noundef %b) { +; CHECK-LABEL: add16mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw %si, (%rdi), %ax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %add = add nsw i16 %t, %b + ret i16 %add +} + +define i32 @add32mr(ptr %a, i32 noundef %b) { +; CHECK-LABEL: add32mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl %esi, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %add = add nsw i32 %t, %b + ret i32 %add +} + +define i64 @add64mr(ptr %a, i64 noundef %b) { +; CHECK-LABEL: add64mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq %rsi, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %add = add nsw i64 %t, %b + ret i64 %add +} + +define i16 @add16mi8(ptr %a) { +; CHECK-LABEL: add16mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: addl $123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %add = add nsw i16 %t, 123 + ret i16 %add +} + +define i32 @add32mi8(ptr %a) { +; CHECK-LABEL: add32mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %add = add nsw i32 %t, 123 + ret i32 %add +} + +define i64 @add64mi8(ptr %a) { +; CHECK-LABEL: add64mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $123, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %add = add nsw i64 %t, 123 + ret i64 %add +} + +define i8 @add8mi(ptr %a) { +; CHECK-LABEL: add8mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb $123, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %add = add nsw i8 %t, 123 + ret i8 %add +} + +define i16 @add16mi(ptr %a) { +; CHECK-LABEL: add16mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: addl $1234, %eax, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %add = add nsw i16 %t, 1234 + ret i16 %add +} + +define i32 @add32mi(ptr %a) { +; CHECK-LABEL: add32mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123456, (%rdi), %eax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %add = add nsw i32 %t, 123456 + ret i32 %add +} + +define i64 @add64mi(ptr %a) { +; CHECK-LABEL: add64mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $123456, (%rdi), %rax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %add = add nsw i64 %t, 123456 + ret i64 %add +} + +declare i8 @llvm.uadd.sat.i8(i8, i8) +declare i16 @llvm.uadd.sat.i16(i16, i16) +declare i32 @llvm.uadd.sat.i32(i32, i32) +declare i64 @llvm.uadd.sat.i64(i64, i64) + +define i8 @addflag8rr(i8 noundef %a, i8 noundef %b) { +; CHECK-LABEL: addflag8rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb %sil, %dil, %al +; CHECK-NEXT: movzbl %al, %ecx +; CHECK-NEXT: movl $255, %eax +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %add = call i8 @llvm.uadd.sat.i8(i8 %a, i8 %b) + ret i8 %add +} + +define i16 @addflag16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: addflag16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw %si, %di, %cx +; CHECK-NEXT: movl $65535, %eax # imm = 0xFFFF +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %add = call i16 @llvm.uadd.sat.i16(i16 %a, i16 %b) + ret i16 %add +} + +define i32 @addflag32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: addflag32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl %esi, %edi, %ecx +; CHECK-NEXT: movl $-1, %eax +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: retq +entry: + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) + ret i32 %add +} + +define i64 @addflag64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: addflag64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq %rsi, %rdi, %rcx +; CHECK-NEXT: movq $-1, %rax +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %add = call i64 @llvm.uadd.sat.i64(i64 %a, i64 %b) + ret i64 %add +} + +define i8 @addflag8rm(i8 noundef %a, ptr %b) { +; CHECK-LABEL: addflag8rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb (%rsi), %dil, %al +; CHECK-NEXT: movzbl %al, %ecx +; CHECK-NEXT: movl $255, %eax +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %t = load i8, ptr %b + %add = call i8 @llvm.uadd.sat.i8(i8 %a, i8 %t) + ret i8 %add +} + +define i16 @addflag16rm(i16 noundef %a, ptr %b) { +; CHECK-LABEL: addflag16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw (%rsi), %di, %cx +; CHECK-NEXT: movl $65535, %eax # imm = 0xFFFF +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t = load i16, ptr %b + %add = call i16 @llvm.uadd.sat.i16(i16 %a, i16 %t) + ret i16 %add +} + +define i32 @addflag32rm(i32 noundef %a, ptr %b) { +; CHECK-LABEL: addflag32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl (%rsi), %edi, %ecx +; CHECK-NEXT: movl $-1, %eax +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: retq +entry: + %t = load i32, ptr %b + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %t) + ret i32 %add +} + +define i64 @addflag64rm(i64 noundef %a, ptr %b) { +; CHECK-LABEL: addflag64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq (%rsi), %rdi, %rcx +; CHECK-NEXT: movq $-1, %rax +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %t = load i64, ptr %b + %add = call i64 @llvm.uadd.sat.i64(i64 %a, i64 %t) + ret i64 %add +} + +define i16 @addflag16ri8(i16 noundef %a) { +; CHECK-LABEL: addflag16ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw $123, %di, %cx +; CHECK-NEXT: movl $65535, %eax # imm = 0xFFFF +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %add = call i16 @llvm.uadd.sat.i16(i16 %a, i16 123) + ret i16 %add +} + +define i32 @addflag32ri8(i32 noundef %a) { +; CHECK-LABEL: addflag32ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123, %edi, %ecx +; CHECK-NEXT: movl $-1, %eax +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: retq +entry: + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 123) + ret i32 %add +} + +define i64 @addflag64ri8(i64 noundef %a) { +; CHECK-LABEL: addflag64ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $123, %rdi, %rcx +; CHECK-NEXT: movq $-1, %rax +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %add = call i64 @llvm.uadd.sat.i64(i64 %a, i64 123) + ret i64 %add +} + +define i8 @addflag8ri(i8 noundef %a) { +; CHECK-LABEL: addflag8ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb $123, %dil, %al +; CHECK-NEXT: movzbl %al, %ecx +; CHECK-NEXT: movl $255, %eax +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %add = call i8 @llvm.uadd.sat.i8(i8 %a, i8 123) + ret i8 %add +} + +define i16 @addflag16ri(i16 noundef %a) { +; CHECK-LABEL: addflag16ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw $1234, %di, %cx # imm = 0x4D2 +; CHECK-NEXT: movl $65535, %eax # imm = 0xFFFF +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %add = call i16 @llvm.uadd.sat.i16(i16 %a, i16 1234) + ret i16 %add +} + +define i32 @addflag32ri(i32 noundef %a) { +; CHECK-LABEL: addflag32ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123456, %edi, %ecx # imm = 0x1E240 +; CHECK-NEXT: movl $-1, %eax +; CHECK-NEXT: cmovael %ecx, %eax +; CHECK-NEXT: retq +entry: + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 123456) + ret i32 %add +} + +define i64 @addflag64ri(i64 noundef %a) { +; CHECK-LABEL: addflag64ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $123456, %rdi, %rcx # imm = 0x1E240 +; CHECK-NEXT: movq $-1, %rax +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %add = call i64 @llvm.uadd.sat.i64(i64 %a, i64 123456) + ret i64 %add +} + +@val = external dso_local global i16, align 4 + +define i1 @add64ri_reloc(i16 %k) { +; CHECK-LABEL: add64ri_reloc: +; CHECK: # %bb.0: +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: movswq %di, %rax +; CHECK-NEXT: addq %rax, %rax, %rax +; CHECK-NEXT: addq $val, %rax, %rax +; CHECK-NEXT: setne %al +; CHECK-NEXT: retq + %g = getelementptr inbounds i16, ptr @val, i16 %k + %cmp = icmp ne ptr %g, null + ret i1 %cmp +} + +define void @add8mr_legacy(ptr %a, i8 noundef %b) { +; CHECK-LABEL: add8mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb %sil, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %add = add i8 %t, %b + store i8 %add, ptr %a + ret void +} + +define void @add16mr_legacy(ptr %a, i16 noundef %b) { +; CHECK-LABEL: add16mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw %si, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %add = add i16 %t, %b + store i16 %add, ptr %a + ret void +} + +define void @add32mr_legacy(ptr %a, i32 noundef %b) { +; CHECK-LABEL: add32mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl %esi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %add = add i32 %t, %b + store i32 %add, ptr %a + ret void +} + +define void @add64mr_legacy(ptr %a, i64 noundef %b) { +; CHECK-LABEL: add64mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq %rsi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %add = add i64 %t, %b + store i64 %add, ptr %a + ret void +} + +define void @add8mi_legacy(ptr %a) { +; CHECK-LABEL: add8mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb $123, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %add = add nsw i8 %t, 123 + store i8 %add, ptr %a + ret void +} + +define void @add16mi_legacy(ptr %a) { +; CHECK-LABEL: add16mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw $1234, (%rdi) # imm = 0x4D2 +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %add = add nsw i16 %t, 1234 + store i16 %add, ptr %a + ret void +} + +define void @add32mi_legacy(ptr %a) { +; CHECK-LABEL: add32mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $123456, (%rdi) # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %add = add nsw i32 %t, 123456 + store i32 %add, ptr %a + ret void +} + +define void @add64mi_legacy(ptr %a) { +; CHECK-LABEL: add64mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $123456, (%rdi) # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %add = add nsw i64 %t, 123456 + store i64 %add, ptr %a + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/dec.ll b/llvm/test/CodeGen/X86/apx/dec.ll new file mode 100644 index 000000000000..d79f1f5886ba --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/dec.ll @@ -0,0 +1,137 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @dec8r(i8 noundef %a) { +; CHECK-LABEL: dec8r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decb %dil, %al +; CHECK-NEXT: retq +entry: + %dec = sub i8 %a, 1 + ret i8 %dec +} + +define i16 @dec16r(i16 noundef %a) { +; CHECK-LABEL: dec16r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decl %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %dec = sub i16 %a, 1 + ret i16 %dec +} + +define i32 @dec32r(i32 noundef %a) { +; CHECK-LABEL: dec32r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decl %edi, %eax +; CHECK-NEXT: retq +entry: + %dec = sub i32 %a, 1 + ret i32 %dec +} + +define i64 @dec64r(i64 noundef %a) { +; CHECK-LABEL: dec64r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decq %rdi, %rax +; CHECK-NEXT: retq +entry: + %dec = sub i64 %a, 1 + ret i64 %dec +} + +define i8 @dec8m(ptr %ptr) { +; CHECK-LABEL: dec8m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decb (%rdi), %al +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %dec = sub i8 %a, 1 + ret i8 %dec +} + +define i16 @dec16m(ptr %ptr) { +; CHECK-LABEL: dec16m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: decl %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %dec = sub i16 %a, 1 + ret i16 %dec +} + +define i32 @dec32m(ptr %ptr) { +; CHECK-LABEL: dec32m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decl (%rdi), %eax +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %dec = sub i32 %a, 1 + ret i32 %dec +} + +define i64 @dec64m(ptr %ptr) { +; CHECK-LABEL: dec64m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decq (%rdi), %rax +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %dec = sub i64 %a, 1 + ret i64 %dec +} + +define void @dec8m_legacy(ptr %ptr) { +; CHECK-LABEL: dec8m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decb (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %dec = sub i8 %a, 1 + store i8 %dec, ptr %ptr + ret void +} + +define void @dec16m_legacy(ptr %ptr) { +; CHECK-LABEL: dec16m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decw (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %dec = sub i16 %a, 1 + store i16 %dec, ptr %ptr + ret void +} + +define void @dec32m_legacy(ptr %ptr) { +; CHECK-LABEL: dec32m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decl (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %dec = sub i32 %a, 1 + store i32 %dec, ptr %ptr + ret void +} + +define void @dec64m_legacy(ptr %ptr) { +; CHECK-LABEL: dec64m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: decq (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %dec = sub i64 %a, 1 + store i64 %dec, ptr %ptr + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/imul.ll b/llvm/test/CodeGen/X86/apx/imul.ll new file mode 100644 index 000000000000..2963a6477be4 --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/imul.ll @@ -0,0 +1,139 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i16 @mul16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: mul16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imull %esi, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %mul = mul i16 %a, %b + ret i16 %mul +} + +define i32 @mul32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: mul32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imull %esi, %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul i32 %a, %b + ret i32 %mul +} + +define i64 @mul64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: mul64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imulq %rsi, %rdi, %rax +; CHECK-NEXT: retq +entry: + %mul = mul i64 %a, %b + ret i64 %mul +} + +define i16 @smul16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: smul16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imulw %si, %di, %ax +; CHECK-NEXT: retq +entry: + %t = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b) + %mul = extractvalue {i16, i1} %t, 0 + ret i16 %mul +} + +define i32 @smul32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: smul32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imull %esi, %edi, %eax +; CHECK-NEXT: retq +entry: + %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b) + %mul = extractvalue {i32, i1} %t, 0 + ret i32 %mul +} + +define i64 @smul64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: smul64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imulq %rsi, %rdi, %rax +; CHECK-NEXT: retq +entry: + %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a, i64 %b) + %mul = extractvalue {i64, i1} %t, 0 + ret i64 %mul +} + +define i16 @mul16rm(i16 noundef %a, ptr %ptr) { +; CHECK-LABEL: mul16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imulw (%rsi), %di, %ax +; CHECK-NEXT: retq +entry: + %b = load i16, ptr %ptr + %mul = mul i16 %a, %b + ret i16 %mul +} + +define i32 @mul32rm(i32 noundef %a, ptr %ptr) { +; CHECK-LABEL: mul32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imull (%rsi), %edi, %eax +; CHECK-NEXT: retq +entry: + %b = load i32, ptr %ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +define i64 @mul64rm(i64 noundef %a, ptr %ptr) { +; CHECK-LABEL: mul64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imulq (%rsi), %rdi, %rax +; CHECK-NEXT: retq +entry: + %b = load i64, ptr %ptr + %mul = mul i64 %a, %b + ret i64 %mul +} + +define i16 @smul16rm(i16 noundef %a, ptr %ptr) { +; CHECK-LABEL: smul16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imulw (%rsi), %di, %ax +; CHECK-NEXT: retq +entry: + %b = load i16, ptr %ptr + %t = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b) + %mul = extractvalue {i16, i1} %t, 0 + ret i16 %mul +} + +define i32 @smul32rm(i32 noundef %a, ptr %ptr) { +; CHECK-LABEL: smul32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imull (%rsi), %edi, %eax +; CHECK-NEXT: retq +entry: + %b = load i32, ptr %ptr + %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b) + %mul = extractvalue {i32, i1} %t, 0 + ret i32 %mul +} + +define i64 @smul64rm(i64 noundef %a, ptr %ptr) { +; CHECK-LABEL: smul64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: imulq (%rsi), %rdi, %rax +; CHECK-NEXT: retq +entry: + %b = load i64, ptr %ptr + %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a, i64 %b) + %mul = extractvalue {i64, i1} %t, 0 + ret i64 %mul +} + +declare { i16, i1 } @llvm.smul.with.overflow.i16(i16, i16) nounwind readnone +declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone +declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone diff --git a/llvm/test/CodeGen/X86/apx/inc.ll b/llvm/test/CodeGen/X86/apx/inc.ll new file mode 100644 index 000000000000..28dbf75f5ada --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/inc.ll @@ -0,0 +1,193 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @inc8r(i8 noundef %a) { +; CHECK-LABEL: inc8r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incb %dil, %al +; CHECK-NEXT: retq +entry: + %inc = add i8 %a, 1 + ret i8 %inc +} + +define i16 @inc16r(i16 noundef %a) { +; CHECK-LABEL: inc16r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incl %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %inc = add i16 %a, 1 + ret i16 %inc +} + +define i32 @inc32r(i32 noundef %a) { +; CHECK-LABEL: inc32r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incl %edi, %eax +; CHECK-NEXT: retq +entry: + %inc = add i32 %a, 1 + ret i32 %inc +} + +define i64 @inc64r(i64 noundef %a) { +; CHECK-LABEL: inc64r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incq %rdi, %rax +; CHECK-NEXT: retq +entry: + %inc = add i64 %a, 1 + ret i64 %inc +} + +define i8 @inc8m(ptr %ptr) { +; CHECK-LABEL: inc8m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incb (%rdi), %al +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %inc = add i8 %a, 1 + ret i8 %inc +} + +define i16 @inc16m(ptr %ptr) { +; CHECK-LABEL: inc16m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: incl %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %inc = add i16 %a, 1 + ret i16 %inc +} + +define i32 @inc32m(ptr %ptr) { +; CHECK-LABEL: inc32m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incl (%rdi), %eax +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %inc = add i32 %a, 1 + ret i32 %inc +} + +define i64 @inc64m(ptr %ptr) { +; CHECK-LABEL: inc64m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incq (%rdi), %rax +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %inc = add i64 %a, 1 + ret i64 %inc +} + +define i8 @uinc8r(i8 noundef %a) { +; CHECK-LABEL: uinc8r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incb %dil, %al +; CHECK-NEXT: movzbl %al, %ecx +; CHECK-NEXT: movl $255, %eax +; CHECK-NEXT: cmovnel %ecx, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %inc = call i8 @llvm.uadd.sat.i8(i8 %a, i8 1) + ret i8 %inc +} + +define i16 @uinc16r(i16 noundef %a) { +; CHECK-LABEL: uinc16r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incw %di, %cx +; CHECK-NEXT: movl $65535, %eax # imm = 0xFFFF +; CHECK-NEXT: cmovnel %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %inc = call i16 @llvm.uadd.sat.i16(i16 %a, i16 1) + ret i16 %inc +} + +define i32 @uinc32r(i32 noundef %a) { +; CHECK-LABEL: uinc32r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incl %edi, %ecx +; CHECK-NEXT: movl $-1, %eax +; CHECK-NEXT: cmovnel %ecx, %eax +; CHECK-NEXT: retq +entry: + %inc = call i32 @llvm.uadd.sat.i32(i32 %a, i32 1) + ret i32 %inc +} + +define i64 @uinc64r(i64 noundef %a) { +; CHECK-LABEL: uinc64r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incq %rdi, %rcx +; CHECK-NEXT: movq $-1, %rax +; CHECK-NEXT: cmovneq %rcx, %rax +; CHECK-NEXT: retq +entry: + %inc = call i64 @llvm.uadd.sat.i64(i64 %a, i64 1) + ret i64 %inc +} + +declare i8 @llvm.uadd.sat.i8(i8, i8) +declare i16 @llvm.uadd.sat.i16(i16, i16) +declare i32 @llvm.uadd.sat.i32(i32, i32) +declare i64 @llvm.uadd.sat.i64(i64, i64) + +define void @inc8m_legacy(ptr %ptr) { +; CHECK-LABEL: inc8m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incb (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %inc = add i8 %a, 1 + store i8 %inc, ptr %ptr + ret void +} + +define void @inc16m_legacy(ptr %ptr) { +; CHECK-LABEL: inc16m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incw (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %inc = add i16 %a, 1 + store i16 %inc, ptr %ptr + ret void +} + +define void @inc32m_legacy(ptr %ptr) { +; CHECK-LABEL: inc32m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incl (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %inc = add i32 %a, 1 + store i32 %inc, ptr %ptr + ret void +} + +define void @inc64m_legacy(ptr %ptr) { +; CHECK-LABEL: inc64m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: incq (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %inc = add i64 %a, 1 + store i64 %inc, ptr %ptr + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/neg.ll b/llvm/test/CodeGen/X86/apx/neg.ll new file mode 100644 index 000000000000..c1c53fbdaebd --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/neg.ll @@ -0,0 +1,233 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @neg8r(i8 noundef %a) { +; CHECK-LABEL: neg8r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negb %dil, %al +; CHECK-NEXT: retq +entry: + %neg = sub i8 0, %a + ret i8 %neg +} + +define i16 @neg16r(i16 noundef %a) { +; CHECK-LABEL: neg16r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negl %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %neg = sub i16 0, %a + ret i16 %neg +} + +define i32 @neg32r(i32 noundef %a) { +; CHECK-LABEL: neg32r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negl %edi, %eax +; CHECK-NEXT: retq +entry: + %neg = sub i32 0, %a + ret i32 %neg +} + +define i64 @neg64r(i64 noundef %a) { +; CHECK-LABEL: neg64r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negq %rdi, %rax +; CHECK-NEXT: retq +entry: + %neg = sub i64 0, %a + ret i64 %neg +} + +define i8 @neg8m(ptr %ptr) { +; CHECK-LABEL: neg8m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negb (%rdi), %al +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %neg = sub i8 0, %a + ret i8 %neg +} + +define i16 @neg16m(ptr %ptr) { +; CHECK-LABEL: neg16m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negw (%rdi), %ax +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %neg = sub i16 0, %a + ret i16 %neg +} + +define i32 @neg32m(ptr %ptr) { +; CHECK-LABEL: neg32m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negl (%rdi), %eax +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %neg = sub i32 0, %a + ret i32 %neg +} + +define i64 @neg64m(ptr %ptr) { +; CHECK-LABEL: neg64m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negq (%rdi), %rax +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %neg = sub i64 0, %a + ret i64 %neg +} + +define i8 @uneg8r(i8 noundef %a) { +; CHECK-LABEL: uneg8r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negb %dil, %al +; CHECK-NEXT: retq +entry: + %t = call {i8, i1} @llvm.usub.with.overflow.i8(i8 0, i8 %a) + %neg = extractvalue {i8, i1} %t, 0 + ret i8 %neg +} + +define i16 @uneg16r(i16 noundef %a) { +; CHECK-LABEL: uneg16r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negl %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t = call {i16, i1} @llvm.usub.with.overflow.i16(i16 0, i16 %a) + %neg = extractvalue {i16, i1} %t, 0 + ret i16 %neg +} + +define i32 @uneg32r(i32 noundef %a) { +; CHECK-LABEL: uneg32r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negl %edi, %eax +; CHECK-NEXT: retq +entry: + %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 0, i32 %a) + %neg = extractvalue {i32, i1} %t, 0 + ret i32 %neg +} + +define i64 @uneg64r(i64 noundef %a) { +; CHECK-LABEL: uneg64r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negq %rdi, %rax +; CHECK-NEXT: retq +entry: + %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 0, i64 %a) + %neg = extractvalue {i64, i1} %t, 0 + ret i64 %neg +} + +define i8 @uneg8m(ptr %ptr) { +; CHECK-LABEL: uneg8m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negb (%rdi), %al +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %t = call {i8, i1} @llvm.usub.with.overflow.i8(i8 0, i8 %a) + %neg = extractvalue {i8, i1} %t, 0 + ret i8 %neg +} + +define i16 @uneg16m(ptr %ptr) { +; CHECK-LABEL: uneg16m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negw (%rdi), %ax +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %t = call {i16, i1} @llvm.usub.with.overflow.i16(i16 0, i16 %a) + %neg = extractvalue {i16, i1} %t, 0 + ret i16 %neg +} + +define i32 @uneg32m(ptr %ptr) { +; CHECK-LABEL: uneg32m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negl (%rdi), %eax +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 0, i32 %a) + %neg = extractvalue {i32, i1} %t, 0 + ret i32 %neg +} + +define i64 @uneg64m(ptr %ptr) { +; CHECK-LABEL: uneg64m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negq (%rdi), %rax +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 0, i64 %a) + %neg = extractvalue {i64, i1} %t, 0 + ret i64 %neg +} + +declare {i8, i1} @llvm.usub.with.overflow.i8(i8, i8) +declare {i16, i1} @llvm.usub.with.overflow.i16(i16, i16) +declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) +declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) + +define void @neg8m_legacy(ptr %ptr) { +; CHECK-LABEL: neg8m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negb (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %neg = sub i8 0, %a + store i8 %neg, ptr %ptr + ret void +} + +define void @neg16m_legacy(ptr %ptr) { +; CHECK-LABEL: neg16m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negw (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %neg = sub i16 0, %a + store i16 %neg, ptr %ptr + ret void +} + +define void @neg32m_legacy(ptr %ptr) { +; CHECK-LABEL: neg32m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negl (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %neg = sub i32 0, %a + store i32 %neg, ptr %ptr + ret void +} + +define void @neg64m_legacy(ptr %ptr) { +; CHECK-LABEL: neg64m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: negq (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %neg = sub i64 0, %a + store i64 %neg, ptr %ptr + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/not.ll b/llvm/test/CodeGen/X86/apx/not.ll new file mode 100644 index 000000000000..5369819d5129 --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/not.ll @@ -0,0 +1,137 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @not8r(i8 noundef %a) { +; CHECK-LABEL: not8r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notb %dil, %al +; CHECK-NEXT: retq +entry: + %not = xor i8 %a, -1 + ret i8 %not +} + +define i16 @not16r(i16 noundef %a) { +; CHECK-LABEL: not16r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notl %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %not = xor i16 %a, -1 + ret i16 %not +} + +define i32 @not32r(i32 noundef %a) { +; CHECK-LABEL: not32r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notl %edi, %eax +; CHECK-NEXT: retq +entry: + %not = xor i32 %a, -1 + ret i32 %not +} + +define i64 @not64r(i64 noundef %a) { +; CHECK-LABEL: not64r: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notq %rdi, %rax +; CHECK-NEXT: retq +entry: + %not = xor i64 %a, -1 + ret i64 %not +} + +define i8 @not8m(ptr %ptr) { +; CHECK-LABEL: not8m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notb (%rdi), %al +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %not = xor i8 %a, -1 + ret i8 %not +} + +define i16 @not16m(ptr %ptr) { +; CHECK-LABEL: not16m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: notl %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %not = xor i16 %a, -1 + ret i16 %not +} + +define i32 @not32m(ptr %ptr) { +; CHECK-LABEL: not32m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notl (%rdi), %eax +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %not = xor i32 %a, -1 + ret i32 %not +} + +define i64 @not64m(ptr %ptr) { +; CHECK-LABEL: not64m: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notq (%rdi), %rax +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %not = xor i64 %a, -1 + ret i64 %not +} + +define void @not8m_legacy(ptr %ptr) { +; CHECK-LABEL: not8m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notb (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i8, ptr %ptr + %not = xor i8 %a, -1 + store i8 %not, ptr %ptr + ret void +} + +define void @not16m_legacy(ptr %ptr) { +; CHECK-LABEL: not16m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notw (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i16, ptr %ptr + %not = xor i16 %a, -1 + store i16 %not, ptr %ptr + ret void +} + +define void @not32m_legacy(ptr %ptr) { +; CHECK-LABEL: not32m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notl (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i32, ptr %ptr + %not = xor i32 %a, -1 + store i32 %not, ptr %ptr + ret void +} + +define void @not64m_legacy(ptr %ptr) { +; CHECK-LABEL: not64m_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: notq (%rdi) +; CHECK-NEXT: retq +entry: + %a = load i64, ptr %ptr + %not = xor i64 %a, -1 + store i64 %not, ptr %ptr + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/or.ll b/llvm/test/CodeGen/X86/apx/or.ll new file mode 100644 index 000000000000..bd8149818203 --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/or.ll @@ -0,0 +1,593 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @or8rr(i8 noundef %a, i8 noundef %b) { +; CHECK-LABEL: or8rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl %esi, %edi, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %or = or i8 %a, %b + ret i8 %or +} + +define i16 @or16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: or16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl %esi, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %or = or i16 %a, %b + ret i16 %or +} + +define i32 @or32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: or32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl %esi, %edi, %eax +; CHECK-NEXT: retq +entry: + %or = or i32 %a, %b + ret i32 %or +} + +define i64 @or64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: or64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq %rsi, %rdi, %rax +; CHECK-NEXT: retq +entry: + %or = or i64 %a, %b + ret i64 %or +} + +define i8 @or8rm(i8 noundef %a, ptr %b) { +; CHECK-LABEL: or8rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orb (%rsi), %dil, %al +; CHECK-NEXT: retq +entry: + %t = load i8, ptr %b + %or = or i8 %a, %t + ret i8 %or +} + +define i16 @or16rm(i16 noundef %a, ptr %b) { +; CHECK-LABEL: or16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orw (%rsi), %di, %ax +; CHECK-NEXT: retq +entry: + %t = load i16, ptr %b + %or = or i16 %a, %t + ret i16 %or +} + +define i32 @or32rm(i32 noundef %a, ptr %b) { +; CHECK-LABEL: or32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl (%rsi), %edi, %eax +; CHECK-NEXT: retq +entry: + %t = load i32, ptr %b + %or = or i32 %a, %t + ret i32 %or +} + +define i64 @or64rm(i64 noundef %a, ptr %b) { +; CHECK-LABEL: or64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq (%rsi), %rdi, %rax +; CHECK-NEXT: retq +entry: + %t = load i64, ptr %b + %or = or i64 %a, %t + ret i64 %or +} + +define i16 @or16ri8(i16 noundef %a) { +; CHECK-LABEL: or16ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl $123, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %or = or i16 %a, 123 + ret i16 %or +} + +define i32 @or32ri8(i32 noundef %a) { +; CHECK-LABEL: or32ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl $123, %edi, %eax +; CHECK-NEXT: retq +entry: + %or = or i32 %a, 123 + ret i32 %or +} + +define i64 @or64ri8(i64 noundef %a) { +; CHECK-LABEL: or64ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq $123, %rdi, %rax +; CHECK-NEXT: retq +entry: + %or = or i64 %a, 123 + ret i64 %or +} + +define i8 @or8ri(i8 noundef %a) { +; CHECK-LABEL: or8ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orb $123, %dil, %al +; CHECK-NEXT: retq +entry: + %or = or i8 %a, 123 + ret i8 %or +} + +define i16 @or16ri(i16 noundef %a) { +; CHECK-LABEL: or16ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl $1234, %edi, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %or = or i16 %a, 1234 + ret i16 %or +} + +define i32 @or32ri(i32 noundef %a) { +; CHECK-LABEL: or32ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl $123456, %edi, %eax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %or = or i32 %a, 123456 + ret i32 %or +} + +define i64 @or64ri(i64 noundef %a) { +; CHECK-LABEL: or64ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq $123456, %rdi, %rax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %or = or i64 %a, 123456 + ret i64 %or +} + +define i8 @or8mr(ptr %a, i8 noundef %b) { +; CHECK-LABEL: or8mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orb %sil, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %or = or i8 %t, %b + ret i8 %or +} + +define i16 @or16mr(ptr %a, i16 noundef %b) { +; CHECK-LABEL: or16mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orw %si, (%rdi), %ax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %or = or i16 %t, %b + ret i16 %or +} + +define i32 @or32mr(ptr %a, i32 noundef %b) { +; CHECK-LABEL: or32mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl %esi, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %or = or i32 %t, %b + ret i32 %or +} + +define i64 @or64mr(ptr %a, i64 noundef %b) { +; CHECK-LABEL: or64mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq %rsi, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %or = or i64 %t, %b + ret i64 %or +} + +define i16 @or16mi8(ptr %a) { +; CHECK-LABEL: or16mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: orl $123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %or = or i16 %t, 123 + ret i16 %or +} + +define i32 @or32mi8(ptr %a) { +; CHECK-LABEL: or32mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl $123, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %or = or i32 %t, 123 + ret i32 %or +} + +define i64 @or64mi8(ptr %a) { +; CHECK-LABEL: or64mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq $123, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %or = or i64 %t, 123 + ret i64 %or +} + +define i8 @or8mi(ptr %a) { +; CHECK-LABEL: or8mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orb $123, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %or = or i8 %t, 123 + ret i8 %or +} + +define i16 @or16mi(ptr %a) { +; CHECK-LABEL: or16mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: orl $1234, %eax, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %or = or i16 %t, 1234 + ret i16 %or +} + +define i32 @or32mi(ptr %a) { +; CHECK-LABEL: or32mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl $123456, (%rdi), %eax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %or = or i32 %t, 123456 + ret i32 %or +} + +define i64 @or64mi(ptr %a) { +; CHECK-LABEL: or64mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq $123456, (%rdi), %rax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %or = or i64 %t, 123456 + ret i64 %or +} + +@d64 = dso_local global i64 0 + +define i1 @orflag8rr(i8 %a, i8 %b) { +; CHECK-LABEL: orflag8rr: +; CHECK: # %bb.0: +; CHECK-NEXT: notb %sil, %al +; CHECK-NEXT: orb %al, %dil, %cl +; CHECK-NEXT: sete %al +; CHECK-NEXT: movb %cl, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i8 %b, -1 + %v0 = or i8 %a, %xor ; 0xff << 50 + %v1 = icmp eq i8 %v0, 0 + store i8 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag16rr(i16 %a, i16 %b) { +; CHECK-LABEL: orflag16rr: +; CHECK: # %bb.0: +; CHECK-NEXT: notl %esi, %eax +; CHECK-NEXT: orw %ax, %di, %cx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i16 %b, -1 + %v0 = or i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag32rr(i32 %a, i32 %b) { +; CHECK-LABEL: orflag32rr: +; CHECK: # %bb.0: +; CHECK-NEXT: orl %esi, %edi, %ecx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %v0 = or i32 %a, %b ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag64rr(i64 %a, i64 %b) { +; CHECK-LABEL: orflag64rr: +; CHECK: # %bb.0: +; CHECK-NEXT: orq %rsi, %rdi, %rcx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %v0 = or i64 %a, %b ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag8rm(ptr %ptr, i8 %b) { +; CHECK-LABEL: orflag8rm: +; CHECK: # %bb.0: +; CHECK-NEXT: notb %sil, %al +; CHECK-NEXT: orb (%rdi), %al, %cl +; CHECK-NEXT: sete %al +; CHECK-NEXT: movb %cl, d64(%rip) +; CHECK-NEXT: retq + %a = load i8, ptr %ptr + %xor = xor i8 %b, -1 + %v0 = or i8 %a, %xor ; 0xff << 50 + %v1 = icmp eq i8 %v0, 0 + store i8 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag16rm(ptr %ptr, i16 %b) { +; CHECK-LABEL: orflag16rm: +; CHECK: # %bb.0: +; CHECK-NEXT: notl %esi, %eax +; CHECK-NEXT: orw (%rdi), %ax, %cx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %a = load i16, ptr %ptr + %xor = xor i16 %b, -1 + %v0 = or i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag32rm(ptr %ptr, i32 %b) { +; CHECK-LABEL: orflag32rm: +; CHECK: # %bb.0: +; CHECK-NEXT: orl (%rdi), %esi, %ecx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %a = load i32, ptr %ptr + %v0 = or i32 %a, %b ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag64rm(ptr %ptr, i64 %b) { +; CHECK-LABEL: orflag64rm: +; CHECK: # %bb.0: +; CHECK-NEXT: orq (%rdi), %rsi, %rcx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %a = load i64, ptr %ptr + %v0 = or i64 %a, %b ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag8ri(i8 %a) { +; CHECK-LABEL: orflag8ri: +; CHECK: # %bb.0: +; CHECK-NEXT: orb $-124, %dil, %cl +; CHECK-NEXT: sete %al +; CHECK-NEXT: movb %cl, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i8 123, -1 + %v0 = or i8 %a, %xor ; 0xff << 50 + %v1 = icmp eq i8 %v0, 0 + store i8 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag16ri(i16 %a) { +; CHECK-LABEL: orflag16ri: +; CHECK: # %bb.0: +; CHECK-NEXT: orw $-1235, %di, %cx # imm = 0xFB2D +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i16 1234, -1 + %v0 = or i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag32ri(i32 %a) { +; CHECK-LABEL: orflag32ri: +; CHECK: # %bb.0: +; CHECK-NEXT: orl $123456, %edi, %ecx # imm = 0x1E240 +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %v0 = or i32 %a, 123456 ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag64ri(i64 %a) { +; CHECK-LABEL: orflag64ri: +; CHECK: # %bb.0: +; CHECK-NEXT: orq $123456, %rdi, %rcx # imm = 0x1E240 +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %v0 = or i64 %a, 123456 ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag16ri8(i16 %a) { +; CHECK-LABEL: orflag16ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: orw $-124, %di, %cx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i16 123, -1 + %v0 = or i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag32ri8(i32 %a) { +; CHECK-LABEL: orflag32ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: orl $123, %edi, %ecx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %v0 = or i32 %a, 123 ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @orflag64ri8(i64 %a) { +; CHECK-LABEL: orflag64ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: orq $123, %rdi, %rcx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %v0 = or i64 %a, 123 ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define void @or8mr_legacy(ptr %a, i8 noundef %b) { +; CHECK-LABEL: or8mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orb %sil, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %or = or i8 %t, %b + store i8 %or, ptr %a + ret void +} + +define void @or16mr_legacy(ptr %a, i16 noundef %b) { +; CHECK-LABEL: or16mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orw %si, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %or = or i16 %t, %b + store i16 %or, ptr %a + ret void +} + +define void @or32mr_legacy(ptr %a, i32 noundef %b) { +; CHECK-LABEL: or32mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl %esi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %or = or i32 %t, %b + store i32 %or, ptr %a + ret void +} + +define void @or64mr_legacy(ptr %a, i64 noundef %b) { +; CHECK-LABEL: or64mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq %rsi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %or = or i64 %t, %b + store i64 %or, ptr %a + ret void +} + +define void @or8mi_legacy(ptr %a) { +; CHECK-LABEL: or8mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orb $123, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %or = or i8 %t, 123 + store i8 %or, ptr %a + ret void +} + +define void @or16mi_legacy(ptr %a) { +; CHECK-LABEL: or16mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orw $1234, (%rdi) # imm = 0x4D2 +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %or = or i16 %t, 1234 + store i16 %or, ptr %a + ret void +} + +define void @or32mi_legacy(ptr %a) { +; CHECK-LABEL: or32mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orl $123456, (%rdi) # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %or = or i32 %t, 123456 + store i32 %or, ptr %a + ret void +} + +define void @or64mi_legacy(ptr %a) { +; CHECK-LABEL: or64mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: orq $123456, (%rdi) # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %or = or i64 %t, 123456 + store i64 %or, ptr %a + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/sbb.ll b/llvm/test/CodeGen/X86/apx/sbb.ll new file mode 100644 index 000000000000..72a488e70b2c --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/sbb.ll @@ -0,0 +1,433 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @sbb8rr(i8 %a, i8 %b, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: sbb8rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: sbbb %sil, %dil, %al +; CHECK-NEXT: retq + %s = sub i8 %a, %b + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = sub i8 %s, %z + ret i8 %r +} + +define i16 @sbb16rr(i16 %a, i16 %b, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: sbbw %si, %di, %ax +; CHECK-NEXT: retq + %s = sub i16 %a, %b + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + ret i16 %r +} + +define i32 @sbb32rr(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: sbbl %esi, %edi, %eax +; CHECK-NEXT: retq + %s = sub i32 %a, %b + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + ret i32 %r +} + +define i64 @sbb64rr(i64 %a, i64 %b, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64rr: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: sbbq %rsi, %rdi, %rax +; CHECK-NEXT: retq + %s = sub i64 %a, %b + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + ret i64 %r +} + +define i8 @sbb8rm(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: sbb8rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: sbbb (%rsi), %dil, %al +; CHECK-NEXT: retq + %b = load i8, ptr %ptr + %s = sub i8 %a, %b + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = sub i8 %s, %z + ret i8 %r +} + +define i16 @sbb16rm(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: sbbw (%rsi), %di, %ax +; CHECK-NEXT: retq + %b = load i16, ptr %ptr + %s = sub i16 %a, %b + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + ret i16 %r +} + +define i32 @sbb32rm(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: sbbl (%rsi), %edi, %eax +; CHECK-NEXT: retq + %b = load i32, ptr %ptr + %s = sub i32 %a, %b + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + ret i32 %r +} + +define i64 @sbb64rm(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64rm: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: sbbq (%rsi), %rdi, %rax +; CHECK-NEXT: retq + %b = load i64, ptr %ptr + %s = sub i64 %a, %b + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + ret i64 %r +} + +define i16 @sbb16ri8(i16 %a, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: sbbw $0, %di, %ax +; CHECK-NEXT: addl $-123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %s = sub i16 %a, 123 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + ret i16 %r +} + +define i32 @sbb32ri8(i32 %a, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: sbbl $0, %edi, %eax +; CHECK-NEXT: addl $-123, %eax, %eax +; CHECK-NEXT: retq + %s = sub i32 %a, 123 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + ret i32 %r +} + +define i64 @sbb64ri8(i64 %a, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: sbbq $0, %rdi, %rax +; CHECK-NEXT: addq $-123, %rax, %rax +; CHECK-NEXT: retq + %s = sub i64 %a, 123 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + ret i64 %r +} + +define i8 @sbb8ri(i8 %a, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: sbb8ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %sil, %dl, %al +; CHECK-NEXT: sbbb $0, %dil, %al +; CHECK-NEXT: addb $-123, %al, %al +; CHECK-NEXT: retq + %s = sub i8 %a, 123 + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = sub i8 %s, %z + ret i8 %r +} + +define i16 @sbb16ri(i16 %a, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: sbbw $0, %di, %ax +; CHECK-NEXT: addl $-1234, %eax, %eax # imm = 0xFB2E +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %s = sub i16 %a, 1234 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + ret i16 %r +} + +define i32 @sbb32ri(i32 %a, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: sbbl $0, %edi, %eax +; CHECK-NEXT: addl $-123456, %eax, %eax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq + %s = sub i32 %a, 123456 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + ret i32 %r +} + +define i64 @sbb64ri(i64 %a, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64ri: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: sbbq $0, %rdi, %rax +; CHECK-NEXT: addq $-123456, %rax, %rax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq + %s = sub i64 %a, 123456 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + ret i64 %r +} + +define i8 @sbb8mr(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: sbb8mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: sbbb %dil, (%rsi), %al +; CHECK-NEXT: retq + %b = load i8, ptr %ptr + %s = sub i8 %b, %a + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = sub i8 %s, %z + ret i8 %r +} + +define i16 @sbb16mr(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: sbbw %di, (%rsi), %ax +; CHECK-NEXT: retq + %b = load i16, ptr %ptr + %s = sub i16 %b, %a + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + ret i16 %r +} + +define i32 @sbb32mr(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: sbbl %edi, (%rsi), %eax +; CHECK-NEXT: retq + %b = load i32, ptr %ptr + %s = sub i32 %b, %a + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + ret i32 %r +} + +define i64 @sbb64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64mr: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: sbbq %rdi, (%rsi), %rax +; CHECK-NEXT: retq + %b = load i64, ptr %ptr + %s = sub i64 %b, %a + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + ret i64 %r +} + +define i16 @sbb16mi8(ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16mi8: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: sbbw $0, (%rdi), %ax +; CHECK-NEXT: addl $-123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %a = load i16, ptr %ptr + %s = sub i16 %a, 123 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + ret i16 %r +} + +define i32 @sbb32mi8(ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32mi8: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: sbbl $0, (%rdi), %eax +; CHECK-NEXT: addl $-123, %eax, %eax +; CHECK-NEXT: retq + %a = load i32, ptr %ptr + %s = sub i32 %a, 123 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + ret i32 %r +} + +define i64 @sbb64mi8(ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64mi8: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: sbbq $0, (%rdi), %rax +; CHECK-NEXT: addq $-123, %rax, %rax +; CHECK-NEXT: retq + %a = load i64, ptr %ptr + %s = sub i64 %a, 123 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + ret i64 %r +} + +define i8 @sbb8mi(ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: sbb8mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %sil, %dl, %al +; CHECK-NEXT: sbbb $0, (%rdi), %al +; CHECK-NEXT: addb $-123, %al, %al +; CHECK-NEXT: retq + %a = load i8, ptr %ptr + %s = sub i8 %a, 123 + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = sub i8 %s, %z + ret i8 %r +} + +define i16 @sbb16mi(ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %si, %dx, %ax +; CHECK-NEXT: sbbw $0, (%rdi), %ax +; CHECK-NEXT: addl $-1234, %eax, %eax # imm = 0xFB2E +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq + %a = load i16, ptr %ptr + %s = sub i16 %a, 1234 + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + ret i16 %r +} + +define i32 @sbb32mi(ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %esi, %edx, %eax +; CHECK-NEXT: sbbl $0, (%rdi), %eax +; CHECK-NEXT: addl $-123456, %eax, %eax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq + %a = load i32, ptr %ptr + %s = sub i32 %a, 123456 + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + ret i32 %r +} + +define i64 @sbb64mi(ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64mi: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rsi, %rdx, %rax +; CHECK-NEXT: sbbq $0, (%rdi), %rax +; CHECK-NEXT: addq $-123456, %rax, %rax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq + %a = load i64, ptr %ptr + %s = sub i64 %a, 123456 + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + ret i64 %r +} + +define void @sbb8mr_legacy(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind { +; CHECK-LABEL: sbb8mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subb %dl, %cl, %al +; CHECK-NEXT: sbbb %dil, (%rsi) +; CHECK-NEXT: retq + %b = load i8, ptr %ptr + %s = sub i8 %b, %a + %k = icmp ugt i8 %x, %y + %z = zext i1 %k to i8 + %r = sub i8 %s, %z + store i8 %r, ptr %ptr + ret void +} + +define void @sbb16mr_legacy(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind { +; CHECK-LABEL: sbb16mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subw %dx, %cx, %ax +; CHECK-NEXT: sbbw %di, (%rsi) +; CHECK-NEXT: retq + %b = load i16, ptr %ptr + %s = sub i16 %b, %a + %k = icmp ugt i16 %x, %y + %z = zext i1 %k to i16 + %r = sub i16 %s, %z + store i16 %r, ptr %ptr + ret void +} + +define void @sbb32mr_legacy(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind { +; CHECK-LABEL: sbb32mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subl %edx, %ecx, %eax +; CHECK-NEXT: sbbl %edi, (%rsi) +; CHECK-NEXT: retq + %b = load i32, ptr %ptr + %s = sub i32 %b, %a + %k = icmp ugt i32 %x, %y + %z = zext i1 %k to i32 + %r = sub i32 %s, %z + store i32 %r, ptr %ptr + ret void +} + +define void @sbb64mr_legacy(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind { +; CHECK-LABEL: sbb64mr_legacy: +; CHECK: # %bb.0: +; CHECK-NEXT: subq %rdx, %rcx, %rax +; CHECK-NEXT: sbbq %rdi, (%rsi) +; CHECK-NEXT: retq + %b = load i64, ptr %ptr + %s = sub i64 %b, %a + %k = icmp ugt i64 %x, %y + %z = zext i1 %k to i64 + %r = sub i64 %s, %z + store i64 %r, ptr %ptr + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/sub.ll b/llvm/test/CodeGen/X86/apx/sub.ll new file mode 100644 index 000000000000..a6c76fe081b2 --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/sub.ll @@ -0,0 +1,609 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @sub8rr(i8 noundef %a, i8 noundef %b) { +; CHECK-LABEL: sub8rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subb %sil, %dil, %al +; CHECK-NEXT: retq +entry: + %sub = sub i8 %a, %b + ret i8 %sub +} + +define i16 @sub16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: sub16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subl %esi, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %sub = sub i16 %a, %b + ret i16 %sub +} + +define i32 @sub32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: sub32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subl %esi, %edi, %eax +; CHECK-NEXT: retq +entry: + %sub = sub i32 %a, %b + ret i32 %sub +} + +define i64 @sub64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: sub64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq %rsi, %rdi, %rax +; CHECK-NEXT: retq +entry: + %sub = sub i64 %a, %b + ret i64 %sub +} + +define i8 @sub8rm(i8 noundef %a, ptr %ptr) { +; CHECK-LABEL: sub8rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subb (%rsi), %dil, %al +; CHECK-NEXT: retq +entry: + %b = load i8, ptr %ptr + %sub = sub i8 %a, %b + ret i8 %sub +} + +define i16 @sub16rm(i16 noundef %a, ptr %ptr) { +; CHECK-LABEL: sub16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subw (%rsi), %di, %ax +; CHECK-NEXT: retq +entry: + %b = load i16, ptr %ptr + %sub = sub i16 %a, %b + ret i16 %sub +} + +define i32 @sub32rm(i32 noundef %a, ptr %ptr) { +; CHECK-LABEL: sub32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subl (%rsi), %edi, %eax +; CHECK-NEXT: retq +entry: + %b = load i32, ptr %ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +define i64 @sub64rm(i64 noundef %a, ptr %ptr) { +; CHECK-LABEL: sub64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq (%rsi), %rdi, %rax +; CHECK-NEXT: retq +entry: + %b = load i64, ptr %ptr + %sub = sub i64 %a, %b + ret i64 %sub +} + +define i16 @sub16ri8(i16 noundef %a) { +; CHECK-LABEL: sub16ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $-123, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %sub = sub i16 %a, 123 + ret i16 %sub +} + +define i32 @sub32ri8(i32 noundef %a) { +; CHECK-LABEL: sub32ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $-123, %edi, %eax +; CHECK-NEXT: retq +entry: + %sub = sub i32 %a, 123 + ret i32 %sub +} + +define i64 @sub64ri8(i64 noundef %a) { +; CHECK-LABEL: sub64ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $-123, %rdi, %rax +; CHECK-NEXT: retq +entry: + %sub = sub i64 %a, 123 + ret i64 %sub +} + +define i8 @sub8ri(i8 noundef %a) { +; CHECK-LABEL: sub8ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb $-123, %dil, %al +; CHECK-NEXT: retq +entry: + %sub = sub i8 %a, 123 + ret i8 %sub +} + +define i16 @sub16ri(i16 noundef %a) { +; CHECK-LABEL: sub16ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $-1234, %edi, %eax # imm = 0xFB2E +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %sub = sub i16 %a, 1234 + ret i16 %sub +} + +define i32 @sub32ri(i32 noundef %a) { +; CHECK-LABEL: sub32ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $-123456, %edi, %eax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq +entry: + %sub = sub i32 %a, 123456 + ret i32 %sub +} + +define i64 @sub64ri(i64 noundef %a) { +; CHECK-LABEL: sub64ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $-123456, %rdi, %rax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq +entry: + %sub = sub i64 %a, 123456 + ret i64 %sub +} + +define i8 @sub8mr(ptr %a, i8 noundef %b) { +; CHECK-LABEL: sub8mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subb %sil, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %sub = sub nsw i8 %t, %b + ret i8 %sub +} + +define i16 @sub16mr(ptr %a, i16 noundef %b) { +; CHECK-LABEL: sub16mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: subl %esi, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %sub = sub nsw i16 %t, %b + ret i16 %sub +} + +define i32 @sub32mr(ptr %a, i32 noundef %b) { +; CHECK-LABEL: sub32mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subl %esi, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %sub = sub nsw i32 %t, %b + ret i32 %sub +} + +define i64 @sub64mr(ptr %a, i64 noundef %b) { +; CHECK-LABEL: sub64mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq %rsi, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %sub = sub nsw i64 %t, %b + ret i64 %sub +} + +define i16 @sub16mi8(ptr %a) { +; CHECK-LABEL: sub16mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: addl $-123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %sub = sub nsw i16 %t, 123 + ret i16 %sub +} + +define i32 @sub32mi8(ptr %a) { +; CHECK-LABEL: sub32mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $-123, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %sub = sub nsw i32 %t, 123 + ret i32 %sub +} + +define i64 @sub64mi8(ptr %a) { +; CHECK-LABEL: sub64mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $-123, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %sub = sub nsw i64 %t, 123 + ret i64 %sub +} + +define i8 @sub8mi(ptr %a) { +; CHECK-LABEL: sub8mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb $-123, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %sub = sub nsw i8 %t, 123 + ret i8 %sub +} + +define i16 @sub16mi(ptr %a) { +; CHECK-LABEL: sub16mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: addl $-1234, %eax, %eax # imm = 0xFB2E +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %sub = sub nsw i16 %t, 1234 + ret i16 %sub +} + +define i32 @sub32mi(ptr %a) { +; CHECK-LABEL: sub32mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $-123456, (%rdi), %eax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %sub = sub nsw i32 %t, 123456 + ret i32 %sub +} + +define i64 @sub64mi(ptr %a) { +; CHECK-LABEL: sub64mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $-123456, (%rdi), %rax # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %sub = sub nsw i64 %t, 123456 + ret i64 %sub +} + +declare i8 @llvm.usub.sat.i8(i8, i8) +declare i16 @llvm.usub.sat.i16(i16, i16) +declare i32 @llvm.usub.sat.i32(i32, i32) +declare i64 @llvm.usub.sat.i64(i64, i64) + +define i8 @subflag8rr(i8 noundef %a, i8 noundef %b) { +; CHECK-LABEL: subflag8rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subb %sil, %dil, %al +; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %sub = call i8 @llvm.usub.sat.i8(i8 %a, i8 %b) + ret i8 %sub +} + +define i16 @subflag16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: subflag16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subw %si, %di, %ax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %sub = call i16 @llvm.usub.sat.i16(i16 %a, i16 %b) + ret i16 %sub +} + +define i32 @subflag32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: subflag32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subl %esi, %edi, %eax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: retq +entry: + %sub = call i32 @llvm.usub.sat.i32(i32 %a, i32 %b) + ret i32 %sub +} + +define i64 @subflag64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: subflag64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: subq %rsi, %rdi, %rcx +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %sub = call i64 @llvm.usub.sat.i64(i64 %a, i64 %b) + ret i64 %sub +} + +define i8 @subflag8rm(i8 noundef %a, ptr %b) { +; CHECK-LABEL: subflag8rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subb (%rsi), %dil, %al +; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %t = load i8, ptr %b + %sub = call i8 @llvm.usub.sat.i8(i8 %a, i8 %t) + ret i8 %sub +} + +define i16 @subflag16rm(i16 noundef %a, ptr %b) { +; CHECK-LABEL: subflag16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subw (%rsi), %di, %ax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t = load i16, ptr %b + %sub = call i16 @llvm.usub.sat.i16(i16 %a, i16 %t) + ret i16 %sub +} + +define i32 @subflag32rm(i32 noundef %a, ptr %b) { +; CHECK-LABEL: subflag32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subl (%rsi), %edi, %eax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: retq +entry: + %t = load i32, ptr %b + %sub = call i32 @llvm.usub.sat.i32(i32 %a, i32 %t) + ret i32 %sub +} + +define i64 @subflag64rm(i64 noundef %a, ptr %b) { +; CHECK-LABEL: subflag64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: subq (%rsi), %rdi, %rcx +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %t = load i64, ptr %b + %sub = call i64 @llvm.usub.sat.i64(i64 %a, i64 %t) + ret i64 %sub +} + +define i16 @subflag16ri8(i16 noundef %a) { +; CHECK-LABEL: subflag16ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subw $123, %di, %ax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %sub = call i16 @llvm.usub.sat.i16(i16 %a, i16 123) + ret i16 %sub +} + +define i32 @subflag32ri8(i32 noundef %a) { +; CHECK-LABEL: subflag32ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subl $123, %edi, %eax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: retq +entry: + %sub = call i32 @llvm.usub.sat.i32(i32 %a, i32 123) + ret i32 %sub +} + +define i64 @subflag64ri8(i64 noundef %a) { +; CHECK-LABEL: subflag64ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: subq $123, %rdi, %rcx +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %sub = call i64 @llvm.usub.sat.i64(i64 %a, i64 123) + ret i64 %sub +} + +define i8 @subflag8ri(i8 noundef %a) { +; CHECK-LABEL: subflag8ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subb $123, %dil, %al +; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %sub = call i8 @llvm.usub.sat.i8(i8 %a, i8 123) + ret i8 %sub +} + +define i16 @subflag16ri(i16 noundef %a) { +; CHECK-LABEL: subflag16ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subw $1234, %di, %ax # imm = 0x4D2 +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %sub = call i16 @llvm.usub.sat.i16(i16 %a, i16 1234) + ret i16 %sub +} + +define i32 @subflag32ri(i32 noundef %a) { +; CHECK-LABEL: subflag32ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: subl $123456, %edi, %eax # imm = 0x1E240 +; CHECK-NEXT: cmovbl %ecx, %eax +; CHECK-NEXT: retq +entry: + %sub = call i32 @llvm.usub.sat.i32(i32 %a, i32 123456) + ret i32 %sub +} + +define i64 @subflag64ri(i64 noundef %a) { +; CHECK-LABEL: subflag64ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: subq $123456, %rdi, %rcx # imm = 0x1E240 +; CHECK-NEXT: cmovaeq %rcx, %rax +; CHECK-NEXT: retq +entry: + %sub = call i64 @llvm.usub.sat.i64(i64 %a, i64 123456) + ret i64 %sub +} + +@val = external hidden global i8 + +declare void @f() + +define void @sub64ri_reloc(i64 %val) { +; CHECK-LABEL: sub64ri_reloc: +; CHECK: # %bb.0: +; CHECK-NEXT: subq $val, %rdi, %rax +; CHECK-NEXT: jbe .LBB41_2 +; CHECK-NEXT: # %bb.1: # %t +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: callq f@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: .LBB41_2: # %f +; CHECK-NEXT: retq + %cmp = icmp ugt i64 %val, ptrtoint (ptr @val to i64) + br i1 %cmp, label %t, label %f + +t: + call void @f() + ret void + +f: + ret void +} + +define void @sub8mr_legacy(ptr %a, i8 noundef %b) { +; CHECK-LABEL: sub8mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subb %sil, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %sub = sub i8 %t, %b + store i8 %sub, ptr %a + ret void +} + +define void @sub16mr_legacy(ptr %a, i16 noundef %b) { +; CHECK-LABEL: sub16mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subw %si, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %sub = sub i16 %t, %b + store i16 %sub, ptr %a + ret void +} + +define void @sub32mr_legacy(ptr %a, i32 noundef %b) { +; CHECK-LABEL: sub32mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subl %esi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %sub = sub i32 %t, %b + store i32 %sub, ptr %a + ret void +} + +define void @sub64mr_legacy(ptr %a, i64 noundef %b) { +; CHECK-LABEL: sub64mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq %rsi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %sub = sub i64 %t, %b + store i64 %sub, ptr %a + ret void +} + +define void @sub8mi_legacy(ptr %a) { +; CHECK-LABEL: sub8mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addb $-123, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %sub = sub nsw i8 %t, 123 + store i8 %sub, ptr %a + ret void +} + +define void @sub16mi_legacy(ptr %a) { +; CHECK-LABEL: sub16mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addw $-1234, (%rdi) # imm = 0xFB2E +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %sub = sub nsw i16 %t, 1234 + store i16 %sub, ptr %a + ret void +} + +define void @sub32mi_legacy(ptr %a) { +; CHECK-LABEL: sub32mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl $-123456, (%rdi) # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %sub = sub nsw i32 %t, 123456 + store i32 %sub, ptr %a + ret void +} + +define void @sub64mi_legacy(ptr %a) { +; CHECK-LABEL: sub64mi_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq $-123456, (%rdi) # imm = 0xFFFE1DC0 +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %sub = sub nsw i64 %t, 123456 + store i64 %sub, ptr %a + ret void +} diff --git a/llvm/test/CodeGen/X86/apx/xor.ll b/llvm/test/CodeGen/X86/apx/xor.ll new file mode 100644 index 000000000000..53f26f043331 --- /dev/null +++ b/llvm/test/CodeGen/X86/apx/xor.ll @@ -0,0 +1,545 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s + +define i8 @xor8rr(i8 noundef %a, i8 noundef %b) { +; CHECK-LABEL: xor8rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %esi, %edi, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: retq +entry: + %xor = xor i8 %a, %b + ret i8 %xor +} + +define i16 @xor16rr(i16 noundef %a, i16 noundef %b) { +; CHECK-LABEL: xor16rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %esi, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %xor = xor i16 %a, %b + ret i16 %xor +} + +define i32 @xor32rr(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: xor32rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %esi, %edi, %eax +; CHECK-NEXT: retq +entry: + %xor = xor i32 %a, %b + ret i32 %xor +} + +define i64 @xor64rr(i64 noundef %a, i64 noundef %b) { +; CHECK-LABEL: xor64rr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq %rsi, %rdi, %rax +; CHECK-NEXT: retq +entry: + %xor = xor i64 %a, %b + ret i64 %xor +} + +define i8 @xor8rm(i8 noundef %a, ptr %b) { +; CHECK-LABEL: xor8rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorb (%rsi), %dil, %al +; CHECK-NEXT: retq +entry: + %t = load i8, ptr %b + %xor = xor i8 %a, %t + ret i8 %xor +} + +define i16 @xor16rm(i16 noundef %a, ptr %b) { +; CHECK-LABEL: xor16rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorw (%rsi), %di, %ax +; CHECK-NEXT: retq +entry: + %t = load i16, ptr %b + %xor = xor i16 %a, %t + ret i16 %xor +} + +define i32 @xor32rm(i32 noundef %a, ptr %b) { +; CHECK-LABEL: xor32rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl (%rsi), %edi, %eax +; CHECK-NEXT: retq +entry: + %t = load i32, ptr %b + %xor = xor i32 %a, %t + ret i32 %xor +} + +define i64 @xor64rm(i64 noundef %a, ptr %b) { +; CHECK-LABEL: xor64rm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq (%rsi), %rdi, %rax +; CHECK-NEXT: retq +entry: + %t = load i64, ptr %b + %xor = xor i64 %a, %t + ret i64 %xor +} + +define i16 @xor16ri8(i16 noundef %a) { +; CHECK-LABEL: xor16ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl $123, %edi, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %xor = xor i16 %a, 123 + ret i16 %xor +} + +define i32 @xor32ri8(i32 noundef %a) { +; CHECK-LABEL: xor32ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl $123, %edi, %eax +; CHECK-NEXT: retq +entry: + %xor = xor i32 %a, 123 + ret i32 %xor +} + +define i64 @xor64ri8(i64 noundef %a) { +; CHECK-LABEL: xor64ri8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq $123, %rdi, %rax +; CHECK-NEXT: retq +entry: + %xor = xor i64 %a, 123 + ret i64 %xor +} + +define i8 @xor8ri(i8 noundef %a) { +; CHECK-LABEL: xor8ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorb $123, %dil, %al +; CHECK-NEXT: retq +entry: + %xor = xor i8 %a, 123 + ret i8 %xor +} + +define i16 @xor16ri(i16 noundef %a) { +; CHECK-LABEL: xor16ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl $1234, %edi, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %xor = xor i16 %a, 1234 + ret i16 %xor +} + +define i32 @xor32ri(i32 noundef %a) { +; CHECK-LABEL: xor32ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl $123456, %edi, %eax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %xor = xor i32 %a, 123456 + ret i32 %xor +} + +define i64 @xor64ri(i64 noundef %a) { +; CHECK-LABEL: xor64ri: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq $123456, %rdi, %rax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %xor = xor i64 %a, 123456 + ret i64 %xor +} + +define i8 @xor8mr(ptr %a, i8 noundef %b) { +; CHECK-LABEL: xor8mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorb %sil, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %xor = xor i8 %t, %b + ret i8 %xor +} + +define i16 @xor16mr(ptr %a, i16 noundef %b) { +; CHECK-LABEL: xor16mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorw %si, (%rdi), %ax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %xor = xor i16 %t, %b + ret i16 %xor +} + +define i32 @xor32mr(ptr %a, i32 noundef %b) { +; CHECK-LABEL: xor32mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %esi, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %xor = xor i32 %t, %b + ret i32 %xor +} + +define i64 @xor64mr(ptr %a, i64 noundef %b) { +; CHECK-LABEL: xor64mr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq %rsi, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %xor = xor i64 %t, %b + ret i64 %xor +} + +define i16 @xor16mi8(ptr %a) { +; CHECK-LABEL: xor16mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: xorl $123, %eax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %xor = xor i16 %t, 123 + ret i16 %xor +} + +define i32 @xor32mi8(ptr %a) { +; CHECK-LABEL: xor32mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl $123, (%rdi), %eax +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %xor = xor i32 %t, 123 + ret i32 %xor +} + +define i64 @xor64mi8(ptr %a) { +; CHECK-LABEL: xor64mi8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq $123, (%rdi), %rax +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %xor = xor i64 %t, 123 + ret i64 %xor +} + +define i8 @xor8mi(ptr %a) { +; CHECK-LABEL: xor8mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorb $123, (%rdi), %al +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %xor = xor i8 %t, 123 + ret i8 %xor +} + +define i16 @xor16mi(ptr %a) { +; CHECK-LABEL: xor16mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl (%rdi), %eax +; CHECK-NEXT: xorl $1234, %eax, %eax # imm = 0x4D2 +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %xor = xor i16 %t, 1234 + ret i16 %xor +} + +define i32 @xor32mi(ptr %a) { +; CHECK-LABEL: xor32mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl $123456, (%rdi), %eax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %xor = xor i32 %t, 123456 + ret i32 %xor +} + +define i64 @xor64mi(ptr %a) { +; CHECK-LABEL: xor64mi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq $123456, (%rdi), %rax # imm = 0x1E240 +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %xor = xor i64 %t, 123456 + ret i64 %xor +} + +@d64 = dso_local global i64 0 + +define i1 @xorflag8rr(i8 %a, i8 %b) { +; CHECK-LABEL: xorflag8rr: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %edi, %esi, %eax +; CHECK-NEXT: xorb $-1, %al, %cl +; CHECK-NEXT: sete %al +; CHECK-NEXT: movb %cl, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i8 %b, -1 + %v0 = xor i8 %a, %xor ; 0xff << 50 + %v1 = icmp eq i8 %v0, 0 + store i8 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag16rr(i16 %a, i16 %b) { +; CHECK-LABEL: xorflag16rr: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %edi, %esi, %eax +; CHECK-NEXT: xorw $-1, %ax, %cx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i16 %b, -1 + %v0 = xor i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag32rr(i32 %a, i32 %b) { +; CHECK-LABEL: xorflag32rr: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %esi, %edi, %ecx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %v0 = xor i32 %a, %b ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag64rr(i64 %a, i64 %b) { +; CHECK-LABEL: xorflag64rr: +; CHECK: # %bb.0: +; CHECK-NEXT: xorq %rsi, %rdi, %rcx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %v0 = xor i64 %a, %b ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag8rm(ptr %ptr, i8 %b) { +; CHECK-LABEL: xorflag8rm: +; CHECK: # %bb.0: +; CHECK-NEXT: xorb (%rdi), %sil, %al +; CHECK-NEXT: xorb $-1, %al, %cl +; CHECK-NEXT: sete %al +; CHECK-NEXT: movb %cl, d64(%rip) +; CHECK-NEXT: retq + %a = load i8, ptr %ptr + %xor = xor i8 %b, -1 + %v0 = xor i8 %a, %xor ; 0xff << 50 + %v1 = icmp eq i8 %v0, 0 + store i8 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag16rm(ptr %ptr, i16 %b) { +; CHECK-LABEL: xorflag16rm: +; CHECK: # %bb.0: +; CHECK-NEXT: xorw (%rdi), %si, %ax +; CHECK-NEXT: xorw $-1, %ax, %cx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %a = load i16, ptr %ptr + %xor = xor i16 %b, -1 + %v0 = xor i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag32rm(ptr %ptr, i32 %b) { +; CHECK-LABEL: xorflag32rm: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl (%rdi), %esi, %ecx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %a = load i32, ptr %ptr + %v0 = xor i32 %a, %b ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag64rm(ptr %ptr, i64 %b) { +; CHECK-LABEL: xorflag64rm: +; CHECK: # %bb.0: +; CHECK-NEXT: xorq (%rdi), %rsi, %rcx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %a = load i64, ptr %ptr + %v0 = xor i64 %a, %b ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag8ri(i8 %a) { +; CHECK-LABEL: xorflag8ri: +; CHECK: # %bb.0: +; CHECK-NEXT: xorb $-124, %dil, %cl +; CHECK-NEXT: sete %al +; CHECK-NEXT: movb %cl, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i8 123, -1 + %v0 = xor i8 %a, %xor ; 0xff << 50 + %v1 = icmp eq i8 %v0, 0 + store i8 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag16ri(i16 %a) { +; CHECK-LABEL: xorflag16ri: +; CHECK: # %bb.0: +; CHECK-NEXT: xorw $-1235, %di, %cx # imm = 0xFB2D +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i16 1234, -1 + %v0 = xor i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag32ri(i32 %a) { +; CHECK-LABEL: xorflag32ri: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl $123456, %edi, %ecx # imm = 0x1E240 +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %v0 = xor i32 %a, 123456 ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag64ri(i64 %a) { +; CHECK-LABEL: xorflag64ri: +; CHECK: # %bb.0: +; CHECK-NEXT: xorq $123456, %rdi, %rcx # imm = 0x1E240 +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %v0 = xor i64 %a, 123456 ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag16ri8(i16 %a) { +; CHECK-LABEL: xorflag16ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: xorw $-124, %di, %cx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movw %cx, d64(%rip) +; CHECK-NEXT: retq + %xor = xor i16 123, -1 + %v0 = xor i16 %a, %xor ; 0xff << 50 + %v1 = icmp eq i16 %v0, 0 + store i16 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag32ri8(i32 %a) { +; CHECK-LABEL: xorflag32ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl $123, %edi, %ecx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movl %ecx, d64(%rip) +; CHECK-NEXT: retq + %v0 = xor i32 %a, 123 ; 0xff << 50 + %v1 = icmp eq i32 %v0, 0 + store i32 %v0, ptr @d64 + ret i1 %v1 +} + +define i1 @xorflag64ri8(i64 %a) { +; CHECK-LABEL: xorflag64ri8: +; CHECK: # %bb.0: +; CHECK-NEXT: xorq $123, %rdi, %rcx +; CHECK-NEXT: sete %al +; CHECK-NEXT: movq %rcx, d64(%rip) +; CHECK-NEXT: retq + %v0 = xor i64 %a, 123 ; 0xff << 50 + %v1 = icmp eq i64 %v0, 0 + store i64 %v0, ptr @d64 + ret i1 %v1 +} + +define void @xor8mr_legacy(ptr %a, i8 noundef %b) { +; CHECK-LABEL: xor8mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorb %sil, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i8, ptr %a + %xor = xor i8 %t, %b + store i8 %xor, ptr %a + ret void +} + +define void @xor16mr_legacy(ptr %a, i16 noundef %b) { +; CHECK-LABEL: xor16mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorw %si, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i16, ptr %a + %xor = xor i16 %t, %b + store i16 %xor, ptr %a + ret void +} + +define void @xor32mr_legacy(ptr %a, i32 noundef %b) { +; CHECK-LABEL: xor32mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %esi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i32, ptr %a + %xor = xor i32 %t, %b + store i32 %xor, ptr %a + ret void +} + +define void @xor64mr_legacy(ptr %a, i64 noundef %b) { +; CHECK-LABEL: xor64mr_legacy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorq %rsi, (%rdi) +; CHECK-NEXT: retq +entry: + %t= load i64, ptr %a + %xor = xor i64 %t, %b + store i64 %xor, ptr %a + ret void +} -- GitLab From 1e05236dbdf6f1b27b5e68c3948fec7deea4e3dc Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 10 Jan 2024 20:25:24 -0800 Subject: [PATCH 412/652] [Target] Use isNullConstant (NFC) --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 10 +++------- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 ++------ llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 13 ++++--------- 3 files changed, 9 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 119aa80b9bb5..41462d7a133e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1579,13 +1579,9 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, bool AMDGPUDAGToDAGISel::SelectBUFSOffset(SDValue ByteOffsetNode, SDValue &SOffset) const { - if (Subtarget->hasRestrictedSOffset()) { - if (auto SOffsetConst = dyn_cast(ByteOffsetNode)) { - if (SOffsetConst->isZero()) { - SOffset = CurDAG->getRegister(AMDGPU::SGPR_NULL, MVT::i32); - return true; - } - } + if (Subtarget->hasRestrictedSOffset() && isNullConstant(ByteOffsetNode)) { + SOffset = CurDAG->getRegister(AMDGPU::SGPR_NULL, MVT::i32); + return true; } SOffset = ByteOffsetNode; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 6ddc7e864fb2..5a9222e91588 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -8181,12 +8181,8 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, // SGPR_NULL to avoid generating an extra s_mov with zero. static SDValue selectSOffset(SDValue SOffset, SelectionDAG &DAG, const GCNSubtarget *Subtarget) { - if (Subtarget->hasRestrictedSOffset()) - if (auto SOffsetConst = dyn_cast(SOffset)) { - if (SOffsetConst->isZero()) { - return DAG.getRegister(AMDGPU::SGPR_NULL, MVT::i32); - } - } + if (Subtarget->hasRestrictedSOffset() && isNullConstant(SOffset)) + return DAG.getRegister(AMDGPU::SGPR_NULL, MVT::i32); return SOffset; } diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index e68904863cfc..fc066f001316 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -1149,15 +1149,10 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { // but they are different from CMP. // FIXME: since we're doing a post-processing, use a pseudoinstr here, so // lowering & isel wouldn't diverge. - bool andCC = false; - if (ConstantSDNode *RHSC = dyn_cast(RHS)) { - if (RHSC->isZero() && LHS.hasOneUse() && - (LHS.getOpcode() == ISD::AND || - (LHS.getOpcode() == ISD::TRUNCATE && - LHS.getOperand(0).getOpcode() == ISD::AND))) { - andCC = true; - } - } + bool andCC = isNullConstant(RHS) && LHS.hasOneUse() && + (LHS.getOpcode() == ISD::AND || + (LHS.getOpcode() == ISD::TRUNCATE && + LHS.getOperand(0).getOpcode() == ISD::AND)); ISD::CondCode CC = cast(Op.getOperand(2))->get(); SDValue TargetCC; SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); -- GitLab From 12bba0d4f8c2df655958decb8eb788327543b3fe Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 10 Jan 2024 20:31:41 -0800 Subject: [PATCH 413/652] [clang-query] Use StringRef::ltrim (NFC) --- clang-tools-extra/clang-query/QueryParser.cpp | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/clang-tools-extra/clang-query/QueryParser.cpp b/clang-tools-extra/clang-query/QueryParser.cpp index 41933625a4fa..162acc1a598d 100644 --- a/clang-tools-extra/clang-query/QueryParser.cpp +++ b/clang-tools-extra/clang-query/QueryParser.cpp @@ -28,10 +28,8 @@ namespace query { // is found before End, return StringRef(). Begin is adjusted to exclude the // lexed region. StringRef QueryParser::lexWord() { - Line = Line.drop_while([](char c) { - // Don't trim newlines. - return StringRef(" \t\v\f\r").contains(c); - }); + // Don't trim newlines. + Line = Line.ltrim(" \t\v\f\r"); if (Line.empty()) // Even though the Line is empty, it contains a pointer and @@ -152,8 +150,7 @@ QueryRef QueryParser::parseSetTraversalKind(TraversalKind QuerySession::*Var) { QueryRef QueryParser::endQuery(QueryRef Q) { StringRef Extra = Line; - StringRef ExtraTrimmed = Extra.drop_while( - [](char c) { return StringRef(" \t\v\f\r").contains(c); }); + StringRef ExtraTrimmed = Extra.ltrim(" \t\v\f\r"); if ((!ExtraTrimmed.empty() && ExtraTrimmed[0] == '\n') || (ExtraTrimmed.size() >= 2 && ExtraTrimmed[0] == '\r' && -- GitLab From be76f1646f966cbebb4c52ca0faa41921a284262 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 10 Jan 2024 21:06:01 -0800 Subject: [PATCH 414/652] [Target] Use getConstantOperandAPInt (NFC) --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 +-- llvm/lib/Target/ARM/ARMISelLowering.cpp | 9 +++------ llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 4 +--- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++-- 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 47e665176e8b..e2d07a096496 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4513,8 +4513,7 @@ static SDValue skipExtensionForVectorMULL(SDValue N, SelectionDAG &DAG) { SDLoc dl(N); SmallVector Ops; for (unsigned i = 0; i != NumElts; ++i) { - ConstantSDNode *C = cast(N.getOperand(i)); - const APInt &CInt = C->getAPIntValue(); + const APInt &CInt = N.getConstantOperandAPInt(i); // Element types smaller than 32 bits are not legal, so use i32 elements. // The values are implicitly truncated so sext vs. zext doesn't matter. Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32)); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 568085bd0ab3..f8a281032c77 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -9577,8 +9577,7 @@ static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) { SmallVector Ops; SDLoc dl(N); for (unsigned i = 0; i != NumElts; ++i) { - ConstantSDNode *C = cast(N->getOperand(i)); - const APInt &CInt = C->getAPIntValue(); + const APInt &CInt = N->getConstantOperandAPInt(i); // Element types smaller than 32 bits are not legal, so use i32 elements. // The values are implicitly truncated so sext vs. zext doesn't matter. Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32)); @@ -18080,8 +18079,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D SDValue Op0 = CMOV->getOperand(0); SDValue Op1 = CMOV->getOperand(1); - auto CCNode = cast(CMOV->getOperand(2)); - auto CC = CCNode->getAPIntValue().getLimitedValue(); + auto CC = CMOV->getConstantOperandAPInt(2).getLimitedValue(); SDValue CmpZ = CMOV->getOperand(4); // The compare must be against zero. @@ -20109,8 +20107,7 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, // The operand to BFI is already a mask suitable for removing the bits it // sets. - ConstantSDNode *CI = cast(Op.getOperand(2)); - const APInt &Mask = CI->getAPIntValue(); + const APInt &Mask = Op.getConstantOperandAPInt(2); Known.Zero &= Mask; Known.One &= Mask; return; diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 407cd6c0f8be..34c5569b8076 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -2019,9 +2019,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, DL, RetTy, Args, Outs, retAlignment, HasVAArgs ? std::optional>(std::make_pair( - CLI.NumFixedArgs, - cast(VADeclareParam->getOperand(1)) - ->getAPIntValue())) + CLI.NumFixedArgs, VADeclareParam->getConstantOperandAPInt(1))) : std::nullopt, *CB, UniqueCallSite); const char *ProtoStr = nvTM->getStrPool().save(Proto).data(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5f6f500e49dd..700ab797b2f6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -4822,8 +4822,8 @@ static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits, APInt UndefSrcElts(NumSrcElts, 0); SmallVector SrcEltBits; - auto *CN = cast(Op.getOperand(0).getOperand(0)); - SrcEltBits.push_back(CN->getAPIntValue().zextOrTrunc(SrcEltSizeInBits)); + const APInt &C = Op.getOperand(0).getConstantOperandAPInt(0); + SrcEltBits.push_back(C.zextOrTrunc(SrcEltSizeInBits)); SrcEltBits.append(NumSrcElts - 1, APInt(SrcEltSizeInBits, 0)); return CastBitData(UndefSrcElts, SrcEltBits); } -- GitLab From e8790027b169fa10dcdb04f076cf4efafeda704c Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Thu, 11 Jan 2024 12:12:46 +0700 Subject: [PATCH 415/652] [RISCV] Allow vsetvlis with same register AVL in doLocalPostpass (#76801) --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 37 +++++++------------ .../CodeGen/RISCV/rvv/fixed-vectors-insert.ll | 6 +-- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 3 +- 3 files changed, 17 insertions(+), 29 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index e591aa935c0b..6c9e529e4bfb 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -1464,20 +1464,6 @@ static void doUnion(DemandedFields &A, DemandedFields B) { A.MaskPolicy |= B.MaskPolicy; } -static bool isNonZeroAVL(const MachineOperand &MO, - const MachineRegisterInfo &MRI) { - if (MO.isReg()) { - if (MO.getReg() == RISCV::X0) - return true; - if (MachineInstr *MI = MRI.getVRegDef(MO.getReg()); - MI && isNonZeroLoadImmediate(*MI)) - return true; - return false; - } - assert(MO.isImm()); - return 0 != MO.getImm(); -} - // Return true if we can mutate PrevMI to match MI without changing any the // fields which would be observed. static bool canMutatePriorConfig(const MachineInstr &PrevMI, @@ -1491,21 +1477,26 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI, if (Used.VLAny) return false; - // We don't bother to handle the equally zero case here as it's largely - // uninteresting. if (Used.VLZeroness) { if (isVLPreservingConfig(PrevMI)) return false; - if (!isNonZeroAVL(MI.getOperand(1), MRI) || - !isNonZeroAVL(PrevMI.getOperand(1), MRI)) + if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI), + MRI)) return false; } - // TODO: Track whether the register is defined between - // PrevMI and MI. - if (MI.getOperand(1).isReg() && - RISCV::X0 != MI.getOperand(1).getReg()) - return false; + auto &AVL = MI.getOperand(1); + auto &PrevAVL = PrevMI.getOperand(1); + assert(MRI.isSSA()); + + // If the AVL is a register, we need to make sure MI's AVL dominates PrevMI. + // For now just check that PrevMI uses the same virtual register. + if (AVL.isReg() && AVL.getReg() != RISCV::X0) { + if (AVL.getReg().isPhysical()) + return false; + if (!PrevAVL.isReg() || PrevAVL.getReg() != AVL.getReg()) + return false; + } } if (!PrevMI.getOperand(2).isImm() || !MI.getOperand(2).isImm()) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll index 57760070603b..4954827876c1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll @@ -63,9 +63,8 @@ define <32 x i32> @insertelt_v32i32_31(<32 x i32> %a, i32 %y) { ; CHECK-LABEL: insertelt_v32i32_31: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma -; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vslideup.vi v8, v16, 31 ; CHECK-NEXT: ret %b = insertelement <32 x i32> %a, i32 %y, i32 31 @@ -101,9 +100,8 @@ define <64 x i32> @insertelt_v64i32_63(<64 x i32> %a, i32 %y) { ; CHECK-LABEL: insertelt_v64i32_63: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma -; CHECK-NEXT: vmv.s.x v24, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vmv.s.x v24, a0 ; CHECK-NEXT: vslideup.vi v16, v24, 31 ; CHECK-NEXT: ret %b = insertelement <64 x i32> %a, i32 %y, i32 63 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll index e15c5a3323cb..7c95d8130665 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll @@ -643,9 +643,8 @@ define @fp_reduction_vfmv_s_f(float %0, @int_reduction_vmv_s_x(i32 signext %0, %1, i64 %2) { ; CHECK-LABEL: int_reduction_vmv_s_x: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma -; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vredsum.vs v8, v8, v12 ; CHECK-NEXT: ret %4 = tail call @llvm.riscv.vmv.s.x.nxv8i32.i64( poison, i32 %0, i64 %2) -- GitLab From 164f85db876e61cf4a3c34493ed11e8f5820f968 Mon Sep 17 00:00:00 2001 From: Bill Wendling <5993918+bwendling@users.noreply.github.com> Date: Wed, 10 Jan 2024 15:21:10 -0800 Subject: [PATCH 416/652] [Clang] Implement the 'counted_by' attribute (#76348) The 'counted_by' attribute is used on flexible array members. The argument for the attribute is the name of the field member holding the count of elements in the flexible array. This information is used to improve the results of the array bound sanitizer and the '__builtin_dynamic_object_size' builtin. The 'count' field member must be within the same non-anonymous, enclosing struct as the flexible array member. For example: ``` struct bar; struct foo { int count; struct inner { struct { int count; /* The 'count' referenced by 'counted_by' */ }; struct { /* ... */ struct bar *array[] __attribute__((counted_by(count))); }; } baz; }; ``` This example specifies that the flexible array member 'array' has the number of elements allocated for it in 'count': ``` struct bar; struct foo { size_t count; /* ... */ struct bar *array[] __attribute__((counted_by(count))); }; ``` This establishes a relationship between 'array' and 'count'; specifically that 'p->array' must have *at least* 'p->count' number of elements available. It's the user's responsibility to ensure that this relationship is maintained throughout changes to the structure. In the following, the allocated array erroneously has fewer elements than what's specified by 'p->count'. This would result in an out-of-bounds access not not being detected: ``` struct foo *p; void foo_alloc(size_t count) { p = malloc(MAX(sizeof(struct foo), offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); p->count = count + 42; } ``` The next example updates 'p->count', breaking the relationship requirement that 'p->array' must have at least 'p->count' number of elements available: ``` void use_foo(int index, int val) { p->count += 42; p->array[index] = val; /* The sanitizer can't properly check this access */ } ``` In this example, an update to 'p->count' maintains the relationship requirement: ``` void use_foo(int index, int val) { if (p->count == 0) return; --p->count; p->array[index] = val; } ``` --- clang/docs/ReleaseNotes.rst | 5 + clang/include/clang/AST/DeclBase.h | 10 + clang/include/clang/Basic/Attr.td | 18 + clang/include/clang/Basic/AttrDocs.td | 78 + .../clang/Basic/DiagnosticSemaKinds.td | 13 + clang/include/clang/Sema/Sema.h | 3 + clang/include/clang/Sema/TypoCorrection.h | 12 +- clang/lib/AST/ASTImporter.cpp | 13 + clang/lib/AST/DeclBase.cpp | 74 +- clang/lib/AST/Expr.cpp | 83 +- clang/lib/CodeGen/CGBuiltin.cpp | 240 +++ clang/lib/CodeGen/CGExpr.cpp | 340 ++- clang/lib/CodeGen/CodeGenFunction.h | 22 + clang/lib/Sema/SemaDecl.cpp | 6 + clang/lib/Sema/SemaDeclAttr.cpp | 133 ++ clang/lib/Sema/SemaExpr.cpp | 16 +- clang/test/CodeGen/attr-counted-by.c | 1828 +++++++++++++++++ clang/test/CodeGen/bounds-checking.c | 10 +- ...a-attribute-supported-attributes-list.test | 1 + clang/test/Sema/attr-counted-by.c | 64 + 20 files changed, 2877 insertions(+), 92 deletions(-) create mode 100644 clang/test/CodeGen/attr-counted-by.c create mode 100644 clang/test/Sema/attr-counted-by.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 7abc65b8734a..a18d36a16b1a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -208,6 +208,11 @@ C Language Changes - Enums will now be represented in TBAA metadata using their actual underlying integer type. Previously they were treated as chars, which meant they could alias with all other types. +- Clang now supports the C-only attribute ``counted_by``. When applied to a + struct's flexible array member, it points to the struct field that holds the + number of elements in the flexible array member. This information can improve + the results of the array bound sanitizer and the + ``__builtin_dynamic_object_size`` builtin. C23 Feature Support ^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h index 10dcbdb262d8..5b1038582bc6 100644 --- a/clang/include/clang/AST/DeclBase.h +++ b/clang/include/clang/AST/DeclBase.h @@ -19,6 +19,7 @@ #include "clang/AST/SelectorLocationsKind.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LLVM.h" +#include "clang/Basic/LangOptions.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/Specifiers.h" #include "llvm/ADT/ArrayRef.h" @@ -488,6 +489,15 @@ public: // Return true if this is a FileContext Decl. bool isFileContextDecl() const; + /// Whether it resembles a flexible array member. This is a static member + /// because we want to be able to call it with a nullptr. That allows us to + /// perform non-Decl specific checks based on the object's type and strict + /// flex array level. + static bool isFlexibleArrayMemberLike( + ASTContext &Context, const Decl *D, QualType Ty, + LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, + bool IgnoreTemplateOrMacroSubstitution); + ASTContext &getASTContext() const LLVM_READONLY; /// Helper to get the language options from the ASTContext. diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index d5eabaad4889..a03b0e44e15f 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -4372,3 +4372,21 @@ def CodeAlign: StmtAttr { static constexpr int MaximumAlignment = 4096; }]; } + +def CountedBy : InheritableAttr { + let Spellings = [Clang<"counted_by">]; + let Subjects = SubjectList<[Field]>; + let Args = [IdentifierArgument<"CountedByField">]; + let Documentation = [CountedByDocs]; + let LangOpts = [COnly]; + // FIXME: This is ugly. Let using a DeclArgument would be nice, but a Decl + // isn't yet available due to the fact that we're still parsing the + // structure. Maybe that code could be changed sometime in the future. + code AdditionalMembers = [{ + private: + SourceRange CountedByFieldLoc; + public: + SourceRange getCountedByFieldLoc() const { return CountedByFieldLoc; } + void setCountedByFieldLoc(SourceRange Loc) { CountedByFieldLoc = Loc; } + }]; +} diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 5416a0cbdd07..2e8d7752c975 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7749,3 +7749,81 @@ but do not pass them to the underlying coroutine or pass them by value. .. _`CRT`: https://clang.llvm.org/docs/AttributeReference.html#coro-return-type }]; } + +def CountedByDocs : Documentation { + let Category = DocCatField; + let Content = [{ +Clang supports the ``counted_by`` attribute on the flexible array member of a +structure in C. The argument for the attribute is the name of a field member +holding the count of elements in the flexible array. This information can be +used to improve the results of the array bound sanitizer and the +``__builtin_dynamic_object_size`` builtin. The ``count`` field member must be +within the same non-anonymous, enclosing struct as the flexible array member. + +This example specifies that the flexible array member ``array`` has the number +of elements allocated for it in ``count``: + +.. code-block:: c + + struct bar; + + struct foo { + size_t count; + char other; + struct bar *array[] __attribute__((counted_by(count))); + }; + +This establishes a relationship between ``array`` and ``count``. Specifically, +``array`` must have at least ``count`` number of elements available. It's the +user's responsibility to ensure that this relationship is maintained through +changes to the structure. + +In the following example, the allocated array erroneously has fewer elements +than what's specified by ``p->count``. This would result in an out-of-bounds +access not being detected. + +.. code-block:: c + + #define SIZE_INCR 42 + + struct foo *p; + + void foo_alloc(size_t count) { + p = malloc(MAX(sizeof(struct foo), + offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); + p->count = count + SIZE_INCR; + } + +The next example updates ``p->count``, but breaks the relationship requirement +that ``p->array`` must have at least ``p->count`` number of elements available: + +.. code-block:: c + + #define SIZE_INCR 42 + + struct foo *p; + + void foo_alloc(size_t count) { + p = malloc(MAX(sizeof(struct foo), + offsetof(struct foo, array[0]) + count * sizeof(struct bar *))); + p->count = count; + } + + void use_foo(int index, int val) { + p->count += SIZE_INCR + 1; /* 'count' is now larger than the number of elements of 'array'. */ + p->array[index] = val; /* The sanitizer can't properly check this access. */ + } + +In this example, an update to ``p->count`` maintains the relationship +requirement: + +.. code-block:: c + + void use_foo(int index, int val) { + if (p->count == 0) + return; + --p->count; + p->array[index] = val; + } + }]; +} diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 3884dca59e2f..1a79892e4003 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -6441,6 +6441,19 @@ def warn_superclass_variable_sized_type_not_at_end : Warning< "field %0 can overwrite instance variable %1 with variable sized type %2" " in superclass %3">, InGroup; +def err_flexible_array_count_not_in_same_struct : Error< + "'counted_by' field %0 isn't within the same struct as the flexible array">; +def err_counted_by_attr_not_on_flexible_array_member : Error< + "'counted_by' only applies to C99 flexible array members">; +def err_counted_by_attr_refers_to_flexible_array : Error< + "'counted_by' cannot refer to the flexible array %0">; +def err_counted_by_must_be_in_structure : Error< + "field %0 in 'counted_by' not inside structure">; +def err_flexible_array_counted_by_attr_field_not_integer : Error< + "field %0 in 'counted_by' must be a non-boolean integer type">; +def note_flexible_array_counted_by_attr_field : Note< + "field %0 declared here">; + let CategoryName = "ARC Semantic Issue" in { // ARC-mode diagnostics. diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index edaee4c4b66d..cf2d4fbe6d3b 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -4799,6 +4799,8 @@ public: bool CheckAlwaysInlineAttr(const Stmt *OrigSt, const Stmt *CurSt, const AttributeCommonInfo &A); + bool CheckCountedByAttr(Scope *Scope, const FieldDecl *FD); + /// Adjust the calling convention of a method to be the ABI default if it /// wasn't specified explicitly. This handles method types formed from /// function type typedefs and typename template arguments. @@ -5642,6 +5644,7 @@ public: CorrectionCandidateCallback &CCC, TemplateArgumentListInfo *ExplicitTemplateArgs = nullptr, ArrayRef Args = std::nullopt, + DeclContext *LookupCtx = nullptr, TypoExpr **Out = nullptr); DeclResult LookupIvarInObjCMethod(LookupResult &Lookup, Scope *S, diff --git a/clang/include/clang/Sema/TypoCorrection.h b/clang/include/clang/Sema/TypoCorrection.h index e0f8d152dbe5..09de164297e7 100644 --- a/clang/include/clang/Sema/TypoCorrection.h +++ b/clang/include/clang/Sema/TypoCorrection.h @@ -282,7 +282,7 @@ class CorrectionCandidateCallback { public: static const unsigned InvalidDistance = TypoCorrection::InvalidDistance; - explicit CorrectionCandidateCallback(IdentifierInfo *Typo = nullptr, + explicit CorrectionCandidateCallback(const IdentifierInfo *Typo = nullptr, NestedNameSpecifier *TypoNNS = nullptr) : Typo(Typo), TypoNNS(TypoNNS) {} @@ -319,7 +319,7 @@ public: /// this method. virtual std::unique_ptr clone() = 0; - void setTypoName(IdentifierInfo *II) { Typo = II; } + void setTypoName(const IdentifierInfo *II) { Typo = II; } void setTypoNNS(NestedNameSpecifier *NNS) { TypoNNS = NNS; } // Flags for context-dependent keywords. WantFunctionLikeCasts is only @@ -345,13 +345,13 @@ protected: candidate.getCorrectionSpecifier() == TypoNNS; } - IdentifierInfo *Typo; + const IdentifierInfo *Typo; NestedNameSpecifier *TypoNNS; }; class DefaultFilterCCC final : public CorrectionCandidateCallback { public: - explicit DefaultFilterCCC(IdentifierInfo *Typo = nullptr, + explicit DefaultFilterCCC(const IdentifierInfo *Typo = nullptr, NestedNameSpecifier *TypoNNS = nullptr) : CorrectionCandidateCallback(Typo, TypoNNS) {} @@ -365,6 +365,10 @@ public: template class DeclFilterCCC final : public CorrectionCandidateCallback { public: + explicit DeclFilterCCC(const IdentifierInfo *Typo = nullptr, + NestedNameSpecifier *TypoNNS = nullptr) + : CorrectionCandidateCallback(Typo, TypoNNS) {} + bool ValidateCandidate(const TypoCorrection &candidate) override { return candidate.getCorrectionDeclAs(); } diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 5e5570bb42a1..0540159f07e8 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -9030,6 +9030,10 @@ class AttrImporter { public: AttrImporter(ASTImporter &I) : Importer(I), NImporter(I) {} + // Useful for accessing the imported attribute. + template T *castAttrAs() { return cast(ToAttr); } + template const T *castAttrAs() const { return cast(ToAttr); } + // Create an "importer" for an attribute parameter. // Result of the 'value()' of that object is to be passed to the function // 'importAttr', in the order that is expected by the attribute class. @@ -9243,6 +9247,15 @@ Expected ASTImporter::Import(const Attr *FromAttr) { From->args_size()); break; } + case attr::CountedBy: { + AI.cloneAttr(FromAttr); + const auto *CBA = cast(FromAttr); + Expected SR = Import(CBA->getCountedByFieldLoc()).get(); + if (!SR) + return SR.takeError(); + AI.castAttrAs()->setCountedByFieldLoc(SR.get()); + break; + } default: { // The default branch works for attributes that have no arguments to import. diff --git a/clang/lib/AST/DeclBase.cpp b/clang/lib/AST/DeclBase.cpp index b1733c2d052a..8163f9bdaf8d 100644 --- a/clang/lib/AST/DeclBase.cpp +++ b/clang/lib/AST/DeclBase.cpp @@ -29,7 +29,6 @@ #include "clang/AST/Type.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LLVM.h" -#include "clang/Basic/LangOptions.h" #include "clang/Basic/Module.h" #include "clang/Basic/ObjCRuntime.h" #include "clang/Basic/PartialDiagnostic.h" @@ -411,6 +410,79 @@ bool Decl::isFileContextDecl() const { return DC && DC->isFileContext(); } +bool Decl::isFlexibleArrayMemberLike( + ASTContext &Ctx, const Decl *D, QualType Ty, + LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, + bool IgnoreTemplateOrMacroSubstitution) { + // For compatibility with existing code, we treat arrays of length 0 or + // 1 as flexible array members. + const auto *CAT = Ctx.getAsConstantArrayType(Ty); + if (CAT) { + using FAMKind = LangOptions::StrictFlexArraysLevelKind; + + llvm::APInt Size = CAT->getSize(); + if (StrictFlexArraysLevel == FAMKind::IncompleteOnly) + return false; + + // GCC extension, only allowed to represent a FAM. + if (Size.isZero()) + return true; + + if (StrictFlexArraysLevel == FAMKind::ZeroOrIncomplete && Size.uge(1)) + return false; + + if (StrictFlexArraysLevel == FAMKind::OneZeroOrIncomplete && Size.uge(2)) + return false; + } else if (!Ctx.getAsIncompleteArrayType(Ty)) { + return false; + } + + if (const auto *OID = dyn_cast_if_present(D)) + return OID->getNextIvar() == nullptr; + + const auto *FD = dyn_cast_if_present(D); + if (!FD) + return false; + + if (CAT) { + // GCC treats an array memeber of a union as an FAM if the size is one or + // zero. + llvm::APInt Size = CAT->getSize(); + if (FD->getParent()->isUnion() && (Size.isZero() || Size.isOne())) + return true; + } + + // Don't consider sizes resulting from macro expansions or template argument + // substitution to form C89 tail-padded arrays. + if (IgnoreTemplateOrMacroSubstitution) { + TypeSourceInfo *TInfo = FD->getTypeSourceInfo(); + while (TInfo) { + TypeLoc TL = TInfo->getTypeLoc(); + + // Look through typedefs. + if (TypedefTypeLoc TTL = TL.getAsAdjusted()) { + const TypedefNameDecl *TDL = TTL.getTypedefNameDecl(); + TInfo = TDL->getTypeSourceInfo(); + continue; + } + + if (auto CTL = TL.getAs()) { + if (const Expr *SizeExpr = + dyn_cast_if_present(CTL.getSizeExpr()); + !SizeExpr || SizeExpr->getExprLoc().isMacroID()) + return false; + } + + break; + } + } + + // Test that the field is the last in the structure. + RecordDecl::field_iterator FI( + DeclContext::decl_iterator(const_cast(FD))); + return ++FI == FD->getParent()->field_end(); +} + TranslationUnitDecl *Decl::getTranslationUnitDecl() { if (auto *TUD = dyn_cast(this)) return TUD; diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp index a90f92d07f86..b125fc676da8 100644 --- a/clang/lib/AST/Expr.cpp +++ b/clang/lib/AST/Expr.cpp @@ -205,85 +205,22 @@ bool Expr::isKnownToHaveBooleanValue(bool Semantic) const { } bool Expr::isFlexibleArrayMemberLike( - ASTContext &Context, + ASTContext &Ctx, LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel, bool IgnoreTemplateOrMacroSubstitution) const { - - // For compatibility with existing code, we treat arrays of length 0 or - // 1 as flexible array members. - const auto *CAT = Context.getAsConstantArrayType(getType()); - if (CAT) { - llvm::APInt Size = CAT->getSize(); - - using FAMKind = LangOptions::StrictFlexArraysLevelKind; - - if (StrictFlexArraysLevel == FAMKind::IncompleteOnly) - return false; - - // GCC extension, only allowed to represent a FAM. - if (Size == 0) - return true; - - if (StrictFlexArraysLevel == FAMKind::ZeroOrIncomplete && Size.uge(1)) - return false; - - if (StrictFlexArraysLevel == FAMKind::OneZeroOrIncomplete && Size.uge(2)) - return false; - } else if (!Context.getAsIncompleteArrayType(getType())) - return false; - const Expr *E = IgnoreParens(); + const Decl *D = nullptr; - const NamedDecl *ND = nullptr; - if (const auto *DRE = dyn_cast(E)) - ND = DRE->getDecl(); - else if (const auto *ME = dyn_cast(E)) - ND = ME->getMemberDecl(); + if (const auto *ME = dyn_cast(E)) + D = ME->getMemberDecl(); + else if (const auto *DRE = dyn_cast(E)) + D = DRE->getDecl(); else if (const auto *IRE = dyn_cast(E)) - return IRE->getDecl()->getNextIvar() == nullptr; - - if (!ND) - return false; + D = IRE->getDecl(); - // A flexible array member must be the last member in the class. - // FIXME: If the base type of the member expr is not FD->getParent(), - // this should not be treated as a flexible array member access. - if (const auto *FD = dyn_cast(ND)) { - // GCC treats an array memeber of a union as an FAM if the size is one or - // zero. - if (CAT) { - llvm::APInt Size = CAT->getSize(); - if (FD->getParent()->isUnion() && (Size.isZero() || Size.isOne())) - return true; - } - - // Don't consider sizes resulting from macro expansions or template argument - // substitution to form C89 tail-padded arrays. - if (IgnoreTemplateOrMacroSubstitution) { - TypeSourceInfo *TInfo = FD->getTypeSourceInfo(); - while (TInfo) { - TypeLoc TL = TInfo->getTypeLoc(); - // Look through typedefs. - if (TypedefTypeLoc TTL = TL.getAsAdjusted()) { - const TypedefNameDecl *TDL = TTL.getTypedefNameDecl(); - TInfo = TDL->getTypeSourceInfo(); - continue; - } - if (ConstantArrayTypeLoc CTL = TL.getAs()) { - const Expr *SizeExpr = dyn_cast(CTL.getSizeExpr()); - if (!SizeExpr || SizeExpr->getExprLoc().isMacroID()) - return false; - } - break; - } - } - - RecordDecl::field_iterator FI( - DeclContext::decl_iterator(const_cast(FD))); - return ++FI == FD->getParent()->field_end(); - } - - return false; + return Decl::isFlexibleArrayMemberLike(Ctx, D, E->getType(), + StrictFlexArraysLevel, + IgnoreTemplateOrMacroSubstitution); } const ValueDecl * diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 1ed35befe136..998fcc3af581 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -25,6 +25,7 @@ #include "clang/AST/Attr.h" #include "clang/AST/Decl.h" #include "clang/AST/OSLog.h" +#include "clang/AST/OperationKinds.h" #include "clang/Basic/TargetBuiltins.h" #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" @@ -818,6 +819,238 @@ CodeGenFunction::evaluateOrEmitBuiltinObjectSize(const Expr *E, unsigned Type, return ConstantInt::get(ResType, ObjectSize, /*isSigned=*/true); } +const FieldDecl *CodeGenFunction::FindFlexibleArrayMemberField( + ASTContext &Ctx, const RecordDecl *RD, StringRef Name, uint64_t &Offset) { + const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = + getLangOpts().getStrictFlexArraysLevel(); + unsigned FieldNo = 0; + bool IsUnion = RD->isUnion(); + + for (const Decl *D : RD->decls()) { + if (const auto *Field = dyn_cast(D); + Field && (Name.empty() || Field->getNameAsString() == Name) && + Decl::isFlexibleArrayMemberLike( + Ctx, Field, Field->getType(), StrictFlexArraysLevel, + /*IgnoreTemplateOrMacroSubstitution=*/true)) { + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); + Offset += Layout.getFieldOffset(FieldNo); + return Field; + } + + if (const auto *Record = dyn_cast(D)) + if (const FieldDecl *Field = + FindFlexibleArrayMemberField(Ctx, Record, Name, Offset)) { + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); + Offset += Layout.getFieldOffset(FieldNo); + return Field; + } + + if (!IsUnion && isa(D)) + ++FieldNo; + } + + return nullptr; +} + +static unsigned CountCountedByAttrs(const RecordDecl *RD) { + unsigned Num = 0; + + for (const Decl *D : RD->decls()) { + if (const auto *FD = dyn_cast(D); + FD && FD->hasAttr()) { + return ++Num; + } + + if (const auto *Rec = dyn_cast(D)) + Num += CountCountedByAttrs(Rec); + } + + return Num; +} + +llvm::Value * +CodeGenFunction::emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, + llvm::IntegerType *ResType) { + // The code generated here calculates the size of a struct with a flexible + // array member that uses the counted_by attribute. There are two instances + // we handle: + // + // struct s { + // unsigned long flags; + // int count; + // int array[] __attribute__((counted_by(count))); + // } + // + // 1) bdos of the flexible array itself: + // + // __builtin_dynamic_object_size(p->array, 1) == + // p->count * sizeof(*p->array) + // + // 2) bdos of a pointer into the flexible array: + // + // __builtin_dynamic_object_size(&p->array[42], 1) == + // (p->count - 42) * sizeof(*p->array) + // + // 2) bdos of the whole struct, including the flexible array: + // + // __builtin_dynamic_object_size(p, 1) == + // max(sizeof(struct s), + // offsetof(struct s, array) + p->count * sizeof(*p->array)) + // + ASTContext &Ctx = getContext(); + const Expr *Base = E->IgnoreParenImpCasts(); + const Expr *Idx = nullptr; + + if (const auto *UO = dyn_cast(Base); + UO && UO->getOpcode() == UO_AddrOf) { + Expr *SubExpr = UO->getSubExpr()->IgnoreParenImpCasts(); + if (const auto *ASE = dyn_cast(SubExpr)) { + Base = ASE->getBase()->IgnoreParenImpCasts(); + Idx = ASE->getIdx()->IgnoreParenImpCasts(); + + if (const auto *IL = dyn_cast(Idx)) { + int64_t Val = IL->getValue().getSExtValue(); + if (Val < 0) + return getDefaultBuiltinObjectSizeResult(Type, ResType); + + if (Val == 0) + // The index is 0, so we don't need to take it into account. + Idx = nullptr; + } + } else { + // Potential pointer to another element in the struct. + Base = SubExpr; + } + } + + // Get the flexible array member Decl. + const RecordDecl *OuterRD = nullptr; + std::string FAMName; + if (const auto *ME = dyn_cast(Base)) { + // Check if \p Base is referencing the FAM itself. + const ValueDecl *VD = ME->getMemberDecl(); + OuterRD = VD->getDeclContext()->getOuterLexicalRecordContext(); + FAMName = VD->getNameAsString(); + } else if (const auto *DRE = dyn_cast(Base)) { + // Check if we're pointing to the whole struct. + QualType Ty = DRE->getDecl()->getType(); + if (Ty->isPointerType()) + Ty = Ty->getPointeeType(); + OuterRD = Ty->getAsRecordDecl(); + + // If we have a situation like this: + // + // struct union_of_fams { + // int flags; + // union { + // signed char normal_field; + // struct { + // int count1; + // int arr1[] __counted_by(count1); + // }; + // struct { + // signed char count2; + // int arr2[] __counted_by(count2); + // }; + // }; + // }; + // + // We don't konw which 'count' to use in this scenario: + // + // size_t get_size(struct union_of_fams *p) { + // return __builtin_dynamic_object_size(p, 1); + // } + // + // Instead of calculating a wrong number, we give up. + if (OuterRD && CountCountedByAttrs(OuterRD) > 1) + return nullptr; + } + + if (!OuterRD) + return nullptr; + + uint64_t Offset = 0; + const FieldDecl *FAMDecl = + FindFlexibleArrayMemberField(Ctx, OuterRD, FAMName, Offset); + Offset = Ctx.toCharUnitsFromBits(Offset).getQuantity(); + + if (!FAMDecl || !FAMDecl->hasAttr()) + // No flexible array member found or it doesn't have the "counted_by" + // attribute. + return nullptr; + + const FieldDecl *CountedByFD = FindCountedByField(FAMDecl); + if (!CountedByFD) + // Can't find the field referenced by the "counted_by" attribute. + return nullptr; + + // Build a load of the counted_by field. + bool IsSigned = CountedByFD->getType()->isSignedIntegerType(); + Value *CountedByInst = EmitCountedByFieldExpr(Base, FAMDecl, CountedByFD); + if (!CountedByInst) + return getDefaultBuiltinObjectSizeResult(Type, ResType); + + CountedByInst = Builder.CreateIntCast(CountedByInst, ResType, IsSigned); + + // Build a load of the index and subtract it from the count. + Value *IdxInst = nullptr; + if (Idx) { + if (Idx->HasSideEffects(getContext())) + // We can't have side-effects. + return getDefaultBuiltinObjectSizeResult(Type, ResType); + + bool IdxSigned = Idx->getType()->isSignedIntegerType(); + IdxInst = EmitAnyExprToTemp(Idx).getScalarVal(); + IdxInst = Builder.CreateIntCast(IdxInst, ResType, IdxSigned); + + // We go ahead with the calculation here. If the index turns out to be + // negative, we'll catch it at the end. + CountedByInst = + Builder.CreateSub(CountedByInst, IdxInst, "", !IsSigned, IsSigned); + } + + // Calculate how large the flexible array member is in bytes. + const ArrayType *ArrayTy = Ctx.getAsArrayType(FAMDecl->getType()); + CharUnits Size = Ctx.getTypeSizeInChars(ArrayTy->getElementType()); + llvm::Constant *ElemSize = + llvm::ConstantInt::get(ResType, Size.getQuantity(), IsSigned); + Value *FAMSize = + Builder.CreateMul(CountedByInst, ElemSize, "", !IsSigned, IsSigned); + FAMSize = Builder.CreateIntCast(FAMSize, ResType, IsSigned); + Value *Res = FAMSize; + + if (const auto *DRE = dyn_cast(Base)) { + // The whole struct is specificed in the __bdos. + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(OuterRD); + + // Get the offset of the FAM. + llvm::Constant *FAMOffset = ConstantInt::get(ResType, Offset, IsSigned); + Value *OffsetAndFAMSize = + Builder.CreateAdd(FAMOffset, Res, "", !IsSigned, IsSigned); + + // Get the full size of the struct. + llvm::Constant *SizeofStruct = + ConstantInt::get(ResType, Layout.getSize().getQuantity(), IsSigned); + + // max(sizeof(struct s), + // offsetof(struct s, array) + p->count * sizeof(*p->array)) + Res = IsSigned + ? Builder.CreateBinaryIntrinsic(llvm::Intrinsic::smax, + OffsetAndFAMSize, SizeofStruct) + : Builder.CreateBinaryIntrinsic(llvm::Intrinsic::umax, + OffsetAndFAMSize, SizeofStruct); + } + + // A negative \p IdxInst or \p CountedByInst means that the index lands + // outside of the flexible array member. If that's the case, we want to + // return 0. + Value *Cmp = Builder.CreateIsNotNeg(CountedByInst); + if (IdxInst) + Cmp = Builder.CreateAnd(Builder.CreateIsNotNeg(IdxInst), Cmp); + + return Builder.CreateSelect(Cmp, Res, ConstantInt::get(ResType, 0, IsSigned)); +} + /// Returns a Value corresponding to the size of the given expression. /// This Value may be either of the following: /// - A llvm::Argument (if E is a param with the pass_object_size attribute on @@ -850,6 +1083,13 @@ CodeGenFunction::emitBuiltinObjectSize(const Expr *E, unsigned Type, } } + if (IsDynamic) { + // Emit special code for a flexible array member with the "counted_by" + // attribute. + if (Value *V = emitFlexibleArrayMemberSize(E, Type, ResType)) + return V; + } + // LLVM can't handle Type=3 appropriately, and __builtin_object_size shouldn't // evaluate E for side-effects. In either case, we shouldn't lower to // @llvm.objectsize. diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 3f277725d9e7..d12e85b48d0b 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -26,10 +26,12 @@ #include "clang/AST/Attr.h" #include "clang/AST/DeclObjC.h" #include "clang/AST/NSAPI.h" +#include "clang/AST/StmtVisitor.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/CodeGenOptions.h" #include "clang/Basic/SourceManager.h" #include "llvm/ADT/Hashing.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Intrinsics.h" @@ -925,16 +927,21 @@ static llvm::Value *getArrayIndexingBound(CodeGenFunction &CGF, if (CE->getCastKind() == CK_ArrayToPointerDecay && !CE->getSubExpr()->isFlexibleArrayMemberLike(CGF.getContext(), StrictFlexArraysLevel)) { + CodeGenFunction::SanitizerScope SanScope(&CGF); + IndexedType = CE->getSubExpr()->getType(); const ArrayType *AT = IndexedType->castAsArrayTypeUnsafe(); if (const auto *CAT = dyn_cast(AT)) return CGF.Builder.getInt(CAT->getSize()); - else if (const auto *VAT = dyn_cast(AT)) + + if (const auto *VAT = dyn_cast(AT)) return CGF.getVLASize(VAT).NumElts; // Ignore pass_object_size here. It's not applicable on decayed pointers. } } + CodeGenFunction::SanitizerScope SanScope(&CGF); + QualType EltTy{Base->getType()->getPointeeOrArrayElementType(), 0}; if (llvm::Value *POS = CGF.LoadPassedObjectSize(Base, EltTy)) { IndexedType = Base->getType(); @@ -944,22 +951,248 @@ static llvm::Value *getArrayIndexingBound(CodeGenFunction &CGF, return nullptr; } +namespace { + +/// \p StructAccessBase returns the base \p Expr of a field access. It returns +/// either a \p DeclRefExpr, representing the base pointer to the struct, i.e.: +/// +/// p in p-> a.b.c +/// +/// or a \p MemberExpr, if the \p MemberExpr has the \p RecordDecl we're +/// looking for: +/// +/// struct s { +/// struct s *ptr; +/// int count; +/// char array[] __attribute__((counted_by(count))); +/// }; +/// +/// If we have an expression like \p p->ptr->array[index], we want the +/// \p MemberExpr for \p p->ptr instead of \p p. +class StructAccessBase + : public ConstStmtVisitor { + const RecordDecl *ExpectedRD; + + bool IsExpectedRecordDecl(const Expr *E) const { + QualType Ty = E->getType(); + if (Ty->isPointerType()) + Ty = Ty->getPointeeType(); + return ExpectedRD == Ty->getAsRecordDecl(); + } + +public: + StructAccessBase(const RecordDecl *ExpectedRD) : ExpectedRD(ExpectedRD) {} + + //===--------------------------------------------------------------------===// + // Visitor Methods + //===--------------------------------------------------------------------===// + + // NOTE: If we build C++ support for counted_by, then we'll have to handle + // horrors like this: + // + // struct S { + // int x, y; + // int blah[] __attribute__((counted_by(x))); + // } s; + // + // int foo(int index, int val) { + // int (S::*IHatePMDs)[] = &S::blah; + // (s.*IHatePMDs)[index] = val; + // } + + const Expr *Visit(const Expr *E) { + return ConstStmtVisitor::Visit(E); + } + + const Expr *VisitStmt(const Stmt *S) { return nullptr; } + + // These are the types we expect to return (in order of most to least + // likely): + // + // 1. DeclRefExpr - This is the expression for the base of the structure. + // It's exactly what we want to build an access to the \p counted_by + // field. + // 2. MemberExpr - This is the expression that has the same \p RecordDecl + // as the flexble array member's lexical enclosing \p RecordDecl. This + // allows us to catch things like: "p->p->array" + // 3. CompoundLiteralExpr - This is for people who create something + // heretical like (struct foo has a flexible array member): + // + // (struct foo){ 1, 2 }.blah[idx]; + const Expr *VisitDeclRefExpr(const DeclRefExpr *E) { + return IsExpectedRecordDecl(E) ? E : nullptr; + } + const Expr *VisitMemberExpr(const MemberExpr *E) { + if (IsExpectedRecordDecl(E) && E->isArrow()) + return E; + const Expr *Res = Visit(E->getBase()); + return !Res && IsExpectedRecordDecl(E) ? E : Res; + } + const Expr *VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) { + return IsExpectedRecordDecl(E) ? E : nullptr; + } + const Expr *VisitCallExpr(const CallExpr *E) { + return IsExpectedRecordDecl(E) ? E : nullptr; + } + + const Expr *VisitArraySubscriptExpr(const ArraySubscriptExpr *E) { + if (IsExpectedRecordDecl(E)) + return E; + return Visit(E->getBase()); + } + const Expr *VisitCastExpr(const CastExpr *E) { + return Visit(E->getSubExpr()); + } + const Expr *VisitParenExpr(const ParenExpr *E) { + return Visit(E->getSubExpr()); + } + const Expr *VisitUnaryAddrOf(const UnaryOperator *E) { + return Visit(E->getSubExpr()); + } + const Expr *VisitUnaryDeref(const UnaryOperator *E) { + return Visit(E->getSubExpr()); + } +}; + +} // end anonymous namespace + +using RecIndicesTy = + SmallVector, 8>; + +static bool getGEPIndicesToField(CodeGenFunction &CGF, const RecordDecl *RD, + const FieldDecl *FD, RecIndicesTy &Indices) { + const CGRecordLayout &Layout = CGF.CGM.getTypes().getCGRecordLayout(RD); + int64_t FieldNo = -1; + for (const Decl *D : RD->decls()) { + if (const auto *Field = dyn_cast(D)) { + FieldNo = Layout.getLLVMFieldNo(Field); + if (FD == Field) { + Indices.emplace_back(std::make_pair(RD, CGF.Builder.getInt32(FieldNo))); + return true; + } + } + + if (const auto *Record = dyn_cast(D)) { + ++FieldNo; + if (getGEPIndicesToField(CGF, Record, FD, Indices)) { + if (RD->isUnion()) + FieldNo = 0; + Indices.emplace_back(std::make_pair(RD, CGF.Builder.getInt32(FieldNo))); + return true; + } + } + } + + return false; +} + +/// This method is typically called in contexts where we can't generate +/// side-effects, like in __builtin_dynamic_object_size. When finding +/// expressions, only choose those that have either already been emitted or can +/// be loaded without side-effects. +/// +/// - \p FAMDecl: the \p Decl for the flexible array member. It may not be +/// within the top-level struct. +/// - \p CountDecl: must be within the same non-anonymous struct as \p FAMDecl. +llvm::Value *CodeGenFunction::EmitCountedByFieldExpr( + const Expr *Base, const FieldDecl *FAMDecl, const FieldDecl *CountDecl) { + const RecordDecl *RD = CountDecl->getParent()->getOuterLexicalRecordContext(); + + // Find the base struct expr (i.e. p in p->a.b.c.d). + const Expr *StructBase = StructAccessBase(RD).Visit(Base); + if (!StructBase || StructBase->HasSideEffects(getContext())) + return nullptr; + + llvm::Value *Res = nullptr; + if (const auto *DRE = dyn_cast(StructBase)) { + Res = EmitDeclRefLValue(DRE).getPointer(*this); + Res = Builder.CreateAlignedLoad(ConvertType(DRE->getType()), Res, + getPointerAlign(), "dre.load"); + } else if (const MemberExpr *ME = dyn_cast(StructBase)) { + LValue LV = EmitMemberExpr(ME); + Address Addr = LV.getAddress(*this); + Res = Addr.getPointer(); + } else if (StructBase->getType()->isPointerType()) { + LValueBaseInfo BaseInfo; + TBAAAccessInfo TBAAInfo; + Address Addr = EmitPointerWithAlignment(StructBase, &BaseInfo, &TBAAInfo); + Res = Addr.getPointer(); + } else { + return nullptr; + } + + llvm::Value *Zero = Builder.getInt32(0); + RecIndicesTy Indices; + + getGEPIndicesToField(*this, RD, CountDecl, Indices); + + for (auto I = Indices.rbegin(), E = Indices.rend(); I != E; ++I) + Res = Builder.CreateInBoundsGEP( + ConvertType(QualType(I->first->getTypeForDecl(), 0)), Res, + {Zero, I->second}, "..counted_by.gep"); + + return Builder.CreateAlignedLoad(ConvertType(CountDecl->getType()), Res, + getIntAlign(), "..counted_by.load"); +} + +const FieldDecl *CodeGenFunction::FindCountedByField(const FieldDecl *FD) { + if (!FD || !FD->hasAttr()) + return nullptr; + + const auto *CBA = FD->getAttr(); + if (!CBA) + return nullptr; + + auto GetNonAnonStructOrUnion = + [](const RecordDecl *RD) -> const RecordDecl * { + while (RD && RD->isAnonymousStructOrUnion()) { + const auto *R = dyn_cast(RD->getDeclContext()); + if (!R) + return nullptr; + RD = R; + } + return RD; + }; + const RecordDecl *EnclosingRD = GetNonAnonStructOrUnion(FD->getParent()); + if (!EnclosingRD) + return nullptr; + + DeclarationName DName(CBA->getCountedByField()); + DeclContext::lookup_result Lookup = EnclosingRD->lookup(DName); + + if (Lookup.empty()) + return nullptr; + + const NamedDecl *ND = Lookup.front(); + if (const auto *IFD = dyn_cast(ND)) + ND = IFD->getAnonField(); + + return dyn_cast(ND); +} + void CodeGenFunction::EmitBoundsCheck(const Expr *E, const Expr *Base, llvm::Value *Index, QualType IndexType, bool Accessed) { assert(SanOpts.has(SanitizerKind::ArrayBounds) && "should not be called unless adding bounds checks"); - SanitizerScope SanScope(this); - const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = - getLangOpts().getStrictFlexArraysLevel(); - + getLangOpts().getStrictFlexArraysLevel(); QualType IndexedType; llvm::Value *Bound = getArrayIndexingBound(*this, Base, IndexedType, StrictFlexArraysLevel); + + EmitBoundsCheckImpl(E, Bound, Index, IndexType, IndexedType, Accessed); +} + +void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, + llvm::Value *Index, + QualType IndexType, + QualType IndexedType, bool Accessed) { if (!Bound) return; + SanitizerScope SanScope(this); + bool IndexSigned = IndexType->isSignedIntegerOrEnumerationType(); llvm::Value *IndexVal = Builder.CreateIntCast(Index, SizeTy, IndexSigned); llvm::Value *BoundVal = Builder.CreateIntCast(Bound, SizeTy, false); @@ -975,7 +1208,6 @@ void CodeGenFunction::EmitBoundsCheck(const Expr *E, const Expr *Base, SanitizerHandler::OutOfBounds, StaticData, Index); } - CodeGenFunction::ComplexPairTy CodeGenFunction:: EmitComplexPrePostIncDec(const UnaryOperator *E, LValue LV, bool isInc, bool isPre) { @@ -3823,6 +4055,61 @@ static Address emitArraySubscriptGEP(CodeGenFunction &CGF, Address addr, return Address(eltPtr, CGF.ConvertTypeForMem(eltType), eltAlign); } +/// The offset of a field from the beginning of the record. +static bool getFieldOffsetInBits(CodeGenFunction &CGF, const RecordDecl *RD, + const FieldDecl *FD, int64_t &Offset) { + ASTContext &Ctx = CGF.getContext(); + const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); + unsigned FieldNo = 0; + + for (const Decl *D : RD->decls()) { + if (const auto *Record = dyn_cast(D)) + if (getFieldOffsetInBits(CGF, Record, FD, Offset)) { + Offset += Layout.getFieldOffset(FieldNo); + return true; + } + + if (const auto *Field = dyn_cast(D)) + if (FD == Field) { + Offset += Layout.getFieldOffset(FieldNo); + return true; + } + + if (isa(D)) + ++FieldNo; + } + + return false; +} + +/// Returns the relative offset difference between \p FD1 and \p FD2. +/// \code +/// offsetof(struct foo, FD1) - offsetof(struct foo, FD2) +/// \endcode +/// Both fields must be within the same struct. +static std::optional getOffsetDifferenceInBits(CodeGenFunction &CGF, + const FieldDecl *FD1, + const FieldDecl *FD2) { + const RecordDecl *FD1OuterRec = + FD1->getParent()->getOuterLexicalRecordContext(); + const RecordDecl *FD2OuterRec = + FD2->getParent()->getOuterLexicalRecordContext(); + + if (FD1OuterRec != FD2OuterRec) + // Fields must be within the same RecordDecl. + return std::optional(); + + int64_t FD1Offset = 0; + if (!getFieldOffsetInBits(CGF, FD1OuterRec, FD1, FD1Offset)) + return std::optional(); + + int64_t FD2Offset = 0; + if (!getFieldOffsetInBits(CGF, FD2OuterRec, FD2, FD2Offset)) + return std::optional(); + + return std::make_optional(FD1Offset - FD2Offset); +} + LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E, bool Accessed) { // The index must always be an integer, which is not an aggregate. Emit it @@ -3950,6 +4237,47 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const ArraySubscriptExpr *E, ArrayLV = EmitLValue(Array); auto *Idx = EmitIdxAfterBase(/*Promote*/true); + if (SanOpts.has(SanitizerKind::ArrayBounds)) { + // If the array being accessed has a "counted_by" attribute, generate + // bounds checking code. The "count" field is at the top level of the + // struct or in an anonymous struct, that's also at the top level. Future + // expansions may allow the "count" to reside at any place in the struct, + // but the value of "counted_by" will be a "simple" path to the count, + // i.e. "a.b.count", so we shouldn't need the full force of EmitLValue or + // similar to emit the correct GEP. + const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = + getLangOpts().getStrictFlexArraysLevel(); + + if (const auto *ME = dyn_cast(Array); + ME && + ME->isFlexibleArrayMemberLike(getContext(), StrictFlexArraysLevel) && + ME->getMemberDecl()->hasAttr()) { + const FieldDecl *FAMDecl = dyn_cast(ME->getMemberDecl()); + if (const FieldDecl *CountFD = FindCountedByField(FAMDecl)) { + if (std::optional Diff = + getOffsetDifferenceInBits(*this, CountFD, FAMDecl)) { + CharUnits OffsetDiff = CGM.getContext().toCharUnitsFromBits(*Diff); + + // Create a GEP with a byte offset between the FAM and count and + // use that to load the count value. + Addr = Builder.CreatePointerBitCastOrAddrSpaceCast( + ArrayLV.getAddress(*this), Int8PtrTy, Int8Ty); + + llvm::Type *CountTy = ConvertType(CountFD->getType()); + llvm::Value *Res = Builder.CreateInBoundsGEP( + Int8Ty, Addr.getPointer(), + Builder.getInt32(OffsetDiff.getQuantity()), ".counted_by.gep"); + Res = Builder.CreateAlignedLoad(CountTy, Res, getIntAlign(), + ".counted_by.load"); + + // Now emit the bounds checking. + EmitBoundsCheckImpl(E, Res, Idx, E->getIdx()->getType(), + Array->getType(), Accessed); + } + } + } + } + // Propagate the alignment from the array itself to the result. QualType arrayType = Array->getType(); Addr = emitArraySubscriptGEP( diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 07c7678df87e..143ad64e8816 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3073,6 +3073,25 @@ public: /// this expression is used as an lvalue, for instance in "&Arr[Idx]". void EmitBoundsCheck(const Expr *E, const Expr *Base, llvm::Value *Index, QualType IndexType, bool Accessed); + void EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, + llvm::Value *Index, QualType IndexType, + QualType IndexedType, bool Accessed); + + // Find a struct's flexible array member. It may be embedded inside multiple + // sub-structs, but must still be the last field. + const FieldDecl *FindFlexibleArrayMemberField(ASTContext &Ctx, + const RecordDecl *RD, + StringRef Name, + uint64_t &Offset); + + /// Find the FieldDecl specified in a FAM's "counted_by" attribute. Returns + /// \p nullptr if either the attribute or the field doesn't exist. + const FieldDecl *FindCountedByField(const FieldDecl *FD); + + /// Build an expression accessing the "counted_by" field. + llvm::Value *EmitCountedByFieldExpr(const Expr *Base, + const FieldDecl *FAMDecl, + const FieldDecl *CountDecl); llvm::Value *EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, bool isInc, bool isPre); @@ -4873,6 +4892,9 @@ private: llvm::Value *EmittedE, bool IsDynamic); + llvm::Value *emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, + llvm::IntegerType *ResType); + void emitZeroOrPatternForAutoVarInit(QualType type, const VarDecl &D, Address Loc); diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 8e46c4984d93..e92fd104d78e 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -2315,6 +2315,12 @@ void Sema::ActOnPopScope(SourceLocation Loc, Scope *S) { } ShadowingDecls.erase(ShadowI); } + + if (!getLangOpts().CPlusPlus && S->isClassScope()) { + if (auto *FD = dyn_cast(TmpD); + FD && FD->hasAttr()) + CheckCountedByAttr(S, FD); + } } llvm::sort(DeclDiags, diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index d059b406ef86..1a58cfd8e417 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -8460,6 +8460,135 @@ static void handleZeroCallUsedRegsAttr(Sema &S, Decl *D, const ParsedAttr &AL) { D->addAttr(ZeroCallUsedRegsAttr::Create(S.Context, Kind, AL)); } +static void handleCountedByAttr(Sema &S, Decl *D, const ParsedAttr &AL) { + if (!AL.isArgIdent(0)) { + S.Diag(AL.getLoc(), diag::err_attribute_argument_type) + << AL << AANT_ArgumentIdentifier; + return; + } + + IdentifierLoc *IL = AL.getArgAsIdent(0); + CountedByAttr *CBA = + ::new (S.Context) CountedByAttr(S.Context, AL, IL->Ident); + CBA->setCountedByFieldLoc(IL->Loc); + D->addAttr(CBA); +} + +static const FieldDecl * +FindFieldInTopLevelOrAnonymousStruct(const RecordDecl *RD, + const IdentifierInfo *FieldName) { + for (const Decl *D : RD->decls()) { + if (const auto *FD = dyn_cast(D)) + if (FD->getName() == FieldName->getName()) + return FD; + + if (const auto *R = dyn_cast(D)) + if (const FieldDecl *FD = + FindFieldInTopLevelOrAnonymousStruct(R, FieldName)) + return FD; + } + + return nullptr; +} + +bool Sema::CheckCountedByAttr(Scope *S, const FieldDecl *FD) { + LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = + LangOptions::StrictFlexArraysLevelKind::IncompleteOnly; + if (!Decl::isFlexibleArrayMemberLike(Context, FD, FD->getType(), + StrictFlexArraysLevel, true)) { + // The "counted_by" attribute must be on a flexible array member. + SourceRange SR = FD->getLocation(); + Diag(SR.getBegin(), diag::err_counted_by_attr_not_on_flexible_array_member) + << SR; + return true; + } + + const auto *CBA = FD->getAttr(); + const IdentifierInfo *FieldName = CBA->getCountedByField(); + + auto GetNonAnonStructOrUnion = [](const RecordDecl *RD) { + while (RD && !RD->getDeclName()) + if (const auto *R = dyn_cast(RD->getDeclContext())) + RD = R; + else + break; + + return RD; + }; + + const RecordDecl *EnclosingRD = GetNonAnonStructOrUnion(FD->getParent()); + const FieldDecl *CountFD = + FindFieldInTopLevelOrAnonymousStruct(EnclosingRD, FieldName); + + if (!CountFD) { + DeclarationNameInfo NameInfo(FieldName, + CBA->getCountedByFieldLoc().getBegin()); + LookupResult MemResult(*this, NameInfo, Sema::LookupMemberName); + LookupName(MemResult, S); + + if (!MemResult.empty()) { + SourceRange SR = CBA->getCountedByFieldLoc(); + Diag(SR.getBegin(), diag::err_flexible_array_count_not_in_same_struct) + << CBA->getCountedByField() << SR; + + if (auto *ND = MemResult.getAsSingle()) { + SR = ND->getLocation(); + Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) + << ND << SR; + } + + return true; + } else { + // The "counted_by" field needs to exist in the struct. + LookupResult OrdResult(*this, NameInfo, Sema::LookupOrdinaryName); + LookupName(OrdResult, S); + + if (!OrdResult.empty()) { + SourceRange SR = FD->getLocation(); + Diag(SR.getBegin(), diag::err_counted_by_must_be_in_structure) + << FieldName << SR; + + if (auto *ND = OrdResult.getAsSingle()) { + SR = ND->getLocation(); + Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) + << ND << SR; + } + + return true; + } + } + + CXXScopeSpec SS; + DeclFilterCCC Filter(FieldName); + return DiagnoseEmptyLookup(S, SS, MemResult, Filter, nullptr, std::nullopt, + const_cast(FD->getDeclContext())); + } + + if (CountFD->hasAttr()) { + // The "counted_by" field can't point to the flexible array member. + SourceRange SR = CBA->getCountedByFieldLoc(); + Diag(SR.getBegin(), diag::err_counted_by_attr_refers_to_flexible_array) + << CBA->getCountedByField() << SR; + return true; + } + + if (!CountFD->getType()->isIntegerType() || + CountFD->getType()->isBooleanType()) { + // The "counted_by" field must have an integer type. + SourceRange SR = CBA->getCountedByFieldLoc(); + Diag(SR.getBegin(), + diag::err_flexible_array_counted_by_attr_field_not_integer) + << CBA->getCountedByField() << SR; + + SR = CountFD->getLocation(); + Diag(SR.getBegin(), diag::note_flexible_array_counted_by_attr_field) + << CountFD << SR; + return true; + } + + return false; +} + static void handleFunctionReturnThunksAttr(Sema &S, Decl *D, const ParsedAttr &AL) { StringRef KindStr; @@ -9420,6 +9549,10 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, handleAvailableOnlyInDefaultEvalMethod(S, D, AL); break; + case ParsedAttr::AT_CountedBy: + handleCountedByAttr(S, D, AL); + break; + // Microsoft attributes: case ParsedAttr::AT_LayoutVersion: handleLayoutVersion(S, D, AL); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 60ad035570c8..2f48ea237cdf 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -2469,7 +2469,8 @@ bool Sema::DiagnoseDependentMemberLookup(const LookupResult &R) { bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, CorrectionCandidateCallback &CCC, TemplateArgumentListInfo *ExplicitTemplateArgs, - ArrayRef Args, TypoExpr **Out) { + ArrayRef Args, DeclContext *LookupCtx, + TypoExpr **Out) { DeclarationName Name = R.getLookupName(); unsigned diagnostic = diag::err_undeclared_var_use; @@ -2485,7 +2486,8 @@ bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, // unqualified lookup. This is useful when (for example) the // original lookup would not have found something because it was a // dependent name. - DeclContext *DC = SS.isEmpty() ? CurContext : nullptr; + DeclContext *DC = + LookupCtx ? LookupCtx : (SS.isEmpty() ? CurContext : nullptr); while (DC) { if (isa(DC)) { LookupQualifiedName(R, DC); @@ -2528,12 +2530,12 @@ bool Sema::DiagnoseEmptyLookup(Scope *S, CXXScopeSpec &SS, LookupResult &R, emitEmptyLookupTypoDiagnostic(TC, *this, SS, Name, TypoLoc, Args, diagnostic, diagnostic_suggest); }, - nullptr, CTK_ErrorRecovery); + nullptr, CTK_ErrorRecovery, LookupCtx); if (*Out) return true; - } else if (S && - (Corrected = CorrectTypo(R.getLookupNameInfo(), R.getLookupKind(), - S, &SS, CCC, CTK_ErrorRecovery))) { + } else if (S && (Corrected = + CorrectTypo(R.getLookupNameInfo(), R.getLookupKind(), S, + &SS, CCC, CTK_ErrorRecovery, LookupCtx))) { std::string CorrectedStr(Corrected.getAsString(getLangOpts())); bool DroppedSpecifier = Corrected.WillReplaceSpecifier() && Name.getAsString() == CorrectedStr; @@ -2823,7 +2825,7 @@ Sema::ActOnIdExpression(Scope *S, CXXScopeSpec &SS, // a template name, but we happen to have always already looked up the name // before we get here if it must be a template name. if (DiagnoseEmptyLookup(S, SS, R, CCC ? *CCC : DefaultValidator, nullptr, - std::nullopt, &TE)) { + std::nullopt, nullptr, &TE)) { if (TE && KeywordReplacement) { auto &State = getTypoExprState(TE); auto BestTC = State.Consumer->getNextCorrection(); diff --git a/clang/test/CodeGen/attr-counted-by.c b/clang/test/CodeGen/attr-counted-by.c new file mode 100644 index 000000000000..74d5457e398b --- /dev/null +++ b/clang/test/CodeGen/attr-counted-by.c @@ -0,0 +1,1828 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -DCOUNTED_BY -O2 -Wall -fsanitize=array-bounds,object-size,local-bounds -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=SANITIZE-WITH-ATTR %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -DCOUNTED_BY -O2 -Wall -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=NO-SANITIZE-WITH-ATTR %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O2 -Wall -fsanitize=array-bounds,object-size,local-bounds -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=SANITIZE-WITHOUT-ATTR %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O2 -Wall -fstrict-flex-arrays=3 -emit-llvm -o - %s | FileCheck --check-prefix=NO-SANITIZE-WITHOUT-ATTR %s + +#if !__has_attribute(counted_by) +#error "has attribute broken" +#endif + +#ifdef COUNTED_BY +#define __counted_by(member) __attribute__((__counted_by__(member))) +#else +#define __counted_by(member) +#endif + +#define DECLARE_FLEX_ARRAY(TYPE, NAME) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[]; \ + } + +#define DECLARE_BOUNDED_FLEX_ARRAY(COUNT_TYPE, COUNT, TYPE, NAME) \ + struct { \ + COUNT_TYPE COUNT; \ + TYPE NAME[] __counted_by(COUNT); \ + } + +#define DECLARE_FLEX_ARRAY_COUNTED_BY(TYPE, NAME, COUNTED_BY) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[] __counted_by(COUNTED_BY); \ + } + +typedef long unsigned int size_t; + +struct annotated { + unsigned long flags; + int count; + int array[] __counted_by(count); +}; + +struct union_of_fams { + unsigned long flags; + union { + /* count member type intentionally mismatched to induce padding */ + DECLARE_BOUNDED_FLEX_ARRAY(int, count_bytes, unsigned char, bytes); + DECLARE_BOUNDED_FLEX_ARRAY(unsigned char, count_ints, unsigned char, ints); + DECLARE_FLEX_ARRAY(unsigned char, unsafe); + }; +}; + +struct anon_struct { + unsigned long flags; + size_t count; + DECLARE_FLEX_ARRAY_COUNTED_BY(int, array, count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test1( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3:![0-9]+]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB2:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10:[0-9]+]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test1( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test1( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test1( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[VAL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[VAL]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test1(struct annotated *p, int index, int val) { + p->array[index] = val; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test2( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], [[INDEX]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB4:[0-9]+]], i64 [[INDEX]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP2]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test2( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP0]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test2( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test2( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test2(struct annotated *p, size_t index) { + p->array[index] = __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test2_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 [[TMP1]], i64 0 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP3]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test2_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 [[TMP1]], i64 0 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP3]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test2_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test2_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test2_bdos(struct annotated *p) { + return __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test3( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], [[INDEX]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB5:[0-9]+]], i64 [[INDEX]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP3]], i64 4) +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 12 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP6]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test3( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP4]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test3( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test3( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test3(struct annotated *p, size_t index) { + // This test differs from 'test2' by checking bdos on the whole array and not + // just the FAM. + p->array[index] = __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test3_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 12 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP3]], i64 0 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP5]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test3_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP1]], i64 4) +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP3]], i64 0 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP5]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test3_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test3_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test3_bdos(struct annotated *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test4( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT4:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB6:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont4: +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 244 +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 252 +// SANITIZE-WITH-ATTR-NEXT: [[CONV1:%.*]] = select i1 [[TMP2]], i32 [[TMP5]], i32 0 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV1]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD7:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM13:%.*]] = sext i32 [[ADD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD7]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = icmp ult i64 [[IDXPROM13]], [[TMP6]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP7]], label [[CONT20:%.*]], label [[HANDLER_OUT_OF_BOUNDS16:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds16: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB7:[0-9]+]], i64 [[IDXPROM13]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont20: +// SANITIZE-WITH-ATTR-NEXT: [[TMP8:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD7]], 3 +// SANITIZE-WITH-ATTR-NEXT: [[TMP9:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD7]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 240 +// SANITIZE-WITH-ATTR-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 252 +// SANITIZE-WITH-ATTR-NEXT: [[CONV9:%.*]] = select i1 [[TMP8]], i32 [[TMP11]], i32 0 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM13]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV9]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD23:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[ADD29:%.*]] = add nsw i32 [[INDEX]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM30:%.*]] = sext i32 [[ADD29]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP12:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD23]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP13:%.*]] = icmp ult i64 [[IDXPROM30]], [[TMP12]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP13]], label [[CONT37:%.*]], label [[HANDLER_OUT_OF_BOUNDS33:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds33: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB8:[0-9]+]], i64 [[IDXPROM30]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont37: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM30]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP14:%.*]] = icmp sgt i32 [[FAM_IDX]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP15:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD23]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP16:%.*]] = sext i32 [[FAM_IDX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP17:%.*]] = sub nsw i64 [[TMP15]], [[TMP16]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[TMP17]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP19:%.*]] = and i1 [[TMP14]], [[TMP18]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTTR:%.*]] = trunc i64 [[TMP17]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP20:%.*]] = shl i32 [[DOTTR]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP21:%.*]] = and i32 [[TMP20]], 252 +// SANITIZE-WITH-ATTR-NEXT: [[CONV25:%.*]] = select i1 [[TMP19]], i32 [[TMP21]], i32 0 +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV25]], ptr [[ARRAYIDX35]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test4( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 244 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 252 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV1:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV1]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD4:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD4]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 240 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = icmp sgt i32 [[DOT_COUNTED_BY_LOAD4]], 3 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = and i32 [[TMP5]], 252 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV6:%.*]] = select i1 [[TMP6]], i32 [[TMP7]], i32 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM8:%.*]] = sext i32 [[ADD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM8]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV6]], ptr [[ARRAYIDX9]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD12:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP8:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD12]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP9:%.*]] = sext i32 [[FAM_IDX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP10:%.*]] = sub nsw i64 [[TMP8]], [[TMP9]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP11:%.*]] = icmp sgt i64 [[TMP10]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP12:%.*]] = icmp sgt i32 [[FAM_IDX]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP13:%.*]] = and i1 [[TMP12]], [[TMP11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTTR:%.*]] = trunc i64 [[TMP10]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP14:%.*]] = shl i32 [[DOTTR]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP15:%.*]] = and i32 [[TMP14]], 252 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV14:%.*]] = select i1 [[TMP13]], i32 [[TMP15]], i32 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ADD16:%.*]] = add nsw i32 [[INDEX]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM17:%.*]] = sext i32 [[ADD16]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM17]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV14]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test4( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM17:%.*]] = sext i32 [[ADD]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM17]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[ADD31:%.*]] = add nsw i32 [[INDEX]], 2 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM32:%.*]] = sext i32 [[ADD31]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM32]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX33]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test4( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]], i32 noundef [[FAM_IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX3]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ADD:%.*]] = add nsw i32 [[INDEX]], 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM9:%.*]] = sext i32 [[ADD]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM9]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX10]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ADD17:%.*]] = add nsw i32 [[INDEX]], 2 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM18:%.*]] = sext i32 [[ADD17]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM18]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 255, ptr [[ARRAYIDX19]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test4(struct annotated *p, int index, int fam_idx) { + // This tests calculating the size from a pointer inside the FAM. + p->array[index] = (unsigned char)__builtin_dynamic_object_size(&p->array[3], 1); + p->array[index + 1] = (unsigned char)__builtin_dynamic_object_size(&(p->array[4]), 1); + p->array[index + 2] = (unsigned char)__builtin_dynamic_object_size(&(p->array[fam_idx]), 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test4_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sub nsw i64 [[TMP0]], [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i64 [[TMP2]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[INDEX]], -1 +// SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = and i1 [[TMP5]], [[TMP4]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 [[TMP3]], i64 0 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP7]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test4_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = sext i32 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = sub nsw i64 [[TMP0]], [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp sgt i64 [[TMP2]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[INDEX]], -1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP6:%.*]] = and i1 [[TMP5]], [[TMP4]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 [[TMP3]], i64 0 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP7]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test4_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test4_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test4_bdos(struct annotated *p, int index) { + return __builtin_dynamic_object_size(&p->array[index], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test5( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[DOT_COUNTED_BY_LOAD]], [[IDXPROM]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB9:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 16 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP2]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test5( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 16 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test5( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test5( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test5(struct anon_struct *p, int index) { + p->array[index] = __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test5_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add nuw i64 [[TMP0]], 16 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test5_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = add nuw i64 [[TMP0]], 16 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP2]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test5_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test5_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test5_bdos(struct anon_struct *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test6( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[DOT_COUNTED_BY_LOAD]], [[IDXPROM]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB10:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test6( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD_TR:%.*]] = trunc i64 [[DOT_COUNTED_BY_LOAD]] to i32 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD_TR]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP0]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT]], ptr [[P]], i64 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test6( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test6( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAY:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARRAY]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test6(struct anon_struct *p, int index) { + p->array[index] = __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test6_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP0]] +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP1]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test6_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANON_STRUCT:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i64, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = shl nuw i64 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i64 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = select i1 [[DOTINV]], i64 0, i64 [[TMP0]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP1]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test6_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test6_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test6_bdos(struct anon_struct *p) { + return __builtin_dynamic_object_size(p->array, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test7( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i8, ptr [[TMP0]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i8 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP1]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT7:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB12:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont7: +// SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test7( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test7( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test7( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test7(struct union_of_fams *p, int index) { + p->ints[index] = __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test7_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test7_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test7_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test7_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test7_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test8( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT9:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB13:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont9: +// SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i8 [[DOT_COUNTED_BY_LOAD]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test8( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 [[DOT_COUNTED_BY_LOAD]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test8( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test8( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[INTS:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[INTS]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test8(struct union_of_fams *p, int index) { + p->ints[index] = __builtin_dynamic_object_size(p->ints, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test8_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test8_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i8, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i8 [[DOT_COUNTED_BY_LOAD]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test8_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test8_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test8_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p->ints, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test9( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[TMP0]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP1]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT7:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB14:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont7: +// SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test9( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test9( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test9( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test9(struct union_of_fams *p, int index) { + p->bytes[index] = (unsigned char)__builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test9_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test9_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test9_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test9_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test9_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test10( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT9:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB15:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont9: +// SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = trunc i32 [[NARROW]] to i8 +// SANITIZE-WITH-ATTR-NEXT: store i8 [[CONV]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA8]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test10( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = trunc i32 [[NARROW]] to i8 +// NO-SANITIZE-WITH-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i8 [[CONV]], ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test10( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test10( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BYTES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i8], ptr [[BYTES]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i8 -1, ptr [[ARRAYIDX]], align 1, !tbaa [[TBAA6]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test10(struct union_of_fams *p, int index) { + p->bytes[index] = (unsigned char)__builtin_dynamic_object_size(p->bytes, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test10_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext nneg i32 [[NARROW]] to i64 +// SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i64 @test10_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_UNION_OF_FAMS:%.*]], ptr [[P]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[NARROW:%.*]] = tail call i32 @llvm.smax.i32(i32 [[DOT_COUNTED_BY_LOAD]], i32 0) +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext nneg i32 [[NARROW]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test10_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test10_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test10_bdos(struct union_of_fams *p) { + return __builtin_dynamic_object_size(p->bytes, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test11( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB16:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test11( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test11( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test11( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef writeonly [[P:%.*]], i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[P]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 4, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test11(struct annotated *p, int index) { + p->array[index] = __builtin_dynamic_object_size(&p->count, 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test11_bdos( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 4 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test11_bdos( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 4 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test11_bdos( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 4 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test11_bdos( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 4 +// +size_t test11_bdos(struct annotated *p) { + return __builtin_dynamic_object_size(&p->count, 1); +} + +struct { + struct { + struct { + int num_entries; + }; + }; + int entries[] __attribute__((__counted_by__(num_entries))); +} test12_foo; + +struct hang { + int entries[6]; +} test12_bar; + +int test12_a, test12_b; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i32 @test12( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR5:[0-9]+]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR11:[0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT9:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[INDEX]], 6 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB18:[0-9]+]], i64 [[TMP1]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP2]], ptr @test12_b, align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr @test12_foo, align 4 +// SANITIZE-WITH-ATTR-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[DOTCOUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[DOTNOT]], label [[HANDLER_OUT_OF_BOUNDS4:%.*]], label [[HANDLER_TYPE_MISMATCH6:%.*]], !prof [[PROF10:![0-9]+]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds4: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB19:[0-9]+]], i64 0) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.type_mismatch6: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_type_mismatch_v1_abort(ptr nonnull @[[GLOB20:[0-9]+]], i64 ptrtoint (ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0) to i64)) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i32 @test12( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR5:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR12:[0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0), align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[TMP1]], ptr @test12_a, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: br label [[FOR_COND:%.*]] +// NO-SANITIZE-WITH-ATTR: for.cond: +// NO-SANITIZE-WITH-ATTR-NEXT: br label [[FOR_COND]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i32 @test12( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR7:[0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[INDEX]], 6 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[CONT:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8:![0-9]+]], !nosanitize [[META9:![0-9]+]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB2:[0-9]+]], i64 [[TMP1]]) #[[ATTR8:[0-9]+]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: cont: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[TMP1]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP2]], ptr @test12_b, align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr @test12_foo, align 4 +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[DOTCOUNTED_BY_LOAD]], 0 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[DOTNOT]], label [[HANDLER_OUT_OF_BOUNDS4:%.*]], label [[HANDLER_TYPE_MISMATCH6:%.*]], !prof [[PROF10:![0-9]+]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds4: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB4:[0-9]+]], i64 0) #[[ATTR8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.type_mismatch6: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_type_mismatch_v1_abort(ptr nonnull @[[GLOB5:[0-9]+]], i64 ptrtoint (ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0) to i64)) #[[ATTR8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i32 @test12( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[BAZ:%.*]] = alloca [[STRUCT_HANG:%.*]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR9:[0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_ANON_5:%.*]], ptr @test12_foo, i64 1, i32 0, i32 0, i32 0), align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 [[TMP1]], ptr @test12_a, align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: br label [[FOR_COND:%.*]] +// NO-SANITIZE-WITHOUT-ATTR: for.cond: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: br label [[FOR_COND]] +// +int test12(int index) { + struct hang baz = test12_bar; + + for (;; test12_a = (&test12_foo)->entries[0]) + test12_b = baz.entries[index]; + + return test12_b; +} + +struct test13_foo { + struct test13_bar *domain; +} test13_f; + +struct test13_bar { + struct test13_bar *parent; + int revmap_size; + struct test13_foo *revmap[] __attribute__((__counted_by__(revmap_size))); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i32 @test13( +// SANITIZE-WITH-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA11:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], [[INDEX]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP2]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB23:[0-9]+]], i64 [[INDEX]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont5: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITH-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14:![0-9]+]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 0 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i32 @test13( +// NO-SANITIZE-WITH-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR8:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA8:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITH-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11:![0-9]+]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 0 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i32 @test13( +// SANITIZE-WITHOUT-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA11:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], [[INDEX]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP2]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB8:[0-9]+]], i64 [[INDEX]]) #[[ATTR8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: cont5: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// SANITIZE-WITHOUT-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14:![0-9]+]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 0 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i32 @test13( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i64 noundef [[INDEX:%.*]]) local_unnamed_addr #[[ATTR5:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr @test13_f, align 8, !tbaa [[TBAA8:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST13_BAR:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[INDEX]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store ptr null, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11:![0-9]+]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 0 +// +int test13(long index) { + test13_f.domain->revmap[index] = 0; + return 0; +} + +struct test14_foo { + int x, y; + int blah[] __attribute__((counted_by(x))); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test14( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB24:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: trap: +// SANITIZE-WITH-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR10]] +// SANITIZE-WITH-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test14( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTCOMPOUNDLITERAL:%.*]] = alloca [[STRUCT_TEST14_FOO:%.*]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 1, ptr [[DOTCOMPOUNDLITERAL]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 2, ptr [[Y]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test14( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB9:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: trap: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR8]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test14( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[DOTCOMPOUNDLITERAL:%.*]] = alloca [[STRUCT_TEST14_FOO:%.*]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 1, ptr [[DOTCOMPOUNDLITERAL]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 2, ptr [[Y]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST14_FOO]], ptr [[DOTCOMPOUNDLITERAL]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +int test14(int idx) { + return (struct test14_foo){ 1, 2 }.blah[idx]; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test15( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB25:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: trap: +// SANITIZE-WITH-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR10]] +// SANITIZE-WITH-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test15( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[FOO:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR12]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 1, ptr [[FOO]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[FOO]], i64 4 +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 2, ptr [[TMP0]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[FOO]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR12]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test15( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp eq i32 [[IDX]], 0 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[TRAP:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB10:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: trap: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @llvm.trap() #[[ATTR8]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test15( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[IDX:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[FOO:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR9]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 1, ptr [[FOO]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[FOO]], i64 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 2, ptr [[TMP0]], align 4 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[FOO]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr nonnull [[FOO]]) #[[ATTR9]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] +// +int test15(int idx) { + struct { + int x, y; + int blah[] __attribute__((counted_by(x))); + } foo = { 1, 2 }; + + return foo.blah[idx]; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test19( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test19( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test19( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i64 @test19( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test19(struct annotated *p) { + // Avoid pointer arithmetic. It could lead to security issues. + return __builtin_dynamic_object_size(&(p + 42)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test20( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test20( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test20( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test20( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test20(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(++p)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test21( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test21( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test21( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test21( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test21(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(p++)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test22( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test22( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test22( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test22( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test22(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(--p)->array[2], 1); +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test23( +// SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local noundef i64 @test23( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR4]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: ret i64 -1 +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test23( +// SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local noundef i64 @test23( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readnone [[P:%.*]]) local_unnamed_addr #[[ATTR1]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i64 -1 +// +size_t test23(struct annotated *p) { + // Avoid side-effects. + return __builtin_dynamic_object_size(&(p--)->array[2], 1); +} + +struct tests_foo { + int count; + int arr[] __counted_by(count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test24( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 10 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[DOTCOUNTED_BY_LOAD]], 10 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT4:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB26:[0-9]+]], i64 10) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont4: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO]], ptr [[VAR]], i64 21 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test24( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test24( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test24( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[VAR]], i64 21 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +int test24(int c, struct tests_foo *var) { + // Invalid: there can't be an array of flexible arrays. + return var[10].arr[10]; +} + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test25( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[TMP0]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[DOTCOUNTED_BY_LOAD]], 10 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB27:[0-9]+]], i64 10) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont5: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test25( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR9:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP1]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test25( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[VAR:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test25( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[VAR:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TESTS_FOO:%.*]], ptr [[TMP0]], i64 11 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP1]] +// +int test25(int c, struct tests_foo **var) { + // Double dereferenced variable. + return (**var).arr[10]; +} + +// Outer struct +struct test26_foo { + int a; + struct tests_foo s; +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test26( +// SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[FOO:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[S:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[S]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT5:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB28:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont5: +// SANITIZE-WITH-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO]], ptr [[FOO]], i64 1 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP2]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test26( +// NO-SANITIZE-WITH-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[FOO:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP0]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test26( +// SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr noundef [[FOO:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test26( +// NO-SANITIZE-WITHOUT-ATTR-SAME: i32 noundef [[C:%.*]], ptr nocapture noundef readonly [[FOO:%.*]]) local_unnamed_addr #[[ATTR6]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_TEST26_FOO:%.*]], ptr [[FOO]], i64 1 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[C]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [0 x i32], ptr [[ARR]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP0]] +// +int test26(int c, struct test26_foo *foo) { + // Invalid: A structure with a flexible array must be a pointer. + return foo->s.arr[c]; +} + +struct test27_baz; + +struct test27_bar { + unsigned char type; + unsigned char flags; + unsigned short use_cnt; + unsigned char hw_priv; +}; + +struct test27_foo { + struct test27_baz *a; + + unsigned char bit1 : 1; + unsigned char bit2 : 1; + unsigned char bit3 : 1; + + unsigned int n_tables; + unsigned long missed; + struct test27_bar *entries[] __counted_by(n_tables); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local ptr @test27( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP0]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP1]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB30:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM4:%.*]] = sext i32 [[J]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP2]], i64 [[IDXPROM4]] +// SANITIZE-WITH-ATTR-NEXT: ret ptr [[ARRAYIDX5]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local ptr @test27( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR2]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[J]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM1]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret ptr [[ARRAYIDX2]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local ptr @test27( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM3:%.*]] = sext i32 [[J]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM3]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret ptr [[ARRAYIDX4]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local ptr @test27( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]], i32 noundef [[J:%.*]]) local_unnamed_addr #[[ATTR6]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST27_FOO:%.*]], ptr [[P]], i64 0, i32 4, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[J]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_TEST27_BAR:%.*]], ptr [[TMP0]], i64 [[IDXPROM1]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret ptr [[ARRAYIDX2]] +// +struct test27_bar *test27(struct test27_foo *p, int i, int j) { + return &p->entries[i][j]; +} + +struct test28_foo { + struct test28_foo *s; + int count; + int arr[] __counted_by(count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test28( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOTCOUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOTCOUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = zext i32 [[DOTCOUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[IDXPROM]], [[TMP3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP4]], label [[CONT17:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB31:[0-9]+]], i64 [[IDXPROM]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont17: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP5]] +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local i32 @test28( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR9]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret i32 [[TMP3]] +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test28( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP3]] +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local i32 @test28( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[P:%.*]], i32 noundef [[I:%.*]]) local_unnamed_addr #[[ATTR7]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_TEST28_FOO:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret i32 [[TMP3]] +// +int test28(struct test28_foo *p, int i) { + return p->s->s->s->arr[i]; +} + +struct annotated_struct_array { + struct annotated *ann_array[10]; + unsigned long flags; + int count; + int array[] __counted_by(count); +}; + +// SANITIZE-WITH-ATTR-LABEL: define dso_local void @test29( +// SANITIZE-WITH-ATTR-SAME: ptr noundef [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITH-ATTR-NEXT: entry: +// SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[IDX1]], 10 +// SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[IDX1]] to i64 +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP0]], label [[CONT3:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB33:[0-9]+]], i64 [[TMP1]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont3: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[TMP1]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP2]], i64 0, i32 1 +// SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// SANITIZE-WITH-ATTR-NEXT: [[IDXPROM15:%.*]] = sext i32 [[IDX2]] to i64 +// SANITIZE-WITH-ATTR-NEXT: [[TMP3:%.*]] = zext i32 [[DOT_COUNTED_BY_LOAD]] to i64, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[IDXPROM15]], [[TMP3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: br i1 [[TMP4]], label [[CONT20:%.*]], label [[HANDLER_OUT_OF_BOUNDS16:%.*]], !prof [[PROF3]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: handler.out_of_bounds16: +// SANITIZE-WITH-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB34:[0-9]+]], i64 [[IDXPROM15]]) #[[ATTR10]], !nosanitize [[META2]] +// SANITIZE-WITH-ATTR-NEXT: unreachable, !nosanitize [[META2]] +// SANITIZE-WITH-ATTR: cont20: +// SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM15]] +// SANITIZE-WITH-ATTR-NEXT: [[TMP5:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP5]] +// SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX18]], align 4, !tbaa [[TBAA4]] +// SANITIZE-WITH-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITH-ATTR-LABEL: define dso_local void @test29( +// NO-SANITIZE-WITH-ATTR-SAME: ptr nocapture noundef readonly [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR10:[0-9]+]] { +// NO-SANITIZE-WITH-ATTR-NEXT: entry: +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX1]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP0]], i64 0, i32 1 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOT_COUNTED_BY_LOAD:%.*]] = load i32, ptr [[DOT_COUNTED_BY_GEP]], align 4 +// NO-SANITIZE-WITH-ATTR-NEXT: [[TMP1:%.*]] = shl i32 [[DOT_COUNTED_BY_LOAD]], 2 +// NO-SANITIZE-WITH-ATTR-NEXT: [[DOTINV:%.*]] = icmp slt i32 [[DOT_COUNTED_BY_LOAD]], 0 +// NO-SANITIZE-WITH-ATTR-NEXT: [[CONV:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]] +// NO-SANITIZE-WITH-ATTR-NEXT: [[IDXPROM4:%.*]] = sext i32 [[IDX2]] to i64 +// NO-SANITIZE-WITH-ATTR-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED]], ptr [[TMP0]], i64 0, i32 2, i64 [[IDXPROM4]] +// NO-SANITIZE-WITH-ATTR-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITH-ATTR-NEXT: ret void +// +// SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test29( +// SANITIZE-WITHOUT-ATTR-SAME: ptr noundef [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR0]] { +// SANITIZE-WITHOUT-ATTR-NEXT: entry: +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = icmp ult i32 [[IDX1]], 10 +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP1:%.*]] = zext i32 [[IDX1]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: br i1 [[TMP0]], label [[CONT21:%.*]], label [[HANDLER_OUT_OF_BOUNDS:%.*]], !prof [[PROF8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: handler.out_of_bounds: +// SANITIZE-WITHOUT-ATTR-NEXT: tail call void @__ubsan_handle_out_of_bounds_abort(ptr nonnull @[[GLOB12:[0-9]+]], i64 [[TMP1]]) #[[ATTR8]], !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR-NEXT: unreachable, !nosanitize [[META9]] +// SANITIZE-WITHOUT-ATTR: cont21: +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[TMP1]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA14]] +// SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM18:%.*]] = sext i32 [[IDX2]] to i64 +// SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP2]], i64 0, i32 2, i64 [[IDXPROM18]] +// SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX19]], align 4, !tbaa [[TBAA2]] +// SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +// NO-SANITIZE-WITHOUT-ATTR-LABEL: define dso_local void @test29( +// NO-SANITIZE-WITHOUT-ATTR-SAME: ptr nocapture noundef readonly [[ANN:%.*]], i32 noundef [[IDX1:%.*]], i32 noundef [[IDX2:%.*]]) local_unnamed_addr #[[ATTR8:[0-9]+]] { +// NO-SANITIZE-WITHOUT-ATTR-NEXT: entry: +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM:%.*]] = sext i32 [[IDX1]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[ANN]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA11]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[IDXPROM5:%.*]] = sext i32 [[IDX2]] to i64 +// NO-SANITIZE-WITHOUT-ATTR-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [[STRUCT_ANNOTATED:%.*]], ptr [[TMP0]], i64 0, i32 2, i64 [[IDXPROM5]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: store i32 -1, ptr [[ARRAYIDX6]], align 4, !tbaa [[TBAA2]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT: ret void +// +void test29(struct annotated_struct_array *ann, int idx1, int idx2) { + ann->ann_array[idx1]->array[idx2] = __builtin_dynamic_object_size(ann->ann_array[idx1]->array, 1); +} diff --git a/clang/test/CodeGen/bounds-checking.c b/clang/test/CodeGen/bounds-checking.c index 636d4f289e24..8100e30d0650 100644 --- a/clang/test/CodeGen/bounds-checking.c +++ b/clang/test/CodeGen/bounds-checking.c @@ -69,7 +69,6 @@ int f7(union U *u, int i) { return u->c[i]; } - char B[10]; char B2[10]; // CHECK-LABEL: @f8 @@ -82,3 +81,12 @@ void f8(int i, int k) { // NOOPTARRAY: call void @llvm.ubsantrap(i8 4) B2[k] = '\0'; } + +// See commit 9a954c6 that caused a SEGFAULT in this code. +struct S { + __builtin_va_list ap; +} *s; +// CHECK-LABEL: @f9 +struct S *f9(int i) { + return &s[i]; +} diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test index 2f80c96e1d52..e476c15b35de 100644 --- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test +++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test @@ -62,6 +62,7 @@ // CHECK-NEXT: CoroOnlyDestroyWhenComplete (SubjectMatchRule_record) // CHECK-NEXT: CoroReturnType (SubjectMatchRule_record) // CHECK-NEXT: CoroWrapper (SubjectMatchRule_function) +// CHECK-NEXT: CountedBy (SubjectMatchRule_field) // CHECK-NEXT: DLLExport (SubjectMatchRule_function, SubjectMatchRule_variable, SubjectMatchRule_record, SubjectMatchRule_objc_interface) // CHECK-NEXT: DLLImport (SubjectMatchRule_function, SubjectMatchRule_variable, SubjectMatchRule_record, SubjectMatchRule_objc_interface) // CHECK-NEXT: Destructor (SubjectMatchRule_function) diff --git a/clang/test/Sema/attr-counted-by.c b/clang/test/Sema/attr-counted-by.c new file mode 100644 index 000000000000..f14da9c77fa8 --- /dev/null +++ b/clang/test/Sema/attr-counted-by.c @@ -0,0 +1,64 @@ +// RUN: %clang_cc1 -fsyntax-only -verify %s + +#define __counted_by(f) __attribute__((counted_by(f))) + +struct bar; + +struct not_found { + int count; + struct bar *fam[] __counted_by(bork); // expected-error {{use of undeclared identifier 'bork'}} +}; + +struct no_found_count_not_in_substruct { + unsigned long flags; + unsigned char count; // expected-note {{field 'count' declared here}} + struct A { + int dummy; + int array[] __counted_by(count); // expected-error {{'counted_by' field 'count' isn't within the same struct as the flexible array}} + } a; +}; + +struct not_found_suggest { + int bork; // expected-note {{'bork' declared here}} + struct bar *fam[] __counted_by(blork); // expected-error {{use of undeclared identifier 'blork'; did you mean 'bork'?}} +}; + +int global; // expected-note {{'global' declared here}} + +struct found_outside_of_struct { + int bork; + struct bar *fam[] __counted_by(global); // expected-error {{field 'global' in 'counted_by' not inside structure}} +}; + +struct self_referrential { + int bork; + struct bar *self[] __counted_by(self); // expected-error {{'counted_by' cannot refer to the flexible array 'self'}} +}; + +struct non_int_count { + double dbl_count; // expected-note {{field 'dbl_count' declared here}} + struct bar *fam[] __counted_by(dbl_count); // expected-error {{field 'dbl_count' in 'counted_by' must be a non-boolean integer type}} +}; + +struct array_of_ints_count { + int integers[2]; // expected-note {{field 'integers' declared here}} + struct bar *fam[] __counted_by(integers); // expected-error {{field 'integers' in 'counted_by' must be a non-boolean integer type}} +}; + +struct not_a_fam { + int count; + struct bar *non_fam __counted_by(count); // expected-error {{'counted_by' only applies to C99 flexible array members}} +}; + +struct not_a_c99_fam { + int count; + struct bar *non_c99_fam[0] __counted_by(count); // expected-error {{'counted_by' only applies to C99 flexible array members}} +}; + +struct annotated_with_anon_struct { + unsigned long flags; + struct { + unsigned char count; // expected-note {{'count' declared here}} + int array[] __counted_by(crount); // expected-error {{use of undeclared identifier 'crount'; did you mean 'count'?}} + }; +}; -- GitLab From 3d795bdd4d9067e96b2ff9e6278a5b8847eebe2b Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Thu, 11 Jan 2024 15:15:12 +0800 Subject: [PATCH 417/652] [InstCombine] Handle a bitreverse idiom which ends with a bswap (#77677) This patch handles the following `bitreverse` idiom, which is found in https://github.com/abseil/abseil-cpp/blob/8bd6445acc4bd0d123da2a44448b7218dfc70939/absl/crc/internal/crc.cc#L75-L80: ``` uint32_t ReverseBits(uint32_t bits) { bits = (bits & 0xaaaaaaaau) >> 1 | (bits & 0x55555555u) << 1; bits = (bits & 0xccccccccu) >> 2 | (bits & 0x33333333u) << 2; bits = (bits & 0xf0f0f0f0u) >> 4 | (bits & 0x0f0f0f0fu) << 4; return absl::gbswap_32(bits); } ``` Alive2: https://alive2.llvm.org/ce/z/ZYXNmj --- .../InstCombine/InstCombineCalls.cpp | 4 +++ llvm/lib/Transforms/Utils/Local.cpp | 3 ++- .../test/Transforms/InstCombine/bitreverse.ll | 26 +++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index 40b48699f758..64fbd5543a9e 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -1884,6 +1884,10 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { return crossLogicOpFold; } + // Try to fold into bitreverse if bswap is the root of the expression tree. + if (Instruction *BitOp = matchBSwapOrBitReverse(*II, /*MatchBSwaps*/ false, + /*MatchBitReversals*/ true)) + return BitOp; break; } case Intrinsic::masked_load: diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index c76cc9db16d7..b9cad764aaef 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -3905,7 +3905,8 @@ bool llvm::recognizeBSwapOrBitReverseIdiom( SmallVectorImpl &InsertedInsts) { if (!match(I, m_Or(m_Value(), m_Value())) && !match(I, m_FShl(m_Value(), m_Value(), m_Value())) && - !match(I, m_FShr(m_Value(), m_Value(), m_Value()))) + !match(I, m_FShr(m_Value(), m_Value(), m_Value())) && + !match(I, m_BSwap(m_Value()))) return false; if (!MatchBSwaps && !MatchBitReversals) return false; diff --git a/llvm/test/Transforms/InstCombine/bitreverse.ll b/llvm/test/Transforms/InstCombine/bitreverse.ll index 7d122297c11b..cbe9695c4869 100644 --- a/llvm/test/Transforms/InstCombine/bitreverse.ll +++ b/llvm/test/Transforms/InstCombine/bitreverse.ll @@ -106,6 +106,30 @@ entry: ret i32 %or.4 } +define i32 @rev32_bswap(i32 %v) { +; CHECK-LABEL: @rev32_bswap( +; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[V:%.*]]) +; CHECK-NEXT: ret i32 [[RET]] +; + %and.i = lshr i32 %v, 1 + %shr.i = and i32 %and.i, 1431655765 + %and1.i = shl i32 %v, 1 + %shl.i = and i32 %and1.i, -1431655766 + %or.i = or disjoint i32 %shr.i, %shl.i + %and2.i = lshr i32 %or.i, 2 + %shr3.i = and i32 %and2.i, 858993459 + %and4.i = shl i32 %or.i, 2 + %shl5.i = and i32 %and4.i, -858993460 + %or6.i = or disjoint i32 %shr3.i, %shl5.i + %and7.i = lshr i32 %or6.i, 4 + %shr8.i = and i32 %and7.i, 252645135 + %and9.i = shl i32 %or6.i, 4 + %shl10.i = and i32 %and9.i, -252645136 + %or11.i = or disjoint i32 %shr8.i, %shl10.i + %ret = call i32 @llvm.bswap.i32(i32 %or11.i) + ret i32 %ret +} + define i64 @rev64(i64 %v) { ; CHECK-LABEL: @rev64( ; CHECK-NEXT: entry: @@ -508,3 +532,5 @@ define i64 @rev_all_operand64_multiuse_both(i64 %a, i64 %b) #0 { call void @use_i64(i64 %2) ret i64 %4 } + +declare i32 @llvm.bswap.i32(i32 %or11.i) -- GitLab From 211abe38d83aced510726601c7cf6b464f6ee5b1 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 11 Jan 2024 15:28:12 +0800 Subject: [PATCH 418/652] [SelectionDAG] Add space-optimized forms of OPC_CheckComplexPat (#73310) We record the usage of each `ComplexPat` and sort the `ComplexPat`s by usage. For the top 8 `ComplexPat`s, we will emit a `OPC_CheckComplexPatN` to save one byte. Overall this reduces the llc binary size with all in-tree targets by about 89K. --- llvm/include/llvm/CodeGen/SelectionDAGISel.h | 8 +++ .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 14 ++++- llvm/test/TableGen/dag-isel-complexpattern.td | 2 +- llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 55 ++++++++++++++----- 4 files changed, 63 insertions(+), 16 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index 40046e0a8dec..99ce658e7eb7 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -207,6 +207,14 @@ public: OPC_CheckChild2CondCode, OPC_CheckValueType, OPC_CheckComplexPat, + OPC_CheckComplexPat0, + OPC_CheckComplexPat1, + OPC_CheckComplexPat2, + OPC_CheckComplexPat3, + OPC_CheckComplexPat4, + OPC_CheckComplexPat5, + OPC_CheckComplexPat6, + OPC_CheckComplexPat7, OPC_CheckAndImm, OPC_CheckOrImm, OPC_CheckImmAllOnesV, diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 9acfc76d7d5e..344dc8d8a9b6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3358,8 +3358,18 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, break; continue; } - case OPC_CheckComplexPat: { - unsigned CPNum = MatcherTable[MatcherIndex++]; + case OPC_CheckComplexPat: + case OPC_CheckComplexPat0: + case OPC_CheckComplexPat1: + case OPC_CheckComplexPat2: + case OPC_CheckComplexPat3: + case OPC_CheckComplexPat4: + case OPC_CheckComplexPat5: + case OPC_CheckComplexPat6: + case OPC_CheckComplexPat7: { + unsigned CPNum = Opcode == OPC_CheckComplexPat + ? MatcherTable[MatcherIndex++] + : Opcode - OPC_CheckComplexPat0; unsigned RecNo = MatcherTable[MatcherIndex++]; assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); diff --git a/llvm/test/TableGen/dag-isel-complexpattern.td b/llvm/test/TableGen/dag-isel-complexpattern.td index 3d74e4e46dc4..b8f517a1fc28 100644 --- a/llvm/test/TableGen/dag-isel-complexpattern.td +++ b/llvm/test/TableGen/dag-isel-complexpattern.td @@ -22,7 +22,7 @@ def CP32 : ComplexPattern; def INSTR : Instruction { // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::STORE) // CHECK: OPC_CheckTypeI32 -// CHECK: OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectCP32:$ +// CHECK: OPC_CheckComplexPat0, /*#*/1, // SelectCP32:$ // CHECK: Src: (st (add:{ *:[i32] } (CP32:{ *:[i32] }), (CP32:{ *:[i32] })), i64:{ *:[i64] }:$addr) let OutOperandList = (outs); let InOperandList = (ins GPR64:$addr); diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index 6fd5698e7372..e460a2804c66 100644 --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -63,7 +63,6 @@ class MatcherTableEmitter { StringMap PatternPredicateMap; std::vector PatternPredicates; - DenseMap ComplexPatternMap; std::vector ComplexPatterns; @@ -84,8 +83,38 @@ class MatcherTableEmitter { } public: - MatcherTableEmitter(const CodeGenDAGPatterns &cgp) - : CGP(cgp), OpcodeCounts(Matcher::HighestKind + 1, 0) {} + MatcherTableEmitter(const Matcher *TheMatcher, const CodeGenDAGPatterns &cgp) + : CGP(cgp), OpcodeCounts(Matcher::HighestKind + 1, 0) { + // Record the usage of ComplexPattern. + DenseMap ComplexPatternUsage; + + // Iterate the whole MatcherTable once and do some statistics. + std::function Statistic = [&](const Matcher *N) { + while (N) { + if (auto *SM = dyn_cast(N)) + for (unsigned I = 0; I < SM->getNumChildren(); I++) + Statistic(SM->getChild(I)); + else if (auto *SOM = dyn_cast(N)) + for (unsigned I = 0; I < SOM->getNumCases(); I++) + Statistic(SOM->getCaseMatcher(I)); + else if (auto *STM = dyn_cast(N)) + for (unsigned I = 0; I < STM->getNumCases(); I++) + Statistic(STM->getCaseMatcher(I)); + else if (auto *CPM = dyn_cast(N)) + ++ComplexPatternUsage[&CPM->getPattern()]; + N = N->getNext(); + } + }; + Statistic(TheMatcher); + + // Sort ComplexPatterns by usage. + std::vector> ComplexPatternList( + ComplexPatternUsage.begin(), ComplexPatternUsage.end()); + sort(ComplexPatternList, + [](const auto &A, const auto &B) { return A.second > B.second; }); + for (const auto &ComplexPattern : ComplexPatternList) + ComplexPatterns.push_back(ComplexPattern.first); + } unsigned EmitMatcherList(const Matcher *N, const unsigned Indent, unsigned StartIdx, raw_ostream &OS); @@ -146,12 +175,7 @@ private: return Entry-1; } unsigned getComplexPat(const ComplexPattern &P) { - unsigned &Entry = ComplexPatternMap[&P]; - if (Entry == 0) { - ComplexPatterns.push_back(&P); - Entry = ComplexPatterns.size(); - } - return Entry-1; + return llvm::find(ComplexPatterns, &P) - ComplexPatterns.begin(); } unsigned getNodeXFormID(Record *Rec) { @@ -652,8 +676,13 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, case Matcher::CheckComplexPat: { const CheckComplexPatMatcher *CCPM = cast(N); const ComplexPattern &Pattern = CCPM->getPattern(); - OS << "OPC_CheckComplexPat, /*CP*/" << getComplexPat(Pattern) << ", /*#*/" - << CCPM->getMatchNumber() << ','; + unsigned PatternNo = getComplexPat(Pattern); + if (PatternNo < 8) + OS << "OPC_CheckComplexPat" << PatternNo << ", /*#*/" + << CCPM->getMatchNumber() << ','; + else + OS << "OPC_CheckComplexPat, /*CP*/" << PatternNo << ", /*#*/" + << CCPM->getMatchNumber() << ','; if (!OmitComments) { OS << " // " << Pattern.getSelectFunc(); @@ -665,7 +694,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, OS << " + chain result"; } OS << '\n'; - return 3; + return PatternNo < 8 ? 2 : 3; } case Matcher::CheckAndImm: { @@ -1267,7 +1296,7 @@ void llvm::EmitMatcherTable(Matcher *TheMatcher, OS << "#endif\n\n"; BeginEmitFunction(OS, "void", "SelectCode(SDNode *N)", false/*AddOverride*/); - MatcherTableEmitter MatcherEmitter(CGP); + MatcherTableEmitter MatcherEmitter(TheMatcher, CGP); // First we size all the children of the three kinds of matchers that have // them. This is done by sharing the code in EmitMatcher(). but we don't -- GitLab From 5c8d1238382ce3ef6004d9cbe3fe67b8342d868c Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 11 Jan 2024 15:36:21 +0800 Subject: [PATCH 419/652] [SelectionDAG] Add space-optimized forms of OPC_CheckPatternPredicate (#73319) We record the usage of each `PatternPredicate` and sort them by usage. For the top 8 `PatternPredicate`s, we will emit a `OPC_CheckPatternPredicateN` to save one byte. The old `OPC_CheckPatternPredicate2` is renamed to `OPC_CheckPatternPredicateTwoByte`. Overall this reduces the llc binary size with all in-tree targets by about 93K. --- llvm/include/llvm/CodeGen/SelectionDAGISel.h | 8 +++++ .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 34 ++++++++++++++----- llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 26 +++++++++----- 3 files changed, 51 insertions(+), 17 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index 99ce658e7eb7..e4d90f6e898f 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -159,7 +159,15 @@ public: OPC_CheckChild2Same, OPC_CheckChild3Same, OPC_CheckPatternPredicate, + OPC_CheckPatternPredicate0, + OPC_CheckPatternPredicate1, OPC_CheckPatternPredicate2, + OPC_CheckPatternPredicate3, + OPC_CheckPatternPredicate4, + OPC_CheckPatternPredicate5, + OPC_CheckPatternPredicate6, + OPC_CheckPatternPredicate7, + OPC_CheckPatternPredicateTwoByte, OPC_CheckPredicate, OPC_CheckPredicateWithOperands, OPC_CheckOpcode, diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 344dc8d8a9b6..678d273e4bd6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2697,9 +2697,14 @@ LLVM_ATTRIBUTE_ALWAYS_INLINE static bool CheckChildSame( /// CheckPatternPredicate - Implements OP_CheckPatternPredicate. LLVM_ATTRIBUTE_ALWAYS_INLINE static bool -CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, - const SelectionDAGISel &SDISel, bool TwoBytePredNo) { - unsigned PredNo = MatcherTable[MatcherIndex++]; +CheckPatternPredicate(unsigned Opcode, const unsigned char *MatcherTable, + unsigned &MatcherIndex, const SelectionDAGISel &SDISel) { + bool TwoBytePredNo = + Opcode == SelectionDAGISel::OPC_CheckPatternPredicateTwoByte; + unsigned PredNo = + TwoBytePredNo || Opcode == SelectionDAGISel::OPC_CheckPatternPredicate + ? MatcherTable[MatcherIndex++] + : Opcode - SelectionDAGISel::OPC_CheckPatternPredicate0; if (TwoBytePredNo) PredNo |= MatcherTable[MatcherIndex++] << 8; return SDISel.CheckPatternPredicate(PredNo); @@ -2851,10 +2856,16 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table, Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); return Index; case SelectionDAGISel::OPC_CheckPatternPredicate: + case SelectionDAGISel::OPC_CheckPatternPredicate0: + case SelectionDAGISel::OPC_CheckPatternPredicate1: case SelectionDAGISel::OPC_CheckPatternPredicate2: - Result = !::CheckPatternPredicate( - Table, Index, SDISel, - Table[Index - 1] == SelectionDAGISel::OPC_CheckPatternPredicate2); + case SelectionDAGISel::OPC_CheckPatternPredicate3: + case SelectionDAGISel::OPC_CheckPatternPredicate4: + case SelectionDAGISel::OPC_CheckPatternPredicate5: + case SelectionDAGISel::OPC_CheckPatternPredicate6: + case SelectionDAGISel::OPC_CheckPatternPredicate7: + case SelectionDAGISel::OPC_CheckPatternPredicateTwoByte: + Result = !::CheckPatternPredicate(Opcode, Table, Index, SDISel); return Index; case SelectionDAGISel::OPC_CheckPredicate: Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); @@ -3336,9 +3347,16 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, continue; case OPC_CheckPatternPredicate: + case OPC_CheckPatternPredicate0: + case OPC_CheckPatternPredicate1: case OPC_CheckPatternPredicate2: - if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this, - Opcode == OPC_CheckPatternPredicate2)) + case OPC_CheckPatternPredicate3: + case OPC_CheckPatternPredicate4: + case OPC_CheckPatternPredicate5: + case OPC_CheckPatternPredicate6: + case OPC_CheckPatternPredicate7: + case OPC_CheckPatternPredicateTwoByte: + if (!::CheckPatternPredicate(Opcode, MatcherTable, MatcherIndex, *this)) break; continue; case OPC_CheckPredicate: diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index e460a2804c66..a3e2facf948e 100644 --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -60,7 +60,6 @@ class MatcherTableEmitter { // all the patterns with "identical" predicates. StringMap> NodePredicatesByCodeToRun; - StringMap PatternPredicateMap; std::vector PatternPredicates; std::vector ComplexPatterns; @@ -87,6 +86,8 @@ public: : CGP(cgp), OpcodeCounts(Matcher::HighestKind + 1, 0) { // Record the usage of ComplexPattern. DenseMap ComplexPatternUsage; + // Record the usage of PatternPredicate. + std::map PatternPredicateUsage; // Iterate the whole MatcherTable once and do some statistics. std::function Statistic = [&](const Matcher *N) { @@ -102,6 +103,8 @@ public: Statistic(STM->getCaseMatcher(I)); else if (auto *CPM = dyn_cast(N)) ++ComplexPatternUsage[&CPM->getPattern()]; + else if (auto *CPPM = dyn_cast(N)) + ++PatternPredicateUsage[CPPM->getPredicate()]; N = N->getNext(); } }; @@ -114,6 +117,14 @@ public: [](const auto &A, const auto &B) { return A.second > B.second; }); for (const auto &ComplexPattern : ComplexPatternList) ComplexPatterns.push_back(ComplexPattern.first); + + // Sort PatternPredicates by usage. + std::vector> PatternPredicateList( + PatternPredicateUsage.begin(), PatternPredicateUsage.end()); + sort(PatternPredicateList, + [](const auto &A, const auto &B) { return A.second > B.second; }); + for (const auto &PatternPredicate : PatternPredicateList) + PatternPredicates.push_back(PatternPredicate.first); } unsigned EmitMatcherList(const Matcher *N, const unsigned Indent, @@ -167,12 +178,7 @@ private: } unsigned getPatternPredicate(StringRef PredName) { - unsigned &Entry = PatternPredicateMap[PredName]; - if (Entry == 0) { - PatternPredicates.push_back(PredName.str()); - Entry = PatternPredicates.size(); - } - return Entry-1; + return llvm::find(PatternPredicates, PredName) - PatternPredicates.begin(); } unsigned getComplexPat(const ComplexPattern &P) { return llvm::find(ComplexPatterns, &P) - ComplexPatterns.begin(); @@ -510,13 +516,15 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, StringRef Pred = cast(N)->getPredicate(); unsigned PredNo = getPatternPredicate(Pred); if (PredNo > 255) - OS << "OPC_CheckPatternPredicate2, TARGET_VAL(" << PredNo << "),"; + OS << "OPC_CheckPatternPredicateTwoByte, TARGET_VAL(" << PredNo << "),"; + else if (PredNo < 8) + OS << "OPC_CheckPatternPredicate" << PredNo << ','; else OS << "OPC_CheckPatternPredicate, " << PredNo << ','; if (!OmitComments) OS << " // " << Pred; OS << '\n'; - return 2 + (PredNo > 255); + return 2 + (PredNo > 255) - (PredNo < 8); } case Matcher::CheckPredicate: { TreePredicateFn Pred = cast(N)->getPredicate(); -- GitLab From 1a5792735aa0bb10e5624a438bcf7fd5091ee265 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 11 Jan 2024 15:43:40 +0800 Subject: [PATCH 420/652] [SelectionDAG] Add space-optimized forms of OPC_CheckPredicate (#73488) We record the usage of each `Predicate` and sort them by usage. For the top 8 `Predicate`s, we will emit a `PC_CheckPredicateN` to save one byte. Overall this reduces the llc binary size with all in-tree targets by about 61K. --- llvm/include/llvm/CodeGen/SelectionDAGISel.h | 8 ++ .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 30 +++++- llvm/test/TableGen/address-space-patfrags.td | 4 +- llvm/test/TableGen/predicate-patfags.td | 4 +- llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 93 ++++++++++++------- 5 files changed, 94 insertions(+), 45 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index e4d90f6e898f..dbd9b391f4a4 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -169,6 +169,14 @@ public: OPC_CheckPatternPredicate7, OPC_CheckPatternPredicateTwoByte, OPC_CheckPredicate, + OPC_CheckPredicate0, + OPC_CheckPredicate1, + OPC_CheckPredicate2, + OPC_CheckPredicate3, + OPC_CheckPredicate4, + OPC_CheckPredicate5, + OPC_CheckPredicate6, + OPC_CheckPredicate7, OPC_CheckPredicateWithOperands, OPC_CheckOpcode, OPC_SwitchOpcode, diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 678d273e4bd6..359d738d2ca0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2712,9 +2712,13 @@ CheckPatternPredicate(unsigned Opcode, const unsigned char *MatcherTable, /// CheckNodePredicate - Implements OP_CheckNodePredicate. LLVM_ATTRIBUTE_ALWAYS_INLINE static bool -CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, - const SelectionDAGISel &SDISel, SDNode *N) { - return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); +CheckNodePredicate(unsigned Opcode, const unsigned char *MatcherTable, + unsigned &MatcherIndex, const SelectionDAGISel &SDISel, + SDNode *N) { + unsigned PredNo = Opcode == SelectionDAGISel::OPC_CheckPredicate + ? MatcherTable[MatcherIndex++] + : Opcode - SelectionDAGISel::OPC_CheckPredicate0; + return SDISel.CheckNodePredicate(N, PredNo); } LLVM_ATTRIBUTE_ALWAYS_INLINE static bool @@ -2868,7 +2872,15 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table, Result = !::CheckPatternPredicate(Opcode, Table, Index, SDISel); return Index; case SelectionDAGISel::OPC_CheckPredicate: - Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); + case SelectionDAGISel::OPC_CheckPredicate0: + case SelectionDAGISel::OPC_CheckPredicate1: + case SelectionDAGISel::OPC_CheckPredicate2: + case SelectionDAGISel::OPC_CheckPredicate3: + case SelectionDAGISel::OPC_CheckPredicate4: + case SelectionDAGISel::OPC_CheckPredicate5: + case SelectionDAGISel::OPC_CheckPredicate6: + case SelectionDAGISel::OPC_CheckPredicate7: + Result = !::CheckNodePredicate(Opcode, Table, Index, SDISel, N.getNode()); return Index; case SelectionDAGISel::OPC_CheckOpcode: Result = !::CheckOpcode(Table, Index, N.getNode()); @@ -3359,8 +3371,16 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, if (!::CheckPatternPredicate(Opcode, MatcherTable, MatcherIndex, *this)) break; continue; + case SelectionDAGISel::OPC_CheckPredicate0: + case SelectionDAGISel::OPC_CheckPredicate1: + case SelectionDAGISel::OPC_CheckPredicate2: + case SelectionDAGISel::OPC_CheckPredicate3: + case SelectionDAGISel::OPC_CheckPredicate4: + case SelectionDAGISel::OPC_CheckPredicate5: + case SelectionDAGISel::OPC_CheckPredicate6: + case SelectionDAGISel::OPC_CheckPredicate7: case OPC_CheckPredicate: - if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, + if (!::CheckNodePredicate(Opcode, MatcherTable, MatcherIndex, *this, N.getNode())) break; continue; diff --git a/llvm/test/TableGen/address-space-patfrags.td b/llvm/test/TableGen/address-space-patfrags.td index 27b174b4633c..4aec6ea7e0ea 100644 --- a/llvm/test/TableGen/address-space-patfrags.td +++ b/llvm/test/TableGen/address-space-patfrags.td @@ -46,7 +46,7 @@ def inst_d : Instruction { let InOperandList = (ins GPR32:$src0, GPR32:$src1); } -// SDAG: case 2: { +// SDAG: case 1: { // SDAG-NEXT: // Predicate_pat_frag_b // SDAG-NEXT: // Predicate_truncstorei16_addrspace // SDAG-NEXT: SDNode *N = Node; @@ -69,7 +69,7 @@ def : Pat < >; -// SDAG: case 3: { +// SDAG: case 6: { // SDAG: // Predicate_pat_frag_a // SDAG-NEXT: SDNode *N = Node; // SDAG-NEXT: (void)N; diff --git a/llvm/test/TableGen/predicate-patfags.td b/llvm/test/TableGen/predicate-patfags.td index 0912b05127ef..2cf29769dc13 100644 --- a/llvm/test/TableGen/predicate-patfags.td +++ b/llvm/test/TableGen/predicate-patfags.td @@ -39,10 +39,10 @@ def TGTmul24_oneuse : PatFrag< } // SDAG: OPC_CheckOpcode, TARGET_VAL(ISD::INTRINSIC_W_CHAIN), -// SDAG: OPC_CheckPredicate, 0, // Predicate_TGTmul24_oneuse +// SDAG: OPC_CheckPredicate0, // Predicate_TGTmul24_oneuse // SDAG: OPC_CheckOpcode, TARGET_VAL(TargetISD::MUL24), -// SDAG: OPC_CheckPredicate, 0, // Predicate_TGTmul24_oneuse +// SDAG: OPC_CheckPredicate0, // Predicate_TGTmul24_oneuse // GISEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), // GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_mul24), diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index a3e2facf948e..69d040f9b85c 100644 --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -52,9 +52,8 @@ class MatcherTableEmitter { SmallVector OpcodeCounts; - DenseMap NodePredicateMap; - std::vector NodePredicates; - std::vector NodePredicatesWithOperands; + std::vector NodePredicates; + std::vector NodePredicatesWithOperands; // We de-duplicate the predicates by code string, and use this map to track // all the patterns with "identical" predicates. @@ -88,6 +87,8 @@ public: DenseMap ComplexPatternUsage; // Record the usage of PatternPredicate. std::map PatternPredicateUsage; + // Record the usage of Predicate. + DenseMap PredicateUsage; // Iterate the whole MatcherTable once and do some statistics. std::function Statistic = [&](const Matcher *N) { @@ -105,6 +106,8 @@ public: ++ComplexPatternUsage[&CPM->getPattern()]; else if (auto *CPPM = dyn_cast(N)) ++PatternPredicateUsage[CPPM->getPredicate()]; + else if (auto *PM = dyn_cast(N)) + ++PredicateUsage[PM->getPredicate().getOrigPatFragRecord()]; N = N->getNext(); } }; @@ -125,6 +128,39 @@ public: [](const auto &A, const auto &B) { return A.second > B.second; }); for (const auto &PatternPredicate : PatternPredicateList) PatternPredicates.push_back(PatternPredicate.first); + + // Sort Predicates by usage. + // Merge predicates with same code. + for (const auto &Usage : PredicateUsage) { + TreePattern *TP = Usage.first; + TreePredicateFn Pred(TP); + NodePredicatesByCodeToRun[Pred.getCodeToRunOnSDNode()].push_back(TP); + } + + std::vector> PredicateList; + // Sum the usage. + for (auto &Predicate : NodePredicatesByCodeToRun) { + TinyPtrVector &TPs = Predicate.second; + sort(TPs, [](const auto *A, const auto *B) { + return A->getRecord()->getName() < B->getRecord()->getName(); + }); + unsigned Uses = 0; + for (TreePattern *TP : TPs) + Uses += PredicateUsage.at(TP); + + // We only add the first predicate here since they are with the same code. + PredicateList.push_back({TPs[0], Uses}); + } + + sort(PredicateList, + [](const auto &A, const auto &B) { return A.second > B.second; }); + for (const auto &Predicate : PredicateList) { + TreePattern *TP = Predicate.first; + if (TreePredicateFn(TP).usesOperands()) + NodePredicatesWithOperands.push_back(TP); + else + NodePredicates.push_back(TP); + } } unsigned EmitMatcherList(const Matcher *N, const unsigned Indent, @@ -139,7 +175,7 @@ public: void EmitPatternMatchTable(raw_ostream &OS); private: - void EmitNodePredicatesFunction(const std::vector &Preds, + void EmitNodePredicatesFunction(const std::vector &Preds, StringRef Decl, raw_ostream &OS); unsigned SizeMatcher(Matcher *N, raw_ostream &OS); @@ -148,33 +184,13 @@ private: raw_ostream &OS); unsigned getNodePredicate(TreePredicateFn Pred) { - TreePattern *TP = Pred.getOrigPatFragRecord(); - unsigned &Entry = NodePredicateMap[TP]; - if (Entry == 0) { - TinyPtrVector &SameCodePreds = - NodePredicatesByCodeToRun[Pred.getCodeToRunOnSDNode()]; - if (SameCodePreds.empty()) { - // We've never seen a predicate with the same code: allocate an entry. - if (Pred.usesOperands()) { - NodePredicatesWithOperands.push_back(Pred); - Entry = NodePredicatesWithOperands.size(); - } else { - NodePredicates.push_back(Pred); - Entry = NodePredicates.size(); - } - } else { - // We did see an identical predicate: re-use it. - Entry = NodePredicateMap[SameCodePreds.front()]; - assert(Entry != 0); - assert(TreePredicateFn(SameCodePreds.front()).usesOperands() == - Pred.usesOperands() && - "PatFrags with some code must have same usesOperands setting"); - } - // In both cases, we've never seen this particular predicate before, so - // mark it in the list of predicates sharing the same code. - SameCodePreds.push_back(TP); - } - return Entry-1; + // We use the first predicate. + TreePattern *PredPat = + NodePredicatesByCodeToRun[Pred.getCodeToRunOnSDNode()][0]; + return Pred.usesOperands() + ? llvm::find(NodePredicatesWithOperands, PredPat) - + NodePredicatesWithOperands.begin() + : llvm::find(NodePredicates, PredPat) - NodePredicates.begin(); } unsigned getPatternPredicate(StringRef PredName) { @@ -529,6 +545,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, case Matcher::CheckPredicate: { TreePredicateFn Pred = cast(N)->getPredicate(); unsigned OperandBytes = 0; + unsigned PredNo = getNodePredicate(Pred); if (Pred.usesOperands()) { unsigned NumOps = cast(N)->getNumOperands(); @@ -537,10 +554,15 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, OS << cast(N)->getOperandNo(i) << ", "; OperandBytes = 1 + NumOps; } else { - OS << "OPC_CheckPredicate, "; + if (PredNo < 8) { + OperandBytes = -1; + OS << "OPC_CheckPredicate" << PredNo << ", "; + } else + OS << "OPC_CheckPredicate, "; } - OS << getNodePredicate(Pred) << ','; + if (PredNo >= 8 || Pred.usesOperands()) + OS << PredNo << ','; if (!OmitComments) OS << " // " << Pred.getFnName(); OS << '\n'; @@ -1029,8 +1051,7 @@ EmitMatcherList(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, } void MatcherTableEmitter::EmitNodePredicatesFunction( - const std::vector &Preds, StringRef Decl, - raw_ostream &OS) { + const std::vector &Preds, StringRef Decl, raw_ostream &OS) { if (Preds.empty()) return; @@ -1040,7 +1061,7 @@ void MatcherTableEmitter::EmitNodePredicatesFunction( OS << " default: llvm_unreachable(\"Invalid predicate in table?\");\n"; for (unsigned i = 0, e = Preds.size(); i != e; ++i) { // Emit the predicate code corresponding to this pattern. - const TreePredicateFn PredFn = Preds[i]; + TreePredicateFn PredFn(Preds[i]); assert(!PredFn.isAlwaysTrue() && "No code in this predicate"); std::string PredFnCodeStr = PredFn.getCodeToRunOnSDNode(); -- GitLab From 3643d11988d6b14171b4320cbdfb15aba9764d0b Mon Sep 17 00:00:00 2001 From: jeanPerier Date: Thu, 11 Jan 2024 08:50:35 +0100 Subject: [PATCH 421/652] [flang][hlfir] Support box in user defined assignments (#77578) When dealing with overlaps in user defined assignments, some entities with descriptors (fir.box) may be saved without descriptors. The current code was replacing the original box entity with the "raw" copy with a simple cast instead of creating a box for the copy. This patch ensures a fir.embox is emitted instead. --- .../LowerHLFIROrderedAssignments.cpp | 8 +++++++ .../user-defined-assignment.fir | 23 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp index c4aee7d39e4a..84101353a740 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp @@ -421,6 +421,14 @@ convertToMoldType(mlir::Location loc, fir::FirOpBuilder &builder, } // Variable to Variable mismatch (e.g., fir.heap vs fir.ref), or value // to Value mismatch (e.g. i1 vs fir.logical<4>). + if (mlir::isa(mold.getType()) && + !mlir::isa(input.getType())) { + // An entity may have have been saved without descriptor while the original + // value had a descriptor (e.g., it was not contiguous). + auto emboxed = hlfir::convertToBox(loc, builder, input, mold.getType()); + assert(!emboxed.second && "temp should already be in memory"); + input = hlfir::Entity{fir::getBase(emboxed.first)}; + } return hlfir::Entity{builder.createConvert(loc, mold.getType(), input)}; } diff --git a/flang/test/HLFIR/order_assignments/user-defined-assignment.fir b/flang/test/HLFIR/order_assignments/user-defined-assignment.fir index 521288d0cfa1..61836b8bcc57 100644 --- a/flang/test/HLFIR/order_assignments/user-defined-assignment.fir +++ b/flang/test/HLFIR/order_assignments/user-defined-assignment.fir @@ -180,3 +180,26 @@ func.func @test_scalar_forall_overlap(%i: !fir.ref>) { // CHECK: fir.call @logical_value_to_numeric(%[[VAL_32]], %[[VAL_33]]) : (!fir.ref, !fir.logical<4>) -> () // CHECK: } // CHECK: fir.freemem %[[VAL_15]] : !fir.heap> + +func.func @test_saved_scalar_box(%arg0: !fir.box>, %arg1: !fir.class>) { + hlfir.region_assign { + hlfir.yield %arg0 : !fir.box> + } to { + hlfir.yield %arg1 : !fir.class> + } user_defined_assign (%arg2: !fir.box>) to (%arg3: !fir.class>) { + fir.call @user_assign_box(%arg3, %arg2) : (!fir.class>, !fir.box>) -> () + } + return +} +func.func private @user_assign_box(!fir.class>, !fir.box>) -> () + +// CHECK-LABEL: func.func @test_saved_scalar_box( +// CHECK-SAME: %[[VAL_0:.*]]: !fir.box>, +// CHECK-SAME: %[[VAL_1:.*]]: !fir.class>) { +// CHECK: %[[VAL_2:.*]] = hlfir.as_expr %[[VAL_0]] : (!fir.box>) -> !hlfir.expr> +// CHECK: %[[VAL_3:.*]]:3 = hlfir.associate %[[VAL_2]] +// CHECK: %[[VAL_4:.*]] = fir.embox %[[VAL_3]]#1 : (!fir.ref>) -> !fir.box> +// CHECK: fir.call @user_assign_box(%[[VAL_1]], %[[VAL_4]]) : (!fir.class>, !fir.box>) -> () +// CHECK: hlfir.end_associate %[[VAL_3]]#1, %[[VAL_3]]#2 : !fir.ref>, i1 +// CHECK: return +// CHECK: } -- GitLab From e3993e044ec5925e59c131f798f823a9f16f0433 Mon Sep 17 00:00:00 2001 From: Timm Baeder Date: Thu, 11 Jan 2024 09:02:24 +0100 Subject: [PATCH 422/652] [clang][Interp] Implement __builtin_addressof (#77303) We don't need to do anything here, since the input is already a Pointer. The only complexity is that we pre-classify the parameters as PT_Ptr, but they might end up being of a different pointer type, e.g. PT_FnPtr. --- clang/lib/AST/Interp/Interp.cpp | 12 ++++++++++ clang/lib/AST/Interp/InterpBuiltin.cpp | 33 +++++++++++++++++++++++--- clang/test/AST/Interp/functions.cpp | 24 +++++++++++++++++++ 3 files changed, 66 insertions(+), 3 deletions(-) diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index 21ea2503b94b..9de0926b9dba 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -134,6 +134,18 @@ void cleanupAfterFunctionCall(InterpState &S, CodePtr OpPC) { if (CurFunc->isUnevaluatedBuiltin()) return; + // Some builtin functions require us to only look at the call site, since + // the classified parameter types do not match. + if (CurFunc->isBuiltin()) { + const auto *CE = + cast(S.Current->Caller->getExpr(S.Current->getRetPC())); + for (int32_t I = CE->getNumArgs() - 1; I >= 0; --I) { + const Expr *A = CE->getArg(I); + popArg(S, A); + } + return; + } + if (S.Current->Caller && CurFunc->isVariadic()) { // CallExpr we're look for is at the return PC of the current function, i.e. // in the caller. diff --git a/clang/lib/AST/Interp/InterpBuiltin.cpp b/clang/lib/AST/Interp/InterpBuiltin.cpp index b55b1569a259..754ca96b0c64 100644 --- a/clang/lib/AST/Interp/InterpBuiltin.cpp +++ b/clang/lib/AST/Interp/InterpBuiltin.cpp @@ -164,6 +164,8 @@ static bool retPrimValue(InterpState &S, CodePtr OpPC, APValue &Result, case X: \ return Ret(S, OpPC, Result); switch (*T) { + RET_CASE(PT_Ptr); + RET_CASE(PT_FnPtr); RET_CASE(PT_Float); RET_CASE(PT_Bool); RET_CASE(PT_Sint8); @@ -613,15 +615,34 @@ static bool interp__builtin_ffs(InterpState &S, CodePtr OpPC, return true; } +static bool interp__builtin_addressof(InterpState &S, CodePtr OpPC, + const InterpFrame *Frame, + const Function *Func, + const CallExpr *Call) { + PrimType PtrT = + S.getContext().classify(Call->getArg(0)->getType()).value_or(PT_Ptr); + + if (PtrT == PT_FnPtr) { + const FunctionPointer &Arg = S.Stk.peek(); + S.Stk.push(Arg); + } else if (PtrT == PT_Ptr) { + const Pointer &Arg = S.Stk.peek(); + S.Stk.push(Arg); + } else { + assert(false && "Unsupported pointer type passed to __builtin_addressof()"); + } + return true; +} + bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F, const CallExpr *Call) { InterpFrame *Frame = S.Current; APValue Dummy; - QualType ReturnType = Call->getCallReturnType(S.getCtx()); - std::optional ReturnT = S.getContext().classify(ReturnType); + std::optional ReturnT = S.getContext().classify(Call->getType()); + // If classify failed, we assume void. - assert(ReturnT || ReturnType->isVoidType()); + assert(ReturnT || Call->getType()->isVoidType()); switch (F->getBuiltinID()) { case Builtin::BI__builtin_is_constant_evaluated: @@ -820,6 +841,12 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F, if (!interp__builtin_ffs(S, OpPC, Frame, F, Call)) return false; break; + case Builtin::BIaddressof: + case Builtin::BI__addressof: + case Builtin::BI__builtin_addressof: + if (!interp__builtin_addressof(S, OpPC, Frame, F, Call)) + return false; + break; default: return false; diff --git a/clang/test/AST/Interp/functions.cpp b/clang/test/AST/Interp/functions.cpp index 179a195098b1..75f3c5d192b2 100644 --- a/clang/test/AST/Interp/functions.cpp +++ b/clang/test/AST/Interp/functions.cpp @@ -389,3 +389,27 @@ namespace Packs { static_assert(foo() == 2, ""); static_assert(foo<>() == 0, ""); } + +namespace AddressOf { + struct S {} s; + static_assert(__builtin_addressof(s) == &s, ""); + + struct T { constexpr T *operator&() const { return nullptr; } int n; } t; + constexpr T *pt = __builtin_addressof(t); + static_assert(&pt->n == &t.n, ""); + + struct U { int n : 5; } u; + int *pbf = __builtin_addressof(u.n); // expected-error {{address of bit-field requested}} \ + // ref-error {{address of bit-field requested}} + + S *ptmp = __builtin_addressof(S{}); // expected-error {{taking the address of a temporary}} \ + // expected-warning {{temporary whose address is used as value of local variable 'ptmp' will be destroyed at the end of the full-expression}} \ + // ref-error {{taking the address of a temporary}} \ + // ref-warning {{temporary whose address is used as value of local variable 'ptmp' will be destroyed at the end of the full-expression}} + + constexpr int foo() {return 1;} + static_assert(__builtin_addressof(foo) == foo, ""); + + constexpr _Complex float F = {3, 4}; + static_assert(__builtin_addressof(F) == &F, ""); +} -- GitLab From 79889fedc57707e99740abc1f48e6c5601d5a3f3 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Thu, 11 Jan 2024 15:07:24 +0700 Subject: [PATCH 423/652] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (#77645) We have two structs for representing the version of an extension in RISCVISAInfo, RISCVExtensionInfo and RISCVExtensionVersion, both with the exact same fields. This patch deduplicates them. --- clang/lib/Basic/Targets/RISCV.cpp | 5 +- lld/ELF/Arch/RISCV.cpp | 4 +- llvm/include/llvm/Support/RISCVISAInfo.h | 16 +- llvm/lib/Support/RISCVISAInfo.cpp | 331 ++++++++++---------- llvm/unittests/Support/RISCVISAInfoTest.cpp | 86 ++--- 5 files changed, 221 insertions(+), 221 deletions(-) diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index daaa8639ae83..fb312b6cf26e 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -163,9 +163,8 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, auto ExtName = Extension.first; auto ExtInfo = Extension.second; - Builder.defineMacro( - Twine("__riscv_", ExtName), - Twine(getVersionValue(ExtInfo.MajorVersion, ExtInfo.MinorVersion))); + Builder.defineMacro(Twine("__riscv_", ExtName), + Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor))); } if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul")) diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 62498ded1a2b..8906de073735 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -957,8 +957,8 @@ static void mergeArch(RISCVISAInfo::OrderedExtensionMap &mergedExts, } else { for (const auto &ext : info.getExtensions()) { if (auto it = mergedExts.find(ext.first); it != mergedExts.end()) { - if (std::tie(it->second.MajorVersion, it->second.MinorVersion) >= - std::tie(ext.second.MajorVersion, ext.second.MinorVersion)) + if (std::tie(it->second.Major, it->second.Minor) >= + std::tie(ext.second.Major, ext.second.Minor)) continue; } mergedExts[ext.first] = ext.second; diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h index 97f1051b0540..46df93d75226 100644 --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/Support/RISCVISAInfo.h @@ -18,11 +18,6 @@ #include namespace llvm { -struct RISCVExtensionInfo { - unsigned MajorVersion; - unsigned MinorVersion; -}; - void riscvExtensionsHelp(StringMap DescMap); class RISCVISAInfo { @@ -30,6 +25,12 @@ public: RISCVISAInfo(const RISCVISAInfo &) = delete; RISCVISAInfo &operator=(const RISCVISAInfo &) = delete; + /// Represents the major and version number components of a RISC-V extension. + struct ExtensionVersion { + unsigned Major; + unsigned Minor; + }; + static bool compareExtension(const std::string &LHS, const std::string &RHS); /// Helper class for OrderedExtensionMap. @@ -41,7 +42,7 @@ public: /// OrderedExtensionMap is std::map, it's specialized to keep entries /// in canonical order of extension. - typedef std::map + typedef std::map OrderedExtensionMap; RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts) @@ -104,8 +105,7 @@ private: OrderedExtensionMap Exts; - void addExtension(StringRef ExtName, unsigned MajorVersion, - unsigned MinorVersion); + void addExtension(StringRef ExtName, ExtensionVersion Version); Error checkDependency(); diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 70f531e40b90..390d950486a7 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -24,16 +24,11 @@ using namespace llvm; namespace { -/// Represents the major and version number components of a RISC-V extension -struct RISCVExtensionVersion { - unsigned Major; - unsigned Minor; -}; struct RISCVSupportedExtension { const char *Name; /// Supported version. - RISCVExtensionVersion Version; + RISCVISAInfo::ExtensionVersion Version; bool operator<(const RISCVSupportedExtension &RHS) const { return StringRef(Name) < StringRef(RHS.Name); @@ -50,161 +45,161 @@ static const char *RISCVGImplications[] = { // NOTE: This table should be sorted alphabetically by extension name. static const RISCVSupportedExtension SupportedExtensions[] = { - {"a", RISCVExtensionVersion{2, 1}}, - {"c", RISCVExtensionVersion{2, 0}}, - {"d", RISCVExtensionVersion{2, 2}}, - {"e", RISCVExtensionVersion{2, 0}}, - {"f", RISCVExtensionVersion{2, 2}}, - {"h", RISCVExtensionVersion{1, 0}}, - {"i", RISCVExtensionVersion{2, 1}}, - {"m", RISCVExtensionVersion{2, 0}}, - - {"smaia", RISCVExtensionVersion{1, 0}}, - {"ssaia", RISCVExtensionVersion{1, 0}}, - {"svinval", RISCVExtensionVersion{1, 0}}, - {"svnapot", RISCVExtensionVersion{1, 0}}, - {"svpbmt", RISCVExtensionVersion{1, 0}}, - - {"v", RISCVExtensionVersion{1, 0}}, + {"a", {2, 1}}, + {"c", {2, 0}}, + {"d", {2, 2}}, + {"e", {2, 0}}, + {"f", {2, 2}}, + {"h", {1, 0}}, + {"i", {2, 1}}, + {"m", {2, 0}}, + + {"smaia", {1, 0}}, + {"ssaia", {1, 0}}, + {"svinval", {1, 0}}, + {"svnapot", {1, 0}}, + {"svpbmt", {1, 0}}, + + {"v", {1, 0}}, // vendor-defined ('X') extensions - {"xcvalu", RISCVExtensionVersion{1, 0}}, - {"xcvbi", RISCVExtensionVersion{1, 0}}, - {"xcvbitmanip", RISCVExtensionVersion{1, 0}}, - {"xcvelw", RISCVExtensionVersion{1, 0}}, - {"xcvmac", RISCVExtensionVersion{1, 0}}, - {"xcvmem", RISCVExtensionVersion{1, 0}}, - {"xcvsimd", RISCVExtensionVersion{1, 0}}, - {"xsfvcp", RISCVExtensionVersion{1, 0}}, - {"xsfvfnrclipxfqf", RISCVExtensionVersion{1, 0}}, - {"xsfvfwmaccqqq", RISCVExtensionVersion{1, 0}}, - {"xsfvqmaccdod", RISCVExtensionVersion{1, 0}}, - {"xsfvqmaccqoq", RISCVExtensionVersion{1, 0}}, - {"xtheadba", RISCVExtensionVersion{1, 0}}, - {"xtheadbb", RISCVExtensionVersion{1, 0}}, - {"xtheadbs", RISCVExtensionVersion{1, 0}}, - {"xtheadcmo", RISCVExtensionVersion{1, 0}}, - {"xtheadcondmov", RISCVExtensionVersion{1, 0}}, - {"xtheadfmemidx", RISCVExtensionVersion{1, 0}}, - {"xtheadmac", RISCVExtensionVersion{1, 0}}, - {"xtheadmemidx", RISCVExtensionVersion{1, 0}}, - {"xtheadmempair", RISCVExtensionVersion{1, 0}}, - {"xtheadsync", RISCVExtensionVersion{1, 0}}, - {"xtheadvdot", RISCVExtensionVersion{1, 0}}, - {"xventanacondops", RISCVExtensionVersion{1, 0}}, - - {"zawrs", RISCVExtensionVersion{1, 0}}, - - {"zba", RISCVExtensionVersion{1, 0}}, - {"zbb", RISCVExtensionVersion{1, 0}}, - {"zbc", RISCVExtensionVersion{1, 0}}, - {"zbkb", RISCVExtensionVersion{1, 0}}, - {"zbkc", RISCVExtensionVersion{1, 0}}, - {"zbkx", RISCVExtensionVersion{1, 0}}, - {"zbs", RISCVExtensionVersion{1, 0}}, - - {"zca", RISCVExtensionVersion{1, 0}}, - {"zcb", RISCVExtensionVersion{1, 0}}, - {"zcd", RISCVExtensionVersion{1, 0}}, - {"zce", RISCVExtensionVersion{1, 0}}, - {"zcf", RISCVExtensionVersion{1, 0}}, - {"zcmp", RISCVExtensionVersion{1, 0}}, - {"zcmt", RISCVExtensionVersion{1, 0}}, - - {"zdinx", RISCVExtensionVersion{1, 0}}, - - {"zfa", RISCVExtensionVersion{1, 0}}, - {"zfh", RISCVExtensionVersion{1, 0}}, - {"zfhmin", RISCVExtensionVersion{1, 0}}, - {"zfinx", RISCVExtensionVersion{1, 0}}, - - {"zhinx", RISCVExtensionVersion{1, 0}}, - {"zhinxmin", RISCVExtensionVersion{1, 0}}, - - {"zicbom", RISCVExtensionVersion{1, 0}}, - {"zicbop", RISCVExtensionVersion{1, 0}}, - {"zicboz", RISCVExtensionVersion{1, 0}}, - {"zicntr", RISCVExtensionVersion{2, 0}}, - {"zicsr", RISCVExtensionVersion{2, 0}}, - {"zifencei", RISCVExtensionVersion{2, 0}}, - {"zihintntl", RISCVExtensionVersion{1, 0}}, - {"zihintpause", RISCVExtensionVersion{2, 0}}, - {"zihpm", RISCVExtensionVersion{2, 0}}, - - {"zk", RISCVExtensionVersion{1, 0}}, - {"zkn", RISCVExtensionVersion{1, 0}}, - {"zknd", RISCVExtensionVersion{1, 0}}, - {"zkne", RISCVExtensionVersion{1, 0}}, - {"zknh", RISCVExtensionVersion{1, 0}}, - {"zkr", RISCVExtensionVersion{1, 0}}, - {"zks", RISCVExtensionVersion{1, 0}}, - {"zksed", RISCVExtensionVersion{1, 0}}, - {"zksh", RISCVExtensionVersion{1, 0}}, - {"zkt", RISCVExtensionVersion{1, 0}}, - - {"zmmul", RISCVExtensionVersion{1, 0}}, - - {"zvbb", RISCVExtensionVersion{1, 0}}, - {"zvbc", RISCVExtensionVersion{1, 0}}, - - {"zve32f", RISCVExtensionVersion{1, 0}}, - {"zve32x", RISCVExtensionVersion{1, 0}}, - {"zve64d", RISCVExtensionVersion{1, 0}}, - {"zve64f", RISCVExtensionVersion{1, 0}}, - {"zve64x", RISCVExtensionVersion{1, 0}}, - - {"zvfh", RISCVExtensionVersion{1, 0}}, - {"zvfhmin", RISCVExtensionVersion{1, 0}}, + {"xcvalu", {1, 0}}, + {"xcvbi", {1, 0}}, + {"xcvbitmanip", {1, 0}}, + {"xcvelw", {1, 0}}, + {"xcvmac", {1, 0}}, + {"xcvmem", {1, 0}}, + {"xcvsimd", {1, 0}}, + {"xsfvcp", {1, 0}}, + {"xsfvfnrclipxfqf", {1, 0}}, + {"xsfvfwmaccqqq", {1, 0}}, + {"xsfvqmaccdod", {1, 0}}, + {"xsfvqmaccqoq", {1, 0}}, + {"xtheadba", {1, 0}}, + {"xtheadbb", {1, 0}}, + {"xtheadbs", {1, 0}}, + {"xtheadcmo", {1, 0}}, + {"xtheadcondmov", {1, 0}}, + {"xtheadfmemidx", {1, 0}}, + {"xtheadmac", {1, 0}}, + {"xtheadmemidx", {1, 0}}, + {"xtheadmempair", {1, 0}}, + {"xtheadsync", {1, 0}}, + {"xtheadvdot", {1, 0}}, + {"xventanacondops", {1, 0}}, + + {"zawrs", {1, 0}}, + + {"zba", {1, 0}}, + {"zbb", {1, 0}}, + {"zbc", {1, 0}}, + {"zbkb", {1, 0}}, + {"zbkc", {1, 0}}, + {"zbkx", {1, 0}}, + {"zbs", {1, 0}}, + + {"zca", {1, 0}}, + {"zcb", {1, 0}}, + {"zcd", {1, 0}}, + {"zce", {1, 0}}, + {"zcf", {1, 0}}, + {"zcmp", {1, 0}}, + {"zcmt", {1, 0}}, + + {"zdinx", {1, 0}}, + + {"zfa", {1, 0}}, + {"zfh", {1, 0}}, + {"zfhmin", {1, 0}}, + {"zfinx", {1, 0}}, + + {"zhinx", {1, 0}}, + {"zhinxmin", {1, 0}}, + + {"zicbom", {1, 0}}, + {"zicbop", {1, 0}}, + {"zicboz", {1, 0}}, + {"zicntr", {2, 0}}, + {"zicsr", {2, 0}}, + {"zifencei", {2, 0}}, + {"zihintntl", {1, 0}}, + {"zihintpause", {2, 0}}, + {"zihpm", {2, 0}}, + + {"zk", {1, 0}}, + {"zkn", {1, 0}}, + {"zknd", {1, 0}}, + {"zkne", {1, 0}}, + {"zknh", {1, 0}}, + {"zkr", {1, 0}}, + {"zks", {1, 0}}, + {"zksed", {1, 0}}, + {"zksh", {1, 0}}, + {"zkt", {1, 0}}, + + {"zmmul", {1, 0}}, + + {"zvbb", {1, 0}}, + {"zvbc", {1, 0}}, + + {"zve32f", {1, 0}}, + {"zve32x", {1, 0}}, + {"zve64d", {1, 0}}, + {"zve64f", {1, 0}}, + {"zve64x", {1, 0}}, + + {"zvfh", {1, 0}}, + {"zvfhmin", {1, 0}}, // vector crypto - {"zvkb", RISCVExtensionVersion{1, 0}}, - {"zvkg", RISCVExtensionVersion{1, 0}}, - {"zvkn", RISCVExtensionVersion{1, 0}}, - {"zvknc", RISCVExtensionVersion{1, 0}}, - {"zvkned", RISCVExtensionVersion{1, 0}}, - {"zvkng", RISCVExtensionVersion{1, 0}}, - {"zvknha", RISCVExtensionVersion{1, 0}}, - {"zvknhb", RISCVExtensionVersion{1, 0}}, - {"zvks", RISCVExtensionVersion{1, 0}}, - {"zvksc", RISCVExtensionVersion{1, 0}}, - {"zvksed", RISCVExtensionVersion{1, 0}}, - {"zvksg", RISCVExtensionVersion{1, 0}}, - {"zvksh", RISCVExtensionVersion{1, 0}}, - {"zvkt", RISCVExtensionVersion{1, 0}}, - - {"zvl1024b", RISCVExtensionVersion{1, 0}}, - {"zvl128b", RISCVExtensionVersion{1, 0}}, - {"zvl16384b", RISCVExtensionVersion{1, 0}}, - {"zvl2048b", RISCVExtensionVersion{1, 0}}, - {"zvl256b", RISCVExtensionVersion{1, 0}}, - {"zvl32768b", RISCVExtensionVersion{1, 0}}, - {"zvl32b", RISCVExtensionVersion{1, 0}}, - {"zvl4096b", RISCVExtensionVersion{1, 0}}, - {"zvl512b", RISCVExtensionVersion{1, 0}}, - {"zvl64b", RISCVExtensionVersion{1, 0}}, - {"zvl65536b", RISCVExtensionVersion{1, 0}}, - {"zvl8192b", RISCVExtensionVersion{1, 0}}, + {"zvkb", {1, 0}}, + {"zvkg", {1, 0}}, + {"zvkn", {1, 0}}, + {"zvknc", {1, 0}}, + {"zvkned", {1, 0}}, + {"zvkng", {1, 0}}, + {"zvknha", {1, 0}}, + {"zvknhb", {1, 0}}, + {"zvks", {1, 0}}, + {"zvksc", {1, 0}}, + {"zvksed", {1, 0}}, + {"zvksg", {1, 0}}, + {"zvksh", {1, 0}}, + {"zvkt", {1, 0}}, + + {"zvl1024b", {1, 0}}, + {"zvl128b", {1, 0}}, + {"zvl16384b", {1, 0}}, + {"zvl2048b", {1, 0}}, + {"zvl256b", {1, 0}}, + {"zvl32768b", {1, 0}}, + {"zvl32b", {1, 0}}, + {"zvl4096b", {1, 0}}, + {"zvl512b", {1, 0}}, + {"zvl64b", {1, 0}}, + {"zvl65536b", {1, 0}}, + {"zvl8192b", {1, 0}}, }; // NOTE: This table should be sorted alphabetically by extension name. static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { - {"zacas", RISCVExtensionVersion{1, 0}}, + {"zacas", {1, 0}}, - {"zcmop", RISCVExtensionVersion{0, 2}}, + {"zcmop", {0, 2}}, - {"zfbfmin", RISCVExtensionVersion{0, 8}}, + {"zfbfmin", {0, 8}}, - {"zicfilp", RISCVExtensionVersion{0, 4}}, - {"zicfiss", RISCVExtensionVersion{0, 4}}, + {"zicfilp", {0, 4}}, + {"zicfiss", {0, 4}}, - {"zicond", RISCVExtensionVersion{1, 0}}, + {"zicond", {1, 0}}, - {"zimop", RISCVExtensionVersion{0, 1}}, + {"zimop", {0, 1}}, - {"ztso", RISCVExtensionVersion{0, 1}}, + {"ztso", {0, 1}}, - {"zvfbfmin", RISCVExtensionVersion{0, 8}}, - {"zvfbfwma", RISCVExtensionVersion{0, 8}}, + {"zvfbfmin", {0, 8}}, + {"zvfbfwma", {0, 8}}, }; static void verifyTables() { @@ -237,8 +232,8 @@ void llvm::riscvExtensionsHelp(StringMap DescMap) { for (const auto &E : SupportedExtensions) ExtMap[E.Name] = {E.Version.Major, E.Version.Minor}; for (const auto &E : ExtMap) { - std::string Version = std::to_string(E.second.MajorVersion) + "." + - std::to_string(E.second.MinorVersion); + std::string Version = + std::to_string(E.second.Major) + "." + std::to_string(E.second.Minor); PrintExtension(E.first, Version, DescMap[E.first]); } @@ -247,8 +242,8 @@ void llvm::riscvExtensionsHelp(StringMap DescMap) { for (const auto &E : SupportedExperimentalExtensions) ExtMap[E.Name] = {E.Version.Major, E.Version.Minor}; for (const auto &E : ExtMap) { - std::string Version = std::to_string(E.second.MajorVersion) + "." + - std::to_string(E.second.MinorVersion); + std::string Version = + std::to_string(E.second.Major) + "." + std::to_string(E.second.Minor); PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); } @@ -293,7 +288,7 @@ struct LessExtName { }; } // namespace -static std::optional +static std::optional findDefaultVersion(StringRef ExtName) { // Find default version of an extension. // TODO: We might set default version based on profile or ISA spec. @@ -309,12 +304,9 @@ findDefaultVersion(StringRef ExtName) { return std::nullopt; } -void RISCVISAInfo::addExtension(StringRef ExtName, unsigned MajorVersion, - unsigned MinorVersion) { - RISCVExtensionInfo Ext; - Ext.MajorVersion = MajorVersion; - Ext.MinorVersion = MinorVersion; - Exts[ExtName.str()] = Ext; +void RISCVISAInfo::addExtension(StringRef ExtName, + RISCVISAInfo::ExtensionVersion Version) { + Exts[ExtName.str()] = Version; } static StringRef getExtensionTypeDesc(StringRef Ext) { @@ -337,7 +329,7 @@ static StringRef getExtensionType(StringRef Ext) { return StringRef(); } -static std::optional +static std::optional isExperimentalExtension(StringRef Ext) { auto I = llvm::lower_bound(SupportedExperimentalExtensions, Ext, LessExtName()); @@ -634,8 +626,7 @@ RISCVISAInfo::parseFeatures(unsigned XLen, continue; if (Add) - ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major, - ExtensionInfoIterator->Version.Minor); + ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version); else ISAInfo->Exts.erase(ExtName.str()); } @@ -696,7 +687,7 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { if (MajorVersionStr.getAsInteger(10, MajorVersion)) return createStringError(errc::invalid_argument, "failed to parse major version number"); - ISAInfo->addExtension(ExtName, MajorVersion, MinorVersion); + ISAInfo->addExtension(ExtName, {MajorVersion, MinorVersion}); } ISAInfo->updateFLen(); ISAInfo->updateMinVLen(); @@ -775,7 +766,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, // ISA spec. for (const auto *Ext : RISCVGImplications) { if (auto Version = findDefaultVersion(Ext)) - ISAInfo->addExtension(Ext, Version->Major, Version->Minor); + ISAInfo->addExtension(Ext, *Version); else llvm_unreachable("Default extension version not found?"); } @@ -794,7 +785,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, Minor = Version->Minor; } - ISAInfo->addExtension(StringRef(&Baseline, 1), Major, Minor); + ISAInfo->addExtension(StringRef(&Baseline, 1), {Major, Minor}); } // Consume the base ISA version number and any '_' between rvxxx and the @@ -860,7 +851,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "unsupported standard user-level extension '%c'", C); } - ISAInfo->addExtension(StringRef(&C, 1), Major, Minor); + ISAInfo->addExtension(StringRef(&C, 1), {Major, Minor}); // Consume full extension name and version, including any optional '_' // between this extension and the next @@ -928,7 +919,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, if (IgnoreUnknown && !isSupportedExtension(Name)) continue; - ISAInfo->addExtension(Name, Major, Minor); + ISAInfo->addExtension(Name, {Major, Minor}); // Extension format is correct, keep parsing the extensions. // TODO: Save Type, Name, Major, Minor to avoid parsing them later. AllExts.push_back(Name); @@ -1143,7 +1134,7 @@ void RISCVISAInfo::updateImplication() { // implied if (!HasE && !HasI) { auto Version = findDefaultVersion("i"); - addExtension("i", Version->Major, Version->Minor); + addExtension("i", Version.value()); } assert(llvm::is_sorted(ImpliedExts) && "Table not sorted by Name"); @@ -1164,7 +1155,7 @@ void RISCVISAInfo::updateImplication() { if (Exts.count(ImpliedExt)) continue; auto Version = findDefaultVersion(ImpliedExt); - addExtension(ImpliedExt, Version->Major, Version->Minor); + addExtension(ImpliedExt, Version.value()); WorkList.insert(ImpliedExt); } } @@ -1174,7 +1165,7 @@ void RISCVISAInfo::updateImplication() { if (XLen == 32 && Exts.count("zce") && Exts.count("f") && !Exts.count("zcf")) { auto Version = findDefaultVersion("zcf"); - addExtension("zcf", Version->Major, Version->Minor); + addExtension("zcf", Version.value()); } } @@ -1209,7 +1200,7 @@ void RISCVISAInfo::updateCombination() { IsAllRequiredFeatureExist &= hasExtension(Ext); if (IsAllRequiredFeatureExist) { auto Version = findDefaultVersion(CombineExt); - addExtension(CombineExt, Version->Major, Version->Minor); + addExtension(CombineExt, Version.value()); IsNewCombine = true; } } @@ -1266,7 +1257,7 @@ std::string RISCVISAInfo::toString() const { StringRef ExtName = Ext.first; auto ExtInfo = Ext.second; Arch << LS << ExtName; - Arch << ExtInfo.MajorVersion << "p" << ExtInfo.MinorVersion; + Arch << ExtInfo.Major << "p" << ExtInfo.Minor; } return Arch.str(); diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 42759f30fd1b..997551e5c44c 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -15,9 +15,9 @@ using ::testing::ElementsAre; using namespace llvm; -bool operator==(const llvm::RISCVExtensionInfo &A, - const llvm::RISCVExtensionInfo &B) { - return A.MajorVersion == B.MajorVersion && A.MinorVersion == B.MinorVersion; +bool operator==(const RISCVISAInfo::ExtensionVersion &A, + const RISCVISAInfo::ExtensionVersion &B) { + return A.Major == B.Major && A.Minor == B.Minor; } TEST(ParseNormalizedArchString, RejectsUpperCase) { @@ -50,28 +50,32 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) { ASSERT_THAT_EXPECTED(MaybeRV32I, Succeeded()); RISCVISAInfo &InfoRV32I = **MaybeRV32I; EXPECT_EQ(InfoRV32I.getExtensions().size(), 1UL); - EXPECT_TRUE(InfoRV32I.getExtensions().at("i") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(InfoRV32I.getExtensions().at("i") == + (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32I.getXLen(), 32U); auto MaybeRV32E = RISCVISAInfo::parseNormalizedArchString("rv32e2p0"); ASSERT_THAT_EXPECTED(MaybeRV32E, Succeeded()); RISCVISAInfo &InfoRV32E = **MaybeRV32E; EXPECT_EQ(InfoRV32E.getExtensions().size(), 1UL); - EXPECT_TRUE(InfoRV32E.getExtensions().at("e") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(InfoRV32E.getExtensions().at("e") == + (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32E.getXLen(), 32U); auto MaybeRV64I = RISCVISAInfo::parseNormalizedArchString("rv64i2p0"); ASSERT_THAT_EXPECTED(MaybeRV64I, Succeeded()); RISCVISAInfo &InfoRV64I = **MaybeRV64I; EXPECT_EQ(InfoRV64I.getExtensions().size(), 1UL); - EXPECT_TRUE(InfoRV64I.getExtensions().at("i") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(InfoRV64I.getExtensions().at("i") == + (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64I.getXLen(), 64U); auto MaybeRV64E = RISCVISAInfo::parseNormalizedArchString("rv64e2p0"); ASSERT_THAT_EXPECTED(MaybeRV64E, Succeeded()); RISCVISAInfo &InfoRV64E = **MaybeRV64E; EXPECT_EQ(InfoRV64E.getExtensions().size(), 1UL); - EXPECT_TRUE(InfoRV64E.getExtensions().at("e") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(InfoRV64E.getExtensions().at("e") == + (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64E.getXLen(), 64U); } @@ -81,12 +85,16 @@ TEST(ParseNormalizedArchString, AcceptsArbitraryExtensionsAndVersions) { ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo &Info = **MaybeISAInfo; EXPECT_EQ(Info.getExtensions().size(), 5UL); - EXPECT_TRUE(Info.getExtensions().at("i") == (RISCVExtensionInfo{5, 1})); - EXPECT_TRUE(Info.getExtensions().at("m") == (RISCVExtensionInfo{3, 2})); + EXPECT_TRUE(Info.getExtensions().at("i") == + (RISCVISAInfo::ExtensionVersion{5, 1})); + EXPECT_TRUE(Info.getExtensions().at("m") == + (RISCVISAInfo::ExtensionVersion{3, 2})); EXPECT_TRUE(Info.getExtensions().at("zmadeup") == - (RISCVExtensionInfo{11, 12})); - EXPECT_TRUE(Info.getExtensions().at("sfoo") == (RISCVExtensionInfo{2, 0})); - EXPECT_TRUE(Info.getExtensions().at("xbar") == (RISCVExtensionInfo{3, 0})); + (RISCVISAInfo::ExtensionVersion{11, 12})); + EXPECT_TRUE(Info.getExtensions().at("sfoo") == + (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(Info.getExtensions().at("xbar") == + (RISCVISAInfo::ExtensionVersion{3, 0})); } TEST(ParseNormalizedArchString, UpdatesFLenMinVLenMaxELen) { @@ -131,7 +139,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV32I = **MaybeRV32I; RISCVISAInfo::OrderedExtensionMap ExtsRV32I = InfoRV32I.getExtensions(); EXPECT_EQ(ExtsRV32I.size(), 1UL); - EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVExtensionInfo{2, 1})); + EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); EXPECT_EQ(InfoRV32I.getXLen(), 32U); EXPECT_EQ(InfoRV32I.getFLen(), 0U); @@ -140,7 +148,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV32E = **MaybeRV32E; RISCVISAInfo::OrderedExtensionMap ExtsRV32E = InfoRV32E.getExtensions(); EXPECT_EQ(ExtsRV32E.size(), 1UL); - EXPECT_TRUE(ExtsRV32E.at("e") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(ExtsRV32E.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32E.getXLen(), 32U); EXPECT_EQ(InfoRV32E.getFLen(), 0U); @@ -149,13 +157,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV32G = **MaybeRV32G; RISCVISAInfo::OrderedExtensionMap ExtsRV32G = InfoRV32G.getExtensions(); EXPECT_EQ(ExtsRV32G.size(), 7UL); - EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVExtensionInfo{2, 1})); - EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVExtensionInfo{2, 0})); - EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVExtensionInfo{2, 1})); - EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVExtensionInfo{2, 2})); - EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVExtensionInfo{2, 2})); - EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVExtensionInfo{2, 0})); - EXPECT_TRUE(ExtsRV32G.at("zifencei") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVISAInfo::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVISAInfo::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("zifencei") == + (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32G.getXLen(), 32U); EXPECT_EQ(InfoRV32G.getFLen(), 64U); @@ -164,7 +173,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV64I = **MaybeRV64I; RISCVISAInfo::OrderedExtensionMap ExtsRV64I = InfoRV64I.getExtensions(); EXPECT_EQ(ExtsRV64I.size(), 1UL); - EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVExtensionInfo{2, 1})); + EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); EXPECT_EQ(InfoRV64I.getXLen(), 64U); EXPECT_EQ(InfoRV64I.getFLen(), 0U); @@ -173,7 +182,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV64E = **MaybeRV64E; RISCVISAInfo::OrderedExtensionMap ExtsRV64E = InfoRV64E.getExtensions(); EXPECT_EQ(ExtsRV64E.size(), 1UL); - EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64E.getXLen(), 64U); EXPECT_EQ(InfoRV64E.getFLen(), 0U); @@ -182,13 +191,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV64G = **MaybeRV64G; RISCVISAInfo::OrderedExtensionMap ExtsRV64G = InfoRV64G.getExtensions(); EXPECT_EQ(ExtsRV64G.size(), 7UL); - EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVExtensionInfo{2, 1})); - EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVExtensionInfo{2, 0})); - EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVExtensionInfo{2, 1})); - EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVExtensionInfo{2, 2})); - EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVExtensionInfo{2, 2})); - EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVExtensionInfo{2, 0})); - EXPECT_TRUE(ExtsRV64G.at("zifencei") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVISAInfo::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVISAInfo::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV64G.at("zifencei") == + (RISCVISAInfo::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64G.getXLen(), 64U); EXPECT_EQ(InfoRV64G.getFLen(), 64U); } @@ -236,7 +246,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) { RISCVISAInfo &Info = **MaybeISAInfo; RISCVISAInfo::OrderedExtensionMap Exts = Info.getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); } // Checks that supported extensions aren't incorrectly ignored when a @@ -245,7 +255,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) { RISCVISAInfo::parseArchString("rv32i_zbc1p0_xmadeup", true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_TRUE(Exts.at("zbc") == (RISCVExtensionInfo{1, 0})); + EXPECT_TRUE(Exts.at("zbc") == (RISCVISAInfo::ExtensionVersion{1, 0})); } TEST(ParseArchString, AcceptsVersionInLongOrShortForm) { @@ -253,13 +263,13 @@ TEST(ParseArchString, AcceptsVersionInLongOrShortForm) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); } for (StringRef Input : {"rv32i_zfinx1", "rv32i_zfinx1p0"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_TRUE(Exts.at("zfinx") == (RISCVExtensionInfo{1, 0})); + EXPECT_TRUE(Exts.at("zfinx") == (RISCVISAInfo::ExtensionVersion{1, 0})); } } @@ -288,14 +298,14 @@ TEST(ParseArchString, ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); } for (StringRef Input : {"rv32e0p1", "rv32e99p99", "rv64e0p1", "rv64e99p99"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("e") == (RISCVExtensionInfo{2, 0})); + EXPECT_TRUE(Exts.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0})); } } @@ -306,7 +316,7 @@ TEST(ParseArchString, ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); } } @@ -396,7 +406,7 @@ TEST(ParseArchString, ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); - EXPECT_TRUE(Exts.at("zicond") == (RISCVExtensionInfo{9, 9})); + EXPECT_TRUE(Exts.at("zicond") == (RISCVISAInfo::ExtensionVersion{9, 9})); } TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) { -- GitLab From 16945bc16dbb4c4acac854001b73e1454f3b601c Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 11 Jan 2024 09:14:52 +0100 Subject: [PATCH 424/652] [AMDGPU] Don't send DEALLOC_VGPRs after calls (#77439) Calls do not have to wait for VsCnt, so after they return there might still be scratch stores in progress. It's important that we don't send the DEALLOC_VGPR message in that case, since that might release the VGPRs and scratch allocation before those stores are complete. --- llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 5 +-- .../CodeGen/AMDGPU/call-argument-types.ll | 2 -- .../CodeGen/AMDGPU/calling-conventions.ll | 4 --- .../AMDGPU/global_atomics_scan_fadd.ll | 24 -------------- .../AMDGPU/promote-constOffset-to-imm.ll | 16 ---------- llvm/test/CodeGen/AMDGPU/release-vgprs.mir | 32 +++++++++++++++++++ 6 files changed, 35 insertions(+), 48 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 1cb1d32707f2..1f480c248154 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -292,7 +292,7 @@ public: VgprVmemTypes[GprNo] = 0; } - void setNonKernelFunctionInitialState() { + void setStateOnFunctionEntryOrReturn() { setScoreUB(VS_CNT, getWaitCountMax(VS_CNT)); PendingEvents |= WaitEventMaskForInst[VS_CNT]; } @@ -1487,6 +1487,7 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst, if (callWaitsOnFunctionReturn(Inst)) { // Act as a wait on everything ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt::allZeroExceptVsCnt()); + ScoreBrackets->setStateOnFunctionEntryOrReturn(); } else { // May need to way wait for anything. ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt()); @@ -1879,7 +1880,7 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) { auto NonKernelInitialState = std::make_unique(ST, Limits, Encoding); - NonKernelInitialState->setNonKernelFunctionInitialState(); + NonKernelInitialState->setStateOnFunctionEntryOrReturn(); BlockInfos[&EntryBB].Incoming = std::move(NonKernelInitialState); Modified = true; diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll index a192a1b8dff9..87e17a1c8208 100644 --- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll @@ -4462,8 +4462,6 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: buffer_store_b32 v0, off, s[36:39], 0 dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; HSA-LABEL: test_call_external_i32_func_i32_imm: diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll index d63ebdeb50a1..ce1ce649c227 100644 --- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll +++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll @@ -167,8 +167,6 @@ define amdgpu_kernel void @call_coldcc() #0 { ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: global_store_b32 v[0:1], v0, off -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm %val = call float @coldcc(float 1.0) store float %val, ptr addrspace(1) undef @@ -231,8 +229,6 @@ define amdgpu_kernel void @call_fastcc() #0 { ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: global_store_b32 v[0:1], v0, off -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm %val = call float @fastcc(float 1.0) store float %val, ptr addrspace(1) undef diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll index 5ebd3eef69f2..499046a2e222 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll @@ -626,8 +626,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1164-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164-NEXT: global_atomic_add_f32 v0, v1, s[0:1] ; GFX1164-NEXT: .LBB1_4: -; GFX1164-NEXT: s_nop 0 -; GFX1164-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1164-NEXT: s_endpgm ; ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_align4_unsafe: @@ -675,8 +673,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1132-NEXT: s_waitcnt lgkmcnt(0) ; GFX1132-NEXT: global_atomic_add_f32 v0, v1, s[0:1] ; GFX1132-NEXT: .LBB1_4: -; GFX1132-NEXT: s_nop 0 -; GFX1132-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1132-NEXT: s_endpgm ; ; GFX9-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_align4_unsafe: @@ -988,8 +984,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164-DPP-NEXT: global_atomic_add_f32 v4, v0, s[0:1] ; GFX1164-DPP-NEXT: .LBB1_2: -; GFX1164-DPP-NEXT: s_nop 0 -; GFX1164-DPP-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1164-DPP-NEXT: s_endpgm ; ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_align4_unsafe: @@ -1051,8 +1045,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0) ; GFX1132-DPP-NEXT: global_atomic_add_f32 v4, v0, s[0:1] ; GFX1132-DPP-NEXT: .LBB1_2: -; GFX1132-DPP-NEXT: s_nop 0 -; GFX1132-DPP-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1132-DPP-NEXT: s_endpgm %divValue = call float @div.float.value() %result = atomicrmw fadd ptr addrspace(1) %ptr, float %divValue syncscope("agent") monotonic, align 4 @@ -3042,8 +3034,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1164-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164-NEXT: global_atomic_add_f32 v0, v1, s[0:1] ; GFX1164-NEXT: .LBB5_4: -; GFX1164-NEXT: s_nop 0 -; GFX1164-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1164-NEXT: s_endpgm ; ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe: @@ -3091,8 +3081,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1132-NEXT: s_waitcnt lgkmcnt(0) ; GFX1132-NEXT: global_atomic_add_f32 v0, v1, s[0:1] ; GFX1132-NEXT: .LBB5_4: -; GFX1132-NEXT: s_nop 0 -; GFX1132-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1132-NEXT: s_endpgm ; ; GFX9-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe: @@ -3404,8 +3392,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164-DPP-NEXT: global_atomic_add_f32 v4, v0, s[0:1] ; GFX1164-DPP-NEXT: .LBB5_2: -; GFX1164-DPP-NEXT: s_nop 0 -; GFX1164-DPP-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1164-DPP-NEXT: s_endpgm ; ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe: @@ -3467,8 +3453,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0) ; GFX1132-DPP-NEXT: global_atomic_add_f32 v4, v0, s[0:1] ; GFX1132-DPP-NEXT: .LBB5_2: -; GFX1132-DPP-NEXT: s_nop 0 -; GFX1132-DPP-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1132-DPP-NEXT: s_endpgm %divValue = call float @div.float.value() %result = atomicrmw fadd ptr addrspace(1) %ptr, float %divValue syncscope("agent") monotonic @@ -3770,8 +3754,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1164-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164-NEXT: global_atomic_add_f32 v0, v1, s[0:1] ; GFX1164-NEXT: .LBB6_4: -; GFX1164-NEXT: s_nop 0 -; GFX1164-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1164-NEXT: s_endpgm ; ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe_structfp: @@ -3819,8 +3801,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1132-NEXT: s_waitcnt lgkmcnt(0) ; GFX1132-NEXT: global_atomic_add_f32 v0, v1, s[0:1] ; GFX1132-NEXT: .LBB6_4: -; GFX1132-NEXT: s_nop 0 -; GFX1132-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1132-NEXT: s_endpgm ; ; GFX9-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe_structfp: @@ -4132,8 +4112,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164-DPP-NEXT: global_atomic_add_f32 v4, v0, s[0:1] ; GFX1164-DPP-NEXT: .LBB6_2: -; GFX1164-DPP-NEXT: s_nop 0 -; GFX1164-DPP-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1164-DPP-NEXT: s_endpgm ; ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe_structfp: @@ -4195,8 +4173,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_ ; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0) ; GFX1132-DPP-NEXT: global_atomic_add_f32 v4, v0, s[0:1] ; GFX1132-DPP-NEXT: .LBB6_2: -; GFX1132-DPP-NEXT: s_nop 0 -; GFX1132-DPP-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX1132-DPP-NEXT: s_endpgm %divValue = call float @div.float.value() %result = atomicrmw fadd ptr addrspace(1) %ptr, float %divValue syncscope("agent") monotonic diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll index 8081d40f7e66..b6afb7cf8c9a 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -300,8 +300,6 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) { ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo ; GFX11-NEXT: global_store_b64 v16, v[0:1], s[34:35] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: %call = tail call i64 @_Z13get_global_idj(i32 0) @@ -930,8 +928,6 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s35, 0, s0 ; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: %call = tail call i64 @_Z13get_global_idj(i32 0) @@ -1294,8 +1290,6 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) { ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_add3_u32 v0, v3, v1, v0 ; GFX11-NEXT: global_store_b32 v6, v0, s[34:35] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: %call = tail call i64 @_Z13get_global_idj(i32 0) @@ -1543,8 +1537,6 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo ; GFX11-NEXT: global_store_b64 v8, v[0:1], s[34:35] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: %call = tail call i64 @_Z13get_global_idj(i32 0) @@ -1753,8 +1745,6 @@ define amdgpu_kernel void @p32Offset64(ptr addrspace(1) %buffer) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_add3_u32 v0, v2, v0, v3 ; GFX11-NEXT: global_store_b32 v6, v0, s[34:35] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: %call = tail call i64 @_Z13get_global_idj(i32 0) @@ -2017,8 +2007,6 @@ define amdgpu_kernel void @DiffBase(ptr addrspace(1) %buffer1, ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo ; GFX11-NEXT: global_store_b64 v12, v[0:1], s[36:37] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ptr addrspace(1) %buffer2) { entry: @@ -2349,8 +2337,6 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) { ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo ; GFX11-NEXT: global_store_b64 v16, v[0:1], s[34:35] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: %call = tail call i64 @_Z13get_global_idj(i32 0) @@ -2553,8 +2539,6 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX11-NEXT: global_store_b64 v4, v[0:1], s[34:35] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm entry: %call = tail call i64 @_Z13get_global_idj(i32 0) #2 diff --git a/llvm/test/CodeGen/AMDGPU/release-vgprs.mir b/llvm/test/CodeGen/AMDGPU/release-vgprs.mir index 07f8567ac068..e80585299b91 100644 --- a/llvm/test/CodeGen/AMDGPU/release-vgprs.mir +++ b/llvm/test/CodeGen/AMDGPU/release-vgprs.mir @@ -22,6 +22,8 @@ define amdgpu_ps void @global_atomic() { ret void } define amdgpu_ps void @image_atomic() { ret void } define amdgpu_ps void @global_store_optnone() noinline optnone { ret void } + define amdgpu_cs void @with_calls() { ret void } + define fastcc void @with_tail_calls() { ret void } ... --- @@ -565,3 +567,33 @@ body: | S_WAITCNT_VSCNT undef $sgpr_null, 0 S_ENDPGM 0 ... + +--- +name: with_calls +frameInfo: + hasCalls: true +body: | + bb.0: + ; Make sure we don't send DEALLOC_VGPRS after a call, since there might be + ; scratch stores still in progress. + ; CHECK-LABEL: name: with_calls + ; CHECK-NOT: S_SENDMSG 3 + ; CHECK: S_ENDPGM 0 + GLOBAL_STORE_DWORD undef renamable $vgpr0_vgpr1, killed renamable $vgpr1, 0, 4, implicit $exec + $sgpr30_sgpr31 = SI_CALL undef renamable $sgpr4_sgpr5, 0, csr_amdgpu + S_ENDPGM 0 +... + +--- +name: with_tail_calls +frameInfo: + hasCalls: true +body: | + bb.0: + ; Make sure we don't send DEALLOC_VGPRS when there's a tail call, since the + ; only valid action after DEALLOC_VGPRS is to terminate the wave. + ; CHECK-LABEL: name: with_tail_calls + ; CHECK-NOT: S_SENDMSG 3 + GLOBAL_STORE_DWORD undef renamable $vgpr0_vgpr1, killed renamable $vgpr1, 0, 4, implicit $exec + SI_TCRETURN undef renamable $sgpr4_sgpr5, @with_tail_calls, 0, csr_amdgpu +... -- GitLab From c9c8f0c2fcf3b25ec310a75216f1d5b582ec343f Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 11 Jan 2024 08:26:23 +0000 Subject: [PATCH 425/652] [AMDGPU] Update tests for GFX12 errors and unsupported instructions (#77624) --- llvm/test/MC/AMDGPU/gfx12_err.s | 72 +++++++++++++++++++++++++ llvm/test/MC/AMDGPU/gfx12_unsupported.s | 27 ++++++++++ 2 files changed, 99 insertions(+) diff --git a/llvm/test/MC/AMDGPU/gfx12_err.s b/llvm/test/MC/AMDGPU/gfx12_err.s index b103d7cef976..edc24f4cf4fe 100644 --- a/llvm/test/MC/AMDGPU/gfx12_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_err.s @@ -1,5 +1,77 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR --implicit-check-not=error: -strict-whitespace %s +v_cubesc_f32_e64_dpp v5, v1, v2, 12345678 row_shr:4 row_mask:0xf bank_mask:0xf +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_add3_u32_e64_dpp v5, v1, v2, 49812340 dpp8:[7,6,5,4,3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cvt_f32_i32_e64_dpp v5, s1 dpp8:[7,6,5,4,3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cvt_f32_i32_e64_dpp v5, s1 row_shl:15 row_mask:0xf bank_mask:0xf +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cvt_f16_u16_e64_dpp v5, s1 dpp8:[7,6,5,4,3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cvt_f16_u16_e64_dpp v5, s1 row_shl:1 row_mask:0xf bank_mask:0xf +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +; disallow space between colons +v_dual_mul_f32 v0, v0, v2 : : v_dual_mul_f32 v1, v1, v3 +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression + +// On GFX12, v_dot8_i32_i4 is a valid SP3 alias for v_dot8_i32_iu4. +// However, we intentionally leave it unimplemented because on other +// processors v_dot8_i32_i4 denotes an instruction of a different +// behaviour, which is considered potentially dangerous. +v_dot8_i32_i4 v0, v1, v2, v3 +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +// On GFX12, v_dot4_i32_i8 is a valid SP3 alias for v_dot4_i32_iu8. +// However, we intentionally leave it unimplemented because on other +// processors v_dot4_i32_i8 denotes an instruction of a different +// behaviour, which is considered potentially dangerous. +v_dot4_i32_i8 v0, v1, v2, v3 +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_dot4c_i32_i8 v0, v1, v2 +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cmp_class_f16_e64_dpp s105, s2, v2 row_ror:15 +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmpx_class_f32_e64_dpp s1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_fma_mix_f32_e64_dpp v5, s1, v3, v4 quad_perm:[3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_fma_mix_f32_e64_dpp v5, v1, s3, v4 quad_perm:[3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_fma_mix_f32_e64_dpp v5, s1, v3, v4 dpp8:[7,6,5,4,3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_fma_mix_f32_e64_dpp v5, v1, s3, v4 dpp8:[7,6,5,4,3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_fma_mixhi_f16_e64_dpp v5, v1, 0, v4 quad_perm:[3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_fma_mixlo_f16_e64_dpp v5, v1, 1, v4 dpp8:[7,6,5,4,3,2,1,0] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +v_lshlrev_b64 v[5:6], s2, s[0:1] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) + +v_lshrrev_b64 v[5:6], s2, s[0:1] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) + +v_ashrrev_i64 v[5:6], s2, s[0:1] +// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) + image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:0x7 // GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: expected an identifier diff --git a/llvm/test/MC/AMDGPU/gfx12_unsupported.s b/llvm/test/MC/AMDGPU/gfx12_unsupported.s index aabaf526dc2a..bf8f7437c042 100644 --- a/llvm/test/MC/AMDGPU/gfx12_unsupported.s +++ b/llvm/test/MC/AMDGPU/gfx12_unsupported.s @@ -34,6 +34,18 @@ s_cbranch_cdbgsys_or_user 0 s_cbranch_cdbgsys_and_user 0 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU +v_fmac_legacy_f32 v0, v1, v2 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_dot2c_f32_f16 v0, v1, v2 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_dual_max_f32 v0, v1, v2 :: v_dual_max_f32 v3, v4, v5 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_dual_min_f32 v0, v1, v2 :: v_dual_min_f32 v3, v4, v5 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + ds_cmpstore_f32 v0, v1, v2 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU @@ -91,6 +103,15 @@ s_cmpk_lt_u32 s0, 0 s_cmpk_le_u32 s0, 0 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU +buffer_atomic_cmpswap_f32 v[5:6], off, s[96:99], s3 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +flat_atomic_cmpswap_f32 v[5:6], off, s[96:99], s3 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +global_atomic_cmpswap_f32 v[5:6], off, s[96:99], s3 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + ds_gws_sema_release_all gds // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU @@ -208,6 +229,12 @@ buffer_gl1_inv buffer_wbinvl1 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU +flat_atomic_csub v1, v[0:1], v2 offset:64 th:TH_ATOMIC_RETURN +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid instruction + +ds_add_f32 v255, v255 offset:4 gds +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: gds modifier is not supported on this GPU + buffer_load_lds_b32 off, s[8:11], s3 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU -- GitLab From 66eedd1dd370d22ddf994540c20848618d64d1a6 Mon Sep 17 00:00:00 2001 From: hanbeom Date: Thu, 11 Jan 2024 17:34:30 +0900 Subject: [PATCH 426/652] [InstCombine] Fix worklist management in select fold (#77738) `InstCombine` uses `Worklist` to manage change history. `setOperand`, which was previously used to change the `Select` Instruction, does not, so it is `run` twice, which causes an `LLVM ERROR`. This problem is resolved by changing `setOperand` to `replaceOperand` as the change history will be registered in the Worklist. Fixes #77553. --- .../Transforms/InstCombine/InstCombineSelect.cpp | 4 ++-- llvm/test/Transforms/InstCombine/select.ll | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index ab55f235920a..21bfc91148bf 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -1704,11 +1704,11 @@ Instruction *InstCombinerImpl::foldSelectInstWithICmp(SelectInst &SI, if (CmpRHS != CmpLHS && isa(CmpRHS) && !isa(CmpLHS)) { if (CmpLHS == TrueVal && Pred == ICmpInst::ICMP_EQ) { // Transform (X == C) ? X : Y -> (X == C) ? C : Y - SI.setOperand(1, CmpRHS); + replaceOperand(SI, 1, CmpRHS); Changed = true; } else if (CmpLHS == FalseVal && Pred == ICmpInst::ICMP_NE) { // Transform (X != C) ? Y : X -> (X != C) ? Y : C - SI.setOperand(2, CmpRHS); + replaceOperand(SI, 2, CmpRHS); Changed = true; } } diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll index d3e959b1eaa0..c5f1b77c6d74 100644 --- a/llvm/test/Transforms/InstCombine/select.ll +++ b/llvm/test/Transforms/InstCombine/select.ll @@ -3658,3 +3658,17 @@ loop: exit: ret i32 %rem } + +; (X == C) ? X : Y -> (X == C) ? C : Y +; Fixed #77553 +define i32 @src_select_xxory_eq0_xorxy_y(i32 %x, i32 %y) { +; CHECK-LABEL: @src_select_xxory_eq0_xorxy_y( +; CHECK-NEXT: [[XOR0:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[COND:%.*]] = select i1 [[XOR0]], i32 0, i32 [[Y]] +; CHECK-NEXT: ret i32 [[COND]] +; + %xor = xor i32 %x, %y + %xor0 = icmp eq i32 %xor, 0 + %cond = select i1 %xor0, i32 %xor, i32 %y + ret i32 %cond +} -- GitLab From 158d72d728261c1e54dc77931372b2322c52849f Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 11 Jan 2024 09:46:54 +0100 Subject: [PATCH 427/652] [Clang] Set writable and dead_on_unwind attributes on sret arguments (#77116) Set the writable and dead_on_unwind attributes for sret arguments. These indicate that the argument points to writable memory (and it's legal to introduce spurious writes to it on entry to the function) and that the argument memory will not be used if the call unwinds. This enables additional MemCpyOpt/DSE/LICM optimizations. --- clang/lib/CodeGen/CGCall.cpp | 2 + .../test/CodeGen/2006-05-19-SingleEltReturn.c | 4 +- clang/test/CodeGen/64bit-swiftcall.c | 22 +-- clang/test/CodeGen/CSKY/csky-abi.c | 4 +- clang/test/CodeGen/CSKY/csky-hard-abi.c | 44 +++--- clang/test/CodeGen/CSKY/csky-soft-abi.c | 44 +++--- clang/test/CodeGen/PowerPC/aix-alignment.c | 4 +- .../test/CodeGen/PowerPC/powerpc-c99complex.c | 6 +- .../CodeGen/PowerPC/ppc-aggregate-abi.cpp | 22 +-- .../PowerPC/ppc32-and-aix-struct-return.c | 22 +-- .../test/CodeGen/PowerPC/ppc64-align-struct.c | 16 +- clang/test/CodeGen/PowerPC/ppc64-elf-abi.c | 2 +- clang/test/CodeGen/PowerPC/ppc64-soft-float.c | 46 +++--- clang/test/CodeGen/PowerPC/ppc64-vector.c | 4 +- .../test/CodeGen/PowerPC/ppc64le-aggregates.c | 12 +- .../CodeGen/PowerPC/ppc64le-f128Aggregates.c | 4 +- clang/test/CodeGen/RISCV/bfloat-abi.c | 4 +- clang/test/CodeGen/RISCV/riscv-abi.cpp | 8 +- clang/test/CodeGen/RISCV/riscv32-abi.c | 66 ++++---- clang/test/CodeGen/RISCV/riscv64-abi.c | 10 +- .../SystemZ/gnu-atomic-builtins-i128-8Al.c | 54 ++----- .../test/CodeGen/SystemZ/systemz-abi-vector.c | 124 +++++++-------- clang/test/CodeGen/SystemZ/systemz-abi.c | 94 ++++++------ clang/test/CodeGen/SystemZ/systemz-abi.cpp | 36 ++--- .../test/CodeGen/SystemZ/systemz-inline-asm.c | 2 +- .../test/CodeGen/WebAssembly/wasm-arguments.c | 12 +- clang/test/CodeGen/WebAssembly/wasm-varargs.c | 4 +- .../CodeGen/X86/x86_32-arguments-darwin.c | 18 +-- .../test/CodeGen/X86/x86_32-arguments-iamcu.c | 2 +- .../test/CodeGen/X86/x86_64-arguments-nacl.c | 2 +- .../test/CodeGen/X86/x86_64-arguments-win32.c | 2 +- clang/test/CodeGen/X86/x86_64-arguments.c | 6 +- ...-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c | 2 +- clang/test/CodeGen/aarch64-varargs.c | 4 +- clang/test/CodeGen/aggregate-assign-call.c | 4 +- clang/test/CodeGen/aligned-sret.c | 2 +- clang/test/CodeGen/arc/arguments.c | 8 +- clang/test/CodeGen/arm-aapcs-vfp.c | 2 +- clang/test/CodeGen/arm-arguments.c | 28 ++-- clang/test/CodeGen/arm-homogenous.c | 8 +- clang/test/CodeGen/arm-neon-vld.c | 144 +++++++++--------- clang/test/CodeGen/arm-swiftcall.c | 26 ++-- clang/test/CodeGen/arm-varargs.c | 18 +-- clang/test/CodeGen/arm-vector-arguments.c | 6 +- clang/test/CodeGen/arm-vfp16-arguments.c | 2 +- clang/test/CodeGen/arm-vfp16-arguments2.cpp | 10 +- clang/test/CodeGen/arm64-arguments.c | 4 +- .../CodeGen/arm64-microsoft-arguments.cpp | 34 ++--- clang/test/CodeGen/arm64_32.c | 2 +- clang/test/CodeGen/armv7k-abi.c | 2 +- clang/test/CodeGen/attr-noundef.cpp | 6 +- clang/test/CodeGen/blocks.c | 2 +- clang/test/CodeGen/c11atomics-ios.c | 4 +- clang/test/CodeGen/c11atomics.c | 4 +- clang/test/CodeGen/ext-int-cc.c | 124 +++++++-------- clang/test/CodeGen/isfpclass.c | 2 +- clang/test/CodeGen/lanai-arguments.c | 4 +- clang/test/CodeGen/mcu-struct-return.c | 4 +- clang/test/CodeGen/mingw-long-double.c | 8 +- clang/test/CodeGen/mips-vector-return.c | 6 +- clang/test/CodeGen/mips-zero-sized-struct.c | 2 +- .../test/CodeGen/mips64-nontrivial-return.cpp | 2 +- clang/test/CodeGen/mips64-padding-arg.c | 6 +- clang/test/CodeGen/ms_abi.c | 4 +- clang/test/CodeGen/paren-list-agg-init.cpp | 6 +- clang/test/CodeGen/regcall2.c | 2 +- clang/test/CodeGen/regparm-struct.c | 2 +- clang/test/CodeGen/renderscript.c | 18 +-- clang/test/CodeGen/sparcv9-abi.c | 2 +- clang/test/CodeGen/sret.c | 10 +- clang/test/CodeGen/vectorcall.c | 4 +- clang/test/CodeGen/windows-struct-abi.c | 2 +- clang/test/CodeGen/windows-swiftcall.c | 4 +- clang/test/CodeGenCXX/aix-alignment.cpp | 2 +- clang/test/CodeGenCXX/arm-cc.cpp | 2 +- clang/test/CodeGenCXX/arm-swiftcall.cpp | 2 +- clang/test/CodeGenCXX/attr-musttail.cpp | 6 +- .../CodeGenCXX/call-with-static-chain.cpp | 4 +- clang/test/CodeGenCXX/conditional-gnu-ext.cpp | 8 +- clang/test/CodeGenCXX/cxx1z-copy-omission.cpp | 4 +- .../CodeGenCXX/cxx1z-lambda-star-this.cpp | 4 +- clang/test/CodeGenCXX/exceptions.cpp | 6 +- .../CodeGenCXX/homogeneous-aggregates.cpp | 28 ++-- clang/test/CodeGenCXX/lambda-expressions.cpp | 4 +- clang/test/CodeGenCXX/matrix-casts.cpp | 4 +- .../test/CodeGenCXX/matrix-type-builtins.cpp | 8 +- clang/test/CodeGenCXX/matrix-type.cpp | 2 +- .../CodeGenCXX/microsoft-abi-byval-sret.cpp | 4 +- .../CodeGenCXX/microsoft-abi-byval-thunks.cpp | 4 +- .../microsoft-abi-cdecl-method-sret.cpp | 8 +- .../CodeGenCXX/microsoft-abi-eh-cleanups.cpp | 8 +- .../microsoft-abi-sret-and-byval.cpp | 88 +++++------ .../CodeGenCXX/microsoft-abi-unknown-arch.cpp | 2 +- .../microsoft-abi-vmemptr-conflicts.cpp | 2 +- clang/test/CodeGenCXX/ms-thread_local.cpp | 4 +- clang/test/CodeGenCXX/nrvo.cpp | 18 +-- .../test/CodeGenCXX/pass-by-value-noalias.cpp | 4 +- clang/test/CodeGenCXX/regcall.cpp | 8 +- clang/test/CodeGenCXX/regcall4.cpp | 8 +- .../CodeGenCXX/stack-reuse-miscompile.cpp | 2 +- clang/test/CodeGenCXX/stack-reuse.cpp | 2 +- clang/test/CodeGenCXX/temporaries.cpp | 12 +- .../CodeGenCXX/thiscall-struct-return.cpp | 4 +- .../CodeGenCXX/thunk-returning-memptr.cpp | 4 +- clang/test/CodeGenCXX/trivial_abi.cpp | 8 +- clang/test/CodeGenCXX/unknown-anytype.cpp | 2 +- clang/test/CodeGenCXX/wasm-args-returns.cpp | 18 +-- clang/test/CodeGenCXX/x86_32-arguments.cpp | 8 +- clang/test/CodeGenCXX/x86_64-arguments.cpp | 4 +- clang/test/CodeGenCoroutines/coro-await.cpp | 10 +- clang/test/CodeGenCoroutines/coro-gro2.cpp | 10 +- clang/test/CodeGenHLSL/sret_output.hlsl | 2 +- clang/test/CodeGenObjC/arc.m | 4 +- clang/test/CodeGenObjC/direct-method.m | 2 +- .../nontrivial-c-struct-exception.m | 4 +- .../objc-non-trivial-struct-nrvo.m | 6 +- clang/test/CodeGenObjC/stret-1.m | 8 +- clang/test/CodeGenObjC/stret_lookup.m | 4 +- clang/test/CodeGenObjC/weak-in-c-struct.m | 2 +- .../CodeGenObjC/x86_64-struct-return-gc.m | 2 +- .../test/CodeGenObjCXX/objc-struct-cxx-abi.mm | 2 +- .../CodeGenOpenCL/addr-space-struct-arg.cl | 6 +- .../amdgpu-abi-struct-arg-byref.cl | 4 +- .../CodeGenOpenCL/amdgpu-abi-struct-coerce.cl | 6 +- .../CodeGenOpenCLCXX/addrspace-of-this.clcpp | 4 +- clang/test/Modules/templates.mm | 2 +- clang/test/OpenMP/irbuilder_for_iterator.cpp | 2 +- clang/test/OpenMP/irbuilder_for_rangefor.cpp | 6 +- .../master_taskloop_in_reduction_codegen.cpp | 4 +- ...ter_taskloop_simd_in_reduction_codegen.cpp | 4 +- .../OpenMP/target_in_reduction_codegen.cpp | 4 +- .../test/OpenMP/task_in_reduction_codegen.cpp | 4 +- .../OpenMP/taskloop_in_reduction_codegen.cpp | 4 +- .../taskloop_simd_in_reduction_codegen.cpp | 4 +- 134 files changed, 815 insertions(+), 837 deletions(-) diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 51a43b5f85b3..13677cf150ae 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -2612,6 +2612,8 @@ void CodeGenModule::ConstructAttributeList(StringRef Name, if (IRFunctionArgs.hasSRetArg()) { llvm::AttrBuilder SRETAttrs(getLLVMContext()); SRETAttrs.addStructRetAttr(getTypes().ConvertTypeForMem(RetTy)); + SRETAttrs.addAttribute(llvm::Attribute::Writable); + SRETAttrs.addAttribute(llvm::Attribute::DeadOnUnwind); hasUsedSRet = true; if (RetAI.getInReg()) SRETAttrs.addAttribute(llvm::Attribute::InReg); diff --git a/clang/test/CodeGen/2006-05-19-SingleEltReturn.c b/clang/test/CodeGen/2006-05-19-SingleEltReturn.c index 16eacf3ec162..b542242606cc 100644 --- a/clang/test/CodeGen/2006-05-19-SingleEltReturn.c +++ b/clang/test/CodeGen/2006-05-19-SingleEltReturn.c @@ -24,7 +24,7 @@ struct Y bar(void) { // X86_32: define{{.*}} void @foo(ptr noundef %P) -// X86_32: call void @bar(ptr sret(%struct.Y) align 4 %{{[^),]*}}) +// X86_32: call void @bar(ptr dead_on_unwind writable sret(%struct.Y) align 4 %{{[^),]*}}) -// X86_32: define{{.*}} void @bar(ptr noalias sret(%struct.Y) align 4 %{{[^,)]*}}) +// X86_32: define{{.*}} void @bar(ptr dead_on_unwind noalias writable sret(%struct.Y) align 4 %{{[^,)]*}}) // X86_32: ret void diff --git a/clang/test/CodeGen/64bit-swiftcall.c b/clang/test/CodeGen/64bit-swiftcall.c index da6f18248c2a..b1c42e3b0a65 100644 --- a/clang/test/CodeGen/64bit-swiftcall.c +++ b/clang/test/CodeGen/64bit-swiftcall.c @@ -30,7 +30,7 @@ SWIFTCALL int indirect_result_2(OUT int *arg0, OUT float *arg1) { __builtin_unr typedef struct { char array[1024]; } struct_reallybig; SWIFTCALL struct_reallybig indirect_result_3(OUT int *arg0, OUT float *arg1) { __builtin_unreachable(); } -// CHECK-LABEL: define {{.*}} void @indirect_result_3(ptr noalias sret(%struct.struct_reallybig) {{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}) +// CHECK-LABEL: define {{.*}} void @indirect_result_3(ptr dead_on_unwind noalias writable sret(%struct.struct_reallybig) {{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}) SWIFTCALL void context_1(CONTEXT void *self) {} // CHECK-LABEL: define {{.*}} void @context_1(ptr swiftself @@ -238,7 +238,7 @@ typedef struct { } struct_big_1; TEST(struct_big_1) -// CHECK-LABEL: define {{.*}} void @return_struct_big_1({{.*}} noalias sret +// CHECK-LABEL: define {{.*}} void @return_struct_big_1(ptr dead_on_unwind noalias writable sret // Should not be byval. // CHECK-LABEL: define {{.*}} void @take_struct_big_1(ptr{{( %.*)?}}) @@ -522,7 +522,7 @@ typedef struct { double d4; } struct_d5; TEST(struct_d5) -// CHECK: define{{.*}} swiftcc void @return_struct_d5(ptr noalias sret([[STRUCT5:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_d5(ptr dead_on_unwind noalias writable sret([[STRUCT5:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_d5(ptr typedef struct { @@ -709,7 +709,7 @@ typedef struct { long long l4; } struct_l5; TEST(struct_l5) -// CHECK: define{{.*}} swiftcc void @return_struct_l5(ptr noalias sret([[STRUCT5:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_l5(ptr dead_on_unwind noalias writable sret([[STRUCT5:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_l5(ptr typedef struct { @@ -754,7 +754,7 @@ typedef struct { char16 c4; } struct_vc5; TEST(struct_vc5) -// CHECK: define{{.*}} swiftcc void @return_struct_vc5(ptr noalias sret([[STRUCT:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vc5(ptr dead_on_unwind noalias writable sret([[STRUCT:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_vc5(ptr typedef struct { @@ -799,7 +799,7 @@ typedef struct { short8 c4; } struct_vs5; TEST(struct_vs5) -// CHECK: define{{.*}} swiftcc void @return_struct_vs5(ptr noalias sret([[STRUCT:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vs5(ptr dead_on_unwind noalias writable sret([[STRUCT:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_vs5(ptr typedef struct { @@ -844,7 +844,7 @@ typedef struct { int4 c4; } struct_vi5; TEST(struct_vi5) -// CHECK: define{{.*}} swiftcc void @return_struct_vi5(ptr noalias sret([[STRUCT:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vi5(ptr dead_on_unwind noalias writable sret([[STRUCT:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_vi5(ptr typedef struct { @@ -872,7 +872,7 @@ typedef struct { long2 c4; } struct_vl5; TEST(struct_vl5) -// CHECK: define{{.*}} swiftcc void @return_struct_vl5(ptr noalias sret([[STRUCT:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vl5(ptr dead_on_unwind noalias writable sret([[STRUCT:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_vl5(ptr typedef struct { @@ -900,7 +900,7 @@ typedef struct { double2 c4; } struct_vd5; TEST(struct_vd5) -// CHECK: define{{.*}} swiftcc void @return_struct_vd5(ptr noalias sret([[STRUCT:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vd5(ptr dead_on_unwind noalias writable sret([[STRUCT:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_vd5(ptr typedef struct { @@ -924,7 +924,7 @@ typedef struct { double4 c2; } struct_vd43; TEST(struct_vd43) -// CHECK: define{{.*}} swiftcc void @return_struct_vd43(ptr noalias sret([[STRUCT:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vd43(ptr dead_on_unwind noalias writable sret([[STRUCT:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_vd43(ptr typedef struct { @@ -960,7 +960,7 @@ typedef struct { float4 c4; } struct_vf5; TEST(struct_vf5) -// CHECK: define{{.*}} swiftcc void @return_struct_vf5(ptr noalias sret([[STRUCT:.+]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vf5(ptr dead_on_unwind noalias writable sret([[STRUCT:.+]]) // CHECK: define{{.*}} swiftcc void @take_struct_vf5(ptr typedef struct { diff --git a/clang/test/CodeGen/CSKY/csky-abi.c b/clang/test/CodeGen/CSKY/csky-abi.c index a24d4d8d6407..2e549376ba93 100644 --- a/clang/test/CodeGen/CSKY/csky-abi.c +++ b/clang/test/CodeGen/CSKY/csky-abi.c @@ -117,7 +117,7 @@ void f_agg_large(struct large x) { // The address where the struct should be written to will be the first // argument -// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(ptr noalias sret(%struct.large) align 4 %agg.result, i32 noundef %i, i8 noundef signext %j) +// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(ptr dead_on_unwind noalias writable sret(%struct.large) align 4 %agg.result, i32 noundef %i, i8 noundef signext %j) struct large f_agg_large_ret(int32_t i, int8_t j) { return (struct large){1, 2, 3, 4}; } @@ -144,7 +144,7 @@ int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c, // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(ptr noalias sret(%struct.large) align 4 %agg.result, i32 noundef %a, i64 noundef %b, i64 noundef %c, double noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef zeroext %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(ptr dead_on_unwind noalias writable sret(%struct.large) align 4 %agg.result, i32 noundef %a, i64 noundef %b, i64 noundef %c, double noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef zeroext %g) struct large f_scalar_stack_2(int32_t a, int64_t b, int64_t c, long double d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; diff --git a/clang/test/CodeGen/CSKY/csky-hard-abi.c b/clang/test/CodeGen/CSKY/csky-hard-abi.c index 2171da8091e2..0bc4a5a8808e 100644 --- a/clang/test/CodeGen/CSKY/csky-hard-abi.c +++ b/clang/test/CodeGen/CSKY/csky-hard-abi.c @@ -72,7 +72,7 @@ struct double_float_s { // CHECK: define{{.*}} void @f_double_double_s_arg([4 x i32] %a.coerce) void f_double_double_s_arg(struct double_double_s a) {} -// CHECK: define{{.*}} void @f_ret_double_double_s(ptr noalias sret(%struct.double_double_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_double_s(ptr dead_on_unwind noalias writable sret(%struct.double_double_s) align 4 %agg.result) struct double_double_s f_ret_double_double_s(void) { return (struct double_double_s){1.0, 2.0}; } @@ -80,7 +80,7 @@ struct double_double_s f_ret_double_double_s(void) { // CHECK: define{{.*}} void @f_double_float_s_arg([3 x i32] %a.coerce) void f_double_float_s_arg(struct double_float_s a) {} -// CHECK: define{{.*}} void @f_ret_double_float_s(ptr noalias sret(%struct.double_float_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_float_s(ptr dead_on_unwind noalias writable sret(%struct.double_float_s) align 4 %agg.result) struct double_float_s f_ret_double_float_s(void) { return (struct double_float_s){1.0, 2.0}; } @@ -118,7 +118,7 @@ struct double_int8_zbf_s { // CHECK: define{{.*}} @f_double_int8_s_arg([3 x i32] %a.coerce) void f_double_int8_s_arg(struct double_int8_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int8_s(ptr noalias sret(%struct.double_int8_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int8_s(ptr dead_on_unwind noalias writable sret(%struct.double_int8_s) align 4 %agg.result) struct double_int8_s f_ret_double_int8_s(void) { return (struct double_int8_s){1.0, 2}; } @@ -126,7 +126,7 @@ struct double_int8_s f_ret_double_int8_s(void) { // CHECK: define{{.*}} void @f_double_uint8_s_arg([3 x i32] %a.coerce) void f_double_uint8_s_arg(struct double_uint8_s a) {} -// CHECK: define{{.*}} void @f_ret_double_uint8_s(ptr noalias sret(%struct.double_uint8_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_uint8_s(ptr dead_on_unwind noalias writable sret(%struct.double_uint8_s) align 4 %agg.result) struct double_uint8_s f_ret_double_uint8_s(void) { return (struct double_uint8_s){1.0, 2}; } @@ -134,7 +134,7 @@ struct double_uint8_s f_ret_double_uint8_s(void) { // CHECK: define{{.*}} void @f_double_int32_s_arg([3 x i32] %a.coerce) void f_double_int32_s_arg(struct double_int32_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int32_s(ptr noalias sret(%struct.double_int32_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int32_s(ptr dead_on_unwind noalias writable sret(%struct.double_int32_s) align 4 %agg.result) struct double_int32_s f_ret_double_int32_s(void) { return (struct double_int32_s){1.0, 2}; } @@ -142,7 +142,7 @@ struct double_int32_s f_ret_double_int32_s(void) { // CHECK: define{{.*}} void @f_double_int64_s_arg([4 x i32] %a.coerce) void f_double_int64_s_arg(struct double_int64_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int64_s(ptr noalias sret(%struct.double_int64_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int64_s(ptr dead_on_unwind noalias writable sret(%struct.double_int64_s) align 4 %agg.result) struct double_int64_s f_ret_double_int64_s(void) { return (struct double_int64_s){1.0, 2}; } @@ -150,7 +150,7 @@ struct double_int64_s f_ret_double_int64_s(void) { // CHECK: define{{.*}} void @f_double_int64bf_s_arg([3 x i32] %a.coerce) void f_double_int64bf_s_arg(struct double_int64bf_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int64bf_s(ptr noalias sret(%struct.double_int64bf_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int64bf_s(ptr dead_on_unwind noalias writable sret(%struct.double_int64bf_s) align 4 %agg.result) struct double_int64bf_s f_ret_double_int64bf_s(void) { return (struct double_int64bf_s){1.0, 2}; } @@ -158,7 +158,7 @@ struct double_int64bf_s f_ret_double_int64bf_s(void) { // CHECK: define{{.*}} void @f_double_int8_zbf_s([3 x i32] %a.coerce) void f_double_int8_zbf_s(struct double_int8_zbf_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int8_zbf_s(ptr noalias sret(%struct.double_int8_zbf_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int8_zbf_s(ptr dead_on_unwind noalias writable sret(%struct.double_int8_zbf_s) align 4 %agg.result) struct double_int8_zbf_s f_ret_double_int8_zbf_s(void) { return (struct double_int8_zbf_s){1.0, 2}; } @@ -179,7 +179,7 @@ void f_struct_double_int8_insufficient_fprs(float a, double b, double c, double // CHECK: define{{.*}} void @f_doublecomplex(double noundef %a.coerce0, double noundef %a.coerce1) void f_doublecomplex(double __complex__ a) {} -// CHECK: define{{.*}} void @f_ret_doublecomplex(ptr noalias sret({ double, double }) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublecomplex(ptr dead_on_unwind noalias writable sret({ double, double }) align 4 %agg.result) double __complex__ f_ret_doublecomplex(void) { return 1.0; } @@ -191,7 +191,7 @@ struct doublecomplex_s { // CHECK: define{{.*}} void @f_doublecomplex_s_arg([4 x i32] %a.coerce) void f_doublecomplex_s_arg(struct doublecomplex_s a) {} -// CHECK: define{{.*}} void @f_ret_doublecomplex_s(ptr noalias sret(%struct.doublecomplex_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublecomplex_s(ptr dead_on_unwind noalias writable sret(%struct.doublecomplex_s) align 4 %agg.result) struct doublecomplex_s f_ret_doublecomplex_s(void) { return (struct doublecomplex_s){1.0}; } @@ -218,7 +218,7 @@ struct doublearr2_s { // CHECK: define{{.*}} void @f_doublearr2_s_arg([4 x i32] %a.coerce) void f_doublearr2_s_arg(struct doublearr2_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_s(ptr noalias sret(%struct.doublearr2_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_s) align 4 %agg.result) struct doublearr2_s f_ret_doublearr2_s(void) { return (struct doublearr2_s){{1.0, 2.0}}; } @@ -232,7 +232,7 @@ struct doublearr2_tricky1_s { // CHECK: define{{.*}} void @f_doublearr2_tricky1_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky1_s_arg(struct doublearr2_tricky1_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky1_s(ptr noalias sret(%struct.doublearr2_tricky1_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky1_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky1_s) align 4 %agg.result) struct doublearr2_tricky1_s f_ret_doublearr2_tricky1_s(void) { return (struct doublearr2_tricky1_s){{{{1.0}}, {{2.0}}}}; } @@ -247,7 +247,7 @@ struct doublearr2_tricky2_s { // CHECK: define{{.*}} void @f_doublearr2_tricky2_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky2_s_arg(struct doublearr2_tricky2_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky2_s(ptr noalias sret(%struct.doublearr2_tricky2_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky2_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky2_s) align 4 %agg.result) struct doublearr2_tricky2_s f_ret_doublearr2_tricky2_s(void) { return (struct doublearr2_tricky2_s){{}, {{{1.0}}, {{2.0}}}}; } @@ -262,7 +262,7 @@ struct doublearr2_tricky3_s { // CHECK: define{{.*}} void @f_doublearr2_tricky3_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky3_s_arg(struct doublearr2_tricky3_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky3_s(ptr noalias sret(%struct.doublearr2_tricky3_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky3_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky3_s) align 4 %agg.result) struct doublearr2_tricky3_s f_ret_doublearr2_tricky3_s(void) { return (struct doublearr2_tricky3_s){{}, {{{1.0}}, {{2.0}}}}; } @@ -278,7 +278,7 @@ struct doublearr2_tricky4_s { // CHECK: define{{.*}} void @f_doublearr2_tricky4_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky4_s_arg(struct doublearr2_tricky4_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky4_s(ptr noalias sret(%struct.doublearr2_tricky4_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky4_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky4_s) align 4 %agg.result) struct doublearr2_tricky4_s f_ret_doublearr2_tricky4_s(void) { return (struct doublearr2_tricky4_s){{}, {{{}, {1.0}}, {{}, {2.0}}}}; } @@ -292,7 +292,7 @@ struct int_double_int_s { // CHECK: define{{.*}} void @f_int_double_int_s_arg([4 x i32] %a.coerce) void f_int_double_int_s_arg(struct int_double_int_s a) {} -// CHECK: define{{.*}} void @f_ret_int_double_int_s(ptr noalias sret(%struct.int_double_int_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_int_double_int_s(ptr dead_on_unwind noalias writable sret(%struct.int_double_int_s) align 4 %agg.result) struct int_double_int_s f_ret_int_double_int_s(void) { return (struct int_double_int_s){1, 2.0, 3}; } @@ -305,7 +305,7 @@ struct int64_double_s { // CHECK: define{{.*}} void @f_int64_double_s_arg([4 x i32] %a.coerce) void f_int64_double_s_arg(struct int64_double_s a) {} -// CHECK: define{{.*}} void @f_ret_int64_double_s(ptr noalias sret(%struct.int64_double_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_int64_double_s(ptr dead_on_unwind noalias writable sret(%struct.int64_double_s) align 4 %agg.result) struct int64_double_s f_ret_int64_double_s(void) { return (struct int64_double_s){1, 2.0}; } @@ -319,7 +319,7 @@ struct char_char_double_s { // CHECK-LABEL: define{{.*}} void @f_char_char_double_s_arg([3 x i32] %a.coerce) void f_char_char_double_s_arg(struct char_char_double_s a) {} -// CHECK: define{{.*}} void @f_ret_char_char_double_s(ptr noalias sret(%struct.char_char_double_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_char_char_double_s(ptr dead_on_unwind noalias writable sret(%struct.char_char_double_s) align 4 %agg.result) struct char_char_double_s f_ret_char_char_double_s(void) { return (struct char_char_double_s){1, 2, 3.0}; } @@ -338,19 +338,19 @@ union double_u f_ret_double_u(void) { return (union double_u){1.0}; } -// CHECK: define{{.*}} void @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(ptr noalias sret(%struct.double_int32_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) +// CHECK: define{{.*}} void @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(ptr dead_on_unwind noalias writable sret(%struct.double_int32_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) struct double_int32_s f_ret_double_int32_s_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return (struct double_int32_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(ptr noalias sret(%struct.double_double_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) +// CHECK: define{{.*}} void @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(ptr dead_on_unwind noalias writable sret(%struct.double_double_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) struct double_double_s f_ret_double_double_s_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return (struct double_double_s){1.0, 2.0}; } -// CHECK: define{{.*}} void @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(ptr noalias sret({ double, double }) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) +// CHECK: define{{.*}} void @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(ptr dead_on_unwind noalias writable sret({ double, double }) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) double __complex__ f_ret_doublecomplex_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return 1.0; @@ -376,7 +376,7 @@ struct large { // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(ptr noalias sret(%struct.large) align 4 %agg.result, float noundef %a, i64 noundef %b, double noundef %c, double noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef zeroext %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(ptr dead_on_unwind noalias writable sret(%struct.large) align 4 %agg.result, float noundef %a, i64 noundef %b, double noundef %c, double noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef zeroext %g) struct large f_scalar_stack_2(float a, int64_t b, double c, long double d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; diff --git a/clang/test/CodeGen/CSKY/csky-soft-abi.c b/clang/test/CodeGen/CSKY/csky-soft-abi.c index 1aba2df1f20a..04fb7a494084 100644 --- a/clang/test/CodeGen/CSKY/csky-soft-abi.c +++ b/clang/test/CodeGen/CSKY/csky-soft-abi.c @@ -72,7 +72,7 @@ struct double_float_s { // CHECK: define{{.*}} void @f_double_double_s_arg([4 x i32] %a.coerce) void f_double_double_s_arg(struct double_double_s a) {} -// CHECK: define{{.*}} void @f_ret_double_double_s(ptr noalias sret(%struct.double_double_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_double_s(ptr dead_on_unwind noalias writable sret(%struct.double_double_s) align 4 %agg.result) struct double_double_s f_ret_double_double_s(void) { return (struct double_double_s){1.0, 2.0}; } @@ -80,7 +80,7 @@ struct double_double_s f_ret_double_double_s(void) { // CHECK: define{{.*}} void @f_double_float_s_arg([3 x i32] %a.coerce) void f_double_float_s_arg(struct double_float_s a) {} -// CHECK: define{{.*}} void @f_ret_double_float_s(ptr noalias sret(%struct.double_float_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_float_s(ptr dead_on_unwind noalias writable sret(%struct.double_float_s) align 4 %agg.result) struct double_float_s f_ret_double_float_s(void) { return (struct double_float_s){1.0, 2.0}; } @@ -118,7 +118,7 @@ struct double_int8_zbf_s { // CHECK: define{{.*}} @f_double_int8_s_arg([3 x i32] %a.coerce) void f_double_int8_s_arg(struct double_int8_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int8_s(ptr noalias sret(%struct.double_int8_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int8_s(ptr dead_on_unwind noalias writable sret(%struct.double_int8_s) align 4 %agg.result) struct double_int8_s f_ret_double_int8_s(void) { return (struct double_int8_s){1.0, 2}; } @@ -126,7 +126,7 @@ struct double_int8_s f_ret_double_int8_s(void) { // CHECK: define{{.*}} void @f_double_uint8_s_arg([3 x i32] %a.coerce) void f_double_uint8_s_arg(struct double_uint8_s a) {} -// CHECK: define{{.*}} void @f_ret_double_uint8_s(ptr noalias sret(%struct.double_uint8_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_uint8_s(ptr dead_on_unwind noalias writable sret(%struct.double_uint8_s) align 4 %agg.result) struct double_uint8_s f_ret_double_uint8_s(void) { return (struct double_uint8_s){1.0, 2}; } @@ -134,7 +134,7 @@ struct double_uint8_s f_ret_double_uint8_s(void) { // CHECK: define{{.*}} void @f_double_int32_s_arg([3 x i32] %a.coerce) void f_double_int32_s_arg(struct double_int32_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int32_s(ptr noalias sret(%struct.double_int32_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int32_s(ptr dead_on_unwind noalias writable sret(%struct.double_int32_s) align 4 %agg.result) struct double_int32_s f_ret_double_int32_s(void) { return (struct double_int32_s){1.0, 2}; } @@ -142,7 +142,7 @@ struct double_int32_s f_ret_double_int32_s(void) { // CHECK: define{{.*}} void @f_double_int64_s_arg([4 x i32] %a.coerce) void f_double_int64_s_arg(struct double_int64_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int64_s(ptr noalias sret(%struct.double_int64_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int64_s(ptr dead_on_unwind noalias writable sret(%struct.double_int64_s) align 4 %agg.result) struct double_int64_s f_ret_double_int64_s(void) { return (struct double_int64_s){1.0, 2}; } @@ -150,7 +150,7 @@ struct double_int64_s f_ret_double_int64_s(void) { // CHECK: define{{.*}} void @f_double_int64bf_s_arg([3 x i32] %a.coerce) void f_double_int64bf_s_arg(struct double_int64bf_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int64bf_s(ptr noalias sret(%struct.double_int64bf_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int64bf_s(ptr dead_on_unwind noalias writable sret(%struct.double_int64bf_s) align 4 %agg.result) struct double_int64bf_s f_ret_double_int64bf_s(void) { return (struct double_int64bf_s){1.0, 2}; } @@ -158,7 +158,7 @@ struct double_int64bf_s f_ret_double_int64bf_s(void) { // CHECK: define{{.*}} void @f_double_int8_zbf_s([3 x i32] %a.coerce) void f_double_int8_zbf_s(struct double_int8_zbf_s a) {} -// CHECK: define{{.*}} void @f_ret_double_int8_zbf_s(ptr noalias sret(%struct.double_int8_zbf_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_double_int8_zbf_s(ptr dead_on_unwind noalias writable sret(%struct.double_int8_zbf_s) align 4 %agg.result) struct double_int8_zbf_s f_ret_double_int8_zbf_s(void) { return (struct double_int8_zbf_s){1.0, 2}; } @@ -180,7 +180,7 @@ void f_struct_double_int8_insufficient_fprs(float a, double b, double c, double // CHECK: define{{.*}} void @f_doublecomplex([4 x i32] noundef %a.coerce) void f_doublecomplex(double __complex__ a) {} -// CHECK: define{{.*}} void @f_ret_doublecomplex(ptr noalias sret({ double, double }) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublecomplex(ptr dead_on_unwind noalias writable sret({ double, double }) align 4 %agg.result) double __complex__ f_ret_doublecomplex(void) { return 1.0; } @@ -192,7 +192,7 @@ struct doublecomplex_s { // CHECK: define{{.*}} void @f_doublecomplex_s_arg([4 x i32] %a.coerce) void f_doublecomplex_s_arg(struct doublecomplex_s a) {} -// CHECK: define{{.*}} void @f_ret_doublecomplex_s(ptr noalias sret(%struct.doublecomplex_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublecomplex_s(ptr dead_on_unwind noalias writable sret(%struct.doublecomplex_s) align 4 %agg.result) struct doublecomplex_s f_ret_doublecomplex_s(void) { return (struct doublecomplex_s){1.0}; } @@ -219,7 +219,7 @@ struct doublearr2_s { // CHECK: define{{.*}} void @f_doublearr2_s_arg([4 x i32] %a.coerce) void f_doublearr2_s_arg(struct doublearr2_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_s(ptr noalias sret(%struct.doublearr2_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_s) align 4 %agg.result) struct doublearr2_s f_ret_doublearr2_s(void) { return (struct doublearr2_s){{1.0, 2.0}}; } @@ -233,7 +233,7 @@ struct doublearr2_tricky1_s { // CHECK: define{{.*}} void @f_doublearr2_tricky1_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky1_s_arg(struct doublearr2_tricky1_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky1_s(ptr noalias sret(%struct.doublearr2_tricky1_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky1_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky1_s) align 4 %agg.result) struct doublearr2_tricky1_s f_ret_doublearr2_tricky1_s(void) { return (struct doublearr2_tricky1_s){{{{1.0}}, {{2.0}}}}; } @@ -248,7 +248,7 @@ struct doublearr2_tricky2_s { // CHECK: define{{.*}} void @f_doublearr2_tricky2_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky2_s_arg(struct doublearr2_tricky2_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky2_s(ptr noalias sret(%struct.doublearr2_tricky2_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky2_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky2_s) align 4 %agg.result) struct doublearr2_tricky2_s f_ret_doublearr2_tricky2_s(void) { return (struct doublearr2_tricky2_s){{}, {{{1.0}}, {{2.0}}}}; } @@ -263,7 +263,7 @@ struct doublearr2_tricky3_s { // CHECK: define{{.*}} void @f_doublearr2_tricky3_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky3_s_arg(struct doublearr2_tricky3_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky3_s(ptr noalias sret(%struct.doublearr2_tricky3_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky3_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky3_s) align 4 %agg.result) struct doublearr2_tricky3_s f_ret_doublearr2_tricky3_s(void) { return (struct doublearr2_tricky3_s){{}, {{{1.0}}, {{2.0}}}}; } @@ -279,7 +279,7 @@ struct doublearr2_tricky4_s { // CHECK: define{{.*}} void @f_doublearr2_tricky4_s_arg([4 x i32] %a.coerce) void f_doublearr2_tricky4_s_arg(struct doublearr2_tricky4_s a) {} -// CHECK: define{{.*}} void @f_ret_doublearr2_tricky4_s(ptr noalias sret(%struct.doublearr2_tricky4_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_doublearr2_tricky4_s(ptr dead_on_unwind noalias writable sret(%struct.doublearr2_tricky4_s) align 4 %agg.result) struct doublearr2_tricky4_s f_ret_doublearr2_tricky4_s(void) { return (struct doublearr2_tricky4_s){{}, {{{}, {1.0}}, {{}, {2.0}}}}; } @@ -293,7 +293,7 @@ struct int_double_int_s { // CHECK: define{{.*}} void @f_int_double_int_s_arg([4 x i32] %a.coerce) void f_int_double_int_s_arg(struct int_double_int_s a) {} -// CHECK: define{{.*}} void @f_ret_int_double_int_s(ptr noalias sret(%struct.int_double_int_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_int_double_int_s(ptr dead_on_unwind noalias writable sret(%struct.int_double_int_s) align 4 %agg.result) struct int_double_int_s f_ret_int_double_int_s(void) { return (struct int_double_int_s){1, 2.0, 3}; } @@ -306,7 +306,7 @@ struct int64_double_s { // CHECK: define{{.*}} void @f_int64_double_s_arg([4 x i32] %a.coerce) void f_int64_double_s_arg(struct int64_double_s a) {} -// CHECK: define{{.*}} void @f_ret_int64_double_s(ptr noalias sret(%struct.int64_double_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_int64_double_s(ptr dead_on_unwind noalias writable sret(%struct.int64_double_s) align 4 %agg.result) struct int64_double_s f_ret_int64_double_s(void) { return (struct int64_double_s){1, 2.0}; } @@ -320,7 +320,7 @@ struct char_char_double_s { // CHECK-LABEL: define{{.*}} void @f_char_char_double_s_arg([3 x i32] %a.coerce) void f_char_char_double_s_arg(struct char_char_double_s a) {} -// CHECK: define{{.*}} void @f_ret_char_char_double_s(ptr noalias sret(%struct.char_char_double_s) align 4 %agg.result) +// CHECK: define{{.*}} void @f_ret_char_char_double_s(ptr dead_on_unwind noalias writable sret(%struct.char_char_double_s) align 4 %agg.result) struct char_char_double_s f_ret_char_char_double_s(void) { return (struct char_char_double_s){1, 2, 3.0}; } @@ -339,19 +339,19 @@ union double_u f_ret_double_u(void) { return (union double_u){1.0}; } -// CHECK: define{{.*}} void @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(ptr noalias sret(%struct.double_int32_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) +// CHECK: define{{.*}} void @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(ptr dead_on_unwind noalias writable sret(%struct.double_int32_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) struct double_int32_s f_ret_double_int32_s_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return (struct double_int32_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(ptr noalias sret(%struct.double_double_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) +// CHECK: define{{.*}} void @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(ptr dead_on_unwind noalias writable sret(%struct.double_double_s) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) struct double_double_s f_ret_double_double_s_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return (struct double_double_s){1.0, 2.0}; } -// CHECK: define{{.*}} void @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(ptr noalias sret({ double, double }) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) +// CHECK: define{{.*}} void @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(ptr dead_on_unwind noalias writable sret({ double, double }) align 4 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, [3 x i32] %h.coerce) double __complex__ f_ret_doublecomplex_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return 1.0; @@ -377,7 +377,7 @@ struct large { // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(ptr noalias sret(%struct.large) align 4 %agg.result, float noundef %a, i64 noundef %b, double noundef %c, double noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef zeroext %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(ptr dead_on_unwind noalias writable sret(%struct.large) align 4 %agg.result, float noundef %a, i64 noundef %b, double noundef %c, double noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef zeroext %g) struct large f_scalar_stack_2(float a, int64_t b, double c, long double d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; diff --git a/clang/test/CodeGen/PowerPC/aix-alignment.c b/clang/test/CodeGen/PowerPC/aix-alignment.c index e25fc7ec5599..f732e94569ef 100644 --- a/clang/test/CodeGen/PowerPC/aix-alignment.c +++ b/clang/test/CodeGen/PowerPC/aix-alignment.c @@ -22,8 +22,8 @@ StructDouble d1; // AIX: ret double %0 double retDouble(double x) { return x; } -// AIX32: define void @bar(ptr noalias sret(%struct.StructDouble) align 4 %agg.result, ptr noundef byval(%struct.StructDouble) align 4 %x) -// AIX64: define void @bar(ptr noalias sret(%struct.StructDouble) align 4 %agg.result, ptr noundef byval(%struct.StructDouble) align 8 %x) +// AIX32: define void @bar(ptr dead_on_unwind noalias writable sret(%struct.StructDouble) align 4 %agg.result, ptr noundef byval(%struct.StructDouble) align 4 %x) +// AIX64: define void @bar(ptr dead_on_unwind noalias writable sret(%struct.StructDouble) align 4 %agg.result, ptr noundef byval(%struct.StructDouble) align 8 %x) // AIX32: call void @llvm.memcpy.p0.p0.i32(ptr align 4 %agg.result, ptr align 4 %x, i32 16, i1 false) // AIX64: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.result, ptr align 8 %x, i64 16, i1 false) StructDouble bar(StructDouble x) { return x; } diff --git a/clang/test/CodeGen/PowerPC/powerpc-c99complex.c b/clang/test/CodeGen/PowerPC/powerpc-c99complex.c index f01c7820857e..82b5ac0fdc06 100644 --- a/clang/test/CodeGen/PowerPC/powerpc-c99complex.c +++ b/clang/test/CodeGen/PowerPC/powerpc-c99complex.c @@ -9,7 +9,7 @@ _Complex float foo1(_Complex float x) { // CHECK-LABEL: define{{.*}} { float, float } @foo1(float noundef %x.{{.*}}, float noundef %x.{{.*}}) #0 { // CHECK: ret { float, float } -// PPC32LNX-LABEL: define{{.*}} void @foo1(ptr noalias sret({ float, float }) align 4 %agg.result, ptr noundef byval({ float, float }) align 4 %x) #0 { +// PPC32LNX-LABEL: define{{.*}} void @foo1(ptr dead_on_unwind noalias writable sret({ float, float }) align 4 %agg.result, ptr noundef byval({ float, float }) align 4 %x) #0 { // PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { float, float }, ptr %agg.result, i32 0, i32 0 // PPC32LNX-NEXT: [[RETIMAG:%.*]] = getelementptr inbounds { float, float }, ptr %agg.result, i32 0, i32 1 // PPC32LNX-NEXT: store float %{{.*}}, ptr [[RETREAL]], align 4 @@ -21,7 +21,7 @@ _Complex double foo2(_Complex double x) { // CHECK-LABEL: define{{.*}} { double, double } @foo2(double noundef %x.{{.*}}, double noundef %x.{{.*}}) #0 { // CHECK: ret { double, double } -// PPC32LNX-LABEL: define{{.*}} void @foo2(ptr noalias sret({ double, double }) align 8 %agg.result, ptr noundef byval({ double, double }) align 8 %x) #0 { +// PPC32LNX-LABEL: define{{.*}} void @foo2(ptr dead_on_unwind noalias writable sret({ double, double }) align 8 %agg.result, ptr noundef byval({ double, double }) align 8 %x) #0 { // PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { double, double }, ptr %agg.result, i32 0, i32 0 // PPC32LNX-NEXT: [[RETIMAG:%.*]] = getelementptr inbounds { double, double }, ptr %agg.result, i32 0, i32 1 // PPC32LNX-NEXT: store double %{{.*}}, ptr [[RETREAL]], align 8 @@ -36,7 +36,7 @@ _Complex long double foo3(_Complex long double x) { // CHECK-LDBL128-LABEL: define{{.*}} { ppc_fp128, ppc_fp128 } @foo3(ppc_fp128 noundef %x.{{.*}}, ppc_fp128 noundef %x.{{.*}}) #0 { // CHECK-LDBL128: ret { ppc_fp128, ppc_fp128 } -// PPC32LNX-LABEL: define{{.*}} void @foo3(ptr noalias sret({ ppc_fp128, ppc_fp128 }) align 16 %agg.result, ptr noundef byval({ ppc_fp128, ppc_fp128 }) align 16 %x) #0 { +// PPC32LNX-LABEL: define{{.*}} void @foo3(ptr dead_on_unwind noalias writable sret({ ppc_fp128, ppc_fp128 }) align 16 %agg.result, ptr noundef byval({ ppc_fp128, ppc_fp128 }) align 16 %x) #0 { // PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, ptr %agg.result, i32 0, i32 0 // PPC32LNX-NEXT: [[RETIMAG:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, ptr %agg.result, i32 0, i32 1 // PPC32LNX-NEXT: store ppc_fp128 %{{.*}}, ptr [[RETREAL]], align 16 diff --git a/clang/test/CodeGen/PowerPC/ppc-aggregate-abi.cpp b/clang/test/CodeGen/PowerPC/ppc-aggregate-abi.cpp index 0c094891fec5..a7f7f3ee558c 100644 --- a/clang/test/CodeGen/PowerPC/ppc-aggregate-abi.cpp +++ b/clang/test/CodeGen/PowerPC/ppc-aggregate-abi.cpp @@ -4,57 +4,57 @@ // RUN: -o - %s | FileCheck %s -check-prefix=CHECK-LE class agg_float_class { float a; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(ptr noalias sret(%class.agg_float_class) align 4 %{{.*}}, float inreg %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(ptr dead_on_unwind noalias writable sret(%class.agg_float_class) align 4 %{{.*}}, float inreg %{{.*}}) // CHECK-LE-LABEL: define{{.*}} [1 x float] @_Z20pass_agg_float_class15agg_float_class(float inreg %{{.*}}) agg_float_class pass_agg_float_class(agg_float_class arg) { return arg; } class agg_double_class { double a; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(ptr noalias sret(%class.agg_double_class) align 8 %{{.*}}, double inreg %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(ptr dead_on_unwind noalias writable sret(%class.agg_double_class) align 8 %{{.*}}, double inreg %{{.*}}) // CHECK-LE-LABEL: define{{.*}} [1 x double] @_Z21pass_agg_double_class16agg_double_class(double inreg %{{.*}}) agg_double_class pass_agg_double_class(agg_double_class arg) { return arg; } struct agg_float_cpp { float a; int : 0; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(ptr noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, float inreg %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(ptr dead_on_unwind noalias writable sret(%struct.agg_float_cpp) align 4 %{{.*}}, float inreg %{{.*}}) // CHECK-LE-LABEL: define{{.*}} [1 x float] @_Z18pass_agg_float_cpp13agg_float_cpp(float inreg %{{.*}}) agg_float_cpp pass_agg_float_cpp(agg_float_cpp arg) { return arg; } struct empty { }; struct agg_nofloat_empty { float a; empty dummy; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(ptr noalias sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LE-LABEL: define{{.*}} i64 @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(i64 %{{.*}}) agg_nofloat_empty pass_agg_nofloat_empty(agg_nofloat_empty arg) { return arg; } struct agg_float_empty { float a; [[no_unique_address]] empty dummy; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(ptr noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, float inreg %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(ptr dead_on_unwind noalias writable sret(%struct.agg_float_empty) align 4 %{{.*}}, float inreg %{{.*}}) // CHECK-LE-LABEL: define{{.*}} [1 x float] @_Z20pass_agg_float_empty15agg_float_empty(float inreg %{{.*}}) agg_float_empty pass_agg_float_empty(agg_float_empty arg) { return arg; } struct agg_nofloat_emptyarray { float a; [[no_unique_address]] empty dummy[3]; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(ptr noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LE-LABEL: define{{.*}} i64 @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(i64 %{{.*}}) agg_nofloat_emptyarray pass_agg_nofloat_emptyarray(agg_nofloat_emptyarray arg) { return arg; } struct noemptybase { empty dummy; }; struct agg_nofloat_emptybase : noemptybase { float a; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr noalias sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LE-LABEL: define{{.*}} i64 @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(i64 %{{.*}}) agg_nofloat_emptybase pass_agg_nofloat_emptybase(agg_nofloat_emptybase arg) { return arg; } struct emptybase { [[no_unique_address]] empty dummy; }; struct agg_float_emptybase : emptybase { float a; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float inreg %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr dead_on_unwind noalias writable sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float inreg %{{.*}}) // CHECK-LE-LABEL: define{{.*}} [1 x float] @_Z24pass_agg_float_emptybase19agg_float_emptybase(float inreg %{{.*}}) agg_float_emptybase pass_agg_float_emptybase(agg_float_emptybase arg) { return arg; } struct noemptybasearray { [[no_unique_address]] empty dummy[3]; }; struct agg_nofloat_emptybasearray : noemptybasearray { float a; }; -// CHECK-BE-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(ptr noalias sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-BE-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LE-LABEL: define{{.*}} i64 @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(i64 %{{.*}}) agg_nofloat_emptybasearray pass_agg_nofloat_emptybasearray(agg_nofloat_emptybasearray arg) { return arg; } -// CHECK-BE: call void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float inreg %{{.*}}) +// CHECK-BE: call void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr dead_on_unwind writable sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float inreg %{{.*}}) // CHECK-LE: call [1 x float] @_Z24pass_agg_float_emptybase19agg_float_emptybase(float inreg %{{.*}}) void pass_agg_float_emptybase_ptr(agg_float_emptybase* arg) { pass_agg_float_emptybase(*arg); } -// CHECK-BE: call void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-BE: call void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr dead_on_unwind writable sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LE: call i64 @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(i64 %{{.*}}) void pass_agg_nofloat_emptybase_ptr(agg_nofloat_emptybase* arg) { pass_agg_nofloat_emptybase(*arg); } diff --git a/clang/test/CodeGen/PowerPC/ppc32-and-aix-struct-return.c b/clang/test/CodeGen/PowerPC/ppc32-and-aix-struct-return.c index b0bb089d664c..cfe5c1ca3e85 100644 --- a/clang/test/CodeGen/PowerPC/ppc32-and-aix-struct-return.c +++ b/clang/test/CodeGen/PowerPC/ppc32-and-aix-struct-return.c @@ -59,42 +59,42 @@ typedef struct { char c[9]; } Nine; -// CHECK-AIX-LABEL: define{{.*}} void @ret0(ptr noalias sret(%struct.Zero) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret0(ptr dead_on_unwind noalias writable sret(%struct.Zero) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} void @ret0() Zero ret0(void) { return (Zero){}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret1(ptr noalias sret(%struct.One) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret1(ptr dead_on_unwind noalias writable sret(%struct.One) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i8 @ret1() One ret1(void) { return (One){'a'}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret2(ptr noalias sret(%struct.Two) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret2(ptr dead_on_unwind noalias writable sret(%struct.Two) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i16 @ret2() Two ret2(void) { return (Two){123}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret3(ptr noalias sret(%struct.Three) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret3(ptr dead_on_unwind noalias writable sret(%struct.Three) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i24 @ret3() Three ret3(void) { return (Three){"abc"}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret4(ptr noalias sret(%struct.Four) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret4(ptr dead_on_unwind noalias writable sret(%struct.Four) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i32 @ret4() Four ret4(void) { return (Four){0.4}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret5(ptr noalias sret(%struct.Five) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret5(ptr dead_on_unwind noalias writable sret(%struct.Five) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i40 @ret5() Five ret5(void) { return (Five){"abcde"}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret6(ptr noalias sret(%struct.Six) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret6(ptr dead_on_unwind noalias writable sret(%struct.Six) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i48 @ret6() Six ret6(void) { return (Six){12, 34, 56}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret7(ptr noalias sret(%struct.Seven) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret7(ptr dead_on_unwind noalias writable sret(%struct.Seven) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i56 @ret7() Seven ret7(void) { return (Seven){"abcdefg"}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret8(ptr noalias sret(%struct.Eight) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret8(ptr dead_on_unwind noalias writable sret(%struct.Eight) {{[^,]*}}) // CHECK-SVR4-LABEL: define{{.*}} i64 @ret8() Eight ret8(void) { return (Eight){123, 'a'}; } -// CHECK-AIX-LABEL: define{{.*}} void @ret9(ptr noalias sret(%struct.Nine) {{[^,]*}}) -// CHECK-SVR4-LABEL: define{{.*}} void @ret9(ptr noalias sret(%struct.Nine) {{[^,]*}}) +// CHECK-AIX-LABEL: define{{.*}} void @ret9(ptr dead_on_unwind noalias writable sret(%struct.Nine) {{[^,]*}}) +// CHECK-SVR4-LABEL: define{{.*}} void @ret9(ptr dead_on_unwind noalias writable sret(%struct.Nine) {{[^,]*}}) Nine ret9(void) { return (Nine){"abcdefghi"}; } diff --git a/clang/test/CodeGen/PowerPC/ppc64-align-struct.c b/clang/test/CodeGen/PowerPC/ppc64-align-struct.c index 2476c7149d07..50e8330fceae 100644 --- a/clang/test/CodeGen/PowerPC/ppc64-align-struct.c +++ b/clang/test/CodeGen/PowerPC/ppc64-align-struct.c @@ -60,7 +60,7 @@ void test9 (int x, struct test9 y) { } -// CHECK: define{{.*}} void @test1va(ptr noalias sret(%struct.test1) align 4 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test1va(ptr dead_on_unwind noalias writable sret(%struct.test1) align 4 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 8 // CHECK: store ptr %[[NEXT]], ptr %ap @@ -75,7 +75,7 @@ struct test1 test1va (int x, ...) return y; } -// CHECK: define{{.*}} void @test2va(ptr noalias sret(%struct.test2) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test2va(ptr dead_on_unwind noalias writable sret(%struct.test2) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[TMP0:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i32 15 // CHECK: %[[ALIGN:[^ ]+]] = call ptr @llvm.ptrmask.p0.i64(ptr %[[TMP0]], i64 -16) @@ -92,7 +92,7 @@ struct test2 test2va (int x, ...) return y; } -// CHECK: define{{.*}} void @test3va(ptr noalias sret(%struct.test3) align 32 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test3va(ptr dead_on_unwind noalias writable sret(%struct.test3) align 32 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[TMP0:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i32 15 // CHECK: %[[ALIGN:[^ ]+]] = call ptr @llvm.ptrmask.p0.i64(ptr %[[TMP0]], i64 -16) @@ -109,7 +109,7 @@ struct test3 test3va (int x, ...) return y; } -// CHECK: define{{.*}} void @test4va(ptr noalias sret(%struct.test4) align 4 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test4va(ptr dead_on_unwind noalias writable sret(%struct.test4) align 4 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 16 // CHECK: store ptr %[[NEXT]], ptr %ap @@ -124,7 +124,7 @@ struct test4 test4va (int x, ...) return y; } -// CHECK: define{{.*}} void @test8va(ptr noalias sret(%struct.test8) align 1 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test8va(ptr dead_on_unwind noalias writable sret(%struct.test8) align 1 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 8 // CHECK: store ptr %[[NEXT]], ptr %ap @@ -140,7 +140,7 @@ struct test8 test8va (int x, ...) return y; } -// CHECK: define{{.*}} void @test9va(ptr noalias sret(%struct.test9) align 1 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test9va(ptr dead_on_unwind noalias writable sret(%struct.test9) align 1 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 8 // CHECK: store ptr %[[NEXT]], ptr %ap @@ -156,7 +156,7 @@ struct test9 test9va (int x, ...) return y; } -// CHECK: define{{.*}} void @testva_longdouble(ptr noalias sret(%struct.test_longdouble) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @testva_longdouble(ptr dead_on_unwind noalias writable sret(%struct.test_longdouble) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 16 // CHECK: store ptr %[[NEXT]], ptr %ap @@ -172,7 +172,7 @@ struct test_longdouble testva_longdouble (int x, ...) return y; } -// CHECK: define{{.*}} void @testva_vector(ptr noalias sret(%struct.test_vector) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @testva_vector(ptr dead_on_unwind noalias writable sret(%struct.test_vector) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap // CHECK: %[[TMP0:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i32 15 // CHECK: %[[ALIGN:[^ ]+]] = call ptr @llvm.ptrmask.p0.i64(ptr %[[TMP0]], i64 -16) diff --git a/clang/test/CodeGen/PowerPC/ppc64-elf-abi.c b/clang/test/CodeGen/PowerPC/ppc64-elf-abi.c index 64bff635af95..fa7f79455fda 100644 --- a/clang/test/CodeGen/PowerPC/ppc64-elf-abi.c +++ b/clang/test/CodeGen/PowerPC/ppc64-elf-abi.c @@ -15,7 +15,7 @@ // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s \ // RUN: -target-abi elfv2 | FileCheck %s --check-prefix=CHECK-ELFv2 -// CHECK-ELFv1: define{{.*}} void @func_fab(ptr noalias sret(%struct.fab) align 4 %agg.result, i64 %x.coerce) +// CHECK-ELFv1: define{{.*}} void @func_fab(ptr dead_on_unwind noalias writable sret(%struct.fab) align 4 %agg.result, i64 %x.coerce) // CHECK-ELFv2: define{{.*}} [2 x float] @func_fab([2 x float] %x.coerce) struct fab { float a; float b; }; struct fab func_fab(struct fab x) { return x; } diff --git a/clang/test/CodeGen/PowerPC/ppc64-soft-float.c b/clang/test/CodeGen/PowerPC/ppc64-soft-float.c index c2e887ef7ab6..812d9ff5a350 100644 --- a/clang/test/CodeGen/PowerPC/ppc64-soft-float.c +++ b/clang/test/CodeGen/PowerPC/ppc64-soft-float.c @@ -30,53 +30,53 @@ struct fabc { float a; float b; float c; }; struct f2a2b { float a[2]; float b[2]; }; // CHECK-LE: define{{.*}} i32 @func_f1(float inreg %x.coerce) -// CHECK-BE: define{{.*}} void @func_f1(ptr noalias sret(%struct.f1) align 4 %agg.result, float inreg %x.coerce) +// CHECK-BE: define{{.*}} void @func_f1(ptr dead_on_unwind noalias writable sret(%struct.f1) align 4 %agg.result, float inreg %x.coerce) struct f1 func_f1(struct f1 x) { return x; } // CHECK-LE: define{{.*}} i64 @func_f2(i64 %x.coerce) -// CHECK-BE: define{{.*}} void @func_f2(ptr noalias sret(%struct.f2) align 4 %agg.result, i64 %x.coerce) +// CHECK-BE: define{{.*}} void @func_f2(ptr dead_on_unwind noalias writable sret(%struct.f2) align 4 %agg.result, i64 %x.coerce) struct f2 func_f2(struct f2 x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_f3([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_f3(ptr noalias sret(%struct.f3) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_f3(ptr dead_on_unwind noalias writable sret(%struct.f3) align 4 %agg.result, [2 x i64] %x.coerce) struct f3 func_f3(struct f3 x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_f4([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_f4(ptr noalias sret(%struct.f4) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_f4(ptr dead_on_unwind noalias writable sret(%struct.f4) align 4 %agg.result, [2 x i64] %x.coerce) struct f4 func_f4(struct f4 x) { return x; } -// CHECK: define{{.*}} void @func_f5(ptr noalias sret(%struct.f5) align 4 %agg.result, [3 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f5(ptr dead_on_unwind noalias writable sret(%struct.f5) align 4 %agg.result, [3 x i64] %x.coerce) struct f5 func_f5(struct f5 x) { return x; } -// CHECK: define{{.*}} void @func_f6(ptr noalias sret(%struct.f6) align 4 %agg.result, [3 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f6(ptr dead_on_unwind noalias writable sret(%struct.f6) align 4 %agg.result, [3 x i64] %x.coerce) struct f6 func_f6(struct f6 x) { return x; } -// CHECK: define{{.*}} void @func_f7(ptr noalias sret(%struct.f7) align 4 %agg.result, [4 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f7(ptr dead_on_unwind noalias writable sret(%struct.f7) align 4 %agg.result, [4 x i64] %x.coerce) struct f7 func_f7(struct f7 x) { return x; } -// CHECK: define{{.*}} void @func_f8(ptr noalias sret(%struct.f8) align 4 %agg.result, [4 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f8(ptr dead_on_unwind noalias writable sret(%struct.f8) align 4 %agg.result, [4 x i64] %x.coerce) struct f8 func_f8(struct f8 x) { return x; } -// CHECK: define{{.*}} void @func_f9(ptr noalias sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f9(ptr dead_on_unwind noalias writable sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) struct f9 func_f9(struct f9 x) { return x; } // CHECK-LE: define{{.*}} i64 @func_fab(i64 %x.coerce) -// CHECK-BE: define{{.*}} void @func_fab(ptr noalias sret(%struct.fab) align 4 %agg.result, i64 %x.coerce) +// CHECK-BE: define{{.*}} void @func_fab(ptr dead_on_unwind noalias writable sret(%struct.fab) align 4 %agg.result, i64 %x.coerce) struct fab func_fab(struct fab x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_fabc([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_fabc(ptr noalias sret(%struct.fabc) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_fabc(ptr dead_on_unwind noalias writable sret(%struct.fabc) align 4 %agg.result, [2 x i64] %x.coerce) struct fabc func_fabc(struct fabc x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_f2a2b([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_f2a2b(ptr noalias sret(%struct.f2a2b) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_f2a2b(ptr dead_on_unwind noalias writable sret(%struct.f2a2b) align 4 %agg.result, [2 x i64] %x.coerce) struct f2a2b func_f2a2b(struct f2a2b x) { return x; } // CHECK-LABEL: @call_f1 // CHECK-BE: %[[TMP0:[^ ]+]] = alloca %struct.f1, align 4 // CHECK: %[[TMP:[^ ]+]] = load float, ptr @global_f1, align 4 // CHECK-LE: call i32 @func_f1(float inreg %[[TMP]]) -// CHECK-BE: call void @func_f1(ptr sret(%struct.f1) align 4 %[[TMP0]], float inreg %[[TMP]]) +// CHECK-BE: call void @func_f1(ptr dead_on_unwind writable sret(%struct.f1) align 4 %[[TMP0]], float inreg %[[TMP]]) struct f1 global_f1; void call_f1(void) { global_f1 = func_f1(global_f1); } @@ -84,7 +84,7 @@ void call_f1(void) { global_f1 = func_f1(global_f1); } // CHECK-BE: %[[TMP0:[^ ]+]] = alloca %struct.f2, align 4 // CHECK: %[[TMP:[^ ]+]] = load i64, ptr @global_f2, align 4 // CHECK-LE: call i64 @func_f2(i64 %[[TMP]]) -// CHECK-BE: call void @func_f2(ptr sret(%struct.f2) align 4 %[[TMP0]], i64 %[[TMP]]) +// CHECK-BE: call void @func_f2(ptr dead_on_unwind writable sret(%struct.f2) align 4 %[[TMP0]], i64 %[[TMP]]) struct f2 global_f2; void call_f2(void) { global_f2 = func_f2(global_f2); } @@ -94,7 +94,7 @@ void call_f2(void) { global_f2 = func_f2(global_f2); } // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f3, i64 12, i1 false) // CHECK: %[[TMP3:[^ ]+]] = load [2 x i64], ptr %[[TMP1]] // CHECK-LE: call { i64, i64 } @func_f3([2 x i64] %[[TMP3]]) -// CHECK-BE: call void @func_f3(ptr sret(%struct.f3) align 4 %[[TMP0]], [2 x i64] %[[TMP3]]) +// CHECK-BE: call void @func_f3(ptr dead_on_unwind writable sret(%struct.f3) align 4 %[[TMP0]], [2 x i64] %[[TMP3]]) struct f3 global_f3; void call_f3(void) { global_f3 = func_f3(global_f3); } @@ -102,7 +102,7 @@ void call_f3(void) { global_f3 = func_f3(global_f3); } // CHECK-BE: %[[TMP0:[^ ]+]] = alloca %struct.f4, align 4 // CHECK: %[[TMP:[^ ]+]] = load [2 x i64], ptr @global_f4, align 4 // CHECK-LE: call { i64, i64 } @func_f4([2 x i64] %[[TMP]]) -// CHECK-BE: call void @func_f4(ptr sret(%struct.f4) align 4 %[[TMP0]], [2 x i64] %[[TMP]]) +// CHECK-BE: call void @func_f4(ptr dead_on_unwind writable sret(%struct.f4) align 4 %[[TMP0]], [2 x i64] %[[TMP]]) struct f4 global_f4; void call_f4(void) { global_f4 = func_f4(global_f4); } @@ -111,14 +111,14 @@ void call_f4(void) { global_f4 = func_f4(global_f4); } // CHECK: %[[TMP1:[^ ]+]] = alloca [3 x i64] // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f5, i64 20, i1 false) // CHECK: %[[TMP3:[^ ]+]] = load [3 x i64], ptr %[[TMP1]] -// CHECK: call void @func_f5(ptr sret(%struct.f5) align 4 %[[TMP0]], [3 x i64] %[[TMP3]]) +// CHECK: call void @func_f5(ptr dead_on_unwind writable sret(%struct.f5) align 4 %[[TMP0]], [3 x i64] %[[TMP3]]) struct f5 global_f5; void call_f5(void) { global_f5 = func_f5(global_f5); } // CHECK-LABEL: @call_f6 // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.f6, align 4 // CHECK: %[[TMP:[^ ]+]] = load [3 x i64], ptr @global_f6, align 4 -// CHECK: call void @func_f6(ptr sret(%struct.f6) align 4 %[[TMP0]], [3 x i64] %[[TMP]]) +// CHECK: call void @func_f6(ptr dead_on_unwind writable sret(%struct.f6) align 4 %[[TMP0]], [3 x i64] %[[TMP]]) struct f6 global_f6; void call_f6(void) { global_f6 = func_f6(global_f6); } @@ -127,14 +127,14 @@ void call_f6(void) { global_f6 = func_f6(global_f6); } // CHECK: %[[TMP1:[^ ]+]] = alloca [4 x i64], align 8 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f7, i64 28, i1 false) // CHECK: %[[TMP3:[^ ]+]] = load [4 x i64], ptr %[[TMP1]], align 8 -// CHECK: call void @func_f7(ptr sret(%struct.f7) align 4 %[[TMP0]], [4 x i64] %[[TMP3]]) +// CHECK: call void @func_f7(ptr dead_on_unwind writable sret(%struct.f7) align 4 %[[TMP0]], [4 x i64] %[[TMP3]]) struct f7 global_f7; void call_f7(void) { global_f7 = func_f7(global_f7); } // CHECK-LABEL: @call_f8 // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.f8, align 4 // CHECK: %[[TMP:[^ ]+]] = load [4 x i64], ptr @global_f8, align 4 -// CHECK: call void @func_f8(ptr sret(%struct.f8) align 4 %[[TMP0]], [4 x i64] %[[TMP]]) +// CHECK: call void @func_f8(ptr dead_on_unwind writable sret(%struct.f8) align 4 %[[TMP0]], [4 x i64] %[[TMP]]) struct f8 global_f8; void call_f8(void) { global_f8 = func_f8(global_f8); } @@ -142,7 +142,7 @@ void call_f8(void) { global_f8 = func_f8(global_f8); } // CHECK: %[[TMP1:[^ ]+]] = alloca [5 x i64] // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f9, i64 36, i1 false) // CHECK: %[[TMP3:[^ ]+]] = load [5 x i64], ptr %[[TMP1]] -// CHECK: call void @func_f9(ptr sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) +// CHECK: call void @func_f9(ptr dead_on_unwind writable sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) struct f9 global_f9; void call_f9(void) { global_f9 = func_f9(global_f9); } @@ -150,7 +150,7 @@ void call_f9(void) { global_f9 = func_f9(global_f9); } // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.fab, align 4 // CHECK: %[[TMP:[^ ]+]] = load i64, ptr @global_fab, align 4 // CHECK-LE: %call = call i64 @func_fab(i64 %[[TMP]]) -// CHECK-BE: call void @func_fab(ptr sret(%struct.fab) align 4 %[[TMP0]], i64 %[[TMP]]) +// CHECK-BE: call void @func_fab(ptr dead_on_unwind writable sret(%struct.fab) align 4 %[[TMP0]], i64 %[[TMP]]) struct fab global_fab; void call_fab(void) { global_fab = func_fab(global_fab); } @@ -160,7 +160,7 @@ void call_fab(void) { global_fab = func_fab(global_fab); } // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP0]], ptr align 4 @global_fabc, i64 12, i1 false) // CHECK: %[[TMP3:[^ ]+]] = load [2 x i64], ptr %[[TMP0]], align 8 // CHECK-LE: %call = call { i64, i64 } @func_fabc([2 x i64] %[[TMP3]]) -// CHECK-BE: call void @func_fabc(ptr sret(%struct.fabc) align 4 %[[TMPX]], [2 x i64] %[[TMP3]]) +// CHECK-BE: call void @func_fabc(ptr dead_on_unwind writable sret(%struct.fabc) align 4 %[[TMPX]], [2 x i64] %[[TMP3]]) struct fabc global_fabc; void call_fabc(void) { global_fabc = func_fabc(global_fabc); } diff --git a/clang/test/CodeGen/PowerPC/ppc64-vector.c b/clang/test/CodeGen/PowerPC/ppc64-vector.c index 2e685799efa0..5d3dd86a009d 100644 --- a/clang/test/CodeGen/PowerPC/ppc64-vector.c +++ b/clang/test/CodeGen/PowerPC/ppc64-vector.c @@ -39,13 +39,13 @@ v8i16 test_v8i16(v8i16 x) return x; } -// CHECK: define{{.*}} void @test_v16i16(ptr noalias sret(<16 x i16>) align 32 %agg.result, ptr noundef %0) +// CHECK: define{{.*}} void @test_v16i16(ptr dead_on_unwind noalias writable sret(<16 x i16>) align 32 %agg.result, ptr noundef %0) v16i16 test_v16i16(v16i16 x) { return x; } -// CHECK: define{{.*}} void @test_struct_v16i16(ptr noalias sret(%struct.v16i16) align 32 %agg.result, [2 x i128] %x.coerce) +// CHECK: define{{.*}} void @test_struct_v16i16(ptr dead_on_unwind noalias writable sret(%struct.v16i16) align 32 %agg.result, [2 x i128] %x.coerce) struct v16i16 test_struct_v16i16(struct v16i16 x) { return x; diff --git a/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c b/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c index 42b179217dd2..3ea85a6a8ff3 100644 --- a/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c +++ b/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c @@ -41,7 +41,7 @@ struct f7 func_f7(struct f7 x) { return x; } // CHECK: define{{.*}} [8 x float] @func_f8([8 x float] %x.coerce) struct f8 func_f8(struct f8 x) { return x; } -// CHECK: define{{.*}} void @func_f9(ptr noalias sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f9(ptr dead_on_unwind noalias writable sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) struct f9 func_f9(struct f9 x) { return x; } // CHECK: define{{.*}} [2 x float] @func_fab([2 x float] %x.coerce) @@ -105,7 +105,7 @@ void call_f8(void) { global_f8 = func_f8(global_f8); } // CHECK: %[[TMP1:[^ ]+]] = alloca [5 x i64] // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f9, i64 36, i1 false) // CHECK: %[[TMP3:[^ ]+]] = load [5 x i64], ptr %[[TMP1]] -// CHECK: call void @func_f9(ptr sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) +// CHECK: call void @func_f9(ptr dead_on_unwind writable sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) struct f9 global_f9; void call_f9(void) { global_f9 = func_f9(global_f9); } @@ -161,7 +161,7 @@ struct v7 func_v7(struct v7 x) { return x; } // CHECK: define{{.*}} [8 x <4 x i32>] @func_v8([8 x <4 x i32>] %x.coerce) struct v8 func_v8(struct v8 x) { return x; } -// CHECK: define{{.*}} void @func_v9(ptr noalias sret(%struct.v9) align 16 %agg.result, ptr noundef byval(%struct.v9) align 16 %x) +// CHECK: define{{.*}} void @func_v9(ptr dead_on_unwind noalias writable sret(%struct.v9) align 16 %agg.result, ptr noundef byval(%struct.v9) align 16 %x) struct v9 func_v9(struct v9 x) { return x; } // CHECK: define{{.*}} [2 x <4 x i32>] @func_vab([2 x <4 x i32>] %x.coerce) @@ -219,7 +219,7 @@ struct v8 global_v8; void call_v8(void) { global_v8 = func_v8(global_v8); } // CHECK-LABEL: @call_v9 -// CHECK: call void @func_v9(ptr sret(%struct.v9) align 16 %{{[^ ]+}}, ptr noundef byval(%struct.v9) align 16 @global_v9) +// CHECK: call void @func_v9(ptr dead_on_unwind writable sret(%struct.v9) align 16 %{{[^ ]+}}, ptr noundef byval(%struct.v9) align 16 @global_v9) struct v9 global_v9; void call_v9(void) { global_v9 = func_v9(global_v9); } @@ -278,7 +278,7 @@ struct v3f7 func_v3f7(struct v3f7 x) { return x; } // CHECK: define{{.*}} [8 x <4 x float>] @func_v3f8([8 x <4 x float>] %x.coerce) struct v3f8 func_v3f8(struct v3f8 x) { return x; } -// CHECK: define{{.*}} void @func_v3f9(ptr noalias sret(%struct.v3f9) align 16 %agg.result, ptr noundef byval(%struct.v3f9) align 16 %x) +// CHECK: define{{.*}} void @func_v3f9(ptr dead_on_unwind noalias writable sret(%struct.v3f9) align 16 %agg.result, ptr noundef byval(%struct.v3f9) align 16 %x) struct v3f9 func_v3f9(struct v3f9 x) { return x; } // CHECK: define{{.*}} [2 x <4 x float>] @func_v3fab([2 x <4 x float>] %x.coerce) @@ -336,7 +336,7 @@ struct v3f8 global_v3f8; void call_v3f8(void) { global_v3f8 = func_v3f8(global_v3f8); } // CHECK-LABEL: @call_v3f9 -// CHECK: call void @func_v3f9(ptr sret(%struct.v3f9) align 16 %{{[^ ]+}}, ptr noundef byval(%struct.v3f9) align 16 @global_v3f9) +// CHECK: call void @func_v3f9(ptr dead_on_unwind writable sret(%struct.v3f9) align 16 %{{[^ ]+}}, ptr noundef byval(%struct.v3f9) align 16 @global_v3f9) struct v3f9 global_v3f9; void call_v3f9(void) { global_v3f9 = func_v3f9(global_v3f9); } diff --git a/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c b/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c index 27c3b14f0a04..b2e79d6be9b8 100644 --- a/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c +++ b/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c @@ -42,7 +42,7 @@ struct fp7 func_f7(struct fp7 x) { return x; } // CHECK: define{{.*}} [8 x fp128] @func_f8([8 x fp128] %x.coerce) struct fp8 func_f8(struct fp8 x) { return x; } -// CHECK: define{{.*}} void @func_f9(ptr noalias sret(%struct.fp9) align 16 %agg.result, ptr noundef byval(%struct.fp9) align 16 %x) +// CHECK: define{{.*}} void @func_f9(ptr dead_on_unwind noalias writable sret(%struct.fp9) align 16 %agg.result, ptr noundef byval(%struct.fp9) align 16 %x) struct fp9 func_f9(struct fp9 x) { return x; } // CHECK: define{{.*}} [2 x fp128] @func_fab([2 x fp128] %x.coerce) @@ -104,7 +104,7 @@ void call_fp8(void) { global_f8 = func_f8(global_f8); } // CHECK-LABEL: @call_fp9 // CHECK: %[[TMP1:[^ ]+]] = alloca %struct.fp9, align 16 -// CHECK: call void @func_f9(ptr sret(%struct.fp9) align 16 %[[TMP2:[^ ]+]], ptr noundef byval(%struct.fp9) align 16 @global_f9 +// CHECK: call void @func_f9(ptr dead_on_unwind writable sret(%struct.fp9) align 16 %[[TMP2:[^ ]+]], ptr noundef byval(%struct.fp9) align 16 @global_f9 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 16 @global_f9, ptr align 16 %[[TMP2]], i64 144, i1 false // CHECK: ret void struct fp9 global_f9; diff --git a/clang/test/CodeGen/RISCV/bfloat-abi.c b/clang/test/CodeGen/RISCV/bfloat-abi.c index bfaf1043133b..f38646c8b12f 100644 --- a/clang/test/CodeGen/RISCV/bfloat-abi.c +++ b/clang/test/CodeGen/RISCV/bfloat-abi.c @@ -467,7 +467,7 @@ struct floatbfloat3 { // CHECK-RV64-NEXT: ret [2 x i64] [[TMP4]] // // CHECK-RV32-LABEL: define dso_local void @fh3 -// CHECK-RV32-SAME: (ptr noalias sret([[STRUCT_FLOATBFLOAT3:%.*]]) align 4 [[AGG_RESULT:%.*]], float noundef [[A:%.*]], bfloat noundef [[B:%.*]], bfloat noundef [[C:%.*]], bfloat noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK-RV32-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_FLOATBFLOAT3:%.*]]) align 4 [[AGG_RESULT:%.*]], float noundef [[A:%.*]], bfloat noundef [[B:%.*]], bfloat noundef [[C:%.*]], bfloat noundef [[D:%.*]]) #[[ATTR0]] { // CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 4 // CHECK-RV32-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -545,7 +545,7 @@ struct bfloat5 { // CHECK-RV64-NEXT: ret [2 x i64] [[TMP5]] // // CHECK-RV32-LABEL: define dso_local void @h5 -// CHECK-RV32-SAME: (ptr noalias sret([[STRUCT_BFLOAT5:%.*]]) align 2 [[AGG_RESULT:%.*]], bfloat noundef [[A:%.*]], bfloat noundef [[B:%.*]], bfloat noundef [[C:%.*]], bfloat noundef [[D:%.*]], bfloat noundef [[E:%.*]]) #[[ATTR0]] { +// CHECK-RV32-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_BFLOAT5:%.*]]) align 2 [[AGG_RESULT:%.*]], bfloat noundef [[A:%.*]], bfloat noundef [[B:%.*]], bfloat noundef [[C:%.*]], bfloat noundef [[D:%.*]], bfloat noundef [[E:%.*]]) #[[ATTR0]] { // CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 4 // CHECK-RV32-NEXT: [[A_ADDR:%.*]] = alloca bfloat, align 2 diff --git a/clang/test/CodeGen/RISCV/riscv-abi.cpp b/clang/test/CodeGen/RISCV/riscv-abi.cpp index aa18afe41f6d..fe1a2b6d8595 100644 --- a/clang/test/CodeGen/RISCV/riscv-abi.cpp +++ b/clang/test/CodeGen/RISCV/riscv-abi.cpp @@ -75,7 +75,7 @@ struct child3_int64_s : parent3_float_s { }; // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @_Z30float_int64_struct_inheritance14child3_int64_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_CHILD3_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_CHILD3_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // // LP64-LABEL: define dso_local [2 x i64] @_Z30float_int64_struct_inheritance14child3_int64_s @@ -99,7 +99,7 @@ struct child4_double_s : parent4_double_s { }; // ILP32-ILP32F-LABEL: define dso_local void @_Z32double_double_struct_inheritance15child4_double_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_CHILD4_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_CHILD4_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @_Z32double_double_struct_inheritance15child4_double_s @@ -130,11 +130,11 @@ struct child5_virtual_s : virtual parent5_virtual_s { }; // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @_Z38int32_float_virtual_struct_inheritance16child5_virtual_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_CHILD5_VIRTUAL_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_CHILD5_VIRTUAL_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // // LP64-LP64F-LP64D-LABEL: define dso_local void @_Z38int32_float_virtual_struct_inheritance16child5_virtual_s -// LP64-LP64F-LP64D-SAME: (ptr noalias sret([[STRUCT_CHILD5_VIRTUAL_S:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { +// LP64-LP64F-LP64D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_CHILD5_VIRTUAL_S:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] { // LP64-LP64F-LP64D: entry: // struct child5_virtual_s int32_float_virtual_struct_inheritance(struct child5_virtual_s a) { diff --git a/clang/test/CodeGen/RISCV/riscv32-abi.c b/clang/test/CodeGen/RISCV/riscv32-abi.c index 040ae500fc60..ea1bb3b62ee6 100644 --- a/clang/test/CodeGen/RISCV/riscv32-abi.c +++ b/clang/test/CodeGen/RISCV/riscv32-abi.c @@ -254,7 +254,7 @@ void f_agg_large(struct large x) { // The address where the struct should be written to will be the first // argument // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_agg_large_ret -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_LARGE:%.*]]) align 4 [[AGG_RESULT:%.*]], i32 noundef [[I:%.*]], i8 noundef signext [[J:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_LARGE:%.*]]) align 4 [[AGG_RESULT:%.*]], i32 noundef [[I:%.*]], i8 noundef signext [[J:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct large f_agg_large_ret(int32_t i, int8_t j) { @@ -272,7 +272,7 @@ void f_vec_large_v16i8(v16i8 x) { } // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_vec_large_v16i8_ret -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret(<16 x i8>) align 16 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret(<16 x i8>) align 16 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // v16i8 f_vec_large_v16i8_ret(void) { @@ -292,7 +292,7 @@ int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c, } // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_scalar_stack_2 -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_LARGE:%.*]]) align 4 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]], fp128 noundef [[D:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_LARGE:%.*]]) align 4 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]], fp128 noundef [[D:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct large f_scalar_stack_2(int32_t a, int64_t b, int64_t c, long double d, @@ -329,7 +329,7 @@ int f_scalar_stack_5(int32_t a, int64_t b, float c, double d, long double e, } // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_scalar_stack_6 -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_LARGE:%.*]]) align 4 [[AGG_RESULT:%.*]], float noundef [[A:%.*]], i64 noundef [[B:%.*]], double noundef [[C:%.*]], fp128 noundef [[D:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_LARGE:%.*]]) align 4 [[AGG_RESULT:%.*]], float noundef [[A:%.*]], i64 noundef [[B:%.*]], double noundef [[C:%.*]], fp128 noundef [[D:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct large f_scalar_stack_6(float a, int64_t b, double c, long double d, @@ -374,7 +374,7 @@ struct int_double_s { int a; double b; }; void f_int_double_s_arg(struct int_double_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_int_double_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_INT_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { i32, double } @f_ret_int_double_s @@ -490,7 +490,7 @@ struct double_float_s { double f; float g; }; void f_double_double_s_arg(struct double_double_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_double_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_double_double_s @@ -512,7 +512,7 @@ struct double_double_s f_ret_double_double_s(void) { void f_double_float_s_arg(struct double_float_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_float_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_FLOAT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_FLOAT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, float } @f_ret_double_float_s @@ -547,7 +547,7 @@ struct double_int8_zbf_s { double d; int8_t i; int : 0; }; void f_double_int8_s_arg(struct double_int8_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_double_int8_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_DOUBLE_INT8_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_INT8_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct double_int8_s f_ret_double_int8_s(void) { @@ -565,7 +565,7 @@ struct double_int8_s f_ret_double_int8_s(void) { void f_double_uint8_s_arg(struct double_uint8_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_uint8_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_UINT8_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_UINT8_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, i8 } @f_ret_double_uint8_s @@ -587,7 +587,7 @@ struct double_uint8_s f_ret_double_uint8_s(void) { void f_double_int32_s_arg(struct double_int32_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_int32_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_INT32_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_INT32_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, i32 } @f_ret_double_int32_s @@ -605,7 +605,7 @@ struct double_int32_s f_ret_double_int32_s(void) { void f_double_int64_s_arg(struct double_int64_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_double_int64_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_DOUBLE_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct double_int64_s f_ret_double_int64_s(void) { @@ -623,7 +623,7 @@ struct double_int64_s f_ret_double_int64_s(void) { void f_double_int64bf_s_arg(struct double_int64bf_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_int64bf_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_INT64BF_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_INT64BF_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, i32 } @f_ret_double_int64bf_s @@ -648,7 +648,7 @@ struct double_int64bf_s f_ret_double_int64bf_s(void) { void f_double_int8_zbf_s(struct double_int8_zbf_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_int8_zbf_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_INT8_ZBF_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_INT8_ZBF_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, i8 } @f_ret_double_int8_zbf_s @@ -687,7 +687,7 @@ void f_struct_double_int8_insufficient_fprs(float a, double b, double c, double void f_doublecomplex(double __complex__ a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublecomplex -// ILP32-ILP32F-SAME: (ptr noalias sret({ double, double }) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret({ double, double }) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublecomplex @@ -711,7 +711,7 @@ struct doublecomplex_s { double __complex__ c; }; void f_doublecomplex_s_arg(struct doublecomplex_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublecomplex_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLECOMPLEX_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLECOMPLEX_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublecomplex_s @@ -762,7 +762,7 @@ struct doublearr2_s { double a[2]; }; void f_doublearr2_s_arg(struct doublearr2_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublearr2_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLEARR2_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLEARR2_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublearr2_s @@ -786,7 +786,7 @@ struct doublearr2_tricky1_s { struct { double f[1]; } g[2]; }; void f_doublearr2_tricky1_s_arg(struct doublearr2_tricky1_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublearr2_tricky1_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLEARR2_TRICKY1_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLEARR2_TRICKY1_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublearr2_tricky1_s @@ -810,7 +810,7 @@ struct doublearr2_tricky2_s { struct {}; struct { double f[1]; } g[2]; }; void f_doublearr2_tricky2_s_arg(struct doublearr2_tricky2_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublearr2_tricky2_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLEARR2_TRICKY2_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLEARR2_TRICKY2_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublearr2_tricky2_s @@ -834,7 +834,7 @@ struct doublearr2_tricky3_s { union {}; struct { double f[1]; } g[2]; }; void f_doublearr2_tricky3_s_arg(struct doublearr2_tricky3_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublearr2_tricky3_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLEARR2_TRICKY3_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLEARR2_TRICKY3_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublearr2_tricky3_s @@ -858,7 +858,7 @@ struct doublearr2_tricky4_s { union {}; struct { struct {}; double f[1]; } g[2]; void f_doublearr2_tricky4_s_arg(struct doublearr2_tricky4_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublearr2_tricky4_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLEARR2_TRICKY4_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLEARR2_TRICKY4_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublearr2_tricky4_s @@ -881,7 +881,7 @@ struct int_double_int_s { int a; double b; int c; }; void f_int_double_int_s_arg(struct int_double_int_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_int_double_int_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_INT_DOUBLE_INT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT_DOUBLE_INT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct int_double_int_s f_ret_int_double_int_s(void) { @@ -897,7 +897,7 @@ struct int64_double_s { int64_t a; double b; }; void f_int64_double_s_arg(struct int64_double_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_int64_double_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_INT64_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT64_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct int64_double_s f_ret_int64_double_s(void) { @@ -913,7 +913,7 @@ struct char_char_double_s { char a; char b; double c; }; void f_char_char_double_s_arg(struct char_char_double_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_char_char_double_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_CHAR_CHAR_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_CHAR_CHAR_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct char_char_double_s f_ret_char_char_double_s(void) { @@ -946,7 +946,7 @@ union double_u f_ret_double_u(void) { // double+double structs by the ABI. // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_INT32_S:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]], i32 noundef [[D:%.*]], i32 noundef [[E:%.*]], i32 noundef [[F:%.*]], i32 noundef [[G:%.*]], ptr noundef [[H:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_INT32_S:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]], i32 noundef [[D:%.*]], i32 noundef [[E:%.*]], i32 noundef [[F:%.*]], i32 noundef [[G:%.*]], ptr noundef [[H:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, i32 } @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs @@ -959,7 +959,7 @@ struct double_int32_s f_ret_double_int32_s_double_int32_s_just_sufficient_gprs( } // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_double_s_double_int32_s_just_sufficient_gprs -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]], i32 noundef [[D:%.*]], i32 noundef [[E:%.*]], i32 noundef [[F:%.*]], i32 noundef [[G:%.*]], ptr noundef [[H:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_DOUBLE_S:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]], i32 noundef [[D:%.*]], i32 noundef [[E:%.*]], i32 noundef [[F:%.*]], i32 noundef [[G:%.*]], ptr noundef [[H:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_double_double_s_double_int32_s_just_sufficient_gprs @@ -972,7 +972,7 @@ struct double_double_s f_ret_double_double_s_double_int32_s_just_sufficient_gprs } // ILP32-ILP32F-LABEL: define dso_local void @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs -// ILP32-ILP32F-SAME: (ptr noalias sret({ double, double }) align 8 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]], i32 noundef [[D:%.*]], i32 noundef [[E:%.*]], i32 noundef [[F:%.*]], i32 noundef [[G:%.*]], ptr noundef [[H:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret({ double, double }) align 8 [[AGG_RESULT:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]], i32 noundef [[D:%.*]], i32 noundef [[E:%.*]], i32 noundef [[F:%.*]], i32 noundef [[G:%.*]], ptr noundef [[H:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, double } @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs @@ -1193,7 +1193,7 @@ struct float_int32_s f_ret_float_int32_s(void) { void f_float_int64_s_arg(struct float_int64_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_float_int64_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_FLOAT_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct float_int64_s f_ret_float_int64_s(void) { @@ -1469,7 +1469,7 @@ struct int_float_int_s { int a; float b; int c; }; void f_int_float_int_s_arg(struct int_float_int_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_int_float_int_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_INT_FLOAT_INT_S:%.*]]) align 4 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT_FLOAT_INT_S:%.*]]) align 4 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct int_float_int_s f_ret_int_float_int_s(void) { @@ -1485,7 +1485,7 @@ struct int64_float_s { int64_t a; float b; }; void f_int64_float_s_arg(struct int64_float_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_int64_float_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_INT64_FLOAT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT64_FLOAT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct int64_float_s f_ret_int64_float_s(void) { @@ -1627,7 +1627,7 @@ struct double_float16_s { double f; _Float16 g; }; void f_double_float16_s_arg(struct double_float16_s a) {} // ILP32-ILP32F-LABEL: define dso_local void @f_ret_double_float16_s -// ILP32-ILP32F-SAME: (ptr noalias sret([[STRUCT_DOUBLE_FLOAT16_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_DOUBLE_FLOAT16_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F: entry: // // ILP32D-LABEL: define dso_local { double, half } @f_ret_double_float16_s @@ -1729,7 +1729,7 @@ struct float16_int32_s f_ret_float16_int32_s(void) { void f_float16_int64_s_arg(struct float16_int64_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_float16_int64_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_FLOAT16_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16_INT64_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct float16_int64_s f_ret_float16_int64_s(void) { @@ -2005,7 +2005,7 @@ struct int_float16_int_s { int a; _Float16 b; int c; }; void f_int_float16_int_s_arg(struct int_float16_int_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_int_float16_int_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_INT_FLOAT16_INT_S:%.*]]) align 4 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT_FLOAT16_INT_S:%.*]]) align 4 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct int_float16_int_s f_ret_int_float16_int_s(void) { @@ -2021,7 +2021,7 @@ struct int64_float16_s { int64_t a; _Float16 b; }; void f_int64_float16_s_arg(struct int64_float16_s a) {} // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_ret_int64_float16_s -// ILP32-ILP32F-ILP32D-SAME: (ptr noalias sret([[STRUCT_INT64_FLOAT16_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// ILP32-ILP32F-ILP32D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT64_FLOAT16_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // ILP32-ILP32F-ILP32D: entry: // struct int64_float16_s f_ret_int64_float16_s(void) { diff --git a/clang/test/CodeGen/RISCV/riscv64-abi.c b/clang/test/CodeGen/RISCV/riscv64-abi.c index 8c857f86ddff..3e7654851da0 100644 --- a/clang/test/CodeGen/RISCV/riscv64-abi.c +++ b/clang/test/CodeGen/RISCV/riscv64-abi.c @@ -250,7 +250,7 @@ void f_agg_large(struct large x) { // The address where the struct should be written to will be the first // argument // LP64-LP64F-LP64D-LABEL: define dso_local void @f_agg_large_ret -// LP64-LP64F-LP64D-SAME: (ptr noalias sret([[STRUCT_LARGE:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef signext [[I:%.*]], i8 noundef signext [[J:%.*]]) #[[ATTR0]] { +// LP64-LP64F-LP64D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_LARGE:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef signext [[I:%.*]], i8 noundef signext [[J:%.*]]) #[[ATTR0]] { // LP64-LP64F-LP64D: entry: // struct large f_agg_large_ret(int32_t i, int8_t j) { @@ -268,7 +268,7 @@ void f_vec_large_v32i8(v32i8 x) { } // LP64-LP64F-LP64D-LABEL: define dso_local void @f_vec_large_v32i8_ret -// LP64-LP64F-LP64D-SAME: (ptr noalias sret(<32 x i8>) align 32 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// LP64-LP64F-LP64D-SAME: (ptr dead_on_unwind noalias writable sret(<32 x i8>) align 32 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // LP64-LP64F-LP64D: entry: // v32i8 f_vec_large_v32i8_ret(void) { @@ -310,7 +310,7 @@ int f_scalar_stack_3(int32_t a, __int128_t b, double c, long double d, v32i8 e, // to pass a pointer. // LP64-LP64F-LP64D-LABEL: define dso_local void @f_scalar_stack_4 -// LP64-LP64F-LP64D-SAME: (ptr noalias sret([[STRUCT_LARGE:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef signext [[A:%.*]], i128 noundef [[B:%.*]], fp128 noundef [[C:%.*]], ptr noundef [[TMP0:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { +// LP64-LP64F-LP64D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_LARGE:%.*]]) align 8 [[AGG_RESULT:%.*]], i32 noundef signext [[A:%.*]], i128 noundef [[B:%.*]], fp128 noundef [[C:%.*]], ptr noundef [[TMP0:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { // LP64-LP64F-LP64D: entry: // struct large f_scalar_stack_4(uint32_t a, __int128_t b, long double c, v32i8 d, @@ -319,7 +319,7 @@ struct large f_scalar_stack_4(uint32_t a, __int128_t b, long double c, v32i8 d, } // LP64-LP64F-LP64D-LABEL: define dso_local void @f_scalar_stack_5 -// LP64-LP64F-LP64D-SAME: (ptr noalias sret([[STRUCT_LARGE:%.*]]) align 8 [[AGG_RESULT:%.*]], double noundef [[A:%.*]], i128 noundef [[B:%.*]], fp128 noundef [[C:%.*]], ptr noundef [[TMP0:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { +// LP64-LP64F-LP64D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_LARGE:%.*]]) align 8 [[AGG_RESULT:%.*]], double noundef [[A:%.*]], i128 noundef [[B:%.*]], fp128 noundef [[C:%.*]], ptr noundef [[TMP0:%.*]], i8 noundef zeroext [[E:%.*]], i8 noundef signext [[F:%.*]], i8 noundef zeroext [[G:%.*]]) #[[ATTR0]] { // LP64-LP64F-LP64D: entry: // struct large f_scalar_stack_5(double a, __int128_t b, long double c, v32i8 d, @@ -1444,7 +1444,7 @@ struct int_double_int_s { int a; double b; int c; }; void f_int_double_int_s_arg(struct int_double_int_s a) {} // LP64-LP64F-LP64D-LABEL: define dso_local void @f_ret_int_double_int_s -// LP64-LP64F-LP64D-SAME: (ptr noalias sret([[STRUCT_INT_DOUBLE_INT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { +// LP64-LP64F-LP64D-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_INT_DOUBLE_INT_S:%.*]]) align 8 [[AGG_RESULT:%.*]]) #[[ATTR0]] { // LP64-LP64F-LP64D: entry: // struct int_double_int_s f_ret_int_double_int_s(void) { diff --git a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c index e38e6572bd58..4f6dcbc2c01e 100644 --- a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c +++ b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c @@ -20,10 +20,7 @@ __int128 Des; // CHECK-LABEL: @f1( // CHECK-NEXT: entry: -// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 8 -// CHECK-NEXT: call void @__atomic_load(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull [[ATOMIC_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 8, !tbaa [[TBAA2:![0-9]+]] -// CHECK-NEXT: store i128 [[TMP0]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: tail call void @__atomic_load(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull [[AGG_RESULT:%.*]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f1() { @@ -33,7 +30,7 @@ __int128 f1() { // CHECK-LABEL: @f2( // CHECK-NEXT: entry: // CHECK-NEXT: tail call void @__atomic_load(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull @Ret, i32 noundef signext 5) -// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Ret, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Ret, align 8, !tbaa [[TBAA2:![0-9]+]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // @@ -66,12 +63,9 @@ void f4() { // CHECK-LABEL: @f5( // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i128, align 8 -// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[DOTATOMICTMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_exchange(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull [[DOTATOMICTMP]], ptr noundef nonnull [[ATOMIC_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_exchange(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull [[DOTATOMICTMP]], ptr noundef nonnull [[AGG_RESULT:%.*]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f5() { @@ -119,7 +113,7 @@ _Bool f8() { // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_add_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: call void @__atomic_fetch_add_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP2:%.*]] = add i128 [[TMP1]], [[TMP0]] // CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] @@ -135,7 +129,7 @@ __int128 f9() { // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_sub_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: call void @__atomic_fetch_sub_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP2:%.*]] = sub i128 [[TMP1]], [[TMP0]] // CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] @@ -151,7 +145,7 @@ __int128 f10() { // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_and_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: call void @__atomic_fetch_and_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP2:%.*]] = and i128 [[TMP1]], [[TMP0]] // CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] @@ -167,7 +161,7 @@ __int128 f11() { // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_xor_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: call void @__atomic_fetch_xor_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP2:%.*]] = xor i128 [[TMP1]], [[TMP0]] // CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] @@ -183,7 +177,7 @@ __int128 f12() { // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_or_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: call void @__atomic_fetch_or_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP2:%.*]] = or i128 [[TMP1]], [[TMP0]] // CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] @@ -199,7 +193,7 @@ __int128 f13() { // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_nand_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: call void @__atomic_fetch_nand_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP2:%.*]] = and i128 [[TMP1]], [[TMP0]] // CHECK-NEXT: [[TMP3:%.*]] = xor i128 [[TMP2]], -1 @@ -212,13 +206,10 @@ __int128 f14() { // CHECK-LABEL: @f15( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_add_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_add_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[AGG_RESULT:%.*]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f15() { @@ -227,13 +218,10 @@ __int128 f15() { // CHECK-LABEL: @f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_sub_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_sub_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[AGG_RESULT:%.*]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f16() { @@ -242,13 +230,10 @@ __int128 f16() { // CHECK-LABEL: @f17( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_and_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_and_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[AGG_RESULT:%.*]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f17() { @@ -257,13 +242,10 @@ __int128 f17() { // CHECK-LABEL: @f18( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_xor_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_xor_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[AGG_RESULT:%.*]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f18() { @@ -272,13 +254,10 @@ __int128 f18() { // CHECK-LABEL: @f19( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_or_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_or_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[AGG_RESULT:%.*]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f19() { @@ -287,13 +266,10 @@ __int128 f19() { // CHECK-LABEL: @f20( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] // CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: call void @__atomic_fetch_nand_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) -// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] -// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_nand_16(ptr dead_on_unwind nonnull writable sret(i128) align 8 [[AGG_RESULT:%.*]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) // CHECK-NEXT: ret void // __int128 f20() { diff --git a/clang/test/CodeGen/SystemZ/systemz-abi-vector.c b/clang/test/CodeGen/SystemZ/systemz-abi-vector.c index f7606641a374..6a06d15f22aa 100644 --- a/clang/test/CodeGen/SystemZ/systemz-abi-vector.c +++ b/clang/test/CodeGen/SystemZ/systemz-abi-vector.c @@ -54,91 +54,91 @@ unsigned int align = __alignof__ (v16i8); // CHECK-VECTOR: @align ={{.*}} global i32 8 v1i8 pass_v1i8(v1i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1i8(ptr noalias sret(<1 x i8>) align 1 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1i8(ptr dead_on_unwind noalias writable sret(<1 x i8>) align 1 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x i8> @pass_v1i8(<1 x i8> %{{.*}}) v2i8 pass_v2i8(v2i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v2i8(ptr noalias sret(<2 x i8>) align 2 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v2i8(ptr dead_on_unwind noalias writable sret(<2 x i8>) align 2 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <2 x i8> @pass_v2i8(<2 x i8> %{{.*}}) v4i8 pass_v4i8(v4i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v4i8(ptr noalias sret(<4 x i8>) align 4 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v4i8(ptr dead_on_unwind noalias writable sret(<4 x i8>) align 4 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <4 x i8> @pass_v4i8(<4 x i8> %{{.*}}) v8i8 pass_v8i8(v8i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v8i8(ptr noalias sret(<8 x i8>) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v8i8(ptr dead_on_unwind noalias writable sret(<8 x i8>) align 8 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <8 x i8> @pass_v8i8(<8 x i8> %{{.*}}) v16i8 pass_v16i8(v16i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v16i8(ptr noalias sret(<16 x i8>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v16i8(ptr dead_on_unwind noalias writable sret(<16 x i8>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <16 x i8> @pass_v16i8(<16 x i8> %{{.*}}) v32i8 pass_v32i8(v32i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v32i8(ptr noalias sret(<32 x i8>) align 32 %{{.*}}, ptr %0) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_v32i8(ptr noalias sret(<32 x i8>) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v32i8(ptr dead_on_unwind noalias writable sret(<32 x i8>) align 32 %{{.*}}, ptr %0) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_v32i8(ptr dead_on_unwind noalias writable sret(<32 x i8>) align 8 %{{.*}}, ptr %0) v1i16 pass_v1i16(v1i16 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1i16(ptr noalias sret(<1 x i16>) align 2 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1i16(ptr dead_on_unwind noalias writable sret(<1 x i16>) align 2 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x i16> @pass_v1i16(<1 x i16> %{{.*}}) v2i16 pass_v2i16(v2i16 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v2i16(ptr noalias sret(<2 x i16>) align 4 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v2i16(ptr dead_on_unwind noalias writable sret(<2 x i16>) align 4 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <2 x i16> @pass_v2i16(<2 x i16> %{{.*}}) v4i16 pass_v4i16(v4i16 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v4i16(ptr noalias sret(<4 x i16>) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v4i16(ptr dead_on_unwind noalias writable sret(<4 x i16>) align 8 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <4 x i16> @pass_v4i16(<4 x i16> %{{.*}}) v8i16 pass_v8i16(v8i16 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v8i16(ptr noalias sret(<8 x i16>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v8i16(ptr dead_on_unwind noalias writable sret(<8 x i16>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <8 x i16> @pass_v8i16(<8 x i16> %{{.*}}) v1i32 pass_v1i32(v1i32 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1i32(ptr noalias sret(<1 x i32>) align 4 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1i32(ptr dead_on_unwind noalias writable sret(<1 x i32>) align 4 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x i32> @pass_v1i32(<1 x i32> %{{.*}}) v2i32 pass_v2i32(v2i32 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v2i32(ptr noalias sret(<2 x i32>) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v2i32(ptr dead_on_unwind noalias writable sret(<2 x i32>) align 8 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <2 x i32> @pass_v2i32(<2 x i32> %{{.*}}) v4i32 pass_v4i32(v4i32 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v4i32(ptr noalias sret(<4 x i32>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v4i32(ptr dead_on_unwind noalias writable sret(<4 x i32>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <4 x i32> @pass_v4i32(<4 x i32> %{{.*}}) v1i64 pass_v1i64(v1i64 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1i64(ptr noalias sret(<1 x i64>) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1i64(ptr dead_on_unwind noalias writable sret(<1 x i64>) align 8 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x i64> @pass_v1i64(<1 x i64> %{{.*}}) v2i64 pass_v2i64(v2i64 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v2i64(ptr noalias sret(<2 x i64>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v2i64(ptr dead_on_unwind noalias writable sret(<2 x i64>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <2 x i64> @pass_v2i64(<2 x i64> %{{.*}}) v1i128 pass_v1i128(v1i128 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1i128(ptr noalias sret(<1 x i128>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1i128(ptr dead_on_unwind noalias writable sret(<1 x i128>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x i128> @pass_v1i128(<1 x i128> %{{.*}}) v1f32 pass_v1f32(v1f32 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1f32(ptr noalias sret(<1 x float>) align 4 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1f32(ptr dead_on_unwind noalias writable sret(<1 x float>) align 4 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x float> @pass_v1f32(<1 x float> %{{.*}}) v2f32 pass_v2f32(v2f32 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v2f32(ptr noalias sret(<2 x float>) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v2f32(ptr dead_on_unwind noalias writable sret(<2 x float>) align 8 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <2 x float> @pass_v2f32(<2 x float> %{{.*}}) v4f32 pass_v4f32(v4f32 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v4f32(ptr noalias sret(<4 x float>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v4f32(ptr dead_on_unwind noalias writable sret(<4 x float>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <4 x float> @pass_v4f32(<4 x float> %{{.*}}) v1f64 pass_v1f64(v1f64 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1f64(ptr noalias sret(<1 x double>) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1f64(ptr dead_on_unwind noalias writable sret(<1 x double>) align 8 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x double> @pass_v1f64(<1 x double> %{{.*}}) v2f64 pass_v2f64(v2f64 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v2f64(ptr noalias sret(<2 x double>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v2f64(ptr dead_on_unwind noalias writable sret(<2 x double>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <2 x double> @pass_v2f64(<2 x double> %{{.*}}) v1f128 pass_v1f128(v1f128 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_v1f128(ptr noalias sret(<1 x fp128>) align 16 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_v1f128(ptr dead_on_unwind noalias writable sret(<1 x fp128>) align 16 %{{.*}}, ptr %0) // CHECK-VECTOR-LABEL: define{{.*}} <1 x fp128> @pass_v1f128(<1 x fp128> %{{.*}}) @@ -146,62 +146,62 @@ v1f128 pass_v1f128(v1f128 arg) { return arg; } struct agg_v1i8 { v1i8 a; }; struct agg_v1i8 pass_agg_v1i8(struct agg_v1i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v1i8(ptr noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, i8 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v1i8(ptr noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, <1 x i8> %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v1i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v1i8) align 1 %{{.*}}, i8 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v1i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v1i8) align 1 %{{.*}}, <1 x i8> %{{.*}}) struct agg_v2i8 { v2i8 a; }; struct agg_v2i8 pass_agg_v2i8(struct agg_v2i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v2i8(ptr noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, i16 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v2i8(ptr noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, <2 x i8> %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v2i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v2i8) align 2 %{{.*}}, i16 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v2i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v2i8) align 2 %{{.*}}, <2 x i8> %{{.*}}) struct agg_v4i8 { v4i8 a; }; struct agg_v4i8 pass_agg_v4i8(struct agg_v4i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v4i8(ptr noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, i32 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v4i8(ptr noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, <4 x i8> %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v4i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v4i8) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v4i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v4i8) align 4 %{{.*}}, <4 x i8> %{{.*}}) struct agg_v8i8 { v8i8 a; }; struct agg_v8i8 pass_agg_v8i8(struct agg_v8i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v8i8(ptr noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, i64 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v8i8(ptr noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, <8 x i8> %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v8i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v8i8) align 8 %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v8i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v8i8) align 8 %{{.*}}, <8 x i8> %{{.*}}) struct agg_v16i8 { v16i8 a; }; struct agg_v16i8 pass_agg_v16i8(struct agg_v16i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v16i8(ptr noalias sret(%struct.agg_v16i8) align 16 %{{.*}}, ptr %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v16i8(ptr noalias sret(%struct.agg_v16i8) align 8 %{{.*}}, <16 x i8> %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v16i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v16i8) align 16 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v16i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v16i8) align 8 %{{.*}}, <16 x i8> %{{.*}}) struct agg_v32i8 { v32i8 a; }; struct agg_v32i8 pass_agg_v32i8(struct agg_v32i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v32i8(ptr noalias sret(%struct.agg_v32i8) align 32 %{{.*}}, ptr %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v32i8(ptr noalias sret(%struct.agg_v32i8) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v32i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v32i8) align 32 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v32i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v32i8) align 8 %{{.*}}, ptr %{{.*}}) // Verify that the following are *not* vector-like aggregate types struct agg_novector1 { v4i8 a; v4i8 b; }; struct agg_novector1 pass_agg_novector1(struct agg_novector1 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_novector1(ptr noalias sret(%struct.agg_novector1) align 4 %{{.*}}, i64 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector1(ptr noalias sret(%struct.agg_novector1) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_novector1(ptr dead_on_unwind noalias writable sret(%struct.agg_novector1) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector1(ptr dead_on_unwind noalias writable sret(%struct.agg_novector1) align 4 %{{.*}}, i64 %{{.*}}) struct agg_novector2 { v4i8 a; float b; }; struct agg_novector2 pass_agg_novector2(struct agg_novector2 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_novector2(ptr noalias sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector2(ptr noalias sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_novector2(ptr dead_on_unwind noalias writable sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector2(ptr dead_on_unwind noalias writable sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}}) struct agg_novector3 { v4i8 a; int : 0; }; struct agg_novector3 pass_agg_novector3(struct agg_novector3 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_novector3(ptr noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector3(ptr noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_novector3(ptr dead_on_unwind noalias writable sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector3(ptr dead_on_unwind noalias writable sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) struct agg_novector4 { v4i8 a __attribute__((aligned (8))); }; struct agg_novector4 pass_agg_novector4(struct agg_novector4 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_novector4(ptr noalias sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector4(ptr noalias sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_novector4(ptr dead_on_unwind noalias writable sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector4(ptr dead_on_unwind noalias writable sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}}) // Accessing variable argument lists v1i8 va_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, v1i8); } -// CHECK-LABEL: define{{.*}} void @va_v1i8(ptr noalias sret(<1 x i8>) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_v1i8(ptr dead_on_unwind noalias writable sret(<1 x i8>) align 1 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -230,7 +230,7 @@ v1i8 va_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, v1i8); } // CHECK-VECTOR: ret <1 x i8> [[RET]] v2i8 va_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, v2i8); } -// CHECK-LABEL: define{{.*}} void @va_v2i8(ptr noalias sret(<2 x i8>) align 2 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_v2i8(ptr dead_on_unwind noalias writable sret(<2 x i8>) align 2 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -259,7 +259,7 @@ v2i8 va_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, v2i8); } // CHECK-VECTOR: ret <2 x i8> [[RET]] v4i8 va_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, v4i8); } -// CHECK-LABEL: define{{.*}} void @va_v4i8(ptr noalias sret(<4 x i8>) align 4 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_v4i8(ptr dead_on_unwind noalias writable sret(<4 x i8>) align 4 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -288,7 +288,7 @@ v4i8 va_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, v4i8); } // CHECK-VECTOR: ret <4 x i8> [[RET]] v8i8 va_v8i8(__builtin_va_list l) { return __builtin_va_arg(l, v8i8); } -// CHECK-LABEL: define{{.*}} void @va_v8i8(ptr noalias sret(<8 x i8>) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_v8i8(ptr dead_on_unwind noalias writable sret(<8 x i8>) align 8 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -317,7 +317,7 @@ v8i8 va_v8i8(__builtin_va_list l) { return __builtin_va_arg(l, v8i8); } // CHECK-VECTOR: ret <8 x i8> [[RET]] v16i8 va_v16i8(__builtin_va_list l) { return __builtin_va_arg(l, v16i8); } -// CHECK-LABEL: define{{.*}} void @va_v16i8(ptr noalias sret(<16 x i8>) align 16 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_v16i8(ptr dead_on_unwind noalias writable sret(<16 x i8>) align 16 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -346,7 +346,7 @@ v16i8 va_v16i8(__builtin_va_list l) { return __builtin_va_arg(l, v16i8); } // CHECK-VECTOR: ret <16 x i8> [[RET]] v32i8 va_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, v32i8); } -// CHECK-LABEL: define{{.*}} void @va_v32i8(ptr noalias sret(<32 x i8>) align 32 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_v32i8(ptr dead_on_unwind noalias writable sret(<32 x i8>) align 32 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -366,7 +366,7 @@ v32i8 va_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, v32i8); } // CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi ptr [ [[RAW_REG_ADDR]], %{{.*}} ], [ [[RAW_MEM_ADDR]], %{{.*}} ] // CHECK: [[INDIRECT_ARG:%[^ ]+]] = load ptr, ptr [[VA_ARG_ADDR]] // CHECK: ret void -// CHECK-VECTOR-LABEL: define{{.*}} void @va_v32i8(ptr noalias sret(<32 x i8>) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @va_v32i8(ptr dead_on_unwind noalias writable sret(<32 x i8>) align 8 %{{.*}}, ptr %{{.*}}) // CHECK-VECTOR: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK-VECTOR: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK-VECTOR: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -388,7 +388,7 @@ v32i8 va_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, v32i8); } // CHECK-VECTOR: ret void struct agg_v1i8 va_agg_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v1i8); } -// CHECK-LABEL: define{{.*}} void @va_agg_v1i8(ptr noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_agg_v1i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v1i8) align 1 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -407,7 +407,7 @@ struct agg_v1i8 va_agg_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK: store ptr [[OVERFLOW_ARG_AREA2]], ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi ptr [ [[RAW_REG_ADDR]], %{{.*}} ], [ [[RAW_MEM_ADDR]], %{{.*}} ] // CHECK: ret void -// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v1i8(ptr noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v1i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v1i8) align 1 %{{.*}}, ptr %{{.*}}) // CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 2 // CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load ptr, ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 8 @@ -415,7 +415,7 @@ struct agg_v1i8 va_agg_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK-VECTOR: ret void struct agg_v2i8 va_agg_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v2i8); } -// CHECK-LABEL: define{{.*}} void @va_agg_v2i8(ptr noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_agg_v2i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v2i8) align 2 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -434,7 +434,7 @@ struct agg_v2i8 va_agg_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK: store ptr [[OVERFLOW_ARG_AREA2]], ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi ptr [ [[RAW_REG_ADDR]], %{{.*}} ], [ [[RAW_MEM_ADDR]], %{{.*}} ] // CHECK: ret void -// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v2i8(ptr noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v2i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v2i8) align 2 %{{.*}}, ptr %{{.*}}) // CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 2 // CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load ptr, ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 8 @@ -442,7 +442,7 @@ struct agg_v2i8 va_agg_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK-VECTOR: ret void struct agg_v4i8 va_agg_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v4i8); } -// CHECK-LABEL: define{{.*}} void @va_agg_v4i8(ptr noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_agg_v4i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v4i8) align 4 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -461,7 +461,7 @@ struct agg_v4i8 va_agg_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK: store ptr [[OVERFLOW_ARG_AREA2]], ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi ptr [ [[RAW_REG_ADDR]], %{{.*}} ], [ [[RAW_MEM_ADDR]], %{{.*}} ] // CHECK: ret void -// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v4i8(ptr noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v4i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v4i8) align 4 %{{.*}}, ptr %{{.*}}) // CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 2 // CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load ptr, ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 8 @@ -469,7 +469,7 @@ struct agg_v4i8 va_agg_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK-VECTOR: ret void struct agg_v8i8 va_agg_v8i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v8i8); } -// CHECK-LABEL: define{{.*}} void @va_agg_v8i8(ptr noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_agg_v8i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v8i8) align 8 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -488,7 +488,7 @@ struct agg_v8i8 va_agg_v8i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK: store ptr [[OVERFLOW_ARG_AREA2]], ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi ptr [ [[RAW_REG_ADDR]], %{{.*}} ], [ [[RAW_MEM_ADDR]], %{{.*}} ] // CHECK: ret void -// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v8i8(ptr noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v8i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v8i8) align 8 %{{.*}}, ptr %{{.*}}) // CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 2 // CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load ptr, ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 8 @@ -496,7 +496,7 @@ struct agg_v8i8 va_agg_v8i8(__builtin_va_list l) { return __builtin_va_arg(l, st // CHECK-VECTOR: ret void struct agg_v16i8 va_agg_v16i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v16i8); } -// CHECK-LABEL: define{{.*}} void @va_agg_v16i8(ptr noalias sret(%struct.agg_v16i8) align 16 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_agg_v16i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v16i8) align 16 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -516,7 +516,7 @@ struct agg_v16i8 va_agg_v16i8(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi ptr [ [[RAW_REG_ADDR]], %{{.*}} ], [ [[RAW_MEM_ADDR]], %{{.*}} ] // CHECK: [[INDIRECT_ARG:%[^ ]+]] = load ptr, ptr [[VA_ARG_ADDR]] // CHECK: ret void -// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v16i8(ptr noalias sret(%struct.agg_v16i8) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v16i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v16i8) align 8 %{{.*}}, ptr %{{.*}}) // CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 2 // CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load ptr, ptr [[OVERFLOW_ARG_AREA_PTR]] // CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 16 @@ -524,7 +524,7 @@ struct agg_v16i8 va_agg_v16i8(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK-VECTOR: ret void struct agg_v32i8 va_agg_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v32i8); } -// CHECK-LABEL: define{{.*}} void @va_agg_v32i8(ptr noalias sret(%struct.agg_v32i8) align 32 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_agg_v32i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v32i8) align 32 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -544,7 +544,7 @@ struct agg_v32i8 va_agg_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi ptr [ [[RAW_REG_ADDR]], %{{.*}} ], [ [[RAW_MEM_ADDR]], %{{.*}} ] // CHECK: [[INDIRECT_ARG:%[^ ]+]] = load ptr, ptr [[VA_ARG_ADDR]] // CHECK: ret void -// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v32i8(ptr noalias sret(%struct.agg_v32i8) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @va_agg_v32i8(ptr dead_on_unwind noalias writable sret(%struct.agg_v32i8) align 8 %{{.*}}, ptr %{{.*}}) // CHECK-VECTOR: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK-VECTOR: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK-VECTOR: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 diff --git a/clang/test/CodeGen/SystemZ/systemz-abi.c b/clang/test/CodeGen/SystemZ/systemz-abi.c index 7b2c04ece185..65a2bc9bbb68 100644 --- a/clang/test/CodeGen/SystemZ/systemz-abi.c +++ b/clang/test/CodeGen/SystemZ/systemz-abi.c @@ -43,7 +43,7 @@ long long pass_longlong(long long arg) { return arg; } // CHECK-LABEL: define{{.*}} i64 @pass_longlong(i64 %{{.*}}) __int128 pass_int128(__int128 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_int128(ptr noalias sret(i128) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_int128(ptr dead_on_unwind noalias writable sret(i128) align 8 %{{.*}}, ptr %0) float pass_float(float arg) { return arg; } // CHECK-LABEL: define{{.*}} float @pass_float(float %{{.*}}) @@ -52,125 +52,125 @@ double pass_double(double arg) { return arg; } // CHECK-LABEL: define{{.*}} double @pass_double(double %{{.*}}) long double pass_longdouble(long double arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_longdouble(ptr noalias sret(fp128) align 8 %{{.*}}, ptr %0) +// CHECK-LABEL: define{{.*}} void @pass_longdouble(ptr dead_on_unwind noalias writable sret(fp128) align 8 %{{.*}}, ptr %0) // Complex types _Complex char pass_complex_char(_Complex char arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_char(ptr noalias sret({ i8, i8 }) align 1 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_char(ptr dead_on_unwind noalias writable sret({ i8, i8 }) align 1 %{{.*}}, ptr %{{.*}}arg) _Complex short pass_complex_short(_Complex short arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_short(ptr noalias sret({ i16, i16 }) align 2 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_short(ptr dead_on_unwind noalias writable sret({ i16, i16 }) align 2 %{{.*}}, ptr %{{.*}}arg) _Complex int pass_complex_int(_Complex int arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_int(ptr noalias sret({ i32, i32 }) align 4 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_int(ptr dead_on_unwind noalias writable sret({ i32, i32 }) align 4 %{{.*}}, ptr %{{.*}}arg) _Complex long pass_complex_long(_Complex long arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_long(ptr noalias sret({ i64, i64 }) align 8 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_long(ptr dead_on_unwind noalias writable sret({ i64, i64 }) align 8 %{{.*}}, ptr %{{.*}}arg) _Complex long long pass_complex_longlong(_Complex long long arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_longlong(ptr noalias sret({ i64, i64 }) align 8 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_longlong(ptr dead_on_unwind noalias writable sret({ i64, i64 }) align 8 %{{.*}}, ptr %{{.*}}arg) _Complex float pass_complex_float(_Complex float arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_float(ptr noalias sret({ float, float }) align 4 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_float(ptr dead_on_unwind noalias writable sret({ float, float }) align 4 %{{.*}}, ptr %{{.*}}arg) _Complex double pass_complex_double(_Complex double arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_double(ptr noalias sret({ double, double }) align 8 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_double(ptr dead_on_unwind noalias writable sret({ double, double }) align 8 %{{.*}}, ptr %{{.*}}arg) _Complex long double pass_complex_longdouble(_Complex long double arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_complex_longdouble(ptr noalias sret({ fp128, fp128 }) align 8 %{{.*}}, ptr %{{.*}}arg) +// CHECK-LABEL: define{{.*}} void @pass_complex_longdouble(ptr dead_on_unwind noalias writable sret({ fp128, fp128 }) align 8 %{{.*}}, ptr %{{.*}}arg) // Aggregate types struct agg_1byte { char a[1]; }; struct agg_1byte pass_agg_1byte(struct agg_1byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_1byte(ptr noalias sret(%struct.agg_1byte) align 1 %{{.*}}, i8 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_1byte(ptr dead_on_unwind noalias writable sret(%struct.agg_1byte) align 1 %{{.*}}, i8 %{{.*}}) struct agg_2byte { char a[2]; }; struct agg_2byte pass_agg_2byte(struct agg_2byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_2byte(ptr noalias sret(%struct.agg_2byte) align 1 %{{.*}}, i16 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_2byte(ptr dead_on_unwind noalias writable sret(%struct.agg_2byte) align 1 %{{.*}}, i16 %{{.*}}) struct agg_3byte { char a[3]; }; struct agg_3byte pass_agg_3byte(struct agg_3byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_3byte(ptr noalias sret(%struct.agg_3byte) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_3byte(ptr dead_on_unwind noalias writable sret(%struct.agg_3byte) align 1 %{{.*}}, ptr %{{.*}}) struct agg_4byte { char a[4]; }; struct agg_4byte pass_agg_4byte(struct agg_4byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_4byte(ptr noalias sret(%struct.agg_4byte) align 1 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_4byte(ptr dead_on_unwind noalias writable sret(%struct.agg_4byte) align 1 %{{.*}}, i32 %{{.*}}) struct agg_5byte { char a[5]; }; struct agg_5byte pass_agg_5byte(struct agg_5byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_5byte(ptr noalias sret(%struct.agg_5byte) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_5byte(ptr dead_on_unwind noalias writable sret(%struct.agg_5byte) align 1 %{{.*}}, ptr %{{.*}}) struct agg_6byte { char a[6]; }; struct agg_6byte pass_agg_6byte(struct agg_6byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_6byte(ptr noalias sret(%struct.agg_6byte) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_6byte(ptr dead_on_unwind noalias writable sret(%struct.agg_6byte) align 1 %{{.*}}, ptr %{{.*}}) struct agg_7byte { char a[7]; }; struct agg_7byte pass_agg_7byte(struct agg_7byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_7byte(ptr noalias sret(%struct.agg_7byte) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_7byte(ptr dead_on_unwind noalias writable sret(%struct.agg_7byte) align 1 %{{.*}}, ptr %{{.*}}) struct agg_8byte { char a[8]; }; struct agg_8byte pass_agg_8byte(struct agg_8byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_8byte(ptr noalias sret(%struct.agg_8byte) align 1 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_8byte(ptr dead_on_unwind noalias writable sret(%struct.agg_8byte) align 1 %{{.*}}, i64 %{{.*}}) struct agg_16byte { char a[16]; }; struct agg_16byte pass_agg_16byte(struct agg_16byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_16byte(ptr noalias sret(%struct.agg_16byte) align 1 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_16byte(ptr dead_on_unwind noalias writable sret(%struct.agg_16byte) align 1 %{{.*}}, ptr %{{.*}}) // Float-like aggregate types struct agg_float { float a; }; struct agg_float pass_agg_float(struct agg_float arg) { return arg; } -// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_float(ptr noalias sret(%struct.agg_float) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float(ptr noalias sret(%struct.agg_float) align 4 %{{.*}}, i32 %{{.*}}) +// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_float(ptr dead_on_unwind noalias writable sret(%struct.agg_float) align 4 %{{.*}}, float %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float(ptr dead_on_unwind noalias writable sret(%struct.agg_float) align 4 %{{.*}}, i32 %{{.*}}) struct agg_double { double a; }; struct agg_double pass_agg_double(struct agg_double arg) { return arg; } -// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_double(ptr noalias sret(%struct.agg_double) align 8 %{{.*}}, double %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_double(ptr noalias sret(%struct.agg_double) align 8 %{{.*}}, i64 %{{.*}}) +// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_double(ptr dead_on_unwind noalias writable sret(%struct.agg_double) align 8 %{{.*}}, double %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_double(ptr dead_on_unwind noalias writable sret(%struct.agg_double) align 8 %{{.*}}, i64 %{{.*}}) struct agg_longdouble { long double a; }; struct agg_longdouble pass_agg_longdouble(struct agg_longdouble arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_longdouble(ptr noalias sret(%struct.agg_longdouble) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_longdouble(ptr dead_on_unwind noalias writable sret(%struct.agg_longdouble) align 8 %{{.*}}, ptr %{{.*}}) struct agg_float_a8 { float a __attribute__((aligned (8))); }; struct agg_float_a8 pass_agg_float_a8(struct agg_float_a8 arg) { return arg; } -// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_float_a8(ptr noalias sret(%struct.agg_float_a8) align 8 %{{.*}}, double %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float_a8(ptr noalias sret(%struct.agg_float_a8) align 8 %{{.*}}, i64 %{{.*}}) +// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_float_a8(ptr dead_on_unwind noalias writable sret(%struct.agg_float_a8) align 8 %{{.*}}, double %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float_a8(ptr dead_on_unwind noalias writable sret(%struct.agg_float_a8) align 8 %{{.*}}, i64 %{{.*}}) struct agg_float_a16 { float a __attribute__((aligned (16))); }; struct agg_float_a16 pass_agg_float_a16(struct agg_float_a16 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_float_a16(ptr noalias sret(%struct.agg_float_a16) align 16 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_float_a16(ptr dead_on_unwind noalias writable sret(%struct.agg_float_a16) align 16 %{{.*}}, ptr %{{.*}}) // Verify that the following are *not* float-like aggregate types struct agg_nofloat1 { float a; float b; }; struct agg_nofloat1 pass_agg_nofloat1(struct agg_nofloat1 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat1(ptr noalias sret(%struct.agg_nofloat1) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat1(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat1) align 4 %{{.*}}, i64 %{{.*}}) struct agg_nofloat2 { float a; int b; }; struct agg_nofloat2 pass_agg_nofloat2(struct agg_nofloat2 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat2(ptr noalias sret(%struct.agg_nofloat2) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat2(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat2) align 4 %{{.*}}, i64 %{{.*}}) struct agg_nofloat3 { float a; int : 0; }; struct agg_nofloat3 pass_agg_nofloat3(struct agg_nofloat3 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat3(ptr noalias sret(%struct.agg_nofloat3) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat3(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat3) align 4 %{{.*}}, i32 %{{.*}}) // Union types likewise are *not* float-like aggregate types union union_float { float a; }; union union_float pass_union_float(union union_float arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_union_float(ptr noalias sret(%union.union_float) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_union_float(ptr dead_on_unwind noalias writable sret(%union.union_float) align 4 %{{.*}}, i32 %{{.*}}) union union_double { double a; }; union union_double pass_union_double(union union_double arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_union_double(ptr noalias sret(%union.union_double) align 8 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_union_double(ptr dead_on_unwind noalias writable sret(%union.union_double) align 8 %{{.*}}, i64 %{{.*}}) // Accessing variable argument lists @@ -267,7 +267,7 @@ double va_double(__builtin_va_list l) { return __builtin_va_arg(l, double); } // CHECK: ret double [[RET]] long double va_longdouble(__builtin_va_list l) { return __builtin_va_arg(l, long double); } -// CHECK-LABEL: define{{.*}} void @va_longdouble(ptr noalias sret(fp128) align 8 %{{.*}}, ptr %{{.*}}) +// CHECK-LABEL: define{{.*}} void @va_longdouble(ptr dead_on_unwind noalias writable sret(fp128) align 8 %{{.*}}, ptr %{{.*}}) // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -291,7 +291,7 @@ long double va_longdouble(__builtin_va_list l) { return __builtin_va_arg(l, long // CHECK: ret void _Complex char va_complex_char(__builtin_va_list l) { return __builtin_va_arg(l, _Complex char); } -// CHECK-LABEL: define{{.*}} void @va_complex_char(ptr noalias sret({ i8, i8 }) align 1 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_complex_char(ptr dead_on_unwind noalias writable sret({ i8, i8 }) align 1 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -313,7 +313,7 @@ _Complex char va_complex_char(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: ret void struct agg_1byte va_agg_1byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_1byte); } -// CHECK-LABEL: define{{.*}} void @va_agg_1byte(ptr noalias sret(%struct.agg_1byte) align 1 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_1byte(ptr dead_on_unwind noalias writable sret(%struct.agg_1byte) align 1 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -334,7 +334,7 @@ struct agg_1byte va_agg_1byte(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: ret void struct agg_2byte va_agg_2byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_2byte); } -// CHECK-LABEL: define{{.*}} void @va_agg_2byte(ptr noalias sret(%struct.agg_2byte) align 1 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_2byte(ptr dead_on_unwind noalias writable sret(%struct.agg_2byte) align 1 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -355,7 +355,7 @@ struct agg_2byte va_agg_2byte(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: ret void struct agg_3byte va_agg_3byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_3byte); } -// CHECK-LABEL: define{{.*}} void @va_agg_3byte(ptr noalias sret(%struct.agg_3byte) align 1 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_3byte(ptr dead_on_unwind noalias writable sret(%struct.agg_3byte) align 1 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -377,7 +377,7 @@ struct agg_3byte va_agg_3byte(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: ret void struct agg_4byte va_agg_4byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_4byte); } -// CHECK-LABEL: define{{.*}} void @va_agg_4byte(ptr noalias sret(%struct.agg_4byte) align 1 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_4byte(ptr dead_on_unwind noalias writable sret(%struct.agg_4byte) align 1 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -398,7 +398,7 @@ struct agg_4byte va_agg_4byte(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: ret void struct agg_8byte va_agg_8byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_8byte); } -// CHECK-LABEL: define{{.*}} void @va_agg_8byte(ptr noalias sret(%struct.agg_8byte) align 1 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_8byte(ptr dead_on_unwind noalias writable sret(%struct.agg_8byte) align 1 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -419,7 +419,7 @@ struct agg_8byte va_agg_8byte(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: ret void struct agg_float va_agg_float(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_float); } -// CHECK-LABEL: define{{.*}} void @va_agg_float(ptr noalias sret(%struct.agg_float) align 4 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_float(ptr dead_on_unwind noalias writable sret(%struct.agg_float) align 4 %{{.*}}, ptr %{{.*}} // HARD-FLOAT: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 1 // SOFT-FLOAT: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] @@ -443,7 +443,7 @@ struct agg_float va_agg_float(__builtin_va_list l) { return __builtin_va_arg(l, // CHECK: ret void struct agg_double va_agg_double(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_double); } -// CHECK-LABEL: define{{.*}} void @va_agg_double(ptr noalias sret(%struct.agg_double) align 8 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_double(ptr dead_on_unwind noalias writable sret(%struct.agg_double) align 8 %{{.*}}, ptr %{{.*}} // HARD-FLOAT: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 1 // SOFT-FLOAT: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] @@ -467,7 +467,7 @@ struct agg_double va_agg_double(__builtin_va_list l) { return __builtin_va_arg(l // CHECK: ret void struct agg_longdouble va_agg_longdouble(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_longdouble); } -// CHECK-LABEL: define{{.*}} void @va_agg_longdouble(ptr noalias sret(%struct.agg_longdouble) align 8 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_longdouble(ptr dead_on_unwind noalias writable sret(%struct.agg_longdouble) align 8 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -489,7 +489,7 @@ struct agg_longdouble va_agg_longdouble(__builtin_va_list l) { return __builtin_ // CHECK: ret void struct agg_float_a8 va_agg_float_a8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_float_a8); } -// CHECK-LABEL: define{{.*}} void @va_agg_float_a8(ptr noalias sret(%struct.agg_float_a8) align 8 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_float_a8(ptr dead_on_unwind noalias writable sret(%struct.agg_float_a8) align 8 %{{.*}}, ptr %{{.*}} // HARD-FLOAT: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 1 // SOFT-FLOAT: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] @@ -513,7 +513,7 @@ struct agg_float_a8 va_agg_float_a8(__builtin_va_list l) { return __builtin_va_a // CHECK: ret void struct agg_float_a16 va_agg_float_a16(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_float_a16); } -// CHECK-LABEL: define{{.*}} void @va_agg_float_a16(ptr noalias sret(%struct.agg_float_a16) align 16 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_float_a16(ptr dead_on_unwind noalias writable sret(%struct.agg_float_a16) align 16 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -535,7 +535,7 @@ struct agg_float_a16 va_agg_float_a16(__builtin_va_list l) { return __builtin_va // CHECK: ret void struct agg_nofloat1 va_agg_nofloat1(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_nofloat1); } -// CHECK-LABEL: define{{.*}} void @va_agg_nofloat1(ptr noalias sret(%struct.agg_nofloat1) align 4 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_nofloat1(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat1) align 4 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -556,7 +556,7 @@ struct agg_nofloat1 va_agg_nofloat1(__builtin_va_list l) { return __builtin_va_a // CHECK: ret void struct agg_nofloat2 va_agg_nofloat2(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_nofloat2); } -// CHECK-LABEL: define{{.*}} void @va_agg_nofloat2(ptr noalias sret(%struct.agg_nofloat2) align 4 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_nofloat2(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat2) align 4 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 @@ -577,7 +577,7 @@ struct agg_nofloat2 va_agg_nofloat2(__builtin_va_list l) { return __builtin_va_a // CHECK: ret void struct agg_nofloat3 va_agg_nofloat3(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_nofloat3); } -// CHECK-LABEL: define{{.*}} void @va_agg_nofloat3(ptr noalias sret(%struct.agg_nofloat3) align 4 %{{.*}}, ptr %{{.*}} +// CHECK-LABEL: define{{.*}} void @va_agg_nofloat3(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat3) align 4 %{{.*}}, ptr %{{.*}} // CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, ptr [[REG_COUNT_PTR]] // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 diff --git a/clang/test/CodeGen/SystemZ/systemz-abi.cpp b/clang/test/CodeGen/SystemZ/systemz-abi.cpp index 08bf08c3803f..06be85421ba1 100644 --- a/clang/test/CodeGen/SystemZ/systemz-abi.cpp +++ b/clang/test/CodeGen/SystemZ/systemz-abi.cpp @@ -6,20 +6,20 @@ class agg_float_class { float a; }; class agg_float_class pass_agg_float_class(class agg_float_class arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(ptr noalias sret(%class.agg_float_class) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(ptr noalias sret(%class.agg_float_class) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(ptr dead_on_unwind noalias writable sret(%class.agg_float_class) align 4 %{{.*}}, float %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(ptr dead_on_unwind noalias writable sret(%class.agg_float_class) align 4 %{{.*}}, i32 %{{.*}}) class agg_double_class { double a; }; class agg_double_class pass_agg_double_class(class agg_double_class arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(ptr noalias sret(%class.agg_double_class) align 8 %{{.*}}, double %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(ptr noalias sret(%class.agg_double_class) align 8 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(ptr dead_on_unwind noalias writable sret(%class.agg_double_class) align 8 %{{.*}}, double %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(ptr dead_on_unwind noalias writable sret(%class.agg_double_class) align 8 %{{.*}}, i64 %{{.*}}) // This structure is passed in a GPR in C++ (and C, checked in systemz-abi.c). struct agg_float_cpp { float a; int : 0; }; struct agg_float_cpp pass_agg_float_cpp(struct agg_float_cpp arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(ptr noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(ptr noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(ptr dead_on_unwind noalias writable sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(ptr dead_on_unwind noalias writable sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 %{{.*}}) // A field member of empty class type in C++ makes the record nonhomogeneous, @@ -27,31 +27,31 @@ struct agg_float_cpp pass_agg_float_cpp(struct agg_float_cpp arg) { return arg; struct empty { }; struct agg_nofloat_empty { float a; empty dummy; }; struct agg_nofloat_empty pass_agg_nofloat_empty(struct agg_nofloat_empty arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(ptr noalias sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(ptr noalias sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) struct agg_float_empty { float a; [[no_unique_address]] empty dummy; }; struct agg_float_empty pass_agg_float_empty(struct agg_float_empty arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(ptr noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(ptr noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(ptr dead_on_unwind noalias writable sret(%struct.agg_float_empty) align 4 %{{.*}}, float %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(ptr dead_on_unwind noalias writable sret(%struct.agg_float_empty) align 4 %{{.*}}, i32 %{{.*}}) struct agg_nofloat_emptyarray { float a; [[no_unique_address]] empty dummy[3]; }; struct agg_nofloat_emptyarray pass_agg_nofloat_emptyarray(struct agg_nofloat_emptyarray arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(ptr noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(ptr noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) // And likewise for members of base classes. struct noemptybase { empty dummy; }; struct agg_nofloat_emptybase : noemptybase { float a; }; struct agg_nofloat_emptybase pass_agg_nofloat_emptybase(struct agg_nofloat_emptybase arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr noalias sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr noalias sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) struct emptybase { [[no_unique_address]] empty dummy; }; struct agg_float_emptybase : emptybase { float a; }; struct agg_float_emptybase pass_agg_float_emptybase(struct agg_float_emptybase arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr dead_on_unwind noalias writable sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(ptr dead_on_unwind noalias writable sret(%struct.agg_float_emptybase) align 4 %{{.*}}, i32 %{{.*}}) struct noemptybasearray { [[no_unique_address]] empty dummy[3]; }; struct agg_nofloat_emptybasearray : noemptybasearray { float a; }; struct agg_nofloat_emptybasearray pass_agg_nofloat_emptybasearray(struct agg_nofloat_emptybasearray arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(ptr noalias sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(ptr noalias sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(ptr dead_on_unwind noalias writable sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) diff --git a/clang/test/CodeGen/SystemZ/systemz-inline-asm.c b/clang/test/CodeGen/SystemZ/systemz-inline-asm.c index 0d614f8cbb90..e38d37cd345e 100644 --- a/clang/test/CodeGen/SystemZ/systemz-inline-asm.c +++ b/clang/test/CodeGen/SystemZ/systemz-inline-asm.c @@ -123,7 +123,7 @@ double test_f64(double f, double g) { long double test_f128(long double f, long double g) { asm("axbr %0, %2" : "=f" (f) : "0" (f), "f" (g)); return f; -// CHECK: define{{.*}} void @test_f128(ptr noalias nocapture writeonly sret(fp128) align 8 [[DEST:%.*]], ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1) +// CHECK: define{{.*}} void @test_f128(ptr dead_on_unwind noalias nocapture writable writeonly sret(fp128) align 8 [[DEST:%.*]], ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1) // CHECK: %f = load fp128, ptr %0 // CHECK: %g = load fp128, ptr %1 // CHECK: [[RESULT:%.*]] = tail call fp128 asm "axbr $0, $2", "=f,0,f"(fp128 %f, fp128 %g) diff --git a/clang/test/CodeGen/WebAssembly/wasm-arguments.c b/clang/test/CodeGen/WebAssembly/wasm-arguments.c index 1b54b6401db0..a0914fc76880 100644 --- a/clang/test/CodeGen/WebAssembly/wasm-arguments.c +++ b/clang/test/CodeGen/WebAssembly/wasm-arguments.c @@ -25,9 +25,9 @@ typedef struct { void struct_arg(s1 i) {} // Structs should be returned sret and not simplified by the frontend. -// WEBASSEMBLY32: define void @struct_ret(ptr noalias sret(%struct.s1) align 4 %agg.result) +// WEBASSEMBLY32: define void @struct_ret(ptr dead_on_unwind noalias writable sret(%struct.s1) align 4 %agg.result) // WEBASSEMBLY32: ret void -// WEBASSEMBLY64: define void @struct_ret(ptr noalias sret(%struct.s1) align 4 %agg.result) +// WEBASSEMBLY64: define void @struct_ret(ptr dead_on_unwind noalias writable sret(%struct.s1) align 4 %agg.result) // WEBASSEMBLY64: ret void // Except with the experimental multivalue ABI, which returns structs by value @@ -103,9 +103,9 @@ union simple_union { void union_arg(union simple_union s) {} // Unions should be returned sret and not simplified by the frontend. -// WEBASSEMBLY32: define void @union_ret(ptr noalias sret(%union.simple_union) align 4 %agg.result) +// WEBASSEMBLY32: define void @union_ret(ptr dead_on_unwind noalias writable sret(%union.simple_union) align 4 %agg.result) // WEBASSEMBLY32: ret void -// WEBASSEMBLY64: define void @union_ret(ptr noalias sret(%union.simple_union) align 4 %agg.result) +// WEBASSEMBLY64: define void @union_ret(ptr dead_on_unwind noalias writable sret(%union.simple_union) align 4 %agg.result) // WEBASSEMBLY64: ret void // The experimental multivalue ABI returns them by value, though. @@ -129,8 +129,8 @@ typedef struct { void bitfield_arg(bitfield1 bf1) {} // And returned via sret pointers. -// WEBASSEMBLY32: define void @bitfield_ret(ptr noalias sret(%struct.bitfield1) align 4 %agg.result) -// WEBASSEMBLY64: define void @bitfield_ret(ptr noalias sret(%struct.bitfield1) align 4 %agg.result) +// WEBASSEMBLY32: define void @bitfield_ret(ptr dead_on_unwind noalias writable sret(%struct.bitfield1) align 4 %agg.result) +// WEBASSEMBLY64: define void @bitfield_ret(ptr dead_on_unwind noalias writable sret(%struct.bitfield1) align 4 %agg.result) // Except, of course, in the experimental multivalue ABI // EXPERIMENTAL-MV: define %struct.bitfield1 @bitfield_ret() diff --git a/clang/test/CodeGen/WebAssembly/wasm-varargs.c b/clang/test/CodeGen/WebAssembly/wasm-varargs.c index da22ad6a1b2e..c475de19ae44 100644 --- a/clang/test/CodeGen/WebAssembly/wasm-varargs.c +++ b/clang/test/CodeGen/WebAssembly/wasm-varargs.c @@ -68,7 +68,7 @@ struct S { }; // CHECK-LABEL: define {{[^@]+}}@test_struct -// CHECK-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] { +// CHECK-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4 // CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4 @@ -96,7 +96,7 @@ struct S test_struct(char *fmt, ...) { struct Z {}; // CHECK-LABEL: define {{[^@]+}}@test_empty_struct -// CHECK-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] { +// CHECK-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4 // CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4 diff --git a/clang/test/CodeGen/X86/x86_32-arguments-darwin.c b/clang/test/CodeGen/X86/x86_32-arguments-darwin.c index 69d1156acf7e..8eeba631157d 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-darwin.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-darwin.c @@ -71,7 +71,7 @@ struct s10 { // Small vectors and 1 x {i64,double} are returned in registers // CHECK: i32 @f11() -// CHECK: void @f12(ptr noalias sret(<2 x i32>) align 8 %agg.result) +// CHECK: void @f12(ptr dead_on_unwind noalias writable sret(<2 x i32>) align 8 %agg.result) // CHECK: i64 @f13() // CHECK: i64 @f14() // CHECK: <2 x i64> @f15() @@ -93,11 +93,11 @@ T16 f16(void) { while (1) {} } // 128-bits). // CHECK: i32 @f17() -// CHECK: void @f18(ptr noalias sret(%struct.anon.{{[0-9]+}}) align 8 %agg.result) -// CHECK: void @f19(ptr noalias sret(%struct.anon.{{[0-9]+}}) align 8 %agg.result) -// CHECK: void @f20(ptr noalias sret(%struct.anon.{{[0-9]+}}) align 8 %agg.result) -// CHECK: void @f21(ptr noalias sret(%struct.anon.{{[0-9]+}}) align 16 %agg.result) -// CHECK: void @f22(ptr noalias sret(%struct.anon.{{[0-9]+}}) align 16 %agg.result) +// CHECK: void @f18(ptr dead_on_unwind noalias writable sret(%struct.anon.{{[0-9]+}}) align 8 %agg.result) +// CHECK: void @f19(ptr dead_on_unwind noalias writable sret(%struct.anon.{{[0-9]+}}) align 8 %agg.result) +// CHECK: void @f20(ptr dead_on_unwind noalias writable sret(%struct.anon.{{[0-9]+}}) align 8 %agg.result) +// CHECK: void @f21(ptr dead_on_unwind noalias writable sret(%struct.anon.{{[0-9]+}}) align 16 %agg.result) +// CHECK: void @f22(ptr dead_on_unwind noalias writable sret(%struct.anon.{{[0-9]+}}) align 16 %agg.result) struct { T11 a; } f17(void) { while (1) {} } struct { T12 a; } f18(void) { while (1) {} } struct { T13 a; } f19(void) { while (1) {} } @@ -116,11 +116,11 @@ struct { struct {} a; struct { float a[1]; } b; } f25(void) { while (1) {} } // Small structures are handled recursively // CHECK: i32 @f26() -// CHECK: void @f27(ptr noalias sret(%struct.s27) align 1 %agg.result) +// CHECK: void @f27(ptr dead_on_unwind noalias writable sret(%struct.s27) align 1 %agg.result) struct s26 { struct { char a, b; } a; struct { char a, b; } b; } f26(void) { while (1) {} } struct s27 { struct { char a, b, c; } a; struct { char a; } b; } f27(void) { while (1) {} } -// CHECK: void @f28(ptr noalias sret(%struct.s28) align 4 %agg.result) +// CHECK: void @f28(ptr dead_on_unwind noalias writable sret(%struct.s28) align 4 %agg.result) struct s28 { int a; int b[]; } f28(void) { while (1) {} } // CHECK-LABEL: define{{.*}} i16 @f29() @@ -150,7 +150,7 @@ struct s36 { struct { int : 0; } a[2][10]; char b; char c; } f36(void) { while ( // CHECK-LABEL: define{{.*}} float @f37() struct s37 { float c[1][1]; } f37(void) { while (1) {} } -// CHECK-LABEL: define{{.*}} void @f38(ptr noalias sret(%struct.s38) align 2 %agg.result) +// CHECK-LABEL: define{{.*}} void @f38(ptr dead_on_unwind noalias writable sret(%struct.s38) align 2 %agg.result) struct s38 { char a[3]; short b; } f38(void) { while (1) {} } // CHECK-LABEL: define{{.*}} void @f39(ptr noundef byval(%struct.s39) align 16 %x) diff --git a/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c b/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c index c2b8f23ba5f3..2700bda1e7ed 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c @@ -58,7 +58,7 @@ st4_t retSmallStruct(st4_t r) { return r; } // CHECK-LABEL: define{{.*}} i64 @retPaddedStruct(i32 %r.coerce0, i32 %r.coerce1) st5_t retPaddedStruct(st5_t r) { return r; } -// CHECK-LABEL: define{{.*}} void @retLargeStruct(ptr noalias sret(%struct.st12_t) align 4 %agg.result, i32 noundef %i1, ptr noundef byval(%struct.st12_t) align 4 %r) +// CHECK-LABEL: define{{.*}} void @retLargeStruct(ptr dead_on_unwind noalias writable sret(%struct.st12_t) align 4 %agg.result, i32 noundef %i1, ptr noundef byval(%struct.st12_t) align 4 %r) st12_t retLargeStruct(int i1, st12_t r) { return r; } // CHECK-LABEL: define{{.*}} i32 @varArgs(i32 noundef %i1, ...) diff --git a/clang/test/CodeGen/X86/x86_64-arguments-nacl.c b/clang/test/CodeGen/X86/x86_64-arguments-nacl.c index 3f91ed1b1c46..4d820aef8fd2 100644 --- a/clang/test/CodeGen/X86/x86_64-arguments-nacl.c +++ b/clang/test/CodeGen/X86/x86_64-arguments-nacl.c @@ -61,7 +61,7 @@ void f12_1(struct s12 a0) {} // Check that sret parameter is accounted for when checking available integer // registers. -// CHECK: define{{.*}} void @f13(ptr noalias sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, ptr noundef byval({{.*}}) align 8 %e, i32 noundef %f) +// CHECK: define{{.*}} void @f13(ptr dead_on_unwind noalias writable sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, ptr noundef byval({{.*}}) align 8 %e, i32 noundef %f) struct s13_0 { long long f0[3]; }; struct s13_1 { long long f0[2]; }; diff --git a/clang/test/CodeGen/X86/x86_64-arguments-win32.c b/clang/test/CodeGen/X86/x86_64-arguments-win32.c index 31aa0546a3c8..8768e73a854a 100644 --- a/clang/test/CodeGen/X86/x86_64-arguments-win32.c +++ b/clang/test/CodeGen/X86/x86_64-arguments-win32.c @@ -27,5 +27,5 @@ void f6(_Complex double a) {} // CHECK-LABEL: define dso_local i64 @f7() _Complex float f7(void) { return 1.0; } -// CHECK-LABEL: define dso_local void @f8(ptr noalias sret({ double, double }) align 8 %agg.result) +// CHECK-LABEL: define dso_local void @f8(ptr dead_on_unwind noalias writable sret({ double, double }) align 8 %agg.result) _Complex double f8(void) { return 1.0; } diff --git a/clang/test/CodeGen/X86/x86_64-arguments.c b/clang/test/CodeGen/X86/x86_64-arguments.c index b2c4283b5e6f..cf5636cfd518 100644 --- a/clang/test/CodeGen/X86/x86_64-arguments.c +++ b/clang/test/CodeGen/X86/x86_64-arguments.c @@ -47,7 +47,7 @@ void f7(e7 a0) { // Test merging/passing of upper eightbyte with X87 class. // -// CHECK-LABEL: define{{.*}} void @f8_1(ptr noalias sret(%union.u8) align 16 %agg.result) +// CHECK-LABEL: define{{.*}} void @f8_1(ptr dead_on_unwind noalias writable sret(%union.u8) align 16 %agg.result) // CHECK-LABEL: define{{.*}} void @f8_2(ptr noundef byval(%union.u8) align 16 %a0) union u8 { long double a; @@ -63,7 +63,7 @@ struct s9 { int a; int b; int : 0; } f9(void) { while (1) {} } struct s10 { int a; int b; int : 0; }; void f10(struct s10 a0) {} -// CHECK-LABEL: define{{.*}} void @f11(ptr noalias sret(%union.anon) align 16 %agg.result) +// CHECK-LABEL: define{{.*}} void @f11(ptr dead_on_unwind noalias writable sret(%union.anon) align 16 %agg.result) union { long double a; float b; } f11(void) { while (1) {} } // CHECK-LABEL: define{{.*}} i32 @f12_0() @@ -74,7 +74,7 @@ void f12_1(struct s12 a0) {} // Check that sret parameter is accounted for when checking available integer // registers. -// CHECK: define{{.*}} void @f13(ptr noalias sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, ptr noundef byval({{.*}}) align 8 %e, i32 noundef %f) +// CHECK: define{{.*}} void @f13(ptr dead_on_unwind noalias writable sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, ptr noundef byval({{.*}}) align 8 %e, i32 noundef %f) struct s13_0 { long long f0[3]; }; struct s13_1 { long long f0[2]; }; diff --git a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c index 9c96dfb9e33e..1e6a4500cc88 100644 --- a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c +++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c @@ -59,7 +59,7 @@ typedef int8_t vec_int8 __attribute__((vector_size(N / 8))); // CHECK128-NEXT: ret <16 x i8> [[CASTFIXEDSVE]] // CHECK-LABEL: define{{.*}} void @f2( -// CHECK-SAME: ptr noalias nocapture writeonly sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, ptr nocapture noundef readonly %0) +// CHECK-SAME: ptr dead_on_unwind noalias nocapture writable writeonly sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, ptr nocapture noundef readonly %0) // CHECK-NEXT: entry: // CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, ptr [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]] // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) diff --git a/clang/test/CodeGen/aarch64-varargs.c b/clang/test/CodeGen/aarch64-varargs.c index f2ce7d59a8cc..44b87029e7b3 100644 --- a/clang/test/CodeGen/aarch64-varargs.c +++ b/clang/test/CodeGen/aarch64-varargs.c @@ -601,7 +601,7 @@ typedef struct __attribute__((aligned(32))) { __int128 val; } overaligned_int128_struct; overaligned_int128_struct overaligned_int128_struct_test(void) { -// CHECK-LABEL: define{{.*}} void @overaligned_int128_struct_test(ptr noalias sret(%struct.overaligned_int128_struct) align 32 %agg.result) +// CHECK-LABEL: define{{.*}} void @overaligned_int128_struct_test(ptr dead_on_unwind noalias writable sret(%struct.overaligned_int128_struct) align 32 %agg.result) return va_arg(the_list, overaligned_int128_struct); // CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32, ptr getelementptr inbounds (%struct.__va_list, ptr @the_list, i32 0, i32 3) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[GR_OFFS]], 0 @@ -804,7 +804,7 @@ typedef struct { __int128 val __attribute__((aligned(32))); } overaligned_int128_struct_member; overaligned_int128_struct_member overaligned_int128_struct_member_test(void) { -// CHECK-LABEL: define{{.*}} void @overaligned_int128_struct_member_test(ptr noalias sret(%struct.overaligned_int128_struct_member) align 32 %agg.result) +// CHECK-LABEL: define{{.*}} void @overaligned_int128_struct_member_test(ptr dead_on_unwind noalias writable sret(%struct.overaligned_int128_struct_member) align 32 %agg.result) return va_arg(the_list, overaligned_int128_struct_member); // CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32, ptr getelementptr inbounds (%struct.__va_list, ptr @the_list, i32 0, i32 3) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[GR_OFFS]], 0 diff --git a/clang/test/CodeGen/aggregate-assign-call.c b/clang/test/CodeGen/aggregate-assign-call.c index b5c7f213dcbe..d6571269456a 100644 --- a/clang/test/CodeGen/aggregate-assign-call.c +++ b/clang/test/CodeGen/aggregate-assign-call.c @@ -63,11 +63,11 @@ struct S baz(int i, volatile int *j) { // // O1: call void @llvm.lifetime.end.p0({{[^,]*}}, ptr %[[TMP1_ALLOCA]]) // - // O1: call void @foo_int(ptr sret(%struct.S) align 4 %[[TMP1_ALLOCA]], + // O1: call void @foo_int(ptr dead_on_unwind writable sret(%struct.S) align 4 %[[TMP1_ALLOCA]], // O1: call void @llvm.memcpy // O1: call void @llvm.lifetime.end.p0({{[^,]*}}, ptr %[[TMP1_ALLOCA]]) // O1: call void @llvm.lifetime.start.p0({{[^,]*}}, ptr %[[TMP2_ALLOCA]]) - // O1: call void @foo_int(ptr sret(%struct.S) align 4 %[[TMP2_ALLOCA]], + // O1: call void @foo_int(ptr dead_on_unwind writable sret(%struct.S) align 4 %[[TMP2_ALLOCA]], // O1: call void @llvm.memcpy // O1: call void @llvm.lifetime.end.p0({{[^,]*}}, ptr %[[TMP2_ALLOCA]]) r = foo_int(({ diff --git a/clang/test/CodeGen/aligned-sret.c b/clang/test/CodeGen/aligned-sret.c index 4759d69219a6..4e1f86e7f07a 100644 --- a/clang/test/CodeGen/aligned-sret.c +++ b/clang/test/CodeGen/aligned-sret.c @@ -4,7 +4,7 @@ typedef __attribute__((__ext_vector_type__(4),__aligned__(16))) double simd_doub typedef struct { simd_double4 columns[4]; } simd_double4x4; typedef simd_double4x4 matrix_double4x4; -// CHECK: define{{.*}} void @ident(ptr noalias sret(%struct.simd_double4x4) align 16 %agg.result +// CHECK: define{{.*}} void @ident(ptr dead_on_unwind noalias writable sret(%struct.simd_double4x4) align 16 %agg.result matrix_double4x4 ident(matrix_double4x4 x) { return x; } diff --git a/clang/test/CodeGen/arc/arguments.c b/clang/test/CodeGen/arc/arguments.c index a913984e13f8..648a2ea3ce9c 100644 --- a/clang/test/CodeGen/arc/arguments.c +++ b/clang/test/CodeGen/arc/arguments.c @@ -22,7 +22,7 @@ void cf1(cs1 i) {} typedef struct { int cc; } s2; -// CHECK: define{{.*}} void @f2(ptr noalias sret(%struct.s2) align 4 %agg.result) +// CHECK: define{{.*}} void @f2(ptr dead_on_unwind noalias writable sret(%struct.s2) align 4 %agg.result) s2 f2(void) { s2 foo; return foo; @@ -32,7 +32,7 @@ typedef struct { int cc; int dd; } s3; -// CHECK: define{{.*}} void @f3(ptr noalias sret(%struct.s3) align 4 %agg.result) +// CHECK: define{{.*}} void @f3(ptr dead_on_unwind noalias writable sret(%struct.s3) align 4 %agg.result) s3 f3(void) { s3 foo; return foo; @@ -128,8 +128,8 @@ void st3(s16 a, s16 b, s16 c) {} // 1 sret + 1 i32 + 2*(i32 coerce) + 4*(i32 coerce) + 1 byval s16 st4(int x, s8 a, s16 b, s16 c) { return b; } -// CHECK: define{{.*}} void @st4(ptr noalias sret(%struct.s16) align 4 %agg.result, i32 inreg noundef %x, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce) +// CHECK: define{{.*}} void @st4(ptr dead_on_unwind noalias writable sret(%struct.s16) align 4 %agg.result, i32 inreg noundef %x, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce) // 1 sret + 2*(i32 coerce) + 4*(i32 coerce) + 4*(i32 coerce) s16 st5(s8 a, s16 b, s16 c) { return b; } -// CHECK: define{{.*}} void @st5(ptr noalias sret(%struct.s16) align 4 %agg.result, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce) +// CHECK: define{{.*}} void @st5(ptr dead_on_unwind noalias writable sret(%struct.s16) align 4 %agg.result, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce) diff --git a/clang/test/CodeGen/arm-aapcs-vfp.c b/clang/test/CodeGen/arm-aapcs-vfp.c index 5caf93016cd2..9fae33f476d3 100644 --- a/clang/test/CodeGen/arm-aapcs-vfp.c +++ b/clang/test/CodeGen/arm-aapcs-vfp.c @@ -126,7 +126,7 @@ void test_vfp_stack_gpr_split_1(double a, double b, double c, double d, double e // CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_2(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, [2 x i64] %k.coerce) void test_vfp_stack_gpr_split_2(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_long_long_int k) {} -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(ptr noalias sret(%struct.struct_long_long_int) align 8 %agg.result, double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, [2 x i64] %k.coerce) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(ptr dead_on_unwind noalias writable sret(%struct.struct_long_long_int) align 8 %agg.result, double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, [2 x i64] %k.coerce) struct_long_long_int test_vfp_stack_gpr_split_3(double a, double b, double c, double d, double e, double f, double g, double h, double i, struct_long_long_int k) {} typedef struct { int a; int b:4; int c; } struct_int_bitfield_int; diff --git a/clang/test/CodeGen/arm-arguments.c b/clang/test/CodeGen/arm-arguments.c index 17e4d3abd976..8fe2016315f2 100644 --- a/clang/test/CodeGen/arm-arguments.c +++ b/clang/test/CodeGen/arm-arguments.c @@ -29,13 +29,13 @@ struct s4 { struct s4_0 { int f0; } f0; }; struct s4 f4(void) {} // APCS-GNU-LABEL: define{{.*}} void @f5( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // AAPCS-LABEL: define{{.*}} arm_aapcscc i32 @f5() struct s5 { struct { } f0; int f1; }; struct s5 f5(void) {} // APCS-GNU-LABEL: define{{.*}} void @f6( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // AAPCS-LABEL: define{{.*}} arm_aapcscc i32 @f6() struct s6 { int f0[1]; }; struct s6 f6(void) {} @@ -46,7 +46,7 @@ struct s7 { struct { int : 0; } f0; }; struct s7 f7(void) {} // APCS-GNU-LABEL: define{{.*}} void @f8( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // AAPCS-LABEL: define{{.*}} arm_aapcscc void @f8() struct s8 { struct { int : 0; } f0[1]; }; struct s8 f8(void) {} @@ -62,7 +62,7 @@ struct s10 { int f0; int : 0; int : 0; }; struct s10 f10(void) {} // APCS-GNU-LABEL: define{{.*}} void @f11( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // AAPCS-LABEL: define{{.*}} arm_aapcscc i32 @f11() struct s11 { int : 0; int f0; }; struct s11 f11(void) {} @@ -73,7 +73,7 @@ union u12 { char f0; short f1; int f2; }; union u12 f12(void) {} // APCS-GNU-LABEL: define{{.*}} void @f13( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // FIXME: This should return a float. // AAPCS-FIXME: darm_aapcscc efine float @f13() @@ -81,7 +81,7 @@ struct s13 { float f0; }; struct s13 f13(void) {} // APCS-GNU-LABEL: define{{.*}} void @f14( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // AAPCS-LABEL: define{{.*}} arm_aapcscc i32 @f14() union u14 { float f0; }; union u14 f14(void) {} @@ -105,13 +105,13 @@ struct s18 { short f0; char f1 : 4; }; struct s18 f18(void) {} // APCS-GNU-LABEL: define{{.*}} void @f19( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // AAPCS-LABEL: define{{.*}} arm_aapcscc i32 @f19() struct s19 { int f0; struct s8 f1; }; struct s19 f19(void) {} // APCS-GNU-LABEL: define{{.*}} void @f20( -// APCS-GNU: ptr noalias sret +// APCS-GNU: ptr dead_on_unwind noalias writable sret // AAPCS-LABEL: define{{.*}} arm_aapcscc i32 @f20() struct s20 { struct s8 f1; int f0; }; struct s20 f20(void) {} @@ -129,10 +129,10 @@ struct s21 f21(void) {} // APCS-GNU-LABEL: define{{.*}} i128 @f27() // AAPCS-LABEL: define{{.*}} arm_aapcscc i16 @f22() // AAPCS-LABEL: define{{.*}} arm_aapcscc i32 @f23() -// AAPCS: define{{.*}} arm_aapcscc void @f24({{.*}} noalias sret -// AAPCS: define{{.*}} arm_aapcscc void @f25({{.*}} noalias sret -// AAPCS: define{{.*}} arm_aapcscc void @f26({{.*}} noalias sret -// AAPCS: define{{.*}} arm_aapcscc void @f27({{.*}} noalias sret +// AAPCS: define{{.*}} arm_aapcscc void @f24({{.*}} dead_on_unwind noalias writable sret +// AAPCS: define{{.*}} arm_aapcscc void @f25({{.*}} dead_on_unwind noalias writable sret +// AAPCS: define{{.*}} arm_aapcscc void @f26({{.*}} dead_on_unwind noalias writable sret +// AAPCS: define{{.*}} arm_aapcscc void @f27({{.*}} dead_on_unwind noalias writable sret _Complex char f22(void) {} _Complex short f23(void) {} _Complex int f24(void) {} @@ -150,8 +150,8 @@ struct s28 f28() {} struct s29 { _Complex short f0; }; struct s29 f29() {} -// APCS-GNU: define{{.*}} void @f30({{.*}} noalias sret -// AAPCS: define{{.*}} arm_aapcscc void @f30({{.*}} noalias sret +// APCS-GNU: define{{.*}} void @f30({{.*}} dead_on_unwind noalias writable sret +// AAPCS: define{{.*}} arm_aapcscc void @f30({{.*}} dead_on_unwind noalias writable sret struct s30 { _Complex int f0; }; struct s30 f30() {} diff --git a/clang/test/CodeGen/arm-homogenous.c b/clang/test/CodeGen/arm-homogenous.c index dbfb5fb28446..44a539598eb9 100644 --- a/clang/test/CodeGen/arm-homogenous.c +++ b/clang/test/CodeGen/arm-homogenous.c @@ -27,7 +27,7 @@ void test_union_with_first_floats(void) { void test_return_union_with_first_floats(void) { g_u_f = returns_union_with_first_floats(); } -// CHECK: declare arm_aapcs_vfpcc void @returns_union_with_first_floats(ptr sret(%union.union_with_first_floats) align 4) +// CHECK: declare arm_aapcs_vfpcc void @returns_union_with_first_floats(ptr dead_on_unwind writable sret(%union.union_with_first_floats) align 4) /* This is not a homogenous aggregate - fundamental types are different */ typedef union { @@ -47,7 +47,7 @@ void test_union_with_non_first_floats(void) { void test_return_union_with_non_first_floats(void) { g_u_nf_f = returns_union_with_non_first_floats(); } -// CHECK: declare arm_aapcs_vfpcc void @returns_union_with_non_first_floats(ptr sret(%union.union_with_non_first_floats) align 4) +// CHECK: declare arm_aapcs_vfpcc void @returns_union_with_non_first_floats(ptr dead_on_unwind writable sret(%union.union_with_non_first_floats) align 4) /* This is not a homogenous aggregate - fundamental types are different */ typedef struct { @@ -67,7 +67,7 @@ void test_struct_with_union_with_first_floats(void) { void test_return_struct_with_union_with_first_floats(void) { g_s_f = returns_struct_with_union_with_first_floats(); } -// CHECK: declare arm_aapcs_vfpcc void @returns_struct_with_union_with_first_floats(ptr sret(%struct.struct_with_union_with_first_floats) align 4) +// CHECK: declare arm_aapcs_vfpcc void @returns_struct_with_union_with_first_floats(ptr dead_on_unwind writable sret(%struct.struct_with_union_with_first_floats) align 4) /* This is not a homogenous aggregate - fundamental types are different */ typedef struct { @@ -87,7 +87,7 @@ void test_struct_with_union_with_non_first_floats(void) { void test_return_struct_with_union_with_non_first_floats(void) { g_s_nf_f = returns_struct_with_union_with_non_first_floats(); } -// CHECK: declare arm_aapcs_vfpcc void @returns_struct_with_union_with_non_first_floats(ptr sret(%struct.struct_with_union_with_non_first_floats) align 4) +// CHECK: declare arm_aapcs_vfpcc void @returns_struct_with_union_with_non_first_floats(ptr dead_on_unwind writable sret(%struct.struct_with_union_with_non_first_floats) align 4) /* Plain array is not a homogenous aggregate */ extern void takes_array_of_floats(float a[4]); diff --git a/clang/test/CodeGen/arm-neon-vld.c b/clang/test/CodeGen/arm-neon-vld.c index 697992edb5f6..959c07cc2219 100644 --- a/clang/test/CodeGen/arm-neon-vld.c +++ b/clang/test/CodeGen/arm-neon-vld.c @@ -11,7 +11,7 @@ // CHECK-LABEL: @test_vld1_f16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.float16x4x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v4f16.p0|arm.neon.vld1x2.v4i16.p0}}(ptr %a) // CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] @@ -25,7 +25,7 @@ float16x4x2_t test_vld1_f16_x2(float16_t const *a) { // CHECK-LABEL: @test_vld1_f16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.float16x4x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v4f16.p0|arm.neon.vld1x3.v4i16.p0}}(ptr %a) // CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] @@ -39,7 +39,7 @@ float16x4x3_t test_vld1_f16_x3(float16_t const *a) { // CHECK-LABEL: @test_vld1_f16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.float16x4x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v4f16.p0|arm.neon.vld1x4.v4i16.p0}}(ptr %a) // CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] @@ -53,7 +53,7 @@ float16x4x4_t test_vld1_f16_x4(float16_t const *a) { // CHECK-LABEL: @test_vld1_f32_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.float32x2x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2f32.p0(ptr %a) // CHECK: store { <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] @@ -67,7 +67,7 @@ float32x2x2_t test_vld1_f32_x2(float32_t const *a) { // CHECK-LABEL: @test_vld1_f32_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.float32x2x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2f32.p0(ptr %a) // CHECK: store { <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] @@ -80,7 +80,7 @@ float32x2x3_t test_vld1_f32_x3(float32_t const *a) { // CHECK-LABEL: @test_vld1_f32_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.float32x2x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2f32.p0(ptr %a) // CHECK: store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] @@ -94,7 +94,7 @@ float32x2x4_t test_vld1_f32_x4(float32_t const *a) { // CHECK-LABEL: @test_vld1_p16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.poly16x4x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -108,7 +108,7 @@ poly16x4x2_t test_vld1_p16_x2(poly16_t const *a) { // CHECK-LABEL: @test_vld1_p16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.poly16x4x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -122,7 +122,7 @@ poly16x4x3_t test_vld1_p16_x3(poly16_t const *a) { // CHECK-LABEL: @test_vld1_p16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.poly16x4x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -136,7 +136,7 @@ poly16x4x4_t test_vld1_p16_x4(poly16_t const *a) { // CHECK-LABEL: @test_vld1_p8_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.poly8x8x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -150,7 +150,7 @@ poly8x8x2_t test_vld1_p8_x2(poly8_t const *a) { // CHECK-LABEL: @test_vld1_p8_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.poly8x8x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -164,7 +164,7 @@ poly8x8x3_t test_vld1_p8_x3(poly8_t const *a) { // CHECK-LABEL: @test_vld1_p8_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.poly8x8x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -178,7 +178,7 @@ poly8x8x4_t test_vld1_p8_x4(poly8_t const *a) { // CHECK-LABEL: @test_vld1_s16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int16x4x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -192,7 +192,7 @@ int16x4x2_t test_vld1_s16_x2(int16_t const *a) { // CHECK-LABEL: @test_vld1_s16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int16x4x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -206,7 +206,7 @@ int16x4x3_t test_vld1_s16_x3(int16_t const *a) { // CHECK-LABEL: @test_vld1_s16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int16x4x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -220,7 +220,7 @@ int16x4x4_t test_vld1_s16_x4(int16_t const *a) { // CHECK-LABEL: @test_vld1_s32_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int32x2x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0(ptr %a) // CHECK: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -234,7 +234,7 @@ int32x2x2_t test_vld1_s32_x2(int32_t const *a) { // CHECK-LABEL: @test_vld1_s32_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int32x2x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0(ptr %a) // CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -248,7 +248,7 @@ int32x2x3_t test_vld1_s32_x3(int32_t const *a) { // CHECK-LABEL: @test_vld1_s32_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int32x2x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0(ptr %a) // CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -262,7 +262,7 @@ int32x2x4_t test_vld1_s32_x4(int32_t const *a) { // CHECK-LABEL: @test_vld1_s64_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int64x1x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0(ptr %a) // CHECK: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -276,7 +276,7 @@ int64x1x2_t test_vld1_s64_x2(int64_t const *a) { // CHECK-LABEL: @test_vld1_s64_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int64x1x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0(ptr %a) // CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -290,7 +290,7 @@ int64x1x3_t test_vld1_s64_x3(int64_t const *a) { // CHECK-LABEL: @test_vld1_s64_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int64x1x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0(ptr %a) // CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -304,7 +304,7 @@ int64x1x4_t test_vld1_s64_x4(int64_t const *a) { // CHECK-LABEL: @test_vld1_s8_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int8x8x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -318,7 +318,7 @@ int8x8x2_t test_vld1_s8_x2(int8_t const *a) { // CHECK-LABEL: @test_vld1_s8_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int8x8x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -332,7 +332,7 @@ int8x8x3_t test_vld1_s8_x3(int8_t const *a) { // CHECK-LABEL: @test_vld1_s8_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.int8x8x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -346,7 +346,7 @@ int8x8x4_t test_vld1_s8_x4(int8_t const *a) { // CHECK-LABEL: @test_vld1_u16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint16x4x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -360,7 +360,7 @@ uint16x4x2_t test_vld1_u16_x2(uint16_t const *a) { // CHECK-LABEL: @test_vld1_u16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint16x4x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -374,7 +374,7 @@ uint16x4x3_t test_vld1_u16_x3(uint16_t const *a) { // CHECK-LABEL: @test_vld1_u16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint16x4x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a) // CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -388,7 +388,7 @@ uint16x4x4_t test_vld1_u16_x4(uint16_t const *a) { // CHECK-LABEL: @test_vld1_u32_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint32x2x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0(ptr %a) // CHECK: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -402,7 +402,7 @@ uint32x2x2_t test_vld1_u32_x2(uint32_t const *a) { // CHECK-LABEL: @test_vld1_u32_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint32x2x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0(ptr %a) // CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -416,7 +416,7 @@ uint32x2x3_t test_vld1_u32_x3(uint32_t const *a) { // CHECK-LABEL: @test_vld1_u32_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint32x2x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0(ptr %a) // CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -430,7 +430,7 @@ uint32x2x4_t test_vld1_u32_x4(uint32_t const *a) { // CHECK-LABEL: @test_vld1_u64_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint64x1x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0(ptr %a) // CHECK: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -444,7 +444,7 @@ uint64x1x2_t test_vld1_u64_x2(uint64_t const *a) { // CHECK-LABEL: @test_vld1_u64_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint64x1x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0(ptr %a) // CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -458,7 +458,7 @@ uint64x1x3_t test_vld1_u64_x3(uint64_t const *a) { // CHECK-LABEL: @test_vld1_u64_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint64x1x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0(ptr %a) // CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -472,7 +472,7 @@ uint64x1x4_t test_vld1_u64_x4(uint64_t const *a) { // CHECK-LABEL: @test_vld1_u8_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x2_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint8x8x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -486,7 +486,7 @@ uint8x8x2_t test_vld1_u8_x2(uint8_t const *a) { // CHECK-LABEL: @test_vld1_u8_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x3_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint8x8x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -500,7 +500,7 @@ uint8x8x3_t test_vld1_u8_x3(uint8_t const *a) { // CHECK-LABEL: @test_vld1_u8_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x4_t, align 8 -// CHECK-A32: ptr noalias sret(%struct.uint8x8x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a) // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -514,7 +514,7 @@ uint8x8x4_t test_vld1_u8_x4(uint8_t const *a) { // CHECK-LABEL: @test_vld1q_f16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.float16x8x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v8f16.p0|arm.neon.vld1x2.v8i16.p0}}(ptr %a) // CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] @@ -528,7 +528,7 @@ float16x8x2_t test_vld1q_f16_x2(float16_t const *a) { // CHECK-LABEL: @test_vld1q_f16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.float16x8x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v8f16.p0|arm.neon.vld1x3.v8i16.p0}}(ptr %a) // CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] @@ -542,7 +542,7 @@ float16x8x3_t test_vld1q_f16_x3(float16_t const *a) { // CHECK-LABEL: @test_vld1q_f16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.float16x8x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v8f16.p0|arm.neon.vld1x4.v8i16.p0}}(ptr %a) // CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] @@ -556,7 +556,7 @@ float16x8x4_t test_vld1q_f16_x4(float16_t const *a) { // CHECK-LABEL: @test_vld1q_f32_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.float32x4x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4f32.p0(ptr %a) // CHECK: store { <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] @@ -570,7 +570,7 @@ float32x4x2_t test_vld1q_f32_x2(float32_t const *a) { // CHECK-LABEL: @test_vld1q_f32_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.float32x4x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4f32.p0(ptr %a) // CHECK: store { <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] @@ -584,7 +584,7 @@ float32x4x3_t test_vld1q_f32_x3(float32_t const *a) { // CHECK-LABEL: @test_vld1q_f32_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.float32x4x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4f32.p0(ptr %a) // CHECK: store { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] @@ -598,7 +598,7 @@ float32x4x4_t test_vld1q_f32_x4(float32_t const *a) { // CHECK-LABEL: @test_vld1q_p16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.poly16x8x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -612,7 +612,7 @@ poly16x8x2_t test_vld1q_p16_x2(poly16_t const *a) { // CHECK-LABEL: @test_vld1q_p16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.poly16x8x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -626,7 +626,7 @@ poly16x8x3_t test_vld1q_p16_x3(poly16_t const *a) { // CHECK-LABEL: @test_vld1q_p16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.poly16x8x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -640,7 +640,7 @@ poly16x8x4_t test_vld1q_p16_x4(poly16_t const *a) { // CHECK-LABEL: @test_vld1q_p8_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.poly8x16x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -654,7 +654,7 @@ poly8x16x2_t test_vld1q_p8_x2(poly8_t const *a) { // CHECK-LABEL: @test_vld1q_p8_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.poly8x16x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -668,7 +668,7 @@ poly8x16x3_t test_vld1q_p8_x3(poly8_t const *a) { // CHECK-LABEL: @test_vld1q_p8_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.poly8x16x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -682,7 +682,7 @@ poly8x16x4_t test_vld1q_p8_x4(poly8_t const *a) { // CHECK-LABEL: @test_vld1q_s16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int16x8x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -696,7 +696,7 @@ int16x8x2_t test_vld1q_s16_x2(int16_t const *a) { // CHECK-LABEL: @test_vld1q_s16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int16x8x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -710,7 +710,7 @@ int16x8x3_t test_vld1q_s16_x3(int16_t const *a) { // CHECK-LABEL: @test_vld1q_s16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int16x8x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -724,7 +724,7 @@ int16x8x4_t test_vld1q_s16_x4(int16_t const *a) { // CHECK-LABEL: @test_vld1q_s32_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int32x4x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0(ptr %a) // CHECK: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -738,7 +738,7 @@ int32x4x2_t test_vld1q_s32_x2(int32_t const *a) { // CHECK-LABEL: @test_vld1q_s32_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int32x4x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0(ptr %a) // CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -752,7 +752,7 @@ int32x4x3_t test_vld1q_s32_x3(int32_t const *a) { // CHECK-LABEL: @test_vld1q_s32_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int32x4x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0(ptr %a) // CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -766,7 +766,7 @@ int32x4x4_t test_vld1q_s32_x4(int32_t const *a) { // CHECK-LABEL: @test_vld1q_s64_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int64x2x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0(ptr %a) // CHECK: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -780,7 +780,7 @@ int64x2x2_t test_vld1q_s64_x2(int64_t const *a) { // CHECK-LABEL: @test_vld1q_s64_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int64x2x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0(ptr %a) // CHECK: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -794,7 +794,7 @@ int64x2x3_t test_vld1q_s64_x3(int64_t const *a) { // CHECK-LABEL: @test_vld1q_s64_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int64x2x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0(ptr %a) // CHECK: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -808,7 +808,7 @@ int64x2x4_t test_vld1q_s64_x4(int64_t const *a) { // CHECK-LABEL: @test_vld1q_s8_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int8x16x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -822,7 +822,7 @@ int8x16x2_t test_vld1q_s8_x2(int8_t const *a) { // CHECK-LABEL: @test_vld1q_s8_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int8x16x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -836,7 +836,7 @@ int8x16x3_t test_vld1q_s8_x3(int8_t const *a) { // CHECK-LABEL: @test_vld1q_s8_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.int8x16x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -850,7 +850,7 @@ int8x16x4_t test_vld1q_s8_x4(int8_t const *a) { // CHECK-LABEL: @test_vld1q_u16_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint16x8x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -864,7 +864,7 @@ uint16x8x2_t test_vld1q_u16_x2(uint16_t const *a) { // CHECK-LABEL: @test_vld1q_u16_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint16x8x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -878,7 +878,7 @@ uint16x8x3_t test_vld1q_u16_x3(uint16_t const *a) { // CHECK-LABEL: @test_vld1q_u16_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint16x8x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a) // CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] @@ -892,7 +892,7 @@ uint16x8x4_t test_vld1q_u16_x4(uint16_t const *a) { // CHECK-LABEL: @test_vld1q_u32_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint32x4x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0(ptr %a) // CHECK: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -906,7 +906,7 @@ uint32x4x2_t test_vld1q_u32_x2(uint32_t const *a) { // CHECK-LABEL: @test_vld1q_u32_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint32x4x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0(ptr %a) // CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -920,7 +920,7 @@ uint32x4x3_t test_vld1q_u32_x3(uint32_t const *a) { // CHECK-LABEL: @test_vld1q_u32_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint32x4x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0(ptr %a) // CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] @@ -934,7 +934,7 @@ uint32x4x4_t test_vld1q_u32_x4(uint32_t const *a) { // CHECK-LABEL: @test_vld1q_u64_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint64x2x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0(ptr %a) // CHECK: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -948,7 +948,7 @@ uint64x2x2_t test_vld1q_u64_x2(uint64_t const *a) { // CHECK-LABEL: @test_vld1q_u64_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint64x2x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0(ptr %a) // CHECK: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -962,7 +962,7 @@ uint64x2x3_t test_vld1q_u64_x3(uint64_t const *a) { // CHECK-LABEL: @test_vld1q_u64_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint64x2x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0(ptr %a) // CHECK: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] @@ -976,7 +976,7 @@ uint64x2x4_t test_vld1q_u64_x4(uint64_t const *a) { // CHECK-LABEL: @test_vld1q_u8_x2( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x2_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint8x16x2_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x2_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -990,7 +990,7 @@ uint8x16x2_t test_vld1q_u8_x2(uint8_t const *a) { // CHECK-LABEL: @test_vld1q_u8_x3( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x3_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint8x16x3_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x3_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] @@ -1004,7 +1004,7 @@ uint8x16x3_t test_vld1q_u8_x3(uint8_t const *a) { // CHECK-LABEL: @test_vld1q_u8_x4( // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x4_t, align 16 -// CHECK-A32: ptr noalias sret(%struct.uint8x16x4_t) align 8 [[RETVAL:%.*]], +// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x4_t) align 8 [[RETVAL:%.*]], // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align {{16|8}} // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a) // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] diff --git a/clang/test/CodeGen/arm-swiftcall.c b/clang/test/CodeGen/arm-swiftcall.c index 12bccb5087c8..9fa607a968cc 100644 --- a/clang/test/CodeGen/arm-swiftcall.c +++ b/clang/test/CodeGen/arm-swiftcall.c @@ -22,7 +22,7 @@ SWIFTCALL int indirect_result_2(OUT int *arg0, OUT float *arg1) { __builtin_unr typedef struct { char array[1024]; } struct_reallybig; SWIFTCALL struct_reallybig indirect_result_3(OUT int *arg0, OUT float *arg1) { __builtin_unreachable(); } -// CHECK-LABEL: define{{.*}} void @indirect_result_3(ptr noalias sret(%struct.struct_reallybig) {{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}) +// CHECK-LABEL: define{{.*}} void @indirect_result_3(ptr dead_on_unwind noalias writable sret(%struct.struct_reallybig) {{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}, ptr noalias align 4 dereferenceable(4){{.*}}) SWIFTCALL void context_1(CONTEXT void *self) {} // CHECK-LABEL: define{{.*}} void @context_1(ptr swiftself @@ -258,7 +258,7 @@ typedef struct { } struct_big_1; TEST(struct_big_1) -// CHECK-LABEL: define{{.*}} void @return_struct_big_1({{.*}} noalias sret({{.*}}) +// CHECK-LABEL: define{{.*}} void @return_struct_big_1({{.*}} dead_on_unwind noalias writable sret({{.*}}) // Should not be byval. // CHECK-LABEL: define{{.*}} void @take_struct_big_1(ptr{{( %.*)?}}) @@ -553,7 +553,7 @@ typedef struct { double d4; } struct_d5; TEST(struct_d5) -// CHECK: define{{.*}} swiftcc void @return_struct_d5(ptr noalias sret([[STRUCT5:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_d5(ptr dead_on_unwind noalias writable sret([[STRUCT5:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_d5(ptr typedef struct { @@ -703,7 +703,7 @@ typedef struct { long long l2; } struct_l3; TEST(struct_l3) -// CHECK: define{{.*}} swiftcc void @return_struct_l3(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_l3(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_l3(ptr typedef struct { @@ -713,7 +713,7 @@ typedef struct { long long l3; } struct_l4; TEST(struct_l4) -// CHECK: define{{.*}} swiftcc void @return_struct_l4(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_l4(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_l4(ptr typedef struct { @@ -724,7 +724,7 @@ typedef struct { long long l4; } struct_l5; TEST(struct_l5) -// CHECK: define{{.*}} swiftcc void @return_struct_l5(ptr noalias sret([[STRUCT5:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_l5(ptr dead_on_unwind noalias writable sret([[STRUCT5:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_l5(ptr typedef struct { @@ -769,7 +769,7 @@ typedef struct { char16 c4; } struct_vc5; TEST(struct_vc5) -// CHECK: define{{.*}} swiftcc void @return_struct_vc5(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vc5(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_vc5(ptr typedef struct { @@ -814,7 +814,7 @@ typedef struct { short8 c4; } struct_vs5; TEST(struct_vs5) -// CHECK: define{{.*}} swiftcc void @return_struct_vs5(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vs5(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_vs5(ptr typedef struct { @@ -859,7 +859,7 @@ typedef struct { int4 c4; } struct_vi5; TEST(struct_vi5) -// CHECK: define{{.*}} swiftcc void @return_struct_vi5(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vi5(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_vi5(ptr typedef struct { @@ -887,7 +887,7 @@ typedef struct { long2 c4; } struct_vl5; TEST(struct_vl5) -// CHECK: define{{.*}} swiftcc void @return_struct_vl5(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vl5(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_vl5(ptr typedef struct { @@ -915,7 +915,7 @@ typedef struct { double2 c4; } struct_vd5; TEST(struct_vd5) -// CHECK: define{{.*}} swiftcc void @return_struct_vd5(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vd5(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_vd5(ptr typedef struct { @@ -939,7 +939,7 @@ typedef struct { double4 c2; } struct_vd43; TEST(struct_vd43) -// CHECK: define{{.*}} swiftcc void @return_struct_vd43(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vd43(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_vd43(ptr typedef struct { @@ -975,7 +975,7 @@ typedef struct { float4 c4; } struct_vf5; TEST(struct_vf5) -// CHECK: define{{.*}} swiftcc void @return_struct_vf5(ptr noalias sret([[STRUCT:%.*]]) +// CHECK: define{{.*}} swiftcc void @return_struct_vf5(ptr dead_on_unwind noalias writable sret([[STRUCT:%.*]]) // CHECK: define{{.*}} swiftcc void @take_struct_vf5(ptr typedef struct { diff --git a/clang/test/CodeGen/arm-varargs.c b/clang/test/CodeGen/arm-varargs.c index 17330262e6ad..f754c7f52e59 100644 --- a/clang/test/CodeGen/arm-varargs.c +++ b/clang/test/CodeGen/arm-varargs.c @@ -23,7 +23,7 @@ struct bigstruct { }; struct bigstruct simple_struct(void) { -// CHECK-LABEL: define{{.*}} void @simple_struct(ptr noalias sret(%struct.bigstruct) align 4 %agg.result) +// CHECK-LABEL: define{{.*}} void @simple_struct(ptr dead_on_unwind noalias writable sret(%struct.bigstruct) align 4 %agg.result) return va_arg(the_list, struct bigstruct); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[NEXT:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 40 @@ -38,7 +38,7 @@ struct aligned_bigstruct { }; struct aligned_bigstruct simple_aligned_struct(void) { -// CHECK-LABEL: define{{.*}} void @simple_aligned_struct(ptr noalias sret(%struct.aligned_bigstruct) align 8 %agg.result) +// CHECK-LABEL: define{{.*}} void @simple_aligned_struct(ptr dead_on_unwind noalias writable sret(%struct.aligned_bigstruct) align 8 %agg.result) return va_arg(the_list, struct aligned_bigstruct); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[CUR_INT_ADD:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 7 @@ -66,7 +66,7 @@ struct hfa { }; struct hfa simple_hfa(void) { -// CHECK-LABEL: define{{.*}} void @simple_hfa(ptr noalias sret(%struct.hfa) align 4 %agg.result) +// CHECK-LABEL: define{{.*}} void @simple_hfa(ptr dead_on_unwind noalias writable sret(%struct.hfa) align 4 %agg.result) return va_arg(the_list, struct hfa); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[NEXT:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 8 @@ -159,7 +159,7 @@ typedef struct __attribute__((aligned(16))) { int val; } overaligned_int_struct; overaligned_int_struct overaligned_int_struct_test(void) { -// CHECK-LABEL: define{{.*}} void @overaligned_int_struct_test(ptr noalias sret(%struct.overaligned_int_struct) align 16 %agg.result) +// CHECK-LABEL: define{{.*}} void @overaligned_int_struct_test(ptr dead_on_unwind noalias writable sret(%struct.overaligned_int_struct) align 16 %agg.result) return va_arg(the_list, overaligned_int_struct); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[NEXT:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 16 @@ -172,7 +172,7 @@ typedef struct __attribute__((packed,aligned(2))) { long long val; } underaligned_long_long_struct; underaligned_long_long_struct underaligned_long_long_struct_test(void) { -// CHECK-LABEL: define{{.*}} void @underaligned_long_long_struct_test(ptr noalias sret(%struct.underaligned_long_long_struct) align 2 %agg.result) +// CHECK-LABEL: define{{.*}} void @underaligned_long_long_struct_test(ptr dead_on_unwind noalias writable sret(%struct.underaligned_long_long_struct) align 2 %agg.result) return va_arg(the_list, underaligned_long_long_struct); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[NEXT:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 8 @@ -185,7 +185,7 @@ typedef struct __attribute__((aligned(16))) { long long val; } overaligned_long_long_struct; overaligned_long_long_struct overaligned_long_long_struct_test(void) { -// CHECK-LABEL: define{{.*}} void @overaligned_long_long_struct_test(ptr noalias sret(%struct.overaligned_long_long_struct) align 16 %agg.result) +// CHECK-LABEL: define{{.*}} void @overaligned_long_long_struct_test(ptr dead_on_unwind noalias writable sret(%struct.overaligned_long_long_struct) align 16 %agg.result) return va_arg(the_list, overaligned_long_long_struct); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[CUR_INT_ADD:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 7 @@ -219,7 +219,7 @@ typedef struct { int val __attribute__((aligned(16))); } overaligned_int_struct_member; overaligned_int_struct_member overaligned_int_struct_member_test(void) { -// CHECK-LABEL: define{{.*}} void @overaligned_int_struct_member_test(ptr noalias sret(%struct.overaligned_int_struct_member) align 16 %agg.result) +// CHECK-LABEL: define{{.*}} void @overaligned_int_struct_member_test(ptr dead_on_unwind noalias writable sret(%struct.overaligned_int_struct_member) align 16 %agg.result) return va_arg(the_list, overaligned_int_struct_member); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[CUR_INT_ADD:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 7 @@ -234,7 +234,7 @@ typedef struct { long long val __attribute__((packed,aligned(2))); } underaligned_long_long_struct_member; underaligned_long_long_struct_member underaligned_long_long_struct_member_test(void) { -// CHECK-LABEL: define{{.*}} void @underaligned_long_long_struct_member_test(ptr noalias sret(%struct.underaligned_long_long_struct_member) align 2 %agg.result) +// CHECK-LABEL: define{{.*}} void @underaligned_long_long_struct_member_test(ptr dead_on_unwind noalias writable sret(%struct.underaligned_long_long_struct_member) align 2 %agg.result) return va_arg(the_list, underaligned_long_long_struct_member); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[NEXT:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 8 @@ -247,7 +247,7 @@ typedef struct { long long val __attribute__((aligned(16))); } overaligned_long_long_struct_member; overaligned_long_long_struct_member overaligned_long_long_struct_member_test(void) { -// CHECK-LABEL: define{{.*}} void @overaligned_long_long_struct_member_test(ptr noalias sret(%struct.overaligned_long_long_struct_member) align 16 %agg.result) +// CHECK-LABEL: define{{.*}} void @overaligned_long_long_struct_member_test(ptr dead_on_unwind noalias writable sret(%struct.overaligned_long_long_struct_member) align 16 %agg.result) return va_arg(the_list, overaligned_long_long_struct_member); // CHECK: [[CUR:%[a-z0-9._]+]] = load ptr, ptr @the_list, align 4 // CHECK: [[CUR_INT_ADD:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr [[CUR]], i32 7 diff --git a/clang/test/CodeGen/arm-vector-arguments.c b/clang/test/CodeGen/arm-vector-arguments.c index a92e5a84798b..0e3abfb7e5a0 100644 --- a/clang/test/CodeGen/arm-vector-arguments.c +++ b/clang/test/CodeGen/arm-vector-arguments.c @@ -9,7 +9,7 @@ #include -// CHECK: define{{.*}} void @f0(ptr noalias sret(%struct.int8x16x2_t) align 16 %agg.result, <16 x i8> noundef %{{.*}}, <16 x i8> noundef %{{.*}}) +// CHECK: define{{.*}} void @f0(ptr dead_on_unwind noalias writable sret(%struct.int8x16x2_t) align 16 %agg.result, <16 x i8> noundef %{{.*}}, <16 x i8> noundef %{{.*}}) int8x16x2_t f0(int8x16_t a0, int8x16_t a1) { return vzipq_s8(a0, a1); } @@ -25,7 +25,7 @@ typedef float T_float32x16 __attribute__ ((__vector_size__ (64))); T_float32x2 f1_0(T_float32x2 a0) { return a0; } // CHECK: define{{.*}} <4 x float> @f1_1(<4 x float> noundef %{{.*}}) T_float32x4 f1_1(T_float32x4 a0) { return a0; } -// CHECK: define{{.*}} void @f1_2(ptr noalias sret(<8 x float>) align 32 %{{.*}}, <8 x float> noundef %{{.*}}) +// CHECK: define{{.*}} void @f1_2(ptr dead_on_unwind noalias writable sret(<8 x float>) align 32 %{{.*}}, <8 x float> noundef %{{.*}}) T_float32x8 f1_2(T_float32x8 a0) { return a0; } -// CHECK: define{{.*}} void @f1_3(ptr noalias sret(<16 x float>) align 64 %{{.*}}, <16 x float> noundef %{{.*}}) +// CHECK: define{{.*}} void @f1_3(ptr dead_on_unwind noalias writable sret(<16 x float>) align 64 %{{.*}}, <16 x float> noundef %{{.*}}) T_float32x16 f1_3(T_float32x16 a0) { return a0; } diff --git a/clang/test/CodeGen/arm-vfp16-arguments.c b/clang/test/CodeGen/arm-vfp16-arguments.c index 59120c1cc7f1..da034626024f 100644 --- a/clang/test/CodeGen/arm-vfp16-arguments.c +++ b/clang/test/CodeGen/arm-vfp16-arguments.c @@ -71,6 +71,6 @@ void test_hfa(hfa_t a) {} hfa_t ghfa; hfa_t test_ret_hfa(void) { return ghfa; } -// CHECK-SOFT: define{{.*}} void @test_ret_hfa(ptr noalias nocapture writeonly sret(%struct.hfa_t) align 8 %agg.result) +// CHECK-SOFT: define{{.*}} void @test_ret_hfa(ptr dead_on_unwind noalias nocapture writable writeonly sret(%struct.hfa_t) align 8 %agg.result) // CHECK-HARD: define{{.*}} arm_aapcs_vfpcc [2 x <2 x i32>] @test_ret_hfa() // CHECK-FULL: define{{.*}} arm_aapcs_vfpcc %struct.hfa_t @test_ret_hfa() diff --git a/clang/test/CodeGen/arm-vfp16-arguments2.cpp b/clang/test/CodeGen/arm-vfp16-arguments2.cpp index 2ba0c0d349ab..6221e85e856b 100644 --- a/clang/test/CodeGen/arm-vfp16-arguments2.cpp +++ b/clang/test/CodeGen/arm-vfp16-arguments2.cpp @@ -37,27 +37,27 @@ struct S5 : B1 { B1 M[1]; }; -// CHECK-SOFT: define{{.*}} void @_Z2f12S1(ptr noalias nocapture writeonly sret(%struct.S1) align 8 %agg.result, [2 x i64] %s1.coerce) +// CHECK-SOFT: define{{.*}} void @_Z2f12S1(ptr dead_on_unwind noalias nocapture writable writeonly sret(%struct.S1) align 8 %agg.result, [2 x i64] %s1.coerce) // CHECK-HARD: define{{.*}} arm_aapcs_vfpcc [2 x <2 x i32>] @_Z2f12S1([2 x <2 x i32>] returned %s1.coerce) // CHECK-FULL: define{{.*}} arm_aapcs_vfpcc %struct.S1 @_Z2f12S1(%struct.S1 returned %s1.coerce) struct S1 f1(struct S1 s1) { return s1; } -// CHECK-SOFT: define{{.*}} void @_Z2f22S2(ptr noalias nocapture writeonly sret(%struct.S2) align 8 %agg.result, [4 x i32] %s2.coerce) +// CHECK-SOFT: define{{.*}} void @_Z2f22S2(ptr dead_on_unwind noalias nocapture writable writeonly sret(%struct.S2) align 8 %agg.result, [4 x i32] %s2.coerce) // CHECK-HARD: define{{.*}} arm_aapcs_vfpcc [2 x <2 x i32>] @_Z2f22S2([2 x <2 x i32>] returned %s2.coerce) // CHECK-FULL: define{{.*}} arm_aapcs_vfpcc %struct.S2 @_Z2f22S2(%struct.S2 returned %s2.coerce) struct S2 f2(struct S2 s2) { return s2; } -// CHECK-SOFT: define{{.*}} void @_Z2f32S3(ptr noalias nocapture writeonly sret(%struct.S3) align 8 %agg.result, [2 x i64] %s3.coerce) +// CHECK-SOFT: define{{.*}} void @_Z2f32S3(ptr dead_on_unwind noalias nocapture writable writeonly sret(%struct.S3) align 8 %agg.result, [2 x i64] %s3.coerce) // CHECK-HARD: define{{.*}} arm_aapcs_vfpcc [2 x <2 x i32>] @_Z2f32S3([2 x <2 x i32>] returned %s3.coerce) // CHECK-FULL: define{{.*}} arm_aapcs_vfpcc %struct.S3 @_Z2f32S3(%struct.S3 returned %s3.coerce) struct S3 f3(struct S3 s3) { return s3; } -// CHECK-SOFT: define{{.*}} void @_Z2f42S4(ptr noalias nocapture writeonly sret(%struct.S4) align 8 %agg.result, [2 x i64] %s4.coerce) +// CHECK-SOFT: define{{.*}} void @_Z2f42S4(ptr dead_on_unwind noalias nocapture writable writeonly sret(%struct.S4) align 8 %agg.result, [2 x i64] %s4.coerce) // CHECK-HARD: define{{.*}} arm_aapcs_vfpcc [2 x <2 x i32>] @_Z2f42S4([2 x <2 x i32>] returned %s4.coerce) // CHECK-FULL: define{{.*}} arm_aapcs_vfpcc %struct.S4 @_Z2f42S4(%struct.S4 returned %s4.coerce) struct S4 f4(struct S4 s4) { return s4; } -// CHECK-SOFT: define{{.*}} void @_Z2f52S5(ptr noalias nocapture writeonly sret(%struct.S5) align 8 %agg.result, [2 x i64] %s5.coerce) +// CHECK-SOFT: define{{.*}} void @_Z2f52S5(ptr dead_on_unwind noalias nocapture writable writeonly sret(%struct.S5) align 8 %agg.result, [2 x i64] %s5.coerce) // CHECK-HARD: define{{.*}} arm_aapcs_vfpcc %struct.S5 @_Z2f52S5(%struct.S5 returned %s5.coerce) // CHECK-FULL: define{{.*}} arm_aapcs_vfpcc %struct.S5 @_Z2f52S5(%struct.S5 returned %s5.coerce) struct S5 f5(struct S5 s5) { return s5; } diff --git a/clang/test/CodeGen/arm64-arguments.c b/clang/test/CodeGen/arm64-arguments.c index caa71ced0a8a..8ed9d952f80c 100644 --- a/clang/test/CodeGen/arm64-arguments.c +++ b/clang/test/CodeGen/arm64-arguments.c @@ -226,9 +226,9 @@ T_float32x2 f1_0(T_float32x2 a0) { return a0; } // CHECK: define{{.*}} <4 x float> @f1_1(<4 x float> noundef %{{.*}}) T_float32x4 f1_1(T_float32x4 a0) { return a0; } // Vector with length bigger than 16-byte is illegal and is passed indirectly. -// CHECK: define{{.*}} void @f1_2(ptr noalias sret(<8 x float>) align 16 %{{.*}}, ptr noundef %0) +// CHECK: define{{.*}} void @f1_2(ptr dead_on_unwind noalias writable sret(<8 x float>) align 16 %{{.*}}, ptr noundef %0) T_float32x8 f1_2(T_float32x8 a0) { return a0; } -// CHECK: define{{.*}} void @f1_3(ptr noalias sret(<16 x float>) align 16 %{{.*}}, ptr noundef %0) +// CHECK: define{{.*}} void @f1_3(ptr dead_on_unwind noalias writable sret(<16 x float>) align 16 %{{.*}}, ptr noundef %0) T_float32x16 f1_3(T_float32x16 a0) { return a0; } // Testing alignment with aggregates: HFA, aggregates with size <= 16 bytes and diff --git a/clang/test/CodeGen/arm64-microsoft-arguments.cpp b/clang/test/CodeGen/arm64-microsoft-arguments.cpp index a9ae6911b16e..e8309888dcfe 100644 --- a/clang/test/CodeGen/arm64-microsoft-arguments.cpp +++ b/clang/test/CodeGen/arm64-microsoft-arguments.cpp @@ -28,8 +28,8 @@ S2 f2() { } // Pass and return for type size > 16 bytes. -// CHECK: define {{.*}} void @{{.*}}f3{{.*}}(ptr noalias sret(%struct.S3) align 4 %agg.result) -// CHECK: call void {{.*}}func3{{.*}}(ptr sret(%struct.S3) align 4 %agg.result, ptr noundef %agg.tmp) +// CHECK: define {{.*}} void @{{.*}}f3{{.*}}(ptr dead_on_unwind noalias writable sret(%struct.S3) align 4 %agg.result) +// CHECK: call void {{.*}}func3{{.*}}(ptr dead_on_unwind writable sret(%struct.S3) align 4 %agg.result, ptr noundef %agg.tmp) struct S3 { int a[5]; }; @@ -42,8 +42,8 @@ S3 f3() { // Pass and return aggregate (of size < 16 bytes) with non-trivial destructor. // Passed directly but returned indirectly. -// CHECK: define {{.*}} void {{.*}}f4{{.*}}(ptr inreg noalias sret(%struct.S4) align 4 %agg.result) -// CHECK: call void {{.*}}func4{{.*}}(ptr inreg sret(%struct.S4) align 4 %agg.result, [2 x i64] %0) +// CHECK: define {{.*}} void {{.*}}f4{{.*}}(ptr dead_on_unwind inreg noalias writable sret(%struct.S4) align 4 %agg.result) +// CHECK: call void {{.*}}func4{{.*}}(ptr dead_on_unwind inreg writable sret(%struct.S4) align 4 %agg.result, [2 x i64] %0) struct S4 { int a[3]; ~S4(); @@ -56,8 +56,8 @@ S4 f4() { } // Pass and return from instance method called from instance method. -// CHECK: define {{.*}} void @{{.*}}bar@Q1{{.*}}(ptr {{[^,]*}} %this, ptr inreg noalias sret(%class.P1) align 1 %agg.result) -// CHECK: call void {{.*}}foo@P1{{.*}}(ptr noundef{{[^,]*}} %ref.tmp, ptr inreg sret(%class.P1) align 1 %agg.result, i8 %0) +// CHECK: define {{.*}} void @{{.*}}bar@Q1{{.*}}(ptr {{[^,]*}} %this, ptr dead_on_unwind inreg noalias writable sret(%class.P1) align 1 %agg.result) +// CHECK: call void {{.*}}foo@P1{{.*}}(ptr noundef{{[^,]*}} %ref.tmp, ptr dead_on_unwind inreg writable sret(%class.P1) align 1 %agg.result, i8 %0) class P1 { public: @@ -76,7 +76,7 @@ P1 Q1::bar() { // Pass and return from instance method called from free function. // CHECK: define {{.*}} void {{.*}}bar{{.*}}() -// CHECK: call void {{.*}}foo@P2{{.*}}(ptr noundef{{[^,]*}} %ref.tmp, ptr inreg sret(%class.P2) align 1 %retval, i8 %0) +// CHECK: call void {{.*}}foo@P2{{.*}}(ptr noundef{{[^,]*}} %ref.tmp, ptr dead_on_unwind inreg writable sret(%class.P2) align 1 %retval, i8 %0) class P2 { public: P2 foo(P2 x); @@ -89,8 +89,8 @@ P2 bar() { // Pass and return an object with a user-provided constructor (passed directly, // returned indirectly) -// CHECK: define {{.*}} void @{{.*}}f5{{.*}}(ptr inreg noalias sret(%struct.S5) align 4 %agg.result) -// CHECK: call void {{.*}}func5{{.*}}(ptr inreg sret(%struct.S5) align 4 %agg.result, i64 {{.*}}) +// CHECK: define {{.*}} void @{{.*}}f5{{.*}}(ptr dead_on_unwind inreg noalias writable sret(%struct.S5) align 4 %agg.result) +// CHECK: call void {{.*}}func5{{.*}}(ptr dead_on_unwind inreg writable sret(%struct.S5) align 4 %agg.result, i64 {{.*}}) struct S5 { S5(); int x; @@ -146,8 +146,8 @@ struct S8 { int y; }; -// CHECK: define {{.*}} void {{.*}}?f8{{.*}}(ptr inreg noalias sret(%struct.S8) align 4 {{.*}}) -// CHECK: call void {{.*}}func8{{.*}}(ptr inreg sret(%struct.S8) align 4 {{.*}}, i64 {{.*}}) +// CHECK: define {{.*}} void {{.*}}?f8{{.*}}(ptr dead_on_unwind inreg noalias writable sret(%struct.S8) align 4 {{.*}}) +// CHECK: call void {{.*}}func8{{.*}}(ptr dead_on_unwind inreg writable sret(%struct.S8) align 4 {{.*}}, i64 {{.*}}) S8 func8(S8 x); S8 f8() { S8 x; @@ -157,8 +157,8 @@ S8 f8() { // Pass and return an object with a non-trivial copy-assignment operator and // a trivial copy constructor (passed directly, returned indirectly) -// CHECK: define {{.*}} void @"?f9@@YA?AUS9@@XZ"(ptr inreg noalias sret(%struct.S9) align 4 {{.*}}) -// CHECK: call void {{.*}}func9{{.*}}(ptr inreg sret(%struct.S9) align 4 {{.*}}, i64 {{.*}}) +// CHECK: define {{.*}} void @"?f9@@YA?AUS9@@XZ"(ptr dead_on_unwind inreg noalias writable sret(%struct.S9) align 4 {{.*}}) +// CHECK: call void {{.*}}func9{{.*}}(ptr dead_on_unwind inreg writable sret(%struct.S9) align 4 {{.*}}, i64 {{.*}}) struct S9 { S9& operator=(const S9&); int x; @@ -174,8 +174,8 @@ S9 f9() { // Pass and return an object with a base class (passed directly, returned // indirectly). -// CHECK: define dso_local void {{.*}}f10{{.*}}(ptr inreg noalias sret(%struct.S10) align 4 {{.*}}) -// CHECK: call void {{.*}}func10{{.*}}(ptr inreg sret(%struct.S10) align 4 {{.*}}, [2 x i64] {{.*}}) +// CHECK: define dso_local void {{.*}}f10{{.*}}(ptr dead_on_unwind inreg noalias writable sret(%struct.S10) align 4 {{.*}}) +// CHECK: call void {{.*}}func10{{.*}}(ptr dead_on_unwind inreg writable sret(%struct.S10) align 4 {{.*}}, [2 x i64] {{.*}}) struct S10 : public S1 { int x; }; @@ -189,8 +189,8 @@ S10 f10() { // Pass and return a non aggregate object exceeding > 128 bits (passed // indirectly, returned indirectly) -// CHECK: define dso_local void {{.*}}f11{{.*}}(ptr inreg noalias sret(%struct.S11) align 8 {{.*}}) -// CHECK: call void {{.*}}func11{{.*}}(ptr inreg sret(%struct.S11) align 8 {{.*}}, ptr {{.*}}) +// CHECK: define dso_local void {{.*}}f11{{.*}}(ptr dead_on_unwind inreg noalias writable sret(%struct.S11) align 8 {{.*}}) +// CHECK: call void {{.*}}func11{{.*}}(ptr dead_on_unwind inreg writable sret(%struct.S11) align 8 {{.*}}, ptr {{.*}}) struct S11 { virtual void f(); int a[5]; diff --git a/clang/test/CodeGen/arm64_32.c b/clang/test/CodeGen/arm64_32.c index 31d94c610704..f7473610d30d 100644 --- a/clang/test/CodeGen/arm64_32.c +++ b/clang/test/CodeGen/arm64_32.c @@ -27,4 +27,4 @@ long double LongDoubleVar = 0.0; typedef float __attribute__((ext_vector_type(16))) v16f32; v16f32 func(v16f32 in) { return in; } -// CHECK: define{{.*}} void @func(ptr noalias sret(<16 x float>) align 16 {{%.*}}, <16 x float> noundef {{%.*}}) +// CHECK: define{{.*}} void @func(ptr dead_on_unwind noalias writable sret(<16 x float>) align 16 {{%.*}}, <16 x float> noundef {{%.*}}) diff --git a/clang/test/CodeGen/armv7k-abi.c b/clang/test/CodeGen/armv7k-abi.c index e070d5a9c704..fd18dafa7d03 100644 --- a/clang/test/CodeGen/armv7k-abi.c +++ b/clang/test/CodeGen/armv7k-abi.c @@ -42,7 +42,7 @@ typedef struct { // CHECK: define{{.*}} void @big_struct_indirect(ptr noundef %b) void big_struct_indirect(BigStruct b) {} -// CHECK: define{{.*}} void @return_big_struct_indirect(ptr noalias sret +// CHECK: define{{.*}} void @return_big_struct_indirect(ptr dead_on_unwind noalias writable sret BigStruct return_big_struct_indirect() {} // Structs smaller than 16 bytes should be passed directly, and coerced to diff --git a/clang/test/CodeGen/attr-noundef.cpp b/clang/test/CodeGen/attr-noundef.cpp index a2aa7e313f0e..d236b35fdfd7 100644 --- a/clang/test/CodeGen/attr-noundef.cpp +++ b/clang/test/CodeGen/attr-noundef.cpp @@ -26,7 +26,7 @@ struct NoCopy { }; NoCopy ret_nocopy() { return {}; } void pass_nocopy(NoCopy e) {} -// CHECK: [[DEF]] void @{{.*}}ret_nocopy{{.*}}(ptr noalias sret({{[^)]+}}) align 4 % +// CHECK: [[DEF]] void @{{.*}}ret_nocopy{{.*}}(ptr dead_on_unwind noalias writable sret({{[^)]+}}) align 4 % // CHECK: [[DEF]] void @{{.*}}pass_nocopy{{.*}}(ptr noundef % struct Huge { @@ -34,7 +34,7 @@ struct Huge { }; Huge ret_huge() { return {}; } void pass_huge(Huge h) {} -// CHECK: [[DEF]] void @{{.*}}ret_huge{{.*}}(ptr noalias sret({{[^)]+}}) align 4 % +// CHECK: [[DEF]] void @{{.*}}ret_huge{{.*}}(ptr dead_on_unwind noalias writable sret({{[^)]+}}) align 4 % // CHECK: [[DEF]] void @{{.*}}pass_huge{{.*}}(ptr noundef } // namespace check_structs @@ -58,7 +58,7 @@ union NoCopy { }; NoCopy ret_nocopy() { return {}; } void pass_nocopy(NoCopy e) {} -// CHECK: [[DEF]] void @{{.*}}ret_nocopy{{.*}}(ptr noalias sret({{[^)]+}}) align 4 % +// CHECK: [[DEF]] void @{{.*}}ret_nocopy{{.*}}(ptr dead_on_unwind noalias writable sret({{[^)]+}}) align 4 % // CHECK: [[DEF]] void @{{.*}}pass_nocopy{{.*}}(ptr noundef % } // namespace check_unions diff --git a/clang/test/CodeGen/blocks.c b/clang/test/CodeGen/blocks.c index 469cf7cb89a2..8f947fcdfccb 100644 --- a/clang/test/CodeGen/blocks.c +++ b/clang/test/CodeGen/blocks.c @@ -15,7 +15,7 @@ struct s0 { int a[64]; }; -// CHECK: define internal void @__f2_block_invoke(ptr noalias sret(%struct.s0) align 4 {{%.*}}, ptr noundef {{%.*}}, ptr noundef byval(%struct.s0) align 4 {{.*}}) +// CHECK: define internal void @__f2_block_invoke(ptr dead_on_unwind noalias writable sret(%struct.s0) align 4 {{%.*}}, ptr noundef {{%.*}}, ptr noundef byval(%struct.s0) align 4 {{.*}}) struct s0 f2(struct s0 a0) { return ^(struct s0 a1){ return a1; }(a0); } diff --git a/clang/test/CodeGen/c11atomics-ios.c b/clang/test/CodeGen/c11atomics-ios.c index af489811edc5..bcb6519ab0dc 100644 --- a/clang/test/CodeGen/c11atomics-ios.c +++ b/clang/test/CodeGen/c11atomics-ios.c @@ -178,7 +178,7 @@ void testPromotedStruct(_Atomic(PS) *fp) { } PS test_promoted_load(_Atomic(PS) *addr) { - // CHECK-LABEL: @test_promoted_load(ptr noalias sret(%struct.PS) align 2 %agg.result, ptr noundef %addr) + // CHECK-LABEL: @test_promoted_load(ptr dead_on_unwind noalias writable sret(%struct.PS) align 2 %agg.result, ptr noundef %addr) // CHECK: [[ADDR_ARG:%.*]] = alloca ptr, align 4 // CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: store ptr %addr, ptr [[ADDR_ARG]], align 4 @@ -209,7 +209,7 @@ void test_promoted_store(_Atomic(PS) *addr, PS *val) { } PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { - // CHECK-LABEL: @test_promoted_exchange(ptr noalias sret(%struct.PS) align 2 %agg.result, ptr noundef %addr, ptr noundef %val) + // CHECK-LABEL: @test_promoted_exchange(ptr dead_on_unwind noalias writable sret(%struct.PS) align 2 %agg.result, ptr noundef %addr, ptr noundef %val) // CHECK: [[ADDR_ARG:%.*]] = alloca ptr, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca ptr, align 4 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 diff --git a/clang/test/CodeGen/c11atomics.c b/clang/test/CodeGen/c11atomics.c index 773ed41991f7..dd1f52f70ae0 100644 --- a/clang/test/CodeGen/c11atomics.c +++ b/clang/test/CodeGen/c11atomics.c @@ -338,7 +338,7 @@ void testPromotedStruct(_Atomic(PS) *fp) { } PS test_promoted_load(_Atomic(PS) *addr) { - // CHECK-LABEL: @test_promoted_load(ptr noalias sret(%struct.PS) align 2 %agg.result, ptr noundef %addr) + // CHECK-LABEL: @test_promoted_load(ptr dead_on_unwind noalias writable sret(%struct.PS) align 2 %agg.result, ptr noundef %addr) // CHECK: [[ADDR_ARG:%.*]] = alloca ptr, align 4 // CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: store ptr %addr, ptr [[ADDR_ARG]], align 4 @@ -368,7 +368,7 @@ void test_promoted_store(_Atomic(PS) *addr, PS *val) { } PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { - // CHECK-LABEL: @test_promoted_exchange(ptr noalias sret(%struct.PS) align 2 %agg.result, ptr noundef %addr, ptr noundef %val) + // CHECK-LABEL: @test_promoted_exchange(ptr dead_on_unwind noalias writable sret(%struct.PS) align 2 %agg.result, ptr noundef %addr, ptr noundef %val) // CHECK: [[ADDR_ARG:%.*]] = alloca ptr, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca ptr, align 4 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 diff --git a/clang/test/CodeGen/ext-int-cc.c b/clang/test/CodeGen/ext-int-cc.c index bcf29fc1309d..001e866d34b4 100644 --- a/clang/test/CodeGen/ext-int-cc.c +++ b/clang/test/CodeGen/ext-int-cc.c @@ -226,104 +226,104 @@ _BitInt(64) ReturnPassing2(void){} _BitInt(127) ReturnPassing3(void){} // LIN64: define{{.*}} { i64, i64 } @ReturnPassing3( -// WIN64: define dso_local void @ReturnPassing3(ptr noalias sret -// LIN32: define{{.*}} void @ReturnPassing3(ptr noalias sret -// WIN32: define dso_local void @ReturnPassing3(ptr noalias sret -// NACL: define{{.*}} void @ReturnPassing3(ptr noalias sret +// WIN64: define dso_local void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// LIN32: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// WIN32: define dso_local void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// NACL: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret // NVPTX/64 makes the intentional choice to put all return values direct, even // large structures, so we do the same here. // NVPTX64: define{{.*}} i127 @ReturnPassing3( // NVPTX: define{{.*}} i127 @ReturnPassing3( // SPARCV9: define{{.*}} i127 @ReturnPassing3( -// SPARC: define{{.*}} void @ReturnPassing3(ptr noalias sret +// SPARC: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret // MIPS64: define{{.*}} i127 @ReturnPassing3( -// MIPS: define{{.*}} void @ReturnPassing3(ptr noalias sret -// SPIR64: define{{.*}} spir_func void @ReturnPassing3(ptr noalias sret -// SPIR: define{{.*}} spir_func void @ReturnPassing3(ptr noalias sret -// HEX: define{{.*}} void @ReturnPassing3(ptr noalias sret -// LANAI: define{{.*}} void @ReturnPassing3(ptr noalias sret -// R600: define{{.*}} void @ReturnPassing3(ptr addrspace(5) noalias sret -// ARC: define{{.*}} void @ReturnPassing3(ptr noalias sret -// XCORE: define{{.*}} void @ReturnPassing3(ptr noalias sret +// MIPS: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// SPIR64: define{{.*}} spir_func void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// SPIR: define{{.*}} spir_func void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// HEX: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// LANAI: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// R600: define{{.*}} void @ReturnPassing3(ptr addrspace(5) dead_on_unwind noalias writable sret +// ARC: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret +// XCORE: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret // RISCV64: define{{.*}} i127 @ReturnPassing3( -// RISCV32: define{{.*}} void @ReturnPassing3(ptr noalias sret +// RISCV32: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret // WASM: define{{.*}} i127 @ReturnPassing3( -// SYSTEMZ: define{{.*}} void @ReturnPassing3(ptr noalias sret +// SYSTEMZ: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret // PPC64: define{{.*}} i127 @ReturnPassing3( -// PPC32: define{{.*}} void @ReturnPassing3(ptr noalias sret +// PPC32: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret // AARCH64: define{{.*}} i127 @ReturnPassing3( // AARCH64DARWIN: define{{.*}} i127 @ReturnPassing3( -// ARM: define{{.*}} arm_aapcscc void @ReturnPassing3(ptr noalias sret +// ARM: define{{.*}} arm_aapcscc void @ReturnPassing3(ptr dead_on_unwind noalias writable sret // LA64: define{{.*}} i127 @ReturnPassing3( -// LA32: define{{.*}} void @ReturnPassing3(ptr noalias sret +// LA32: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret _BitInt(128) ReturnPassing4(void){} // LIN64: define{{.*}} { i64, i64 } @ReturnPassing4( -// WIN64: define dso_local void @ReturnPassing4(ptr noalias sret -// LIN32: define{{.*}} void @ReturnPassing4(ptr noalias sret -// WIN32: define dso_local void @ReturnPassing4(ptr noalias sret -// NACL: define{{.*}} void @ReturnPassing4(ptr noalias sret +// WIN64: define dso_local void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// LIN32: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// WIN32: define dso_local void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// NACL: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret // NVPTX64: define{{.*}} i128 @ReturnPassing4( // NVPTX: define{{.*}} i128 @ReturnPassing4( // SPARCV9: define{{.*}} i128 @ReturnPassing4( -// SPARC: define{{.*}} void @ReturnPassing4(ptr noalias sret +// SPARC: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret // MIPS64: define{{.*}} i128 @ReturnPassing4( -// MIPS: define{{.*}} void @ReturnPassing4(ptr noalias sret -// SPIR64: define{{.*}} spir_func void @ReturnPassing4(ptr noalias sret -// SPIR: define{{.*}} spir_func void @ReturnPassing4(ptr noalias sret -// HEX: define{{.*}} void @ReturnPassing4(ptr noalias sret -// LANAI: define{{.*}} void @ReturnPassing4(ptr noalias sret -// R600: define{{.*}} void @ReturnPassing4(ptr addrspace(5) noalias sret -// ARC: define{{.*}} void @ReturnPassing4(ptr noalias sret -// XCORE: define{{.*}} void @ReturnPassing4(ptr noalias sret +// MIPS: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// SPIR64: define{{.*}} spir_func void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// SPIR: define{{.*}} spir_func void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// HEX: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// LANAI: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// R600: define{{.*}} void @ReturnPassing4(ptr addrspace(5) dead_on_unwind noalias writable sret +// ARC: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret +// XCORE: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret // RISCV64: define{{.*}} i128 @ReturnPassing4( -// RISCV32: define{{.*}} void @ReturnPassing4(ptr noalias sret +// RISCV32: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret // WASM: define{{.*}} i128 @ReturnPassing4( -// SYSTEMZ: define{{.*}} void @ReturnPassing4(ptr noalias sret +// SYSTEMZ: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret // PPC64: define{{.*}} i128 @ReturnPassing4( -// PPC32: define{{.*}} void @ReturnPassing4(ptr noalias sret +// PPC32: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret // AARCH64: define{{.*}} i128 @ReturnPassing4( // AARCH64DARWIN: define{{.*}} i128 @ReturnPassing4( -// ARM: define{{.*}} arm_aapcscc void @ReturnPassing4(ptr noalias sret +// ARM: define{{.*}} arm_aapcscc void @ReturnPassing4(ptr dead_on_unwind noalias writable sret // LA64: define{{.*}} i128 @ReturnPassing4( -// LA32: define{{.*}} void @ReturnPassing4(ptr noalias sret +// LA32: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret #if __BITINT_MAXWIDTH__ > 128 _BitInt(129) ReturnPassing5(void){} -// LIN64: define{{.*}} void @ReturnPassing5(ptr noalias sret -// WIN64: define dso_local void @ReturnPassing5(ptr noalias sret -// LIN32: define{{.*}} void @ReturnPassing5(ptr noalias sret -// WIN32: define dso_local void @ReturnPassing5(ptr noalias sret -// NACL-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret +// LIN64: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// WIN64: define dso_local void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// LIN32: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// WIN32: define dso_local void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// NACL-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret // NVPTX64-NOT: define{{.*}} i129 @ReturnPassing5( // NVPTX-NOT: define{{.*}} i129 @ReturnPassing5( // SPARCV9-NOT: define{{.*}} i129 @ReturnPassing5( -// SPARC-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// MIPS64-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// MIPS-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// SPIR64-NOT: define{{.*}} spir_func void @ReturnPassing5(ptr noalias sret -// SPIR-NOT: define{{.*}} spir_func void @ReturnPassing5(ptr noalias sret -// HEX-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// LANAI-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret +// SPARC-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// MIPS64-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// MIPS-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// SPIR64-NOT: define{{.*}} spir_func void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// SPIR-NOT: define{{.*}} spir_func void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// HEX-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// LANAI-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret // R600-NOT: define{{.*}} void @ReturnPassing5(ptr addrspace(5) noalias sret -// ARC-NOT: define{{.*}} void @ReturnPassing5(ptr inreg noalias sret -// XCORE-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// RISCV64-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// RISCV32-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// WASM-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// SYSTEMZ-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// PPC64-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// PPC32-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// AARCH64-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// AARCH64DARWIN-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// ARM-NOT: define{{.*}} arm_aapcscc void @ReturnPassing5(ptr noalias sret -// LA64-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret -// LA32-NOT: define{{.*}} void @ReturnPassing5(ptr noalias sret +// ARC-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind inreg noalias writable sret +// XCORE-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// RISCV64-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// RISCV32-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// WASM-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// SYSTEMZ-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// PPC64-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// PPC32-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// AARCH64-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// AARCH64DARWIN-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// ARM-NOT: define{{.*}} arm_aapcscc void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// LA64-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret +// LA32-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret // SparcV9 is odd in that it has a return-size limit of 256, not 128 or 64 // like other platforms, so test to make sure this behavior will still work. _BitInt(256) ReturnPassing6(void) {} // SPARCV9-NOT: define{{.*}} i256 @ReturnPassing6( _BitInt(257) ReturnPassing7(void) {} -// SPARCV9-NOT: define{{.*}} void @ReturnPassing7(ptr noalias sret +// SPARCV9-NOT: define{{.*}} void @ReturnPassing7(ptr dead_on_unwind noalias writable sret #endif diff --git a/clang/test/CodeGen/isfpclass.c b/clang/test/CodeGen/isfpclass.c index 430f5d94211f..6633db88f71a 100644 --- a/clang/test/CodeGen/isfpclass.c +++ b/clang/test/CodeGen/isfpclass.c @@ -160,7 +160,7 @@ int4 check_isfpclass_nan_strict_v4f32(float4 x) { } // CHECK-LABEL: define dso_local void @check_isfpclass_nan_v4f64 -// CHECK-SAME: (ptr noalias nocapture writeonly sret(<4 x i64>) align 16 [[AGG_RESULT:%.*]], ptr nocapture noundef readonly [[TMP0:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { +// CHECK-SAME: (ptr dead_on_unwind noalias nocapture writable writeonly sret(<4 x i64>) align 16 [[AGG_RESULT:%.*]], ptr nocapture noundef readonly [[TMP0:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[X:%.*]] = load <4 x double>, ptr [[TMP0]], align 16, !tbaa [[TBAA2:![0-9]+]] // CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <4 x double> [[X]], zeroinitializer diff --git a/clang/test/CodeGen/lanai-arguments.c b/clang/test/CodeGen/lanai-arguments.c index bc291faa867f..bfd3b41a91eb 100644 --- a/clang/test/CodeGen/lanai-arguments.c +++ b/clang/test/CodeGen/lanai-arguments.c @@ -16,7 +16,7 @@ void f1(s1 i) {} typedef struct { int cc; } s2; -// CHECK: define{{.*}} void @f2(ptr noalias sret(%struct.s2) align 4 %agg.result) +// CHECK: define{{.*}} void @f2(ptr dead_on_unwind noalias writable sret(%struct.s2) align 4 %agg.result) s2 f2(void) { s2 foo; return foo; @@ -26,7 +26,7 @@ typedef struct { int cc; int dd; } s3; -// CHECK: define{{.*}} void @f3(ptr noalias sret(%struct.s3) align 4 %agg.result) +// CHECK: define{{.*}} void @f3(ptr dead_on_unwind noalias writable sret(%struct.s3) align 4 %agg.result) s3 f3(void) { s3 foo; return foo; diff --git a/clang/test/CodeGen/mcu-struct-return.c b/clang/test/CodeGen/mcu-struct-return.c index 218f9734c9c3..38a9bc2a36bf 100644 --- a/clang/test/CodeGen/mcu-struct-return.c +++ b/clang/test/CodeGen/mcu-struct-return.c @@ -42,7 +42,7 @@ struct S1 bar1(void) { return s1; } struct S2 bar2(void) { return s2; } struct S1 bar3(union U1 u) { return s1; } // CHECK: define{{.*}} void @foo1() -// CHECK: define{{.*}} void @foo2(ptr noalias sret([[UNION2_TYPE]]) align 4 %{{.+}}) +// CHECK: define{{.*}} void @foo2(ptr dead_on_unwind noalias writable sret([[UNION2_TYPE]]) align 4 %{{.+}}) // CHECK: define{{.*}} i32 @foo3() // CHECK: define{{.*}} void @bar1() // CHECK: define{{.*}} i32 @bar2() @@ -62,7 +62,7 @@ void run(void) { // CHECK: [[Y1:%.+]] = alloca [[STRUCT1_TYPE]] // CHECK: [[Y2:%.+]] = alloca [[STRUCT2_TYPE]] // CHECK: call void @foo1() - // CHECK: call void @foo2(ptr sret([[UNION2_TYPE]]) align 4 [[X2]]) + // CHECK: call void @foo2(ptr dead_on_unwind writable sret([[UNION2_TYPE]]) align 4 [[X2]]) // CHECK: {{.+}} = call i32 @foo3() // CHECK: call void @bar1() // CHECK: {{.+}} = call i32 @bar2() diff --git a/clang/test/CodeGen/mingw-long-double.c b/clang/test/CodeGen/mingw-long-double.c index a50f8f0b3b63..4be97526f963 100644 --- a/clang/test/CodeGen/mingw-long-double.c +++ b/clang/test/CodeGen/mingw-long-double.c @@ -32,15 +32,15 @@ long double TestLD(long double x) { return x * x; } // GNU32: define dso_local x86_fp80 @TestLD(x86_fp80 noundef %x) -// GNU64: define dso_local void @TestLD(ptr noalias sret(x86_fp80) align 16 %agg.result, ptr noundef %0) +// GNU64: define dso_local void @TestLD(ptr dead_on_unwind noalias writable sret(x86_fp80) align 16 %agg.result, ptr noundef %0) // MSC64: define dso_local double @TestLD(double noundef %x) long double _Complex TestLDC(long double _Complex x) { return x * x; } -// GNU32: define dso_local void @TestLDC(ptr noalias sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 4 %x) -// GNU64: define dso_local void @TestLDC(ptr noalias sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, ptr noundef %x) -// MSC64: define dso_local void @TestLDC(ptr noalias sret({ double, double }) align 8 %agg.result, ptr noundef %x) +// GNU32: define dso_local void @TestLDC(ptr dead_on_unwind noalias writable sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 4 %x) +// GNU64: define dso_local void @TestLDC(ptr dead_on_unwind noalias writable sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, ptr noundef %x) +// MSC64: define dso_local void @TestLDC(ptr dead_on_unwind noalias writable sret({ double, double }) align 8 %agg.result, ptr noundef %x) // GNU32: declare dso_local void @__mulxc3 // GNU64: declare dso_local void @__mulxc3 diff --git a/clang/test/CodeGen/mips-vector-return.c b/clang/test/CodeGen/mips-vector-return.c index b6da2af2ffd6..d2103d1def74 100644 --- a/clang/test/CodeGen/mips-vector-return.c +++ b/clang/test/CodeGen/mips-vector-return.c @@ -8,14 +8,14 @@ typedef float v4sf __attribute__ ((__vector_size__ (16))); typedef double v4df __attribute__ ((__vector_size__ (32))); typedef int v4i32 __attribute__ ((__vector_size__ (16))); -// O32-LABEL: define{{.*}} void @test_v4sf(ptr noalias nocapture writeonly sret +// O32-LABEL: define{{.*}} void @test_v4sf(ptr dead_on_unwind noalias nocapture writable writeonly sret // N64: define{{.*}} inreg { i64, i64 } @test_v4sf v4sf test_v4sf(float a) { return (v4sf){0.0f, a, 0.0f, 0.0f}; } -// O32-LABEL: define{{.*}} void @test_v4df(ptr noalias nocapture writeonly sret -// N64-LABEL: define{{.*}} void @test_v4df(ptr noalias nocapture writeonly sret +// O32-LABEL: define{{.*}} void @test_v4df(ptr dead_on_unwind noalias nocapture writable writeonly sret +// N64-LABEL: define{{.*}} void @test_v4df(ptr dead_on_unwind noalias nocapture writable writeonly sret v4df test_v4df(double a) { return (v4df){0.0, a, 0.0, 0.0}; } diff --git a/clang/test/CodeGen/mips-zero-sized-struct.c b/clang/test/CodeGen/mips-zero-sized-struct.c index 12bd9abf6cf4..b40ff59f73fb 100644 --- a/clang/test/CodeGen/mips-zero-sized-struct.c +++ b/clang/test/CodeGen/mips-zero-sized-struct.c @@ -19,7 +19,7 @@ // RUN: %clang_cc1 -triple mipsisa64r6-unknown-linux-gnuabi64 -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s // RUN: %clang_cc1 -triple mipsisa64r6el-unknown-linux-gnuabi64 -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s -// O32: define{{.*}} void @fn28(ptr noalias sret(%struct.T2) align 1 %agg.result, i8 noundef signext %arg0) +// O32: define{{.*}} void @fn28(ptr dead_on_unwind noalias writable sret(%struct.T2) align 1 %agg.result, i8 noundef signext %arg0) // N32: define{{.*}} void @fn28(i8 noundef signext %arg0) // N64: define{{.*}} void @fn28(i8 noundef signext %arg0) diff --git a/clang/test/CodeGen/mips64-nontrivial-return.cpp b/clang/test/CodeGen/mips64-nontrivial-return.cpp index 0987dcaf355d..a8fbf4622f80 100644 --- a/clang/test/CodeGen/mips64-nontrivial-return.cpp +++ b/clang/test/CodeGen/mips64-nontrivial-return.cpp @@ -10,7 +10,7 @@ class D : public B { extern D gd0; -// CHECK: _Z4foo1v(ptr noalias nocapture writeonly sret +// CHECK: _Z4foo1v(ptr dead_on_unwind noalias nocapture writable writeonly sret D foo1(void) { return gd0; diff --git a/clang/test/CodeGen/mips64-padding-arg.c b/clang/test/CodeGen/mips64-padding-arg.c index 7fda45f75098..038103b1df3a 100644 --- a/clang/test/CodeGen/mips64-padding-arg.c +++ b/clang/test/CodeGen/mips64-padding-arg.c @@ -33,9 +33,9 @@ void foo3(int a0, long double a1) { // Insert padding after hidden argument. // -// N64-LABEL: define{{.*}} void @foo5(ptr noalias sret(%struct.S0) align 16 %agg.result, i64 %0, fp128 noundef %a0) -// N64: call void @foo6(ptr sret(%struct.S0) align 16 %agg.result, i32 noundef signext 1, i32 noundef signext 2, i64 undef, fp128 noundef %a0) -// N64: declare void @foo6(ptr sret(%struct.S0) align 16, i32 noundef signext, i32 noundef signext, i64, fp128 noundef) +// N64-LABEL: define{{.*}} void @foo5(ptr dead_on_unwind noalias writable sret(%struct.S0) align 16 %agg.result, i64 %0, fp128 noundef %a0) +// N64: call void @foo6(ptr dead_on_unwind writable sret(%struct.S0) align 16 %agg.result, i32 noundef signext 1, i32 noundef signext 2, i64 undef, fp128 noundef %a0) +// N64: declare void @foo6(ptr dead_on_unwind writable sret(%struct.S0) align 16, i32 noundef signext, i32 noundef signext, i64, fp128 noundef) extern S0 foo6(int, int, long double); diff --git a/clang/test/CodeGen/ms_abi.c b/clang/test/CodeGen/ms_abi.c index adc5094267cb..0fe1741cf9a0 100644 --- a/clang/test/CodeGen/ms_abi.c +++ b/clang/test/CodeGen/ms_abi.c @@ -141,7 +141,7 @@ struct i128 { }; __attribute__((ms_abi)) struct i128 f7(struct i128 a) { - // WIN64: define dso_local void @f7(ptr noalias sret(%struct.i128) align 8 %agg.result, ptr noundef %a) - // FREEBSD: define{{.*}} win64cc void @f7(ptr noalias sret(%struct.i128) align 8 %agg.result, ptr noundef %a) + // WIN64: define dso_local void @f7(ptr dead_on_unwind noalias writable sret(%struct.i128) align 8 %agg.result, ptr noundef %a) + // FREEBSD: define{{.*}} win64cc void @f7(ptr dead_on_unwind noalias writable sret(%struct.i128) align 8 %agg.result, ptr noundef %a) return a; } diff --git a/clang/test/CodeGen/paren-list-agg-init.cpp b/clang/test/CodeGen/paren-list-agg-init.cpp index 0e68beb5c370..eb8d91a7f97f 100644 --- a/clang/test/CodeGen/paren-list-agg-init.cpp +++ b/clang/test/CodeGen/paren-list-agg-init.cpp @@ -136,7 +136,7 @@ A foo1() { return a1; } -// CHECK: define dso_local void @{{.*foo2.*}}(ptr noalias sret([[STRUCT_B]]) align 8 [[AGG_RESULT:%.*]]) +// CHECK: define dso_local void @{{.*foo2.*}}(ptr dead_on_unwind noalias writable sret([[STRUCT_B]]) align 8 [[AGG_RESULT:%.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[AGG_RESULT]], ptr align 8 [[B1]], i64 24, i1 false) // CHECK-NEXT: ret void @@ -144,7 +144,7 @@ B foo2() { return b1; } -// CHECK: define dso_local void @{{.*foo3.*}}(ptr noalias sret([[STRUCT_C]]) align 8 [[AGG_RESULT:%.*]]) +// CHECK: define dso_local void @{{.*foo3.*}}(ptr dead_on_unwind noalias writable sret([[STRUCT_C]]) align 8 [[AGG_RESULT:%.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[AGG_RESULT]], ptr align 8 [[C1]], i64 48, i1 false) // CHECK-NEXT: ret void @@ -229,7 +229,7 @@ void foo7() { D d(A(1, 1), A(11, 11), A(111, 111)); } -// CHECK: dso_local void @{{.*foo8.*}}(ptr noalias sret([[STRUCT_D]]) align 8 [[AGG_RESULT:%.*]]) +// CHECK: dso_local void @{{.*foo8.*}}(ptr dead_on_unwind noalias writable sret([[STRUCT_D]]) align 8 [[AGG_RESULT:%.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[AGG_RESULT]], ptr align 8 [[D1]], i64 56, i1 false) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGen/regcall2.c b/clang/test/CodeGen/regcall2.c index 96bc6615012a..c88d4e485b10 100644 --- a/clang/test/CodeGen/regcall2.c +++ b/clang/test/CodeGen/regcall2.c @@ -19,7 +19,7 @@ double __regcall bar(__sVector a) { } // FIXME: Do we need to change for Windows? -// Win: define dso_local x86_regcallcc void @__regcall3__foo(ptr noalias sret(%struct.__sVector) align 64 %agg.result, i32 noundef %a) #0 +// Win: define dso_local x86_regcallcc void @__regcall3__foo(ptr dead_on_unwind noalias writable sret(%struct.__sVector) align 64 %agg.result, i32 noundef %a) #0 // Win: define dso_local x86_regcallcc double @__regcall3__bar(ptr noundef %a) #0 // Win: attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+avx,+avx2,+avx512f,+avx512vl,+crc32,+cx8,+evex512,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" } diff --git a/clang/test/CodeGen/regparm-struct.c b/clang/test/CodeGen/regparm-struct.c index 70901ca364d0..a533f6cedbba 100644 --- a/clang/test/CodeGen/regparm-struct.c +++ b/clang/test/CodeGen/regparm-struct.c @@ -159,7 +159,7 @@ void g16(void) { } __attribute__((regparm(3))) struct s12 f17(int a, int b, int c); -// CHECK: declare void @f17(ptr inreg sret(%struct.s12) align 4, i32 inreg noundef, i32 inreg noundef, i32 noundef) +// CHECK: declare void @f17(ptr dead_on_unwind inreg writable sret(%struct.s12) align 4, i32 inreg noundef, i32 inreg noundef, i32 noundef) void g17(void) { f17(41, 42, 43); } diff --git a/clang/test/CodeGen/renderscript.c b/clang/test/CodeGen/renderscript.c index 8acf16566454..1629665c1ffb 100644 --- a/clang/test/CodeGen/renderscript.c +++ b/clang/test/CodeGen/renderscript.c @@ -83,15 +83,15 @@ void argLongInt(sLongInt s) {} // and coerced to [a x iNN] for 64-bit RenderScript // ============================================================================= -// CHECK-RS32: void @retShortCharShort(ptr noalias sret(%struct.sShortCharShort) align 2 %agg.result) +// CHECK-RS32: void @retShortCharShort(ptr dead_on_unwind noalias writable sret(%struct.sShortCharShort) align 2 %agg.result) // CHECK-RS64: [3 x i16] @retShortCharShort() sShortCharShort retShortCharShort(void) { sShortCharShort r; return r; } -// CHECK-RS32: void @retIntShortChar(ptr noalias sret(%struct.sIntShortChar) align 4 %agg.result) +// CHECK-RS32: void @retIntShortChar(ptr dead_on_unwind noalias writable sret(%struct.sIntShortChar) align 4 %agg.result) // CHECK-RS64: [2 x i32] @retIntShortChar() sIntShortChar retIntShortChar(void) { sIntShortChar r; return r; } -// CHECK-RS32: void @retLongInt(ptr noalias sret(%struct.sLongInt) align 8 %agg.result) +// CHECK-RS32: void @retLongInt(ptr dead_on_unwind noalias writable sret(%struct.sLongInt) align 8 %agg.result) // CHECK-RS64: [2 x i64] @retLongInt() sLongInt retLongInt(void) { sLongInt r; return r; } @@ -116,12 +116,12 @@ void argLong2Char(sLong2Char s) {} // 64-bit RenderScript // ============================================================================= -// CHECK-RS32: void @retInt5(ptr noalias sret(%struct.sInt5) align 4 %agg.result) -// CHECK-RS64: void @retInt5(ptr noalias sret(%struct.sInt5) align 4 %agg.result) +// CHECK-RS32: void @retInt5(ptr dead_on_unwind noalias writable sret(%struct.sInt5) align 4 %agg.result) +// CHECK-RS64: void @retInt5(ptr dead_on_unwind noalias writable sret(%struct.sInt5) align 4 %agg.result) sInt5 retInt5(void) { sInt5 r; return r;} -// CHECK-RS32: void @retLong2Char(ptr noalias sret(%struct.sLong2Char) align 8 %agg.result) -// CHECK-RS64: void @retLong2Char(ptr noalias sret(%struct.sLong2Char) align 8 %agg.result) +// CHECK-RS32: void @retLong2Char(ptr dead_on_unwind noalias writable sret(%struct.sLong2Char) align 8 %agg.result) +// CHECK-RS64: void @retLong2Char(ptr dead_on_unwind noalias writable sret(%struct.sLong2Char) align 8 %agg.result) sLong2Char retLong2Char(void) { sLong2Char r; return r;} // ============================================================================= @@ -135,6 +135,6 @@ typedef struct {long l1, l2, l3, l4, l5, l6, l7, l8, l9; } sLong9; // CHECK-RS64: void @argLong9(ptr noundef %s) void argLong9(sLong9 s) {} -// CHECK-RS32: void @retLong9(ptr noalias sret(%struct.sLong9) align 8 %agg.result) -// CHECK-RS64: void @retLong9(ptr noalias sret(%struct.sLong9) align 8 %agg.result) +// CHECK-RS32: void @retLong9(ptr dead_on_unwind noalias writable sret(%struct.sLong9) align 8 %agg.result) +// CHECK-RS64: void @retLong9(ptr dead_on_unwind noalias writable sret(%struct.sLong9) align 8 %agg.result) sLong9 retLong9(void) { sLong9 r; return r; } diff --git a/clang/test/CodeGen/sparcv9-abi.c b/clang/test/CodeGen/sparcv9-abi.c index 2d39c64c1c2c..5e74a9a883ce 100644 --- a/clang/test/CodeGen/sparcv9-abi.c +++ b/clang/test/CodeGen/sparcv9-abi.c @@ -53,7 +53,7 @@ struct large { int x; }; -// CHECK-LABEL: define{{.*}} void @f_large(ptr noalias sret(%struct.large) align 8 %agg.result, ptr noundef %x) +// CHECK-LABEL: define{{.*}} void @f_large(ptr dead_on_unwind noalias writable sret(%struct.large) align 8 %agg.result, ptr noundef %x) struct large f_large(struct large x) { x.a += *x.b; x.b = 0; diff --git a/clang/test/CodeGen/sret.c b/clang/test/CodeGen/sret.c index 548581d3e3dc..6d905e89b2c6 100644 --- a/clang/test/CodeGen/sret.c +++ b/clang/test/CodeGen/sret.c @@ -9,15 +9,15 @@ struct abc { }; struct abc foo1(void); -// CHECK-DAG: declare {{.*}} @foo1(ptr sret(%struct.abc) +// CHECK-DAG: declare {{.*}} @foo1(ptr dead_on_unwind writable sret(%struct.abc) struct abc foo2(); -// CHECK-DAG: declare {{.*}} @foo2(ptr sret(%struct.abc) +// CHECK-DAG: declare {{.*}} @foo2(ptr dead_on_unwind writable sret(%struct.abc) struct abc foo3(void){} -// CHECK-DAG: define {{.*}} @foo3(ptr noalias sret(%struct.abc) +// CHECK-DAG: define {{.*}} @foo3(ptr dead_on_unwind noalias writable sret(%struct.abc) void bar(void) { struct abc dummy1 = foo1(); - // CHECK-DAG: call {{.*}} @foo1(ptr sret(%struct.abc) + // CHECK-DAG: call {{.*}} @foo1(ptr dead_on_unwind writable sret(%struct.abc) struct abc dummy2 = foo2(); - // CHECK-DAG: call {{.*}} @foo2(ptr sret(%struct.abc) + // CHECK-DAG: call {{.*}} @foo2(ptr dead_on_unwind writable sret(%struct.abc) } diff --git a/clang/test/CodeGen/vectorcall.c b/clang/test/CodeGen/vectorcall.c index b5f7efec6751..cb53ecc70351 100644 --- a/clang/test/CodeGen/vectorcall.c +++ b/clang/test/CodeGen/vectorcall.c @@ -90,8 +90,8 @@ struct HVA4 __vectorcall hva6(struct HVA4 a, struct HVA4 b) { return b;} // X64: define dso_local x86_vectorcallcc %struct.HVA4 @"\01hva6@@128"(%struct.HVA4 inreg %a.coerce, ptr noundef %b) struct HVA5 __vectorcall hva7(void) {struct HVA5 a = {}; return a;} -// X86: define dso_local x86_vectorcallcc void @"\01hva7@@0"(ptr inreg noalias sret(%struct.HVA5) align 16 %agg.result) -// X64: define dso_local x86_vectorcallcc void @"\01hva7@@0"(ptr noalias sret(%struct.HVA5) align 16 %agg.result) +// X86: define dso_local x86_vectorcallcc void @"\01hva7@@0"(ptr dead_on_unwind inreg noalias writable sret(%struct.HVA5) align 16 %agg.result) +// X64: define dso_local x86_vectorcallcc void @"\01hva7@@0"(ptr dead_on_unwind noalias writable sret(%struct.HVA5) align 16 %agg.result) v4f32 __vectorcall hva8(v4f32 a, v4f32 b, v4f32 c, v4f32 d, int e, v4f32 f) {return f;} // X86: define dso_local x86_vectorcallcc <4 x float> @"\01hva8@@84"(<4 x float> inreg noundef %a, <4 x float> inreg noundef %b, <4 x float> inreg noundef %c, <4 x float> inreg noundef %d, i32 inreg noundef %e, <4 x float> inreg noundef %f) diff --git a/clang/test/CodeGen/windows-struct-abi.c b/clang/test/CodeGen/windows-struct-abi.c index 4431d91b63ca..5e63c5b3344d 100644 --- a/clang/test/CodeGen/windows-struct-abi.c +++ b/clang/test/CodeGen/windows-struct-abi.c @@ -34,7 +34,7 @@ struct f4 { struct f4 return_f4(void) { while (1); } -// CHECK: define dso_local void @return_f4(ptr noalias sret(%struct.f4) align 4 %agg.result) +// CHECK: define dso_local void @return_f4(ptr dead_on_unwind noalias writable sret(%struct.f4) align 4 %agg.result) void receive_f4(struct f4 a0) { } diff --git a/clang/test/CodeGen/windows-swiftcall.c b/clang/test/CodeGen/windows-swiftcall.c index 3e5c8a4d4b9d..6c138a341835 100644 --- a/clang/test/CodeGen/windows-swiftcall.c +++ b/clang/test/CodeGen/windows-swiftcall.c @@ -20,7 +20,7 @@ SWIFTCALL int indirect_result_2(OUT int *arg0, OUT float *arg1) { __builtin_unr typedef struct { char array[1024]; } struct_reallybig; SWIFTCALL struct_reallybig indirect_result_3(OUT int *arg0, OUT float *arg1) { __builtin_unreachable(); } -// CHECK-LABEL: define {{.*}} void @indirect_result_3(ptr noalias sret({{.*}}) {{.*}}, ptr noalias noundef align 4 dereferenceable(4){{.*}}, ptr noalias noundef align 4 dereferenceable(4){{.*}}) +// CHECK-LABEL: define {{.*}} void @indirect_result_3(ptr dead_on_unwind noalias writable sret({{.*}}) {{.*}}, ptr noalias noundef align 4 dereferenceable(4){{.*}}, ptr noalias noundef align 4 dereferenceable(4){{.*}}) SWIFTCALL void context_1(CONTEXT void *self) {} // CHECK-LABEL: define {{.*}} void @context_1(ptr noundef swiftself @@ -218,7 +218,7 @@ typedef struct { } struct_big_1; TEST(struct_big_1) -// CHECK-LABEL: define {{.*}} void @return_struct_big_1({{.*}} noalias sret +// CHECK-LABEL: define {{.*}} void @return_struct_big_1({{.*}} dead_on_unwind noalias writable sret // Should not be byval. // CHECK-LABEL: define {{.*}} void @take_struct_big_1(ptr noundef{{( %.*)?}}) diff --git a/clang/test/CodeGenCXX/aix-alignment.cpp b/clang/test/CodeGenCXX/aix-alignment.cpp index a8bb95814b1a..d4397f3120ec 100644 --- a/clang/test/CodeGenCXX/aix-alignment.cpp +++ b/clang/test/CodeGenCXX/aix-alignment.cpp @@ -29,7 +29,7 @@ typedef struct D { ~D(){}; } D; -// AIX: define void @_Z3foo1D(ptr noalias sret(%struct.D) align 4 %agg.result, ptr noundef %x) +// AIX: define void @_Z3foo1D(ptr dead_on_unwind noalias writable sret(%struct.D) align 4 %agg.result, ptr noundef %x) // AIX32 call void @llvm.memcpy.p0.p0.i32(ptr align 4 %agg.result, ptr align 4 %x, i32 16, i1 false) // AIX64: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.result, ptr align 4 %x, i64 16, i1 false) D foo(D x) { return x; } diff --git a/clang/test/CodeGenCXX/arm-cc.cpp b/clang/test/CodeGenCXX/arm-cc.cpp index 967d10096f72..68e1b7e4e1e4 100644 --- a/clang/test/CodeGenCXX/arm-cc.cpp +++ b/clang/test/CodeGenCXX/arm-cc.cpp @@ -16,5 +16,5 @@ void baz() { zed(a); } -// CHECK: declare void @_Z3fooPv(ptr sret(%class.SMLoc) align 4, ptr noundef) +// CHECK: declare void @_Z3fooPv(ptr dead_on_unwind writable sret(%class.SMLoc) align 4, ptr noundef) // CHECK: declare void @_Z3zed5SMLoc(ptr noundef) diff --git a/clang/test/CodeGenCXX/arm-swiftcall.cpp b/clang/test/CodeGenCXX/arm-swiftcall.cpp index 687e4c8b4dcb..e60c1482700a 100644 --- a/clang/test/CodeGenCXX/arm-swiftcall.cpp +++ b/clang/test/CodeGenCXX/arm-swiftcall.cpp @@ -105,7 +105,7 @@ struct struct_indirect_1 { }; TEST(struct_indirect_1) -// CHECK-LABEL: define {{.*}} void @return_struct_indirect_1({{.*}} noalias sret +// CHECK-LABEL: define {{.*}} void @return_struct_indirect_1({{.*}} dead_on_unwind noalias writable sret // Should not be byval. // CHECK-LABEL: define {{.*}} void @take_struct_indirect_1(ptr noundef{{( %.*)?}}) diff --git a/clang/test/CodeGenCXX/attr-musttail.cpp b/clang/test/CodeGenCXX/attr-musttail.cpp index b8a1961d5eb7..720e50c5a240 100644 --- a/clang/test/CodeGenCXX/attr-musttail.cpp +++ b/clang/test/CodeGenCXX/attr-musttail.cpp @@ -162,7 +162,7 @@ HasNonTrivialCopyConstructor TestNonElidableCopyConstructor() { [[clang::musttail]] return (((ReturnsClassByValue()))); } -// CHECK: musttail call void @_Z19ReturnsClassByValuev(ptr sret(%struct.HasNonTrivialCopyConstructor) align 1 %agg.result) +// CHECK: musttail call void @_Z19ReturnsClassByValuev(ptr dead_on_unwind writable sret(%struct.HasNonTrivialCopyConstructor) align 1 %agg.result) struct HasNonTrivialCopyConstructor2 { // Copy constructor works even if it has extra default params. @@ -191,8 +191,8 @@ LargeWithCopyConstructor TestLargeWithCopyConstructor() { [[clang::musttail]] return ReturnsLarge(); } -// CHECK: define dso_local void @_Z28TestLargeWithCopyConstructorv(ptr noalias sret(%struct.LargeWithCopyConstructor) align 1 %agg.result) -// CHECK: musttail call void @_Z12ReturnsLargev(ptr sret(%struct.LargeWithCopyConstructor) align 1 %agg.result) +// CHECK: define dso_local void @_Z28TestLargeWithCopyConstructorv(ptr dead_on_unwind noalias writable sret(%struct.LargeWithCopyConstructor) align 1 %agg.result) +// CHECK: musttail call void @_Z12ReturnsLargev(ptr dead_on_unwind writable sret(%struct.LargeWithCopyConstructor) align 1 %agg.result) using IntFunctionType = int(); IntFunctionType *ReturnsIntFunction(); diff --git a/clang/test/CodeGenCXX/call-with-static-chain.cpp b/clang/test/CodeGenCXX/call-with-static-chain.cpp index 06c3f15396a8..61011a65e4a2 100644 --- a/clang/test/CodeGenCXX/call-with-static-chain.cpp +++ b/clang/test/CodeGenCXX/call-with-static-chain.cpp @@ -25,8 +25,8 @@ void test() { // CHECK64: call i32 @f1(ptr nest noundef @f1 __builtin_call_with_static_chain(f1(a, a, a, a), f1); - // CHECK32: call void @f2(ptr sret(%struct.B) align 4 %{{[0-9a-z]+}}, ptr nest noundef @f2) - // CHECK64: call void @f2(ptr sret(%struct.B) align 8 %{{[0-9a-z]+}}, ptr nest noundef @f2) + // CHECK32: call void @f2(ptr dead_on_unwind writable sret(%struct.B) align 4 %{{[0-9a-z]+}}, ptr nest noundef @f2) + // CHECK64: call void @f2(ptr dead_on_unwind writable sret(%struct.B) align 8 %{{[0-9a-z]+}}, ptr nest noundef @f2) __builtin_call_with_static_chain(f2(), f2); // CHECK32: call i64 @f3(ptr nest noundef @f3) diff --git a/clang/test/CodeGenCXX/conditional-gnu-ext.cpp b/clang/test/CodeGenCXX/conditional-gnu-ext.cpp index b17e0f7bb9a2..3d3d210f22f6 100644 --- a/clang/test/CodeGenCXX/conditional-gnu-ext.cpp +++ b/clang/test/CodeGenCXX/conditional-gnu-ext.cpp @@ -94,7 +94,7 @@ namespace test3 { B test1() { // CHECK-LABEL: define{{.*}} void @_ZN5test35test1Ev( // CHECK: [[TEMP:%.*]] = alloca [[B:%.*]], - // CHECK: call void @_ZN5test312test1_helperEv(ptr sret([[B]]) align 1 [[TEMP]]) + // CHECK: call void @_ZN5test312test1_helperEv(ptr dead_on_unwind writable sret([[B]]) align 1 [[TEMP]]) // CHECK-NEXT: [[BOOL:%.*]] = call noundef zeroext i1 @_ZN5test31BcvbEv(ptr {{[^,]*}} [[TEMP]]) // CHECK-NEXT: br i1 [[BOOL]] // CHECK: call void @_ZN5test31BC1ERKS0_(ptr {{[^,]*}} [[RESULT:%.*]], ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[TEMP]]) @@ -117,7 +117,7 @@ namespace test3 { // CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[X]] // CHECK-NEXT: [[BOOL:%.*]] = call noundef zeroext i1 @_ZN5test31BcvbEv(ptr {{[^,]*}} [[T0]]) // CHECK-NEXT: br i1 [[BOOL]] - // CHECK: call void @_ZN5test31BcvNS_1AEEv(ptr sret([[A:%.*]]) align 1 [[RESULT:%.*]], ptr {{[^,]*}} [[T0]]) + // CHECK: call void @_ZN5test31BcvNS_1AEEv(ptr dead_on_unwind writable sret([[A:%.*]]) align 1 [[RESULT:%.*]], ptr {{[^,]*}} [[T0]]) // CHECK-NEXT: br label // CHECK: call void @_ZN5test31AC1Ev(ptr {{[^,]*}} [[RESULT]]) // CHECK-NEXT: br label @@ -128,10 +128,10 @@ namespace test3 { A test3() { // CHECK-LABEL: define{{.*}} void @_ZN5test35test3Ev( // CHECK: [[TEMP:%.*]] = alloca [[B]], - // CHECK: call void @_ZN5test312test3_helperEv(ptr sret([[B]]) align 1 [[TEMP]]) + // CHECK: call void @_ZN5test312test3_helperEv(ptr dead_on_unwind writable sret([[B]]) align 1 [[TEMP]]) // CHECK-NEXT: [[BOOL:%.*]] = call noundef zeroext i1 @_ZN5test31BcvbEv(ptr {{[^,]*}} [[TEMP]]) // CHECK-NEXT: br i1 [[BOOL]] - // CHECK: call void @_ZN5test31BcvNS_1AEEv(ptr sret([[A]]) align 1 [[RESULT:%.*]], ptr {{[^,]*}} [[TEMP]]) + // CHECK: call void @_ZN5test31BcvNS_1AEEv(ptr dead_on_unwind writable sret([[A]]) align 1 [[RESULT:%.*]], ptr {{[^,]*}} [[TEMP]]) // CHECK-NEXT: br label // CHECK: call void @_ZN5test31AC1Ev(ptr {{[^,]*}} [[RESULT]]) // CHECK-NEXT: br label diff --git a/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp b/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp index db6671bcd301..e64d163fd3d6 100644 --- a/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp +++ b/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp @@ -19,7 +19,7 @@ void g() { // CHECK: %[[A:.*]] = alloca // CHECK-NOT: alloca // CHECK-NOT: call - // CHECK: call {{.*}} @_Z1fv(ptr sret({{.*}}) align 4 %[[A]]) + // CHECK: call {{.*}} @_Z1fv(ptr dead_on_unwind writable sret({{.*}}) align 4 %[[A]]) A a = A( A{ f() } ); // CHECK-NOT: call @@ -40,7 +40,7 @@ void h() { // CHECK-NOT: alloca // CHECK-NOT: call - // CHECK: call {{.*}} @_Z1fv(ptr sret({{.*}}) align 4 %[[A]]) + // CHECK: call {{.*}} @_Z1fv(ptr dead_on_unwind writable sret({{.*}}) align 4 %[[A]]) // CHECK-NOT: call // CHECK: call {{.*}} @_Z1f1A(ptr noundef %[[A]]) f(f()); diff --git a/clang/test/CodeGenCXX/cxx1z-lambda-star-this.cpp b/clang/test/CodeGenCXX/cxx1z-lambda-star-this.cpp index 63bfe5603b69..1388f1b87889 100644 --- a/clang/test/CodeGenCXX/cxx1z-lambda-star-this.cpp +++ b/clang/test/CodeGenCXX/cxx1z-lambda-star-this.cpp @@ -10,7 +10,7 @@ namespace ns1 { int X = A{}.foo()(); } //end ns1 -//CHECK: @"?foo@A@@QAE?A?@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%class.anon) align 8 %[[A_LAMBDA_RETVAL:.*]]) +//CHECK: @"?foo@A@@QAE?A?@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%class.anon) align 8 %[[A_LAMBDA_RETVAL:.*]]) // get the first object with the closure type, which is of type 'struct.A' //CHECK: %[[I0:.+]] = getelementptr inbounds %[[A_LAMBDA]], ptr %[[A_LAMBDA_RETVAL]], i32 0, i32 0 // copy the contents ... @@ -24,6 +24,6 @@ struct B { namespace ns2 { int X = B{}.bar()(); } -//CHECK: @"?bar@B@@QAE?A?@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%class.anon.0) align 4 %agg.result) +//CHECK: @"?bar@B@@QAE?A?@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%class.anon.0) align 4 %agg.result) //CHECK: %[[I20:.+]] = getelementptr inbounds %class.anon.0, ptr %agg.result, i32 0, i32 0 //CHECK: store ptr %this1, ptr %[[I20]], align 4 diff --git a/clang/test/CodeGenCXX/exceptions.cpp b/clang/test/CodeGenCXX/exceptions.cpp index 483876cc212e..e8179f9828fb 100644 --- a/clang/test/CodeGenCXX/exceptions.cpp +++ b/clang/test/CodeGenCXX/exceptions.cpp @@ -142,12 +142,12 @@ namespace test1 { // CHECK: [[ACTIVE:%.*]] = alloca i1 // CHECK: [[NEW:%.*]] = call noalias nonnull ptr @_Znwm(i64 8) // CHECK-NEXT: store i1 true, ptr [[ACTIVE]] - // CHECK-NEXT: invoke void @_ZN5test15makeBEv(ptr sret([[B:%.*]]) align 4 [[T0:%.*]]) + // CHECK-NEXT: invoke void @_ZN5test15makeBEv(ptr dead_on_unwind writable sret([[B:%.*]]) align 4 [[T0:%.*]]) // CHECK: [[T1:%.*]] = invoke i32 @_ZN5test11BcviEv(ptr {{[^,]*}} [[T0]]) // CHECK: invoke void @_ZN5test11AC1Ei(ptr {{[^,]*}} [[NEW]], i32 [[T1]]) // CHECK: store i1 false, ptr [[ACTIVE]] // CHECK-NEXT: store ptr [[NEW]], ptr [[X]], align 8 - // CHECK: invoke void @_ZN5test15makeBEv(ptr sret([[B:%.*]]) align 4 [[T2:%.*]]) + // CHECK: invoke void @_ZN5test15makeBEv(ptr dead_on_unwind writable sret([[B:%.*]]) align 4 [[T2:%.*]]) // CHECK: [[RET:%.*]] = load ptr, ptr [[X]], align 8 // CHECK98: invoke void @_ZN5test11BD1Ev(ptr {{[^,]*}} [[T2]]) @@ -231,7 +231,7 @@ namespace test3 { // CHECK-NEXT: store ptr [[NEW]], ptr [[SAVED0]] // CHECK-NEXT: store ptr [[FOO]], ptr [[SAVED1]] // CHECK-NEXT: store i1 true, ptr [[CLEANUPACTIVE]] - // CHECK-NEXT: invoke void @_ZN5test35makeAEv(ptr sret([[A:%.*]]) align 8 [[NEW]]) + // CHECK-NEXT: invoke void @_ZN5test35makeAEv(ptr dead_on_unwind writable sret([[A:%.*]]) align 8 [[NEW]]) // CHECK: br label // -> cond.end new(foo(),10.0) A(makeA()) : diff --git a/clang/test/CodeGenCXX/homogeneous-aggregates.cpp b/clang/test/CodeGenCXX/homogeneous-aggregates.cpp index bd83b9f932aa..63ffc6b5bfac 100644 --- a/clang/test/CodeGenCXX/homogeneous-aggregates.cpp +++ b/clang/test/CodeGenCXX/homogeneous-aggregates.cpp @@ -39,10 +39,10 @@ struct I2 : Base2 {}; struct I3 : Base2 {}; struct D5 : I1, I2, I3 {}; // homogeneous aggregate -// PPC: define{{.*}} void @_Z7func_D12D1(ptr noalias sret(%struct.D1) align 8 %agg.result, [3 x i64] %x.coerce) -// ARM32: define{{.*}} arm_aapcs_vfpcc void @_Z7func_D12D1(ptr noalias sret(%struct.D1) align 8 %agg.result, [3 x i64] %x.coerce) -// ARM64: define{{.*}} void @_Z7func_D12D1(ptr noalias sret(%struct.D1) align 8 %agg.result, ptr noundef %x) -// X64: define dso_local x86_vectorcallcc void @"\01_Z7func_D12D1@@24"(ptr noalias sret(%struct.D1) align 8 %agg.result, ptr noundef %x) +// PPC: define{{.*}} void @_Z7func_D12D1(ptr dead_on_unwind noalias writable sret(%struct.D1) align 8 %agg.result, [3 x i64] %x.coerce) +// ARM32: define{{.*}} arm_aapcs_vfpcc void @_Z7func_D12D1(ptr dead_on_unwind noalias writable sret(%struct.D1) align 8 %agg.result, [3 x i64] %x.coerce) +// ARM64: define{{.*}} void @_Z7func_D12D1(ptr dead_on_unwind noalias writable sret(%struct.D1) align 8 %agg.result, ptr noundef %x) +// X64: define dso_local x86_vectorcallcc void @"\01_Z7func_D12D1@@24"(ptr dead_on_unwind noalias writable sret(%struct.D1) align 8 %agg.result, ptr noundef %x) D1 CC func_D1(D1 x) { return x; } // PPC: define{{.*}} [3 x double] @_Z7func_D22D2([3 x double] %x.coerce) @@ -51,9 +51,9 @@ D1 CC func_D1(D1 x) { return x; } // X64: define dso_local x86_vectorcallcc %struct.D2 @"\01_Z7func_D22D2@@24"(%struct.D2 inreg %x.coerce) D2 CC func_D2(D2 x) { return x; } -// PPC: define{{.*}} void @_Z7func_D32D3(ptr noalias sret(%struct.D3) align 8 %agg.result, [4 x i64] %x.coerce) -// ARM32: define{{.*}} arm_aapcs_vfpcc void @_Z7func_D32D3(ptr noalias sret(%struct.D3) align 8 %agg.result, [4 x i64] %x.coerce) -// ARM64: define{{.*}} void @_Z7func_D32D3(ptr noalias sret(%struct.D3) align 8 %agg.result, ptr noundef %x) +// PPC: define{{.*}} void @_Z7func_D32D3(ptr dead_on_unwind noalias writable sret(%struct.D3) align 8 %agg.result, [4 x i64] %x.coerce) +// ARM32: define{{.*}} arm_aapcs_vfpcc void @_Z7func_D32D3(ptr dead_on_unwind noalias writable sret(%struct.D3) align 8 %agg.result, [4 x i64] %x.coerce) +// ARM64: define{{.*}} void @_Z7func_D32D3(ptr dead_on_unwind noalias writable sret(%struct.D3) align 8 %agg.result, ptr noundef %x) D3 CC func_D3(D3 x) { return x; } // PPC: define{{.*}} [4 x double] @_Z7func_D42D4([4 x double] %x.coerce) @@ -133,13 +133,13 @@ struct HasEmptyBase : public Empty { struct HasPodBase : public Pod {}; // WOA64-LABEL: define dso_local %"struct.pr47611::Pod" @"?copy@pr47611@@YA?AUPod@1@PEAU21@@Z"(ptr noundef %x) Pod copy(Pod *x) { return *x; } // MSVC: ldp d0,d1,[x0], Clang: ldp d0,d1,[x0] -// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(ptr inreg noalias sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %agg.result, ptr noundef %x) +// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(ptr dead_on_unwind inreg noalias writable sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %agg.result, ptr noundef %x) NotCXX14Aggregate copy(NotCXX14Aggregate *x) { return *x; } // MSVC: stp x8,x9,[x0], Clang: str q0,[x0] // WOA64-LABEL: define dso_local [2 x i64] @"?copy@pr47611@@YA?AUNotPod@1@PEAU21@@Z"(ptr noundef %x) NotPod copy(NotPod *x) { return *x; } -// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(ptr inreg noalias sret(%"struct.pr47611::HasEmptyBase") align 8 %agg.result, ptr noundef %x) +// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(ptr dead_on_unwind inreg noalias writable sret(%"struct.pr47611::HasEmptyBase") align 8 %agg.result, ptr noundef %x) HasEmptyBase copy(HasEmptyBase *x) { return *x; } -// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(ptr inreg noalias sret(%"struct.pr47611::HasPodBase") align 8 %agg.result, ptr noundef %x) +// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(ptr dead_on_unwind inreg noalias writable sret(%"struct.pr47611::HasPodBase") align 8 %agg.result, ptr noundef %x) HasPodBase copy(HasPodBase *x) { return *x; } void call_copy_pod(Pod *pod) { @@ -151,7 +151,7 @@ void call_copy_pod(Pod *pod) { void call_copy_notcxx14aggregate(NotCXX14Aggregate *notcxx14aggregate) { *notcxx14aggregate = copy(notcxx14aggregate); // WOA64-LABEL: define dso_local void @"?call_copy_notcxx14aggregate@pr47611@@YAXPEAUNotCXX14Aggregate@1@@Z" - // WOA64: call void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(ptr inreg sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %{{.*}}, ptr noundef %{{.*}}) + // WOA64: call void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(ptr dead_on_unwind inreg writable sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %{{.*}}, ptr noundef %{{.*}}) } void call_copy_notpod(NotPod *notPod) { @@ -163,13 +163,13 @@ void call_copy_notpod(NotPod *notPod) { void call_copy_hasemptybase(HasEmptyBase *hasEmptyBase) { *hasEmptyBase = copy(hasEmptyBase); // WOA64-LABEL: define dso_local void @"?call_copy_hasemptybase@pr47611@@YAXPEAUHasEmptyBase@1@@Z" - // WOA64: call void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(ptr inreg sret(%"struct.pr47611::HasEmptyBase") align 8 %{{.*}}, ptr noundef %{{.*}}) + // WOA64: call void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(ptr dead_on_unwind inreg writable sret(%"struct.pr47611::HasEmptyBase") align 8 %{{.*}}, ptr noundef %{{.*}}) } void call_copy_haspodbase(HasPodBase *hasPodBase) { *hasPodBase = copy(hasPodBase); // WOA64-LABEL: define dso_local void @"?call_copy_haspodbase@pr47611@@YAXPEAUHasPodBase@1@@Z" - // WOA64: call void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(ptr inreg sret(%"struct.pr47611::HasPodBase") align 8 %{{.*}}, ptr noundef %{{.*}}) + // WOA64: call void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(ptr dead_on_unwind inreg writable sret(%"struct.pr47611::HasPodBase") align 8 %{{.*}}, ptr noundef %{{.*}}) } } // namespace pr47611 @@ -300,5 +300,5 @@ test f(test *x) { return *x; } struct base2 { double v; }; struct test2 : base2 { test2(double); protected: double v2;}; test2 f(test2 *x) { return *x; } -// WOA64: define dso_local void @"?f@pr62223@@YA?AUtest2@1@PEAU21@@Z"(ptr inreg noalias sret(%"struct.pr62223::test2") align 8 %{{.*}}, ptr noundef %{{.*}}) +// WOA64: define dso_local void @"?f@pr62223@@YA?AUtest2@1@PEAU21@@Z"(ptr dead_on_unwind inreg noalias writable sret(%"struct.pr62223::test2") align 8 %{{.*}}, ptr noundef %{{.*}}) } diff --git a/clang/test/CodeGenCXX/lambda-expressions.cpp b/clang/test/CodeGenCXX/lambda-expressions.cpp index 3ad982a195cc..b929aa0c6751 100644 --- a/clang/test/CodeGenCXX/lambda-expressions.cpp +++ b/clang/test/CodeGenCXX/lambda-expressions.cpp @@ -193,8 +193,8 @@ namespace pr28595 { // CHECK-NEXT: call noundef i32 @"_ZZ1fvENK3$_0clEii" // CHECK-NEXT: ret i32 -// CHECK-LABEL: define internal void @"_ZZ1hvEN3$_08__invokeEv"(ptr noalias sret(%struct.A) align 1 %agg.result) {{.*}} { -// CHECK: call void @"_ZZ1hvENK3$_0clEv"(ptr sret(%struct.A) align 1 %agg.result, +// CHECK-LABEL: define internal void @"_ZZ1hvEN3$_08__invokeEv"(ptr dead_on_unwind noalias writable sret(%struct.A) align 1 %agg.result) {{.*}} { +// CHECK: call void @"_ZZ1hvENK3$_0clEv"(ptr dead_on_unwind writable sret(%struct.A) align 1 %agg.result, // CHECK-NEXT: ret void struct A { ~A(); }; void h() { diff --git a/clang/test/CodeGenCXX/matrix-casts.cpp b/clang/test/CodeGenCXX/matrix-casts.cpp index 4369d99a3491..0a946e464ade 100644 --- a/clang/test/CodeGenCXX/matrix-casts.cpp +++ b/clang/test/CodeGenCXX/matrix-casts.cpp @@ -324,7 +324,7 @@ public: }; Foo class_constructor_matrix_ty(matrix_5_5 m) { - // CHECK-LABEL: define void @_Z27class_constructor_matrix_tyu11matrix_typeILm5ELm5EiE(ptr noalias sret(%class.Foo) align 4 %agg.result, <25 x i32> noundef %m) + // CHECK-LABEL: define void @_Z27class_constructor_matrix_tyu11matrix_typeILm5ELm5EiE(ptr dead_on_unwind noalias writable sret(%class.Foo) align 4 %agg.result, <25 x i32> noundef %m) // CHECK: [[M:%.*]] = load <25 x i32>, ptr {{.*}}, align 4 // CHECK-NEXT: call void @_ZN3FooC1Eu11matrix_typeILm5ELm5EiE(ptr noundef nonnull align 4 dereferenceable(40) %agg.result, <25 x i32> noundef [[M]]) // CHECK-NEXT: ret void @@ -338,7 +338,7 @@ struct Bar { }; Bar struct_constructor_matrix_ty(matrix_4_4 m) { - // CHECK-LABEL: define void @_Z28struct_constructor_matrix_tyu11matrix_typeILm4ELm4EfE(ptr noalias sret(%struct.Bar) align 4 %agg.result, <16 x float> noundef %m) + // CHECK-LABEL: define void @_Z28struct_constructor_matrix_tyu11matrix_typeILm4ELm4EfE(ptr dead_on_unwind noalias writable sret(%struct.Bar) align 4 %agg.result, <16 x float> noundef %m) // CHECK: [[M:%.*]] = load <16 x float>, ptr {{.*}}, align 4 // CHECK-NEXT: call void @_ZN3BarC1Eu11matrix_typeILm4ELm4EfE(ptr noundef nonnull align 4 dereferenceable(40) %agg.result, <16 x float> noundef [[M]]) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenCXX/matrix-type-builtins.cpp b/clang/test/CodeGenCXX/matrix-type-builtins.cpp index 732fe1a18db3..9c334a6858f1 100644 --- a/clang/test/CodeGenCXX/matrix-type-builtins.cpp +++ b/clang/test/CodeGenCXX/matrix-type-builtins.cpp @@ -19,7 +19,7 @@ MyMatrix transpose(const MyMatrix &M) { void test_transpose_template1() { // CHECK-LABEL: define{{.*}} void @_Z24test_transpose_template1v() - // CHECK: call void @_Z9transposeIiLj4ELj10EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr sret(%struct.MyMatrix.0) align 4 %M1_t, ptr noundef nonnull align 4 dereferenceable(160) %M1) + // CHECK: call void @_Z9transposeIiLj4ELj10EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr dead_on_unwind writable sret(%struct.MyMatrix.0) align 4 %M1_t, ptr noundef nonnull align 4 dereferenceable(160) %M1) // CHECK-LABEL: define linkonce_odr void @_Z9transposeIiLj4ELj10EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE( // CHECK: [[M:%.*]] = load <40 x i32>, ptr {{.*}}, align 4 @@ -31,9 +31,9 @@ void test_transpose_template1() { void test_transpose_template2(MyMatrix &M) { // CHECK-LABEL: define{{.*}} void @_Z24test_transpose_template2R8MyMatrixIdLj7ELj6EE( - // CHECK: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr sret(%struct.MyMatrix.1) align 8 %ref.tmp1, ptr noundef nonnull align 8 dereferenceable(336) %0) - // CHECK-NEXT: call void @_Z9transposeIdLj6ELj7EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr sret(%struct.MyMatrix.2) align 8 %ref.tmp, ptr noundef nonnull align 8 dereferenceable(336) %ref.tmp1) - // CHECK-NEXT: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr sret(%struct.MyMatrix.1) align 8 %M2_t, ptr noundef nonnull align 8 dereferenceable(336) %ref.tmp) + // CHECK: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr dead_on_unwind writable sret(%struct.MyMatrix.1) align 8 %ref.tmp1, ptr noundef nonnull align 8 dereferenceable(336) %0) + // CHECK-NEXT: call void @_Z9transposeIdLj6ELj7EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr dead_on_unwind writable sret(%struct.MyMatrix.2) align 8 %ref.tmp, ptr noundef nonnull align 8 dereferenceable(336) %ref.tmp1) + // CHECK-NEXT: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(ptr dead_on_unwind writable sret(%struct.MyMatrix.1) align 8 %M2_t, ptr noundef nonnull align 8 dereferenceable(336) %ref.tmp) // CHECK-LABEL: define linkonce_odr void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE( // CHECK: [[M:%.*]] = load <42 x double>, ptr {{.*}}, align 8 diff --git a/clang/test/CodeGenCXX/matrix-type.cpp b/clang/test/CodeGenCXX/matrix-type.cpp index 79bceabb115f..d93db29d4d0a 100644 --- a/clang/test/CodeGenCXX/matrix-type.cpp +++ b/clang/test/CodeGenCXX/matrix-type.cpp @@ -127,7 +127,7 @@ void matrix_template_reference(MatrixClassTemplate &a, MatrixCla } MatrixClassTemplate matrix_template_reference_caller(float *Data) { - // CHECK-LABEL: define{{.*}} void @_Z32matrix_template_reference_callerPf(ptr noalias sret(%class.MatrixClassTemplate) align 8 %agg.result, ptr %Data + // CHECK-LABEL: define{{.*}} void @_Z32matrix_template_reference_callerPf(ptr dead_on_unwind noalias writable sret(%class.MatrixClassTemplate) align 8 %agg.result, ptr %Data // CHECK-NEXT: entry: // CHECK-NEXT: %Data.addr = alloca ptr, align 8 // CHECK-NEXT: %Arg = alloca %class.MatrixClassTemplate, align 8 diff --git a/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp b/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp index fde27c6ce85d..668a27e9d262 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp @@ -49,7 +49,7 @@ A B::qux(A x) { } // CHECK-LABEL: define dso_local x86_fastcallcc void @"?qux@B@@QAI?AUA@@U2@@Z" -// CHECK: (ptr inreg noundef %this, ptr inreg noalias sret(%struct.A) align 4 %agg.result, ptr inalloca(<{ %struct.A }>) %0) +// CHECK: (ptr inreg noundef %this, ptr dead_on_unwind inreg noalias writable sret(%struct.A) align 4 %agg.result, ptr inalloca(<{ %struct.A }>) %0) // CHECK: ret void int main() { @@ -67,4 +67,4 @@ int main() { // CHECK: call x86_stdcallcc ptr @"?baz@B@@QAG?AUA@@U2@@Z" // CHECK: (ptr inalloca(<{ ptr, ptr, %struct.A }>) %{{[^,]*}}) // CHECK: call x86_fastcallcc void @"?qux@B@@QAI?AUA@@U2@@Z" -// CHECK: (ptr inreg noundef %{{[^,]*}}, ptr inreg sret(%struct.A) align 4 %{{.*}}, ptr inalloca(<{ %struct.A }>) %{{[^,]*}}) +// CHECK: (ptr inreg noundef %{{[^,]*}}, ptr dead_on_unwind inreg writable sret(%struct.A) align 4 %{{.*}}, ptr inalloca(<{ %struct.A }>) %{{[^,]*}}) diff --git a/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp b/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp index 66ecf500a869..4c485fc3142a 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp @@ -86,10 +86,10 @@ C::C() {} // force emission // CHECK32-NEXT: ret ptr %[[rv]] // CHECK64-LABEL: define linkonce_odr dso_local void @"?foo@C@sret_thunk@@W7EAA?AUAgg@2@U32@@Z" -// CHECK64: (ptr noundef %this, ptr noalias sret(%"struct.sret_thunk::Agg") align 4 %agg.result, ptr noundef %x) +// CHECK64: (ptr noundef %this, ptr dead_on_unwind noalias writable sret(%"struct.sret_thunk::Agg") align 4 %agg.result, ptr noundef %x) // CHECK64: getelementptr i8, ptr %{{.*}}, i32 -8 // CHECK64: call void @"?foo@C@sret_thunk@@UEAA?AUAgg@2@U32@@Z" -// CHECK64: (ptr {{[^,]*}} %{{.*}}, ptr sret(%"struct.sret_thunk::Agg") align 4 %agg.result, ptr noundef %x) +// CHECK64: (ptr {{[^,]*}} %{{.*}}, ptr dead_on_unwind writable sret(%"struct.sret_thunk::Agg") align 4 %agg.result, ptr noundef %x) // CHECK64-NOT: call // CHECK64: ret void } diff --git a/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp b/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp index b4a6ff8e6d0f..a1faab25b109 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp @@ -19,9 +19,9 @@ S C::variadic_sret(const char *f, ...) { return S(); } S C::cdecl_sret() { return S(); } S C::byval_and_sret(S a) { return S(); } -// CHECK: define dso_local void @"?variadic_sret@C@@QAA?AUS@@PBDZZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.S) align 4 %agg.result, ptr noundef %f, ...) -// CHECK: define dso_local void @"?cdecl_sret@C@@QAA?AUS@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.S) align 4 %agg.result) -// CHECK: define dso_local void @"?byval_and_sret@C@@QAA?AUS@@U2@@Z"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.S) align 4 %agg.result, ptr noundef byval(%struct.S) align 4 %a) +// CHECK: define dso_local void @"?variadic_sret@C@@QAA?AUS@@PBDZZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.S) align 4 %agg.result, ptr noundef %f, ...) +// CHECK: define dso_local void @"?cdecl_sret@C@@QAA?AUS@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.S) align 4 %agg.result) +// CHECK: define dso_local void @"?byval_and_sret@C@@QAA?AUS@@U2@@Z"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.S) align 4 %agg.result, ptr noundef byval(%struct.S) align 4 %a) int main() { C c; @@ -41,4 +41,4 @@ struct A { S A::f(int x) { return S(); } -// CHECK-LABEL: define dso_local x86_fastcallcc void @"?f@A@@QAI?AUS@@H@Z"(ptr inreg noundef nonnull align 1 dereferenceable(1) %this, ptr inreg noalias sret(%struct.S) align 4 %agg.result, i32 noundef %x) +// CHECK-LABEL: define dso_local x86_fastcallcc void @"?f@A@@QAI?AUS@@H@Z"(ptr inreg noundef nonnull align 1 dereferenceable(1) %this, ptr dead_on_unwind inreg noalias writable sret(%struct.S) align 4 %agg.result, i32 noundef %x) diff --git a/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp b/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp index 4bff7ccf8986..f00cf9076275 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp @@ -18,9 +18,9 @@ void HasEHCleanup() { // WIN32-LABEL: define dso_local void @"?HasEHCleanup@@YAXXZ"() {{.*}} { // WIN32: %[[base:.*]] = call ptr @llvm.stacksave.p0() // If this call throws, we have to restore the stack. -// WIN32: call void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) +// WIN32: call void @"?getA@@YA?AUA@@XZ"(ptr dead_on_unwind writable sret(%struct.A) align 4 %{{.*}}) // If this call throws, we have to cleanup the first temporary. -// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) +// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr dead_on_unwind writable sret(%struct.A) align 4 %{{.*}}) // If this call throws, we have to cleanup the stacksave. // WIN32: call noundef i32 @"?TakesTwo@@YAHUA@@0@Z" // WIN32: call void @llvm.stackrestore @@ -42,8 +42,8 @@ void HasEHCleanupNoexcept() noexcept { // With exceptions, we need to clean up at least one of these temporaries. // WIN32-LABEL: define dso_local void @"?HasEHCleanupNoexcept@@YAXXZ"() {{.*}} { // WIN32: %[[base:.*]] = call ptr @llvm.stacksave.p0() -// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) -// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) +// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr dead_on_unwind writable sret(%struct.A) align 4 %{{.*}}) +// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr dead_on_unwind writable sret(%struct.A) align 4 %{{.*}}) // WIN32: invoke noundef i32 @"?TakesTwo@@YAHUA@@0@Z" // WIN32: call void @llvm.stackrestore // WIN32: ret void diff --git a/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp b/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp index 9d737e3979dd..585167d0a142 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp @@ -87,58 +87,58 @@ void call_bools_and_chars() { // Returning structs that fit into a register. Small small_return() { return Small(); } -// LINUX-LABEL: define{{.*}} void @_Z12small_returnv(ptr noalias sret(%struct.Small) align 4 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z12small_returnv(ptr dead_on_unwind noalias writable sret(%struct.Small) align 4 %agg.result) // WIN32: define dso_local i32 @"?small_return@@YA?AUSmall@@XZ"() // WIN64: define dso_local i32 @"?small_return@@YA?AUSmall@@XZ"() // WOA64: define dso_local i32 @"?small_return@@YA?AUSmall@@XZ"() Medium medium_return() { return Medium(); } -// LINUX-LABEL: define{{.*}} void @_Z13medium_returnv(ptr noalias sret(%struct.Medium) align 4 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z13medium_returnv(ptr dead_on_unwind noalias writable sret(%struct.Medium) align 4 %agg.result) // WIN32: define dso_local i64 @"?medium_return@@YA?AUMedium@@XZ"() // WIN64: define dso_local i64 @"?medium_return@@YA?AUMedium@@XZ"() // WOA64: define dso_local i64 @"?medium_return@@YA?AUMedium@@XZ"() // Returning structs that fit into a register but are not POD. SmallCpp11NotCpp03Pod small_non_pod_return() { return SmallCpp11NotCpp03Pod(); } -// LINUX-LABEL: define{{.*}} void @_Z20small_non_pod_returnv(ptr noalias sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) -// WIN32: define dso_local void @"?small_non_pod_return@@YA?AUSmallCpp11NotCpp03Pod@@XZ"(ptr noalias sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) -// WIN64: define dso_local void @"?small_non_pod_return@@YA?AUSmallCpp11NotCpp03Pod@@XZ"(ptr noalias sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) -// WOA64: define dso_local void @"?small_non_pod_return@@YA?AUSmallCpp11NotCpp03Pod@@XZ"(ptr inreg noalias sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z20small_non_pod_returnv(ptr dead_on_unwind noalias writable sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) +// WIN32: define dso_local void @"?small_non_pod_return@@YA?AUSmallCpp11NotCpp03Pod@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) +// WIN64: define dso_local void @"?small_non_pod_return@@YA?AUSmallCpp11NotCpp03Pod@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) +// WOA64: define dso_local void @"?small_non_pod_return@@YA?AUSmallCpp11NotCpp03Pod@@XZ"(ptr dead_on_unwind inreg noalias writable sret(%struct.SmallCpp11NotCpp03Pod) align 4 %agg.result) SmallWithCtor small_with_ctor_return() { return SmallWithCtor(); } -// LINUX-LABEL: define{{.*}} void @_Z22small_with_ctor_returnv(ptr noalias sret(%struct.SmallWithCtor) align 4 %agg.result) -// WIN32: define dso_local void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr noalias sret(%struct.SmallWithCtor) align 4 %agg.result) -// WIN64: define dso_local void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr noalias sret(%struct.SmallWithCtor) align 4 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z22small_with_ctor_returnv(ptr dead_on_unwind noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) +// WIN32: define dso_local void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) +// WIN64: define dso_local void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) // FIXME: The 'sret' mark here doesn't seem to be enough to convince LLVM to // preserve the hidden sret pointer in R0 across the function. -// WOA: define dso_local arm_aapcs_vfpcc void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr noalias sret(%struct.SmallWithCtor) align 4 %agg.result) -// WOA64: define dso_local void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr inreg noalias sret(%struct.SmallWithCtor) align 4 %agg.result) +// WOA: define dso_local arm_aapcs_vfpcc void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) +// WOA64: define dso_local void @"?small_with_ctor_return@@YA?AUSmallWithCtor@@XZ"(ptr dead_on_unwind inreg noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) SmallWithDtor small_with_dtor_return() { return SmallWithDtor(); } -// LINUX-LABEL: define{{.*}} void @_Z22small_with_dtor_returnv(ptr noalias sret(%struct.SmallWithDtor) align 4 %agg.result) -// WIN32: define dso_local void @"?small_with_dtor_return@@YA?AUSmallWithDtor@@XZ"(ptr noalias sret(%struct.SmallWithDtor) align 4 %agg.result) -// WIN64: define dso_local void @"?small_with_dtor_return@@YA?AUSmallWithDtor@@XZ"(ptr noalias sret(%struct.SmallWithDtor) align 4 %agg.result) -// WOA64: define dso_local void @"?small_with_dtor_return@@YA?AUSmallWithDtor@@XZ"(ptr inreg noalias sret(%struct.SmallWithDtor) align 4 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z22small_with_dtor_returnv(ptr dead_on_unwind noalias writable sret(%struct.SmallWithDtor) align 4 %agg.result) +// WIN32: define dso_local void @"?small_with_dtor_return@@YA?AUSmallWithDtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallWithDtor) align 4 %agg.result) +// WIN64: define dso_local void @"?small_with_dtor_return@@YA?AUSmallWithDtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallWithDtor) align 4 %agg.result) +// WOA64: define dso_local void @"?small_with_dtor_return@@YA?AUSmallWithDtor@@XZ"(ptr dead_on_unwind inreg noalias writable sret(%struct.SmallWithDtor) align 4 %agg.result) SmallWithVftable small_with_vftable_return() { return SmallWithVftable(); } -// LINUX-LABEL: define{{.*}} void @_Z25small_with_vftable_returnv(ptr noalias sret(%struct.SmallWithVftable) align 4 %agg.result) -// WIN32: define dso_local void @"?small_with_vftable_return@@YA?AUSmallWithVftable@@XZ"(ptr noalias sret(%struct.SmallWithVftable) align 4 %agg.result) -// WIN64: define dso_local void @"?small_with_vftable_return@@YA?AUSmallWithVftable@@XZ"(ptr noalias sret(%struct.SmallWithVftable) align 8 %agg.result) -// WOA64: define dso_local void @"?small_with_vftable_return@@YA?AUSmallWithVftable@@XZ"(ptr inreg noalias sret(%struct.SmallWithVftable) align 8 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z25small_with_vftable_returnv(ptr dead_on_unwind noalias writable sret(%struct.SmallWithVftable) align 4 %agg.result) +// WIN32: define dso_local void @"?small_with_vftable_return@@YA?AUSmallWithVftable@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallWithVftable) align 4 %agg.result) +// WIN64: define dso_local void @"?small_with_vftable_return@@YA?AUSmallWithVftable@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.SmallWithVftable) align 8 %agg.result) +// WOA64: define dso_local void @"?small_with_vftable_return@@YA?AUSmallWithVftable@@XZ"(ptr dead_on_unwind inreg noalias writable sret(%struct.SmallWithVftable) align 8 %agg.result) MediumWithCopyCtor medium_with_copy_ctor_return() { return MediumWithCopyCtor(); } -// LINUX-LABEL: define{{.*}} void @_Z28medium_with_copy_ctor_returnv(ptr noalias sret(%struct.MediumWithCopyCtor) align 4 %agg.result) -// WIN32: define dso_local void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr noalias sret(%struct.MediumWithCopyCtor) align 4 %agg.result) -// WIN64: define dso_local void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr noalias sret(%struct.MediumWithCopyCtor) align 4 %agg.result) -// WOA: define dso_local arm_aapcs_vfpcc void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr noalias sret(%struct.MediumWithCopyCtor) align 4 %agg.result) -// WOA64: define dso_local void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr inreg noalias sret(%struct.MediumWithCopyCtor) align 4 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z28medium_with_copy_ctor_returnv(ptr dead_on_unwind noalias writable sret(%struct.MediumWithCopyCtor) align 4 %agg.result) +// WIN32: define dso_local void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.MediumWithCopyCtor) align 4 %agg.result) +// WIN64: define dso_local void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.MediumWithCopyCtor) align 4 %agg.result) +// WOA: define dso_local arm_aapcs_vfpcc void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.MediumWithCopyCtor) align 4 %agg.result) +// WOA64: define dso_local void @"?medium_with_copy_ctor_return@@YA?AUMediumWithCopyCtor@@XZ"(ptr dead_on_unwind inreg noalias writable sret(%struct.MediumWithCopyCtor) align 4 %agg.result) // Returning a large struct that doesn't fit into a register. Big big_return() { return Big(); } -// LINUX-LABEL: define{{.*}} void @_Z10big_returnv(ptr noalias sret(%struct.Big) align 4 %agg.result) -// WIN32: define dso_local void @"?big_return@@YA?AUBig@@XZ"(ptr noalias sret(%struct.Big) align 4 %agg.result) -// WIN64: define dso_local void @"?big_return@@YA?AUBig@@XZ"(ptr noalias sret(%struct.Big) align 4 %agg.result) -// WOA64: define dso_local void @"?big_return@@YA?AUBig@@XZ"(ptr noalias sret(%struct.Big) align 4 %agg.result) +// LINUX-LABEL: define{{.*}} void @_Z10big_returnv(ptr dead_on_unwind noalias writable sret(%struct.Big) align 4 %agg.result) +// WIN32: define dso_local void @"?big_return@@YA?AUBig@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.Big) align 4 %agg.result) +// WIN64: define dso_local void @"?big_return@@YA?AUBig@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.Big) align 4 %agg.result) +// WOA64: define dso_local void @"?big_return@@YA?AUBig@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.Big) align 4 %agg.result) void small_arg(Small s) {} @@ -197,7 +197,7 @@ void small_arg_with_dtor(SmallWithDtor s) {} // Test that the eligible non-aggregate is passed directly, but returned // indirectly on ARM64 Windows. -// WOA64: define dso_local void @"?small_arg_with_private_member@@YA?AUSmallWithPrivate@@U1@@Z"(ptr inreg noalias sret(%struct.SmallWithPrivate) align 4 %agg.result, i64 %s.coerce) {{.*}} { +// WOA64: define dso_local void @"?small_arg_with_private_member@@YA?AUSmallWithPrivate@@U1@@Z"(ptr dead_on_unwind inreg noalias writable sret(%struct.SmallWithPrivate) align 4 %agg.result, i64 %s.coerce) {{.*}} { SmallWithPrivate small_arg_with_private_member(SmallWithPrivate s) { return s; } // WOA64: define dso_local i32 @"?small_arg_with_small_struct_with_private_member@@YA?AUSmallWithSmallWithPrivate@@U1@@Z"(i64 %s.coerce) {{.*}} { @@ -301,27 +301,27 @@ void pass_ref_field() { class Class { public: Small thiscall_method_small() { return Small(); } - // LINUX: define {{.*}} void @_ZN5Class21thiscall_method_smallEv(ptr noalias sret(%struct.Small) align 4 %agg.result, ptr {{[^,]*}} %this) - // WIN32: define {{.*}} x86_thiscallcc void @"?thiscall_method_small@Class@@QAE?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.Small) align 4 %agg.result) - // WIN64: define linkonce_odr dso_local void @"?thiscall_method_small@Class@@QEAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.Small) align 4 %agg.result) - // WOA64: define linkonce_odr dso_local void @"?thiscall_method_small@Class@@QEAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr inreg noalias sret(%struct.Small) align 4 %agg.result) + // LINUX: define {{.*}} void @_ZN5Class21thiscall_method_smallEv(ptr dead_on_unwind noalias writable sret(%struct.Small) align 4 %agg.result, ptr {{[^,]*}} %this) + // WIN32: define {{.*}} x86_thiscallcc void @"?thiscall_method_small@Class@@QAE?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.Small) align 4 %agg.result) + // WIN64: define linkonce_odr dso_local void @"?thiscall_method_small@Class@@QEAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.Small) align 4 %agg.result) + // WOA64: define linkonce_odr dso_local void @"?thiscall_method_small@Class@@QEAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind inreg noalias writable sret(%struct.Small) align 4 %agg.result) SmallWithCtor thiscall_method_small_with_ctor() { return SmallWithCtor(); } - // LINUX: define {{.*}} void @_ZN5Class31thiscall_method_small_with_ctorEv(ptr noalias sret(%struct.SmallWithCtor) align 4 %agg.result, ptr {{[^,]*}} %this) - // WIN32: define {{.*}} x86_thiscallcc void @"?thiscall_method_small_with_ctor@Class@@QAE?AUSmallWithCtor@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.SmallWithCtor) align 4 %agg.result) - // WIN64: define linkonce_odr dso_local void @"?thiscall_method_small_with_ctor@Class@@QEAA?AUSmallWithCtor@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.SmallWithCtor) align 4 %agg.result) - // WOA64: define linkonce_odr dso_local void @"?thiscall_method_small_with_ctor@Class@@QEAA?AUSmallWithCtor@@XZ"(ptr {{[^,]*}} %this, ptr inreg noalias sret(%struct.SmallWithCtor) align 4 %agg.result) + // LINUX: define {{.*}} void @_ZN5Class31thiscall_method_small_with_ctorEv(ptr dead_on_unwind noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result, ptr {{[^,]*}} %this) + // WIN32: define {{.*}} x86_thiscallcc void @"?thiscall_method_small_with_ctor@Class@@QAE?AUSmallWithCtor@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) + // WIN64: define linkonce_odr dso_local void @"?thiscall_method_small_with_ctor@Class@@QEAA?AUSmallWithCtor@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) + // WOA64: define linkonce_odr dso_local void @"?thiscall_method_small_with_ctor@Class@@QEAA?AUSmallWithCtor@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind inreg noalias writable sret(%struct.SmallWithCtor) align 4 %agg.result) Small __cdecl cdecl_method_small() { return Small(); } - // LINUX: define {{.*}} void @_ZN5Class18cdecl_method_smallEv(ptr noalias sret(%struct.Small) align 4 %agg.result, ptr {{[^,]*}} %this) - // WIN32: define {{.*}} void @"?cdecl_method_small@Class@@QAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.Small) align 4 %agg.result) - // WIN64: define linkonce_odr dso_local void @"?cdecl_method_small@Class@@QEAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.Small) align 4 %agg.result) + // LINUX: define {{.*}} void @_ZN5Class18cdecl_method_smallEv(ptr dead_on_unwind noalias writable sret(%struct.Small) align 4 %agg.result, ptr {{[^,]*}} %this) + // WIN32: define {{.*}} void @"?cdecl_method_small@Class@@QAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.Small) align 4 %agg.result) + // WIN64: define linkonce_odr dso_local void @"?cdecl_method_small@Class@@QEAA?AUSmall@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.Small) align 4 %agg.result) Big __cdecl cdecl_method_big() { return Big(); } - // LINUX: define {{.*}} void @_ZN5Class16cdecl_method_bigEv(ptr noalias sret(%struct.Big) align 4 %agg.result, ptr {{[^,]*}} %this) - // WIN32: define {{.*}} void @"?cdecl_method_big@Class@@QAA?AUBig@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.Big) align 4 %agg.result) - // WIN64: define linkonce_odr dso_local void @"?cdecl_method_big@Class@@QEAA?AUBig@@XZ"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.Big) align 4 %agg.result) - // WOA64: define linkonce_odr dso_local void @"?cdecl_method_big@Class@@QEAA?AUBig@@XZ"(ptr {{[^,]*}} %this, ptr inreg noalias sret(%struct.Big) align 4 %agg.result) + // LINUX: define {{.*}} void @_ZN5Class16cdecl_method_bigEv(ptr dead_on_unwind noalias writable sret(%struct.Big) align 4 %agg.result, ptr {{[^,]*}} %this) + // WIN32: define {{.*}} void @"?cdecl_method_big@Class@@QAA?AUBig@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.Big) align 4 %agg.result) + // WIN64: define linkonce_odr dso_local void @"?cdecl_method_big@Class@@QEAA?AUBig@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.Big) align 4 %agg.result) + // WOA64: define linkonce_odr dso_local void @"?cdecl_method_big@Class@@QEAA?AUBig@@XZ"(ptr {{[^,]*}} %this, ptr dead_on_unwind inreg noalias writable sret(%struct.Big) align 4 %agg.result) void thiscall_method_arg(Empty s) {} // LINUX: define {{.*}} void @_ZN5Class19thiscall_method_argE5Empty(ptr {{[^,]*}} %this) diff --git a/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp b/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp index 3045e90777cb..9e37e71e257f 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp @@ -18,4 +18,4 @@ A B::foo(A x) { return x; } -// CHECK-LABEL: define{{.*}} void @"?foo@B@@QEAA?AUA@@U2@@Z"(ptr {{[^,]*}} %this, ptr noalias sret(%struct.A) align 4 %agg.result, ptr noundef %x) +// CHECK-LABEL: define{{.*}} void @"?foo@B@@QEAA?AUA@@U2@@Z"(ptr {{[^,]*}} %this, ptr dead_on_unwind noalias writable sret(%struct.A) align 4 %agg.result, ptr noundef %x) diff --git a/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp b/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp index 2a29a080d025..615a2e34d7a2 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp @@ -65,7 +65,7 @@ void f(C *c) { // CHECK-LABEL: define dso_local void @"?f@sret@@YAXPAUC@1@@Z"(ptr noundef %c) // CHECK: call x86_thiscallcc noundef i32 @"??_9C@sret@@$BA@AE"(ptr {{[^,]*}} %{{.*}}) -// CHECK: call x86_thiscallcc void @"??_9C@sret@@$BA@AE"(ptr {{[^,]*}} %{{.*}}, ptr sret(%"struct.sret::Big") align 4 %{{.*}}) +// CHECK: call x86_thiscallcc void @"??_9C@sret@@$BA@AE"(ptr {{[^,]*}} %{{.*}}, ptr dead_on_unwind writable sret(%"struct.sret::Big") align 4 %{{.*}}) // CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@sret@@$BA@AE"(ptr noundef %this, ...) {{.*}} comdat // CHECK: musttail call x86_thiscallcc void (ptr, ...) %{{.*}}(ptr noundef %{{.*}}, ...) diff --git a/clang/test/CodeGenCXX/ms-thread_local.cpp b/clang/test/CodeGenCXX/ms-thread_local.cpp index a6c62967f23d..cb0e8720c19b 100644 --- a/clang/test/CodeGenCXX/ms-thread_local.cpp +++ b/clang/test/CodeGenCXX/ms-thread_local.cpp @@ -29,9 +29,9 @@ thread_local A b; // CHECK-LD-LABEL: declare dso_local void @__dyn_tls_on_demand_init() // CHECK-LEGACY-NOT: declare dso_local void @__dyn_tls_on_demand_init() -// CHECK-LABEL: define dso_local void @"?f@@YA?AUA@@XZ"(ptr noalias sret(%struct.A) align 1 %agg.result) +// CHECK-LABEL: define dso_local void @"?f@@YA?AUA@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.A) align 1 %agg.result) // CHECK: call void @__dyn_tls_on_demand_init() -// CHECK-LD-LABEL: define dso_local void @"?f@@YA?AUA@@XZ"(ptr noalias sret(%struct.A) align 1 %agg.result) +// CHECK-LD-LABEL: define dso_local void @"?f@@YA?AUA@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.A) align 1 %agg.result) // CHECK-LD: call void @__dyn_tls_on_demand_init() // CHECK-LEGACY-NOT: call void @__dyn_tls_on_demand_init() diff --git a/clang/test/CodeGenCXX/nrvo.cpp b/clang/test/CodeGenCXX/nrvo.cpp index 975cf6ee1b66..33dc4cf9dbc8 100644 --- a/clang/test/CodeGenCXX/nrvo.cpp +++ b/clang/test/CodeGenCXX/nrvo.cpp @@ -1059,7 +1059,7 @@ X test8(bool b) { // CHECK-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 4 // CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_Y:%.*]], align 1 // CHECK-NEXT: store ptr [[AGG_RESULT:%.*]], ptr [[RESULT_PTR]], align 4 -// CHECK-NEXT: call void @_ZN1YIiE1fEv(ptr sret([[STRUCT_Y]]) align 1 [[TMP]]) +// CHECK-NEXT: call void @_ZN1YIiE1fEv(ptr dead_on_unwind writable sret([[STRUCT_Y]]) align 1 [[TMP]]) // CHECK-NEXT: call void @llvm.trap() // CHECK-NEXT: unreachable // @@ -1068,7 +1068,7 @@ X test8(bool b) { // CHECK-EH-03-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 4 // CHECK-EH-03-NEXT: [[TMP:%.*]] = alloca [[STRUCT_Y:%.*]], align 1 // CHECK-EH-03-NEXT: store ptr [[AGG_RESULT:%.*]], ptr [[RESULT_PTR]], align 4 -// CHECK-EH-03-NEXT: call void @_ZN1YIiE1fEv(ptr sret([[STRUCT_Y]]) align 1 [[TMP]]) +// CHECK-EH-03-NEXT: call void @_ZN1YIiE1fEv(ptr dead_on_unwind writable sret([[STRUCT_Y]]) align 1 [[TMP]]) // CHECK-EH-03-NEXT: call void @llvm.trap() // CHECK-EH-03-NEXT: unreachable // @@ -1077,7 +1077,7 @@ X test8(bool b) { // CHECK-EH-11-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 4 // CHECK-EH-11-NEXT: [[TMP:%.*]] = alloca [[STRUCT_Y:%.*]], align 1 // CHECK-EH-11-NEXT: store ptr [[AGG_RESULT:%.*]], ptr [[RESULT_PTR]], align 4 -// CHECK-EH-11-NEXT: call void @_ZN1YIiE1fEv(ptr sret([[STRUCT_Y]]) align 1 [[TMP]]) +// CHECK-EH-11-NEXT: call void @_ZN1YIiE1fEv(ptr dead_on_unwind writable sret([[STRUCT_Y]]) align 1 [[TMP]]) // CHECK-EH-11-NEXT: call void @llvm.trap() // CHECK-EH-11-NEXT: unreachable // @@ -1915,7 +1915,7 @@ X test15(bool b) { // http://wg21.link/p2025r2#ex-15 // CHECK-EH-11-NEXT: call void @_ZN1XC1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[X]]) // CHECK-EH-11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK-EH-11-NEXT: store ptr [[X]], ptr [[TMP0]], align 4 -// CHECK-EH-11-NEXT: invoke void @"_ZZ6test16vENK3$_0clEv"(ptr sret([[CLASS_X]]) align 1 [[AGG_TMP]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK-EH-11-NEXT: invoke void @"_ZZ6test16vENK3$_0clEv"(ptr dead_on_unwind writable sret([[CLASS_X]]) align 1 [[AGG_TMP]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK-EH-11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK-EH-11: invoke.cont: // CHECK-EH-11-NEXT: invoke void @_Z8ConsumeX1X(ptr noundef [[AGG_TMP]]) @@ -2530,7 +2530,7 @@ X test18(int i) { // http://wg21.link/p2025r2#ex-11 // CHECK-EH-11-NEXT: call void @_ZN1XC1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_RESULT]]) // CHECK-EH-11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK-EH-11-NEXT: store ptr [[AGG_RESULT]], ptr [[TMP0]], align 4 -// CHECK-EH-11-NEXT: invoke void @"_ZZ6test19vENK3$_0clEv"(ptr sret([[CLASS_X]]) align 1 [[L]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK-EH-11-NEXT: invoke void @"_ZZ6test19vENK3$_0clEv"(ptr dead_on_unwind writable sret([[CLASS_X]]) align 1 [[L]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK-EH-11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK-EH-11: invoke.cont: // CHECK-EH-11-NEXT: store i1 true, ptr [[NRVO]], align 1 @@ -2584,9 +2584,9 @@ X test20() { // http://wg21.link/p2025r2#ex-18 // CHECK-EH-11-NEXT: entry: // CHECK-EH-11-NEXT: [[AGG_TMP_ENSURED:%.*]] = alloca [[CLASS_X:%.*]], align 1 // CHECK-EH-11-NEXT: [[AGG_TMP_ENSURED1:%.*]] = alloca [[CLASS_X]], align 1 -// CHECK-EH-11-NEXT: call void @_Z6test20ILb1EE1Xv(ptr sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED]]) +// CHECK-EH-11-NEXT: call void @_Z6test20ILb1EE1Xv(ptr dead_on_unwind writable sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED]]) // CHECK-EH-11-NEXT: call void @_ZN1XD1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP_ENSURED]]) #[[ATTR6]] -// CHECK-EH-11-NEXT: call void @_Z6test20ILb0EE1Xv(ptr sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED1]]) +// CHECK-EH-11-NEXT: call void @_Z6test20ILb0EE1Xv(ptr dead_on_unwind writable sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED1]]) // CHECK-EH-11-NEXT: call void @_ZN1XD1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP_ENSURED1]]) #[[ATTR6]] // CHECK-EH-11-NEXT: ret void // @@ -2934,9 +2934,9 @@ X test25() { // CHECK-EH-11-NEXT: entry: // CHECK-EH-11-NEXT: [[AGG_TMP_ENSURED:%.*]] = alloca [[CLASS_X:%.*]], align 1 // CHECK-EH-11-NEXT: [[AGG_TMP_ENSURED1:%.*]] = alloca [[CLASS_X]], align 1 -// CHECK-EH-11-NEXT: call void @_Z6test25ILb1EE1Xv(ptr sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED]]) +// CHECK-EH-11-NEXT: call void @_Z6test25ILb1EE1Xv(ptr dead_on_unwind writable sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED]]) // CHECK-EH-11-NEXT: call void @_ZN1XD1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP_ENSURED]]) #[[ATTR6]] -// CHECK-EH-11-NEXT: call void @_Z6test25ILb0EE1Xv(ptr sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED1]]) +// CHECK-EH-11-NEXT: call void @_Z6test25ILb0EE1Xv(ptr dead_on_unwind writable sret([[CLASS_X]]) align 1 [[AGG_TMP_ENSURED1]]) // CHECK-EH-11-NEXT: call void @_ZN1XD1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP_ENSURED1]]) #[[ATTR6]] // CHECK-EH-11-NEXT: ret void // diff --git a/clang/test/CodeGenCXX/pass-by-value-noalias.cpp b/clang/test/CodeGenCXX/pass-by-value-noalias.cpp index 765a6fb66a72..773cf6b81c3b 100644 --- a/clang/test/CodeGenCXX/pass-by-value-noalias.cpp +++ b/clang/test/CodeGenCXX/pass-by-value-noalias.cpp @@ -58,8 +58,8 @@ A *p; // NO_NOALIAS: define{{.*}} void @_Z4take1A(ptr noundef %arg) void take(A arg) {} -// WITH_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(ptr noalias sret(%struct.A) align 1 %agg.result, ptr noundef %where) -// NO_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(ptr noalias sret(%struct.A) align 1 %agg.result, ptr noundef %where) +// WITH_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(ptr dead_on_unwind noalias writable sret(%struct.A) align 1 %agg.result, ptr noundef %where) +// NO_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(ptr dead_on_unwind noalias writable sret(%struct.A) align 1 %agg.result, ptr noundef %where) A CreateA(A **where) { A justlikethis; *where = &justlikethis; //Escaped pointer 2 (should also be UB, then) diff --git a/clang/test/CodeGenCXX/regcall.cpp b/clang/test/CodeGenCXX/regcall.cpp index b47a2125d787..1ff7597e9dee 100644 --- a/clang/test/CodeGenCXX/regcall.cpp +++ b/clang/test/CodeGenCXX/regcall.cpp @@ -74,8 +74,8 @@ bool __regcall operator ==(const test_class&, const test_class&){ --x; return fa // CHECK-WIN32-DAG: define dso_local x86_regcallcc noundef zeroext i1 @"??8@Yw_NABVtest_class@@0@Z" test_class __regcall operator""_test_class (unsigned long long) { ++x; return test_class{};} -// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr noalias sret(%class.test_class) align 4 %agg.result, i64 noundef %0) -// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr inreg noalias sret(%class.test_class) align 4 %agg.result, i64 noundef %0) +// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr dead_on_unwind noalias writable sret(%class.test_class) align 4 %agg.result, i64 noundef %0) +// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr dead_on_unwind inreg noalias writable sret(%class.test_class) align 4 %agg.result, i64 noundef %0) // CHECK-WIN64-DAG: ??__K_test_class@@Yw?AVtest_class@@_K@Z" // CHECK-WIN32-DAG: ??__K_test_class@@Yw?AVtest_class@@_K@Z" @@ -99,8 +99,8 @@ void force_gen() { long double _Complex __regcall foo(long double _Complex f) { return f; } -// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe(ptr noalias sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %f) -// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe(ptr inreg noalias sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 4 %f) +// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe(ptr dead_on_unwind noalias writable sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %f) +// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe(ptr dead_on_unwind inreg noalias writable sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 4 %f) // CHECK-WIN64-DAG: define dso_local x86_regcallcc noundef { double, double } @"?foo@@YwU?$_Complex@O@__clang@@U12@@Z"(double noundef %f.0, double noundef %f.1) // CHECK-WIN32-DAG: define dso_local x86_regcallcc noundef { double, double } @"?foo@@YwU?$_Complex@O@__clang@@U12@@Z"(double noundef %f.0, double noundef %f.1) diff --git a/clang/test/CodeGenCXX/regcall4.cpp b/clang/test/CodeGenCXX/regcall4.cpp index 7c35db36e105..2ecd5b4951c7 100644 --- a/clang/test/CodeGenCXX/regcall4.cpp +++ b/clang/test/CodeGenCXX/regcall4.cpp @@ -74,8 +74,8 @@ bool __regcall operator ==(const test_class&, const test_class&){ --x; return fa // CHECK-WIN32-DAG: define dso_local x86_regcallcc noundef zeroext i1 @"??8@Yx_NABVtest_class@@0@Z" test_class __regcall operator""_test_class (unsigned long long) { ++x; return test_class{};} -// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr noalias sret(%class.test_class) align 4 %agg.result, i64 noundef %0) -// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr inreg noalias sret(%class.test_class) align 4 %agg.result, i64 noundef %0) +// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr dead_on_unwind noalias writable sret(%class.test_class) align 4 %agg.result, i64 noundef %0) +// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(ptr dead_on_unwind inreg noalias writable sret(%class.test_class) align 4 %agg.result, i64 noundef %0) // CHECK-WIN64-DAG: ??__K_test_class@@Yx?AVtest_class@@_K@Z" // CHECK-WIN32-DAG: ??__K_test_class@@Yx?AVtest_class@@_K@Z" @@ -99,8 +99,8 @@ void force_gen() { long double _Complex __regcall foo(long double _Complex f) { return f; } -// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall4__fooCe(ptr noalias sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %f) -// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall4__fooCe(ptr inreg noalias sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 4 %f) +// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall4__fooCe(ptr dead_on_unwind noalias writable sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %f) +// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall4__fooCe(ptr dead_on_unwind inreg noalias writable sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, ptr noundef byval({ x86_fp80, x86_fp80 }) align 4 %f) // CHECK-WIN64-DAG: define dso_local x86_regcallcc noundef { double, double } @"?foo@@YxU?$_Complex@O@__clang@@U12@@Z"(double noundef %f.0, double noundef %f.1) // CHECK-WIN32-DAG: define dso_local x86_regcallcc noundef { double, double } @"?foo@@YxU?$_Complex@O@__clang@@U12@@Z"(double noundef %f.0, double noundef %f.1) diff --git a/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp b/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp index dbeea5e32cfb..50a8d167f5b7 100644 --- a/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp +++ b/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp @@ -36,7 +36,7 @@ const char * f(S s) // CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr [[T3]]) // CHECK: [[T5:%.*]] = call noundef ptr @_ZN1TC1E1S(ptr {{[^,]*}} [[T3]], [2 x i32] %{{.*}}) // -// CHECK: call void @_ZNK1T6concatERKS_(ptr sret(%class.T) align 4 [[T1]], ptr {{[^,]*}} [[T2]], ptr noundef nonnull align 4 dereferenceable(16) [[T3]]) +// CHECK: call void @_ZNK1T6concatERKS_(ptr dead_on_unwind writable sret(%class.T) align 4 [[T1]], ptr {{[^,]*}} [[T2]], ptr noundef nonnull align 4 dereferenceable(16) [[T3]]) // CHECK: [[T6:%.*]] = call noundef ptr @_ZNK1T3strEv(ptr {{[^,]*}} [[T1]]) // // CHECK: call void @llvm.lifetime.end.p0( diff --git a/clang/test/CodeGenCXX/stack-reuse.cpp b/clang/test/CodeGenCXX/stack-reuse.cpp index e2412a55c1f6..ca73781b79ec 100644 --- a/clang/test/CodeGenCXX/stack-reuse.cpp +++ b/clang/test/CodeGenCXX/stack-reuse.cpp @@ -135,7 +135,7 @@ int large_combiner_test(S_large s) { // CHECK: [[T2:%.*]] = alloca %struct.Combiner // CHECK: [[T1:%.*]] = alloca %struct.Combiner // CHECK: [[T3:%.*]] = call noundef ptr @_ZN8CombinerC1E7S_large(ptr {{[^,]*}} [[T1]], [9 x i32] %s.coerce) -// CHECK: call void @_ZN8Combiner1fEv(ptr nonnull sret(%struct.Combiner) align 4 [[T2]], ptr {{[^,]*}} [[T1]]) +// CHECK: call void @_ZN8Combiner1fEv(ptr dead_on_unwind nonnull writable sret(%struct.Combiner) align 4 [[T2]], ptr {{[^,]*}} [[T1]]) // CHECK: [[T5:%.*]] = load i32, ptr [[T2]] // CHECK: ret i32 [[T5]] diff --git a/clang/test/CodeGenCXX/temporaries.cpp b/clang/test/CodeGenCXX/temporaries.cpp index c5adb42a6f17..9f29d3b73278 100644 --- a/clang/test/CodeGenCXX/temporaries.cpp +++ b/clang/test/CodeGenCXX/temporaries.cpp @@ -414,13 +414,13 @@ namespace Elision { // CHECK-NEXT: call void @_ZN7Elision1AC1Ev(ptr {{[^,]*}} [[I]]) A i = (foo(), A()); - // CHECK-NEXT: call void @_ZN7Elision4fooAEv(ptr sret([[A]]) align 8 [[T0]]) + // CHECK-NEXT: call void @_ZN7Elision4fooAEv(ptr dead_on_unwind writable sret([[A]]) align 8 [[T0]]) // CHECK-NEXT: call void @_ZN7Elision1AC1Ev(ptr {{[^,]*}} [[J]]) // CHECK-NEXT: call void @_ZN7Elision1AD1Ev(ptr {{[^,]*}} [[T0]]) A j = (fooA(), A()); // CHECK-NEXT: call void @_ZN7Elision1AC1Ev(ptr {{[^,]*}} [[T1]]) - // CHECK-NEXT: call void @_ZN7Elision4fooAEv(ptr sret([[A]]) align 8 [[K]]) + // CHECK-NEXT: call void @_ZN7Elision4fooAEv(ptr dead_on_unwind writable sret([[A]]) align 8 [[K]]) // CHECK-NEXT: call void @_ZN7Elision1AD1Ev(ptr {{[^,]*}} [[T1]]) A k = (A(), fooA()); @@ -447,7 +447,7 @@ namespace Elision { // CHECK-NEXT: call void @_ZN7Elision1AD1Ev(ptr {{[^,]*}} [[I]]) } - // CHECK: define{{.*}} void @_ZN7Elision5test2Ev(ptr noalias sret([[A]]) align 8 + // CHECK: define{{.*}} void @_ZN7Elision5test2Ev(ptr dead_on_unwind noalias writable sret([[A]]) align 8 A test2() { // CHECK: call void @_ZN7Elision3fooEv() // CHECK-NEXT: call void @_ZN7Elision1AC1Ev(ptr {{[^,]*}} [[RET:%.*]]) @@ -455,7 +455,7 @@ namespace Elision { return (foo(), A()); } - // CHECK: define{{.*}} void @_ZN7Elision5test3EiNS_1AE(ptr noalias sret([[A]]) align 8 + // CHECK: define{{.*}} void @_ZN7Elision5test3EiNS_1AE(ptr dead_on_unwind noalias writable sret([[A]]) align 8 A test3(int v, A x) { if (v < 5) // CHECK: call void @_ZN7Elision1AC1Ev(ptr {{[^,]*}} [[RET:%.*]]) @@ -495,7 +495,7 @@ namespace Elision { // CHECK: call void @_ZN7Elision1AD1Ev(ptr {{[^,]*}} [[X]]) } - // CHECK: define{{.*}} void @_ZN7Elision5test5Ev(ptr noalias sret([[A]]) align 8 + // CHECK: define{{.*}} void @_ZN7Elision5test5Ev(ptr dead_on_unwind noalias writable sret([[A]]) align 8 struct B { A a; B(); }; A test5() { // CHECK: [[AT0:%.*]] = alloca [[A]], align 8 @@ -533,7 +533,7 @@ namespace Elision { void test6(const C *x) { // CHECK: [[T0:%.*]] = alloca [[A]], align 8 // CHECK: [[X:%.*]] = load ptr, ptr {{%.*}}, align 8 - // CHECK-NEXT: call void @_ZNK7Elision1CcvNS_1AEEv(ptr sret([[A]]) align 8 [[T0]], ptr {{[^,]*}} [[X]]) + // CHECK-NEXT: call void @_ZNK7Elision1CcvNS_1AEEv(ptr dead_on_unwind writable sret([[A]]) align 8 [[T0]], ptr {{[^,]*}} [[X]]) // CHECK-NEXT: call void @_ZNK7Elision1A3fooEv(ptr {{[^,]*}} [[T0]]) // CHECK-NEXT: call void @_ZN7Elision1AD1Ev(ptr {{[^,]*}} [[T0]]) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenCXX/thiscall-struct-return.cpp b/clang/test/CodeGenCXX/thiscall-struct-return.cpp index c29ec56b41c1..7802ed4b18eb 100644 --- a/clang/test/CodeGenCXX/thiscall-struct-return.cpp +++ b/clang/test/CodeGenCXX/thiscall-struct-return.cpp @@ -34,8 +34,8 @@ void test( void ) { // CHECK: call void @_ZN1CC1Ev(ptr {{[^,]*}} [[C:%.+]]) C c; -// CHECK: call x86_thiscallcc void @_ZNK1C5SmallEv(ptr sret(%struct.S) align 4 %{{.+}}, ptr {{[^,]*}} [[C]]) +// CHECK: call x86_thiscallcc void @_ZNK1C5SmallEv(ptr dead_on_unwind writable sret(%struct.S) align 4 %{{.+}}, ptr {{[^,]*}} [[C]]) (void)c.Small(); -// CHECK: call x86_thiscallcc void @_ZNK1C6MediumEv(ptr sret(%struct.M) align 4 %{{.+}}, ptr {{[^,]*}} [[C]]) +// CHECK: call x86_thiscallcc void @_ZNK1C6MediumEv(ptr dead_on_unwind writable sret(%struct.M) align 4 %{{.+}}, ptr {{[^,]*}} [[C]]) (void)c.Medium(); } diff --git a/clang/test/CodeGenCXX/thunk-returning-memptr.cpp b/clang/test/CodeGenCXX/thunk-returning-memptr.cpp index aaa5c8605f23..99ef76f91cec 100644 --- a/clang/test/CodeGenCXX/thunk-returning-memptr.cpp +++ b/clang/test/CodeGenCXX/thunk-returning-memptr.cpp @@ -23,5 +23,5 @@ C::C() {} // Because of the tail call, the return value cannot be copied into a local // alloca. (PR39901) -// CHECK-LABEL: define linkonce_odr void @_ZThn4_N1C1fEv(ptr noalias sret({ i32, i32 }) align 4 %agg.result, ptr noundef %this) -// CHECK: tail call void @_ZN1C1fEv(ptr sret({ i32, i32 }) align 4 %agg.result +// CHECK-LABEL: define linkonce_odr void @_ZThn4_N1C1fEv(ptr dead_on_unwind noalias writable sret({ i32, i32 }) align 4 %agg.result, ptr noundef %this) +// CHECK: tail call void @_ZN1C1fEv(ptr dead_on_unwind writable sret({ i32, i32 }) align 4 %agg.result diff --git a/clang/test/CodeGenCXX/trivial_abi.cpp b/clang/test/CodeGenCXX/trivial_abi.cpp index 3249df129157..3012b0f2bc33 100644 --- a/clang/test/CodeGenCXX/trivial_abi.cpp +++ b/clang/test/CodeGenCXX/trivial_abi.cpp @@ -151,7 +151,7 @@ void testIgnoredSmall() { void testParamLarge(Large a) noexcept { } -// CHECK: define{{.*}} void @_Z15testReturnLargev(ptr noalias sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_RESULT:.*]]) +// CHECK: define{{.*}} void @_Z15testReturnLargev(ptr dead_on_unwind noalias writable sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_RESULT:.*]]) // CHECK: %[[CALL:.*]] = call noundef ptr @_ZN5LargeC1Ev(ptr {{[^,]*}} %[[AGG_RESULT]]) // CHECK: ret void // CHECK: } @@ -178,7 +178,7 @@ void testCallLarge0() { // CHECK: define{{.*}} void @_Z14testCallLarge1v() // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_LARGE:.*]], align 8 -// CHECK: call void @_Z15testReturnLargev(ptr sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_TMP]]) +// CHECK: call void @_Z15testReturnLargev(ptr dead_on_unwind writable sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_TMP]]) // CHECK: call void @_Z14testParamLarge5Large(ptr noundef %[[AGG_TMP]]) // CHECK: ret void // CHECK: } @@ -189,7 +189,7 @@ void testCallLarge1() { // CHECK: define{{.*}} void @_Z16testIgnoredLargev() // CHECK: %[[AGG_TMP_ENSURED:.*]] = alloca %[[STRUCT_LARGE:.*]], align 8 -// CHECK: call void @_Z15testReturnLargev(ptr sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_TMP_ENSURED]]) +// CHECK: call void @_Z15testReturnLargev(ptr dead_on_unwind writable sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_TMP_ENSURED]]) // CHECK: %[[CALL:.*]] = call noundef ptr @_ZN5LargeD1Ev(ptr {{[^,]*}} %[[AGG_TMP_ENSURED]]) // CHECK: ret void // CHECK: } @@ -210,7 +210,7 @@ Trivial testReturnHasTrivial() { return t; } -// CHECK: define{{.*}} void @_Z23testReturnHasNonTrivialv(ptr noalias sret(%[[STRUCT_NONTRIVIAL:.*]]) align 4 %[[AGG_RESULT:.*]]) +// CHECK: define{{.*}} void @_Z23testReturnHasNonTrivialv(ptr dead_on_unwind noalias writable sret(%[[STRUCT_NONTRIVIAL:.*]]) align 4 %[[AGG_RESULT:.*]]) // CHECK: %[[CALL:.*]] = call noundef ptr @_ZN10NonTrivialC1Ev(ptr {{[^,]*}} %[[AGG_RESULT]]) // CHECK: ret void // CHECK: } diff --git a/clang/test/CodeGenCXX/unknown-anytype.cpp b/clang/test/CodeGenCXX/unknown-anytype.cpp index 862b8fe8b66d..ade9a6482d75 100644 --- a/clang/test/CodeGenCXX/unknown-anytype.cpp +++ b/clang/test/CodeGenCXX/unknown-anytype.cpp @@ -70,7 +70,7 @@ struct Test7 { }; extern "C" __unknown_anytype test7_any(int); Test7 test7() { - // COMMON: call void @test7_any(ptr sret({{%.*}}) align 1 {{%.*}}, i32 noundef 5) + // COMMON: call void @test7_any(ptr dead_on_unwind writable sret({{%.*}}) align 1 {{%.*}}, i32 noundef 5) return (Test7) test7_any(5); } diff --git a/clang/test/CodeGenCXX/wasm-args-returns.cpp b/clang/test/CodeGenCXX/wasm-args-returns.cpp index 090ca9a99756..e80dfefedece 100644 --- a/clang/test/CodeGenCXX/wasm-args-returns.cpp +++ b/clang/test/CodeGenCXX/wasm-args-returns.cpp @@ -30,52 +30,52 @@ struct two_fields { double d, e; }; test(two_fields); -// CHECK: define void @_Z7forward10two_fields(ptr noalias nocapture writeonly sret(%struct.two_fields) align 8 %{{.*}}, ptr nocapture readonly byval(%struct.two_fields) align 8 %{{.*}}) +// CHECK: define void @_Z7forward10two_fields(ptr dead_on_unwind noalias nocapture writable writeonly sret(%struct.two_fields) align 8 %{{.*}}, ptr nocapture readonly byval(%struct.two_fields) align 8 %{{.*}}) // // CHECK: define void @_Z15test_two_fieldsv() // CHECK: %[[tmp:.*]] = alloca %struct.two_fields, align 8 -// CHECK: call void @_Z14def_two_fieldsv(ptr nonnull sret(%struct.two_fields) align 8 %[[tmp]]) +// CHECK: call void @_Z14def_two_fieldsv(ptr dead_on_unwind nonnull writable sret(%struct.two_fields) align 8 %[[tmp]]) // CHECK: call void @_Z3use10two_fields(ptr nonnull byval(%struct.two_fields) align 8 %[[tmp]]) // CHECK: ret void // // CHECK: declare void @_Z3use10two_fields(ptr byval(%struct.two_fields) align 8) -// CHECK: declare void @_Z14def_two_fieldsv(ptr sret(%struct.two_fields) align 8) +// CHECK: declare void @_Z14def_two_fieldsv(ptr dead_on_unwind writable sret(%struct.two_fields) align 8) struct copy_ctor { double d; copy_ctor(copy_ctor const &); }; test(copy_ctor); -// CHECK: define void @_Z7forward9copy_ctor(ptr noalias {{[^,]*}} sret(%struct.copy_ctor) align 8 %{{.*}}, ptr nonnull %{{.*}}) +// CHECK: define void @_Z7forward9copy_ctor(ptr dead_on_unwind noalias {{[^,]*}} sret(%struct.copy_ctor) align 8 %{{.*}}, ptr nonnull %{{.*}}) // // CHECK: declare ptr @_ZN9copy_ctorC1ERKS_(ptr {{[^,]*}} returned {{[^,]*}}, ptr nonnull align 8 dereferenceable(8)) // // CHECK: define void @_Z14test_copy_ctorv() // CHECK: %[[tmp:.*]] = alloca %struct.copy_ctor, align 8 -// CHECK: call void @_Z13def_copy_ctorv(ptr nonnull sret(%struct.copy_ctor) align 8 %[[tmp]]) +// CHECK: call void @_Z13def_copy_ctorv(ptr dead_on_unwind nonnull writable sret(%struct.copy_ctor) align 8 %[[tmp]]) // CHECK: call void @_Z3use9copy_ctor(ptr nonnull %[[tmp]]) // CHECK: ret void // // CHECK: declare void @_Z3use9copy_ctor(ptr) -// CHECK: declare void @_Z13def_copy_ctorv(ptr sret(%struct.copy_ctor) align 8) +// CHECK: declare void @_Z13def_copy_ctorv(ptr dead_on_unwind writable sret(%struct.copy_ctor) align 8) struct __attribute__((aligned(16))) aligned_copy_ctor { double d, e; aligned_copy_ctor(aligned_copy_ctor const &); }; test(aligned_copy_ctor); -// CHECK: define void @_Z7forward17aligned_copy_ctor(ptr noalias {{[^,]*}} sret(%struct.aligned_copy_ctor) align 16 %{{.*}}, ptr nonnull %{{.*}}) +// CHECK: define void @_Z7forward17aligned_copy_ctor(ptr dead_on_unwind noalias {{[^,]*}} sret(%struct.aligned_copy_ctor) align 16 %{{.*}}, ptr nonnull %{{.*}}) // // CHECK: declare ptr @_ZN17aligned_copy_ctorC1ERKS_(ptr {{[^,]*}} returned {{[^,]*}}, ptr nonnull align 16 dereferenceable(16)) // // CHECK: define void @_Z22test_aligned_copy_ctorv() // CHECK: %[[tmp:.*]] = alloca %struct.aligned_copy_ctor, align 16 -// CHECK: call void @_Z21def_aligned_copy_ctorv(ptr nonnull sret(%struct.aligned_copy_ctor) align 16 %[[tmp]]) +// CHECK: call void @_Z21def_aligned_copy_ctorv(ptr dead_on_unwind nonnull writable sret(%struct.aligned_copy_ctor) align 16 %[[tmp]]) // CHECK: call void @_Z3use17aligned_copy_ctor(ptr nonnull %[[tmp]]) // CHECK: ret void // // CHECK: declare void @_Z3use17aligned_copy_ctor(ptr) -// CHECK: declare void @_Z21def_aligned_copy_ctorv(ptr sret(%struct.aligned_copy_ctor) align 16) +// CHECK: declare void @_Z21def_aligned_copy_ctorv(ptr dead_on_unwind writable sret(%struct.aligned_copy_ctor) align 16) struct empty {}; test(empty); diff --git a/clang/test/CodeGenCXX/x86_32-arguments.cpp b/clang/test/CodeGenCXX/x86_32-arguments.cpp index 7388b2fcfe6c..c071548327e8 100644 --- a/clang/test/CodeGenCXX/x86_32-arguments.cpp +++ b/clang/test/CodeGenCXX/x86_32-arguments.cpp @@ -6,7 +6,7 @@ struct S { short s; }; -// CHECK-LABEL: define{{.*}} void @_Z1fv(ptr noalias sret(%struct.S) align 2 % +// CHECK-LABEL: define{{.*}} void @_Z1fv(ptr dead_on_unwind noalias writable sret(%struct.S) align 2 % S f() { return S(); } // CHECK-LABEL: define{{.*}} void @_Z1f1S(ptr noundef %0) void f(S) { } @@ -18,7 +18,7 @@ public: double c; }; -// CHECK-LABEL: define{{.*}} void @_Z1gv(ptr noalias sret(%class.C) align 4 % +// CHECK-LABEL: define{{.*}} void @_Z1gv(ptr dead_on_unwind noalias writable sret(%class.C) align 4 % C g() { return C(); } // CHECK-LABEL: define{{.*}} void @_Z1f1C(ptr noundef %0) @@ -103,13 +103,13 @@ struct s7_1 { double x; }; struct s7 : s7_0, s7_1 { }; s7 f7() { return s7(); } -// CHECK-LABEL: define{{.*}} void @_Z2f8v(ptr noalias sret(%struct.s8) align 4 %agg.result) +// CHECK-LABEL: define{{.*}} void @_Z2f8v(ptr dead_on_unwind noalias writable sret(%struct.s8) align 4 %agg.result) struct s8_0 { }; struct s8_1 { double x; }; struct s8 { s8_0 a; s8_1 b; }; s8 f8() { return s8(); } -// CHECK-LABEL: define{{.*}} void @_Z2f9v(ptr noalias sret(%struct.s9) align 4 %agg.result) +// CHECK-LABEL: define{{.*}} void @_Z2f9v(ptr dead_on_unwind noalias writable sret(%struct.s9) align 4 %agg.result) struct s9_0 { unsigned : 0; }; struct s9_1 { double x; }; struct s9 { s9_0 a; s9_1 b; }; diff --git a/clang/test/CodeGenCXX/x86_64-arguments.cpp b/clang/test/CodeGenCXX/x86_64-arguments.cpp index d1bbf5d30f59..ebeba7fd6549 100644 --- a/clang/test/CodeGenCXX/x86_64-arguments.cpp +++ b/clang/test/CodeGenCXX/x86_64-arguments.cpp @@ -173,7 +173,7 @@ namespace test9 { // CHECK: define{{.*}} void @_ZN5test93fooEPNS_1SEPNS_1TE(ptr %0, ptr %1) void foo(S*, T*) {} - // CHECK: define{{.*}} void @_ZN5test91aEiiiiNS_1TEPv(ptr noalias sret([[S:%.*]]) align 8 {{%.*}}, i32 %0, i32 %1, i32 %2, i32 %3, ptr byval([[T:%.*]]) align 8 %4, ptr %5) + // CHECK: define{{.*}} void @_ZN5test91aEiiiiNS_1TEPv(ptr dead_on_unwind noalias writable sret([[S:%.*]]) align 8 {{%.*}}, i32 %0, i32 %1, i32 %2, i32 %3, ptr byval([[T:%.*]]) align 8 %4, ptr %5) S a(int, int, int, int, T, void*) { return S(); } @@ -183,7 +183,7 @@ namespace test9 { return sret; } - // CHECK: define{{.*}} void @_ZN5test91cEiiiNS_1TEPv(ptr noalias sret([[S]]) align 8 {{%.*}}, i32 %0, i32 %1, i32 %2, ptr {{%.*}}, ptr {{%.*}}, ptr %3) + // CHECK: define{{.*}} void @_ZN5test91cEiiiNS_1TEPv(ptr dead_on_unwind noalias writable sret([[S]]) align 8 {{%.*}}, i32 %0, i32 %1, i32 %2, ptr {{%.*}}, ptr {{%.*}}, ptr %3) S c(int, int, int, T, void*) { return S(); } diff --git a/clang/test/CodeGenCoroutines/coro-await.cpp b/clang/test/CodeGenCoroutines/coro-await.cpp index e1c7039469af..dc5a765ccb83 100644 --- a/clang/test/CodeGenCoroutines/coro-await.cpp +++ b/clang/test/CodeGenCoroutines/coro-await.cpp @@ -127,7 +127,7 @@ extern "C" void f1(int) { // CHECK: %[[PROMISE:.+]] = alloca %"struct.std::coroutine_traits::promise_type" // CHECK: %[[FRAME:.+]] = call ptr @llvm.coro.begin( co_yield 42; - // CHECK: call void @_ZNSt16coroutine_traitsIJviEE12promise_type11yield_valueEi(ptr sret(%struct.suspend_maybe) align 4 %[[AWAITER:.+]], ptr {{[^,]*}} %[[PROMISE]], i32 42) + // CHECK: call void @_ZNSt16coroutine_traitsIJviEE12promise_type11yield_valueEi(ptr dead_on_unwind writable sret(%struct.suspend_maybe) align 4 %[[AWAITER:.+]], ptr {{[^,]*}} %[[PROMISE]], i32 42) // See if we need to suspend: // -------------------------- @@ -194,20 +194,20 @@ extern "C" void UseAggr(Aggr&&); extern "C" void TestAggr() { UseAggr(co_await AggrAwaiter{}); Whatever(); - // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr sret(%struct.Aggr) align 4 %[[AwaitResume:.+]], + // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr dead_on_unwind writable sret(%struct.Aggr) align 4 %[[AwaitResume:.+]], // CHECK: call void @UseAggr(ptr nonnull align 4 dereferenceable(12) %[[AwaitResume]]) // CHECK: call void @_ZN4AggrD1Ev(ptr {{[^,]*}} %[[AwaitResume]]) // CHECK: call void @Whatever() co_await AggrAwaiter{}; Whatever(); - // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr sret(%struct.Aggr) align 4 %[[AwaitResume2:.+]], + // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr dead_on_unwind writable sret(%struct.Aggr) align 4 %[[AwaitResume2:.+]], // CHECK: call void @_ZN4AggrD1Ev(ptr {{[^,]*}} %[[AwaitResume2]]) // CHECK: call void @Whatever() Aggr Val = co_await AggrAwaiter{}; Whatever(); - // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr sret(%struct.Aggr) align 4 %[[AwaitResume3:.+]], + // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr dead_on_unwind writable sret(%struct.Aggr) align 4 %[[AwaitResume3:.+]], // CHECK: call void @Whatever() // CHECK: call void @_ZN4AggrD1Ev(ptr {{[^,]*}} %[[AwaitResume3]]) } @@ -252,7 +252,7 @@ extern "C" void TestOpAwait() { co_await MyAgg{}; // CHECK: call void @_ZN5MyAggawEv(ptr {{[^,]*}} % - // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr sret(%struct.Aggr) align 4 % + // CHECK: call void @_ZN11AggrAwaiter12await_resumeEv(ptr dead_on_unwind writable sret(%struct.Aggr) align 4 % } // CHECK-LABEL: EndlessLoop( diff --git a/clang/test/CodeGenCoroutines/coro-gro2.cpp b/clang/test/CodeGenCoroutines/coro-gro2.cpp index b0faa66edd33..56299574fbf2 100644 --- a/clang/test/CodeGenCoroutines/coro-gro2.cpp +++ b/clang/test/CodeGenCoroutines/coro-gro2.cpp @@ -34,13 +34,13 @@ struct coro { }; // Verify that the RVO is applied. -// CHECK-LABEL: define{{.*}} void @_Z1fi(ptr noalias sret(%struct.coro) align 8 %agg.result, i32 noundef %0) +// CHECK-LABEL: define{{.*}} void @_Z1fi(ptr dead_on_unwind noalias writable sret(%struct.coro) align 8 %agg.result, i32 noundef %0) coro f(int) { // CHECK: %call = call noalias noundef nonnull ptr @_Znwm( // CHECK-NEXT: br label %[[CoroInit:.*]] // CHECK: {{.*}}[[CoroInit]]: -// CHECK: call void @{{.*get_return_objectEv}}(ptr sret(%struct.coro) align 8 %agg.result +// CHECK: call void @{{.*get_return_objectEv}}(ptr dead_on_unwind writable sret(%struct.coro) align 8 %agg.result co_return; } @@ -63,7 +63,7 @@ struct coro_two { }; // Verify that the RVO is applied. -// CHECK-LABEL: define{{.*}} void @_Z1hi(ptr noalias sret(%struct.coro_two) align 8 %agg.result, i32 noundef %0) +// CHECK-LABEL: define{{.*}} void @_Z1hi(ptr dead_on_unwind noalias writable sret(%struct.coro_two) align 8 %agg.result, i32 noundef %0) coro_two h(int) { // CHECK: %call = call noalias noundef ptr @_ZnwmRKSt9nothrow_t @@ -71,11 +71,11 @@ coro_two h(int) { // CHECK-NEXT: br i1 %[[CheckNull]], label %[[InitOnSuccess:.*]], label %[[InitOnFailure:.*]] // CHECK: {{.*}}[[InitOnFailure]]: - // CHECK-NEXT: call void @{{.*get_return_object_on_allocation_failureEv}}(ptr sret(%struct.coro_two) align 8 %agg.result + // CHECK-NEXT: call void @{{.*get_return_object_on_allocation_failureEv}}(ptr dead_on_unwind writable sret(%struct.coro_two) align 8 %agg.result // CHECK-NEXT: br label %[[RetLabel:.*]] // CHECK: {{.*}}[[InitOnSuccess]]: - // CHECK: call void @{{.*get_return_objectEv}}(ptr sret(%struct.coro_two) align 8 %agg.result + // CHECK: call void @{{.*get_return_objectEv}}(ptr dead_on_unwind writable sret(%struct.coro_two) align 8 %agg.result // CHECK: [[RetLabel]]: // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenHLSL/sret_output.hlsl b/clang/test/CodeGenHLSL/sret_output.hlsl index 6b15e017a024..33f88c639525 100644 --- a/clang/test/CodeGenHLSL/sret_output.hlsl +++ b/clang/test/CodeGenHLSL/sret_output.hlsl @@ -10,7 +10,7 @@ struct S { // Make sure sret parameter is generated. -// CHECK:define internal void @"?ps_main@@YA?AUS@@XZ"(ptr noalias sret(%struct.S) align 4 %agg.result) +// CHECK:define internal void @"?ps_main@@YA?AUS@@XZ"(ptr dead_on_unwind noalias writable sret(%struct.S) align 4 %agg.result) // FIXME: change it to real value instead of poison value once semantic is add to a. // Make sure the function with sret is called. // CHECK:call void @"?ps_main@@YA?AUS@@XZ"(ptr poison) diff --git a/clang/test/CodeGenObjC/arc.m b/clang/test/CodeGenObjC/arc.m index 74356d8895d1..aeead58f8131 100644 --- a/clang/test/CodeGenObjC/arc.m +++ b/clang/test/CodeGenObjC/arc.m @@ -1358,11 +1358,11 @@ struct AggDtor getAggDtor(void); // CHECK-LABEL: define{{.*}} void @test71 void test71(void) { // CHECK: call void @llvm.lifetime.start.p0({{[^,]+}}, ptr %[[T:.*]]) - // CHECK: call void @getAggDtor(ptr sret(%struct.AggDtor) align 8 %[[T]]) + // CHECK: call void @getAggDtor(ptr dead_on_unwind writable sret(%struct.AggDtor) align 8 %[[T]]) // CHECK: call void @__destructor_8_s40(ptr %[[T]]) // CHECK: call void @llvm.lifetime.end.p0({{[^,]+}}, ptr %[[T]]) // CHECK: call void @llvm.lifetime.start.p0({{[^,]+}}, ptr %[[T2:.*]]) - // CHECK: call void @getAggDtor(ptr sret(%struct.AggDtor) align 8 %[[T2]]) + // CHECK: call void @getAggDtor(ptr dead_on_unwind writable sret(%struct.AggDtor) align 8 %[[T2]]) // CHECK: call void @__destructor_8_s40(ptr %[[T2]]) // CHECK: call void @llvm.lifetime.end.p0({{[^,]+}}, ptr %[[T2]]) getAggDtor(); diff --git a/clang/test/CodeGenObjC/direct-method.m b/clang/test/CodeGenObjC/direct-method.m index 8a3c2f575d2d..028a0888d594 100644 --- a/clang/test/CodeGenObjC/direct-method.m +++ b/clang/test/CodeGenObjC/direct-method.m @@ -111,7 +111,7 @@ __attribute__((objc_root_class)) // CHECK-LABEL: define hidden void @"\01-[Root getAggregate]"( - (struct my_aggregate_struct)getAggregate __attribute__((objc_direct)) { - // CHECK: ptr noalias sret(%struct.my_aggregate_struct) align 4 [[RETVAL:%[^,]*]], + // CHECK: ptr dead_on_unwind noalias writable sret(%struct.my_aggregate_struct) align 4 [[RETVAL:%[^,]*]], // loading parameters // CHECK-LABEL: entry: diff --git a/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m b/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m index 0159e111d9ad..d2a954ae26a0 100644 --- a/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m +++ b/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m @@ -39,8 +39,8 @@ void testStrongException(void) { // CHECK: define{{.*}} void @testWeakException() // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_WEAK]], align 8 // CHECK: %[[AGG_TMP1:.*]] = alloca %[[STRUCT_WEAK]], align 8 -// CHECK: call void @genWeak(ptr sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_TMP]]) -// CHECK: invoke void @genWeak(ptr sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_TMP1]]) +// CHECK: call void @genWeak(ptr dead_on_unwind writable sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_TMP]]) +// CHECK: invoke void @genWeak(ptr dead_on_unwind writable sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_TMP1]]) // CHECK: call void @calleeWeak(ptr noundef %[[AGG_TMP]], ptr noundef %[[AGG_TMP1]]) // CHECK: ret void diff --git a/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m b/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m index effba8c95844..cc697b0e1537 100644 --- a/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m +++ b/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m @@ -37,7 +37,7 @@ Trivial testTrivial(void) { void func1(TrivialBig *); -// CHECK: define{{.*}} void @testTrivialBig(ptr noalias sret(%[[STRUCT_TRIVIALBIG]]) align 4 %[[AGG_RESULT:.*]]) +// CHECK: define{{.*}} void @testTrivialBig(ptr dead_on_unwind noalias writable sret(%[[STRUCT_TRIVIALBIG]]) align 4 %[[AGG_RESULT:.*]]) // CHECK: call void @func1(ptr noundef %[[AGG_RESULT]]) // CHECK-NEXT: ret void @@ -67,7 +67,7 @@ Strong testStrong(void) { return a; } -// CHECK: define{{.*}} void @testWeak(ptr noalias sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_RESULT:.*]]) +// CHECK: define{{.*}} void @testWeak(ptr dead_on_unwind noalias writable sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_RESULT:.*]]) // CHECK: %[[NRVO:.*]] = alloca i1, align 1 // CHECK: call void @__default_constructor_8_w0(ptr %[[AGG_RESULT]]) // CHECK: store i1 true, ptr %[[NRVO]], align 1 @@ -101,7 +101,7 @@ Weak testWeak2(int c) { return b; } -// CHECK: define internal void @"\01-[C1 foo1]"(ptr noalias sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_RESULT:.*]], ptr noundef %{{.*}}, ptr noundef %{{.*}}) +// CHECK: define internal void @"\01-[C1 foo1]"(ptr dead_on_unwind noalias writable sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_RESULT:.*]], ptr noundef %{{.*}}, ptr noundef %{{.*}}) // CHECK: %[[NRVO:.*]] = alloca i1, align 1 // CHECK: call void @__default_constructor_8_w0(ptr %[[AGG_RESULT]]) // CHECK: store i1 true, ptr %[[NRVO]], align 1 diff --git a/clang/test/CodeGenObjC/stret-1.m b/clang/test/CodeGenObjC/stret-1.m index fb1b4abe70f4..20e26af72c6f 100644 --- a/clang/test/CodeGenObjC/stret-1.m +++ b/clang/test/CodeGenObjC/stret-1.m @@ -13,18 +13,18 @@ int main(int argc, const char **argv) { struct stret s; s = [(id)(argc&~255) method]; - // CHECK: call void @objc_msgSend(ptr sret(%struct.stret) align 4 [[T0:%[^,]+]] + // CHECK: call void @objc_msgSend(ptr dead_on_unwind writable sret(%struct.stret) align 4 [[T0:%[^,]+]] // CHECK: call void @llvm.memset.p0.i64(ptr align 4 [[T0]], i8 0, i64 400, i1 false) s = [Test method]; - // CHECK: call void @objc_msgSend(ptr sret(%struct.stret) align 4 [[T1:%[^,]+]] + // CHECK: call void @objc_msgSend(ptr dead_on_unwind writable sret(%struct.stret) align 4 [[T1:%[^,]+]] // CHECK-NOT: call void @llvm.memset.p0.i64( [(id)(argc&~255) method]; - // CHECK: call void @objc_msgSend(ptr sret(%struct.stret) align 4 [[T1:%[^,]+]] + // CHECK: call void @objc_msgSend(ptr dead_on_unwind writable sret(%struct.stret) align 4 [[T1:%[^,]+]] // CHECK-NOT: call void @llvm.memset.p0.i64( [Test method]; - // CHECK: call void @objc_msgSend(ptr sret(%struct.stret) align 4 [[T1:%[^,]+]] + // CHECK: call void @objc_msgSend(ptr dead_on_unwind writable sret(%struct.stret) align 4 [[T1:%[^,]+]] // CHECK-NOT: call void @llvm.memset.p0.i64( } diff --git a/clang/test/CodeGenObjC/stret_lookup.m b/clang/test/CodeGenObjC/stret_lookup.m index 1a4665d4309d..315a1627da5b 100644 --- a/clang/test/CodeGenObjC/stret_lookup.m +++ b/clang/test/CodeGenObjC/stret_lookup.m @@ -20,8 +20,8 @@ void test0(void) { // HASSTRET-LABEL: define{{.*}} void @test0() // HASSTRET: [[T0:%.*]] = call ptr @objc_msg_lookup_stret(ptr @_OBJC_CLASS_Test0, -// HASSTRET-NEXT: call void [[T0]](ptr sret(%struct.test) {{.*}}, ptr noundef @_OBJC_CLASS_Test0, +// HASSTRET-NEXT: call void [[T0]](ptr dead_on_unwind writable sret(%struct.test) {{.*}}, ptr noundef @_OBJC_CLASS_Test0, // NOSTRET-LABEL: define{{.*}} void @test0() // NOSTRET: [[T0:%.*]] = call ptr @objc_msg_lookup(ptr -// NOSTRET-NEXT: call void [[T0]](ptr sret(%struct.test) {{.*}}, ptr {{.*}}, ptr noundef +// NOSTRET-NEXT: call void [[T0]](ptr dead_on_unwind writable sret(%struct.test) {{.*}}, ptr {{.*}}, ptr noundef diff --git a/clang/test/CodeGenObjC/weak-in-c-struct.m b/clang/test/CodeGenObjC/weak-in-c-struct.m index 3ec08c2b9f18..be80edd1ff11 100644 --- a/clang/test/CodeGenObjC/weak-in-c-struct.m +++ b/clang/test/CodeGenObjC/weak-in-c-struct.m @@ -149,7 +149,7 @@ void test_argument_Weak(Weak *a) { calleeWeak(*a); } -// COMMON: define{{.*}} void @test_return_Weak(ptr noalias sret(%[[STRUCT_WEAK]]) align {{.*}} %[[AGG_RESULT:.*]], ptr noundef %[[A:.*]]) +// COMMON: define{{.*}} void @test_return_Weak(ptr dead_on_unwind noalias writable sret(%[[STRUCT_WEAK]]) align {{.*}} %[[AGG_RESULT:.*]], ptr noundef %[[A:.*]]) // COMMON: %[[A_ADDR:.*]] = alloca ptr // COMMON: store ptr %[[A]], ptr %[[A_ADDR]] // COMMON: %[[V0:.*]] = load ptr, ptr %[[A_ADDR]] diff --git a/clang/test/CodeGenObjC/x86_64-struct-return-gc.m b/clang/test/CodeGenObjC/x86_64-struct-return-gc.m index 6bc2929c7596..bc0b88ff037f 100644 --- a/clang/test/CodeGenObjC/x86_64-struct-return-gc.m +++ b/clang/test/CodeGenObjC/x86_64-struct-return-gc.m @@ -25,7 +25,7 @@ struct Indirect indirect_func(void); void Indirect_test(void) { struct Indirect i; - // CHECK: call void @indirect_func(ptr sret + // CHECK: call void @indirect_func(ptr dead_on_unwind writable sret // CHECK: call ptr @objc_memmove_collectable( i = indirect_func(); } diff --git a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm index ed35eb1a7983..f9f783ff5cac 100644 --- a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm +++ b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm @@ -96,7 +96,7 @@ void testCallStrongWeak(StrongWeak *a) { testParamStrongWeak(*a); } -// CHECK: define{{.*}} void @_Z20testReturnStrongWeakP10StrongWeak(ptr noalias sret(%[[STRUCT_STRONGWEAK:.*]]) align 8 %[[AGG_RESULT:.*]], ptr noundef %[[A:.*]]) +// CHECK: define{{.*}} void @_Z20testReturnStrongWeakP10StrongWeak(ptr dead_on_unwind noalias writable sret(%[[STRUCT_STRONGWEAK:.*]]) align 8 %[[AGG_RESULT:.*]], ptr noundef %[[A:.*]]) // CHECK: %[[A_ADDR:a.addr]] = alloca ptr, align 8 // CHECK: store ptr %[[A]], ptr %[[A_ADDR]], align 8 // CHECK: %[[V0:.*]] = load ptr, ptr %[[A_ADDR]], align 8 diff --git a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl index 054fdc066222..385f8a753cd8 100644 --- a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl +++ b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl @@ -45,7 +45,7 @@ struct LargeStructTwoMember { struct LargeStructOneMember g_s; #endif -// X86-LABEL: define{{.*}} void @foo(ptr noalias sret(%struct.Mat4X4) align 4 %agg.result, ptr noundef byval(%struct.Mat3X3) align 4 %in) +// X86-LABEL: define{{.*}} void @foo(ptr dead_on_unwind noalias writable sret(%struct.Mat4X4) align 4 %agg.result, ptr noundef byval(%struct.Mat3X3) align 4 %in) // AMDGCN-LABEL: define{{.*}} %struct.Mat4X4 @foo([9 x i32] %in.coerce) Mat4X4 __attribute__((noinline)) foo(Mat3X3 in) { Mat4X4 out; @@ -65,8 +65,8 @@ kernel void ker(global Mat3X3 *in, global Mat4X4 *out) { out[0] = foo(in[1]); } -// X86-LABEL: define{{.*}} void @foo_large(ptr noalias sret(%struct.Mat64X64) align 4 %agg.result, ptr noundef byval(%struct.Mat32X32) align 4 %in) -// AMDGCN-LABEL: define{{.*}} void @foo_large(ptr addrspace(5) noalias sret(%struct.Mat64X64) align 4 %agg.result, ptr addrspace(5) noundef byref(%struct.Mat32X32) align 4 %{{.*}} +// X86-LABEL: define{{.*}} void @foo_large(ptr dead_on_unwind noalias writable sret(%struct.Mat64X64) align 4 %agg.result, ptr noundef byval(%struct.Mat32X32) align 4 %in) +// AMDGCN-LABEL: define{{.*}} void @foo_large(ptr addrspace(5) dead_on_unwind noalias writable sret(%struct.Mat64X64) align 4 %agg.result, ptr addrspace(5) noundef byref(%struct.Mat32X32) align 4 %{{.*}} // AMDGCN: %in = alloca %struct.Mat32X32, align 4, addrspace(5) // AMDGCN-NEXT: call void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) align 4 %in, ptr addrspace(5) align 4 %{{.*}}, i64 4096, i1 false) Mat64X64 __attribute__((noinline)) foo_large(Mat32X32 in) { diff --git a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl index 52fad9599de0..fa83a38a01b0 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl @@ -86,7 +86,7 @@ kernel void ker(global Mat3X3 *in, global Mat4X4 *out) { } // AMDGCN-LABEL: define dso_local void @foo_large -// AMDGCN-SAME: (ptr addrspace(5) noalias sret([[STRUCT_MAT64X64:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr addrspace(5) noundef byref([[STRUCT_MAT32X32:%.*]]) align 4 [[TMP0:%.*]]) #[[ATTR0]] { +// AMDGCN-SAME: (ptr addrspace(5) dead_on_unwind noalias writable sret([[STRUCT_MAT64X64:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr addrspace(5) noundef byref([[STRUCT_MAT32X32:%.*]]) align 4 [[TMP0:%.*]]) #[[ATTR0]] { // AMDGCN-NEXT: entry: // AMDGCN-NEXT: [[IN:%.*]] = alloca [[STRUCT_MAT32X32]], align 4, addrspace(5) // AMDGCN-NEXT: call void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) align 4 [[IN]], ptr addrspace(5) align 4 [[TMP0]], i64 4096, i1 false) @@ -111,7 +111,7 @@ Mat64X64 __attribute__((noinline)) foo_large(Mat32X32 in) { // AMDGCN-NEXT: [[TMP1:%.*]] = load ptr addrspace(1), ptr addrspace(5) [[IN_ADDR]], align 8 // AMDGCN-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[STRUCT_MAT32X32]], ptr addrspace(1) [[TMP1]], i64 1 // AMDGCN-NEXT: call void @llvm.memcpy.p5.p1.i64(ptr addrspace(5) align 4 [[BYVAL_TEMP]], ptr addrspace(1) align 4 [[ARRAYIDX1]], i64 4096, i1 false) -// AMDGCN-NEXT: call void @foo_large(ptr addrspace(5) sret([[STRUCT_MAT64X64]]) align 4 [[TMP]], ptr addrspace(5) noundef byref([[STRUCT_MAT32X32]]) align 4 [[BYVAL_TEMP]]) #[[ATTR3]] +// AMDGCN-NEXT: call void @foo_large(ptr addrspace(5) dead_on_unwind writable sret([[STRUCT_MAT64X64]]) align 4 [[TMP]], ptr addrspace(5) noundef byref([[STRUCT_MAT32X32]]) align 4 [[BYVAL_TEMP]]) #[[ATTR3]] // AMDGCN-NEXT: call void @llvm.memcpy.p1.p5.i64(ptr addrspace(1) align 4 [[ARRAYIDX]], ptr addrspace(5) align 4 [[TMP]], i64 16384, i1 false) // AMDGCN-NEXT: ret void // diff --git a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl index 665609e54a83..90e4b65c6f1f 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl @@ -402,14 +402,14 @@ struct_arr16 func_ret_struct_arr16() return s; } -// CHECK: define{{.*}} void @func_ret_struct_arr32(ptr addrspace(5) noalias nocapture writeonly sret(%struct.struct_arr32) align 4 %agg.result) +// CHECK: define{{.*}} void @func_ret_struct_arr32(ptr addrspace(5) dead_on_unwind noalias nocapture writable writeonly sret(%struct.struct_arr32) align 4 %agg.result) struct_arr32 func_ret_struct_arr32() { struct_arr32 s = { 0 }; return s; } -// CHECK: define{{.*}} void @func_ret_struct_arr33(ptr addrspace(5) noalias nocapture writeonly sret(%struct.struct_arr33) align 4 %agg.result) +// CHECK: define{{.*}} void @func_ret_struct_arr33(ptr addrspace(5) dead_on_unwind noalias nocapture writable writeonly sret(%struct.struct_arr33) align 4 %agg.result) struct_arr33 func_ret_struct_arr33() { struct_arr33 s = { 0 }; @@ -438,7 +438,7 @@ different_size_type_pair func_different_size_type_pair_ret() return s; } -// CHECK: define{{.*}} void @func_flexible_array_ret(ptr addrspace(5) noalias nocapture writeonly sret(%struct.flexible_array) align 4 %agg.result) +// CHECK: define{{.*}} void @func_flexible_array_ret(ptr addrspace(5) dead_on_unwind noalias nocapture writable writeonly sret(%struct.flexible_array) align 4 %agg.result) flexible_array func_flexible_array_ret() { flexible_array s = { 0 }; diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp index 1c09743d3c8d..2f1b6c196fd5 100644 --- a/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp @@ -111,7 +111,7 @@ __kernel void test__global() { // Test the address space of 'this' when invoking the operator+ // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast ptr %c1 to ptr addrspace(4) // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast ptr %c2 to ptr addrspace(4) -// COMMON: call spir_func void @_ZNU3AS41CplERU3AS4KS_(ptr sret(%class.C) align 4 %c3, ptr addrspace(4) {{[^,]*}} [[C1GEN]], ptr addrspace(4) noundef align 4 dereferenceable(4) [[C2GEN]]) +// COMMON: call spir_func void @_ZNU3AS41CplERU3AS4KS_(ptr dead_on_unwind writable sret(%class.C) align 4 %c3, ptr addrspace(4) {{[^,]*}} [[C1GEN]], ptr addrspace(4) noundef align 4 dereferenceable(4) [[C2GEN]]) // Test the address space of 'this' when invoking the move constructor // COMMON: [[C4GEN:%[.a-z0-9]+]] = addrspacecast ptr %c4 to ptr addrspace(4) @@ -127,7 +127,7 @@ __kernel void test__global() { // Tests address space of inline members //COMMON: @_ZNU3AS41C3getEv(ptr addrspace(4) {{[^,]*}} %this) -//COMMON: @_ZNU3AS41CplERU3AS4KS_(ptr noalias sret(%class.C) align 4 %agg.result, ptr addrspace(4) {{[^,]*}} %this +//COMMON: @_ZNU3AS41CplERU3AS4KS_(ptr dead_on_unwind noalias writable sret(%class.C) align 4 %agg.result, ptr addrspace(4) {{[^,]*}} %this #define TEST(AS) \ __kernel void test##AS() { \ AS C c; \ diff --git a/clang/test/Modules/templates.mm b/clang/test/Modules/templates.mm index 0e66c9843cc0..d7b7d5af030a 100644 --- a/clang/test/Modules/templates.mm +++ b/clang/test/Modules/templates.mm @@ -125,7 +125,7 @@ void testWithAttributes() { // Check that returnNonTrivial doesn't return Class0 directly in registers. -// CHECK: declare void @_Z16returnNonTrivialv(ptr sret(%struct.Class0) align 8) +// CHECK: declare void @_Z16returnNonTrivialv(ptr dead_on_unwind writable sret(%struct.Class0) align 8) @import template_nontrivial0; @import template_nontrivial1; diff --git a/clang/test/OpenMP/irbuilder_for_iterator.cpp b/clang/test/OpenMP/irbuilder_for_iterator.cpp index 91bbb6fc18dd..b88416b36c4f 100644 --- a/clang/test/OpenMP/irbuilder_for_iterator.cpp +++ b/clang/test/OpenMP/irbuilder_for_iterator.cpp @@ -159,7 +159,7 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { // CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[LOGICAL_ADDR]], align 8 // CHECK-NEXT: [[MUL:%.*]] = mul i64 1, [[TMP2]] // CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[MUL]] to i32 -// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(ptr sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP1]], i32 noundef [[CONV]]) +// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(ptr dead_on_unwind writable sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP1]], i32 noundef [[CONV]]) // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8 // CHECK-NEXT: [[CALL:%.*]] = call noundef nonnull align 1 dereferenceable(1) ptr @_ZN10MyIteratoraSERKS_(ptr noundef nonnull align 1 dereferenceable(1) [[TMP3]], ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK-NEXT: ret void diff --git a/clang/test/OpenMP/irbuilder_for_rangefor.cpp b/clang/test/OpenMP/irbuilder_for_rangefor.cpp index 3b952d43eb25..6bf91bfda138 100644 --- a/clang/test/OpenMP/irbuilder_for_rangefor.cpp +++ b/clang/test/OpenMP/irbuilder_for_rangefor.cpp @@ -57,9 +57,9 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { // CHECK-NEXT: call void @_ZN7MyRangeC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]], i32 noundef 42) // CHECK-NEXT: store ptr [[REF_TMP]], ptr [[__RANGE2]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 -// CHECK-NEXT: call void @_ZN7MyRange5beginEv(ptr sret([[STRUCT_MYITERATOR]]) align 1 [[__BEGIN2]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP0]]) +// CHECK-NEXT: call void @_ZN7MyRange5beginEv(ptr dead_on_unwind writable sret([[STRUCT_MYITERATOR]]) align 1 [[__BEGIN2]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 -// CHECK-NEXT: call void @_ZN7MyRange3endEv(ptr sret([[STRUCT_MYITERATOR]]) align 1 [[__END2]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP1]]) +// CHECK-NEXT: call void @_ZN7MyRange3endEv(ptr dead_on_unwind writable sret([[STRUCT_MYITERATOR]]) align 1 [[__END2]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP1]]) // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK10MyIteratordeEv(ptr noundef nonnull align 1 dereferenceable(1) [[__BEGIN2]]) // CHECK-NEXT: store i32 [[CALL]], ptr [[I]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 @@ -177,7 +177,7 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { // CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[LOGICAL_ADDR]], align 8 // CHECK-NEXT: [[MUL:%.*]] = mul i64 1, [[TMP2]] // CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[MUL]] to i32 -// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(ptr sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP1]], i32 noundef [[CONV]]) +// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(ptr dead_on_unwind writable sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], ptr noundef nonnull align 1 dereferenceable(1) [[TMP1]], i32 noundef [[CONV]]) // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK10MyIteratordeEv(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8 // CHECK-NEXT: store i32 [[CALL]], ptr [[TMP3]], align 4 diff --git a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp index 7afaf035988f..41c086c7e1d0 100644 --- a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp @@ -339,7 +339,7 @@ int main(int argc, char **argv) { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 @@ -351,7 +351,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZplRK1SS1_ -// CHECK1-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp index 5d6404cd3e54..f25fe346c835 100644 --- a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp @@ -339,7 +339,7 @@ int main(int argc, char **argv) { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 @@ -351,7 +351,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZplRK1SS1_ -// CHECK1-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/target_in_reduction_codegen.cpp b/clang/test/OpenMP/target_in_reduction_codegen.cpp index 2eb605846124..c6b8afba52ee 100644 --- a/clang/test/OpenMP/target_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_in_reduction_codegen.cpp @@ -333,7 +333,7 @@ int main(int argc, char **argv) { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #3 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 @@ -345,7 +345,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZplRK1SS1_ -// CHECK1-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/task_in_reduction_codegen.cpp b/clang/test/OpenMP/task_in_reduction_codegen.cpp index 82d203894364..348bd7bea3b4 100644 --- a/clang/test/OpenMP/task_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/task_in_reduction_codegen.cpp @@ -361,7 +361,7 @@ int main(int argc, char **argv) { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 @@ -373,7 +373,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZplRK1SS1_ -// CHECK1-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp index e48035a71eea..abf9164b789d 100644 --- a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp @@ -339,7 +339,7 @@ int main(int argc, char **argv) { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 @@ -351,7 +351,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZplRK1SS1_ -// CHECK1-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp index e4d24fa48244..f279596401a8 100644 --- a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp @@ -339,7 +339,7 @@ int main(int argc, char **argv) { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 @@ -351,7 +351,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZplRK1SS1_ -// CHECK1-SAME: (ptr noalias sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr dead_on_unwind noalias writable sret([[STRUCT_S:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr nonnull align 4 dereferenceable(4) [[A:%.*]], ptr nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RESULT_PTR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -- GitLab From d7642b2200bdd7dc12f5fe1a840e1fd43b1bbd73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Thu, 11 Jan 2024 09:50:33 +0100 Subject: [PATCH 428/652] [GlobalIsel] Combine select to integer minmax (second attempt). (#77520) Instcombine canonicalizes selects to floating point and integer minmax. This and the dag combiner canonicalize to floating point minmax. None of them canonicalizes to integer minmax. On Neoverse V2 basic integer arithmetic and integer minmax have the same costs. --- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 3 + .../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 84 ++++++ .../AArch64/GlobalISel/arm64-atomic.ll | 32 +- .../AArch64/GlobalISel/arm64-pcsections.ll | 8 +- .../AArch64/GlobalISel/combine-select.mir | 281 ++++++++++++++++++ 5 files changed, 388 insertions(+), 20 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index dcc1a4580b14..a6e9406bed06 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -910,6 +910,9 @@ private: bool tryFoldSelectOfConstants(GSelect *Select, BuildFnTy &MatchInfo); + /// Try to fold (icmp X, Y) ? X : Y -> integer minmax. + bool tryFoldSelectToIntMinMax(GSelect *Select, BuildFnTy &MatchInfo); + bool isOneOrOneSplat(Register Src, bool AllowUndefs); bool isZeroOrZeroSplat(Register Src, bool AllowUndefs); bool isConstantSplatVector(Register Src, int64_t SplatValue, diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 8b15bdb0aca3..fc2793bd7a13 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -6548,6 +6548,87 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select, return false; } +bool CombinerHelper::tryFoldSelectToIntMinMax(GSelect *Select, + BuildFnTy &MatchInfo) { + Register DstReg = Select->getReg(0); + Register Cond = Select->getCondReg(); + Register True = Select->getTrueReg(); + Register False = Select->getFalseReg(); + LLT DstTy = MRI.getType(DstReg); + + // We need an G_ICMP on the condition register. + GICmp *Cmp = getOpcodeDef(Cond, MRI); + if (!Cmp) + return false; + + // We want to fold the icmp and replace the select. + if (!MRI.hasOneNonDBGUse(Cmp->getReg(0))) + return false; + + CmpInst::Predicate Pred = Cmp->getCond(); + // We need a larger or smaller predicate for + // canonicalization. + if (CmpInst::isEquality(Pred)) + return false; + + Register CmpLHS = Cmp->getLHSReg(); + Register CmpRHS = Cmp->getRHSReg(); + + // We can swap CmpLHS and CmpRHS for higher hitrate. + if (True == CmpRHS && False == CmpLHS) { + std::swap(CmpLHS, CmpRHS); + Pred = CmpInst::getSwappedPredicate(Pred); + } + + // (icmp X, Y) ? X : Y -> integer minmax. + // see matchSelectPattern in ValueTracking. + // Legality between G_SELECT and integer minmax can differ. + if (True == CmpLHS && False == CmpRHS) { + switch (Pred) { + case ICmpInst::ICMP_UGT: + case ICmpInst::ICMP_UGE: { + if (!isLegalOrBeforeLegalizer({TargetOpcode::G_UMAX, DstTy})) + return false; + MatchInfo = [=](MachineIRBuilder &B) { + B.buildUMax(DstReg, True, False); + }; + return true; + } + case ICmpInst::ICMP_SGT: + case ICmpInst::ICMP_SGE: { + if (!isLegalOrBeforeLegalizer({TargetOpcode::G_SMAX, DstTy})) + return false; + MatchInfo = [=](MachineIRBuilder &B) { + B.buildSMax(DstReg, True, False); + }; + return true; + } + case ICmpInst::ICMP_ULT: + case ICmpInst::ICMP_ULE: { + if (!isLegalOrBeforeLegalizer({TargetOpcode::G_UMIN, DstTy})) + return false; + MatchInfo = [=](MachineIRBuilder &B) { + B.buildUMin(DstReg, True, False); + }; + return true; + } + case ICmpInst::ICMP_SLT: + case ICmpInst::ICMP_SLE: { + if (!isLegalOrBeforeLegalizer({TargetOpcode::G_SMIN, DstTy})) + return false; + MatchInfo = [=](MachineIRBuilder &B) { + B.buildSMin(DstReg, True, False); + }; + return true; + } + default: + return false; + } + } + + return false; +} + bool CombinerHelper::matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) { GSelect *Select = cast(&MI); @@ -6557,5 +6638,8 @@ bool CombinerHelper::matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) { if (tryFoldBoolSelectToLogic(Select, MatchInfo)) return true; + if (tryFoldSelectToIntMinMax(Select, MatchInfo)) + return true; + return false; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll index 739332414c19..0e9c126e97a3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll @@ -2421,7 +2421,7 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) { ; CHECK-NOLSE-O1-NEXT: ldaxrb w8, [x0] ; CHECK-NOLSE-O1-NEXT: sxtb w9, w8 ; CHECK-NOLSE-O1-NEXT: cmp w9, w1, sxtb -; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, le +; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lt ; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB33_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -2435,7 +2435,7 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ldaxrb w8, [x0] ; CHECK-OUTLINE-O1-NEXT: sxtb w9, w8 ; CHECK-OUTLINE-O1-NEXT: cmp w9, w1, sxtb -; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, le +; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lt ; CHECK-OUTLINE-O1-NEXT: stxrb w10, w9, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB33_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -2662,7 +2662,7 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) { ; CHECK-NOLSE-O1-NEXT: ldaxrb w8, [x0] ; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xff ; CHECK-NOLSE-O1-NEXT: cmp w10, w9 -; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, ls +; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, lo ; CHECK-NOLSE-O1-NEXT: stlxrb w11, w10, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB35_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -2677,7 +2677,7 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ldaxrb w8, [x0] ; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xff ; CHECK-OUTLINE-O1-NEXT: cmp w10, w9 -; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, ls +; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, lo ; CHECK-OUTLINE-O1-NEXT: stlxrb w11, w10, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB35_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -3477,7 +3477,7 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) { ; CHECK-NOLSE-O1-NEXT: ldaxrh w8, [x0] ; CHECK-NOLSE-O1-NEXT: sxth w9, w8 ; CHECK-NOLSE-O1-NEXT: cmp w9, w1, sxth -; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, le +; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lt ; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB43_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -3491,7 +3491,7 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ldaxrh w8, [x0] ; CHECK-OUTLINE-O1-NEXT: sxth w9, w8 ; CHECK-OUTLINE-O1-NEXT: cmp w9, w1, sxth -; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, le +; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lt ; CHECK-OUTLINE-O1-NEXT: stxrh w10, w9, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB43_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -3718,7 +3718,7 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) { ; CHECK-NOLSE-O1-NEXT: ldaxrh w8, [x0] ; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xffff ; CHECK-NOLSE-O1-NEXT: cmp w10, w9 -; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, ls +; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, lo ; CHECK-NOLSE-O1-NEXT: stlxrh w11, w10, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB45_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -3733,7 +3733,7 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ldaxrh w8, [x0] ; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xffff ; CHECK-OUTLINE-O1-NEXT: cmp w10, w9 -; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, ls +; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, lo ; CHECK-OUTLINE-O1-NEXT: stlxrh w11, w10, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB45_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -4526,7 +4526,7 @@ define i32 @atomicrmw_min_i32(ptr %ptr, i32 %rhs) { ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0] ; CHECK-NOLSE-O1-NEXT: cmp w8, w1 -; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, le +; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lt ; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB53_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -4539,7 +4539,7 @@ define i32 @atomicrmw_min_i32(ptr %ptr, i32 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-OUTLINE-O1-NEXT: ldaxr w8, [x0] ; CHECK-OUTLINE-O1-NEXT: cmp w8, w1 -; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, le +; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lt ; CHECK-OUTLINE-O1-NEXT: stxr w10, w9, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB53_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -4754,7 +4754,7 @@ define i32 @atomicrmw_umin_i32(ptr %ptr, i32 %rhs) { ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0] ; CHECK-NOLSE-O1-NEXT: cmp w8, w1 -; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, ls +; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lo ; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB55_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -4767,7 +4767,7 @@ define i32 @atomicrmw_umin_i32(ptr %ptr, i32 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-OUTLINE-O1-NEXT: ldaxr w8, [x0] ; CHECK-OUTLINE-O1-NEXT: cmp w8, w1 -; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, ls +; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lo ; CHECK-OUTLINE-O1-NEXT: stlxr w10, w9, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB55_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -5547,7 +5547,7 @@ define i64 @atomicrmw_min_i64(ptr %ptr, i64 %rhs) { ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0] ; CHECK-NOLSE-O1-NEXT: cmp x8, x1 -; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, le +; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, lt ; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB63_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -5560,7 +5560,7 @@ define i64 @atomicrmw_min_i64(ptr %ptr, i64 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-OUTLINE-O1-NEXT: ldaxr x8, [x0] ; CHECK-OUTLINE-O1-NEXT: cmp x8, x1 -; CHECK-OUTLINE-O1-NEXT: csel x9, x8, x1, le +; CHECK-OUTLINE-O1-NEXT: csel x9, x8, x1, lt ; CHECK-OUTLINE-O1-NEXT: stxr w10, x9, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB63_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -5775,7 +5775,7 @@ define i64 @atomicrmw_umin_i64(ptr %ptr, i64 %rhs) { ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0] ; CHECK-NOLSE-O1-NEXT: cmp x8, x1 -; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, ls +; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, lo ; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0] ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB65_1 ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end @@ -5788,7 +5788,7 @@ define i64 @atomicrmw_umin_i64(ptr %ptr, i64 %rhs) { ; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-OUTLINE-O1-NEXT: ldaxr x8, [x0] ; CHECK-OUTLINE-O1-NEXT: cmp x8, x1 -; CHECK-OUTLINE-O1-NEXT: csel x9, x8, x1, ls +; CHECK-OUTLINE-O1-NEXT: csel x9, x8, x1, lo ; CHECK-OUTLINE-O1-NEXT: stlxr w10, x9, [x0] ; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB65_1 ; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll index 4c07081404c8..5a7bd6ee20f9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll @@ -888,7 +888,7 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) { ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr) ; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 7, pcsections !0 ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 32, implicit-def $nzcv, pcsections !0 - ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 13, implicit killed $nzcv, implicit-def $x9, pcsections !0 + ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, implicit-def $x9, pcsections !0 ; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w9, renamable $x0, implicit killed $x9, pcsections !0 :: (volatile store (s8) into %ir.ptr) ; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0 ; CHECK-NEXT: {{ $}} @@ -943,7 +943,7 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) { ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr) ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 7 ; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0 - ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 9, implicit killed $nzcv, implicit-def $x10, pcsections !0 + ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0 ; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr) ; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0 ; CHECK-NEXT: {{ $}} @@ -1148,7 +1148,7 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) { ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr) ; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 15, pcsections !0 ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 40, implicit-def $nzcv, pcsections !0 - ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 13, implicit killed $nzcv, implicit-def $x9, pcsections !0 + ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, implicit-def $x9, pcsections !0 ; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w9, renamable $x0, implicit killed $x9, pcsections !0 :: (volatile store (s16) into %ir.ptr) ; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0 ; CHECK-NEXT: {{ $}} @@ -1203,7 +1203,7 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) { ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr) ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 15 ; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0 - ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 9, implicit killed $nzcv, implicit-def $x10, pcsections !0 + ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0 ; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr) ; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0 ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir index be2de620fa45..260cb72b0426 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir @@ -544,3 +544,284 @@ body: | %ext:_(s32) = G_ANYEXT %sel $w0 = COPY %ext(s32) ... +--- +# select test(failed,registers) select icmp_ugt t,f_t_f --> umax(t,f) +name: select_failed_icmp_ugt_t_f_t_f_umax_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_failed_icmp_ugt_t_f_t_f_umax_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 + ; CHECK-NEXT: %t:_(s8) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f:_(s8) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %y:_(s8) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: %z:_(s8) = G_TRUNC [[COPY3]](s64) + ; CHECK-NEXT: %c:_(s8) = G_ICMP intpred(ugt), %t(s8), %y + ; CHECK-NEXT: %sel:_(s8) = exact G_SELECT %c(s8), %f, %z + ; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s8) + ; CHECK-NEXT: $w0 = COPY %ext(s32) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %3:_(s64) = COPY $x3 + %4:_(s64) = COPY $x4 + %t:_(s8) = G_TRUNC %0 + %f:_(s8) = G_TRUNC %1 + %y:_(s8) = G_TRUNC %2 + %z:_(s8) = G_TRUNC %3 + %c:_(s8) = G_ICMP intpred(ugt), %t(s8), %y(s8) + %sel:_(s8) = exact G_SELECT %c, %f, %z + %ext:_(s32) = G_ANYEXT %sel + $w0 = COPY %ext(s32) +... +--- +# test select icmp_ugt t,f_t_f --> umax(t,f) +name: select_icmp_ugt_t_f_t_f_umax_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_ugt_t_f_t_f_umax_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_UMAX %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(ugt), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# test select icmp_uge t,f_t_f --> umax(t,f) +name: select_icmp_uge_t_f_t_f_umax_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_uge_t_f_t_f_umax_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_UMAX %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(uge), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# test select icmp_sgt t,f_t_f --> smax(t,f) +name: select_icmp_sgt_t_f_t_f_smax_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_sgt_t_f_t_f_smax_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_SMAX %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(sgt), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# test select icmp_sge t,f_t_f --> smax(t,f) +name: select_icmp_sge_t_f_t_f_smax_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_sge_t_f_t_f_smax_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_SMAX %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(sge), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# test select icmp_ult t,f_t_f --> umin(t,f) +name: select_icmp_ult_t_f_t_f_umin_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_ult_t_f_t_f_umin_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_UMIN %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(ult), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# test select icmp_ule t,f_t_f --> umin(t,f) +name: select_icmp_ule_t_f_t_f_umin_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_ule_t_f_t_f_umin_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_UMIN %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(ule), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# test select icmp_slt t,f_t_f --> smin(t,f) +name: select_icmp_slt_t_f_t_f_smin_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_slt_t_f_t_f_smin_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_SMIN %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(slt), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# test select icmp_sle t,f_t_f --> smin(t,f) +name: select_icmp_sle_t_f_t_f_smin_t_f +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_icmp_sle_t_f_t_f_smin_t_f + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %sel:_(<4 x s32>) = G_SMIN %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(sle), %t(<4 x s32>), %f(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... +--- +# multi use test select icmp_sle t,f_t_f --> smin(t,f) failed +name: multi_use_select_icmp_sle_t_f_t_f_smin_t_f_failed +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: multi_use_select_icmp_sle_t_f_t_f_smin_t_f_failed + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %t1:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: %f1:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: %t:_(<4 x s32>) = G_BUILD_VECTOR %t1(s32), %t1(s32), %t1(s32), %t1(s32) + ; CHECK-NEXT: %f:_(<4 x s32>) = G_BUILD_VECTOR %f1(s32), %f1(s32), %f1(s32), %f1(s32) + ; CHECK-NEXT: %c:_(<4 x s32>) = G_ICMP intpred(sle), %t(<4 x s32>), %f + ; CHECK-NEXT: $q1 = COPY %c(<4 x s32>) + ; CHECK-NEXT: %sel:_(<4 x s32>) = exact G_SELECT %c(<4 x s32>), %t, %f + ; CHECK-NEXT: $q0 = COPY %sel(<4 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %t1:_(s32) = G_TRUNC %0 + %f1:_(s32) = G_TRUNC %1 + %t:_(<4 x s32>) = G_BUILD_VECTOR %t1, %t1, %t1, %t1 + %f:_(<4 x s32>) = G_BUILD_VECTOR %f1, %f1, %f1, %f1 + %c:_(<4 x s32>) = G_ICMP intpred(sle), %t(<4 x s32>), %f(<4 x s32>) + $q1 = COPY %c(<4 x s32>) + %sel:_(<4 x s32>) = exact G_SELECT %c, %t, %f + $q0 = COPY %sel(<4 x s32>) +... -- GitLab From 9ef2ac3ad1bd5aa9e589f63047e8abeac11ad1b2 Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Thu, 11 Jan 2024 16:59:18 +0800 Subject: [PATCH 429/652] [clangd] Handle lambda scopes inside Node::getDeclContext() (#76329) We used to consider the `DeclContext` for selection nodes inside a lambda as the enclosing scope of the lambda expression, rather than the lambda itself. For example, ```cpp void foo(); auto lambda = [] { return ^foo(); }; ``` where `N` is the selection node for the expression `foo()`, `N.getDeclContext()` returns the `TranslationUnitDecl` previously, which IMO is wrong, since the method `operator()` of the lambda is closer. Incidentally, this fixes a glitch in add-using-declaration tweaks. (Thanks @HighCommander4 for the test case.) --- clang-tools-extra/clangd/Selection.cpp | 3 +++ .../clangd/unittests/SelectionTests.cpp | 13 +++++++++++ .../clangd/unittests/tweaks/AddUsingTests.cpp | 23 +++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/clang-tools-extra/clangd/Selection.cpp b/clang-tools-extra/clangd/Selection.cpp index 8c6d5750ecef..277cb8769a1b 100644 --- a/clang-tools-extra/clangd/Selection.cpp +++ b/clang-tools-extra/clangd/Selection.cpp @@ -1113,6 +1113,9 @@ const DeclContext &SelectionTree::Node::getDeclContext() const { return *DC; return *Current->getLexicalDeclContext(); } + if (const auto *LE = CurrentNode->ASTNode.get()) + if (CurrentNode != this) + return *LE->getCallOperator(); } llvm_unreachable("A tree must always be rooted at TranslationUnitDecl."); } diff --git a/clang-tools-extra/clangd/unittests/SelectionTests.cpp b/clang-tools-extra/clangd/unittests/SelectionTests.cpp index 4c019a1524f3..754e8c287c51 100644 --- a/clang-tools-extra/clangd/unittests/SelectionTests.cpp +++ b/clang-tools-extra/clangd/unittests/SelectionTests.cpp @@ -880,6 +880,19 @@ TEST(SelectionTest, DeclContextIsLexical) { } } +TEST(SelectionTest, DeclContextLambda) { + llvm::Annotations Test(R"cpp( + void foo(); + auto lambda = [] { + return $1^foo(); + }; + )cpp"); + auto AST = TestTU::withCode(Test.code()).build(); + auto ST = SelectionTree::createRight(AST.getASTContext(), AST.getTokens(), + Test.point("1"), Test.point("1")); + EXPECT_TRUE(ST.commonAncestor()->getDeclContext().isFunctionOrMethod()); +} + } // namespace } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/unittests/tweaks/AddUsingTests.cpp b/clang-tools-extra/clangd/unittests/tweaks/AddUsingTests.cpp index 1fd2487378d7..c2dd8e1bb8ee 100644 --- a/clang-tools-extra/clangd/unittests/tweaks/AddUsingTests.cpp +++ b/clang-tools-extra/clangd/unittests/tweaks/AddUsingTests.cpp @@ -309,6 +309,29 @@ namespace foo { void fun(); } void foo::fun() { ff(); })cpp"}, + // Inside a lambda. + { + R"cpp( +namespace NS { +void unrelated(); +void foo(); +} + +auto L = [] { + using NS::unrelated; + NS::f^oo(); +};)cpp", + R"cpp( +namespace NS { +void unrelated(); +void foo(); +} + +auto L = [] { + using NS::foo;using NS::unrelated; + foo(); +};)cpp", + }, // If all other using are fully qualified, add :: {R"cpp( #include "test.hpp" -- GitLab From ee431288a6639b3bdc07b819f5d584bfb39793ed Mon Sep 17 00:00:00 2001 From: Dominik Adamski Date: Thu, 11 Jan 2024 10:18:11 +0100 Subject: [PATCH 430/652] [NFC][OpenMP][Flang] Add smoke test for omp target parallel (#77579) Added test which proves that end-to-end compilation of omp target parallel costruct is successful for Flang compiler. --- .../fortran/basic-target-parallel-region.f90 | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 openmp/libomptarget/test/offloading/fortran/basic-target-parallel-region.f90 diff --git a/openmp/libomptarget/test/offloading/fortran/basic-target-parallel-region.f90 b/openmp/libomptarget/test/offloading/fortran/basic-target-parallel-region.f90 new file mode 100644 index 000000000000..54341f7c40ff --- /dev/null +++ b/openmp/libomptarget/test/offloading/fortran/basic-target-parallel-region.f90 @@ -0,0 +1,21 @@ +! Basic offloading test with a target region +! REQUIRES: flang +! UNSUPPORTED: nvptx64-nvidia-cuda-LTO +! UNSUPPORTED: aarch64-unknown-linux-gnu +! UNSUPPORTED: aarch64-unknown-linux-gnu-LTO +! UNSUPPORTED: x86_64-pc-linux-gnu +! UNSUPPORTED: x86_64-pc-linux-gnu-LTO + +! RUN: %libomptarget-compile-fortran-run-and-check-generic +program main + use omp_lib + integer :: x + + !$omp target parallel map(from: x) + x = omp_get_num_threads() + !$omp end target parallel + print *,"parallel = ", (x .ne. 1) + +end program main + +! CHECK: parallel = T -- GitLab From 33e5db6e045d3a82e29a7c6ebffe259dfafefb3d Mon Sep 17 00:00:00 2001 From: Corentin Jabot Date: Thu, 11 Jan 2024 10:19:44 +0100 Subject: [PATCH 431/652] [clang] Improve colors in status tracking web pages. Use a consistent, more pastel color for unknown status in papers and issues tracking pages --- clang/.clang-tidy | 2 +- clang/www/c_dr_status.html | 4 +- clang/www/c_status.html | 2 +- clang/www/cxx_dr_status.html | 3239 ++++++++++---------- clang/www/make_cxx_dr_status | 3 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 2 +- 6 files changed, 1627 insertions(+), 1625 deletions(-) diff --git a/clang/.clang-tidy b/clang/.clang-tidy index ba55beb095f5..7eef110c3cf7 100644 --- a/clang/.clang-tidy +++ b/clang/.clang-tidy @@ -1,5 +1,5 @@ # Note that the readability-identifier-naming check is disabled, there are too # many violations in the codebase and they create too much noise in clang-tidy # results. -Checks: '-readability-identifier-naming' +Checks: '-readability-identifier-naming, -misc-include*' InheritParentConfig: true diff --git a/clang/www/c_dr_status.html b/clang/www/c_dr_status.html index 4fe088e29775..fa2ceb1be58b 100644 --- a/clang/www/c_dr_status.html +++ b/clang/www/c_dr_status.html @@ -12,7 +12,7 @@ .unreleased { background-color: #FFFF99 } .full { background-color: #CCFF99 } .na { background-color: #DDDDDD } - .unknown { background-color: #FF55FF } + .unknown { background-color: #EBCAFE } .open * { color: #AAAAAA } //.open { filter: opacity(0.2) } tr:target { background-color: #FFFFBB } @@ -35,7 +35,7 @@

The implementation status for defect reports against the C Standard are currently under investigation. Any defect report whose status in Clang is -currently unknown will be marked in magenta.

+currently unknown will be marked in purple.

The LLVM bug tracker uses the "c", "c99", "c11", "c17", and "c23" labels to track known bugs with Clang's language diff --git a/clang/www/c_status.html b/clang/www/c_status.html index 47acb1f87b8e..fe56bc791ccb 100644 --- a/clang/www/c_status.html +++ b/clang/www/c_status.html @@ -9,7 +9,7 @@ .none { background-color: #FFCCCC } .partial { background-color: #FFE0B0 } .unreleased { background-color: #FFFF99 } - .unknown { background-color: #FF55FF } + .unknown { background-color: #DDAEF7 } .full { background-color: #CCFF99 } .na { background-color: #DDDDDD } :target { background-color: #FFFFBB; outline: #DDDD55 solid thin; } diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 2bded63d5cd4..4a3ed19161f9 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -8,6 +8,7 @@